1 /* Analyze RTL for GNU compiler. 2 Copyright (C) 1987-2013 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 21 #include "config.h" 22 #include "system.h" 23 #include "coretypes.h" 24 #include "tm.h" 25 #include "diagnostic-core.h" 26 #include "hard-reg-set.h" 27 #include "rtl.h" 28 #include "insn-config.h" 29 #include "recog.h" 30 #include "target.h" 31 #include "output.h" 32 #include "tm_p.h" 33 #include "flags.h" 34 #include "regs.h" 35 #include "function.h" 36 #include "df.h" 37 #include "tree.h" 38 #include "emit-rtl.h" /* FIXME: Can go away once crtl is moved to rtl.h. */ 39 #include "addresses.h" 40 41 /* Forward declarations */ 42 static void set_of_1 (rtx, const_rtx, void *); 43 static bool covers_regno_p (const_rtx, unsigned int); 44 static bool covers_regno_no_parallel_p (const_rtx, unsigned int); 45 static int rtx_referenced_p_1 (rtx *, void *); 46 static int computed_jump_p_1 (const_rtx); 47 static void parms_set (rtx, const_rtx, void *); 48 49 static unsigned HOST_WIDE_INT cached_nonzero_bits (const_rtx, enum machine_mode, 50 const_rtx, enum machine_mode, 51 unsigned HOST_WIDE_INT); 52 static unsigned HOST_WIDE_INT nonzero_bits1 (const_rtx, enum machine_mode, 53 const_rtx, enum machine_mode, 54 unsigned HOST_WIDE_INT); 55 static unsigned int cached_num_sign_bit_copies (const_rtx, enum machine_mode, const_rtx, 56 enum machine_mode, 57 unsigned int); 58 static unsigned int num_sign_bit_copies1 (const_rtx, enum machine_mode, const_rtx, 59 enum machine_mode, unsigned int); 60 61 /* Offset of the first 'e', 'E' or 'V' operand for each rtx code, or 62 -1 if a code has no such operand. */ 63 static int non_rtx_starting_operands[NUM_RTX_CODE]; 64 65 /* Truncation narrows the mode from SOURCE mode to DESTINATION mode. 66 If TARGET_MODE_REP_EXTENDED (DESTINATION, DESTINATION_REP) is 67 SIGN_EXTEND then while narrowing we also have to enforce the 68 representation and sign-extend the value to mode DESTINATION_REP. 69 70 If the value is already sign-extended to DESTINATION_REP mode we 71 can just switch to DESTINATION mode on it. For each pair of 72 integral modes SOURCE and DESTINATION, when truncating from SOURCE 73 to DESTINATION, NUM_SIGN_BIT_COPIES_IN_REP[SOURCE][DESTINATION] 74 contains the number of high-order bits in SOURCE that have to be 75 copies of the sign-bit so that we can do this mode-switch to 76 DESTINATION. */ 77 78 static unsigned int 79 num_sign_bit_copies_in_rep[MAX_MODE_INT + 1][MAX_MODE_INT + 1]; 80 81 /* Return 1 if the value of X is unstable 82 (would be different at a different point in the program). 83 The frame pointer, arg pointer, etc. are considered stable 84 (within one function) and so is anything marked `unchanging'. */ 85 86 int 87 rtx_unstable_p (const_rtx x) 88 { 89 const RTX_CODE code = GET_CODE (x); 90 int i; 91 const char *fmt; 92 93 switch (code) 94 { 95 case MEM: 96 return !MEM_READONLY_P (x) || rtx_unstable_p (XEXP (x, 0)); 97 98 case CONST: 99 CASE_CONST_ANY: 100 case SYMBOL_REF: 101 case LABEL_REF: 102 return 0; 103 104 case REG: 105 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */ 106 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx 107 /* The arg pointer varies if it is not a fixed register. */ 108 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM])) 109 return 0; 110 /* ??? When call-clobbered, the value is stable modulo the restore 111 that must happen after a call. This currently screws up local-alloc 112 into believing that the restore is not needed. */ 113 if (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED && x == pic_offset_table_rtx) 114 return 0; 115 return 1; 116 117 case ASM_OPERANDS: 118 if (MEM_VOLATILE_P (x)) 119 return 1; 120 121 /* Fall through. */ 122 123 default: 124 break; 125 } 126 127 fmt = GET_RTX_FORMAT (code); 128 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 129 if (fmt[i] == 'e') 130 { 131 if (rtx_unstable_p (XEXP (x, i))) 132 return 1; 133 } 134 else if (fmt[i] == 'E') 135 { 136 int j; 137 for (j = 0; j < XVECLEN (x, i); j++) 138 if (rtx_unstable_p (XVECEXP (x, i, j))) 139 return 1; 140 } 141 142 return 0; 143 } 144 145 /* Return 1 if X has a value that can vary even between two 146 executions of the program. 0 means X can be compared reliably 147 against certain constants or near-constants. 148 FOR_ALIAS is nonzero if we are called from alias analysis; if it is 149 zero, we are slightly more conservative. 150 The frame pointer and the arg pointer are considered constant. */ 151 152 bool 153 rtx_varies_p (const_rtx x, bool for_alias) 154 { 155 RTX_CODE code; 156 int i; 157 const char *fmt; 158 159 if (!x) 160 return 0; 161 162 code = GET_CODE (x); 163 switch (code) 164 { 165 case MEM: 166 return !MEM_READONLY_P (x) || rtx_varies_p (XEXP (x, 0), for_alias); 167 168 case CONST: 169 CASE_CONST_ANY: 170 case SYMBOL_REF: 171 case LABEL_REF: 172 return 0; 173 174 case REG: 175 /* Note that we have to test for the actual rtx used for the frame 176 and arg pointers and not just the register number in case we have 177 eliminated the frame and/or arg pointer and are using it 178 for pseudos. */ 179 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx 180 /* The arg pointer varies if it is not a fixed register. */ 181 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM])) 182 return 0; 183 if (x == pic_offset_table_rtx 184 /* ??? When call-clobbered, the value is stable modulo the restore 185 that must happen after a call. This currently screws up 186 local-alloc into believing that the restore is not needed, so we 187 must return 0 only if we are called from alias analysis. */ 188 && (!PIC_OFFSET_TABLE_REG_CALL_CLOBBERED || for_alias)) 189 return 0; 190 return 1; 191 192 case LO_SUM: 193 /* The operand 0 of a LO_SUM is considered constant 194 (in fact it is related specifically to operand 1) 195 during alias analysis. */ 196 return (! for_alias && rtx_varies_p (XEXP (x, 0), for_alias)) 197 || rtx_varies_p (XEXP (x, 1), for_alias); 198 199 case ASM_OPERANDS: 200 if (MEM_VOLATILE_P (x)) 201 return 1; 202 203 /* Fall through. */ 204 205 default: 206 break; 207 } 208 209 fmt = GET_RTX_FORMAT (code); 210 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 211 if (fmt[i] == 'e') 212 { 213 if (rtx_varies_p (XEXP (x, i), for_alias)) 214 return 1; 215 } 216 else if (fmt[i] == 'E') 217 { 218 int j; 219 for (j = 0; j < XVECLEN (x, i); j++) 220 if (rtx_varies_p (XVECEXP (x, i, j), for_alias)) 221 return 1; 222 } 223 224 return 0; 225 } 226 227 /* Return nonzero if the use of X+OFFSET as an address in a MEM with SIZE 228 bytes can cause a trap. MODE is the mode of the MEM (not that of X) and 229 UNALIGNED_MEMS controls whether nonzero is returned for unaligned memory 230 references on strict alignment machines. */ 231 232 static int 233 rtx_addr_can_trap_p_1 (const_rtx x, HOST_WIDE_INT offset, HOST_WIDE_INT size, 234 enum machine_mode mode, bool unaligned_mems) 235 { 236 enum rtx_code code = GET_CODE (x); 237 238 /* The offset must be a multiple of the mode size if we are considering 239 unaligned memory references on strict alignment machines. */ 240 if (STRICT_ALIGNMENT && unaligned_mems && GET_MODE_SIZE (mode) != 0) 241 { 242 HOST_WIDE_INT actual_offset = offset; 243 244 #ifdef SPARC_STACK_BOUNDARY_HACK 245 /* ??? The SPARC port may claim a STACK_BOUNDARY higher than 246 the real alignment of %sp. However, when it does this, the 247 alignment of %sp+STACK_POINTER_OFFSET is STACK_BOUNDARY. */ 248 if (SPARC_STACK_BOUNDARY_HACK 249 && (x == stack_pointer_rtx || x == hard_frame_pointer_rtx)) 250 actual_offset -= STACK_POINTER_OFFSET; 251 #endif 252 253 if (actual_offset % GET_MODE_SIZE (mode) != 0) 254 return 1; 255 } 256 257 switch (code) 258 { 259 case SYMBOL_REF: 260 if (SYMBOL_REF_WEAK (x)) 261 return 1; 262 if (!CONSTANT_POOL_ADDRESS_P (x)) 263 { 264 tree decl; 265 HOST_WIDE_INT decl_size; 266 267 if (offset < 0) 268 return 1; 269 if (size == 0) 270 size = GET_MODE_SIZE (mode); 271 if (size == 0) 272 return offset != 0; 273 274 /* If the size of the access or of the symbol is unknown, 275 assume the worst. */ 276 decl = SYMBOL_REF_DECL (x); 277 278 /* Else check that the access is in bounds. TODO: restructure 279 expr_size/tree_expr_size/int_expr_size and just use the latter. */ 280 if (!decl) 281 decl_size = -1; 282 else if (DECL_P (decl) && DECL_SIZE_UNIT (decl)) 283 decl_size = (host_integerp (DECL_SIZE_UNIT (decl), 0) 284 ? tree_low_cst (DECL_SIZE_UNIT (decl), 0) 285 : -1); 286 else if (TREE_CODE (decl) == STRING_CST) 287 decl_size = TREE_STRING_LENGTH (decl); 288 else if (TYPE_SIZE_UNIT (TREE_TYPE (decl))) 289 decl_size = int_size_in_bytes (TREE_TYPE (decl)); 290 else 291 decl_size = -1; 292 293 return (decl_size <= 0 ? offset != 0 : offset + size > decl_size); 294 } 295 296 return 0; 297 298 case LABEL_REF: 299 return 0; 300 301 case REG: 302 /* Stack references are assumed not to trap, but we need to deal with 303 nonsensical offsets. */ 304 if (x == frame_pointer_rtx) 305 { 306 HOST_WIDE_INT adj_offset = offset - STARTING_FRAME_OFFSET; 307 if (size == 0) 308 size = GET_MODE_SIZE (mode); 309 if (FRAME_GROWS_DOWNWARD) 310 { 311 if (adj_offset < frame_offset || adj_offset + size - 1 >= 0) 312 return 1; 313 } 314 else 315 { 316 if (adj_offset < 0 || adj_offset + size - 1 >= frame_offset) 317 return 1; 318 } 319 return 0; 320 } 321 /* ??? Need to add a similar guard for nonsensical offsets. */ 322 if (x == hard_frame_pointer_rtx 323 || x == stack_pointer_rtx 324 /* The arg pointer varies if it is not a fixed register. */ 325 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM])) 326 return 0; 327 /* All of the virtual frame registers are stack references. */ 328 if (REGNO (x) >= FIRST_VIRTUAL_REGISTER 329 && REGNO (x) <= LAST_VIRTUAL_REGISTER) 330 return 0; 331 return 1; 332 333 case CONST: 334 return rtx_addr_can_trap_p_1 (XEXP (x, 0), offset, size, 335 mode, unaligned_mems); 336 337 case PLUS: 338 /* An address is assumed not to trap if: 339 - it is the pic register plus a constant. */ 340 if (XEXP (x, 0) == pic_offset_table_rtx && CONSTANT_P (XEXP (x, 1))) 341 return 0; 342 343 /* - or it is an address that can't trap plus a constant integer. */ 344 if (CONST_INT_P (XEXP (x, 1)) 345 && !rtx_addr_can_trap_p_1 (XEXP (x, 0), offset + INTVAL (XEXP (x, 1)), 346 size, mode, unaligned_mems)) 347 return 0; 348 349 return 1; 350 351 case LO_SUM: 352 case PRE_MODIFY: 353 return rtx_addr_can_trap_p_1 (XEXP (x, 1), offset, size, 354 mode, unaligned_mems); 355 356 case PRE_DEC: 357 case PRE_INC: 358 case POST_DEC: 359 case POST_INC: 360 case POST_MODIFY: 361 return rtx_addr_can_trap_p_1 (XEXP (x, 0), offset, size, 362 mode, unaligned_mems); 363 364 default: 365 break; 366 } 367 368 /* If it isn't one of the case above, it can cause a trap. */ 369 return 1; 370 } 371 372 /* Return nonzero if the use of X as an address in a MEM can cause a trap. */ 373 374 int 375 rtx_addr_can_trap_p (const_rtx x) 376 { 377 return rtx_addr_can_trap_p_1 (x, 0, 0, VOIDmode, false); 378 } 379 380 /* Return true if X is an address that is known to not be zero. */ 381 382 bool 383 nonzero_address_p (const_rtx x) 384 { 385 const enum rtx_code code = GET_CODE (x); 386 387 switch (code) 388 { 389 case SYMBOL_REF: 390 return !SYMBOL_REF_WEAK (x); 391 392 case LABEL_REF: 393 return true; 394 395 case REG: 396 /* As in rtx_varies_p, we have to use the actual rtx, not reg number. */ 397 if (x == frame_pointer_rtx || x == hard_frame_pointer_rtx 398 || x == stack_pointer_rtx 399 || (x == arg_pointer_rtx && fixed_regs[ARG_POINTER_REGNUM])) 400 return true; 401 /* All of the virtual frame registers are stack references. */ 402 if (REGNO (x) >= FIRST_VIRTUAL_REGISTER 403 && REGNO (x) <= LAST_VIRTUAL_REGISTER) 404 return true; 405 return false; 406 407 case CONST: 408 return nonzero_address_p (XEXP (x, 0)); 409 410 case PLUS: 411 /* Handle PIC references. */ 412 if (XEXP (x, 0) == pic_offset_table_rtx 413 && CONSTANT_P (XEXP (x, 1))) 414 return true; 415 return false; 416 417 case PRE_MODIFY: 418 /* Similar to the above; allow positive offsets. Further, since 419 auto-inc is only allowed in memories, the register must be a 420 pointer. */ 421 if (CONST_INT_P (XEXP (x, 1)) 422 && INTVAL (XEXP (x, 1)) > 0) 423 return true; 424 return nonzero_address_p (XEXP (x, 0)); 425 426 case PRE_INC: 427 /* Similarly. Further, the offset is always positive. */ 428 return true; 429 430 case PRE_DEC: 431 case POST_DEC: 432 case POST_INC: 433 case POST_MODIFY: 434 return nonzero_address_p (XEXP (x, 0)); 435 436 case LO_SUM: 437 return nonzero_address_p (XEXP (x, 1)); 438 439 default: 440 break; 441 } 442 443 /* If it isn't one of the case above, might be zero. */ 444 return false; 445 } 446 447 /* Return 1 if X refers to a memory location whose address 448 cannot be compared reliably with constant addresses, 449 or if X refers to a BLKmode memory object. 450 FOR_ALIAS is nonzero if we are called from alias analysis; if it is 451 zero, we are slightly more conservative. */ 452 453 bool 454 rtx_addr_varies_p (const_rtx x, bool for_alias) 455 { 456 enum rtx_code code; 457 int i; 458 const char *fmt; 459 460 if (x == 0) 461 return 0; 462 463 code = GET_CODE (x); 464 if (code == MEM) 465 return GET_MODE (x) == BLKmode || rtx_varies_p (XEXP (x, 0), for_alias); 466 467 fmt = GET_RTX_FORMAT (code); 468 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 469 if (fmt[i] == 'e') 470 { 471 if (rtx_addr_varies_p (XEXP (x, i), for_alias)) 472 return 1; 473 } 474 else if (fmt[i] == 'E') 475 { 476 int j; 477 for (j = 0; j < XVECLEN (x, i); j++) 478 if (rtx_addr_varies_p (XVECEXP (x, i, j), for_alias)) 479 return 1; 480 } 481 return 0; 482 } 483 484 /* Return the CALL in X if there is one. */ 485 486 rtx 487 get_call_rtx_from (rtx x) 488 { 489 if (INSN_P (x)) 490 x = PATTERN (x); 491 if (GET_CODE (x) == PARALLEL) 492 x = XVECEXP (x, 0, 0); 493 if (GET_CODE (x) == SET) 494 x = SET_SRC (x); 495 if (GET_CODE (x) == CALL && MEM_P (XEXP (x, 0))) 496 return x; 497 return NULL_RTX; 498 } 499 500 /* Return the value of the integer term in X, if one is apparent; 501 otherwise return 0. 502 Only obvious integer terms are detected. 503 This is used in cse.c with the `related_value' field. */ 504 505 HOST_WIDE_INT 506 get_integer_term (const_rtx x) 507 { 508 if (GET_CODE (x) == CONST) 509 x = XEXP (x, 0); 510 511 if (GET_CODE (x) == MINUS 512 && CONST_INT_P (XEXP (x, 1))) 513 return - INTVAL (XEXP (x, 1)); 514 if (GET_CODE (x) == PLUS 515 && CONST_INT_P (XEXP (x, 1))) 516 return INTVAL (XEXP (x, 1)); 517 return 0; 518 } 519 520 /* If X is a constant, return the value sans apparent integer term; 521 otherwise return 0. 522 Only obvious integer terms are detected. */ 523 524 rtx 525 get_related_value (const_rtx x) 526 { 527 if (GET_CODE (x) != CONST) 528 return 0; 529 x = XEXP (x, 0); 530 if (GET_CODE (x) == PLUS 531 && CONST_INT_P (XEXP (x, 1))) 532 return XEXP (x, 0); 533 else if (GET_CODE (x) == MINUS 534 && CONST_INT_P (XEXP (x, 1))) 535 return XEXP (x, 0); 536 return 0; 537 } 538 539 /* Return true if SYMBOL is a SYMBOL_REF and OFFSET + SYMBOL points 540 to somewhere in the same object or object_block as SYMBOL. */ 541 542 bool 543 offset_within_block_p (const_rtx symbol, HOST_WIDE_INT offset) 544 { 545 tree decl; 546 547 if (GET_CODE (symbol) != SYMBOL_REF) 548 return false; 549 550 if (offset == 0) 551 return true; 552 553 if (offset > 0) 554 { 555 if (CONSTANT_POOL_ADDRESS_P (symbol) 556 && offset < (int) GET_MODE_SIZE (get_pool_mode (symbol))) 557 return true; 558 559 decl = SYMBOL_REF_DECL (symbol); 560 if (decl && offset < int_size_in_bytes (TREE_TYPE (decl))) 561 return true; 562 } 563 564 if (SYMBOL_REF_HAS_BLOCK_INFO_P (symbol) 565 && SYMBOL_REF_BLOCK (symbol) 566 && SYMBOL_REF_BLOCK_OFFSET (symbol) >= 0 567 && ((unsigned HOST_WIDE_INT) offset + SYMBOL_REF_BLOCK_OFFSET (symbol) 568 < (unsigned HOST_WIDE_INT) SYMBOL_REF_BLOCK (symbol)->size)) 569 return true; 570 571 return false; 572 } 573 574 /* Split X into a base and a constant offset, storing them in *BASE_OUT 575 and *OFFSET_OUT respectively. */ 576 577 void 578 split_const (rtx x, rtx *base_out, rtx *offset_out) 579 { 580 if (GET_CODE (x) == CONST) 581 { 582 x = XEXP (x, 0); 583 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1))) 584 { 585 *base_out = XEXP (x, 0); 586 *offset_out = XEXP (x, 1); 587 return; 588 } 589 } 590 *base_out = x; 591 *offset_out = const0_rtx; 592 } 593 594 /* Return the number of places FIND appears within X. If COUNT_DEST is 595 zero, we do not count occurrences inside the destination of a SET. */ 596 597 int 598 count_occurrences (const_rtx x, const_rtx find, int count_dest) 599 { 600 int i, j; 601 enum rtx_code code; 602 const char *format_ptr; 603 int count; 604 605 if (x == find) 606 return 1; 607 608 code = GET_CODE (x); 609 610 switch (code) 611 { 612 case REG: 613 CASE_CONST_ANY: 614 case SYMBOL_REF: 615 case CODE_LABEL: 616 case PC: 617 case CC0: 618 return 0; 619 620 case EXPR_LIST: 621 count = count_occurrences (XEXP (x, 0), find, count_dest); 622 if (XEXP (x, 1)) 623 count += count_occurrences (XEXP (x, 1), find, count_dest); 624 return count; 625 626 case MEM: 627 if (MEM_P (find) && rtx_equal_p (x, find)) 628 return 1; 629 break; 630 631 case SET: 632 if (SET_DEST (x) == find && ! count_dest) 633 return count_occurrences (SET_SRC (x), find, count_dest); 634 break; 635 636 default: 637 break; 638 } 639 640 format_ptr = GET_RTX_FORMAT (code); 641 count = 0; 642 643 for (i = 0; i < GET_RTX_LENGTH (code); i++) 644 { 645 switch (*format_ptr++) 646 { 647 case 'e': 648 count += count_occurrences (XEXP (x, i), find, count_dest); 649 break; 650 651 case 'E': 652 for (j = 0; j < XVECLEN (x, i); j++) 653 count += count_occurrences (XVECEXP (x, i, j), find, count_dest); 654 break; 655 } 656 } 657 return count; 658 } 659 660 661 /* Return TRUE if OP is a register or subreg of a register that 662 holds an unsigned quantity. Otherwise, return FALSE. */ 663 664 bool 665 unsigned_reg_p (rtx op) 666 { 667 if (REG_P (op) 668 && REG_EXPR (op) 669 && TYPE_UNSIGNED (TREE_TYPE (REG_EXPR (op)))) 670 return true; 671 672 if (GET_CODE (op) == SUBREG 673 && SUBREG_PROMOTED_UNSIGNED_P (op)) 674 return true; 675 676 return false; 677 } 678 679 680 /* Nonzero if register REG appears somewhere within IN. 681 Also works if REG is not a register; in this case it checks 682 for a subexpression of IN that is Lisp "equal" to REG. */ 683 684 int 685 reg_mentioned_p (const_rtx reg, const_rtx in) 686 { 687 const char *fmt; 688 int i; 689 enum rtx_code code; 690 691 if (in == 0) 692 return 0; 693 694 if (reg == in) 695 return 1; 696 697 if (GET_CODE (in) == LABEL_REF) 698 return reg == XEXP (in, 0); 699 700 code = GET_CODE (in); 701 702 switch (code) 703 { 704 /* Compare registers by number. */ 705 case REG: 706 return REG_P (reg) && REGNO (in) == REGNO (reg); 707 708 /* These codes have no constituent expressions 709 and are unique. */ 710 case SCRATCH: 711 case CC0: 712 case PC: 713 return 0; 714 715 CASE_CONST_ANY: 716 /* These are kept unique for a given value. */ 717 return 0; 718 719 default: 720 break; 721 } 722 723 if (GET_CODE (reg) == code && rtx_equal_p (reg, in)) 724 return 1; 725 726 fmt = GET_RTX_FORMAT (code); 727 728 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 729 { 730 if (fmt[i] == 'E') 731 { 732 int j; 733 for (j = XVECLEN (in, i) - 1; j >= 0; j--) 734 if (reg_mentioned_p (reg, XVECEXP (in, i, j))) 735 return 1; 736 } 737 else if (fmt[i] == 'e' 738 && reg_mentioned_p (reg, XEXP (in, i))) 739 return 1; 740 } 741 return 0; 742 } 743 744 /* Return 1 if in between BEG and END, exclusive of BEG and END, there is 745 no CODE_LABEL insn. */ 746 747 int 748 no_labels_between_p (const_rtx beg, const_rtx end) 749 { 750 rtx p; 751 if (beg == end) 752 return 0; 753 for (p = NEXT_INSN (beg); p != end; p = NEXT_INSN (p)) 754 if (LABEL_P (p)) 755 return 0; 756 return 1; 757 } 758 759 /* Nonzero if register REG is used in an insn between 760 FROM_INSN and TO_INSN (exclusive of those two). */ 761 762 int 763 reg_used_between_p (const_rtx reg, const_rtx from_insn, const_rtx to_insn) 764 { 765 rtx insn; 766 767 if (from_insn == to_insn) 768 return 0; 769 770 for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn)) 771 if (NONDEBUG_INSN_P (insn) 772 && (reg_overlap_mentioned_p (reg, PATTERN (insn)) 773 || (CALL_P (insn) && find_reg_fusage (insn, USE, reg)))) 774 return 1; 775 return 0; 776 } 777 778 /* Nonzero if the old value of X, a register, is referenced in BODY. If X 779 is entirely replaced by a new value and the only use is as a SET_DEST, 780 we do not consider it a reference. */ 781 782 int 783 reg_referenced_p (const_rtx x, const_rtx body) 784 { 785 int i; 786 787 switch (GET_CODE (body)) 788 { 789 case SET: 790 if (reg_overlap_mentioned_p (x, SET_SRC (body))) 791 return 1; 792 793 /* If the destination is anything other than CC0, PC, a REG or a SUBREG 794 of a REG that occupies all of the REG, the insn references X if 795 it is mentioned in the destination. */ 796 if (GET_CODE (SET_DEST (body)) != CC0 797 && GET_CODE (SET_DEST (body)) != PC 798 && !REG_P (SET_DEST (body)) 799 && ! (GET_CODE (SET_DEST (body)) == SUBREG 800 && REG_P (SUBREG_REG (SET_DEST (body))) 801 && (((GET_MODE_SIZE (GET_MODE (SUBREG_REG (SET_DEST (body)))) 802 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD) 803 == ((GET_MODE_SIZE (GET_MODE (SET_DEST (body))) 804 + (UNITS_PER_WORD - 1)) / UNITS_PER_WORD))) 805 && reg_overlap_mentioned_p (x, SET_DEST (body))) 806 return 1; 807 return 0; 808 809 case ASM_OPERANDS: 810 for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--) 811 if (reg_overlap_mentioned_p (x, ASM_OPERANDS_INPUT (body, i))) 812 return 1; 813 return 0; 814 815 case CALL: 816 case USE: 817 case IF_THEN_ELSE: 818 return reg_overlap_mentioned_p (x, body); 819 820 case TRAP_IF: 821 return reg_overlap_mentioned_p (x, TRAP_CONDITION (body)); 822 823 case PREFETCH: 824 return reg_overlap_mentioned_p (x, XEXP (body, 0)); 825 826 case UNSPEC: 827 case UNSPEC_VOLATILE: 828 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 829 if (reg_overlap_mentioned_p (x, XVECEXP (body, 0, i))) 830 return 1; 831 return 0; 832 833 case PARALLEL: 834 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 835 if (reg_referenced_p (x, XVECEXP (body, 0, i))) 836 return 1; 837 return 0; 838 839 case CLOBBER: 840 if (MEM_P (XEXP (body, 0))) 841 if (reg_overlap_mentioned_p (x, XEXP (XEXP (body, 0), 0))) 842 return 1; 843 return 0; 844 845 case COND_EXEC: 846 if (reg_overlap_mentioned_p (x, COND_EXEC_TEST (body))) 847 return 1; 848 return reg_referenced_p (x, COND_EXEC_CODE (body)); 849 850 default: 851 return 0; 852 } 853 } 854 855 /* Nonzero if register REG is set or clobbered in an insn between 856 FROM_INSN and TO_INSN (exclusive of those two). */ 857 858 int 859 reg_set_between_p (const_rtx reg, const_rtx from_insn, const_rtx to_insn) 860 { 861 const_rtx insn; 862 863 if (from_insn == to_insn) 864 return 0; 865 866 for (insn = NEXT_INSN (from_insn); insn != to_insn; insn = NEXT_INSN (insn)) 867 if (INSN_P (insn) && reg_set_p (reg, insn)) 868 return 1; 869 return 0; 870 } 871 872 /* Internals of reg_set_between_p. */ 873 int 874 reg_set_p (const_rtx reg, const_rtx insn) 875 { 876 /* After delay slot handling, call and branch insns might be in a 877 sequence. Check all the elements there. */ 878 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == SEQUENCE) 879 { 880 for (int i = 0; i < XVECLEN (PATTERN (insn), 0); ++i) 881 if (reg_set_p (reg, XVECEXP (PATTERN (insn), 0, i))) 882 return true; 883 884 return false; 885 } 886 887 /* We can be passed an insn or part of one. If we are passed an insn, 888 check if a side-effect of the insn clobbers REG. */ 889 if (INSN_P (insn) 890 && (FIND_REG_INC_NOTE (insn, reg) 891 || (CALL_P (insn) 892 && ((REG_P (reg) 893 && REGNO (reg) < FIRST_PSEUDO_REGISTER 894 && overlaps_hard_reg_set_p (regs_invalidated_by_call, 895 GET_MODE (reg), REGNO (reg))) 896 || MEM_P (reg) 897 || find_reg_fusage (insn, CLOBBER, reg))))) 898 return true; 899 900 return set_of (reg, insn) != NULL_RTX; 901 } 902 903 /* Similar to reg_set_between_p, but check all registers in X. Return 0 904 only if none of them are modified between START and END. Return 1 if 905 X contains a MEM; this routine does use memory aliasing. */ 906 907 int 908 modified_between_p (const_rtx x, const_rtx start, const_rtx end) 909 { 910 const enum rtx_code code = GET_CODE (x); 911 const char *fmt; 912 int i, j; 913 rtx insn; 914 915 if (start == end) 916 return 0; 917 918 switch (code) 919 { 920 CASE_CONST_ANY: 921 case CONST: 922 case SYMBOL_REF: 923 case LABEL_REF: 924 return 0; 925 926 case PC: 927 case CC0: 928 return 1; 929 930 case MEM: 931 if (modified_between_p (XEXP (x, 0), start, end)) 932 return 1; 933 if (MEM_READONLY_P (x)) 934 return 0; 935 for (insn = NEXT_INSN (start); insn != end; insn = NEXT_INSN (insn)) 936 if (memory_modified_in_insn_p (x, insn)) 937 return 1; 938 return 0; 939 break; 940 941 case REG: 942 return reg_set_between_p (x, start, end); 943 944 default: 945 break; 946 } 947 948 fmt = GET_RTX_FORMAT (code); 949 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 950 { 951 if (fmt[i] == 'e' && modified_between_p (XEXP (x, i), start, end)) 952 return 1; 953 954 else if (fmt[i] == 'E') 955 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 956 if (modified_between_p (XVECEXP (x, i, j), start, end)) 957 return 1; 958 } 959 960 return 0; 961 } 962 963 /* Similar to reg_set_p, but check all registers in X. Return 0 only if none 964 of them are modified in INSN. Return 1 if X contains a MEM; this routine 965 does use memory aliasing. */ 966 967 int 968 modified_in_p (const_rtx x, const_rtx insn) 969 { 970 const enum rtx_code code = GET_CODE (x); 971 const char *fmt; 972 int i, j; 973 974 switch (code) 975 { 976 CASE_CONST_ANY: 977 case CONST: 978 case SYMBOL_REF: 979 case LABEL_REF: 980 return 0; 981 982 case PC: 983 case CC0: 984 return 1; 985 986 case MEM: 987 if (modified_in_p (XEXP (x, 0), insn)) 988 return 1; 989 if (MEM_READONLY_P (x)) 990 return 0; 991 if (memory_modified_in_insn_p (x, insn)) 992 return 1; 993 return 0; 994 break; 995 996 case REG: 997 return reg_set_p (x, insn); 998 999 default: 1000 break; 1001 } 1002 1003 fmt = GET_RTX_FORMAT (code); 1004 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1005 { 1006 if (fmt[i] == 'e' && modified_in_p (XEXP (x, i), insn)) 1007 return 1; 1008 1009 else if (fmt[i] == 'E') 1010 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1011 if (modified_in_p (XVECEXP (x, i, j), insn)) 1012 return 1; 1013 } 1014 1015 return 0; 1016 } 1017 1018 /* Helper function for set_of. */ 1019 struct set_of_data 1020 { 1021 const_rtx found; 1022 const_rtx pat; 1023 }; 1024 1025 static void 1026 set_of_1 (rtx x, const_rtx pat, void *data1) 1027 { 1028 struct set_of_data *const data = (struct set_of_data *) (data1); 1029 if (rtx_equal_p (x, data->pat) 1030 || (!MEM_P (x) && reg_overlap_mentioned_p (data->pat, x))) 1031 data->found = pat; 1032 } 1033 1034 /* Give an INSN, return a SET or CLOBBER expression that does modify PAT 1035 (either directly or via STRICT_LOW_PART and similar modifiers). */ 1036 const_rtx 1037 set_of (const_rtx pat, const_rtx insn) 1038 { 1039 struct set_of_data data; 1040 data.found = NULL_RTX; 1041 data.pat = pat; 1042 note_stores (INSN_P (insn) ? PATTERN (insn) : insn, set_of_1, &data); 1043 return data.found; 1044 } 1045 1046 /* This function, called through note_stores, collects sets and 1047 clobbers of hard registers in a HARD_REG_SET, which is pointed to 1048 by DATA. */ 1049 void 1050 record_hard_reg_sets (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) 1051 { 1052 HARD_REG_SET *pset = (HARD_REG_SET *)data; 1053 if (REG_P (x) && HARD_REGISTER_P (x)) 1054 add_to_hard_reg_set (pset, GET_MODE (x), REGNO (x)); 1055 } 1056 1057 /* Examine INSN, and compute the set of hard registers written by it. 1058 Store it in *PSET. Should only be called after reload. */ 1059 void 1060 find_all_hard_reg_sets (const_rtx insn, HARD_REG_SET *pset) 1061 { 1062 rtx link; 1063 1064 CLEAR_HARD_REG_SET (*pset); 1065 note_stores (PATTERN (insn), record_hard_reg_sets, pset); 1066 if (CALL_P (insn)) 1067 IOR_HARD_REG_SET (*pset, call_used_reg_set); 1068 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1069 if (REG_NOTE_KIND (link) == REG_INC) 1070 record_hard_reg_sets (XEXP (link, 0), NULL, pset); 1071 } 1072 1073 /* A for_each_rtx subroutine of record_hard_reg_uses. */ 1074 static int 1075 record_hard_reg_uses_1 (rtx *px, void *data) 1076 { 1077 rtx x = *px; 1078 HARD_REG_SET *pused = (HARD_REG_SET *)data; 1079 1080 if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER) 1081 { 1082 int nregs = hard_regno_nregs[REGNO (x)][GET_MODE (x)]; 1083 while (nregs-- > 0) 1084 SET_HARD_REG_BIT (*pused, REGNO (x) + nregs); 1085 } 1086 return 0; 1087 } 1088 1089 /* Like record_hard_reg_sets, but called through note_uses. */ 1090 void 1091 record_hard_reg_uses (rtx *px, void *data) 1092 { 1093 for_each_rtx (px, record_hard_reg_uses_1, data); 1094 } 1095 1096 /* Given an INSN, return a SET expression if this insn has only a single SET. 1097 It may also have CLOBBERs, USEs, or SET whose output 1098 will not be used, which we ignore. */ 1099 1100 rtx 1101 single_set_2 (const_rtx insn, const_rtx pat) 1102 { 1103 rtx set = NULL; 1104 int set_verified = 1; 1105 int i; 1106 1107 if (GET_CODE (pat) == PARALLEL) 1108 { 1109 for (i = 0; i < XVECLEN (pat, 0); i++) 1110 { 1111 rtx sub = XVECEXP (pat, 0, i); 1112 switch (GET_CODE (sub)) 1113 { 1114 case USE: 1115 case CLOBBER: 1116 break; 1117 1118 case SET: 1119 /* We can consider insns having multiple sets, where all 1120 but one are dead as single set insns. In common case 1121 only single set is present in the pattern so we want 1122 to avoid checking for REG_UNUSED notes unless necessary. 1123 1124 When we reach set first time, we just expect this is 1125 the single set we are looking for and only when more 1126 sets are found in the insn, we check them. */ 1127 if (!set_verified) 1128 { 1129 if (find_reg_note (insn, REG_UNUSED, SET_DEST (set)) 1130 && !side_effects_p (set)) 1131 set = NULL; 1132 else 1133 set_verified = 1; 1134 } 1135 if (!set) 1136 set = sub, set_verified = 0; 1137 else if (!find_reg_note (insn, REG_UNUSED, SET_DEST (sub)) 1138 || side_effects_p (sub)) 1139 return NULL_RTX; 1140 break; 1141 1142 default: 1143 return NULL_RTX; 1144 } 1145 } 1146 } 1147 return set; 1148 } 1149 1150 /* Given an INSN, return nonzero if it has more than one SET, else return 1151 zero. */ 1152 1153 int 1154 multiple_sets (const_rtx insn) 1155 { 1156 int found; 1157 int i; 1158 1159 /* INSN must be an insn. */ 1160 if (! INSN_P (insn)) 1161 return 0; 1162 1163 /* Only a PARALLEL can have multiple SETs. */ 1164 if (GET_CODE (PATTERN (insn)) == PARALLEL) 1165 { 1166 for (i = 0, found = 0; i < XVECLEN (PATTERN (insn), 0); i++) 1167 if (GET_CODE (XVECEXP (PATTERN (insn), 0, i)) == SET) 1168 { 1169 /* If we have already found a SET, then return now. */ 1170 if (found) 1171 return 1; 1172 else 1173 found = 1; 1174 } 1175 } 1176 1177 /* Either zero or one SET. */ 1178 return 0; 1179 } 1180 1181 /* Return nonzero if the destination of SET equals the source 1182 and there are no side effects. */ 1183 1184 int 1185 set_noop_p (const_rtx set) 1186 { 1187 rtx src = SET_SRC (set); 1188 rtx dst = SET_DEST (set); 1189 1190 if (dst == pc_rtx && src == pc_rtx) 1191 return 1; 1192 1193 if (MEM_P (dst) && MEM_P (src)) 1194 return rtx_equal_p (dst, src) && !side_effects_p (dst); 1195 1196 if (GET_CODE (dst) == ZERO_EXTRACT) 1197 return rtx_equal_p (XEXP (dst, 0), src) 1198 && ! BYTES_BIG_ENDIAN && XEXP (dst, 2) == const0_rtx 1199 && !side_effects_p (src); 1200 1201 if (GET_CODE (dst) == STRICT_LOW_PART) 1202 dst = XEXP (dst, 0); 1203 1204 if (GET_CODE (src) == SUBREG && GET_CODE (dst) == SUBREG) 1205 { 1206 if (SUBREG_BYTE (src) != SUBREG_BYTE (dst)) 1207 return 0; 1208 src = SUBREG_REG (src); 1209 dst = SUBREG_REG (dst); 1210 } 1211 1212 return (REG_P (src) && REG_P (dst) 1213 && REGNO (src) == REGNO (dst)); 1214 } 1215 1216 /* Return nonzero if an insn consists only of SETs, each of which only sets a 1217 value to itself. */ 1218 1219 int 1220 noop_move_p (const_rtx insn) 1221 { 1222 rtx pat = PATTERN (insn); 1223 1224 if (INSN_CODE (insn) == NOOP_MOVE_INSN_CODE) 1225 return 1; 1226 1227 /* Insns carrying these notes are useful later on. */ 1228 if (find_reg_note (insn, REG_EQUAL, NULL_RTX)) 1229 return 0; 1230 1231 if (GET_CODE (pat) == SET && set_noop_p (pat)) 1232 return 1; 1233 1234 if (GET_CODE (pat) == PARALLEL) 1235 { 1236 int i; 1237 /* If nothing but SETs of registers to themselves, 1238 this insn can also be deleted. */ 1239 for (i = 0; i < XVECLEN (pat, 0); i++) 1240 { 1241 rtx tem = XVECEXP (pat, 0, i); 1242 1243 if (GET_CODE (tem) == USE 1244 || GET_CODE (tem) == CLOBBER) 1245 continue; 1246 1247 if (GET_CODE (tem) != SET || ! set_noop_p (tem)) 1248 return 0; 1249 } 1250 1251 return 1; 1252 } 1253 return 0; 1254 } 1255 1256 1257 /* Return the last thing that X was assigned from before *PINSN. If VALID_TO 1258 is not NULL_RTX then verify that the object is not modified up to VALID_TO. 1259 If the object was modified, if we hit a partial assignment to X, or hit a 1260 CODE_LABEL first, return X. If we found an assignment, update *PINSN to 1261 point to it. ALLOW_HWREG is set to 1 if hardware registers are allowed to 1262 be the src. */ 1263 1264 rtx 1265 find_last_value (rtx x, rtx *pinsn, rtx valid_to, int allow_hwreg) 1266 { 1267 rtx p; 1268 1269 for (p = PREV_INSN (*pinsn); p && !LABEL_P (p); 1270 p = PREV_INSN (p)) 1271 if (INSN_P (p)) 1272 { 1273 rtx set = single_set (p); 1274 rtx note = find_reg_note (p, REG_EQUAL, NULL_RTX); 1275 1276 if (set && rtx_equal_p (x, SET_DEST (set))) 1277 { 1278 rtx src = SET_SRC (set); 1279 1280 if (note && GET_CODE (XEXP (note, 0)) != EXPR_LIST) 1281 src = XEXP (note, 0); 1282 1283 if ((valid_to == NULL_RTX 1284 || ! modified_between_p (src, PREV_INSN (p), valid_to)) 1285 /* Reject hard registers because we don't usually want 1286 to use them; we'd rather use a pseudo. */ 1287 && (! (REG_P (src) 1288 && REGNO (src) < FIRST_PSEUDO_REGISTER) || allow_hwreg)) 1289 { 1290 *pinsn = p; 1291 return src; 1292 } 1293 } 1294 1295 /* If set in non-simple way, we don't have a value. */ 1296 if (reg_set_p (x, p)) 1297 break; 1298 } 1299 1300 return x; 1301 } 1302 1303 /* Return nonzero if register in range [REGNO, ENDREGNO) 1304 appears either explicitly or implicitly in X 1305 other than being stored into. 1306 1307 References contained within the substructure at LOC do not count. 1308 LOC may be zero, meaning don't ignore anything. */ 1309 1310 int 1311 refers_to_regno_p (unsigned int regno, unsigned int endregno, const_rtx x, 1312 rtx *loc) 1313 { 1314 int i; 1315 unsigned int x_regno; 1316 RTX_CODE code; 1317 const char *fmt; 1318 1319 repeat: 1320 /* The contents of a REG_NONNEG note is always zero, so we must come here 1321 upon repeat in case the last REG_NOTE is a REG_NONNEG note. */ 1322 if (x == 0) 1323 return 0; 1324 1325 code = GET_CODE (x); 1326 1327 switch (code) 1328 { 1329 case REG: 1330 x_regno = REGNO (x); 1331 1332 /* If we modifying the stack, frame, or argument pointer, it will 1333 clobber a virtual register. In fact, we could be more precise, 1334 but it isn't worth it. */ 1335 if ((x_regno == STACK_POINTER_REGNUM 1336 #if FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 1337 || x_regno == ARG_POINTER_REGNUM 1338 #endif 1339 || x_regno == FRAME_POINTER_REGNUM) 1340 && regno >= FIRST_VIRTUAL_REGISTER && regno <= LAST_VIRTUAL_REGISTER) 1341 return 1; 1342 1343 return endregno > x_regno && regno < END_REGNO (x); 1344 1345 case SUBREG: 1346 /* If this is a SUBREG of a hard reg, we can see exactly which 1347 registers are being modified. Otherwise, handle normally. */ 1348 if (REG_P (SUBREG_REG (x)) 1349 && REGNO (SUBREG_REG (x)) < FIRST_PSEUDO_REGISTER) 1350 { 1351 unsigned int inner_regno = subreg_regno (x); 1352 unsigned int inner_endregno 1353 = inner_regno + (inner_regno < FIRST_PSEUDO_REGISTER 1354 ? subreg_nregs (x) : 1); 1355 1356 return endregno > inner_regno && regno < inner_endregno; 1357 } 1358 break; 1359 1360 case CLOBBER: 1361 case SET: 1362 if (&SET_DEST (x) != loc 1363 /* Note setting a SUBREG counts as referring to the REG it is in for 1364 a pseudo but not for hard registers since we can 1365 treat each word individually. */ 1366 && ((GET_CODE (SET_DEST (x)) == SUBREG 1367 && loc != &SUBREG_REG (SET_DEST (x)) 1368 && REG_P (SUBREG_REG (SET_DEST (x))) 1369 && REGNO (SUBREG_REG (SET_DEST (x))) >= FIRST_PSEUDO_REGISTER 1370 && refers_to_regno_p (regno, endregno, 1371 SUBREG_REG (SET_DEST (x)), loc)) 1372 || (!REG_P (SET_DEST (x)) 1373 && refers_to_regno_p (regno, endregno, SET_DEST (x), loc)))) 1374 return 1; 1375 1376 if (code == CLOBBER || loc == &SET_SRC (x)) 1377 return 0; 1378 x = SET_SRC (x); 1379 goto repeat; 1380 1381 default: 1382 break; 1383 } 1384 1385 /* X does not match, so try its subexpressions. */ 1386 1387 fmt = GET_RTX_FORMAT (code); 1388 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1389 { 1390 if (fmt[i] == 'e' && loc != &XEXP (x, i)) 1391 { 1392 if (i == 0) 1393 { 1394 x = XEXP (x, 0); 1395 goto repeat; 1396 } 1397 else 1398 if (refers_to_regno_p (regno, endregno, XEXP (x, i), loc)) 1399 return 1; 1400 } 1401 else if (fmt[i] == 'E') 1402 { 1403 int j; 1404 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1405 if (loc != &XVECEXP (x, i, j) 1406 && refers_to_regno_p (regno, endregno, XVECEXP (x, i, j), loc)) 1407 return 1; 1408 } 1409 } 1410 return 0; 1411 } 1412 1413 /* Nonzero if modifying X will affect IN. If X is a register or a SUBREG, 1414 we check if any register number in X conflicts with the relevant register 1415 numbers. If X is a constant, return 0. If X is a MEM, return 1 iff IN 1416 contains a MEM (we don't bother checking for memory addresses that can't 1417 conflict because we expect this to be a rare case. */ 1418 1419 int 1420 reg_overlap_mentioned_p (const_rtx x, const_rtx in) 1421 { 1422 unsigned int regno, endregno; 1423 1424 /* If either argument is a constant, then modifying X can not 1425 affect IN. Here we look at IN, we can profitably combine 1426 CONSTANT_P (x) with the switch statement below. */ 1427 if (CONSTANT_P (in)) 1428 return 0; 1429 1430 recurse: 1431 switch (GET_CODE (x)) 1432 { 1433 case STRICT_LOW_PART: 1434 case ZERO_EXTRACT: 1435 case SIGN_EXTRACT: 1436 /* Overly conservative. */ 1437 x = XEXP (x, 0); 1438 goto recurse; 1439 1440 case SUBREG: 1441 regno = REGNO (SUBREG_REG (x)); 1442 if (regno < FIRST_PSEUDO_REGISTER) 1443 regno = subreg_regno (x); 1444 endregno = regno + (regno < FIRST_PSEUDO_REGISTER 1445 ? subreg_nregs (x) : 1); 1446 goto do_reg; 1447 1448 case REG: 1449 regno = REGNO (x); 1450 endregno = END_REGNO (x); 1451 do_reg: 1452 return refers_to_regno_p (regno, endregno, in, (rtx*) 0); 1453 1454 case MEM: 1455 { 1456 const char *fmt; 1457 int i; 1458 1459 if (MEM_P (in)) 1460 return 1; 1461 1462 fmt = GET_RTX_FORMAT (GET_CODE (in)); 1463 for (i = GET_RTX_LENGTH (GET_CODE (in)) - 1; i >= 0; i--) 1464 if (fmt[i] == 'e') 1465 { 1466 if (reg_overlap_mentioned_p (x, XEXP (in, i))) 1467 return 1; 1468 } 1469 else if (fmt[i] == 'E') 1470 { 1471 int j; 1472 for (j = XVECLEN (in, i) - 1; j >= 0; --j) 1473 if (reg_overlap_mentioned_p (x, XVECEXP (in, i, j))) 1474 return 1; 1475 } 1476 1477 return 0; 1478 } 1479 1480 case SCRATCH: 1481 case PC: 1482 case CC0: 1483 return reg_mentioned_p (x, in); 1484 1485 case PARALLEL: 1486 { 1487 int i; 1488 1489 /* If any register in here refers to it we return true. */ 1490 for (i = XVECLEN (x, 0) - 1; i >= 0; i--) 1491 if (XEXP (XVECEXP (x, 0, i), 0) != 0 1492 && reg_overlap_mentioned_p (XEXP (XVECEXP (x, 0, i), 0), in)) 1493 return 1; 1494 return 0; 1495 } 1496 1497 default: 1498 gcc_assert (CONSTANT_P (x)); 1499 return 0; 1500 } 1501 } 1502 1503 /* Call FUN on each register or MEM that is stored into or clobbered by X. 1504 (X would be the pattern of an insn). DATA is an arbitrary pointer, 1505 ignored by note_stores, but passed to FUN. 1506 1507 FUN receives three arguments: 1508 1. the REG, MEM, CC0 or PC being stored in or clobbered, 1509 2. the SET or CLOBBER rtx that does the store, 1510 3. the pointer DATA provided to note_stores. 1511 1512 If the item being stored in or clobbered is a SUBREG of a hard register, 1513 the SUBREG will be passed. */ 1514 1515 void 1516 note_stores (const_rtx x, void (*fun) (rtx, const_rtx, void *), void *data) 1517 { 1518 int i; 1519 1520 if (GET_CODE (x) == COND_EXEC) 1521 x = COND_EXEC_CODE (x); 1522 1523 if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) 1524 { 1525 rtx dest = SET_DEST (x); 1526 1527 while ((GET_CODE (dest) == SUBREG 1528 && (!REG_P (SUBREG_REG (dest)) 1529 || REGNO (SUBREG_REG (dest)) >= FIRST_PSEUDO_REGISTER)) 1530 || GET_CODE (dest) == ZERO_EXTRACT 1531 || GET_CODE (dest) == STRICT_LOW_PART) 1532 dest = XEXP (dest, 0); 1533 1534 /* If we have a PARALLEL, SET_DEST is a list of EXPR_LIST expressions, 1535 each of whose first operand is a register. */ 1536 if (GET_CODE (dest) == PARALLEL) 1537 { 1538 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) 1539 if (XEXP (XVECEXP (dest, 0, i), 0) != 0) 1540 (*fun) (XEXP (XVECEXP (dest, 0, i), 0), x, data); 1541 } 1542 else 1543 (*fun) (dest, x, data); 1544 } 1545 1546 else if (GET_CODE (x) == PARALLEL) 1547 for (i = XVECLEN (x, 0) - 1; i >= 0; i--) 1548 note_stores (XVECEXP (x, 0, i), fun, data); 1549 } 1550 1551 /* Like notes_stores, but call FUN for each expression that is being 1552 referenced in PBODY, a pointer to the PATTERN of an insn. We only call 1553 FUN for each expression, not any interior subexpressions. FUN receives a 1554 pointer to the expression and the DATA passed to this function. 1555 1556 Note that this is not quite the same test as that done in reg_referenced_p 1557 since that considers something as being referenced if it is being 1558 partially set, while we do not. */ 1559 1560 void 1561 note_uses (rtx *pbody, void (*fun) (rtx *, void *), void *data) 1562 { 1563 rtx body = *pbody; 1564 int i; 1565 1566 switch (GET_CODE (body)) 1567 { 1568 case COND_EXEC: 1569 (*fun) (&COND_EXEC_TEST (body), data); 1570 note_uses (&COND_EXEC_CODE (body), fun, data); 1571 return; 1572 1573 case PARALLEL: 1574 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 1575 note_uses (&XVECEXP (body, 0, i), fun, data); 1576 return; 1577 1578 case SEQUENCE: 1579 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 1580 note_uses (&PATTERN (XVECEXP (body, 0, i)), fun, data); 1581 return; 1582 1583 case USE: 1584 (*fun) (&XEXP (body, 0), data); 1585 return; 1586 1587 case ASM_OPERANDS: 1588 for (i = ASM_OPERANDS_INPUT_LENGTH (body) - 1; i >= 0; i--) 1589 (*fun) (&ASM_OPERANDS_INPUT (body, i), data); 1590 return; 1591 1592 case TRAP_IF: 1593 (*fun) (&TRAP_CONDITION (body), data); 1594 return; 1595 1596 case PREFETCH: 1597 (*fun) (&XEXP (body, 0), data); 1598 return; 1599 1600 case UNSPEC: 1601 case UNSPEC_VOLATILE: 1602 for (i = XVECLEN (body, 0) - 1; i >= 0; i--) 1603 (*fun) (&XVECEXP (body, 0, i), data); 1604 return; 1605 1606 case CLOBBER: 1607 if (MEM_P (XEXP (body, 0))) 1608 (*fun) (&XEXP (XEXP (body, 0), 0), data); 1609 return; 1610 1611 case SET: 1612 { 1613 rtx dest = SET_DEST (body); 1614 1615 /* For sets we replace everything in source plus registers in memory 1616 expression in store and operands of a ZERO_EXTRACT. */ 1617 (*fun) (&SET_SRC (body), data); 1618 1619 if (GET_CODE (dest) == ZERO_EXTRACT) 1620 { 1621 (*fun) (&XEXP (dest, 1), data); 1622 (*fun) (&XEXP (dest, 2), data); 1623 } 1624 1625 while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == STRICT_LOW_PART) 1626 dest = XEXP (dest, 0); 1627 1628 if (MEM_P (dest)) 1629 (*fun) (&XEXP (dest, 0), data); 1630 } 1631 return; 1632 1633 default: 1634 /* All the other possibilities never store. */ 1635 (*fun) (pbody, data); 1636 return; 1637 } 1638 } 1639 1640 /* Return nonzero if X's old contents don't survive after INSN. 1641 This will be true if X is (cc0) or if X is a register and 1642 X dies in INSN or because INSN entirely sets X. 1643 1644 "Entirely set" means set directly and not through a SUBREG, or 1645 ZERO_EXTRACT, so no trace of the old contents remains. 1646 Likewise, REG_INC does not count. 1647 1648 REG may be a hard or pseudo reg. Renumbering is not taken into account, 1649 but for this use that makes no difference, since regs don't overlap 1650 during their lifetimes. Therefore, this function may be used 1651 at any time after deaths have been computed. 1652 1653 If REG is a hard reg that occupies multiple machine registers, this 1654 function will only return 1 if each of those registers will be replaced 1655 by INSN. */ 1656 1657 int 1658 dead_or_set_p (const_rtx insn, const_rtx x) 1659 { 1660 unsigned int regno, end_regno; 1661 unsigned int i; 1662 1663 /* Can't use cc0_rtx below since this file is used by genattrtab.c. */ 1664 if (GET_CODE (x) == CC0) 1665 return 1; 1666 1667 gcc_assert (REG_P (x)); 1668 1669 regno = REGNO (x); 1670 end_regno = END_REGNO (x); 1671 for (i = regno; i < end_regno; i++) 1672 if (! dead_or_set_regno_p (insn, i)) 1673 return 0; 1674 1675 return 1; 1676 } 1677 1678 /* Return TRUE iff DEST is a register or subreg of a register and 1679 doesn't change the number of words of the inner register, and any 1680 part of the register is TEST_REGNO. */ 1681 1682 static bool 1683 covers_regno_no_parallel_p (const_rtx dest, unsigned int test_regno) 1684 { 1685 unsigned int regno, endregno; 1686 1687 if (GET_CODE (dest) == SUBREG 1688 && (((GET_MODE_SIZE (GET_MODE (dest)) 1689 + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1690 == ((GET_MODE_SIZE (GET_MODE (SUBREG_REG (dest))) 1691 + UNITS_PER_WORD - 1) / UNITS_PER_WORD))) 1692 dest = SUBREG_REG (dest); 1693 1694 if (!REG_P (dest)) 1695 return false; 1696 1697 regno = REGNO (dest); 1698 endregno = END_REGNO (dest); 1699 return (test_regno >= regno && test_regno < endregno); 1700 } 1701 1702 /* Like covers_regno_no_parallel_p, but also handles PARALLELs where 1703 any member matches the covers_regno_no_parallel_p criteria. */ 1704 1705 static bool 1706 covers_regno_p (const_rtx dest, unsigned int test_regno) 1707 { 1708 if (GET_CODE (dest) == PARALLEL) 1709 { 1710 /* Some targets place small structures in registers for return 1711 values of functions, and those registers are wrapped in 1712 PARALLELs that we may see as the destination of a SET. */ 1713 int i; 1714 1715 for (i = XVECLEN (dest, 0) - 1; i >= 0; i--) 1716 { 1717 rtx inner = XEXP (XVECEXP (dest, 0, i), 0); 1718 if (inner != NULL_RTX 1719 && covers_regno_no_parallel_p (inner, test_regno)) 1720 return true; 1721 } 1722 1723 return false; 1724 } 1725 else 1726 return covers_regno_no_parallel_p (dest, test_regno); 1727 } 1728 1729 /* Utility function for dead_or_set_p to check an individual register. */ 1730 1731 int 1732 dead_or_set_regno_p (const_rtx insn, unsigned int test_regno) 1733 { 1734 const_rtx pattern; 1735 1736 /* See if there is a death note for something that includes TEST_REGNO. */ 1737 if (find_regno_note (insn, REG_DEAD, test_regno)) 1738 return 1; 1739 1740 if (CALL_P (insn) 1741 && find_regno_fusage (insn, CLOBBER, test_regno)) 1742 return 1; 1743 1744 pattern = PATTERN (insn); 1745 1746 /* If a COND_EXEC is not executed, the value survives. */ 1747 if (GET_CODE (pattern) == COND_EXEC) 1748 return 0; 1749 1750 if (GET_CODE (pattern) == SET) 1751 return covers_regno_p (SET_DEST (pattern), test_regno); 1752 else if (GET_CODE (pattern) == PARALLEL) 1753 { 1754 int i; 1755 1756 for (i = XVECLEN (pattern, 0) - 1; i >= 0; i--) 1757 { 1758 rtx body = XVECEXP (pattern, 0, i); 1759 1760 if (GET_CODE (body) == COND_EXEC) 1761 body = COND_EXEC_CODE (body); 1762 1763 if ((GET_CODE (body) == SET || GET_CODE (body) == CLOBBER) 1764 && covers_regno_p (SET_DEST (body), test_regno)) 1765 return 1; 1766 } 1767 } 1768 1769 return 0; 1770 } 1771 1772 /* Return the reg-note of kind KIND in insn INSN, if there is one. 1773 If DATUM is nonzero, look for one whose datum is DATUM. */ 1774 1775 rtx 1776 find_reg_note (const_rtx insn, enum reg_note kind, const_rtx datum) 1777 { 1778 rtx link; 1779 1780 gcc_checking_assert (insn); 1781 1782 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */ 1783 if (! INSN_P (insn)) 1784 return 0; 1785 if (datum == 0) 1786 { 1787 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1788 if (REG_NOTE_KIND (link) == kind) 1789 return link; 1790 return 0; 1791 } 1792 1793 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1794 if (REG_NOTE_KIND (link) == kind && datum == XEXP (link, 0)) 1795 return link; 1796 return 0; 1797 } 1798 1799 /* Return the reg-note of kind KIND in insn INSN which applies to register 1800 number REGNO, if any. Return 0 if there is no such reg-note. Note that 1801 the REGNO of this NOTE need not be REGNO if REGNO is a hard register; 1802 it might be the case that the note overlaps REGNO. */ 1803 1804 rtx 1805 find_regno_note (const_rtx insn, enum reg_note kind, unsigned int regno) 1806 { 1807 rtx link; 1808 1809 /* Ignore anything that is not an INSN, JUMP_INSN or CALL_INSN. */ 1810 if (! INSN_P (insn)) 1811 return 0; 1812 1813 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1814 if (REG_NOTE_KIND (link) == kind 1815 /* Verify that it is a register, so that scratch and MEM won't cause a 1816 problem here. */ 1817 && REG_P (XEXP (link, 0)) 1818 && REGNO (XEXP (link, 0)) <= regno 1819 && END_REGNO (XEXP (link, 0)) > regno) 1820 return link; 1821 return 0; 1822 } 1823 1824 /* Return a REG_EQUIV or REG_EQUAL note if insn has only a single set and 1825 has such a note. */ 1826 1827 rtx 1828 find_reg_equal_equiv_note (const_rtx insn) 1829 { 1830 rtx link; 1831 1832 if (!INSN_P (insn)) 1833 return 0; 1834 1835 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 1836 if (REG_NOTE_KIND (link) == REG_EQUAL 1837 || REG_NOTE_KIND (link) == REG_EQUIV) 1838 { 1839 /* FIXME: We should never have REG_EQUAL/REG_EQUIV notes on 1840 insns that have multiple sets. Checking single_set to 1841 make sure of this is not the proper check, as explained 1842 in the comment in set_unique_reg_note. 1843 1844 This should be changed into an assert. */ 1845 if (GET_CODE (PATTERN (insn)) == PARALLEL && multiple_sets (insn)) 1846 return 0; 1847 return link; 1848 } 1849 return NULL; 1850 } 1851 1852 /* Check whether INSN is a single_set whose source is known to be 1853 equivalent to a constant. Return that constant if so, otherwise 1854 return null. */ 1855 1856 rtx 1857 find_constant_src (const_rtx insn) 1858 { 1859 rtx note, set, x; 1860 1861 set = single_set (insn); 1862 if (set) 1863 { 1864 x = avoid_constant_pool_reference (SET_SRC (set)); 1865 if (CONSTANT_P (x)) 1866 return x; 1867 } 1868 1869 note = find_reg_equal_equiv_note (insn); 1870 if (note && CONSTANT_P (XEXP (note, 0))) 1871 return XEXP (note, 0); 1872 1873 return NULL_RTX; 1874 } 1875 1876 /* Return true if DATUM, or any overlap of DATUM, of kind CODE is found 1877 in the CALL_INSN_FUNCTION_USAGE information of INSN. */ 1878 1879 int 1880 find_reg_fusage (const_rtx insn, enum rtx_code code, const_rtx datum) 1881 { 1882 /* If it's not a CALL_INSN, it can't possibly have a 1883 CALL_INSN_FUNCTION_USAGE field, so don't bother checking. */ 1884 if (!CALL_P (insn)) 1885 return 0; 1886 1887 gcc_assert (datum); 1888 1889 if (!REG_P (datum)) 1890 { 1891 rtx link; 1892 1893 for (link = CALL_INSN_FUNCTION_USAGE (insn); 1894 link; 1895 link = XEXP (link, 1)) 1896 if (GET_CODE (XEXP (link, 0)) == code 1897 && rtx_equal_p (datum, XEXP (XEXP (link, 0), 0))) 1898 return 1; 1899 } 1900 else 1901 { 1902 unsigned int regno = REGNO (datum); 1903 1904 /* CALL_INSN_FUNCTION_USAGE information cannot contain references 1905 to pseudo registers, so don't bother checking. */ 1906 1907 if (regno < FIRST_PSEUDO_REGISTER) 1908 { 1909 unsigned int end_regno = END_HARD_REGNO (datum); 1910 unsigned int i; 1911 1912 for (i = regno; i < end_regno; i++) 1913 if (find_regno_fusage (insn, code, i)) 1914 return 1; 1915 } 1916 } 1917 1918 return 0; 1919 } 1920 1921 /* Return true if REGNO, or any overlap of REGNO, of kind CODE is found 1922 in the CALL_INSN_FUNCTION_USAGE information of INSN. */ 1923 1924 int 1925 find_regno_fusage (const_rtx insn, enum rtx_code code, unsigned int regno) 1926 { 1927 rtx link; 1928 1929 /* CALL_INSN_FUNCTION_USAGE information cannot contain references 1930 to pseudo registers, so don't bother checking. */ 1931 1932 if (regno >= FIRST_PSEUDO_REGISTER 1933 || !CALL_P (insn) ) 1934 return 0; 1935 1936 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) 1937 { 1938 rtx op, reg; 1939 1940 if (GET_CODE (op = XEXP (link, 0)) == code 1941 && REG_P (reg = XEXP (op, 0)) 1942 && REGNO (reg) <= regno 1943 && END_HARD_REGNO (reg) > regno) 1944 return 1; 1945 } 1946 1947 return 0; 1948 } 1949 1950 1951 /* Allocate a register note with kind KIND and datum DATUM. LIST is 1952 stored as the pointer to the next register note. */ 1953 1954 rtx 1955 alloc_reg_note (enum reg_note kind, rtx datum, rtx list) 1956 { 1957 rtx note; 1958 1959 switch (kind) 1960 { 1961 case REG_CC_SETTER: 1962 case REG_CC_USER: 1963 case REG_LABEL_TARGET: 1964 case REG_LABEL_OPERAND: 1965 case REG_TM: 1966 /* These types of register notes use an INSN_LIST rather than an 1967 EXPR_LIST, so that copying is done right and dumps look 1968 better. */ 1969 note = alloc_INSN_LIST (datum, list); 1970 PUT_REG_NOTE_KIND (note, kind); 1971 break; 1972 1973 default: 1974 note = alloc_EXPR_LIST (kind, datum, list); 1975 break; 1976 } 1977 1978 return note; 1979 } 1980 1981 /* Add register note with kind KIND and datum DATUM to INSN. */ 1982 1983 void 1984 add_reg_note (rtx insn, enum reg_note kind, rtx datum) 1985 { 1986 REG_NOTES (insn) = alloc_reg_note (kind, datum, REG_NOTES (insn)); 1987 } 1988 1989 /* Remove register note NOTE from the REG_NOTES of INSN. */ 1990 1991 void 1992 remove_note (rtx insn, const_rtx note) 1993 { 1994 rtx link; 1995 1996 if (note == NULL_RTX) 1997 return; 1998 1999 if (REG_NOTES (insn) == note) 2000 REG_NOTES (insn) = XEXP (note, 1); 2001 else 2002 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 2003 if (XEXP (link, 1) == note) 2004 { 2005 XEXP (link, 1) = XEXP (note, 1); 2006 break; 2007 } 2008 2009 switch (REG_NOTE_KIND (note)) 2010 { 2011 case REG_EQUAL: 2012 case REG_EQUIV: 2013 df_notes_rescan (insn); 2014 break; 2015 default: 2016 break; 2017 } 2018 } 2019 2020 /* Remove REG_EQUAL and/or REG_EQUIV notes if INSN has such notes. */ 2021 2022 void 2023 remove_reg_equal_equiv_notes (rtx insn) 2024 { 2025 rtx *loc; 2026 2027 loc = ®_NOTES (insn); 2028 while (*loc) 2029 { 2030 enum reg_note kind = REG_NOTE_KIND (*loc); 2031 if (kind == REG_EQUAL || kind == REG_EQUIV) 2032 *loc = XEXP (*loc, 1); 2033 else 2034 loc = &XEXP (*loc, 1); 2035 } 2036 } 2037 2038 /* Remove all REG_EQUAL and REG_EQUIV notes referring to REGNO. */ 2039 2040 void 2041 remove_reg_equal_equiv_notes_for_regno (unsigned int regno) 2042 { 2043 df_ref eq_use; 2044 2045 if (!df) 2046 return; 2047 2048 /* This loop is a little tricky. We cannot just go down the chain because 2049 it is being modified by some actions in the loop. So we just iterate 2050 over the head. We plan to drain the list anyway. */ 2051 while ((eq_use = DF_REG_EQ_USE_CHAIN (regno)) != NULL) 2052 { 2053 rtx insn = DF_REF_INSN (eq_use); 2054 rtx note = find_reg_equal_equiv_note (insn); 2055 2056 /* This assert is generally triggered when someone deletes a REG_EQUAL 2057 or REG_EQUIV note by hacking the list manually rather than calling 2058 remove_note. */ 2059 gcc_assert (note); 2060 2061 remove_note (insn, note); 2062 } 2063 } 2064 2065 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and 2066 return 1 if it is found. A simple equality test is used to determine if 2067 NODE matches. */ 2068 2069 int 2070 in_expr_list_p (const_rtx listp, const_rtx node) 2071 { 2072 const_rtx x; 2073 2074 for (x = listp; x; x = XEXP (x, 1)) 2075 if (node == XEXP (x, 0)) 2076 return 1; 2077 2078 return 0; 2079 } 2080 2081 /* Search LISTP (an EXPR_LIST) for an entry whose first operand is NODE and 2082 remove that entry from the list if it is found. 2083 2084 A simple equality test is used to determine if NODE matches. */ 2085 2086 void 2087 remove_node_from_expr_list (const_rtx node, rtx *listp) 2088 { 2089 rtx temp = *listp; 2090 rtx prev = NULL_RTX; 2091 2092 while (temp) 2093 { 2094 if (node == XEXP (temp, 0)) 2095 { 2096 /* Splice the node out of the list. */ 2097 if (prev) 2098 XEXP (prev, 1) = XEXP (temp, 1); 2099 else 2100 *listp = XEXP (temp, 1); 2101 2102 return; 2103 } 2104 2105 prev = temp; 2106 temp = XEXP (temp, 1); 2107 } 2108 } 2109 2110 /* Nonzero if X contains any volatile instructions. These are instructions 2111 which may cause unpredictable machine state instructions, and thus no 2112 instructions or register uses should be moved or combined across them. 2113 This includes only volatile asms and UNSPEC_VOLATILE instructions. */ 2114 2115 int 2116 volatile_insn_p (const_rtx x) 2117 { 2118 const RTX_CODE code = GET_CODE (x); 2119 switch (code) 2120 { 2121 case LABEL_REF: 2122 case SYMBOL_REF: 2123 case CONST: 2124 CASE_CONST_ANY: 2125 case CC0: 2126 case PC: 2127 case REG: 2128 case SCRATCH: 2129 case CLOBBER: 2130 case ADDR_VEC: 2131 case ADDR_DIFF_VEC: 2132 case CALL: 2133 case MEM: 2134 return 0; 2135 2136 case UNSPEC_VOLATILE: 2137 return 1; 2138 2139 case ASM_INPUT: 2140 case ASM_OPERANDS: 2141 if (MEM_VOLATILE_P (x)) 2142 return 1; 2143 2144 default: 2145 break; 2146 } 2147 2148 /* Recursively scan the operands of this expression. */ 2149 2150 { 2151 const char *const fmt = GET_RTX_FORMAT (code); 2152 int i; 2153 2154 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2155 { 2156 if (fmt[i] == 'e') 2157 { 2158 if (volatile_insn_p (XEXP (x, i))) 2159 return 1; 2160 } 2161 else if (fmt[i] == 'E') 2162 { 2163 int j; 2164 for (j = 0; j < XVECLEN (x, i); j++) 2165 if (volatile_insn_p (XVECEXP (x, i, j))) 2166 return 1; 2167 } 2168 } 2169 } 2170 return 0; 2171 } 2172 2173 /* Nonzero if X contains any volatile memory references 2174 UNSPEC_VOLATILE operations or volatile ASM_OPERANDS expressions. */ 2175 2176 int 2177 volatile_refs_p (const_rtx x) 2178 { 2179 const RTX_CODE code = GET_CODE (x); 2180 switch (code) 2181 { 2182 case LABEL_REF: 2183 case SYMBOL_REF: 2184 case CONST: 2185 CASE_CONST_ANY: 2186 case CC0: 2187 case PC: 2188 case REG: 2189 case SCRATCH: 2190 case CLOBBER: 2191 case ADDR_VEC: 2192 case ADDR_DIFF_VEC: 2193 return 0; 2194 2195 case UNSPEC_VOLATILE: 2196 return 1; 2197 2198 case MEM: 2199 case ASM_INPUT: 2200 case ASM_OPERANDS: 2201 if (MEM_VOLATILE_P (x)) 2202 return 1; 2203 2204 default: 2205 break; 2206 } 2207 2208 /* Recursively scan the operands of this expression. */ 2209 2210 { 2211 const char *const fmt = GET_RTX_FORMAT (code); 2212 int i; 2213 2214 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2215 { 2216 if (fmt[i] == 'e') 2217 { 2218 if (volatile_refs_p (XEXP (x, i))) 2219 return 1; 2220 } 2221 else if (fmt[i] == 'E') 2222 { 2223 int j; 2224 for (j = 0; j < XVECLEN (x, i); j++) 2225 if (volatile_refs_p (XVECEXP (x, i, j))) 2226 return 1; 2227 } 2228 } 2229 } 2230 return 0; 2231 } 2232 2233 /* Similar to above, except that it also rejects register pre- and post- 2234 incrementing. */ 2235 2236 int 2237 side_effects_p (const_rtx x) 2238 { 2239 const RTX_CODE code = GET_CODE (x); 2240 switch (code) 2241 { 2242 case LABEL_REF: 2243 case SYMBOL_REF: 2244 case CONST: 2245 CASE_CONST_ANY: 2246 case CC0: 2247 case PC: 2248 case REG: 2249 case SCRATCH: 2250 case ADDR_VEC: 2251 case ADDR_DIFF_VEC: 2252 case VAR_LOCATION: 2253 return 0; 2254 2255 case CLOBBER: 2256 /* Reject CLOBBER with a non-VOID mode. These are made by combine.c 2257 when some combination can't be done. If we see one, don't think 2258 that we can simplify the expression. */ 2259 return (GET_MODE (x) != VOIDmode); 2260 2261 case PRE_INC: 2262 case PRE_DEC: 2263 case POST_INC: 2264 case POST_DEC: 2265 case PRE_MODIFY: 2266 case POST_MODIFY: 2267 case CALL: 2268 case UNSPEC_VOLATILE: 2269 return 1; 2270 2271 case MEM: 2272 case ASM_INPUT: 2273 case ASM_OPERANDS: 2274 if (MEM_VOLATILE_P (x)) 2275 return 1; 2276 2277 default: 2278 break; 2279 } 2280 2281 /* Recursively scan the operands of this expression. */ 2282 2283 { 2284 const char *fmt = GET_RTX_FORMAT (code); 2285 int i; 2286 2287 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2288 { 2289 if (fmt[i] == 'e') 2290 { 2291 if (side_effects_p (XEXP (x, i))) 2292 return 1; 2293 } 2294 else if (fmt[i] == 'E') 2295 { 2296 int j; 2297 for (j = 0; j < XVECLEN (x, i); j++) 2298 if (side_effects_p (XVECEXP (x, i, j))) 2299 return 1; 2300 } 2301 } 2302 } 2303 return 0; 2304 } 2305 2306 /* Return nonzero if evaluating rtx X might cause a trap. 2307 FLAGS controls how to consider MEMs. A nonzero means the context 2308 of the access may have changed from the original, such that the 2309 address may have become invalid. */ 2310 2311 int 2312 may_trap_p_1 (const_rtx x, unsigned flags) 2313 { 2314 int i; 2315 enum rtx_code code; 2316 const char *fmt; 2317 2318 /* We make no distinction currently, but this function is part of 2319 the internal target-hooks ABI so we keep the parameter as 2320 "unsigned flags". */ 2321 bool code_changed = flags != 0; 2322 2323 if (x == 0) 2324 return 0; 2325 code = GET_CODE (x); 2326 switch (code) 2327 { 2328 /* Handle these cases quickly. */ 2329 CASE_CONST_ANY: 2330 case SYMBOL_REF: 2331 case LABEL_REF: 2332 case CONST: 2333 case PC: 2334 case CC0: 2335 case REG: 2336 case SCRATCH: 2337 return 0; 2338 2339 case UNSPEC: 2340 return targetm.unspec_may_trap_p (x, flags); 2341 2342 case UNSPEC_VOLATILE: 2343 case ASM_INPUT: 2344 case TRAP_IF: 2345 return 1; 2346 2347 case ASM_OPERANDS: 2348 return MEM_VOLATILE_P (x); 2349 2350 /* Memory ref can trap unless it's a static var or a stack slot. */ 2351 case MEM: 2352 /* Recognize specific pattern of stack checking probes. */ 2353 if (flag_stack_check 2354 && MEM_VOLATILE_P (x) 2355 && XEXP (x, 0) == stack_pointer_rtx) 2356 return 1; 2357 if (/* MEM_NOTRAP_P only relates to the actual position of the memory 2358 reference; moving it out of context such as when moving code 2359 when optimizing, might cause its address to become invalid. */ 2360 code_changed 2361 || !MEM_NOTRAP_P (x)) 2362 { 2363 HOST_WIDE_INT size = MEM_SIZE_KNOWN_P (x) ? MEM_SIZE (x) : 0; 2364 return rtx_addr_can_trap_p_1 (XEXP (x, 0), 0, size, 2365 GET_MODE (x), code_changed); 2366 } 2367 2368 return 0; 2369 2370 /* Division by a non-constant might trap. */ 2371 case DIV: 2372 case MOD: 2373 case UDIV: 2374 case UMOD: 2375 if (HONOR_SNANS (GET_MODE (x))) 2376 return 1; 2377 if (SCALAR_FLOAT_MODE_P (GET_MODE (x))) 2378 return flag_trapping_math; 2379 if (!CONSTANT_P (XEXP (x, 1)) || (XEXP (x, 1) == const0_rtx)) 2380 return 1; 2381 break; 2382 2383 case EXPR_LIST: 2384 /* An EXPR_LIST is used to represent a function call. This 2385 certainly may trap. */ 2386 return 1; 2387 2388 case GE: 2389 case GT: 2390 case LE: 2391 case LT: 2392 case LTGT: 2393 case COMPARE: 2394 /* Some floating point comparisons may trap. */ 2395 if (!flag_trapping_math) 2396 break; 2397 /* ??? There is no machine independent way to check for tests that trap 2398 when COMPARE is used, though many targets do make this distinction. 2399 For instance, sparc uses CCFPE for compares which generate exceptions 2400 and CCFP for compares which do not generate exceptions. */ 2401 if (HONOR_NANS (GET_MODE (x))) 2402 return 1; 2403 /* But often the compare has some CC mode, so check operand 2404 modes as well. */ 2405 if (HONOR_NANS (GET_MODE (XEXP (x, 0))) 2406 || HONOR_NANS (GET_MODE (XEXP (x, 1)))) 2407 return 1; 2408 break; 2409 2410 case EQ: 2411 case NE: 2412 if (HONOR_SNANS (GET_MODE (x))) 2413 return 1; 2414 /* Often comparison is CC mode, so check operand modes. */ 2415 if (HONOR_SNANS (GET_MODE (XEXP (x, 0))) 2416 || HONOR_SNANS (GET_MODE (XEXP (x, 1)))) 2417 return 1; 2418 break; 2419 2420 case FIX: 2421 /* Conversion of floating point might trap. */ 2422 if (flag_trapping_math && HONOR_NANS (GET_MODE (XEXP (x, 0)))) 2423 return 1; 2424 break; 2425 2426 case NEG: 2427 case ABS: 2428 case SUBREG: 2429 /* These operations don't trap even with floating point. */ 2430 break; 2431 2432 default: 2433 /* Any floating arithmetic may trap. */ 2434 if (SCALAR_FLOAT_MODE_P (GET_MODE (x)) && flag_trapping_math) 2435 return 1; 2436 } 2437 2438 fmt = GET_RTX_FORMAT (code); 2439 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2440 { 2441 if (fmt[i] == 'e') 2442 { 2443 if (may_trap_p_1 (XEXP (x, i), flags)) 2444 return 1; 2445 } 2446 else if (fmt[i] == 'E') 2447 { 2448 int j; 2449 for (j = 0; j < XVECLEN (x, i); j++) 2450 if (may_trap_p_1 (XVECEXP (x, i, j), flags)) 2451 return 1; 2452 } 2453 } 2454 return 0; 2455 } 2456 2457 /* Return nonzero if evaluating rtx X might cause a trap. */ 2458 2459 int 2460 may_trap_p (const_rtx x) 2461 { 2462 return may_trap_p_1 (x, 0); 2463 } 2464 2465 /* Same as above, but additionally return nonzero if evaluating rtx X might 2466 cause a fault. We define a fault for the purpose of this function as a 2467 erroneous execution condition that cannot be encountered during the normal 2468 execution of a valid program; the typical example is an unaligned memory 2469 access on a strict alignment machine. The compiler guarantees that it 2470 doesn't generate code that will fault from a valid program, but this 2471 guarantee doesn't mean anything for individual instructions. Consider 2472 the following example: 2473 2474 struct S { int d; union { char *cp; int *ip; }; }; 2475 2476 int foo(struct S *s) 2477 { 2478 if (s->d == 1) 2479 return *s->ip; 2480 else 2481 return *s->cp; 2482 } 2483 2484 on a strict alignment machine. In a valid program, foo will never be 2485 invoked on a structure for which d is equal to 1 and the underlying 2486 unique field of the union not aligned on a 4-byte boundary, but the 2487 expression *s->ip might cause a fault if considered individually. 2488 2489 At the RTL level, potentially problematic expressions will almost always 2490 verify may_trap_p; for example, the above dereference can be emitted as 2491 (mem:SI (reg:P)) and this expression is may_trap_p for a generic register. 2492 However, suppose that foo is inlined in a caller that causes s->cp to 2493 point to a local character variable and guarantees that s->d is not set 2494 to 1; foo may have been effectively translated into pseudo-RTL as: 2495 2496 if ((reg:SI) == 1) 2497 (set (reg:SI) (mem:SI (%fp - 7))) 2498 else 2499 (set (reg:QI) (mem:QI (%fp - 7))) 2500 2501 Now (mem:SI (%fp - 7)) is considered as not may_trap_p since it is a 2502 memory reference to a stack slot, but it will certainly cause a fault 2503 on a strict alignment machine. */ 2504 2505 int 2506 may_trap_or_fault_p (const_rtx x) 2507 { 2508 return may_trap_p_1 (x, 1); 2509 } 2510 2511 /* Return nonzero if X contains a comparison that is not either EQ or NE, 2512 i.e., an inequality. */ 2513 2514 int 2515 inequality_comparisons_p (const_rtx x) 2516 { 2517 const char *fmt; 2518 int len, i; 2519 const enum rtx_code code = GET_CODE (x); 2520 2521 switch (code) 2522 { 2523 case REG: 2524 case SCRATCH: 2525 case PC: 2526 case CC0: 2527 CASE_CONST_ANY: 2528 case CONST: 2529 case LABEL_REF: 2530 case SYMBOL_REF: 2531 return 0; 2532 2533 case LT: 2534 case LTU: 2535 case GT: 2536 case GTU: 2537 case LE: 2538 case LEU: 2539 case GE: 2540 case GEU: 2541 return 1; 2542 2543 default: 2544 break; 2545 } 2546 2547 len = GET_RTX_LENGTH (code); 2548 fmt = GET_RTX_FORMAT (code); 2549 2550 for (i = 0; i < len; i++) 2551 { 2552 if (fmt[i] == 'e') 2553 { 2554 if (inequality_comparisons_p (XEXP (x, i))) 2555 return 1; 2556 } 2557 else if (fmt[i] == 'E') 2558 { 2559 int j; 2560 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2561 if (inequality_comparisons_p (XVECEXP (x, i, j))) 2562 return 1; 2563 } 2564 } 2565 2566 return 0; 2567 } 2568 2569 /* Replace any occurrence of FROM in X with TO. The function does 2570 not enter into CONST_DOUBLE for the replace. 2571 2572 Note that copying is not done so X must not be shared unless all copies 2573 are to be modified. */ 2574 2575 rtx 2576 replace_rtx (rtx x, rtx from, rtx to) 2577 { 2578 int i, j; 2579 const char *fmt; 2580 2581 if (x == from) 2582 return to; 2583 2584 /* Allow this function to make replacements in EXPR_LISTs. */ 2585 if (x == 0) 2586 return 0; 2587 2588 if (GET_CODE (x) == SUBREG) 2589 { 2590 rtx new_rtx = replace_rtx (SUBREG_REG (x), from, to); 2591 2592 if (CONST_INT_P (new_rtx)) 2593 { 2594 x = simplify_subreg (GET_MODE (x), new_rtx, 2595 GET_MODE (SUBREG_REG (x)), 2596 SUBREG_BYTE (x)); 2597 gcc_assert (x); 2598 } 2599 else 2600 SUBREG_REG (x) = new_rtx; 2601 2602 return x; 2603 } 2604 else if (GET_CODE (x) == ZERO_EXTEND) 2605 { 2606 rtx new_rtx = replace_rtx (XEXP (x, 0), from, to); 2607 2608 if (CONST_INT_P (new_rtx)) 2609 { 2610 x = simplify_unary_operation (ZERO_EXTEND, GET_MODE (x), 2611 new_rtx, GET_MODE (XEXP (x, 0))); 2612 gcc_assert (x); 2613 } 2614 else 2615 XEXP (x, 0) = new_rtx; 2616 2617 return x; 2618 } 2619 2620 fmt = GET_RTX_FORMAT (GET_CODE (x)); 2621 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 2622 { 2623 if (fmt[i] == 'e') 2624 XEXP (x, i) = replace_rtx (XEXP (x, i), from, to); 2625 else if (fmt[i] == 'E') 2626 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 2627 XVECEXP (x, i, j) = replace_rtx (XVECEXP (x, i, j), from, to); 2628 } 2629 2630 return x; 2631 } 2632 2633 /* Replace occurrences of the old label in *X with the new one. 2634 DATA is a REPLACE_LABEL_DATA containing the old and new labels. */ 2635 2636 int 2637 replace_label (rtx *x, void *data) 2638 { 2639 rtx l = *x; 2640 rtx old_label = ((replace_label_data *) data)->r1; 2641 rtx new_label = ((replace_label_data *) data)->r2; 2642 bool update_label_nuses = ((replace_label_data *) data)->update_label_nuses; 2643 2644 if (l == NULL_RTX) 2645 return 0; 2646 2647 if (GET_CODE (l) == SYMBOL_REF 2648 && CONSTANT_POOL_ADDRESS_P (l)) 2649 { 2650 rtx c = get_pool_constant (l); 2651 if (rtx_referenced_p (old_label, c)) 2652 { 2653 rtx new_c, new_l; 2654 replace_label_data *d = (replace_label_data *) data; 2655 2656 /* Create a copy of constant C; replace the label inside 2657 but do not update LABEL_NUSES because uses in constant pool 2658 are not counted. */ 2659 new_c = copy_rtx (c); 2660 d->update_label_nuses = false; 2661 for_each_rtx (&new_c, replace_label, data); 2662 d->update_label_nuses = update_label_nuses; 2663 2664 /* Add the new constant NEW_C to constant pool and replace 2665 the old reference to constant by new reference. */ 2666 new_l = XEXP (force_const_mem (get_pool_mode (l), new_c), 0); 2667 *x = replace_rtx (l, l, new_l); 2668 } 2669 return 0; 2670 } 2671 2672 /* If this is a JUMP_INSN, then we also need to fix the JUMP_LABEL 2673 field. This is not handled by for_each_rtx because it doesn't 2674 handle unprinted ('0') fields. */ 2675 if (JUMP_P (l) && JUMP_LABEL (l) == old_label) 2676 JUMP_LABEL (l) = new_label; 2677 2678 if ((GET_CODE (l) == LABEL_REF 2679 || GET_CODE (l) == INSN_LIST) 2680 && XEXP (l, 0) == old_label) 2681 { 2682 XEXP (l, 0) = new_label; 2683 if (update_label_nuses) 2684 { 2685 ++LABEL_NUSES (new_label); 2686 --LABEL_NUSES (old_label); 2687 } 2688 return 0; 2689 } 2690 2691 return 0; 2692 } 2693 2694 /* When *BODY is equal to X or X is directly referenced by *BODY 2695 return nonzero, thus FOR_EACH_RTX stops traversing and returns nonzero 2696 too, otherwise FOR_EACH_RTX continues traversing *BODY. */ 2697 2698 static int 2699 rtx_referenced_p_1 (rtx *body, void *x) 2700 { 2701 rtx y = (rtx) x; 2702 2703 if (*body == NULL_RTX) 2704 return y == NULL_RTX; 2705 2706 /* Return true if a label_ref *BODY refers to label Y. */ 2707 if (GET_CODE (*body) == LABEL_REF && LABEL_P (y)) 2708 return XEXP (*body, 0) == y; 2709 2710 /* If *BODY is a reference to pool constant traverse the constant. */ 2711 if (GET_CODE (*body) == SYMBOL_REF 2712 && CONSTANT_POOL_ADDRESS_P (*body)) 2713 return rtx_referenced_p (y, get_pool_constant (*body)); 2714 2715 /* By default, compare the RTL expressions. */ 2716 return rtx_equal_p (*body, y); 2717 } 2718 2719 /* Return true if X is referenced in BODY. */ 2720 2721 int 2722 rtx_referenced_p (rtx x, rtx body) 2723 { 2724 return for_each_rtx (&body, rtx_referenced_p_1, x); 2725 } 2726 2727 /* If INSN is a tablejump return true and store the label (before jump table) to 2728 *LABELP and the jump table to *TABLEP. LABELP and TABLEP may be NULL. */ 2729 2730 bool 2731 tablejump_p (const_rtx insn, rtx *labelp, rtx *tablep) 2732 { 2733 rtx label, table; 2734 2735 if (!JUMP_P (insn)) 2736 return false; 2737 2738 label = JUMP_LABEL (insn); 2739 if (label != NULL_RTX && !ANY_RETURN_P (label) 2740 && (table = next_active_insn (label)) != NULL_RTX 2741 && JUMP_TABLE_DATA_P (table)) 2742 { 2743 if (labelp) 2744 *labelp = label; 2745 if (tablep) 2746 *tablep = table; 2747 return true; 2748 } 2749 return false; 2750 } 2751 2752 /* A subroutine of computed_jump_p, return 1 if X contains a REG or MEM or 2753 constant that is not in the constant pool and not in the condition 2754 of an IF_THEN_ELSE. */ 2755 2756 static int 2757 computed_jump_p_1 (const_rtx x) 2758 { 2759 const enum rtx_code code = GET_CODE (x); 2760 int i, j; 2761 const char *fmt; 2762 2763 switch (code) 2764 { 2765 case LABEL_REF: 2766 case PC: 2767 return 0; 2768 2769 case CONST: 2770 CASE_CONST_ANY: 2771 case SYMBOL_REF: 2772 case REG: 2773 return 1; 2774 2775 case MEM: 2776 return ! (GET_CODE (XEXP (x, 0)) == SYMBOL_REF 2777 && CONSTANT_POOL_ADDRESS_P (XEXP (x, 0))); 2778 2779 case IF_THEN_ELSE: 2780 return (computed_jump_p_1 (XEXP (x, 1)) 2781 || computed_jump_p_1 (XEXP (x, 2))); 2782 2783 default: 2784 break; 2785 } 2786 2787 fmt = GET_RTX_FORMAT (code); 2788 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 2789 { 2790 if (fmt[i] == 'e' 2791 && computed_jump_p_1 (XEXP (x, i))) 2792 return 1; 2793 2794 else if (fmt[i] == 'E') 2795 for (j = 0; j < XVECLEN (x, i); j++) 2796 if (computed_jump_p_1 (XVECEXP (x, i, j))) 2797 return 1; 2798 } 2799 2800 return 0; 2801 } 2802 2803 /* Return nonzero if INSN is an indirect jump (aka computed jump). 2804 2805 Tablejumps and casesi insns are not considered indirect jumps; 2806 we can recognize them by a (use (label_ref)). */ 2807 2808 int 2809 computed_jump_p (const_rtx insn) 2810 { 2811 int i; 2812 if (JUMP_P (insn)) 2813 { 2814 rtx pat = PATTERN (insn); 2815 2816 /* If we have a JUMP_LABEL set, we're not a computed jump. */ 2817 if (JUMP_LABEL (insn) != NULL) 2818 return 0; 2819 2820 if (GET_CODE (pat) == PARALLEL) 2821 { 2822 int len = XVECLEN (pat, 0); 2823 int has_use_labelref = 0; 2824 2825 for (i = len - 1; i >= 0; i--) 2826 if (GET_CODE (XVECEXP (pat, 0, i)) == USE 2827 && (GET_CODE (XEXP (XVECEXP (pat, 0, i), 0)) 2828 == LABEL_REF)) 2829 has_use_labelref = 1; 2830 2831 if (! has_use_labelref) 2832 for (i = len - 1; i >= 0; i--) 2833 if (GET_CODE (XVECEXP (pat, 0, i)) == SET 2834 && SET_DEST (XVECEXP (pat, 0, i)) == pc_rtx 2835 && computed_jump_p_1 (SET_SRC (XVECEXP (pat, 0, i)))) 2836 return 1; 2837 } 2838 else if (GET_CODE (pat) == SET 2839 && SET_DEST (pat) == pc_rtx 2840 && computed_jump_p_1 (SET_SRC (pat))) 2841 return 1; 2842 } 2843 return 0; 2844 } 2845 2846 /* Optimized loop of for_each_rtx, trying to avoid useless recursive 2847 calls. Processes the subexpressions of EXP and passes them to F. */ 2848 static int 2849 for_each_rtx_1 (rtx exp, int n, rtx_function f, void *data) 2850 { 2851 int result, i, j; 2852 const char *format = GET_RTX_FORMAT (GET_CODE (exp)); 2853 rtx *x; 2854 2855 for (; format[n] != '\0'; n++) 2856 { 2857 switch (format[n]) 2858 { 2859 case 'e': 2860 /* Call F on X. */ 2861 x = &XEXP (exp, n); 2862 result = (*f) (x, data); 2863 if (result == -1) 2864 /* Do not traverse sub-expressions. */ 2865 continue; 2866 else if (result != 0) 2867 /* Stop the traversal. */ 2868 return result; 2869 2870 if (*x == NULL_RTX) 2871 /* There are no sub-expressions. */ 2872 continue; 2873 2874 i = non_rtx_starting_operands[GET_CODE (*x)]; 2875 if (i >= 0) 2876 { 2877 result = for_each_rtx_1 (*x, i, f, data); 2878 if (result != 0) 2879 return result; 2880 } 2881 break; 2882 2883 case 'V': 2884 case 'E': 2885 if (XVEC (exp, n) == 0) 2886 continue; 2887 for (j = 0; j < XVECLEN (exp, n); ++j) 2888 { 2889 /* Call F on X. */ 2890 x = &XVECEXP (exp, n, j); 2891 result = (*f) (x, data); 2892 if (result == -1) 2893 /* Do not traverse sub-expressions. */ 2894 continue; 2895 else if (result != 0) 2896 /* Stop the traversal. */ 2897 return result; 2898 2899 if (*x == NULL_RTX) 2900 /* There are no sub-expressions. */ 2901 continue; 2902 2903 i = non_rtx_starting_operands[GET_CODE (*x)]; 2904 if (i >= 0) 2905 { 2906 result = for_each_rtx_1 (*x, i, f, data); 2907 if (result != 0) 2908 return result; 2909 } 2910 } 2911 break; 2912 2913 default: 2914 /* Nothing to do. */ 2915 break; 2916 } 2917 } 2918 2919 return 0; 2920 } 2921 2922 /* Traverse X via depth-first search, calling F for each 2923 sub-expression (including X itself). F is also passed the DATA. 2924 If F returns -1, do not traverse sub-expressions, but continue 2925 traversing the rest of the tree. If F ever returns any other 2926 nonzero value, stop the traversal, and return the value returned 2927 by F. Otherwise, return 0. This function does not traverse inside 2928 tree structure that contains RTX_EXPRs, or into sub-expressions 2929 whose format code is `0' since it is not known whether or not those 2930 codes are actually RTL. 2931 2932 This routine is very general, and could (should?) be used to 2933 implement many of the other routines in this file. */ 2934 2935 int 2936 for_each_rtx (rtx *x, rtx_function f, void *data) 2937 { 2938 int result; 2939 int i; 2940 2941 /* Call F on X. */ 2942 result = (*f) (x, data); 2943 if (result == -1) 2944 /* Do not traverse sub-expressions. */ 2945 return 0; 2946 else if (result != 0) 2947 /* Stop the traversal. */ 2948 return result; 2949 2950 if (*x == NULL_RTX) 2951 /* There are no sub-expressions. */ 2952 return 0; 2953 2954 i = non_rtx_starting_operands[GET_CODE (*x)]; 2955 if (i < 0) 2956 return 0; 2957 2958 return for_each_rtx_1 (*x, i, f, data); 2959 } 2960 2961 2962 2963 /* Data structure that holds the internal state communicated between 2964 for_each_inc_dec, for_each_inc_dec_find_mem and 2965 for_each_inc_dec_find_inc_dec. */ 2966 2967 struct for_each_inc_dec_ops { 2968 /* The function to be called for each autoinc operation found. */ 2969 for_each_inc_dec_fn fn; 2970 /* The opaque argument to be passed to it. */ 2971 void *arg; 2972 /* The MEM we're visiting, if any. */ 2973 rtx mem; 2974 }; 2975 2976 static int for_each_inc_dec_find_mem (rtx *r, void *d); 2977 2978 /* Find PRE/POST-INC/DEC/MODIFY operations within *R, extract the 2979 operands of the equivalent add insn and pass the result to the 2980 operator specified by *D. */ 2981 2982 static int 2983 for_each_inc_dec_find_inc_dec (rtx *r, void *d) 2984 { 2985 rtx x = *r; 2986 struct for_each_inc_dec_ops *data = (struct for_each_inc_dec_ops *)d; 2987 2988 switch (GET_CODE (x)) 2989 { 2990 case PRE_INC: 2991 case POST_INC: 2992 { 2993 int size = GET_MODE_SIZE (GET_MODE (data->mem)); 2994 rtx r1 = XEXP (x, 0); 2995 rtx c = gen_int_mode (size, GET_MODE (r1)); 2996 return data->fn (data->mem, x, r1, r1, c, data->arg); 2997 } 2998 2999 case PRE_DEC: 3000 case POST_DEC: 3001 { 3002 int size = GET_MODE_SIZE (GET_MODE (data->mem)); 3003 rtx r1 = XEXP (x, 0); 3004 rtx c = gen_int_mode (-size, GET_MODE (r1)); 3005 return data->fn (data->mem, x, r1, r1, c, data->arg); 3006 } 3007 3008 case PRE_MODIFY: 3009 case POST_MODIFY: 3010 { 3011 rtx r1 = XEXP (x, 0); 3012 rtx add = XEXP (x, 1); 3013 return data->fn (data->mem, x, r1, add, NULL, data->arg); 3014 } 3015 3016 case MEM: 3017 { 3018 rtx save = data->mem; 3019 int ret = for_each_inc_dec_find_mem (r, d); 3020 data->mem = save; 3021 return ret; 3022 } 3023 3024 default: 3025 return 0; 3026 } 3027 } 3028 3029 /* If *R is a MEM, find PRE/POST-INC/DEC/MODIFY operations within its 3030 address, extract the operands of the equivalent add insn and pass 3031 the result to the operator specified by *D. */ 3032 3033 static int 3034 for_each_inc_dec_find_mem (rtx *r, void *d) 3035 { 3036 rtx x = *r; 3037 if (x != NULL_RTX && MEM_P (x)) 3038 { 3039 struct for_each_inc_dec_ops *data = (struct for_each_inc_dec_ops *) d; 3040 int result; 3041 3042 data->mem = x; 3043 3044 result = for_each_rtx (&XEXP (x, 0), for_each_inc_dec_find_inc_dec, 3045 data); 3046 if (result) 3047 return result; 3048 3049 return -1; 3050 } 3051 return 0; 3052 } 3053 3054 /* Traverse *X looking for MEMs, and for autoinc operations within 3055 them. For each such autoinc operation found, call FN, passing it 3056 the innermost enclosing MEM, the operation itself, the RTX modified 3057 by the operation, two RTXs (the second may be NULL) that, once 3058 added, represent the value to be held by the modified RTX 3059 afterwards, and ARG. FN is to return -1 to skip looking for other 3060 autoinc operations within the visited operation, 0 to continue the 3061 traversal, or any other value to have it returned to the caller of 3062 for_each_inc_dec. */ 3063 3064 int 3065 for_each_inc_dec (rtx *x, 3066 for_each_inc_dec_fn fn, 3067 void *arg) 3068 { 3069 struct for_each_inc_dec_ops data; 3070 3071 data.fn = fn; 3072 data.arg = arg; 3073 data.mem = NULL; 3074 3075 return for_each_rtx (x, for_each_inc_dec_find_mem, &data); 3076 } 3077 3078 3079 /* Searches X for any reference to REGNO, returning the rtx of the 3080 reference found if any. Otherwise, returns NULL_RTX. */ 3081 3082 rtx 3083 regno_use_in (unsigned int regno, rtx x) 3084 { 3085 const char *fmt; 3086 int i, j; 3087 rtx tem; 3088 3089 if (REG_P (x) && REGNO (x) == regno) 3090 return x; 3091 3092 fmt = GET_RTX_FORMAT (GET_CODE (x)); 3093 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 3094 { 3095 if (fmt[i] == 'e') 3096 { 3097 if ((tem = regno_use_in (regno, XEXP (x, i)))) 3098 return tem; 3099 } 3100 else if (fmt[i] == 'E') 3101 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3102 if ((tem = regno_use_in (regno , XVECEXP (x, i, j)))) 3103 return tem; 3104 } 3105 3106 return NULL_RTX; 3107 } 3108 3109 /* Return a value indicating whether OP, an operand of a commutative 3110 operation, is preferred as the first or second operand. The higher 3111 the value, the stronger the preference for being the first operand. 3112 We use negative values to indicate a preference for the first operand 3113 and positive values for the second operand. */ 3114 3115 int 3116 commutative_operand_precedence (rtx op) 3117 { 3118 enum rtx_code code = GET_CODE (op); 3119 3120 /* Constants always come the second operand. Prefer "nice" constants. */ 3121 if (code == CONST_INT) 3122 return -8; 3123 if (code == CONST_DOUBLE) 3124 return -7; 3125 if (code == CONST_FIXED) 3126 return -7; 3127 op = avoid_constant_pool_reference (op); 3128 code = GET_CODE (op); 3129 3130 switch (GET_RTX_CLASS (code)) 3131 { 3132 case RTX_CONST_OBJ: 3133 if (code == CONST_INT) 3134 return -6; 3135 if (code == CONST_DOUBLE) 3136 return -5; 3137 if (code == CONST_FIXED) 3138 return -5; 3139 return -4; 3140 3141 case RTX_EXTRA: 3142 /* SUBREGs of objects should come second. */ 3143 if (code == SUBREG && OBJECT_P (SUBREG_REG (op))) 3144 return -3; 3145 return 0; 3146 3147 case RTX_OBJ: 3148 /* Complex expressions should be the first, so decrease priority 3149 of objects. Prefer pointer objects over non pointer objects. */ 3150 if ((REG_P (op) && REG_POINTER (op)) 3151 || (MEM_P (op) && MEM_POINTER (op))) 3152 return -1; 3153 return -2; 3154 3155 case RTX_COMM_ARITH: 3156 /* Prefer operands that are themselves commutative to be first. 3157 This helps to make things linear. In particular, 3158 (and (and (reg) (reg)) (not (reg))) is canonical. */ 3159 return 4; 3160 3161 case RTX_BIN_ARITH: 3162 /* If only one operand is a binary expression, it will be the first 3163 operand. In particular, (plus (minus (reg) (reg)) (neg (reg))) 3164 is canonical, although it will usually be further simplified. */ 3165 return 2; 3166 3167 case RTX_UNARY: 3168 /* Then prefer NEG and NOT. */ 3169 if (code == NEG || code == NOT) 3170 return 1; 3171 3172 default: 3173 return 0; 3174 } 3175 } 3176 3177 /* Return 1 iff it is necessary to swap operands of commutative operation 3178 in order to canonicalize expression. */ 3179 3180 bool 3181 swap_commutative_operands_p (rtx x, rtx y) 3182 { 3183 return (commutative_operand_precedence (x) 3184 < commutative_operand_precedence (y)); 3185 } 3186 3187 /* Return 1 if X is an autoincrement side effect and the register is 3188 not the stack pointer. */ 3189 int 3190 auto_inc_p (const_rtx x) 3191 { 3192 switch (GET_CODE (x)) 3193 { 3194 case PRE_INC: 3195 case POST_INC: 3196 case PRE_DEC: 3197 case POST_DEC: 3198 case PRE_MODIFY: 3199 case POST_MODIFY: 3200 /* There are no REG_INC notes for SP. */ 3201 if (XEXP (x, 0) != stack_pointer_rtx) 3202 return 1; 3203 default: 3204 break; 3205 } 3206 return 0; 3207 } 3208 3209 /* Return nonzero if IN contains a piece of rtl that has the address LOC. */ 3210 int 3211 loc_mentioned_in_p (rtx *loc, const_rtx in) 3212 { 3213 enum rtx_code code; 3214 const char *fmt; 3215 int i, j; 3216 3217 if (!in) 3218 return 0; 3219 3220 code = GET_CODE (in); 3221 fmt = GET_RTX_FORMAT (code); 3222 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3223 { 3224 if (fmt[i] == 'e') 3225 { 3226 if (loc == &XEXP (in, i) || loc_mentioned_in_p (loc, XEXP (in, i))) 3227 return 1; 3228 } 3229 else if (fmt[i] == 'E') 3230 for (j = XVECLEN (in, i) - 1; j >= 0; j--) 3231 if (loc == &XVECEXP (in, i, j) 3232 || loc_mentioned_in_p (loc, XVECEXP (in, i, j))) 3233 return 1; 3234 } 3235 return 0; 3236 } 3237 3238 /* Helper function for subreg_lsb. Given a subreg's OUTER_MODE, INNER_MODE, 3239 and SUBREG_BYTE, return the bit offset where the subreg begins 3240 (counting from the least significant bit of the operand). */ 3241 3242 unsigned int 3243 subreg_lsb_1 (enum machine_mode outer_mode, 3244 enum machine_mode inner_mode, 3245 unsigned int subreg_byte) 3246 { 3247 unsigned int bitpos; 3248 unsigned int byte; 3249 unsigned int word; 3250 3251 /* A paradoxical subreg begins at bit position 0. */ 3252 if (GET_MODE_PRECISION (outer_mode) > GET_MODE_PRECISION (inner_mode)) 3253 return 0; 3254 3255 if (WORDS_BIG_ENDIAN != BYTES_BIG_ENDIAN) 3256 /* If the subreg crosses a word boundary ensure that 3257 it also begins and ends on a word boundary. */ 3258 gcc_assert (!((subreg_byte % UNITS_PER_WORD 3259 + GET_MODE_SIZE (outer_mode)) > UNITS_PER_WORD 3260 && (subreg_byte % UNITS_PER_WORD 3261 || GET_MODE_SIZE (outer_mode) % UNITS_PER_WORD))); 3262 3263 if (WORDS_BIG_ENDIAN) 3264 word = (GET_MODE_SIZE (inner_mode) 3265 - (subreg_byte + GET_MODE_SIZE (outer_mode))) / UNITS_PER_WORD; 3266 else 3267 word = subreg_byte / UNITS_PER_WORD; 3268 bitpos = word * BITS_PER_WORD; 3269 3270 if (BYTES_BIG_ENDIAN) 3271 byte = (GET_MODE_SIZE (inner_mode) 3272 - (subreg_byte + GET_MODE_SIZE (outer_mode))) % UNITS_PER_WORD; 3273 else 3274 byte = subreg_byte % UNITS_PER_WORD; 3275 bitpos += byte * BITS_PER_UNIT; 3276 3277 return bitpos; 3278 } 3279 3280 /* Given a subreg X, return the bit offset where the subreg begins 3281 (counting from the least significant bit of the reg). */ 3282 3283 unsigned int 3284 subreg_lsb (const_rtx x) 3285 { 3286 return subreg_lsb_1 (GET_MODE (x), GET_MODE (SUBREG_REG (x)), 3287 SUBREG_BYTE (x)); 3288 } 3289 3290 /* Fill in information about a subreg of a hard register. 3291 xregno - A regno of an inner hard subreg_reg (or what will become one). 3292 xmode - The mode of xregno. 3293 offset - The byte offset. 3294 ymode - The mode of a top level SUBREG (or what may become one). 3295 info - Pointer to structure to fill in. */ 3296 void 3297 subreg_get_info (unsigned int xregno, enum machine_mode xmode, 3298 unsigned int offset, enum machine_mode ymode, 3299 struct subreg_info *info) 3300 { 3301 int nregs_xmode, nregs_ymode; 3302 int mode_multiple, nregs_multiple; 3303 int offset_adj, y_offset, y_offset_adj; 3304 int regsize_xmode, regsize_ymode; 3305 bool rknown; 3306 3307 gcc_assert (xregno < FIRST_PSEUDO_REGISTER); 3308 3309 rknown = false; 3310 3311 /* If there are holes in a non-scalar mode in registers, we expect 3312 that it is made up of its units concatenated together. */ 3313 if (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode)) 3314 { 3315 enum machine_mode xmode_unit; 3316 3317 nregs_xmode = HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode); 3318 if (GET_MODE_INNER (xmode) == VOIDmode) 3319 xmode_unit = xmode; 3320 else 3321 xmode_unit = GET_MODE_INNER (xmode); 3322 gcc_assert (HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode_unit)); 3323 gcc_assert (nregs_xmode 3324 == (GET_MODE_NUNITS (xmode) 3325 * HARD_REGNO_NREGS_WITH_PADDING (xregno, xmode_unit))); 3326 gcc_assert (hard_regno_nregs[xregno][xmode] 3327 == (hard_regno_nregs[xregno][xmode_unit] 3328 * GET_MODE_NUNITS (xmode))); 3329 3330 /* You can only ask for a SUBREG of a value with holes in the middle 3331 if you don't cross the holes. (Such a SUBREG should be done by 3332 picking a different register class, or doing it in memory if 3333 necessary.) An example of a value with holes is XCmode on 32-bit 3334 x86 with -m128bit-long-double; it's represented in 6 32-bit registers, 3335 3 for each part, but in memory it's two 128-bit parts. 3336 Padding is assumed to be at the end (not necessarily the 'high part') 3337 of each unit. */ 3338 if ((offset / GET_MODE_SIZE (xmode_unit) + 1 3339 < GET_MODE_NUNITS (xmode)) 3340 && (offset / GET_MODE_SIZE (xmode_unit) 3341 != ((offset + GET_MODE_SIZE (ymode) - 1) 3342 / GET_MODE_SIZE (xmode_unit)))) 3343 { 3344 info->representable_p = false; 3345 rknown = true; 3346 } 3347 } 3348 else 3349 nregs_xmode = hard_regno_nregs[xregno][xmode]; 3350 3351 nregs_ymode = hard_regno_nregs[xregno][ymode]; 3352 3353 /* Paradoxical subregs are otherwise valid. */ 3354 if (!rknown 3355 && offset == 0 3356 && GET_MODE_PRECISION (ymode) > GET_MODE_PRECISION (xmode)) 3357 { 3358 info->representable_p = true; 3359 /* If this is a big endian paradoxical subreg, which uses more 3360 actual hard registers than the original register, we must 3361 return a negative offset so that we find the proper highpart 3362 of the register. */ 3363 if (GET_MODE_SIZE (ymode) > UNITS_PER_WORD 3364 ? REG_WORDS_BIG_ENDIAN : BYTES_BIG_ENDIAN) 3365 info->offset = nregs_xmode - nregs_ymode; 3366 else 3367 info->offset = 0; 3368 info->nregs = nregs_ymode; 3369 return; 3370 } 3371 3372 /* If registers store different numbers of bits in the different 3373 modes, we cannot generally form this subreg. */ 3374 if (!HARD_REGNO_NREGS_HAS_PADDING (xregno, xmode) 3375 && !HARD_REGNO_NREGS_HAS_PADDING (xregno, ymode) 3376 && (GET_MODE_SIZE (xmode) % nregs_xmode) == 0 3377 && (GET_MODE_SIZE (ymode) % nregs_ymode) == 0) 3378 { 3379 regsize_xmode = GET_MODE_SIZE (xmode) / nregs_xmode; 3380 regsize_ymode = GET_MODE_SIZE (ymode) / nregs_ymode; 3381 if (!rknown && regsize_xmode > regsize_ymode && nregs_ymode > 1) 3382 { 3383 info->representable_p = false; 3384 info->nregs 3385 = (GET_MODE_SIZE (ymode) + regsize_xmode - 1) / regsize_xmode; 3386 info->offset = offset / regsize_xmode; 3387 return; 3388 } 3389 if (!rknown && regsize_ymode > regsize_xmode && nregs_xmode > 1) 3390 { 3391 info->representable_p = false; 3392 info->nregs 3393 = (GET_MODE_SIZE (ymode) + regsize_xmode - 1) / regsize_xmode; 3394 info->offset = offset / regsize_xmode; 3395 return; 3396 } 3397 } 3398 3399 /* Lowpart subregs are otherwise valid. */ 3400 if (!rknown && offset == subreg_lowpart_offset (ymode, xmode)) 3401 { 3402 info->representable_p = true; 3403 rknown = true; 3404 3405 if (offset == 0 || nregs_xmode == nregs_ymode) 3406 { 3407 info->offset = 0; 3408 info->nregs = nregs_ymode; 3409 return; 3410 } 3411 } 3412 3413 /* This should always pass, otherwise we don't know how to verify 3414 the constraint. These conditions may be relaxed but 3415 subreg_regno_offset would need to be redesigned. */ 3416 gcc_assert ((GET_MODE_SIZE (xmode) % GET_MODE_SIZE (ymode)) == 0); 3417 gcc_assert ((nregs_xmode % nregs_ymode) == 0); 3418 3419 if (WORDS_BIG_ENDIAN != REG_WORDS_BIG_ENDIAN 3420 && GET_MODE_SIZE (xmode) > UNITS_PER_WORD) 3421 { 3422 HOST_WIDE_INT xsize = GET_MODE_SIZE (xmode); 3423 HOST_WIDE_INT ysize = GET_MODE_SIZE (ymode); 3424 HOST_WIDE_INT off_low = offset & (ysize - 1); 3425 HOST_WIDE_INT off_high = offset & ~(ysize - 1); 3426 offset = (xsize - ysize - off_high) | off_low; 3427 } 3428 /* The XMODE value can be seen as a vector of NREGS_XMODE 3429 values. The subreg must represent a lowpart of given field. 3430 Compute what field it is. */ 3431 offset_adj = offset; 3432 offset_adj -= subreg_lowpart_offset (ymode, 3433 mode_for_size (GET_MODE_BITSIZE (xmode) 3434 / nregs_xmode, 3435 MODE_INT, 0)); 3436 3437 /* Size of ymode must not be greater than the size of xmode. */ 3438 mode_multiple = GET_MODE_SIZE (xmode) / GET_MODE_SIZE (ymode); 3439 gcc_assert (mode_multiple != 0); 3440 3441 y_offset = offset / GET_MODE_SIZE (ymode); 3442 y_offset_adj = offset_adj / GET_MODE_SIZE (ymode); 3443 nregs_multiple = nregs_xmode / nregs_ymode; 3444 3445 gcc_assert ((offset_adj % GET_MODE_SIZE (ymode)) == 0); 3446 gcc_assert ((mode_multiple % nregs_multiple) == 0); 3447 3448 if (!rknown) 3449 { 3450 info->representable_p = (!(y_offset_adj % (mode_multiple / nregs_multiple))); 3451 rknown = true; 3452 } 3453 info->offset = (y_offset / (mode_multiple / nregs_multiple)) * nregs_ymode; 3454 info->nregs = nregs_ymode; 3455 } 3456 3457 /* This function returns the regno offset of a subreg expression. 3458 xregno - A regno of an inner hard subreg_reg (or what will become one). 3459 xmode - The mode of xregno. 3460 offset - The byte offset. 3461 ymode - The mode of a top level SUBREG (or what may become one). 3462 RETURN - The regno offset which would be used. */ 3463 unsigned int 3464 subreg_regno_offset (unsigned int xregno, enum machine_mode xmode, 3465 unsigned int offset, enum machine_mode ymode) 3466 { 3467 struct subreg_info info; 3468 subreg_get_info (xregno, xmode, offset, ymode, &info); 3469 return info.offset; 3470 } 3471 3472 /* This function returns true when the offset is representable via 3473 subreg_offset in the given regno. 3474 xregno - A regno of an inner hard subreg_reg (or what will become one). 3475 xmode - The mode of xregno. 3476 offset - The byte offset. 3477 ymode - The mode of a top level SUBREG (or what may become one). 3478 RETURN - Whether the offset is representable. */ 3479 bool 3480 subreg_offset_representable_p (unsigned int xregno, enum machine_mode xmode, 3481 unsigned int offset, enum machine_mode ymode) 3482 { 3483 struct subreg_info info; 3484 subreg_get_info (xregno, xmode, offset, ymode, &info); 3485 return info.representable_p; 3486 } 3487 3488 /* Return the number of a YMODE register to which 3489 3490 (subreg:YMODE (reg:XMODE XREGNO) OFFSET) 3491 3492 can be simplified. Return -1 if the subreg can't be simplified. 3493 3494 XREGNO is a hard register number. */ 3495 3496 int 3497 simplify_subreg_regno (unsigned int xregno, enum machine_mode xmode, 3498 unsigned int offset, enum machine_mode ymode) 3499 { 3500 struct subreg_info info; 3501 unsigned int yregno; 3502 3503 #ifdef CANNOT_CHANGE_MODE_CLASS 3504 /* Give the backend a chance to disallow the mode change. */ 3505 if (GET_MODE_CLASS (xmode) != MODE_COMPLEX_INT 3506 && GET_MODE_CLASS (xmode) != MODE_COMPLEX_FLOAT 3507 && REG_CANNOT_CHANGE_MODE_P (xregno, xmode, ymode) 3508 /* We can use mode change in LRA for some transformations. */ 3509 && ! lra_in_progress) 3510 return -1; 3511 #endif 3512 3513 /* We shouldn't simplify stack-related registers. */ 3514 if ((!reload_completed || frame_pointer_needed) 3515 && xregno == FRAME_POINTER_REGNUM) 3516 return -1; 3517 3518 if (FRAME_POINTER_REGNUM != ARG_POINTER_REGNUM 3519 && xregno == ARG_POINTER_REGNUM) 3520 return -1; 3521 3522 if (xregno == STACK_POINTER_REGNUM 3523 /* We should convert hard stack register in LRA if it is 3524 possible. */ 3525 && ! lra_in_progress) 3526 return -1; 3527 3528 /* Try to get the register offset. */ 3529 subreg_get_info (xregno, xmode, offset, ymode, &info); 3530 if (!info.representable_p) 3531 return -1; 3532 3533 /* Make sure that the offsetted register value is in range. */ 3534 yregno = xregno + info.offset; 3535 if (!HARD_REGISTER_NUM_P (yregno)) 3536 return -1; 3537 3538 /* See whether (reg:YMODE YREGNO) is valid. 3539 3540 ??? We allow invalid registers if (reg:XMODE XREGNO) is also invalid. 3541 This is a kludge to work around how complex FP arguments are passed 3542 on IA-64 and should be fixed. See PR target/49226. */ 3543 if (!HARD_REGNO_MODE_OK (yregno, ymode) 3544 && HARD_REGNO_MODE_OK (xregno, xmode)) 3545 return -1; 3546 3547 return (int) yregno; 3548 } 3549 3550 /* Return the final regno that a subreg expression refers to. */ 3551 unsigned int 3552 subreg_regno (const_rtx x) 3553 { 3554 unsigned int ret; 3555 rtx subreg = SUBREG_REG (x); 3556 int regno = REGNO (subreg); 3557 3558 ret = regno + subreg_regno_offset (regno, 3559 GET_MODE (subreg), 3560 SUBREG_BYTE (x), 3561 GET_MODE (x)); 3562 return ret; 3563 3564 } 3565 3566 /* Return the number of registers that a subreg expression refers 3567 to. */ 3568 unsigned int 3569 subreg_nregs (const_rtx x) 3570 { 3571 return subreg_nregs_with_regno (REGNO (SUBREG_REG (x)), x); 3572 } 3573 3574 /* Return the number of registers that a subreg REG with REGNO 3575 expression refers to. This is a copy of the rtlanal.c:subreg_nregs 3576 changed so that the regno can be passed in. */ 3577 3578 unsigned int 3579 subreg_nregs_with_regno (unsigned int regno, const_rtx x) 3580 { 3581 struct subreg_info info; 3582 rtx subreg = SUBREG_REG (x); 3583 3584 subreg_get_info (regno, GET_MODE (subreg), SUBREG_BYTE (x), GET_MODE (x), 3585 &info); 3586 return info.nregs; 3587 } 3588 3589 3590 struct parms_set_data 3591 { 3592 int nregs; 3593 HARD_REG_SET regs; 3594 }; 3595 3596 /* Helper function for noticing stores to parameter registers. */ 3597 static void 3598 parms_set (rtx x, const_rtx pat ATTRIBUTE_UNUSED, void *data) 3599 { 3600 struct parms_set_data *const d = (struct parms_set_data *) data; 3601 if (REG_P (x) && REGNO (x) < FIRST_PSEUDO_REGISTER 3602 && TEST_HARD_REG_BIT (d->regs, REGNO (x))) 3603 { 3604 CLEAR_HARD_REG_BIT (d->regs, REGNO (x)); 3605 d->nregs--; 3606 } 3607 } 3608 3609 /* Look backward for first parameter to be loaded. 3610 Note that loads of all parameters will not necessarily be 3611 found if CSE has eliminated some of them (e.g., an argument 3612 to the outer function is passed down as a parameter). 3613 Do not skip BOUNDARY. */ 3614 rtx 3615 find_first_parameter_load (rtx call_insn, rtx boundary) 3616 { 3617 struct parms_set_data parm; 3618 rtx p, before, first_set; 3619 3620 /* Since different machines initialize their parameter registers 3621 in different orders, assume nothing. Collect the set of all 3622 parameter registers. */ 3623 CLEAR_HARD_REG_SET (parm.regs); 3624 parm.nregs = 0; 3625 for (p = CALL_INSN_FUNCTION_USAGE (call_insn); p; p = XEXP (p, 1)) 3626 if (GET_CODE (XEXP (p, 0)) == USE 3627 && REG_P (XEXP (XEXP (p, 0), 0))) 3628 { 3629 gcc_assert (REGNO (XEXP (XEXP (p, 0), 0)) < FIRST_PSEUDO_REGISTER); 3630 3631 /* We only care about registers which can hold function 3632 arguments. */ 3633 if (!FUNCTION_ARG_REGNO_P (REGNO (XEXP (XEXP (p, 0), 0)))) 3634 continue; 3635 3636 SET_HARD_REG_BIT (parm.regs, REGNO (XEXP (XEXP (p, 0), 0))); 3637 parm.nregs++; 3638 } 3639 before = call_insn; 3640 first_set = call_insn; 3641 3642 /* Search backward for the first set of a register in this set. */ 3643 while (parm.nregs && before != boundary) 3644 { 3645 before = PREV_INSN (before); 3646 3647 /* It is possible that some loads got CSEed from one call to 3648 another. Stop in that case. */ 3649 if (CALL_P (before)) 3650 break; 3651 3652 /* Our caller needs either ensure that we will find all sets 3653 (in case code has not been optimized yet), or take care 3654 for possible labels in a way by setting boundary to preceding 3655 CODE_LABEL. */ 3656 if (LABEL_P (before)) 3657 { 3658 gcc_assert (before == boundary); 3659 break; 3660 } 3661 3662 if (INSN_P (before)) 3663 { 3664 int nregs_old = parm.nregs; 3665 note_stores (PATTERN (before), parms_set, &parm); 3666 /* If we found something that did not set a parameter reg, 3667 we're done. Do not keep going, as that might result 3668 in hoisting an insn before the setting of a pseudo 3669 that is used by the hoisted insn. */ 3670 if (nregs_old != parm.nregs) 3671 first_set = before; 3672 else 3673 break; 3674 } 3675 } 3676 return first_set; 3677 } 3678 3679 /* Return true if we should avoid inserting code between INSN and preceding 3680 call instruction. */ 3681 3682 bool 3683 keep_with_call_p (const_rtx insn) 3684 { 3685 rtx set; 3686 3687 if (INSN_P (insn) && (set = single_set (insn)) != NULL) 3688 { 3689 if (REG_P (SET_DEST (set)) 3690 && REGNO (SET_DEST (set)) < FIRST_PSEUDO_REGISTER 3691 && fixed_regs[REGNO (SET_DEST (set))] 3692 && general_operand (SET_SRC (set), VOIDmode)) 3693 return true; 3694 if (REG_P (SET_SRC (set)) 3695 && targetm.calls.function_value_regno_p (REGNO (SET_SRC (set))) 3696 && REG_P (SET_DEST (set)) 3697 && REGNO (SET_DEST (set)) >= FIRST_PSEUDO_REGISTER) 3698 return true; 3699 /* There may be a stack pop just after the call and before the store 3700 of the return register. Search for the actual store when deciding 3701 if we can break or not. */ 3702 if (SET_DEST (set) == stack_pointer_rtx) 3703 { 3704 /* This CONST_CAST is okay because next_nonnote_insn just 3705 returns its argument and we assign it to a const_rtx 3706 variable. */ 3707 const_rtx i2 = next_nonnote_insn (CONST_CAST_RTX(insn)); 3708 if (i2 && keep_with_call_p (i2)) 3709 return true; 3710 } 3711 } 3712 return false; 3713 } 3714 3715 /* Return true if LABEL is a target of JUMP_INSN. This applies only 3716 to non-complex jumps. That is, direct unconditional, conditional, 3717 and tablejumps, but not computed jumps or returns. It also does 3718 not apply to the fallthru case of a conditional jump. */ 3719 3720 bool 3721 label_is_jump_target_p (const_rtx label, const_rtx jump_insn) 3722 { 3723 rtx tmp = JUMP_LABEL (jump_insn); 3724 3725 if (label == tmp) 3726 return true; 3727 3728 if (tablejump_p (jump_insn, NULL, &tmp)) 3729 { 3730 rtvec vec = XVEC (PATTERN (tmp), 3731 GET_CODE (PATTERN (tmp)) == ADDR_DIFF_VEC); 3732 int i, veclen = GET_NUM_ELEM (vec); 3733 3734 for (i = 0; i < veclen; ++i) 3735 if (XEXP (RTVEC_ELT (vec, i), 0) == label) 3736 return true; 3737 } 3738 3739 if (find_reg_note (jump_insn, REG_LABEL_TARGET, label)) 3740 return true; 3741 3742 return false; 3743 } 3744 3745 3746 /* Return an estimate of the cost of computing rtx X. 3747 One use is in cse, to decide which expression to keep in the hash table. 3748 Another is in rtl generation, to pick the cheapest way to multiply. 3749 Other uses like the latter are expected in the future. 3750 3751 X appears as operand OPNO in an expression with code OUTER_CODE. 3752 SPEED specifies whether costs optimized for speed or size should 3753 be returned. */ 3754 3755 int 3756 rtx_cost (rtx x, enum rtx_code outer_code, int opno, bool speed) 3757 { 3758 int i, j; 3759 enum rtx_code code; 3760 const char *fmt; 3761 int total; 3762 int factor; 3763 3764 if (x == 0) 3765 return 0; 3766 3767 /* A size N times larger than UNITS_PER_WORD likely needs N times as 3768 many insns, taking N times as long. */ 3769 factor = GET_MODE_SIZE (GET_MODE (x)) / UNITS_PER_WORD; 3770 if (factor == 0) 3771 factor = 1; 3772 3773 /* Compute the default costs of certain things. 3774 Note that targetm.rtx_costs can override the defaults. */ 3775 3776 code = GET_CODE (x); 3777 switch (code) 3778 { 3779 case MULT: 3780 /* Multiplication has time-complexity O(N*N), where N is the 3781 number of units (translated from digits) when using 3782 schoolbook long multiplication. */ 3783 total = factor * factor * COSTS_N_INSNS (5); 3784 break; 3785 case DIV: 3786 case UDIV: 3787 case MOD: 3788 case UMOD: 3789 /* Similarly, complexity for schoolbook long division. */ 3790 total = factor * factor * COSTS_N_INSNS (7); 3791 break; 3792 case USE: 3793 /* Used in combine.c as a marker. */ 3794 total = 0; 3795 break; 3796 case SET: 3797 /* A SET doesn't have a mode, so let's look at the SET_DEST to get 3798 the mode for the factor. */ 3799 factor = GET_MODE_SIZE (GET_MODE (SET_DEST (x))) / UNITS_PER_WORD; 3800 if (factor == 0) 3801 factor = 1; 3802 /* Pass through. */ 3803 default: 3804 total = factor * COSTS_N_INSNS (1); 3805 } 3806 3807 switch (code) 3808 { 3809 case REG: 3810 return 0; 3811 3812 case SUBREG: 3813 total = 0; 3814 /* If we can't tie these modes, make this expensive. The larger 3815 the mode, the more expensive it is. */ 3816 if (! MODES_TIEABLE_P (GET_MODE (x), GET_MODE (SUBREG_REG (x)))) 3817 return COSTS_N_INSNS (2 + factor); 3818 break; 3819 3820 default: 3821 if (targetm.rtx_costs (x, code, outer_code, opno, &total, speed)) 3822 return total; 3823 break; 3824 } 3825 3826 /* Sum the costs of the sub-rtx's, plus cost of this operation, 3827 which is already in total. */ 3828 3829 fmt = GET_RTX_FORMAT (code); 3830 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3831 if (fmt[i] == 'e') 3832 total += rtx_cost (XEXP (x, i), code, i, speed); 3833 else if (fmt[i] == 'E') 3834 for (j = 0; j < XVECLEN (x, i); j++) 3835 total += rtx_cost (XVECEXP (x, i, j), code, i, speed); 3836 3837 return total; 3838 } 3839 3840 /* Fill in the structure C with information about both speed and size rtx 3841 costs for X, which is operand OPNO in an expression with code OUTER. */ 3842 3843 void 3844 get_full_rtx_cost (rtx x, enum rtx_code outer, int opno, 3845 struct full_rtx_costs *c) 3846 { 3847 c->speed = rtx_cost (x, outer, opno, true); 3848 c->size = rtx_cost (x, outer, opno, false); 3849 } 3850 3851 3852 /* Return cost of address expression X. 3853 Expect that X is properly formed address reference. 3854 3855 SPEED parameter specify whether costs optimized for speed or size should 3856 be returned. */ 3857 3858 int 3859 address_cost (rtx x, enum machine_mode mode, addr_space_t as, bool speed) 3860 { 3861 /* We may be asked for cost of various unusual addresses, such as operands 3862 of push instruction. It is not worthwhile to complicate writing 3863 of the target hook by such cases. */ 3864 3865 if (!memory_address_addr_space_p (mode, x, as)) 3866 return 1000; 3867 3868 return targetm.address_cost (x, mode, as, speed); 3869 } 3870 3871 /* If the target doesn't override, compute the cost as with arithmetic. */ 3872 3873 int 3874 default_address_cost (rtx x, enum machine_mode, addr_space_t, bool speed) 3875 { 3876 return rtx_cost (x, MEM, 0, speed); 3877 } 3878 3879 3880 unsigned HOST_WIDE_INT 3881 nonzero_bits (const_rtx x, enum machine_mode mode) 3882 { 3883 return cached_nonzero_bits (x, mode, NULL_RTX, VOIDmode, 0); 3884 } 3885 3886 unsigned int 3887 num_sign_bit_copies (const_rtx x, enum machine_mode mode) 3888 { 3889 return cached_num_sign_bit_copies (x, mode, NULL_RTX, VOIDmode, 0); 3890 } 3891 3892 /* The function cached_nonzero_bits is a wrapper around nonzero_bits1. 3893 It avoids exponential behavior in nonzero_bits1 when X has 3894 identical subexpressions on the first or the second level. */ 3895 3896 static unsigned HOST_WIDE_INT 3897 cached_nonzero_bits (const_rtx x, enum machine_mode mode, const_rtx known_x, 3898 enum machine_mode known_mode, 3899 unsigned HOST_WIDE_INT known_ret) 3900 { 3901 if (x == known_x && mode == known_mode) 3902 return known_ret; 3903 3904 /* Try to find identical subexpressions. If found call 3905 nonzero_bits1 on X with the subexpressions as KNOWN_X and the 3906 precomputed value for the subexpression as KNOWN_RET. */ 3907 3908 if (ARITHMETIC_P (x)) 3909 { 3910 rtx x0 = XEXP (x, 0); 3911 rtx x1 = XEXP (x, 1); 3912 3913 /* Check the first level. */ 3914 if (x0 == x1) 3915 return nonzero_bits1 (x, mode, x0, mode, 3916 cached_nonzero_bits (x0, mode, known_x, 3917 known_mode, known_ret)); 3918 3919 /* Check the second level. */ 3920 if (ARITHMETIC_P (x0) 3921 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 3922 return nonzero_bits1 (x, mode, x1, mode, 3923 cached_nonzero_bits (x1, mode, known_x, 3924 known_mode, known_ret)); 3925 3926 if (ARITHMETIC_P (x1) 3927 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 3928 return nonzero_bits1 (x, mode, x0, mode, 3929 cached_nonzero_bits (x0, mode, known_x, 3930 known_mode, known_ret)); 3931 } 3932 3933 return nonzero_bits1 (x, mode, known_x, known_mode, known_ret); 3934 } 3935 3936 /* We let num_sign_bit_copies recur into nonzero_bits as that is useful. 3937 We don't let nonzero_bits recur into num_sign_bit_copies, because that 3938 is less useful. We can't allow both, because that results in exponential 3939 run time recursion. There is a nullstone testcase that triggered 3940 this. This macro avoids accidental uses of num_sign_bit_copies. */ 3941 #define cached_num_sign_bit_copies sorry_i_am_preventing_exponential_behavior 3942 3943 /* Given an expression, X, compute which bits in X can be nonzero. 3944 We don't care about bits outside of those defined in MODE. 3945 3946 For most X this is simply GET_MODE_MASK (GET_MODE (MODE)), but if X is 3947 an arithmetic operation, we can do better. */ 3948 3949 static unsigned HOST_WIDE_INT 3950 nonzero_bits1 (const_rtx x, enum machine_mode mode, const_rtx known_x, 3951 enum machine_mode known_mode, 3952 unsigned HOST_WIDE_INT known_ret) 3953 { 3954 unsigned HOST_WIDE_INT nonzero = GET_MODE_MASK (mode); 3955 unsigned HOST_WIDE_INT inner_nz; 3956 enum rtx_code code; 3957 enum machine_mode inner_mode; 3958 unsigned int mode_width = GET_MODE_PRECISION (mode); 3959 3960 /* For floating-point and vector values, assume all bits are needed. */ 3961 if (FLOAT_MODE_P (GET_MODE (x)) || FLOAT_MODE_P (mode) 3962 || VECTOR_MODE_P (GET_MODE (x)) || VECTOR_MODE_P (mode)) 3963 return nonzero; 3964 3965 /* If X is wider than MODE, use its mode instead. */ 3966 if (GET_MODE_PRECISION (GET_MODE (x)) > mode_width) 3967 { 3968 mode = GET_MODE (x); 3969 nonzero = GET_MODE_MASK (mode); 3970 mode_width = GET_MODE_PRECISION (mode); 3971 } 3972 3973 if (mode_width > HOST_BITS_PER_WIDE_INT) 3974 /* Our only callers in this case look for single bit values. So 3975 just return the mode mask. Those tests will then be false. */ 3976 return nonzero; 3977 3978 #ifndef WORD_REGISTER_OPERATIONS 3979 /* If MODE is wider than X, but both are a single word for both the host 3980 and target machines, we can compute this from which bits of the 3981 object might be nonzero in its own mode, taking into account the fact 3982 that on many CISC machines, accessing an object in a wider mode 3983 causes the high-order bits to become undefined. So they are 3984 not known to be zero. */ 3985 3986 if (GET_MODE (x) != VOIDmode && GET_MODE (x) != mode 3987 && GET_MODE_PRECISION (GET_MODE (x)) <= BITS_PER_WORD 3988 && GET_MODE_PRECISION (GET_MODE (x)) <= HOST_BITS_PER_WIDE_INT 3989 && GET_MODE_PRECISION (mode) > GET_MODE_PRECISION (GET_MODE (x))) 3990 { 3991 nonzero &= cached_nonzero_bits (x, GET_MODE (x), 3992 known_x, known_mode, known_ret); 3993 nonzero |= GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x)); 3994 return nonzero; 3995 } 3996 #endif 3997 3998 code = GET_CODE (x); 3999 switch (code) 4000 { 4001 case REG: 4002 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) 4003 /* If pointers extend unsigned and this is a pointer in Pmode, say that 4004 all the bits above ptr_mode are known to be zero. */ 4005 /* As we do not know which address space the pointer is referring to, 4006 we can do this only if the target does not support different pointer 4007 or address modes depending on the address space. */ 4008 if (target_default_pointer_address_modes_p () 4009 && POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode 4010 && REG_POINTER (x)) 4011 nonzero &= GET_MODE_MASK (ptr_mode); 4012 #endif 4013 4014 /* Include declared information about alignment of pointers. */ 4015 /* ??? We don't properly preserve REG_POINTER changes across 4016 pointer-to-integer casts, so we can't trust it except for 4017 things that we know must be pointers. See execute/960116-1.c. */ 4018 if ((x == stack_pointer_rtx 4019 || x == frame_pointer_rtx 4020 || x == arg_pointer_rtx) 4021 && REGNO_POINTER_ALIGN (REGNO (x))) 4022 { 4023 unsigned HOST_WIDE_INT alignment 4024 = REGNO_POINTER_ALIGN (REGNO (x)) / BITS_PER_UNIT; 4025 4026 #ifdef PUSH_ROUNDING 4027 /* If PUSH_ROUNDING is defined, it is possible for the 4028 stack to be momentarily aligned only to that amount, 4029 so we pick the least alignment. */ 4030 if (x == stack_pointer_rtx && PUSH_ARGS) 4031 alignment = MIN ((unsigned HOST_WIDE_INT) PUSH_ROUNDING (1), 4032 alignment); 4033 #endif 4034 4035 nonzero &= ~(alignment - 1); 4036 } 4037 4038 { 4039 unsigned HOST_WIDE_INT nonzero_for_hook = nonzero; 4040 rtx new_rtx = rtl_hooks.reg_nonzero_bits (x, mode, known_x, 4041 known_mode, known_ret, 4042 &nonzero_for_hook); 4043 4044 if (new_rtx) 4045 nonzero_for_hook &= cached_nonzero_bits (new_rtx, mode, known_x, 4046 known_mode, known_ret); 4047 4048 return nonzero_for_hook; 4049 } 4050 4051 case CONST_INT: 4052 #ifdef SHORT_IMMEDIATES_SIGN_EXTEND 4053 /* If X is negative in MODE, sign-extend the value. */ 4054 if (INTVAL (x) > 0 4055 && mode_width < BITS_PER_WORD 4056 && (UINTVAL (x) & ((unsigned HOST_WIDE_INT) 1 << (mode_width - 1))) 4057 != 0) 4058 return UINTVAL (x) | ((unsigned HOST_WIDE_INT) (-1) << mode_width); 4059 #endif 4060 4061 return UINTVAL (x); 4062 4063 case MEM: 4064 #ifdef LOAD_EXTEND_OP 4065 /* In many, if not most, RISC machines, reading a byte from memory 4066 zeros the rest of the register. Noticing that fact saves a lot 4067 of extra zero-extends. */ 4068 if (LOAD_EXTEND_OP (GET_MODE (x)) == ZERO_EXTEND) 4069 nonzero &= GET_MODE_MASK (GET_MODE (x)); 4070 #endif 4071 break; 4072 4073 case EQ: case NE: 4074 case UNEQ: case LTGT: 4075 case GT: case GTU: case UNGT: 4076 case LT: case LTU: case UNLT: 4077 case GE: case GEU: case UNGE: 4078 case LE: case LEU: case UNLE: 4079 case UNORDERED: case ORDERED: 4080 /* If this produces an integer result, we know which bits are set. 4081 Code here used to clear bits outside the mode of X, but that is 4082 now done above. */ 4083 /* Mind that MODE is the mode the caller wants to look at this 4084 operation in, and not the actual operation mode. We can wind 4085 up with (subreg:DI (gt:V4HI x y)), and we don't have anything 4086 that describes the results of a vector compare. */ 4087 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_INT 4088 && mode_width <= HOST_BITS_PER_WIDE_INT) 4089 nonzero = STORE_FLAG_VALUE; 4090 break; 4091 4092 case NEG: 4093 #if 0 4094 /* Disabled to avoid exponential mutual recursion between nonzero_bits 4095 and num_sign_bit_copies. */ 4096 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 4097 == GET_MODE_PRECISION (GET_MODE (x))) 4098 nonzero = 1; 4099 #endif 4100 4101 if (GET_MODE_PRECISION (GET_MODE (x)) < mode_width) 4102 nonzero |= (GET_MODE_MASK (mode) & ~GET_MODE_MASK (GET_MODE (x))); 4103 break; 4104 4105 case ABS: 4106 #if 0 4107 /* Disabled to avoid exponential mutual recursion between nonzero_bits 4108 and num_sign_bit_copies. */ 4109 if (num_sign_bit_copies (XEXP (x, 0), GET_MODE (x)) 4110 == GET_MODE_PRECISION (GET_MODE (x))) 4111 nonzero = 1; 4112 #endif 4113 break; 4114 4115 case TRUNCATE: 4116 nonzero &= (cached_nonzero_bits (XEXP (x, 0), mode, 4117 known_x, known_mode, known_ret) 4118 & GET_MODE_MASK (mode)); 4119 break; 4120 4121 case ZERO_EXTEND: 4122 nonzero &= cached_nonzero_bits (XEXP (x, 0), mode, 4123 known_x, known_mode, known_ret); 4124 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 4125 nonzero &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 4126 break; 4127 4128 case SIGN_EXTEND: 4129 /* If the sign bit is known clear, this is the same as ZERO_EXTEND. 4130 Otherwise, show all the bits in the outer mode but not the inner 4131 may be nonzero. */ 4132 inner_nz = cached_nonzero_bits (XEXP (x, 0), mode, 4133 known_x, known_mode, known_ret); 4134 if (GET_MODE (XEXP (x, 0)) != VOIDmode) 4135 { 4136 inner_nz &= GET_MODE_MASK (GET_MODE (XEXP (x, 0))); 4137 if (val_signbit_known_set_p (GET_MODE (XEXP (x, 0)), inner_nz)) 4138 inner_nz |= (GET_MODE_MASK (mode) 4139 & ~GET_MODE_MASK (GET_MODE (XEXP (x, 0)))); 4140 } 4141 4142 nonzero &= inner_nz; 4143 break; 4144 4145 case AND: 4146 nonzero &= cached_nonzero_bits (XEXP (x, 0), mode, 4147 known_x, known_mode, known_ret) 4148 & cached_nonzero_bits (XEXP (x, 1), mode, 4149 known_x, known_mode, known_ret); 4150 break; 4151 4152 case XOR: case IOR: 4153 case UMIN: case UMAX: case SMIN: case SMAX: 4154 { 4155 unsigned HOST_WIDE_INT nonzero0 4156 = cached_nonzero_bits (XEXP (x, 0), mode, 4157 known_x, known_mode, known_ret); 4158 4159 /* Don't call nonzero_bits for the second time if it cannot change 4160 anything. */ 4161 if ((nonzero & nonzero0) != nonzero) 4162 nonzero &= nonzero0 4163 | cached_nonzero_bits (XEXP (x, 1), mode, 4164 known_x, known_mode, known_ret); 4165 } 4166 break; 4167 4168 case PLUS: case MINUS: 4169 case MULT: 4170 case DIV: case UDIV: 4171 case MOD: case UMOD: 4172 /* We can apply the rules of arithmetic to compute the number of 4173 high- and low-order zero bits of these operations. We start by 4174 computing the width (position of the highest-order nonzero bit) 4175 and the number of low-order zero bits for each value. */ 4176 { 4177 unsigned HOST_WIDE_INT nz0 4178 = cached_nonzero_bits (XEXP (x, 0), mode, 4179 known_x, known_mode, known_ret); 4180 unsigned HOST_WIDE_INT nz1 4181 = cached_nonzero_bits (XEXP (x, 1), mode, 4182 known_x, known_mode, known_ret); 4183 int sign_index = GET_MODE_PRECISION (GET_MODE (x)) - 1; 4184 int width0 = floor_log2 (nz0) + 1; 4185 int width1 = floor_log2 (nz1) + 1; 4186 int low0 = floor_log2 (nz0 & -nz0); 4187 int low1 = floor_log2 (nz1 & -nz1); 4188 unsigned HOST_WIDE_INT op0_maybe_minusp 4189 = nz0 & ((unsigned HOST_WIDE_INT) 1 << sign_index); 4190 unsigned HOST_WIDE_INT op1_maybe_minusp 4191 = nz1 & ((unsigned HOST_WIDE_INT) 1 << sign_index); 4192 unsigned int result_width = mode_width; 4193 int result_low = 0; 4194 4195 switch (code) 4196 { 4197 case PLUS: 4198 result_width = MAX (width0, width1) + 1; 4199 result_low = MIN (low0, low1); 4200 break; 4201 case MINUS: 4202 result_low = MIN (low0, low1); 4203 break; 4204 case MULT: 4205 result_width = width0 + width1; 4206 result_low = low0 + low1; 4207 break; 4208 case DIV: 4209 if (width1 == 0) 4210 break; 4211 if (!op0_maybe_minusp && !op1_maybe_minusp) 4212 result_width = width0; 4213 break; 4214 case UDIV: 4215 if (width1 == 0) 4216 break; 4217 result_width = width0; 4218 break; 4219 case MOD: 4220 if (width1 == 0) 4221 break; 4222 if (!op0_maybe_minusp && !op1_maybe_minusp) 4223 result_width = MIN (width0, width1); 4224 result_low = MIN (low0, low1); 4225 break; 4226 case UMOD: 4227 if (width1 == 0) 4228 break; 4229 result_width = MIN (width0, width1); 4230 result_low = MIN (low0, low1); 4231 break; 4232 default: 4233 gcc_unreachable (); 4234 } 4235 4236 if (result_width < mode_width) 4237 nonzero &= ((unsigned HOST_WIDE_INT) 1 << result_width) - 1; 4238 4239 if (result_low > 0) 4240 nonzero &= ~(((unsigned HOST_WIDE_INT) 1 << result_low) - 1); 4241 } 4242 break; 4243 4244 case ZERO_EXTRACT: 4245 if (CONST_INT_P (XEXP (x, 1)) 4246 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT) 4247 nonzero &= ((unsigned HOST_WIDE_INT) 1 << INTVAL (XEXP (x, 1))) - 1; 4248 break; 4249 4250 case SUBREG: 4251 /* If this is a SUBREG formed for a promoted variable that has 4252 been zero-extended, we know that at least the high-order bits 4253 are zero, though others might be too. */ 4254 4255 if (SUBREG_PROMOTED_VAR_P (x) && SUBREG_PROMOTED_UNSIGNED_P (x) > 0) 4256 nonzero = GET_MODE_MASK (GET_MODE (x)) 4257 & cached_nonzero_bits (SUBREG_REG (x), GET_MODE (x), 4258 known_x, known_mode, known_ret); 4259 4260 inner_mode = GET_MODE (SUBREG_REG (x)); 4261 /* If the inner mode is a single word for both the host and target 4262 machines, we can compute this from which bits of the inner 4263 object might be nonzero. */ 4264 if (GET_MODE_PRECISION (inner_mode) <= BITS_PER_WORD 4265 && (GET_MODE_PRECISION (inner_mode) <= HOST_BITS_PER_WIDE_INT)) 4266 { 4267 nonzero &= cached_nonzero_bits (SUBREG_REG (x), mode, 4268 known_x, known_mode, known_ret); 4269 4270 #if defined (WORD_REGISTER_OPERATIONS) && defined (LOAD_EXTEND_OP) 4271 /* If this is a typical RISC machine, we only have to worry 4272 about the way loads are extended. */ 4273 if ((LOAD_EXTEND_OP (inner_mode) == SIGN_EXTEND 4274 ? val_signbit_known_set_p (inner_mode, nonzero) 4275 : LOAD_EXTEND_OP (inner_mode) != ZERO_EXTEND) 4276 || !MEM_P (SUBREG_REG (x))) 4277 #endif 4278 { 4279 /* On many CISC machines, accessing an object in a wider mode 4280 causes the high-order bits to become undefined. So they are 4281 not known to be zero. */ 4282 if (GET_MODE_PRECISION (GET_MODE (x)) 4283 > GET_MODE_PRECISION (inner_mode)) 4284 nonzero |= (GET_MODE_MASK (GET_MODE (x)) 4285 & ~GET_MODE_MASK (inner_mode)); 4286 } 4287 } 4288 break; 4289 4290 case ASHIFTRT: 4291 case LSHIFTRT: 4292 case ASHIFT: 4293 case ROTATE: 4294 /* The nonzero bits are in two classes: any bits within MODE 4295 that aren't in GET_MODE (x) are always significant. The rest of the 4296 nonzero bits are those that are significant in the operand of 4297 the shift when shifted the appropriate number of bits. This 4298 shows that high-order bits are cleared by the right shift and 4299 low-order bits by left shifts. */ 4300 if (CONST_INT_P (XEXP (x, 1)) 4301 && INTVAL (XEXP (x, 1)) >= 0 4302 && INTVAL (XEXP (x, 1)) < HOST_BITS_PER_WIDE_INT 4303 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (GET_MODE (x))) 4304 { 4305 enum machine_mode inner_mode = GET_MODE (x); 4306 unsigned int width = GET_MODE_PRECISION (inner_mode); 4307 int count = INTVAL (XEXP (x, 1)); 4308 unsigned HOST_WIDE_INT mode_mask = GET_MODE_MASK (inner_mode); 4309 unsigned HOST_WIDE_INT op_nonzero 4310 = cached_nonzero_bits (XEXP (x, 0), mode, 4311 known_x, known_mode, known_ret); 4312 unsigned HOST_WIDE_INT inner = op_nonzero & mode_mask; 4313 unsigned HOST_WIDE_INT outer = 0; 4314 4315 if (mode_width > width) 4316 outer = (op_nonzero & nonzero & ~mode_mask); 4317 4318 if (code == LSHIFTRT) 4319 inner >>= count; 4320 else if (code == ASHIFTRT) 4321 { 4322 inner >>= count; 4323 4324 /* If the sign bit may have been nonzero before the shift, we 4325 need to mark all the places it could have been copied to 4326 by the shift as possibly nonzero. */ 4327 if (inner & ((unsigned HOST_WIDE_INT) 1 << (width - 1 - count))) 4328 inner |= (((unsigned HOST_WIDE_INT) 1 << count) - 1) 4329 << (width - count); 4330 } 4331 else if (code == ASHIFT) 4332 inner <<= count; 4333 else 4334 inner = ((inner << (count % width) 4335 | (inner >> (width - (count % width)))) & mode_mask); 4336 4337 nonzero &= (outer | inner); 4338 } 4339 break; 4340 4341 case FFS: 4342 case POPCOUNT: 4343 /* This is at most the number of bits in the mode. */ 4344 nonzero = ((unsigned HOST_WIDE_INT) 2 << (floor_log2 (mode_width))) - 1; 4345 break; 4346 4347 case CLZ: 4348 /* If CLZ has a known value at zero, then the nonzero bits are 4349 that value, plus the number of bits in the mode minus one. */ 4350 if (CLZ_DEFINED_VALUE_AT_ZERO (mode, nonzero)) 4351 nonzero 4352 |= ((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1; 4353 else 4354 nonzero = -1; 4355 break; 4356 4357 case CTZ: 4358 /* If CTZ has a known value at zero, then the nonzero bits are 4359 that value, plus the number of bits in the mode minus one. */ 4360 if (CTZ_DEFINED_VALUE_AT_ZERO (mode, nonzero)) 4361 nonzero 4362 |= ((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1; 4363 else 4364 nonzero = -1; 4365 break; 4366 4367 case CLRSB: 4368 /* This is at most the number of bits in the mode minus 1. */ 4369 nonzero = ((unsigned HOST_WIDE_INT) 1 << (floor_log2 (mode_width))) - 1; 4370 break; 4371 4372 case PARITY: 4373 nonzero = 1; 4374 break; 4375 4376 case IF_THEN_ELSE: 4377 { 4378 unsigned HOST_WIDE_INT nonzero_true 4379 = cached_nonzero_bits (XEXP (x, 1), mode, 4380 known_x, known_mode, known_ret); 4381 4382 /* Don't call nonzero_bits for the second time if it cannot change 4383 anything. */ 4384 if ((nonzero & nonzero_true) != nonzero) 4385 nonzero &= nonzero_true 4386 | cached_nonzero_bits (XEXP (x, 2), mode, 4387 known_x, known_mode, known_ret); 4388 } 4389 break; 4390 4391 default: 4392 break; 4393 } 4394 4395 return nonzero; 4396 } 4397 4398 /* See the macro definition above. */ 4399 #undef cached_num_sign_bit_copies 4400 4401 4402 /* The function cached_num_sign_bit_copies is a wrapper around 4403 num_sign_bit_copies1. It avoids exponential behavior in 4404 num_sign_bit_copies1 when X has identical subexpressions on the 4405 first or the second level. */ 4406 4407 static unsigned int 4408 cached_num_sign_bit_copies (const_rtx x, enum machine_mode mode, const_rtx known_x, 4409 enum machine_mode known_mode, 4410 unsigned int known_ret) 4411 { 4412 if (x == known_x && mode == known_mode) 4413 return known_ret; 4414 4415 /* Try to find identical subexpressions. If found call 4416 num_sign_bit_copies1 on X with the subexpressions as KNOWN_X and 4417 the precomputed value for the subexpression as KNOWN_RET. */ 4418 4419 if (ARITHMETIC_P (x)) 4420 { 4421 rtx x0 = XEXP (x, 0); 4422 rtx x1 = XEXP (x, 1); 4423 4424 /* Check the first level. */ 4425 if (x0 == x1) 4426 return 4427 num_sign_bit_copies1 (x, mode, x0, mode, 4428 cached_num_sign_bit_copies (x0, mode, known_x, 4429 known_mode, 4430 known_ret)); 4431 4432 /* Check the second level. */ 4433 if (ARITHMETIC_P (x0) 4434 && (x1 == XEXP (x0, 0) || x1 == XEXP (x0, 1))) 4435 return 4436 num_sign_bit_copies1 (x, mode, x1, mode, 4437 cached_num_sign_bit_copies (x1, mode, known_x, 4438 known_mode, 4439 known_ret)); 4440 4441 if (ARITHMETIC_P (x1) 4442 && (x0 == XEXP (x1, 0) || x0 == XEXP (x1, 1))) 4443 return 4444 num_sign_bit_copies1 (x, mode, x0, mode, 4445 cached_num_sign_bit_copies (x0, mode, known_x, 4446 known_mode, 4447 known_ret)); 4448 } 4449 4450 return num_sign_bit_copies1 (x, mode, known_x, known_mode, known_ret); 4451 } 4452 4453 /* Return the number of bits at the high-order end of X that are known to 4454 be equal to the sign bit. X will be used in mode MODE; if MODE is 4455 VOIDmode, X will be used in its own mode. The returned value will always 4456 be between 1 and the number of bits in MODE. */ 4457 4458 static unsigned int 4459 num_sign_bit_copies1 (const_rtx x, enum machine_mode mode, const_rtx known_x, 4460 enum machine_mode known_mode, 4461 unsigned int known_ret) 4462 { 4463 enum rtx_code code = GET_CODE (x); 4464 unsigned int bitwidth = GET_MODE_PRECISION (mode); 4465 int num0, num1, result; 4466 unsigned HOST_WIDE_INT nonzero; 4467 4468 /* If we weren't given a mode, use the mode of X. If the mode is still 4469 VOIDmode, we don't know anything. Likewise if one of the modes is 4470 floating-point. */ 4471 4472 if (mode == VOIDmode) 4473 mode = GET_MODE (x); 4474 4475 if (mode == VOIDmode || FLOAT_MODE_P (mode) || FLOAT_MODE_P (GET_MODE (x)) 4476 || VECTOR_MODE_P (GET_MODE (x)) || VECTOR_MODE_P (mode)) 4477 return 1; 4478 4479 /* For a smaller object, just ignore the high bits. */ 4480 if (bitwidth < GET_MODE_PRECISION (GET_MODE (x))) 4481 { 4482 num0 = cached_num_sign_bit_copies (x, GET_MODE (x), 4483 known_x, known_mode, known_ret); 4484 return MAX (1, 4485 num0 - (int) (GET_MODE_PRECISION (GET_MODE (x)) - bitwidth)); 4486 } 4487 4488 if (GET_MODE (x) != VOIDmode && bitwidth > GET_MODE_PRECISION (GET_MODE (x))) 4489 { 4490 #ifndef WORD_REGISTER_OPERATIONS 4491 /* If this machine does not do all register operations on the entire 4492 register and MODE is wider than the mode of X, we can say nothing 4493 at all about the high-order bits. */ 4494 return 1; 4495 #else 4496 /* Likewise on machines that do, if the mode of the object is smaller 4497 than a word and loads of that size don't sign extend, we can say 4498 nothing about the high order bits. */ 4499 if (GET_MODE_PRECISION (GET_MODE (x)) < BITS_PER_WORD 4500 #ifdef LOAD_EXTEND_OP 4501 && LOAD_EXTEND_OP (GET_MODE (x)) != SIGN_EXTEND 4502 #endif 4503 ) 4504 return 1; 4505 #endif 4506 } 4507 4508 switch (code) 4509 { 4510 case REG: 4511 4512 #if defined(POINTERS_EXTEND_UNSIGNED) && !defined(HAVE_ptr_extend) 4513 /* If pointers extend signed and this is a pointer in Pmode, say that 4514 all the bits above ptr_mode are known to be sign bit copies. */ 4515 /* As we do not know which address space the pointer is referring to, 4516 we can do this only if the target does not support different pointer 4517 or address modes depending on the address space. */ 4518 if (target_default_pointer_address_modes_p () 4519 && ! POINTERS_EXTEND_UNSIGNED && GET_MODE (x) == Pmode 4520 && mode == Pmode && REG_POINTER (x)) 4521 return GET_MODE_PRECISION (Pmode) - GET_MODE_PRECISION (ptr_mode) + 1; 4522 #endif 4523 4524 { 4525 unsigned int copies_for_hook = 1, copies = 1; 4526 rtx new_rtx = rtl_hooks.reg_num_sign_bit_copies (x, mode, known_x, 4527 known_mode, known_ret, 4528 &copies_for_hook); 4529 4530 if (new_rtx) 4531 copies = cached_num_sign_bit_copies (new_rtx, mode, known_x, 4532 known_mode, known_ret); 4533 4534 if (copies > 1 || copies_for_hook > 1) 4535 return MAX (copies, copies_for_hook); 4536 4537 /* Else, use nonzero_bits to guess num_sign_bit_copies (see below). */ 4538 } 4539 break; 4540 4541 case MEM: 4542 #ifdef LOAD_EXTEND_OP 4543 /* Some RISC machines sign-extend all loads of smaller than a word. */ 4544 if (LOAD_EXTEND_OP (GET_MODE (x)) == SIGN_EXTEND) 4545 return MAX (1, ((int) bitwidth 4546 - (int) GET_MODE_PRECISION (GET_MODE (x)) + 1)); 4547 #endif 4548 break; 4549 4550 case CONST_INT: 4551 /* If the constant is negative, take its 1's complement and remask. 4552 Then see how many zero bits we have. */ 4553 nonzero = UINTVAL (x) & GET_MODE_MASK (mode); 4554 if (bitwidth <= HOST_BITS_PER_WIDE_INT 4555 && (nonzero & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 4556 nonzero = (~nonzero) & GET_MODE_MASK (mode); 4557 4558 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); 4559 4560 case SUBREG: 4561 /* If this is a SUBREG for a promoted object that is sign-extended 4562 and we are looking at it in a wider mode, we know that at least the 4563 high-order bits are known to be sign bit copies. */ 4564 4565 if (SUBREG_PROMOTED_VAR_P (x) && ! SUBREG_PROMOTED_UNSIGNED_P (x)) 4566 { 4567 num0 = cached_num_sign_bit_copies (SUBREG_REG (x), mode, 4568 known_x, known_mode, known_ret); 4569 return MAX ((int) bitwidth 4570 - (int) GET_MODE_PRECISION (GET_MODE (x)) + 1, 4571 num0); 4572 } 4573 4574 /* For a smaller object, just ignore the high bits. */ 4575 if (bitwidth <= GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x)))) 4576 { 4577 num0 = cached_num_sign_bit_copies (SUBREG_REG (x), VOIDmode, 4578 known_x, known_mode, known_ret); 4579 return MAX (1, (num0 4580 - (int) (GET_MODE_PRECISION (GET_MODE (SUBREG_REG (x))) 4581 - bitwidth))); 4582 } 4583 4584 #ifdef WORD_REGISTER_OPERATIONS 4585 #ifdef LOAD_EXTEND_OP 4586 /* For paradoxical SUBREGs on machines where all register operations 4587 affect the entire register, just look inside. Note that we are 4588 passing MODE to the recursive call, so the number of sign bit copies 4589 will remain relative to that mode, not the inner mode. */ 4590 4591 /* This works only if loads sign extend. Otherwise, if we get a 4592 reload for the inner part, it may be loaded from the stack, and 4593 then we lose all sign bit copies that existed before the store 4594 to the stack. */ 4595 4596 if (paradoxical_subreg_p (x) 4597 && LOAD_EXTEND_OP (GET_MODE (SUBREG_REG (x))) == SIGN_EXTEND 4598 && MEM_P (SUBREG_REG (x))) 4599 return cached_num_sign_bit_copies (SUBREG_REG (x), mode, 4600 known_x, known_mode, known_ret); 4601 #endif 4602 #endif 4603 break; 4604 4605 case SIGN_EXTRACT: 4606 if (CONST_INT_P (XEXP (x, 1))) 4607 return MAX (1, (int) bitwidth - INTVAL (XEXP (x, 1))); 4608 break; 4609 4610 case SIGN_EXTEND: 4611 return (bitwidth - GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) 4612 + cached_num_sign_bit_copies (XEXP (x, 0), VOIDmode, 4613 known_x, known_mode, known_ret)); 4614 4615 case TRUNCATE: 4616 /* For a smaller object, just ignore the high bits. */ 4617 num0 = cached_num_sign_bit_copies (XEXP (x, 0), VOIDmode, 4618 known_x, known_mode, known_ret); 4619 return MAX (1, (num0 - (int) (GET_MODE_PRECISION (GET_MODE (XEXP (x, 0))) 4620 - bitwidth))); 4621 4622 case NOT: 4623 return cached_num_sign_bit_copies (XEXP (x, 0), mode, 4624 known_x, known_mode, known_ret); 4625 4626 case ROTATE: case ROTATERT: 4627 /* If we are rotating left by a number of bits less than the number 4628 of sign bit copies, we can just subtract that amount from the 4629 number. */ 4630 if (CONST_INT_P (XEXP (x, 1)) 4631 && INTVAL (XEXP (x, 1)) >= 0 4632 && INTVAL (XEXP (x, 1)) < (int) bitwidth) 4633 { 4634 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, 4635 known_x, known_mode, known_ret); 4636 return MAX (1, num0 - (code == ROTATE ? INTVAL (XEXP (x, 1)) 4637 : (int) bitwidth - INTVAL (XEXP (x, 1)))); 4638 } 4639 break; 4640 4641 case NEG: 4642 /* In general, this subtracts one sign bit copy. But if the value 4643 is known to be positive, the number of sign bit copies is the 4644 same as that of the input. Finally, if the input has just one bit 4645 that might be nonzero, all the bits are copies of the sign bit. */ 4646 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, 4647 known_x, known_mode, known_ret); 4648 if (bitwidth > HOST_BITS_PER_WIDE_INT) 4649 return num0 > 1 ? num0 - 1 : 1; 4650 4651 nonzero = nonzero_bits (XEXP (x, 0), mode); 4652 if (nonzero == 1) 4653 return bitwidth; 4654 4655 if (num0 > 1 4656 && (((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero)) 4657 num0--; 4658 4659 return num0; 4660 4661 case IOR: case AND: case XOR: 4662 case SMIN: case SMAX: case UMIN: case UMAX: 4663 /* Logical operations will preserve the number of sign-bit copies. 4664 MIN and MAX operations always return one of the operands. */ 4665 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, 4666 known_x, known_mode, known_ret); 4667 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode, 4668 known_x, known_mode, known_ret); 4669 4670 /* If num1 is clearing some of the top bits then regardless of 4671 the other term, we are guaranteed to have at least that many 4672 high-order zero bits. */ 4673 if (code == AND 4674 && num1 > 1 4675 && bitwidth <= HOST_BITS_PER_WIDE_INT 4676 && CONST_INT_P (XEXP (x, 1)) 4677 && (UINTVAL (XEXP (x, 1)) 4678 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) == 0) 4679 return num1; 4680 4681 /* Similarly for IOR when setting high-order bits. */ 4682 if (code == IOR 4683 && num1 > 1 4684 && bitwidth <= HOST_BITS_PER_WIDE_INT 4685 && CONST_INT_P (XEXP (x, 1)) 4686 && (UINTVAL (XEXP (x, 1)) 4687 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 4688 return num1; 4689 4690 return MIN (num0, num1); 4691 4692 case PLUS: case MINUS: 4693 /* For addition and subtraction, we can have a 1-bit carry. However, 4694 if we are subtracting 1 from a positive number, there will not 4695 be such a carry. Furthermore, if the positive number is known to 4696 be 0 or 1, we know the result is either -1 or 0. */ 4697 4698 if (code == PLUS && XEXP (x, 1) == constm1_rtx 4699 && bitwidth <= HOST_BITS_PER_WIDE_INT) 4700 { 4701 nonzero = nonzero_bits (XEXP (x, 0), mode); 4702 if ((((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1)) & nonzero) == 0) 4703 return (nonzero == 1 || nonzero == 0 ? bitwidth 4704 : bitwidth - floor_log2 (nonzero) - 1); 4705 } 4706 4707 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, 4708 known_x, known_mode, known_ret); 4709 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode, 4710 known_x, known_mode, known_ret); 4711 result = MAX (1, MIN (num0, num1) - 1); 4712 4713 return result; 4714 4715 case MULT: 4716 /* The number of bits of the product is the sum of the number of 4717 bits of both terms. However, unless one of the terms if known 4718 to be positive, we must allow for an additional bit since negating 4719 a negative number can remove one sign bit copy. */ 4720 4721 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, 4722 known_x, known_mode, known_ret); 4723 num1 = cached_num_sign_bit_copies (XEXP (x, 1), mode, 4724 known_x, known_mode, known_ret); 4725 4726 result = bitwidth - (bitwidth - num0) - (bitwidth - num1); 4727 if (result > 0 4728 && (bitwidth > HOST_BITS_PER_WIDE_INT 4729 || (((nonzero_bits (XEXP (x, 0), mode) 4730 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 4731 && ((nonzero_bits (XEXP (x, 1), mode) 4732 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) 4733 != 0)))) 4734 result--; 4735 4736 return MAX (1, result); 4737 4738 case UDIV: 4739 /* The result must be <= the first operand. If the first operand 4740 has the high bit set, we know nothing about the number of sign 4741 bit copies. */ 4742 if (bitwidth > HOST_BITS_PER_WIDE_INT) 4743 return 1; 4744 else if ((nonzero_bits (XEXP (x, 0), mode) 4745 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 4746 return 1; 4747 else 4748 return cached_num_sign_bit_copies (XEXP (x, 0), mode, 4749 known_x, known_mode, known_ret); 4750 4751 case UMOD: 4752 /* The result must be <= the second operand. If the second operand 4753 has (or just might have) the high bit set, we know nothing about 4754 the number of sign bit copies. */ 4755 if (bitwidth > HOST_BITS_PER_WIDE_INT) 4756 return 1; 4757 else if ((nonzero_bits (XEXP (x, 1), mode) 4758 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 4759 return 1; 4760 else 4761 return cached_num_sign_bit_copies (XEXP (x, 1), mode, 4762 known_x, known_mode, known_ret); 4763 4764 case DIV: 4765 /* Similar to unsigned division, except that we have to worry about 4766 the case where the divisor is negative, in which case we have 4767 to add 1. */ 4768 result = cached_num_sign_bit_copies (XEXP (x, 0), mode, 4769 known_x, known_mode, known_ret); 4770 if (result > 1 4771 && (bitwidth > HOST_BITS_PER_WIDE_INT 4772 || (nonzero_bits (XEXP (x, 1), mode) 4773 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 4774 result--; 4775 4776 return result; 4777 4778 case MOD: 4779 result = cached_num_sign_bit_copies (XEXP (x, 1), mode, 4780 known_x, known_mode, known_ret); 4781 if (result > 1 4782 && (bitwidth > HOST_BITS_PER_WIDE_INT 4783 || (nonzero_bits (XEXP (x, 1), mode) 4784 & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0)) 4785 result--; 4786 4787 return result; 4788 4789 case ASHIFTRT: 4790 /* Shifts by a constant add to the number of bits equal to the 4791 sign bit. */ 4792 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, 4793 known_x, known_mode, known_ret); 4794 if (CONST_INT_P (XEXP (x, 1)) 4795 && INTVAL (XEXP (x, 1)) > 0 4796 && INTVAL (XEXP (x, 1)) < GET_MODE_PRECISION (GET_MODE (x))) 4797 num0 = MIN ((int) bitwidth, num0 + INTVAL (XEXP (x, 1))); 4798 4799 return num0; 4800 4801 case ASHIFT: 4802 /* Left shifts destroy copies. */ 4803 if (!CONST_INT_P (XEXP (x, 1)) 4804 || INTVAL (XEXP (x, 1)) < 0 4805 || INTVAL (XEXP (x, 1)) >= (int) bitwidth 4806 || INTVAL (XEXP (x, 1)) >= GET_MODE_PRECISION (GET_MODE (x))) 4807 return 1; 4808 4809 num0 = cached_num_sign_bit_copies (XEXP (x, 0), mode, 4810 known_x, known_mode, known_ret); 4811 return MAX (1, num0 - INTVAL (XEXP (x, 1))); 4812 4813 case IF_THEN_ELSE: 4814 num0 = cached_num_sign_bit_copies (XEXP (x, 1), mode, 4815 known_x, known_mode, known_ret); 4816 num1 = cached_num_sign_bit_copies (XEXP (x, 2), mode, 4817 known_x, known_mode, known_ret); 4818 return MIN (num0, num1); 4819 4820 case EQ: case NE: case GE: case GT: case LE: case LT: 4821 case UNEQ: case LTGT: case UNGE: case UNGT: case UNLE: case UNLT: 4822 case GEU: case GTU: case LEU: case LTU: 4823 case UNORDERED: case ORDERED: 4824 /* If the constant is negative, take its 1's complement and remask. 4825 Then see how many zero bits we have. */ 4826 nonzero = STORE_FLAG_VALUE; 4827 if (bitwidth <= HOST_BITS_PER_WIDE_INT 4828 && (nonzero & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1))) != 0) 4829 nonzero = (~nonzero) & GET_MODE_MASK (mode); 4830 4831 return (nonzero == 0 ? bitwidth : bitwidth - floor_log2 (nonzero) - 1); 4832 4833 default: 4834 break; 4835 } 4836 4837 /* If we haven't been able to figure it out by one of the above rules, 4838 see if some of the high-order bits are known to be zero. If so, 4839 count those bits and return one less than that amount. If we can't 4840 safely compute the mask for this mode, always return BITWIDTH. */ 4841 4842 bitwidth = GET_MODE_PRECISION (mode); 4843 if (bitwidth > HOST_BITS_PER_WIDE_INT) 4844 return 1; 4845 4846 nonzero = nonzero_bits (x, mode); 4847 return nonzero & ((unsigned HOST_WIDE_INT) 1 << (bitwidth - 1)) 4848 ? 1 : bitwidth - floor_log2 (nonzero) - 1; 4849 } 4850 4851 /* Calculate the rtx_cost of a single instruction. A return value of 4852 zero indicates an instruction pattern without a known cost. */ 4853 4854 int 4855 insn_rtx_cost (rtx pat, bool speed) 4856 { 4857 int i, cost; 4858 rtx set; 4859 4860 /* Extract the single set rtx from the instruction pattern. 4861 We can't use single_set since we only have the pattern. */ 4862 if (GET_CODE (pat) == SET) 4863 set = pat; 4864 else if (GET_CODE (pat) == PARALLEL) 4865 { 4866 set = NULL_RTX; 4867 for (i = 0; i < XVECLEN (pat, 0); i++) 4868 { 4869 rtx x = XVECEXP (pat, 0, i); 4870 if (GET_CODE (x) == SET) 4871 { 4872 if (set) 4873 return 0; 4874 set = x; 4875 } 4876 } 4877 if (!set) 4878 return 0; 4879 } 4880 else 4881 return 0; 4882 4883 cost = set_src_cost (SET_SRC (set), speed); 4884 return cost > 0 ? cost : COSTS_N_INSNS (1); 4885 } 4886 4887 /* Given an insn INSN and condition COND, return the condition in a 4888 canonical form to simplify testing by callers. Specifically: 4889 4890 (1) The code will always be a comparison operation (EQ, NE, GT, etc.). 4891 (2) Both operands will be machine operands; (cc0) will have been replaced. 4892 (3) If an operand is a constant, it will be the second operand. 4893 (4) (LE x const) will be replaced with (LT x <const+1>) and similarly 4894 for GE, GEU, and LEU. 4895 4896 If the condition cannot be understood, or is an inequality floating-point 4897 comparison which needs to be reversed, 0 will be returned. 4898 4899 If REVERSE is nonzero, then reverse the condition prior to canonizing it. 4900 4901 If EARLIEST is nonzero, it is a pointer to a place where the earliest 4902 insn used in locating the condition was found. If a replacement test 4903 of the condition is desired, it should be placed in front of that 4904 insn and we will be sure that the inputs are still valid. 4905 4906 If WANT_REG is nonzero, we wish the condition to be relative to that 4907 register, if possible. Therefore, do not canonicalize the condition 4908 further. If ALLOW_CC_MODE is nonzero, allow the condition returned 4909 to be a compare to a CC mode register. 4910 4911 If VALID_AT_INSN_P, the condition must be valid at both *EARLIEST 4912 and at INSN. */ 4913 4914 rtx 4915 canonicalize_condition (rtx insn, rtx cond, int reverse, rtx *earliest, 4916 rtx want_reg, int allow_cc_mode, int valid_at_insn_p) 4917 { 4918 enum rtx_code code; 4919 rtx prev = insn; 4920 const_rtx set; 4921 rtx tem; 4922 rtx op0, op1; 4923 int reverse_code = 0; 4924 enum machine_mode mode; 4925 basic_block bb = BLOCK_FOR_INSN (insn); 4926 4927 code = GET_CODE (cond); 4928 mode = GET_MODE (cond); 4929 op0 = XEXP (cond, 0); 4930 op1 = XEXP (cond, 1); 4931 4932 if (reverse) 4933 code = reversed_comparison_code (cond, insn); 4934 if (code == UNKNOWN) 4935 return 0; 4936 4937 if (earliest) 4938 *earliest = insn; 4939 4940 /* If we are comparing a register with zero, see if the register is set 4941 in the previous insn to a COMPARE or a comparison operation. Perform 4942 the same tests as a function of STORE_FLAG_VALUE as find_comparison_args 4943 in cse.c */ 4944 4945 while ((GET_RTX_CLASS (code) == RTX_COMPARE 4946 || GET_RTX_CLASS (code) == RTX_COMM_COMPARE) 4947 && op1 == CONST0_RTX (GET_MODE (op0)) 4948 && op0 != want_reg) 4949 { 4950 /* Set nonzero when we find something of interest. */ 4951 rtx x = 0; 4952 4953 #ifdef HAVE_cc0 4954 /* If comparison with cc0, import actual comparison from compare 4955 insn. */ 4956 if (op0 == cc0_rtx) 4957 { 4958 if ((prev = prev_nonnote_insn (prev)) == 0 4959 || !NONJUMP_INSN_P (prev) 4960 || (set = single_set (prev)) == 0 4961 || SET_DEST (set) != cc0_rtx) 4962 return 0; 4963 4964 op0 = SET_SRC (set); 4965 op1 = CONST0_RTX (GET_MODE (op0)); 4966 if (earliest) 4967 *earliest = prev; 4968 } 4969 #endif 4970 4971 /* If this is a COMPARE, pick up the two things being compared. */ 4972 if (GET_CODE (op0) == COMPARE) 4973 { 4974 op1 = XEXP (op0, 1); 4975 op0 = XEXP (op0, 0); 4976 continue; 4977 } 4978 else if (!REG_P (op0)) 4979 break; 4980 4981 /* Go back to the previous insn. Stop if it is not an INSN. We also 4982 stop if it isn't a single set or if it has a REG_INC note because 4983 we don't want to bother dealing with it. */ 4984 4985 prev = prev_nonnote_nondebug_insn (prev); 4986 4987 if (prev == 0 4988 || !NONJUMP_INSN_P (prev) 4989 || FIND_REG_INC_NOTE (prev, NULL_RTX) 4990 /* In cfglayout mode, there do not have to be labels at the 4991 beginning of a block, or jumps at the end, so the previous 4992 conditions would not stop us when we reach bb boundary. */ 4993 || BLOCK_FOR_INSN (prev) != bb) 4994 break; 4995 4996 set = set_of (op0, prev); 4997 4998 if (set 4999 && (GET_CODE (set) != SET 5000 || !rtx_equal_p (SET_DEST (set), op0))) 5001 break; 5002 5003 /* If this is setting OP0, get what it sets it to if it looks 5004 relevant. */ 5005 if (set) 5006 { 5007 enum machine_mode inner_mode = GET_MODE (SET_DEST (set)); 5008 #ifdef FLOAT_STORE_FLAG_VALUE 5009 REAL_VALUE_TYPE fsfv; 5010 #endif 5011 5012 /* ??? We may not combine comparisons done in a CCmode with 5013 comparisons not done in a CCmode. This is to aid targets 5014 like Alpha that have an IEEE compliant EQ instruction, and 5015 a non-IEEE compliant BEQ instruction. The use of CCmode is 5016 actually artificial, simply to prevent the combination, but 5017 should not affect other platforms. 5018 5019 However, we must allow VOIDmode comparisons to match either 5020 CCmode or non-CCmode comparison, because some ports have 5021 modeless comparisons inside branch patterns. 5022 5023 ??? This mode check should perhaps look more like the mode check 5024 in simplify_comparison in combine. */ 5025 5026 if ((GET_CODE (SET_SRC (set)) == COMPARE 5027 || (((code == NE 5028 || (code == LT 5029 && val_signbit_known_set_p (inner_mode, 5030 STORE_FLAG_VALUE)) 5031 #ifdef FLOAT_STORE_FLAG_VALUE 5032 || (code == LT 5033 && SCALAR_FLOAT_MODE_P (inner_mode) 5034 && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode), 5035 REAL_VALUE_NEGATIVE (fsfv))) 5036 #endif 5037 )) 5038 && COMPARISON_P (SET_SRC (set)))) 5039 && (((GET_MODE_CLASS (mode) == MODE_CC) 5040 == (GET_MODE_CLASS (inner_mode) == MODE_CC)) 5041 || mode == VOIDmode || inner_mode == VOIDmode)) 5042 x = SET_SRC (set); 5043 else if (((code == EQ 5044 || (code == GE 5045 && val_signbit_known_set_p (inner_mode, 5046 STORE_FLAG_VALUE)) 5047 #ifdef FLOAT_STORE_FLAG_VALUE 5048 || (code == GE 5049 && SCALAR_FLOAT_MODE_P (inner_mode) 5050 && (fsfv = FLOAT_STORE_FLAG_VALUE (inner_mode), 5051 REAL_VALUE_NEGATIVE (fsfv))) 5052 #endif 5053 )) 5054 && COMPARISON_P (SET_SRC (set)) 5055 && (((GET_MODE_CLASS (mode) == MODE_CC) 5056 == (GET_MODE_CLASS (inner_mode) == MODE_CC)) 5057 || mode == VOIDmode || inner_mode == VOIDmode)) 5058 5059 { 5060 reverse_code = 1; 5061 x = SET_SRC (set); 5062 } 5063 else 5064 break; 5065 } 5066 5067 else if (reg_set_p (op0, prev)) 5068 /* If this sets OP0, but not directly, we have to give up. */ 5069 break; 5070 5071 if (x) 5072 { 5073 /* If the caller is expecting the condition to be valid at INSN, 5074 make sure X doesn't change before INSN. */ 5075 if (valid_at_insn_p) 5076 if (modified_in_p (x, prev) || modified_between_p (x, prev, insn)) 5077 break; 5078 if (COMPARISON_P (x)) 5079 code = GET_CODE (x); 5080 if (reverse_code) 5081 { 5082 code = reversed_comparison_code (x, prev); 5083 if (code == UNKNOWN) 5084 return 0; 5085 reverse_code = 0; 5086 } 5087 5088 op0 = XEXP (x, 0), op1 = XEXP (x, 1); 5089 if (earliest) 5090 *earliest = prev; 5091 } 5092 } 5093 5094 /* If constant is first, put it last. */ 5095 if (CONSTANT_P (op0)) 5096 code = swap_condition (code), tem = op0, op0 = op1, op1 = tem; 5097 5098 /* If OP0 is the result of a comparison, we weren't able to find what 5099 was really being compared, so fail. */ 5100 if (!allow_cc_mode 5101 && GET_MODE_CLASS (GET_MODE (op0)) == MODE_CC) 5102 return 0; 5103 5104 /* Canonicalize any ordered comparison with integers involving equality 5105 if we can do computations in the relevant mode and we do not 5106 overflow. */ 5107 5108 if (GET_MODE_CLASS (GET_MODE (op0)) != MODE_CC 5109 && CONST_INT_P (op1) 5110 && GET_MODE (op0) != VOIDmode 5111 && GET_MODE_PRECISION (GET_MODE (op0)) <= HOST_BITS_PER_WIDE_INT) 5112 { 5113 HOST_WIDE_INT const_val = INTVAL (op1); 5114 unsigned HOST_WIDE_INT uconst_val = const_val; 5115 unsigned HOST_WIDE_INT max_val 5116 = (unsigned HOST_WIDE_INT) GET_MODE_MASK (GET_MODE (op0)); 5117 5118 switch (code) 5119 { 5120 case LE: 5121 if ((unsigned HOST_WIDE_INT) const_val != max_val >> 1) 5122 code = LT, op1 = gen_int_mode (const_val + 1, GET_MODE (op0)); 5123 break; 5124 5125 /* When cross-compiling, const_val might be sign-extended from 5126 BITS_PER_WORD to HOST_BITS_PER_WIDE_INT */ 5127 case GE: 5128 if ((const_val & max_val) 5129 != ((unsigned HOST_WIDE_INT) 1 5130 << (GET_MODE_PRECISION (GET_MODE (op0)) - 1))) 5131 code = GT, op1 = gen_int_mode (const_val - 1, GET_MODE (op0)); 5132 break; 5133 5134 case LEU: 5135 if (uconst_val < max_val) 5136 code = LTU, op1 = gen_int_mode (uconst_val + 1, GET_MODE (op0)); 5137 break; 5138 5139 case GEU: 5140 if (uconst_val != 0) 5141 code = GTU, op1 = gen_int_mode (uconst_val - 1, GET_MODE (op0)); 5142 break; 5143 5144 default: 5145 break; 5146 } 5147 } 5148 5149 /* Never return CC0; return zero instead. */ 5150 if (CC0_P (op0)) 5151 return 0; 5152 5153 return gen_rtx_fmt_ee (code, VOIDmode, op0, op1); 5154 } 5155 5156 /* Given a jump insn JUMP, return the condition that will cause it to branch 5157 to its JUMP_LABEL. If the condition cannot be understood, or is an 5158 inequality floating-point comparison which needs to be reversed, 0 will 5159 be returned. 5160 5161 If EARLIEST is nonzero, it is a pointer to a place where the earliest 5162 insn used in locating the condition was found. If a replacement test 5163 of the condition is desired, it should be placed in front of that 5164 insn and we will be sure that the inputs are still valid. If EARLIEST 5165 is null, the returned condition will be valid at INSN. 5166 5167 If ALLOW_CC_MODE is nonzero, allow the condition returned to be a 5168 compare CC mode register. 5169 5170 VALID_AT_INSN_P is the same as for canonicalize_condition. */ 5171 5172 rtx 5173 get_condition (rtx jump, rtx *earliest, int allow_cc_mode, int valid_at_insn_p) 5174 { 5175 rtx cond; 5176 int reverse; 5177 rtx set; 5178 5179 /* If this is not a standard conditional jump, we can't parse it. */ 5180 if (!JUMP_P (jump) 5181 || ! any_condjump_p (jump)) 5182 return 0; 5183 set = pc_set (jump); 5184 5185 cond = XEXP (SET_SRC (set), 0); 5186 5187 /* If this branches to JUMP_LABEL when the condition is false, reverse 5188 the condition. */ 5189 reverse 5190 = GET_CODE (XEXP (SET_SRC (set), 2)) == LABEL_REF 5191 && XEXP (XEXP (SET_SRC (set), 2), 0) == JUMP_LABEL (jump); 5192 5193 return canonicalize_condition (jump, cond, reverse, earliest, NULL_RTX, 5194 allow_cc_mode, valid_at_insn_p); 5195 } 5196 5197 /* Initialize the table NUM_SIGN_BIT_COPIES_IN_REP based on 5198 TARGET_MODE_REP_EXTENDED. 5199 5200 Note that we assume that the property of 5201 TARGET_MODE_REP_EXTENDED(B, C) is sticky to the integral modes 5202 narrower than mode B. I.e., if A is a mode narrower than B then in 5203 order to be able to operate on it in mode B, mode A needs to 5204 satisfy the requirements set by the representation of mode B. */ 5205 5206 static void 5207 init_num_sign_bit_copies_in_rep (void) 5208 { 5209 enum machine_mode mode, in_mode; 5210 5211 for (in_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); in_mode != VOIDmode; 5212 in_mode = GET_MODE_WIDER_MODE (mode)) 5213 for (mode = GET_CLASS_NARROWEST_MODE (MODE_INT); mode != in_mode; 5214 mode = GET_MODE_WIDER_MODE (mode)) 5215 { 5216 enum machine_mode i; 5217 5218 /* Currently, it is assumed that TARGET_MODE_REP_EXTENDED 5219 extends to the next widest mode. */ 5220 gcc_assert (targetm.mode_rep_extended (mode, in_mode) == UNKNOWN 5221 || GET_MODE_WIDER_MODE (mode) == in_mode); 5222 5223 /* We are in in_mode. Count how many bits outside of mode 5224 have to be copies of the sign-bit. */ 5225 for (i = mode; i != in_mode; i = GET_MODE_WIDER_MODE (i)) 5226 { 5227 enum machine_mode wider = GET_MODE_WIDER_MODE (i); 5228 5229 if (targetm.mode_rep_extended (i, wider) == SIGN_EXTEND 5230 /* We can only check sign-bit copies starting from the 5231 top-bit. In order to be able to check the bits we 5232 have already seen we pretend that subsequent bits 5233 have to be sign-bit copies too. */ 5234 || num_sign_bit_copies_in_rep [in_mode][mode]) 5235 num_sign_bit_copies_in_rep [in_mode][mode] 5236 += GET_MODE_PRECISION (wider) - GET_MODE_PRECISION (i); 5237 } 5238 } 5239 } 5240 5241 /* Suppose that truncation from the machine mode of X to MODE is not a 5242 no-op. See if there is anything special about X so that we can 5243 assume it already contains a truncated value of MODE. */ 5244 5245 bool 5246 truncated_to_mode (enum machine_mode mode, const_rtx x) 5247 { 5248 /* This register has already been used in MODE without explicit 5249 truncation. */ 5250 if (REG_P (x) && rtl_hooks.reg_truncated_to_mode (mode, x)) 5251 return true; 5252 5253 /* See if we already satisfy the requirements of MODE. If yes we 5254 can just switch to MODE. */ 5255 if (num_sign_bit_copies_in_rep[GET_MODE (x)][mode] 5256 && (num_sign_bit_copies (x, GET_MODE (x)) 5257 >= num_sign_bit_copies_in_rep[GET_MODE (x)][mode] + 1)) 5258 return true; 5259 5260 return false; 5261 } 5262 5263 /* Initialize non_rtx_starting_operands, which is used to speed up 5264 for_each_rtx. */ 5265 void 5266 init_rtlanal (void) 5267 { 5268 int i; 5269 for (i = 0; i < NUM_RTX_CODE; i++) 5270 { 5271 const char *format = GET_RTX_FORMAT (i); 5272 const char *first = strpbrk (format, "eEV"); 5273 non_rtx_starting_operands[i] = first ? first - format : -1; 5274 } 5275 5276 init_num_sign_bit_copies_in_rep (); 5277 } 5278 5279 /* Check whether this is a constant pool constant. */ 5280 bool 5281 constant_pool_constant_p (rtx x) 5282 { 5283 x = avoid_constant_pool_reference (x); 5284 return CONST_DOUBLE_P (x); 5285 } 5286 5287 /* If M is a bitmask that selects a field of low-order bits within an item but 5288 not the entire word, return the length of the field. Return -1 otherwise. 5289 M is used in machine mode MODE. */ 5290 5291 int 5292 low_bitmask_len (enum machine_mode mode, unsigned HOST_WIDE_INT m) 5293 { 5294 if (mode != VOIDmode) 5295 { 5296 if (GET_MODE_PRECISION (mode) > HOST_BITS_PER_WIDE_INT) 5297 return -1; 5298 m &= GET_MODE_MASK (mode); 5299 } 5300 5301 return exact_log2 (m + 1); 5302 } 5303 5304 /* Return the mode of MEM's address. */ 5305 5306 enum machine_mode 5307 get_address_mode (rtx mem) 5308 { 5309 enum machine_mode mode; 5310 5311 gcc_assert (MEM_P (mem)); 5312 mode = GET_MODE (XEXP (mem, 0)); 5313 if (mode != VOIDmode) 5314 return mode; 5315 return targetm.addr_space.address_mode (MEM_ADDR_SPACE (mem)); 5316 } 5317 5318 /* Split up a CONST_DOUBLE or integer constant rtx 5319 into two rtx's for single words, 5320 storing in *FIRST the word that comes first in memory in the target 5321 and in *SECOND the other. */ 5322 5323 void 5324 split_double (rtx value, rtx *first, rtx *second) 5325 { 5326 if (CONST_INT_P (value)) 5327 { 5328 if (HOST_BITS_PER_WIDE_INT >= (2 * BITS_PER_WORD)) 5329 { 5330 /* In this case the CONST_INT holds both target words. 5331 Extract the bits from it into two word-sized pieces. 5332 Sign extend each half to HOST_WIDE_INT. */ 5333 unsigned HOST_WIDE_INT low, high; 5334 unsigned HOST_WIDE_INT mask, sign_bit, sign_extend; 5335 unsigned bits_per_word = BITS_PER_WORD; 5336 5337 /* Set sign_bit to the most significant bit of a word. */ 5338 sign_bit = 1; 5339 sign_bit <<= bits_per_word - 1; 5340 5341 /* Set mask so that all bits of the word are set. We could 5342 have used 1 << BITS_PER_WORD instead of basing the 5343 calculation on sign_bit. However, on machines where 5344 HOST_BITS_PER_WIDE_INT == BITS_PER_WORD, it could cause a 5345 compiler warning, even though the code would never be 5346 executed. */ 5347 mask = sign_bit << 1; 5348 mask--; 5349 5350 /* Set sign_extend as any remaining bits. */ 5351 sign_extend = ~mask; 5352 5353 /* Pick the lower word and sign-extend it. */ 5354 low = INTVAL (value); 5355 low &= mask; 5356 if (low & sign_bit) 5357 low |= sign_extend; 5358 5359 /* Pick the higher word, shifted to the least significant 5360 bits, and sign-extend it. */ 5361 high = INTVAL (value); 5362 high >>= bits_per_word - 1; 5363 high >>= 1; 5364 high &= mask; 5365 if (high & sign_bit) 5366 high |= sign_extend; 5367 5368 /* Store the words in the target machine order. */ 5369 if (WORDS_BIG_ENDIAN) 5370 { 5371 *first = GEN_INT (high); 5372 *second = GEN_INT (low); 5373 } 5374 else 5375 { 5376 *first = GEN_INT (low); 5377 *second = GEN_INT (high); 5378 } 5379 } 5380 else 5381 { 5382 /* The rule for using CONST_INT for a wider mode 5383 is that we regard the value as signed. 5384 So sign-extend it. */ 5385 rtx high = (INTVAL (value) < 0 ? constm1_rtx : const0_rtx); 5386 if (WORDS_BIG_ENDIAN) 5387 { 5388 *first = high; 5389 *second = value; 5390 } 5391 else 5392 { 5393 *first = value; 5394 *second = high; 5395 } 5396 } 5397 } 5398 else if (!CONST_DOUBLE_P (value)) 5399 { 5400 if (WORDS_BIG_ENDIAN) 5401 { 5402 *first = const0_rtx; 5403 *second = value; 5404 } 5405 else 5406 { 5407 *first = value; 5408 *second = const0_rtx; 5409 } 5410 } 5411 else if (GET_MODE (value) == VOIDmode 5412 /* This is the old way we did CONST_DOUBLE integers. */ 5413 || GET_MODE_CLASS (GET_MODE (value)) == MODE_INT) 5414 { 5415 /* In an integer, the words are defined as most and least significant. 5416 So order them by the target's convention. */ 5417 if (WORDS_BIG_ENDIAN) 5418 { 5419 *first = GEN_INT (CONST_DOUBLE_HIGH (value)); 5420 *second = GEN_INT (CONST_DOUBLE_LOW (value)); 5421 } 5422 else 5423 { 5424 *first = GEN_INT (CONST_DOUBLE_LOW (value)); 5425 *second = GEN_INT (CONST_DOUBLE_HIGH (value)); 5426 } 5427 } 5428 else 5429 { 5430 REAL_VALUE_TYPE r; 5431 long l[2]; 5432 REAL_VALUE_FROM_CONST_DOUBLE (r, value); 5433 5434 /* Note, this converts the REAL_VALUE_TYPE to the target's 5435 format, splits up the floating point double and outputs 5436 exactly 32 bits of it into each of l[0] and l[1] -- 5437 not necessarily BITS_PER_WORD bits. */ 5438 REAL_VALUE_TO_TARGET_DOUBLE (r, l); 5439 5440 /* If 32 bits is an entire word for the target, but not for the host, 5441 then sign-extend on the host so that the number will look the same 5442 way on the host that it would on the target. See for instance 5443 simplify_unary_operation. The #if is needed to avoid compiler 5444 warnings. */ 5445 5446 #if HOST_BITS_PER_LONG > 32 5447 if (BITS_PER_WORD < HOST_BITS_PER_LONG && BITS_PER_WORD == 32) 5448 { 5449 if (l[0] & ((long) 1 << 31)) 5450 l[0] |= ((long) (-1) << 32); 5451 if (l[1] & ((long) 1 << 31)) 5452 l[1] |= ((long) (-1) << 32); 5453 } 5454 #endif 5455 5456 *first = GEN_INT (l[0]); 5457 *second = GEN_INT (l[1]); 5458 } 5459 } 5460 5461 /* Strip outer address "mutations" from LOC and return a pointer to the 5462 inner value. If OUTER_CODE is nonnull, store the code of the innermost 5463 stripped expression there. 5464 5465 "Mutations" either convert between modes or apply some kind of 5466 alignment. */ 5467 5468 rtx * 5469 strip_address_mutations (rtx *loc, enum rtx_code *outer_code) 5470 { 5471 for (;;) 5472 { 5473 enum rtx_code code = GET_CODE (*loc); 5474 if (GET_RTX_CLASS (code) == RTX_UNARY) 5475 /* Things like SIGN_EXTEND, ZERO_EXTEND and TRUNCATE can be 5476 used to convert between pointer sizes. */ 5477 loc = &XEXP (*loc, 0); 5478 else if (code == AND && CONST_INT_P (XEXP (*loc, 1))) 5479 /* (and ... (const_int -X)) is used to align to X bytes. */ 5480 loc = &XEXP (*loc, 0); 5481 else if (code == SUBREG 5482 && !OBJECT_P (SUBREG_REG (*loc)) 5483 && subreg_lowpart_p (*loc)) 5484 /* (subreg (operator ...) ...) inside and is used for mode 5485 conversion too. */ 5486 loc = &SUBREG_REG (*loc); 5487 else 5488 return loc; 5489 if (outer_code) 5490 *outer_code = code; 5491 } 5492 } 5493 5494 /* Return true if X must be a base rather than an index. */ 5495 5496 static bool 5497 must_be_base_p (rtx x) 5498 { 5499 return GET_CODE (x) == LO_SUM; 5500 } 5501 5502 /* Return true if X must be an index rather than a base. */ 5503 5504 static bool 5505 must_be_index_p (rtx x) 5506 { 5507 return GET_CODE (x) == MULT || GET_CODE (x) == ASHIFT; 5508 } 5509 5510 /* Set the segment part of address INFO to LOC, given that INNER is the 5511 unmutated value. */ 5512 5513 static void 5514 set_address_segment (struct address_info *info, rtx *loc, rtx *inner) 5515 { 5516 gcc_checking_assert (GET_CODE (*inner) == UNSPEC); 5517 5518 gcc_assert (!info->segment); 5519 info->segment = loc; 5520 info->segment_term = inner; 5521 } 5522 5523 /* Set the base part of address INFO to LOC, given that INNER is the 5524 unmutated value. */ 5525 5526 static void 5527 set_address_base (struct address_info *info, rtx *loc, rtx *inner) 5528 { 5529 if (GET_CODE (*inner) == LO_SUM) 5530 inner = strip_address_mutations (&XEXP (*inner, 0)); 5531 gcc_checking_assert (REG_P (*inner) 5532 || MEM_P (*inner) 5533 || GET_CODE (*inner) == SUBREG); 5534 5535 gcc_assert (!info->base); 5536 info->base = loc; 5537 info->base_term = inner; 5538 } 5539 5540 /* Set the index part of address INFO to LOC, given that INNER is the 5541 unmutated value. */ 5542 5543 static void 5544 set_address_index (struct address_info *info, rtx *loc, rtx *inner) 5545 { 5546 if ((GET_CODE (*inner) == MULT || GET_CODE (*inner) == ASHIFT) 5547 && CONSTANT_P (XEXP (*inner, 1))) 5548 inner = strip_address_mutations (&XEXP (*inner, 0)); 5549 gcc_checking_assert (REG_P (*inner) 5550 || MEM_P (*inner) 5551 || GET_CODE (*inner) == SUBREG); 5552 5553 gcc_assert (!info->index); 5554 info->index = loc; 5555 info->index_term = inner; 5556 } 5557 5558 /* Set the displacement part of address INFO to LOC, given that INNER 5559 is the constant term. */ 5560 5561 static void 5562 set_address_disp (struct address_info *info, rtx *loc, rtx *inner) 5563 { 5564 gcc_checking_assert (CONSTANT_P (*inner)); 5565 5566 gcc_assert (!info->disp); 5567 info->disp = loc; 5568 info->disp_term = inner; 5569 } 5570 5571 /* INFO->INNER describes a {PRE,POST}_{INC,DEC} address. Set up the 5572 rest of INFO accordingly. */ 5573 5574 static void 5575 decompose_incdec_address (struct address_info *info) 5576 { 5577 info->autoinc_p = true; 5578 5579 rtx *base = &XEXP (*info->inner, 0); 5580 set_address_base (info, base, base); 5581 gcc_checking_assert (info->base == info->base_term); 5582 5583 /* These addresses are only valid when the size of the addressed 5584 value is known. */ 5585 gcc_checking_assert (info->mode != VOIDmode); 5586 } 5587 5588 /* INFO->INNER describes a {PRE,POST}_MODIFY address. Set up the rest 5589 of INFO accordingly. */ 5590 5591 static void 5592 decompose_automod_address (struct address_info *info) 5593 { 5594 info->autoinc_p = true; 5595 5596 rtx *base = &XEXP (*info->inner, 0); 5597 set_address_base (info, base, base); 5598 gcc_checking_assert (info->base == info->base_term); 5599 5600 rtx plus = XEXP (*info->inner, 1); 5601 gcc_assert (GET_CODE (plus) == PLUS); 5602 5603 info->base_term2 = &XEXP (plus, 0); 5604 gcc_checking_assert (rtx_equal_p (*info->base_term, *info->base_term2)); 5605 5606 rtx *step = &XEXP (plus, 1); 5607 rtx *inner_step = strip_address_mutations (step); 5608 if (CONSTANT_P (*inner_step)) 5609 set_address_disp (info, step, inner_step); 5610 else 5611 set_address_index (info, step, inner_step); 5612 } 5613 5614 /* Treat *LOC as a tree of PLUS operands and store pointers to the summed 5615 values in [PTR, END). Return a pointer to the end of the used array. */ 5616 5617 static rtx ** 5618 extract_plus_operands (rtx *loc, rtx **ptr, rtx **end) 5619 { 5620 rtx x = *loc; 5621 if (GET_CODE (x) == PLUS) 5622 { 5623 ptr = extract_plus_operands (&XEXP (x, 0), ptr, end); 5624 ptr = extract_plus_operands (&XEXP (x, 1), ptr, end); 5625 } 5626 else 5627 { 5628 gcc_assert (ptr != end); 5629 *ptr++ = loc; 5630 } 5631 return ptr; 5632 } 5633 5634 /* Evaluate the likelihood of X being a base or index value, returning 5635 positive if it is likely to be a base, negative if it is likely to be 5636 an index, and 0 if we can't tell. Make the magnitude of the return 5637 value reflect the amount of confidence we have in the answer. 5638 5639 MODE, AS, OUTER_CODE and INDEX_CODE are as for ok_for_base_p_1. */ 5640 5641 static int 5642 baseness (rtx x, enum machine_mode mode, addr_space_t as, 5643 enum rtx_code outer_code, enum rtx_code index_code) 5644 { 5645 /* See whether we can be certain. */ 5646 if (must_be_base_p (x)) 5647 return 3; 5648 if (must_be_index_p (x)) 5649 return -3; 5650 5651 /* Believe *_POINTER unless the address shape requires otherwise. */ 5652 if (REG_P (x) && REG_POINTER (x)) 5653 return 2; 5654 if (MEM_P (x) && MEM_POINTER (x)) 5655 return 2; 5656 5657 if (REG_P (x) && HARD_REGISTER_P (x)) 5658 { 5659 /* X is a hard register. If it only fits one of the base 5660 or index classes, choose that interpretation. */ 5661 int regno = REGNO (x); 5662 bool base_p = ok_for_base_p_1 (regno, mode, as, outer_code, index_code); 5663 bool index_p = REGNO_OK_FOR_INDEX_P (regno); 5664 if (base_p != index_p) 5665 return base_p ? 1 : -1; 5666 } 5667 return 0; 5668 } 5669 5670 /* INFO->INNER describes a normal, non-automodified address. 5671 Fill in the rest of INFO accordingly. */ 5672 5673 static void 5674 decompose_normal_address (struct address_info *info) 5675 { 5676 /* Treat the address as the sum of up to four values. */ 5677 rtx *ops[4]; 5678 size_t n_ops = extract_plus_operands (info->inner, ops, 5679 ops + ARRAY_SIZE (ops)) - ops; 5680 5681 /* If there is more than one component, any base component is in a PLUS. */ 5682 if (n_ops > 1) 5683 info->base_outer_code = PLUS; 5684 5685 /* Separate the parts that contain a REG or MEM from those that don't. 5686 Record the latter in INFO and leave the former in OPS. */ 5687 rtx *inner_ops[4]; 5688 size_t out = 0; 5689 for (size_t in = 0; in < n_ops; ++in) 5690 { 5691 rtx *loc = ops[in]; 5692 rtx *inner = strip_address_mutations (loc); 5693 if (CONSTANT_P (*inner)) 5694 set_address_disp (info, loc, inner); 5695 else if (GET_CODE (*inner) == UNSPEC) 5696 set_address_segment (info, loc, inner); 5697 else 5698 { 5699 ops[out] = loc; 5700 inner_ops[out] = inner; 5701 ++out; 5702 } 5703 } 5704 5705 /* Classify the remaining OPS members as bases and indexes. */ 5706 if (out == 1) 5707 { 5708 /* Assume that the remaining value is a base unless the shape 5709 requires otherwise. */ 5710 if (!must_be_index_p (*inner_ops[0])) 5711 set_address_base (info, ops[0], inner_ops[0]); 5712 else 5713 set_address_index (info, ops[0], inner_ops[0]); 5714 } 5715 else if (out == 2) 5716 { 5717 /* In the event of a tie, assume the base comes first. */ 5718 if (baseness (*inner_ops[0], info->mode, info->as, PLUS, 5719 GET_CODE (*ops[1])) 5720 >= baseness (*inner_ops[1], info->mode, info->as, PLUS, 5721 GET_CODE (*ops[0]))) 5722 { 5723 set_address_base (info, ops[0], inner_ops[0]); 5724 set_address_index (info, ops[1], inner_ops[1]); 5725 } 5726 else 5727 { 5728 set_address_base (info, ops[1], inner_ops[1]); 5729 set_address_index (info, ops[0], inner_ops[0]); 5730 } 5731 } 5732 else 5733 gcc_assert (out == 0); 5734 } 5735 5736 /* Describe address *LOC in *INFO. MODE is the mode of the addressed value, 5737 or VOIDmode if not known. AS is the address space associated with LOC. 5738 OUTER_CODE is MEM if *LOC is a MEM address and ADDRESS otherwise. */ 5739 5740 void 5741 decompose_address (struct address_info *info, rtx *loc, enum machine_mode mode, 5742 addr_space_t as, enum rtx_code outer_code) 5743 { 5744 memset (info, 0, sizeof (*info)); 5745 info->mode = mode; 5746 info->as = as; 5747 info->addr_outer_code = outer_code; 5748 info->outer = loc; 5749 info->inner = strip_address_mutations (loc, &outer_code); 5750 info->base_outer_code = outer_code; 5751 switch (GET_CODE (*info->inner)) 5752 { 5753 case PRE_DEC: 5754 case PRE_INC: 5755 case POST_DEC: 5756 case POST_INC: 5757 decompose_incdec_address (info); 5758 break; 5759 5760 case PRE_MODIFY: 5761 case POST_MODIFY: 5762 decompose_automod_address (info); 5763 break; 5764 5765 default: 5766 decompose_normal_address (info); 5767 break; 5768 } 5769 } 5770 5771 /* Describe address operand LOC in INFO. */ 5772 5773 void 5774 decompose_lea_address (struct address_info *info, rtx *loc) 5775 { 5776 decompose_address (info, loc, VOIDmode, ADDR_SPACE_GENERIC, ADDRESS); 5777 } 5778 5779 /* Describe the address of MEM X in INFO. */ 5780 5781 void 5782 decompose_mem_address (struct address_info *info, rtx x) 5783 { 5784 gcc_assert (MEM_P (x)); 5785 decompose_address (info, &XEXP (x, 0), GET_MODE (x), 5786 MEM_ADDR_SPACE (x), MEM); 5787 } 5788 5789 /* Update INFO after a change to the address it describes. */ 5790 5791 void 5792 update_address (struct address_info *info) 5793 { 5794 decompose_address (info, info->outer, info->mode, info->as, 5795 info->addr_outer_code); 5796 } 5797 5798 /* Return the scale applied to *INFO->INDEX_TERM, or 0 if the index is 5799 more complicated than that. */ 5800 5801 HOST_WIDE_INT 5802 get_index_scale (const struct address_info *info) 5803 { 5804 rtx index = *info->index; 5805 if (GET_CODE (index) == MULT 5806 && CONST_INT_P (XEXP (index, 1)) 5807 && info->index_term == &XEXP (index, 0)) 5808 return INTVAL (XEXP (index, 1)); 5809 5810 if (GET_CODE (index) == ASHIFT 5811 && CONST_INT_P (XEXP (index, 1)) 5812 && info->index_term == &XEXP (index, 0)) 5813 return (HOST_WIDE_INT) 1 << INTVAL (XEXP (index, 1)); 5814 5815 if (info->index == info->index_term) 5816 return 1; 5817 5818 return 0; 5819 } 5820 5821 /* Return the "index code" of INFO, in the form required by 5822 ok_for_base_p_1. */ 5823 5824 enum rtx_code 5825 get_index_code (const struct address_info *info) 5826 { 5827 if (info->index) 5828 return GET_CODE (*info->index); 5829 5830 if (info->disp) 5831 return GET_CODE (*info->disp); 5832 5833 return SCRATCH; 5834 } 5835