1 /* Reload pseudo regs into hard regs for insns that require hard regs. 2 Copyright (C) 1987-2020 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "backend.h" 24 #include "target.h" 25 #include "rtl.h" 26 #include "tree.h" 27 #include "predict.h" 28 #include "df.h" 29 #include "memmodel.h" 30 #include "tm_p.h" 31 #include "optabs.h" 32 #include "regs.h" 33 #include "ira.h" 34 #include "recog.h" 35 36 #include "rtl-error.h" 37 #include "expr.h" 38 #include "addresses.h" 39 #include "cfgrtl.h" 40 #include "cfgbuild.h" 41 #include "reload.h" 42 #include "except.h" 43 #include "dumpfile.h" 44 #include "rtl-iter.h" 45 #include "function-abi.h" 46 47 /* This file contains the reload pass of the compiler, which is 48 run after register allocation has been done. It checks that 49 each insn is valid (operands required to be in registers really 50 are in registers of the proper class) and fixes up invalid ones 51 by copying values temporarily into registers for the insns 52 that need them. 53 54 The results of register allocation are described by the vector 55 reg_renumber; the insns still contain pseudo regs, but reg_renumber 56 can be used to find which hard reg, if any, a pseudo reg is in. 57 58 The technique we always use is to free up a few hard regs that are 59 called ``reload regs'', and for each place where a pseudo reg 60 must be in a hard reg, copy it temporarily into one of the reload regs. 61 62 Reload regs are allocated locally for every instruction that needs 63 reloads. When there are pseudos which are allocated to a register that 64 has been chosen as a reload reg, such pseudos must be ``spilled''. 65 This means that they go to other hard regs, or to stack slots if no other 66 available hard regs can be found. Spilling can invalidate more 67 insns, requiring additional need for reloads, so we must keep checking 68 until the process stabilizes. 69 70 For machines with different classes of registers, we must keep track 71 of the register class needed for each reload, and make sure that 72 we allocate enough reload registers of each class. 73 74 The file reload.c contains the code that checks one insn for 75 validity and reports the reloads that it needs. This file 76 is in charge of scanning the entire rtl code, accumulating the 77 reload needs, spilling, assigning reload registers to use for 78 fixing up each insn, and generating the new insns to copy values 79 into the reload registers. */ 80 81 struct target_reload default_target_reload; 82 #if SWITCHABLE_TARGET 83 struct target_reload *this_target_reload = &default_target_reload; 84 #endif 85 86 #define spill_indirect_levels \ 87 (this_target_reload->x_spill_indirect_levels) 88 89 /* During reload_as_needed, element N contains a REG rtx for the hard reg 90 into which reg N has been reloaded (perhaps for a previous insn). */ 91 static rtx *reg_last_reload_reg; 92 93 /* Elt N nonzero if reg_last_reload_reg[N] has been set in this insn 94 for an output reload that stores into reg N. */ 95 static regset_head reg_has_output_reload; 96 97 /* Indicates which hard regs are reload-registers for an output reload 98 in the current insn. */ 99 static HARD_REG_SET reg_is_output_reload; 100 101 /* Widest mode in which each pseudo reg is referred to (via subreg). */ 102 static machine_mode *reg_max_ref_mode; 103 104 /* Vector to remember old contents of reg_renumber before spilling. */ 105 static short *reg_old_renumber; 106 107 /* During reload_as_needed, element N contains the last pseudo regno reloaded 108 into hard register N. If that pseudo reg occupied more than one register, 109 reg_reloaded_contents points to that pseudo for each spill register in 110 use; all of these must remain set for an inheritance to occur. */ 111 static int reg_reloaded_contents[FIRST_PSEUDO_REGISTER]; 112 113 /* During reload_as_needed, element N contains the insn for which 114 hard register N was last used. Its contents are significant only 115 when reg_reloaded_valid is set for this register. */ 116 static rtx_insn *reg_reloaded_insn[FIRST_PSEUDO_REGISTER]; 117 118 /* Indicate if reg_reloaded_insn / reg_reloaded_contents is valid. */ 119 static HARD_REG_SET reg_reloaded_valid; 120 /* Indicate if the register was dead at the end of the reload. 121 This is only valid if reg_reloaded_contents is set and valid. */ 122 static HARD_REG_SET reg_reloaded_dead; 123 124 /* Number of spill-regs so far; number of valid elements of spill_regs. */ 125 static int n_spills; 126 127 /* In parallel with spill_regs, contains REG rtx's for those regs. 128 Holds the last rtx used for any given reg, or 0 if it has never 129 been used for spilling yet. This rtx is reused, provided it has 130 the proper mode. */ 131 static rtx spill_reg_rtx[FIRST_PSEUDO_REGISTER]; 132 133 /* In parallel with spill_regs, contains nonzero for a spill reg 134 that was stored after the last time it was used. 135 The precise value is the insn generated to do the store. */ 136 static rtx_insn *spill_reg_store[FIRST_PSEUDO_REGISTER]; 137 138 /* This is the register that was stored with spill_reg_store. This is a 139 copy of reload_out / reload_out_reg when the value was stored; if 140 reload_out is a MEM, spill_reg_stored_to will be set to reload_out_reg. */ 141 static rtx spill_reg_stored_to[FIRST_PSEUDO_REGISTER]; 142 143 /* This table is the inverse mapping of spill_regs: 144 indexed by hard reg number, 145 it contains the position of that reg in spill_regs, 146 or -1 for something that is not in spill_regs. 147 148 ?!? This is no longer accurate. */ 149 static short spill_reg_order[FIRST_PSEUDO_REGISTER]; 150 151 /* This reg set indicates registers that can't be used as spill registers for 152 the currently processed insn. These are the hard registers which are live 153 during the insn, but not allocated to pseudos, as well as fixed 154 registers. */ 155 static HARD_REG_SET bad_spill_regs; 156 157 /* These are the hard registers that can't be used as spill register for any 158 insn. This includes registers used for user variables and registers that 159 we can't eliminate. A register that appears in this set also can't be used 160 to retry register allocation. */ 161 static HARD_REG_SET bad_spill_regs_global; 162 163 /* Describes order of use of registers for reloading 164 of spilled pseudo-registers. `n_spills' is the number of 165 elements that are actually valid; new ones are added at the end. 166 167 Both spill_regs and spill_reg_order are used on two occasions: 168 once during find_reload_regs, where they keep track of the spill registers 169 for a single insn, but also during reload_as_needed where they show all 170 the registers ever used by reload. For the latter case, the information 171 is calculated during finish_spills. */ 172 static short spill_regs[FIRST_PSEUDO_REGISTER]; 173 174 /* This vector of reg sets indicates, for each pseudo, which hard registers 175 may not be used for retrying global allocation because the register was 176 formerly spilled from one of them. If we allowed reallocating a pseudo to 177 a register that it was already allocated to, reload might not 178 terminate. */ 179 static HARD_REG_SET *pseudo_previous_regs; 180 181 /* This vector of reg sets indicates, for each pseudo, which hard 182 registers may not be used for retrying global allocation because they 183 are used as spill registers during one of the insns in which the 184 pseudo is live. */ 185 static HARD_REG_SET *pseudo_forbidden_regs; 186 187 /* All hard regs that have been used as spill registers for any insn are 188 marked in this set. */ 189 static HARD_REG_SET used_spill_regs; 190 191 /* Index of last register assigned as a spill register. We allocate in 192 a round-robin fashion. */ 193 static int last_spill_reg; 194 195 /* Record the stack slot for each spilled hard register. */ 196 static rtx spill_stack_slot[FIRST_PSEUDO_REGISTER]; 197 198 /* Width allocated so far for that stack slot. */ 199 static poly_uint64_pod spill_stack_slot_width[FIRST_PSEUDO_REGISTER]; 200 201 /* Record which pseudos needed to be spilled. */ 202 static regset_head spilled_pseudos; 203 204 /* Record which pseudos changed their allocation in finish_spills. */ 205 static regset_head changed_allocation_pseudos; 206 207 /* Used for communication between order_regs_for_reload and count_pseudo. 208 Used to avoid counting one pseudo twice. */ 209 static regset_head pseudos_counted; 210 211 /* First uid used by insns created by reload in this function. 212 Used in find_equiv_reg. */ 213 int reload_first_uid; 214 215 /* Flag set by local-alloc or global-alloc if anything is live in 216 a call-clobbered reg across calls. */ 217 int caller_save_needed; 218 219 /* Set to 1 while reload_as_needed is operating. 220 Required by some machines to handle any generated moves differently. */ 221 int reload_in_progress = 0; 222 223 /* This obstack is used for allocation of rtl during register elimination. 224 The allocated storage can be freed once find_reloads has processed the 225 insn. */ 226 static struct obstack reload_obstack; 227 228 /* Points to the beginning of the reload_obstack. All insn_chain structures 229 are allocated first. */ 230 static char *reload_startobj; 231 232 /* The point after all insn_chain structures. Used to quickly deallocate 233 memory allocated in copy_reloads during calculate_needs_all_insns. */ 234 static char *reload_firstobj; 235 236 /* This points before all local rtl generated by register elimination. 237 Used to quickly free all memory after processing one insn. */ 238 static char *reload_insn_firstobj; 239 240 /* List of insn_chain instructions, one for every insn that reload needs to 241 examine. */ 242 class insn_chain *reload_insn_chain; 243 244 /* TRUE if we potentially left dead insns in the insn stream and want to 245 run DCE immediately after reload, FALSE otherwise. */ 246 static bool need_dce; 247 248 /* List of all insns needing reloads. */ 249 static class insn_chain *insns_need_reload; 250 251 /* This structure is used to record information about register eliminations. 252 Each array entry describes one possible way of eliminating a register 253 in favor of another. If there is more than one way of eliminating a 254 particular register, the most preferred should be specified first. */ 255 256 struct elim_table 257 { 258 int from; /* Register number to be eliminated. */ 259 int to; /* Register number used as replacement. */ 260 poly_int64_pod initial_offset; /* Initial difference between values. */ 261 int can_eliminate; /* Nonzero if this elimination can be done. */ 262 int can_eliminate_previous; /* Value returned by TARGET_CAN_ELIMINATE 263 target hook in previous scan over insns 264 made by reload. */ 265 poly_int64_pod offset; /* Current offset between the two regs. */ 266 poly_int64_pod previous_offset; /* Offset at end of previous insn. */ 267 int ref_outside_mem; /* "to" has been referenced outside a MEM. */ 268 rtx from_rtx; /* REG rtx for the register to be eliminated. 269 We cannot simply compare the number since 270 we might then spuriously replace a hard 271 register corresponding to a pseudo 272 assigned to the reg to be eliminated. */ 273 rtx to_rtx; /* REG rtx for the replacement. */ 274 }; 275 276 static struct elim_table *reg_eliminate = 0; 277 278 /* This is an intermediate structure to initialize the table. It has 279 exactly the members provided by ELIMINABLE_REGS. */ 280 static const struct elim_table_1 281 { 282 const int from; 283 const int to; 284 } reg_eliminate_1[] = 285 286 ELIMINABLE_REGS; 287 288 #define NUM_ELIMINABLE_REGS ARRAY_SIZE (reg_eliminate_1) 289 290 /* Record the number of pending eliminations that have an offset not equal 291 to their initial offset. If nonzero, we use a new copy of each 292 replacement result in any insns encountered. */ 293 int num_not_at_initial_offset; 294 295 /* Count the number of registers that we may be able to eliminate. */ 296 static int num_eliminable; 297 /* And the number of registers that are equivalent to a constant that 298 can be eliminated to frame_pointer / arg_pointer + constant. */ 299 static int num_eliminable_invariants; 300 301 /* For each label, we record the offset of each elimination. If we reach 302 a label by more than one path and an offset differs, we cannot do the 303 elimination. This information is indexed by the difference of the 304 number of the label and the first label number. We can't offset the 305 pointer itself as this can cause problems on machines with segmented 306 memory. The first table is an array of flags that records whether we 307 have yet encountered a label and the second table is an array of arrays, 308 one entry in the latter array for each elimination. */ 309 310 static int first_label_num; 311 static char *offsets_known_at; 312 static poly_int64_pod (*offsets_at)[NUM_ELIMINABLE_REGS]; 313 314 vec<reg_equivs_t, va_gc> *reg_equivs; 315 316 /* Stack of addresses where an rtx has been changed. We can undo the 317 changes by popping items off the stack and restoring the original 318 value at each location. 319 320 We use this simplistic undo capability rather than copy_rtx as copy_rtx 321 will not make a deep copy of a normally sharable rtx, such as 322 (const (plus (symbol_ref) (const_int))). If such an expression appears 323 as R1 in gen_reload_chain_without_interm_reg_p, then a shared 324 rtx expression would be changed. See PR 42431. */ 325 326 typedef rtx *rtx_p; 327 static vec<rtx_p> substitute_stack; 328 329 /* Number of labels in the current function. */ 330 331 static int num_labels; 332 333 static void replace_pseudos_in (rtx *, machine_mode, rtx); 334 static void maybe_fix_stack_asms (void); 335 static void copy_reloads (class insn_chain *); 336 static void calculate_needs_all_insns (int); 337 static int find_reg (class insn_chain *, int); 338 static void find_reload_regs (class insn_chain *); 339 static void select_reload_regs (void); 340 static void delete_caller_save_insns (void); 341 342 static void spill_failure (rtx_insn *, enum reg_class); 343 static void count_spilled_pseudo (int, int, int); 344 static void delete_dead_insn (rtx_insn *); 345 static void alter_reg (int, int, bool); 346 static void set_label_offsets (rtx, rtx_insn *, int); 347 static void check_eliminable_occurrences (rtx); 348 static void elimination_effects (rtx, machine_mode); 349 static rtx eliminate_regs_1 (rtx, machine_mode, rtx, bool, bool); 350 static int eliminate_regs_in_insn (rtx_insn *, int); 351 static void update_eliminable_offsets (void); 352 static void mark_not_eliminable (rtx, const_rtx, void *); 353 static void set_initial_elim_offsets (void); 354 static bool verify_initial_elim_offsets (void); 355 static void set_initial_label_offsets (void); 356 static void set_offsets_for_label (rtx_insn *); 357 static void init_eliminable_invariants (rtx_insn *, bool); 358 static void init_elim_table (void); 359 static void free_reg_equiv (void); 360 static void update_eliminables (HARD_REG_SET *); 361 static bool update_eliminables_and_spill (void); 362 static void elimination_costs_in_insn (rtx_insn *); 363 static void spill_hard_reg (unsigned int, int); 364 static int finish_spills (int); 365 static void scan_paradoxical_subregs (rtx); 366 static void count_pseudo (int); 367 static void order_regs_for_reload (class insn_chain *); 368 static void reload_as_needed (int); 369 static void forget_old_reloads_1 (rtx, const_rtx, void *); 370 static void forget_marked_reloads (regset); 371 static int reload_reg_class_lower (const void *, const void *); 372 static void mark_reload_reg_in_use (unsigned int, int, enum reload_type, 373 machine_mode); 374 static void clear_reload_reg_in_use (unsigned int, int, enum reload_type, 375 machine_mode); 376 static int reload_reg_free_p (unsigned int, int, enum reload_type); 377 static int reload_reg_free_for_value_p (int, int, int, enum reload_type, 378 rtx, rtx, int, int); 379 static int free_for_value_p (int, machine_mode, int, enum reload_type, 380 rtx, rtx, int, int); 381 static int allocate_reload_reg (class insn_chain *, int, int); 382 static int conflicts_with_override (rtx); 383 static void failed_reload (rtx_insn *, int); 384 static int set_reload_reg (int, int); 385 static void choose_reload_regs_init (class insn_chain *, rtx *); 386 static void choose_reload_regs (class insn_chain *); 387 static void emit_input_reload_insns (class insn_chain *, struct reload *, 388 rtx, int); 389 static void emit_output_reload_insns (class insn_chain *, struct reload *, 390 int); 391 static void do_input_reload (class insn_chain *, struct reload *, int); 392 static void do_output_reload (class insn_chain *, struct reload *, int); 393 static void emit_reload_insns (class insn_chain *); 394 static void delete_output_reload (rtx_insn *, int, int, rtx); 395 static void delete_address_reloads (rtx_insn *, rtx_insn *); 396 static void delete_address_reloads_1 (rtx_insn *, rtx, rtx_insn *); 397 static void inc_for_reload (rtx, rtx, rtx, poly_int64); 398 static void add_auto_inc_notes (rtx_insn *, rtx); 399 static void substitute (rtx *, const_rtx, rtx); 400 static bool gen_reload_chain_without_interm_reg_p (int, int); 401 static int reloads_conflict (int, int); 402 static rtx_insn *gen_reload (rtx, rtx, int, enum reload_type); 403 static rtx_insn *emit_insn_if_valid_for_reload (rtx); 404 405 /* Initialize the reload pass. This is called at the beginning of compilation 406 and may be called again if the target is reinitialized. */ 407 408 void 409 init_reload (void) 410 { 411 int i; 412 413 /* Often (MEM (REG n)) is still valid even if (REG n) is put on the stack. 414 Set spill_indirect_levels to the number of levels such addressing is 415 permitted, zero if it is not permitted at all. */ 416 417 rtx tem 418 = gen_rtx_MEM (Pmode, 419 gen_rtx_PLUS (Pmode, 420 gen_rtx_REG (Pmode, 421 LAST_VIRTUAL_REGISTER + 1), 422 gen_int_mode (4, Pmode))); 423 spill_indirect_levels = 0; 424 425 while (memory_address_p (QImode, tem)) 426 { 427 spill_indirect_levels++; 428 tem = gen_rtx_MEM (Pmode, tem); 429 } 430 431 /* See if indirect addressing is valid for (MEM (SYMBOL_REF ...)). */ 432 433 tem = gen_rtx_MEM (Pmode, gen_rtx_SYMBOL_REF (Pmode, "foo")); 434 indirect_symref_ok = memory_address_p (QImode, tem); 435 436 /* See if reg+reg is a valid (and offsettable) address. */ 437 438 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 439 { 440 tem = gen_rtx_PLUS (Pmode, 441 gen_rtx_REG (Pmode, HARD_FRAME_POINTER_REGNUM), 442 gen_rtx_REG (Pmode, i)); 443 444 /* This way, we make sure that reg+reg is an offsettable address. */ 445 tem = plus_constant (Pmode, tem, 4); 446 447 for (int mode = 0; mode < MAX_MACHINE_MODE; mode++) 448 if (!double_reg_address_ok[mode] 449 && memory_address_p ((enum machine_mode)mode, tem)) 450 double_reg_address_ok[mode] = 1; 451 } 452 453 /* Initialize obstack for our rtl allocation. */ 454 if (reload_startobj == NULL) 455 { 456 gcc_obstack_init (&reload_obstack); 457 reload_startobj = XOBNEWVAR (&reload_obstack, char, 0); 458 } 459 460 INIT_REG_SET (&spilled_pseudos); 461 INIT_REG_SET (&changed_allocation_pseudos); 462 INIT_REG_SET (&pseudos_counted); 463 } 464 465 /* List of insn chains that are currently unused. */ 466 static class insn_chain *unused_insn_chains = 0; 467 468 /* Allocate an empty insn_chain structure. */ 469 class insn_chain * 470 new_insn_chain (void) 471 { 472 class insn_chain *c; 473 474 if (unused_insn_chains == 0) 475 { 476 c = XOBNEW (&reload_obstack, class insn_chain); 477 INIT_REG_SET (&c->live_throughout); 478 INIT_REG_SET (&c->dead_or_set); 479 } 480 else 481 { 482 c = unused_insn_chains; 483 unused_insn_chains = c->next; 484 } 485 c->is_caller_save_insn = 0; 486 c->need_operand_change = 0; 487 c->need_reload = 0; 488 c->need_elim = 0; 489 return c; 490 } 491 492 /* Small utility function to set all regs in hard reg set TO which are 493 allocated to pseudos in regset FROM. */ 494 495 void 496 compute_use_by_pseudos (HARD_REG_SET *to, regset from) 497 { 498 unsigned int regno; 499 reg_set_iterator rsi; 500 501 EXECUTE_IF_SET_IN_REG_SET (from, FIRST_PSEUDO_REGISTER, regno, rsi) 502 { 503 int r = reg_renumber[regno]; 504 505 if (r < 0) 506 { 507 /* reload_combine uses the information from DF_LIVE_IN, 508 which might still contain registers that have not 509 actually been allocated since they have an 510 equivalence. */ 511 gcc_assert (ira_conflicts_p || reload_completed); 512 } 513 else 514 add_to_hard_reg_set (to, PSEUDO_REGNO_MODE (regno), r); 515 } 516 } 517 518 /* Replace all pseudos found in LOC with their corresponding 519 equivalences. */ 520 521 static void 522 replace_pseudos_in (rtx *loc, machine_mode mem_mode, rtx usage) 523 { 524 rtx x = *loc; 525 enum rtx_code code; 526 const char *fmt; 527 int i, j; 528 529 if (! x) 530 return; 531 532 code = GET_CODE (x); 533 if (code == REG) 534 { 535 unsigned int regno = REGNO (x); 536 537 if (regno < FIRST_PSEUDO_REGISTER) 538 return; 539 540 x = eliminate_regs_1 (x, mem_mode, usage, true, false); 541 if (x != *loc) 542 { 543 *loc = x; 544 replace_pseudos_in (loc, mem_mode, usage); 545 return; 546 } 547 548 if (reg_equiv_constant (regno)) 549 *loc = reg_equiv_constant (regno); 550 else if (reg_equiv_invariant (regno)) 551 *loc = reg_equiv_invariant (regno); 552 else if (reg_equiv_mem (regno)) 553 *loc = reg_equiv_mem (regno); 554 else if (reg_equiv_address (regno)) 555 *loc = gen_rtx_MEM (GET_MODE (x), reg_equiv_address (regno)); 556 else 557 { 558 gcc_assert (!REG_P (regno_reg_rtx[regno]) 559 || REGNO (regno_reg_rtx[regno]) != regno); 560 *loc = regno_reg_rtx[regno]; 561 } 562 563 return; 564 } 565 else if (code == MEM) 566 { 567 replace_pseudos_in (& XEXP (x, 0), GET_MODE (x), usage); 568 return; 569 } 570 571 /* Process each of our operands recursively. */ 572 fmt = GET_RTX_FORMAT (code); 573 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 574 if (*fmt == 'e') 575 replace_pseudos_in (&XEXP (x, i), mem_mode, usage); 576 else if (*fmt == 'E') 577 for (j = 0; j < XVECLEN (x, i); j++) 578 replace_pseudos_in (& XVECEXP (x, i, j), mem_mode, usage); 579 } 580 581 /* Determine if the current function has an exception receiver block 582 that reaches the exit block via non-exceptional edges */ 583 584 static bool 585 has_nonexceptional_receiver (void) 586 { 587 edge e; 588 edge_iterator ei; 589 basic_block *tos, *worklist, bb; 590 591 /* If we're not optimizing, then just err on the safe side. */ 592 if (!optimize) 593 return true; 594 595 /* First determine which blocks can reach exit via normal paths. */ 596 tos = worklist = XNEWVEC (basic_block, n_basic_blocks_for_fn (cfun) + 1); 597 598 FOR_EACH_BB_FN (bb, cfun) 599 bb->flags &= ~BB_REACHABLE; 600 601 /* Place the exit block on our worklist. */ 602 EXIT_BLOCK_PTR_FOR_FN (cfun)->flags |= BB_REACHABLE; 603 *tos++ = EXIT_BLOCK_PTR_FOR_FN (cfun); 604 605 /* Iterate: find everything reachable from what we've already seen. */ 606 while (tos != worklist) 607 { 608 bb = *--tos; 609 610 FOR_EACH_EDGE (e, ei, bb->preds) 611 if (!(e->flags & EDGE_ABNORMAL)) 612 { 613 basic_block src = e->src; 614 615 if (!(src->flags & BB_REACHABLE)) 616 { 617 src->flags |= BB_REACHABLE; 618 *tos++ = src; 619 } 620 } 621 } 622 free (worklist); 623 624 /* Now see if there's a reachable block with an exceptional incoming 625 edge. */ 626 FOR_EACH_BB_FN (bb, cfun) 627 if (bb->flags & BB_REACHABLE && bb_has_abnormal_pred (bb)) 628 return true; 629 630 /* No exceptional block reached exit unexceptionally. */ 631 return false; 632 } 633 634 /* Grow (or allocate) the REG_EQUIVS array from its current size (which may be 635 zero elements) to MAX_REG_NUM elements. 636 637 Initialize all new fields to NULL and update REG_EQUIVS_SIZE. */ 638 void 639 grow_reg_equivs (void) 640 { 641 int old_size = vec_safe_length (reg_equivs); 642 int max_regno = max_reg_num (); 643 int i; 644 reg_equivs_t ze; 645 646 memset (&ze, 0, sizeof (reg_equivs_t)); 647 vec_safe_reserve (reg_equivs, max_regno); 648 for (i = old_size; i < max_regno; i++) 649 reg_equivs->quick_insert (i, ze); 650 } 651 652 653 /* Global variables used by reload and its subroutines. */ 654 655 /* The current basic block while in calculate_elim_costs_all_insns. */ 656 static basic_block elim_bb; 657 658 /* Set during calculate_needs if an insn needs register elimination. */ 659 static int something_needs_elimination; 660 /* Set during calculate_needs if an insn needs an operand changed. */ 661 static int something_needs_operands_changed; 662 /* Set by alter_regs if we spilled a register to the stack. */ 663 static bool something_was_spilled; 664 665 /* Nonzero means we couldn't get enough spill regs. */ 666 static int failure; 667 668 /* Temporary array of pseudo-register number. */ 669 static int *temp_pseudo_reg_arr; 670 671 /* If a pseudo has no hard reg, delete the insns that made the equivalence. 672 If that insn didn't set the register (i.e., it copied the register to 673 memory), just delete that insn instead of the equivalencing insn plus 674 anything now dead. If we call delete_dead_insn on that insn, we may 675 delete the insn that actually sets the register if the register dies 676 there and that is incorrect. */ 677 static void 678 remove_init_insns () 679 { 680 for (int i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 681 { 682 if (reg_renumber[i] < 0 && reg_equiv_init (i) != 0) 683 { 684 rtx list; 685 for (list = reg_equiv_init (i); list; list = XEXP (list, 1)) 686 { 687 rtx_insn *equiv_insn = as_a <rtx_insn *> (XEXP (list, 0)); 688 689 /* If we already deleted the insn or if it may trap, we can't 690 delete it. The latter case shouldn't happen, but can 691 if an insn has a variable address, gets a REG_EH_REGION 692 note added to it, and then gets converted into a load 693 from a constant address. */ 694 if (NOTE_P (equiv_insn) 695 || can_throw_internal (equiv_insn)) 696 ; 697 else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn))) 698 delete_dead_insn (equiv_insn); 699 else 700 SET_INSN_DELETED (equiv_insn); 701 } 702 } 703 } 704 } 705 706 /* Return true if remove_init_insns will delete INSN. */ 707 static bool 708 will_delete_init_insn_p (rtx_insn *insn) 709 { 710 rtx set = single_set (insn); 711 if (!set || !REG_P (SET_DEST (set))) 712 return false; 713 unsigned regno = REGNO (SET_DEST (set)); 714 715 if (can_throw_internal (insn)) 716 return false; 717 718 if (regno < FIRST_PSEUDO_REGISTER || reg_renumber[regno] >= 0) 719 return false; 720 721 for (rtx list = reg_equiv_init (regno); list; list = XEXP (list, 1)) 722 { 723 rtx equiv_insn = XEXP (list, 0); 724 if (equiv_insn == insn) 725 return true; 726 } 727 return false; 728 } 729 730 /* Main entry point for the reload pass. 731 732 FIRST is the first insn of the function being compiled. 733 734 GLOBAL nonzero means we were called from global_alloc 735 and should attempt to reallocate any pseudoregs that we 736 displace from hard regs we will use for reloads. 737 If GLOBAL is zero, we do not have enough information to do that, 738 so any pseudo reg that is spilled must go to the stack. 739 740 Return value is TRUE if reload likely left dead insns in the 741 stream and a DCE pass should be run to elimiante them. Else the 742 return value is FALSE. */ 743 744 bool 745 reload (rtx_insn *first, int global) 746 { 747 int i, n; 748 rtx_insn *insn; 749 struct elim_table *ep; 750 basic_block bb; 751 bool inserted; 752 753 /* Make sure even insns with volatile mem refs are recognizable. */ 754 init_recog (); 755 756 failure = 0; 757 758 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0); 759 760 /* Make sure that the last insn in the chain 761 is not something that needs reloading. */ 762 emit_note (NOTE_INSN_DELETED); 763 764 /* Enable find_equiv_reg to distinguish insns made by reload. */ 765 reload_first_uid = get_max_uid (); 766 767 /* Initialize the secondary memory table. */ 768 clear_secondary_mem (); 769 770 /* We don't have a stack slot for any spill reg yet. */ 771 memset (spill_stack_slot, 0, sizeof spill_stack_slot); 772 memset (spill_stack_slot_width, 0, sizeof spill_stack_slot_width); 773 774 /* Initialize the save area information for caller-save, in case some 775 are needed. */ 776 init_save_areas (); 777 778 /* Compute which hard registers are now in use 779 as homes for pseudo registers. 780 This is done here rather than (eg) in global_alloc 781 because this point is reached even if not optimizing. */ 782 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 783 mark_home_live (i); 784 785 /* A function that has a nonlocal label that can reach the exit 786 block via non-exceptional paths must save all call-saved 787 registers. */ 788 if (cfun->has_nonlocal_label 789 && has_nonexceptional_receiver ()) 790 crtl->saves_all_registers = 1; 791 792 if (crtl->saves_all_registers) 793 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 794 if (! crtl->abi->clobbers_full_reg_p (i) 795 && ! fixed_regs[i] 796 && ! LOCAL_REGNO (i)) 797 df_set_regs_ever_live (i, true); 798 799 /* Find all the pseudo registers that didn't get hard regs 800 but do have known equivalent constants or memory slots. 801 These include parameters (known equivalent to parameter slots) 802 and cse'd or loop-moved constant memory addresses. 803 804 Record constant equivalents in reg_equiv_constant 805 so they will be substituted by find_reloads. 806 Record memory equivalents in reg_mem_equiv so they can 807 be substituted eventually by altering the REG-rtx's. */ 808 809 grow_reg_equivs (); 810 reg_old_renumber = XCNEWVEC (short, max_regno); 811 memcpy (reg_old_renumber, reg_renumber, max_regno * sizeof (short)); 812 pseudo_forbidden_regs = XNEWVEC (HARD_REG_SET, max_regno); 813 pseudo_previous_regs = XCNEWVEC (HARD_REG_SET, max_regno); 814 815 CLEAR_HARD_REG_SET (bad_spill_regs_global); 816 817 init_eliminable_invariants (first, true); 818 init_elim_table (); 819 820 /* Alter each pseudo-reg rtx to contain its hard reg number. Assign 821 stack slots to the pseudos that lack hard regs or equivalents. 822 Do not touch virtual registers. */ 823 824 temp_pseudo_reg_arr = XNEWVEC (int, max_regno - LAST_VIRTUAL_REGISTER - 1); 825 for (n = 0, i = LAST_VIRTUAL_REGISTER + 1; i < max_regno; i++) 826 temp_pseudo_reg_arr[n++] = i; 827 828 if (ira_conflicts_p) 829 /* Ask IRA to order pseudo-registers for better stack slot 830 sharing. */ 831 ira_sort_regnos_for_alter_reg (temp_pseudo_reg_arr, n, reg_max_ref_mode); 832 833 for (i = 0; i < n; i++) 834 alter_reg (temp_pseudo_reg_arr[i], -1, false); 835 836 /* If we have some registers we think can be eliminated, scan all insns to 837 see if there is an insn that sets one of these registers to something 838 other than itself plus a constant. If so, the register cannot be 839 eliminated. Doing this scan here eliminates an extra pass through the 840 main reload loop in the most common case where register elimination 841 cannot be done. */ 842 for (insn = first; insn && num_eliminable; insn = NEXT_INSN (insn)) 843 if (INSN_P (insn)) 844 note_pattern_stores (PATTERN (insn), mark_not_eliminable, NULL); 845 846 maybe_fix_stack_asms (); 847 848 insns_need_reload = 0; 849 something_needs_elimination = 0; 850 851 /* Initialize to -1, which means take the first spill register. */ 852 last_spill_reg = -1; 853 854 /* Spill any hard regs that we know we can't eliminate. */ 855 CLEAR_HARD_REG_SET (used_spill_regs); 856 /* There can be multiple ways to eliminate a register; 857 they should be listed adjacently. 858 Elimination for any register fails only if all possible ways fail. */ 859 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ) 860 { 861 int from = ep->from; 862 int can_eliminate = 0; 863 do 864 { 865 can_eliminate |= ep->can_eliminate; 866 ep++; 867 } 868 while (ep < ®_eliminate[NUM_ELIMINABLE_REGS] && ep->from == from); 869 if (! can_eliminate) 870 spill_hard_reg (from, 1); 871 } 872 873 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER && frame_pointer_needed) 874 spill_hard_reg (HARD_FRAME_POINTER_REGNUM, 1); 875 876 finish_spills (global); 877 878 /* From now on, we may need to generate moves differently. We may also 879 allow modifications of insns which cause them to not be recognized. 880 Any such modifications will be cleaned up during reload itself. */ 881 reload_in_progress = 1; 882 883 /* This loop scans the entire function each go-round 884 and repeats until one repetition spills no additional hard regs. */ 885 for (;;) 886 { 887 int something_changed; 888 poly_int64 starting_frame_size; 889 890 starting_frame_size = get_frame_size (); 891 something_was_spilled = false; 892 893 set_initial_elim_offsets (); 894 set_initial_label_offsets (); 895 896 /* For each pseudo register that has an equivalent location defined, 897 try to eliminate any eliminable registers (such as the frame pointer) 898 assuming initial offsets for the replacement register, which 899 is the normal case. 900 901 If the resulting location is directly addressable, substitute 902 the MEM we just got directly for the old REG. 903 904 If it is not addressable but is a constant or the sum of a hard reg 905 and constant, it is probably not addressable because the constant is 906 out of range, in that case record the address; we will generate 907 hairy code to compute the address in a register each time it is 908 needed. Similarly if it is a hard register, but one that is not 909 valid as an address register. 910 911 If the location is not addressable, but does not have one of the 912 above forms, assign a stack slot. We have to do this to avoid the 913 potential of producing lots of reloads if, e.g., a location involves 914 a pseudo that didn't get a hard register and has an equivalent memory 915 location that also involves a pseudo that didn't get a hard register. 916 917 Perhaps at some point we will improve reload_when_needed handling 918 so this problem goes away. But that's very hairy. */ 919 920 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 921 if (reg_renumber[i] < 0 && reg_equiv_memory_loc (i)) 922 { 923 rtx x = eliminate_regs (reg_equiv_memory_loc (i), VOIDmode, 924 NULL_RTX); 925 926 if (strict_memory_address_addr_space_p 927 (GET_MODE (regno_reg_rtx[i]), XEXP (x, 0), 928 MEM_ADDR_SPACE (x))) 929 reg_equiv_mem (i) = x, reg_equiv_address (i) = 0; 930 else if (CONSTANT_P (XEXP (x, 0)) 931 || (REG_P (XEXP (x, 0)) 932 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER) 933 || (GET_CODE (XEXP (x, 0)) == PLUS 934 && REG_P (XEXP (XEXP (x, 0), 0)) 935 && (REGNO (XEXP (XEXP (x, 0), 0)) 936 < FIRST_PSEUDO_REGISTER) 937 && CONSTANT_P (XEXP (XEXP (x, 0), 1)))) 938 reg_equiv_address (i) = XEXP (x, 0), reg_equiv_mem (i) = 0; 939 else 940 { 941 /* Make a new stack slot. Then indicate that something 942 changed so we go back and recompute offsets for 943 eliminable registers because the allocation of memory 944 below might change some offset. reg_equiv_{mem,address} 945 will be set up for this pseudo on the next pass around 946 the loop. */ 947 reg_equiv_memory_loc (i) = 0; 948 reg_equiv_init (i) = 0; 949 alter_reg (i, -1, true); 950 } 951 } 952 953 if (caller_save_needed) 954 setup_save_areas (); 955 956 if (maybe_ne (starting_frame_size, 0) && crtl->stack_alignment_needed) 957 { 958 /* If we have a stack frame, we must align it now. The 959 stack size may be a part of the offset computation for 960 register elimination. So if this changes the stack size, 961 then repeat the elimination bookkeeping. We don't 962 realign when there is no stack, as that will cause a 963 stack frame when none is needed should 964 TARGET_STARTING_FRAME_OFFSET not be already aligned to 965 STACK_BOUNDARY. */ 966 assign_stack_local (BLKmode, 0, crtl->stack_alignment_needed); 967 } 968 /* If we allocated another stack slot, redo elimination bookkeeping. */ 969 if (something_was_spilled 970 || maybe_ne (starting_frame_size, get_frame_size ())) 971 { 972 if (update_eliminables_and_spill ()) 973 finish_spills (0); 974 continue; 975 } 976 977 if (caller_save_needed) 978 { 979 save_call_clobbered_regs (); 980 /* That might have allocated new insn_chain structures. */ 981 reload_firstobj = XOBNEWVAR (&reload_obstack, char, 0); 982 } 983 984 calculate_needs_all_insns (global); 985 986 if (! ira_conflicts_p) 987 /* Don't do it for IRA. We need this info because we don't 988 change live_throughout and dead_or_set for chains when IRA 989 is used. */ 990 CLEAR_REG_SET (&spilled_pseudos); 991 992 something_changed = 0; 993 994 /* If we allocated any new memory locations, make another pass 995 since it might have changed elimination offsets. */ 996 if (something_was_spilled 997 || maybe_ne (starting_frame_size, get_frame_size ())) 998 something_changed = 1; 999 1000 /* Even if the frame size remained the same, we might still have 1001 changed elimination offsets, e.g. if find_reloads called 1002 force_const_mem requiring the back end to allocate a constant 1003 pool base register that needs to be saved on the stack. */ 1004 else if (!verify_initial_elim_offsets ()) 1005 something_changed = 1; 1006 1007 if (update_eliminables_and_spill ()) 1008 { 1009 finish_spills (0); 1010 something_changed = 1; 1011 } 1012 else 1013 { 1014 select_reload_regs (); 1015 if (failure) 1016 goto failed; 1017 if (insns_need_reload) 1018 something_changed |= finish_spills (global); 1019 } 1020 1021 if (! something_changed) 1022 break; 1023 1024 if (caller_save_needed) 1025 delete_caller_save_insns (); 1026 1027 obstack_free (&reload_obstack, reload_firstobj); 1028 } 1029 1030 /* If global-alloc was run, notify it of any register eliminations we have 1031 done. */ 1032 if (global) 1033 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 1034 if (ep->can_eliminate) 1035 mark_elimination (ep->from, ep->to); 1036 1037 remove_init_insns (); 1038 1039 /* Use the reload registers where necessary 1040 by generating move instructions to move the must-be-register 1041 values into or out of the reload registers. */ 1042 1043 if (insns_need_reload != 0 || something_needs_elimination 1044 || something_needs_operands_changed) 1045 { 1046 poly_int64 old_frame_size = get_frame_size (); 1047 1048 reload_as_needed (global); 1049 1050 gcc_assert (known_eq (old_frame_size, get_frame_size ())); 1051 1052 gcc_assert (verify_initial_elim_offsets ()); 1053 } 1054 1055 /* If we were able to eliminate the frame pointer, show that it is no 1056 longer live at the start of any basic block. If it ls live by 1057 virtue of being in a pseudo, that pseudo will be marked live 1058 and hence the frame pointer will be known to be live via that 1059 pseudo. */ 1060 1061 if (! frame_pointer_needed) 1062 FOR_EACH_BB_FN (bb, cfun) 1063 bitmap_clear_bit (df_get_live_in (bb), HARD_FRAME_POINTER_REGNUM); 1064 1065 /* Come here (with failure set nonzero) if we can't get enough spill 1066 regs. */ 1067 failed: 1068 1069 CLEAR_REG_SET (&changed_allocation_pseudos); 1070 CLEAR_REG_SET (&spilled_pseudos); 1071 reload_in_progress = 0; 1072 1073 /* Now eliminate all pseudo regs by modifying them into 1074 their equivalent memory references. 1075 The REG-rtx's for the pseudos are modified in place, 1076 so all insns that used to refer to them now refer to memory. 1077 1078 For a reg that has a reg_equiv_address, all those insns 1079 were changed by reloading so that no insns refer to it any longer; 1080 but the DECL_RTL of a variable decl may refer to it, 1081 and if so this causes the debugging info to mention the variable. */ 1082 1083 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 1084 { 1085 rtx addr = 0; 1086 1087 if (reg_equiv_mem (i)) 1088 addr = XEXP (reg_equiv_mem (i), 0); 1089 1090 if (reg_equiv_address (i)) 1091 addr = reg_equiv_address (i); 1092 1093 if (addr) 1094 { 1095 if (reg_renumber[i] < 0) 1096 { 1097 rtx reg = regno_reg_rtx[i]; 1098 1099 REG_USERVAR_P (reg) = 0; 1100 PUT_CODE (reg, MEM); 1101 XEXP (reg, 0) = addr; 1102 if (reg_equiv_memory_loc (i)) 1103 MEM_COPY_ATTRIBUTES (reg, reg_equiv_memory_loc (i)); 1104 else 1105 MEM_ATTRS (reg) = 0; 1106 MEM_NOTRAP_P (reg) = 1; 1107 } 1108 else if (reg_equiv_mem (i)) 1109 XEXP (reg_equiv_mem (i), 0) = addr; 1110 } 1111 1112 /* We don't want complex addressing modes in debug insns 1113 if simpler ones will do, so delegitimize equivalences 1114 in debug insns. */ 1115 if (MAY_HAVE_DEBUG_BIND_INSNS && reg_renumber[i] < 0) 1116 { 1117 rtx reg = regno_reg_rtx[i]; 1118 rtx equiv = 0; 1119 df_ref use, next; 1120 1121 if (reg_equiv_constant (i)) 1122 equiv = reg_equiv_constant (i); 1123 else if (reg_equiv_invariant (i)) 1124 equiv = reg_equiv_invariant (i); 1125 else if (reg && MEM_P (reg)) 1126 equiv = targetm.delegitimize_address (reg); 1127 else if (reg && REG_P (reg) && (int)REGNO (reg) != i) 1128 equiv = reg; 1129 1130 if (equiv == reg) 1131 continue; 1132 1133 for (use = DF_REG_USE_CHAIN (i); use; use = next) 1134 { 1135 insn = DF_REF_INSN (use); 1136 1137 /* Make sure the next ref is for a different instruction, 1138 so that we're not affected by the rescan. */ 1139 next = DF_REF_NEXT_REG (use); 1140 while (next && DF_REF_INSN (next) == insn) 1141 next = DF_REF_NEXT_REG (next); 1142 1143 if (DEBUG_BIND_INSN_P (insn)) 1144 { 1145 if (!equiv) 1146 { 1147 INSN_VAR_LOCATION_LOC (insn) = gen_rtx_UNKNOWN_VAR_LOC (); 1148 df_insn_rescan_debug_internal (insn); 1149 } 1150 else 1151 INSN_VAR_LOCATION_LOC (insn) 1152 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (insn), 1153 reg, equiv); 1154 } 1155 } 1156 } 1157 } 1158 1159 /* We must set reload_completed now since the cleanup_subreg_operands call 1160 below will re-recognize each insn and reload may have generated insns 1161 which are only valid during and after reload. */ 1162 reload_completed = 1; 1163 1164 /* Make a pass over all the insns and delete all USEs which we inserted 1165 only to tag a REG_EQUAL note on them. Remove all REG_DEAD and REG_UNUSED 1166 notes. Delete all CLOBBER insns, except those that refer to the return 1167 value and the special mem:BLK CLOBBERs added to prevent the scheduler 1168 from misarranging variable-array code, and simplify (subreg (reg)) 1169 operands. Strip and regenerate REG_INC notes that may have been moved 1170 around. */ 1171 1172 for (insn = first; insn; insn = NEXT_INSN (insn)) 1173 if (INSN_P (insn)) 1174 { 1175 rtx *pnote; 1176 1177 if (CALL_P (insn)) 1178 replace_pseudos_in (& CALL_INSN_FUNCTION_USAGE (insn), 1179 VOIDmode, CALL_INSN_FUNCTION_USAGE (insn)); 1180 1181 if ((GET_CODE (PATTERN (insn)) == USE 1182 /* We mark with QImode USEs introduced by reload itself. */ 1183 && (GET_MODE (insn) == QImode 1184 || find_reg_note (insn, REG_EQUAL, NULL_RTX))) 1185 || (GET_CODE (PATTERN (insn)) == CLOBBER 1186 && (!MEM_P (XEXP (PATTERN (insn), 0)) 1187 || GET_MODE (XEXP (PATTERN (insn), 0)) != BLKmode 1188 || (GET_CODE (XEXP (XEXP (PATTERN (insn), 0), 0)) != SCRATCH 1189 && XEXP (XEXP (PATTERN (insn), 0), 0) 1190 != stack_pointer_rtx)) 1191 && (!REG_P (XEXP (PATTERN (insn), 0)) 1192 || ! REG_FUNCTION_VALUE_P (XEXP (PATTERN (insn), 0))))) 1193 { 1194 delete_insn (insn); 1195 continue; 1196 } 1197 1198 /* Some CLOBBERs may survive until here and still reference unassigned 1199 pseudos with const equivalent, which may in turn cause ICE in later 1200 passes if the reference remains in place. */ 1201 if (GET_CODE (PATTERN (insn)) == CLOBBER) 1202 replace_pseudos_in (& XEXP (PATTERN (insn), 0), 1203 VOIDmode, PATTERN (insn)); 1204 1205 /* Discard obvious no-ops, even without -O. This optimization 1206 is fast and doesn't interfere with debugging. */ 1207 if (NONJUMP_INSN_P (insn) 1208 && GET_CODE (PATTERN (insn)) == SET 1209 && REG_P (SET_SRC (PATTERN (insn))) 1210 && REG_P (SET_DEST (PATTERN (insn))) 1211 && (REGNO (SET_SRC (PATTERN (insn))) 1212 == REGNO (SET_DEST (PATTERN (insn))))) 1213 { 1214 delete_insn (insn); 1215 continue; 1216 } 1217 1218 pnote = ®_NOTES (insn); 1219 while (*pnote != 0) 1220 { 1221 if (REG_NOTE_KIND (*pnote) == REG_DEAD 1222 || REG_NOTE_KIND (*pnote) == REG_UNUSED 1223 || REG_NOTE_KIND (*pnote) == REG_INC) 1224 *pnote = XEXP (*pnote, 1); 1225 else 1226 pnote = &XEXP (*pnote, 1); 1227 } 1228 1229 if (AUTO_INC_DEC) 1230 add_auto_inc_notes (insn, PATTERN (insn)); 1231 1232 /* Simplify (subreg (reg)) if it appears as an operand. */ 1233 cleanup_subreg_operands (insn); 1234 1235 /* Clean up invalid ASMs so that they don't confuse later passes. 1236 See PR 21299. */ 1237 if (asm_noperands (PATTERN (insn)) >= 0) 1238 { 1239 extract_insn (insn); 1240 if (!constrain_operands (1, get_enabled_alternatives (insn))) 1241 { 1242 error_for_asm (insn, 1243 "%<asm%> operand has impossible constraints"); 1244 delete_insn (insn); 1245 continue; 1246 } 1247 } 1248 } 1249 1250 free (temp_pseudo_reg_arr); 1251 1252 /* Indicate that we no longer have known memory locations or constants. */ 1253 free_reg_equiv (); 1254 1255 free (reg_max_ref_mode); 1256 free (reg_old_renumber); 1257 free (pseudo_previous_regs); 1258 free (pseudo_forbidden_regs); 1259 1260 CLEAR_HARD_REG_SET (used_spill_regs); 1261 for (i = 0; i < n_spills; i++) 1262 SET_HARD_REG_BIT (used_spill_regs, spill_regs[i]); 1263 1264 /* Free all the insn_chain structures at once. */ 1265 obstack_free (&reload_obstack, reload_startobj); 1266 unused_insn_chains = 0; 1267 1268 inserted = fixup_abnormal_edges (); 1269 1270 /* We've possibly turned single trapping insn into multiple ones. */ 1271 if (cfun->can_throw_non_call_exceptions) 1272 { 1273 auto_sbitmap blocks (last_basic_block_for_fn (cfun)); 1274 bitmap_ones (blocks); 1275 find_many_sub_basic_blocks (blocks); 1276 } 1277 1278 if (inserted) 1279 commit_edge_insertions (); 1280 1281 /* Replacing pseudos with their memory equivalents might have 1282 created shared rtx. Subsequent passes would get confused 1283 by this, so unshare everything here. */ 1284 unshare_all_rtl_again (first); 1285 1286 #ifdef STACK_BOUNDARY 1287 /* init_emit has set the alignment of the hard frame pointer 1288 to STACK_BOUNDARY. It is very likely no longer valid if 1289 the hard frame pointer was used for register allocation. */ 1290 if (!frame_pointer_needed) 1291 REGNO_POINTER_ALIGN (HARD_FRAME_POINTER_REGNUM) = BITS_PER_UNIT; 1292 #endif 1293 1294 substitute_stack.release (); 1295 1296 gcc_assert (bitmap_empty_p (&spilled_pseudos)); 1297 1298 reload_completed = !failure; 1299 1300 return need_dce; 1301 } 1302 1303 /* Yet another special case. Unfortunately, reg-stack forces people to 1304 write incorrect clobbers in asm statements. These clobbers must not 1305 cause the register to appear in bad_spill_regs, otherwise we'll call 1306 fatal_insn later. We clear the corresponding regnos in the live 1307 register sets to avoid this. 1308 The whole thing is rather sick, I'm afraid. */ 1309 1310 static void 1311 maybe_fix_stack_asms (void) 1312 { 1313 #ifdef STACK_REGS 1314 const char *constraints[MAX_RECOG_OPERANDS]; 1315 machine_mode operand_mode[MAX_RECOG_OPERANDS]; 1316 class insn_chain *chain; 1317 1318 for (chain = reload_insn_chain; chain != 0; chain = chain->next) 1319 { 1320 int i, noperands; 1321 HARD_REG_SET clobbered, allowed; 1322 rtx pat; 1323 1324 if (! INSN_P (chain->insn) 1325 || (noperands = asm_noperands (PATTERN (chain->insn))) < 0) 1326 continue; 1327 pat = PATTERN (chain->insn); 1328 if (GET_CODE (pat) != PARALLEL) 1329 continue; 1330 1331 CLEAR_HARD_REG_SET (clobbered); 1332 CLEAR_HARD_REG_SET (allowed); 1333 1334 /* First, make a mask of all stack regs that are clobbered. */ 1335 for (i = 0; i < XVECLEN (pat, 0); i++) 1336 { 1337 rtx t = XVECEXP (pat, 0, i); 1338 if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) 1339 SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); 1340 } 1341 1342 /* Get the operand values and constraints out of the insn. */ 1343 decode_asm_operands (pat, recog_data.operand, recog_data.operand_loc, 1344 constraints, operand_mode, NULL); 1345 1346 /* For every operand, see what registers are allowed. */ 1347 for (i = 0; i < noperands; i++) 1348 { 1349 const char *p = constraints[i]; 1350 /* For every alternative, we compute the class of registers allowed 1351 for reloading in CLS, and merge its contents into the reg set 1352 ALLOWED. */ 1353 int cls = (int) NO_REGS; 1354 1355 for (;;) 1356 { 1357 char c = *p; 1358 1359 if (c == '\0' || c == ',' || c == '#') 1360 { 1361 /* End of one alternative - mark the regs in the current 1362 class, and reset the class. */ 1363 allowed |= reg_class_contents[cls]; 1364 cls = NO_REGS; 1365 p++; 1366 if (c == '#') 1367 do { 1368 c = *p++; 1369 } while (c != '\0' && c != ','); 1370 if (c == '\0') 1371 break; 1372 continue; 1373 } 1374 1375 switch (c) 1376 { 1377 case 'g': 1378 cls = (int) reg_class_subunion[cls][(int) GENERAL_REGS]; 1379 break; 1380 1381 default: 1382 enum constraint_num cn = lookup_constraint (p); 1383 if (insn_extra_address_constraint (cn)) 1384 cls = (int) reg_class_subunion[cls] 1385 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 1386 ADDRESS, SCRATCH)]; 1387 else 1388 cls = (int) reg_class_subunion[cls] 1389 [reg_class_for_constraint (cn)]; 1390 break; 1391 } 1392 p += CONSTRAINT_LEN (c, p); 1393 } 1394 } 1395 /* Those of the registers which are clobbered, but allowed by the 1396 constraints, must be usable as reload registers. So clear them 1397 out of the life information. */ 1398 allowed &= clobbered; 1399 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1400 if (TEST_HARD_REG_BIT (allowed, i)) 1401 { 1402 CLEAR_REGNO_REG_SET (&chain->live_throughout, i); 1403 CLEAR_REGNO_REG_SET (&chain->dead_or_set, i); 1404 } 1405 } 1406 1407 #endif 1408 } 1409 1410 /* Copy the global variables n_reloads and rld into the corresponding elts 1411 of CHAIN. */ 1412 static void 1413 copy_reloads (class insn_chain *chain) 1414 { 1415 chain->n_reloads = n_reloads; 1416 chain->rld = XOBNEWVEC (&reload_obstack, struct reload, n_reloads); 1417 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); 1418 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0); 1419 } 1420 1421 /* Walk the chain of insns, and determine for each whether it needs reloads 1422 and/or eliminations. Build the corresponding insns_need_reload list, and 1423 set something_needs_elimination as appropriate. */ 1424 static void 1425 calculate_needs_all_insns (int global) 1426 { 1427 class insn_chain **pprev_reload = &insns_need_reload; 1428 class insn_chain *chain, *next = 0; 1429 1430 something_needs_elimination = 0; 1431 1432 reload_insn_firstobj = XOBNEWVAR (&reload_obstack, char, 0); 1433 for (chain = reload_insn_chain; chain != 0; chain = next) 1434 { 1435 rtx_insn *insn = chain->insn; 1436 1437 next = chain->next; 1438 1439 /* Clear out the shortcuts. */ 1440 chain->n_reloads = 0; 1441 chain->need_elim = 0; 1442 chain->need_reload = 0; 1443 chain->need_operand_change = 0; 1444 1445 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might 1446 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see 1447 what effects this has on the known offsets at labels. */ 1448 1449 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) 1450 || (INSN_P (insn) && REG_NOTES (insn) != 0)) 1451 set_label_offsets (insn, insn, 0); 1452 1453 if (INSN_P (insn)) 1454 { 1455 rtx old_body = PATTERN (insn); 1456 int old_code = INSN_CODE (insn); 1457 rtx old_notes = REG_NOTES (insn); 1458 int did_elimination = 0; 1459 int operands_changed = 0; 1460 1461 /* Skip insns that only set an equivalence. */ 1462 if (will_delete_init_insn_p (insn)) 1463 continue; 1464 1465 /* If needed, eliminate any eliminable registers. */ 1466 if (num_eliminable || num_eliminable_invariants) 1467 did_elimination = eliminate_regs_in_insn (insn, 0); 1468 1469 /* Analyze the instruction. */ 1470 operands_changed = find_reloads (insn, 0, spill_indirect_levels, 1471 global, spill_reg_order); 1472 1473 /* If a no-op set needs more than one reload, this is likely 1474 to be something that needs input address reloads. We 1475 can't get rid of this cleanly later, and it is of no use 1476 anyway, so discard it now. 1477 We only do this when expensive_optimizations is enabled, 1478 since this complements reload inheritance / output 1479 reload deletion, and it can make debugging harder. */ 1480 if (flag_expensive_optimizations && n_reloads > 1) 1481 { 1482 rtx set = single_set (insn); 1483 if (set 1484 && 1485 ((SET_SRC (set) == SET_DEST (set) 1486 && REG_P (SET_SRC (set)) 1487 && REGNO (SET_SRC (set)) >= FIRST_PSEUDO_REGISTER) 1488 || (REG_P (SET_SRC (set)) && REG_P (SET_DEST (set)) 1489 && reg_renumber[REGNO (SET_SRC (set))] < 0 1490 && reg_renumber[REGNO (SET_DEST (set))] < 0 1491 && reg_equiv_memory_loc (REGNO (SET_SRC (set))) != NULL 1492 && reg_equiv_memory_loc (REGNO (SET_DEST (set))) != NULL 1493 && rtx_equal_p (reg_equiv_memory_loc (REGNO (SET_SRC (set))), 1494 reg_equiv_memory_loc (REGNO (SET_DEST (set))))))) 1495 { 1496 if (ira_conflicts_p) 1497 /* Inform IRA about the insn deletion. */ 1498 ira_mark_memory_move_deletion (REGNO (SET_DEST (set)), 1499 REGNO (SET_SRC (set))); 1500 delete_insn (insn); 1501 /* Delete it from the reload chain. */ 1502 if (chain->prev) 1503 chain->prev->next = next; 1504 else 1505 reload_insn_chain = next; 1506 if (next) 1507 next->prev = chain->prev; 1508 chain->next = unused_insn_chains; 1509 unused_insn_chains = chain; 1510 continue; 1511 } 1512 } 1513 if (num_eliminable) 1514 update_eliminable_offsets (); 1515 1516 /* Remember for later shortcuts which insns had any reloads or 1517 register eliminations. */ 1518 chain->need_elim = did_elimination; 1519 chain->need_reload = n_reloads > 0; 1520 chain->need_operand_change = operands_changed; 1521 1522 /* Discard any register replacements done. */ 1523 if (did_elimination) 1524 { 1525 obstack_free (&reload_obstack, reload_insn_firstobj); 1526 PATTERN (insn) = old_body; 1527 INSN_CODE (insn) = old_code; 1528 REG_NOTES (insn) = old_notes; 1529 something_needs_elimination = 1; 1530 } 1531 1532 something_needs_operands_changed |= operands_changed; 1533 1534 if (n_reloads != 0) 1535 { 1536 copy_reloads (chain); 1537 *pprev_reload = chain; 1538 pprev_reload = &chain->next_need_reload; 1539 } 1540 } 1541 } 1542 *pprev_reload = 0; 1543 } 1544 1545 /* This function is called from the register allocator to set up estimates 1546 for the cost of eliminating pseudos which have REG_EQUIV equivalences to 1547 an invariant. The structure is similar to calculate_needs_all_insns. */ 1548 1549 void 1550 calculate_elim_costs_all_insns (void) 1551 { 1552 int *reg_equiv_init_cost; 1553 basic_block bb; 1554 int i; 1555 1556 reg_equiv_init_cost = XCNEWVEC (int, max_regno); 1557 init_elim_table (); 1558 init_eliminable_invariants (get_insns (), false); 1559 1560 set_initial_elim_offsets (); 1561 set_initial_label_offsets (); 1562 1563 FOR_EACH_BB_FN (bb, cfun) 1564 { 1565 rtx_insn *insn; 1566 elim_bb = bb; 1567 1568 FOR_BB_INSNS (bb, insn) 1569 { 1570 /* If this is a label, a JUMP_INSN, or has REG_NOTES (which might 1571 include REG_LABEL_OPERAND and REG_LABEL_TARGET), we need to see 1572 what effects this has on the known offsets at labels. */ 1573 1574 if (LABEL_P (insn) || JUMP_P (insn) || JUMP_TABLE_DATA_P (insn) 1575 || (INSN_P (insn) && REG_NOTES (insn) != 0)) 1576 set_label_offsets (insn, insn, 0); 1577 1578 if (INSN_P (insn)) 1579 { 1580 rtx set = single_set (insn); 1581 1582 /* Skip insns that only set an equivalence. */ 1583 if (set && REG_P (SET_DEST (set)) 1584 && reg_renumber[REGNO (SET_DEST (set))] < 0 1585 && (reg_equiv_constant (REGNO (SET_DEST (set))) 1586 || reg_equiv_invariant (REGNO (SET_DEST (set))))) 1587 { 1588 unsigned regno = REGNO (SET_DEST (set)); 1589 rtx_insn_list *init = reg_equiv_init (regno); 1590 if (init) 1591 { 1592 rtx t = eliminate_regs_1 (SET_SRC (set), VOIDmode, insn, 1593 false, true); 1594 machine_mode mode = GET_MODE (SET_DEST (set)); 1595 int cost = set_src_cost (t, mode, 1596 optimize_bb_for_speed_p (bb)); 1597 int freq = REG_FREQ_FROM_BB (bb); 1598 1599 reg_equiv_init_cost[regno] = cost * freq; 1600 continue; 1601 } 1602 } 1603 /* If needed, eliminate any eliminable registers. */ 1604 if (num_eliminable || num_eliminable_invariants) 1605 elimination_costs_in_insn (insn); 1606 1607 if (num_eliminable) 1608 update_eliminable_offsets (); 1609 } 1610 } 1611 } 1612 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 1613 { 1614 if (reg_equiv_invariant (i)) 1615 { 1616 if (reg_equiv_init (i)) 1617 { 1618 int cost = reg_equiv_init_cost[i]; 1619 if (dump_file) 1620 fprintf (dump_file, 1621 "Reg %d has equivalence, initial gains %d\n", i, cost); 1622 if (cost != 0) 1623 ira_adjust_equiv_reg_cost (i, cost); 1624 } 1625 else 1626 { 1627 if (dump_file) 1628 fprintf (dump_file, 1629 "Reg %d had equivalence, but can't be eliminated\n", 1630 i); 1631 ira_adjust_equiv_reg_cost (i, 0); 1632 } 1633 } 1634 } 1635 1636 free (reg_equiv_init_cost); 1637 free (offsets_known_at); 1638 free (offsets_at); 1639 offsets_at = NULL; 1640 offsets_known_at = NULL; 1641 } 1642 1643 /* Comparison function for qsort to decide which of two reloads 1644 should be handled first. *P1 and *P2 are the reload numbers. */ 1645 1646 static int 1647 reload_reg_class_lower (const void *r1p, const void *r2p) 1648 { 1649 int r1 = *(const short *) r1p, r2 = *(const short *) r2p; 1650 int t; 1651 1652 /* Consider required reloads before optional ones. */ 1653 t = rld[r1].optional - rld[r2].optional; 1654 if (t != 0) 1655 return t; 1656 1657 /* Count all solitary classes before non-solitary ones. */ 1658 t = ((reg_class_size[(int) rld[r2].rclass] == 1) 1659 - (reg_class_size[(int) rld[r1].rclass] == 1)); 1660 if (t != 0) 1661 return t; 1662 1663 /* Aside from solitaires, consider all multi-reg groups first. */ 1664 t = rld[r2].nregs - rld[r1].nregs; 1665 if (t != 0) 1666 return t; 1667 1668 /* Consider reloads in order of increasing reg-class number. */ 1669 t = (int) rld[r1].rclass - (int) rld[r2].rclass; 1670 if (t != 0) 1671 return t; 1672 1673 /* If reloads are equally urgent, sort by reload number, 1674 so that the results of qsort leave nothing to chance. */ 1675 return r1 - r2; 1676 } 1677 1678 /* The cost of spilling each hard reg. */ 1679 static int spill_cost[FIRST_PSEUDO_REGISTER]; 1680 1681 /* When spilling multiple hard registers, we use SPILL_COST for the first 1682 spilled hard reg and SPILL_ADD_COST for subsequent regs. SPILL_ADD_COST 1683 only the first hard reg for a multi-reg pseudo. */ 1684 static int spill_add_cost[FIRST_PSEUDO_REGISTER]; 1685 1686 /* Map of hard regno to pseudo regno currently occupying the hard 1687 reg. */ 1688 static int hard_regno_to_pseudo_regno[FIRST_PSEUDO_REGISTER]; 1689 1690 /* Update the spill cost arrays, considering that pseudo REG is live. */ 1691 1692 static void 1693 count_pseudo (int reg) 1694 { 1695 int freq = REG_FREQ (reg); 1696 int r = reg_renumber[reg]; 1697 int nregs; 1698 1699 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */ 1700 if (ira_conflicts_p && r < 0) 1701 return; 1702 1703 if (REGNO_REG_SET_P (&pseudos_counted, reg) 1704 || REGNO_REG_SET_P (&spilled_pseudos, reg)) 1705 return; 1706 1707 SET_REGNO_REG_SET (&pseudos_counted, reg); 1708 1709 gcc_assert (r >= 0); 1710 1711 spill_add_cost[r] += freq; 1712 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg)); 1713 while (nregs-- > 0) 1714 { 1715 hard_regno_to_pseudo_regno[r + nregs] = reg; 1716 spill_cost[r + nregs] += freq; 1717 } 1718 } 1719 1720 /* Calculate the SPILL_COST and SPILL_ADD_COST arrays and determine the 1721 contents of BAD_SPILL_REGS for the insn described by CHAIN. */ 1722 1723 static void 1724 order_regs_for_reload (class insn_chain *chain) 1725 { 1726 unsigned i; 1727 HARD_REG_SET used_by_pseudos; 1728 HARD_REG_SET used_by_pseudos2; 1729 reg_set_iterator rsi; 1730 1731 bad_spill_regs = fixed_reg_set; 1732 1733 memset (spill_cost, 0, sizeof spill_cost); 1734 memset (spill_add_cost, 0, sizeof spill_add_cost); 1735 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1736 hard_regno_to_pseudo_regno[i] = -1; 1737 1738 /* Count number of uses of each hard reg by pseudo regs allocated to it 1739 and then order them by decreasing use. First exclude hard registers 1740 that are live in or across this insn. */ 1741 1742 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); 1743 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); 1744 bad_spill_regs |= used_by_pseudos; 1745 bad_spill_regs |= used_by_pseudos2; 1746 1747 /* Now find out which pseudos are allocated to it, and update 1748 hard_reg_n_uses. */ 1749 CLEAR_REG_SET (&pseudos_counted); 1750 1751 EXECUTE_IF_SET_IN_REG_SET 1752 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) 1753 { 1754 count_pseudo (i); 1755 } 1756 EXECUTE_IF_SET_IN_REG_SET 1757 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) 1758 { 1759 count_pseudo (i); 1760 } 1761 CLEAR_REG_SET (&pseudos_counted); 1762 } 1763 1764 /* Vector of reload-numbers showing the order in which the reloads should 1765 be processed. */ 1766 static short reload_order[MAX_RELOADS]; 1767 1768 /* This is used to keep track of the spill regs used in one insn. */ 1769 static HARD_REG_SET used_spill_regs_local; 1770 1771 /* We decided to spill hard register SPILLED, which has a size of 1772 SPILLED_NREGS. Determine how pseudo REG, which is live during the insn, 1773 is affected. We will add it to SPILLED_PSEUDOS if necessary, and we will 1774 update SPILL_COST/SPILL_ADD_COST. */ 1775 1776 static void 1777 count_spilled_pseudo (int spilled, int spilled_nregs, int reg) 1778 { 1779 int freq = REG_FREQ (reg); 1780 int r = reg_renumber[reg]; 1781 int nregs; 1782 1783 /* Ignore spilled pseudo-registers which can be here only if IRA is used. */ 1784 if (ira_conflicts_p && r < 0) 1785 return; 1786 1787 gcc_assert (r >= 0); 1788 1789 nregs = hard_regno_nregs (r, PSEUDO_REGNO_MODE (reg)); 1790 1791 if (REGNO_REG_SET_P (&spilled_pseudos, reg) 1792 || spilled + spilled_nregs <= r || r + nregs <= spilled) 1793 return; 1794 1795 SET_REGNO_REG_SET (&spilled_pseudos, reg); 1796 1797 spill_add_cost[r] -= freq; 1798 while (nregs-- > 0) 1799 { 1800 hard_regno_to_pseudo_regno[r + nregs] = -1; 1801 spill_cost[r + nregs] -= freq; 1802 } 1803 } 1804 1805 /* Find reload register to use for reload number ORDER. */ 1806 1807 static int 1808 find_reg (class insn_chain *chain, int order) 1809 { 1810 int rnum = reload_order[order]; 1811 struct reload *rl = rld + rnum; 1812 int best_cost = INT_MAX; 1813 int best_reg = -1; 1814 unsigned int i, j, n; 1815 int k; 1816 HARD_REG_SET not_usable; 1817 HARD_REG_SET used_by_other_reload; 1818 reg_set_iterator rsi; 1819 static int regno_pseudo_regs[FIRST_PSEUDO_REGISTER]; 1820 static int best_regno_pseudo_regs[FIRST_PSEUDO_REGISTER]; 1821 1822 not_usable = (bad_spill_regs 1823 | bad_spill_regs_global 1824 | ~reg_class_contents[rl->rclass]); 1825 1826 CLEAR_HARD_REG_SET (used_by_other_reload); 1827 for (k = 0; k < order; k++) 1828 { 1829 int other = reload_order[k]; 1830 1831 if (rld[other].regno >= 0 && reloads_conflict (other, rnum)) 1832 for (j = 0; j < rld[other].nregs; j++) 1833 SET_HARD_REG_BIT (used_by_other_reload, rld[other].regno + j); 1834 } 1835 1836 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1837 { 1838 #ifdef REG_ALLOC_ORDER 1839 unsigned int regno = reg_alloc_order[i]; 1840 #else 1841 unsigned int regno = i; 1842 #endif 1843 1844 if (! TEST_HARD_REG_BIT (not_usable, regno) 1845 && ! TEST_HARD_REG_BIT (used_by_other_reload, regno) 1846 && targetm.hard_regno_mode_ok (regno, rl->mode)) 1847 { 1848 int this_cost = spill_cost[regno]; 1849 int ok = 1; 1850 unsigned int this_nregs = hard_regno_nregs (regno, rl->mode); 1851 1852 for (j = 1; j < this_nregs; j++) 1853 { 1854 this_cost += spill_add_cost[regno + j]; 1855 if ((TEST_HARD_REG_BIT (not_usable, regno + j)) 1856 || TEST_HARD_REG_BIT (used_by_other_reload, regno + j)) 1857 ok = 0; 1858 } 1859 if (! ok) 1860 continue; 1861 1862 if (ira_conflicts_p) 1863 { 1864 /* Ask IRA to find a better pseudo-register for 1865 spilling. */ 1866 for (n = j = 0; j < this_nregs; j++) 1867 { 1868 int r = hard_regno_to_pseudo_regno[regno + j]; 1869 1870 if (r < 0) 1871 continue; 1872 if (n == 0 || regno_pseudo_regs[n - 1] != r) 1873 regno_pseudo_regs[n++] = r; 1874 } 1875 regno_pseudo_regs[n++] = -1; 1876 if (best_reg < 0 1877 || ira_better_spill_reload_regno_p (regno_pseudo_regs, 1878 best_regno_pseudo_regs, 1879 rl->in, rl->out, 1880 chain->insn)) 1881 { 1882 best_reg = regno; 1883 for (j = 0;; j++) 1884 { 1885 best_regno_pseudo_regs[j] = regno_pseudo_regs[j]; 1886 if (regno_pseudo_regs[j] < 0) 1887 break; 1888 } 1889 } 1890 continue; 1891 } 1892 1893 if (rl->in && REG_P (rl->in) && REGNO (rl->in) == regno) 1894 this_cost--; 1895 if (rl->out && REG_P (rl->out) && REGNO (rl->out) == regno) 1896 this_cost--; 1897 if (this_cost < best_cost 1898 /* Among registers with equal cost, prefer caller-saved ones, or 1899 use REG_ALLOC_ORDER if it is defined. */ 1900 || (this_cost == best_cost 1901 #ifdef REG_ALLOC_ORDER 1902 && (inv_reg_alloc_order[regno] 1903 < inv_reg_alloc_order[best_reg]) 1904 #else 1905 && crtl->abi->clobbers_full_reg_p (regno) 1906 && !crtl->abi->clobbers_full_reg_p (best_reg) 1907 #endif 1908 )) 1909 { 1910 best_reg = regno; 1911 best_cost = this_cost; 1912 } 1913 } 1914 } 1915 if (best_reg == -1) 1916 return 0; 1917 1918 if (dump_file) 1919 fprintf (dump_file, "Using reg %d for reload %d\n", best_reg, rnum); 1920 1921 rl->nregs = hard_regno_nregs (best_reg, rl->mode); 1922 rl->regno = best_reg; 1923 1924 EXECUTE_IF_SET_IN_REG_SET 1925 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, j, rsi) 1926 { 1927 count_spilled_pseudo (best_reg, rl->nregs, j); 1928 } 1929 1930 EXECUTE_IF_SET_IN_REG_SET 1931 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, j, rsi) 1932 { 1933 count_spilled_pseudo (best_reg, rl->nregs, j); 1934 } 1935 1936 for (i = 0; i < rl->nregs; i++) 1937 { 1938 gcc_assert (spill_cost[best_reg + i] == 0); 1939 gcc_assert (spill_add_cost[best_reg + i] == 0); 1940 gcc_assert (hard_regno_to_pseudo_regno[best_reg + i] == -1); 1941 SET_HARD_REG_BIT (used_spill_regs_local, best_reg + i); 1942 } 1943 return 1; 1944 } 1945 1946 /* Find more reload regs to satisfy the remaining need of an insn, which 1947 is given by CHAIN. 1948 Do it by ascending class number, since otherwise a reg 1949 might be spilled for a big class and might fail to count 1950 for a smaller class even though it belongs to that class. */ 1951 1952 static void 1953 find_reload_regs (class insn_chain *chain) 1954 { 1955 int i; 1956 1957 /* In order to be certain of getting the registers we need, 1958 we must sort the reloads into order of increasing register class. 1959 Then our grabbing of reload registers will parallel the process 1960 that provided the reload registers. */ 1961 for (i = 0; i < chain->n_reloads; i++) 1962 { 1963 /* Show whether this reload already has a hard reg. */ 1964 if (chain->rld[i].reg_rtx) 1965 { 1966 chain->rld[i].regno = REGNO (chain->rld[i].reg_rtx); 1967 chain->rld[i].nregs = REG_NREGS (chain->rld[i].reg_rtx); 1968 } 1969 else 1970 chain->rld[i].regno = -1; 1971 reload_order[i] = i; 1972 } 1973 1974 n_reloads = chain->n_reloads; 1975 memcpy (rld, chain->rld, n_reloads * sizeof (struct reload)); 1976 1977 CLEAR_HARD_REG_SET (used_spill_regs_local); 1978 1979 if (dump_file) 1980 fprintf (dump_file, "Spilling for insn %d.\n", INSN_UID (chain->insn)); 1981 1982 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); 1983 1984 /* Compute the order of preference for hard registers to spill. */ 1985 1986 order_regs_for_reload (chain); 1987 1988 for (i = 0; i < n_reloads; i++) 1989 { 1990 int r = reload_order[i]; 1991 1992 /* Ignore reloads that got marked inoperative. */ 1993 if ((rld[r].out != 0 || rld[r].in != 0 || rld[r].secondary_p) 1994 && ! rld[r].optional 1995 && rld[r].regno == -1) 1996 if (! find_reg (chain, i)) 1997 { 1998 if (dump_file) 1999 fprintf (dump_file, "reload failure for reload %d\n", r); 2000 spill_failure (chain->insn, rld[r].rclass); 2001 failure = 1; 2002 return; 2003 } 2004 } 2005 2006 chain->used_spill_regs = used_spill_regs_local; 2007 used_spill_regs |= used_spill_regs_local; 2008 2009 memcpy (chain->rld, rld, n_reloads * sizeof (struct reload)); 2010 } 2011 2012 static void 2013 select_reload_regs (void) 2014 { 2015 class insn_chain *chain; 2016 2017 /* Try to satisfy the needs for each insn. */ 2018 for (chain = insns_need_reload; chain != 0; 2019 chain = chain->next_need_reload) 2020 find_reload_regs (chain); 2021 } 2022 2023 /* Delete all insns that were inserted by emit_caller_save_insns during 2024 this iteration. */ 2025 static void 2026 delete_caller_save_insns (void) 2027 { 2028 class insn_chain *c = reload_insn_chain; 2029 2030 while (c != 0) 2031 { 2032 while (c != 0 && c->is_caller_save_insn) 2033 { 2034 class insn_chain *next = c->next; 2035 rtx_insn *insn = c->insn; 2036 2037 if (c == reload_insn_chain) 2038 reload_insn_chain = next; 2039 delete_insn (insn); 2040 2041 if (next) 2042 next->prev = c->prev; 2043 if (c->prev) 2044 c->prev->next = next; 2045 c->next = unused_insn_chains; 2046 unused_insn_chains = c; 2047 c = next; 2048 } 2049 if (c != 0) 2050 c = c->next; 2051 } 2052 } 2053 2054 /* Handle the failure to find a register to spill. 2055 INSN should be one of the insns which needed this particular spill reg. */ 2056 2057 static void 2058 spill_failure (rtx_insn *insn, enum reg_class rclass) 2059 { 2060 if (asm_noperands (PATTERN (insn)) >= 0) 2061 error_for_asm (insn, "cannot find a register in class %qs while " 2062 "reloading %<asm%>", 2063 reg_class_names[rclass]); 2064 else 2065 { 2066 error ("unable to find a register to spill in class %qs", 2067 reg_class_names[rclass]); 2068 2069 if (dump_file) 2070 { 2071 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); 2072 debug_reload_to_stream (dump_file); 2073 } 2074 fatal_insn ("this is the insn:", insn); 2075 } 2076 } 2077 2078 /* Delete an unneeded INSN and any previous insns who sole purpose is loading 2079 data that is dead in INSN. */ 2080 2081 static void 2082 delete_dead_insn (rtx_insn *insn) 2083 { 2084 rtx_insn *prev = prev_active_insn (insn); 2085 rtx prev_dest; 2086 2087 /* If the previous insn sets a register that dies in our insn make 2088 a note that we want to run DCE immediately after reload. 2089 2090 We used to delete the previous insn & recurse, but that's wrong for 2091 block local equivalences. Instead of trying to figure out the exact 2092 circumstances where we can delete the potentially dead insns, just 2093 let DCE do the job. */ 2094 if (prev && BLOCK_FOR_INSN (prev) == BLOCK_FOR_INSN (insn) 2095 && GET_CODE (PATTERN (prev)) == SET 2096 && (prev_dest = SET_DEST (PATTERN (prev)), REG_P (prev_dest)) 2097 && reg_mentioned_p (prev_dest, PATTERN (insn)) 2098 && find_regno_note (insn, REG_DEAD, REGNO (prev_dest)) 2099 && ! side_effects_p (SET_SRC (PATTERN (prev)))) 2100 need_dce = 1; 2101 2102 SET_INSN_DELETED (insn); 2103 } 2104 2105 /* Modify the home of pseudo-reg I. 2106 The new home is present in reg_renumber[I]. 2107 2108 FROM_REG may be the hard reg that the pseudo-reg is being spilled from; 2109 or it may be -1, meaning there is none or it is not relevant. 2110 This is used so that all pseudos spilled from a given hard reg 2111 can share one stack slot. */ 2112 2113 static void 2114 alter_reg (int i, int from_reg, bool dont_share_p) 2115 { 2116 /* When outputting an inline function, this can happen 2117 for a reg that isn't actually used. */ 2118 if (regno_reg_rtx[i] == 0) 2119 return; 2120 2121 /* If the reg got changed to a MEM at rtl-generation time, 2122 ignore it. */ 2123 if (!REG_P (regno_reg_rtx[i])) 2124 return; 2125 2126 /* Modify the reg-rtx to contain the new hard reg 2127 number or else to contain its pseudo reg number. */ 2128 SET_REGNO (regno_reg_rtx[i], 2129 reg_renumber[i] >= 0 ? reg_renumber[i] : i); 2130 2131 /* If we have a pseudo that is needed but has no hard reg or equivalent, 2132 allocate a stack slot for it. */ 2133 2134 if (reg_renumber[i] < 0 2135 && REG_N_REFS (i) > 0 2136 && reg_equiv_constant (i) == 0 2137 && (reg_equiv_invariant (i) == 0 2138 || reg_equiv_init (i) == 0) 2139 && reg_equiv_memory_loc (i) == 0) 2140 { 2141 rtx x = NULL_RTX; 2142 machine_mode mode = GET_MODE (regno_reg_rtx[i]); 2143 poly_uint64 inherent_size = GET_MODE_SIZE (mode); 2144 unsigned int inherent_align = GET_MODE_ALIGNMENT (mode); 2145 machine_mode wider_mode = wider_subreg_mode (mode, reg_max_ref_mode[i]); 2146 poly_uint64 total_size = GET_MODE_SIZE (wider_mode); 2147 /* ??? Seems strange to derive the minimum alignment from the size, 2148 but that's the traditional behavior. For polynomial-size modes, 2149 the natural extension is to use the minimum possible size. */ 2150 unsigned int min_align 2151 = constant_lower_bound (GET_MODE_BITSIZE (reg_max_ref_mode[i])); 2152 poly_int64 adjust = 0; 2153 2154 something_was_spilled = true; 2155 2156 if (ira_conflicts_p) 2157 { 2158 /* Mark the spill for IRA. */ 2159 SET_REGNO_REG_SET (&spilled_pseudos, i); 2160 if (!dont_share_p) 2161 x = ira_reuse_stack_slot (i, inherent_size, total_size); 2162 } 2163 2164 if (x) 2165 ; 2166 2167 /* Each pseudo reg has an inherent size which comes from its own mode, 2168 and a total size which provides room for paradoxical subregs 2169 which refer to the pseudo reg in wider modes. 2170 2171 We can use a slot already allocated if it provides both 2172 enough inherent space and enough total space. 2173 Otherwise, we allocate a new slot, making sure that it has no less 2174 inherent space, and no less total space, then the previous slot. */ 2175 else if (from_reg == -1 || (!dont_share_p && ira_conflicts_p)) 2176 { 2177 rtx stack_slot; 2178 2179 /* The sizes are taken from a subreg operation, which guarantees 2180 that they're ordered. */ 2181 gcc_checking_assert (ordered_p (total_size, inherent_size)); 2182 2183 /* No known place to spill from => no slot to reuse. */ 2184 x = assign_stack_local (mode, total_size, 2185 min_align > inherent_align 2186 || maybe_gt (total_size, inherent_size) 2187 ? -1 : 0); 2188 2189 stack_slot = x; 2190 2191 /* Cancel the big-endian correction done in assign_stack_local. 2192 Get the address of the beginning of the slot. This is so we 2193 can do a big-endian correction unconditionally below. */ 2194 if (BYTES_BIG_ENDIAN) 2195 { 2196 adjust = inherent_size - total_size; 2197 if (maybe_ne (adjust, 0)) 2198 { 2199 poly_uint64 total_bits = total_size * BITS_PER_UNIT; 2200 machine_mode mem_mode 2201 = int_mode_for_size (total_bits, 1).else_blk (); 2202 stack_slot = adjust_address_nv (x, mem_mode, adjust); 2203 } 2204 } 2205 2206 if (! dont_share_p && ira_conflicts_p) 2207 /* Inform IRA about allocation a new stack slot. */ 2208 ira_mark_new_stack_slot (stack_slot, i, total_size); 2209 } 2210 2211 /* Reuse a stack slot if possible. */ 2212 else if (spill_stack_slot[from_reg] != 0 2213 && known_ge (spill_stack_slot_width[from_reg], total_size) 2214 && known_ge (GET_MODE_SIZE 2215 (GET_MODE (spill_stack_slot[from_reg])), 2216 inherent_size) 2217 && MEM_ALIGN (spill_stack_slot[from_reg]) >= min_align) 2218 x = spill_stack_slot[from_reg]; 2219 2220 /* Allocate a bigger slot. */ 2221 else 2222 { 2223 /* Compute maximum size needed, both for inherent size 2224 and for total size. */ 2225 rtx stack_slot; 2226 2227 if (spill_stack_slot[from_reg]) 2228 { 2229 if (partial_subreg_p (mode, 2230 GET_MODE (spill_stack_slot[from_reg]))) 2231 mode = GET_MODE (spill_stack_slot[from_reg]); 2232 total_size = ordered_max (total_size, 2233 spill_stack_slot_width[from_reg]); 2234 if (MEM_ALIGN (spill_stack_slot[from_reg]) > min_align) 2235 min_align = MEM_ALIGN (spill_stack_slot[from_reg]); 2236 } 2237 2238 /* The sizes are taken from a subreg operation, which guarantees 2239 that they're ordered. */ 2240 gcc_checking_assert (ordered_p (total_size, inherent_size)); 2241 2242 /* Make a slot with that size. */ 2243 x = assign_stack_local (mode, total_size, 2244 min_align > inherent_align 2245 || maybe_gt (total_size, inherent_size) 2246 ? -1 : 0); 2247 stack_slot = x; 2248 2249 /* Cancel the big-endian correction done in assign_stack_local. 2250 Get the address of the beginning of the slot. This is so we 2251 can do a big-endian correction unconditionally below. */ 2252 if (BYTES_BIG_ENDIAN) 2253 { 2254 adjust = GET_MODE_SIZE (mode) - total_size; 2255 if (maybe_ne (adjust, 0)) 2256 { 2257 poly_uint64 total_bits = total_size * BITS_PER_UNIT; 2258 machine_mode mem_mode 2259 = int_mode_for_size (total_bits, 1).else_blk (); 2260 stack_slot = adjust_address_nv (x, mem_mode, adjust); 2261 } 2262 } 2263 2264 spill_stack_slot[from_reg] = stack_slot; 2265 spill_stack_slot_width[from_reg] = total_size; 2266 } 2267 2268 /* On a big endian machine, the "address" of the slot 2269 is the address of the low part that fits its inherent mode. */ 2270 adjust += subreg_size_lowpart_offset (inherent_size, total_size); 2271 2272 /* If we have any adjustment to make, or if the stack slot is the 2273 wrong mode, make a new stack slot. */ 2274 x = adjust_address_nv (x, GET_MODE (regno_reg_rtx[i]), adjust); 2275 2276 /* Set all of the memory attributes as appropriate for a spill. */ 2277 set_mem_attrs_for_spill (x); 2278 2279 /* Save the stack slot for later. */ 2280 reg_equiv_memory_loc (i) = x; 2281 } 2282 } 2283 2284 /* Mark the slots in regs_ever_live for the hard regs used by 2285 pseudo-reg number REGNO, accessed in MODE. */ 2286 2287 static void 2288 mark_home_live_1 (int regno, machine_mode mode) 2289 { 2290 int i, lim; 2291 2292 i = reg_renumber[regno]; 2293 if (i < 0) 2294 return; 2295 lim = end_hard_regno (mode, i); 2296 while (i < lim) 2297 df_set_regs_ever_live (i++, true); 2298 } 2299 2300 /* Mark the slots in regs_ever_live for the hard regs 2301 used by pseudo-reg number REGNO. */ 2302 2303 void 2304 mark_home_live (int regno) 2305 { 2306 if (reg_renumber[regno] >= 0) 2307 mark_home_live_1 (regno, PSEUDO_REGNO_MODE (regno)); 2308 } 2309 2310 /* This function handles the tracking of elimination offsets around branches. 2311 2312 X is a piece of RTL being scanned. 2313 2314 INSN is the insn that it came from, if any. 2315 2316 INITIAL_P is nonzero if we are to set the offset to be the initial 2317 offset and zero if we are setting the offset of the label to be the 2318 current offset. */ 2319 2320 static void 2321 set_label_offsets (rtx x, rtx_insn *insn, int initial_p) 2322 { 2323 enum rtx_code code = GET_CODE (x); 2324 rtx tem; 2325 unsigned int i; 2326 struct elim_table *p; 2327 2328 switch (code) 2329 { 2330 case LABEL_REF: 2331 if (LABEL_REF_NONLOCAL_P (x)) 2332 return; 2333 2334 x = label_ref_label (x); 2335 2336 /* fall through */ 2337 2338 case CODE_LABEL: 2339 /* If we know nothing about this label, set the desired offsets. Note 2340 that this sets the offset at a label to be the offset before a label 2341 if we don't know anything about the label. This is not correct for 2342 the label after a BARRIER, but is the best guess we can make. If 2343 we guessed wrong, we will suppress an elimination that might have 2344 been possible had we been able to guess correctly. */ 2345 2346 if (! offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num]) 2347 { 2348 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2349 offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i] 2350 = (initial_p ? reg_eliminate[i].initial_offset 2351 : reg_eliminate[i].offset); 2352 offsets_known_at[CODE_LABEL_NUMBER (x) - first_label_num] = 1; 2353 } 2354 2355 /* Otherwise, if this is the definition of a label and it is 2356 preceded by a BARRIER, set our offsets to the known offset of 2357 that label. */ 2358 2359 else if (x == insn 2360 && (tem = prev_nonnote_insn (insn)) != 0 2361 && BARRIER_P (tem)) 2362 set_offsets_for_label (insn); 2363 else 2364 /* If neither of the above cases is true, compare each offset 2365 with those previously recorded and suppress any eliminations 2366 where the offsets disagree. */ 2367 2368 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 2369 if (maybe_ne (offsets_at[CODE_LABEL_NUMBER (x) - first_label_num][i], 2370 (initial_p ? reg_eliminate[i].initial_offset 2371 : reg_eliminate[i].offset))) 2372 reg_eliminate[i].can_eliminate = 0; 2373 2374 return; 2375 2376 case JUMP_TABLE_DATA: 2377 set_label_offsets (PATTERN (insn), insn, initial_p); 2378 return; 2379 2380 case JUMP_INSN: 2381 set_label_offsets (PATTERN (insn), insn, initial_p); 2382 2383 /* fall through */ 2384 2385 case INSN: 2386 case CALL_INSN: 2387 /* Any labels mentioned in REG_LABEL_OPERAND notes can be branched 2388 to indirectly and hence must have all eliminations at their 2389 initial offsets. */ 2390 for (tem = REG_NOTES (x); tem; tem = XEXP (tem, 1)) 2391 if (REG_NOTE_KIND (tem) == REG_LABEL_OPERAND) 2392 set_label_offsets (XEXP (tem, 0), insn, 1); 2393 return; 2394 2395 case PARALLEL: 2396 case ADDR_VEC: 2397 case ADDR_DIFF_VEC: 2398 /* Each of the labels in the parallel or address vector must be 2399 at their initial offsets. We want the first field for PARALLEL 2400 and ADDR_VEC and the second field for ADDR_DIFF_VEC. */ 2401 2402 for (i = 0; i < (unsigned) XVECLEN (x, code == ADDR_DIFF_VEC); i++) 2403 set_label_offsets (XVECEXP (x, code == ADDR_DIFF_VEC, i), 2404 insn, initial_p); 2405 return; 2406 2407 case SET: 2408 /* We only care about setting PC. If the source is not RETURN, 2409 IF_THEN_ELSE, or a label, disable any eliminations not at 2410 their initial offsets. Similarly if any arm of the IF_THEN_ELSE 2411 isn't one of those possibilities. For branches to a label, 2412 call ourselves recursively. 2413 2414 Note that this can disable elimination unnecessarily when we have 2415 a non-local goto since it will look like a non-constant jump to 2416 someplace in the current function. This isn't a significant 2417 problem since such jumps will normally be when all elimination 2418 pairs are back to their initial offsets. */ 2419 2420 if (SET_DEST (x) != pc_rtx) 2421 return; 2422 2423 switch (GET_CODE (SET_SRC (x))) 2424 { 2425 case PC: 2426 case RETURN: 2427 return; 2428 2429 case LABEL_REF: 2430 set_label_offsets (SET_SRC (x), insn, initial_p); 2431 return; 2432 2433 case IF_THEN_ELSE: 2434 tem = XEXP (SET_SRC (x), 1); 2435 if (GET_CODE (tem) == LABEL_REF) 2436 set_label_offsets (label_ref_label (tem), insn, initial_p); 2437 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2438 break; 2439 2440 tem = XEXP (SET_SRC (x), 2); 2441 if (GET_CODE (tem) == LABEL_REF) 2442 set_label_offsets (label_ref_label (tem), insn, initial_p); 2443 else if (GET_CODE (tem) != PC && GET_CODE (tem) != RETURN) 2444 break; 2445 return; 2446 2447 default: 2448 break; 2449 } 2450 2451 /* If we reach here, all eliminations must be at their initial 2452 offset because we are doing a jump to a variable address. */ 2453 for (p = reg_eliminate; p < ®_eliminate[NUM_ELIMINABLE_REGS]; p++) 2454 if (maybe_ne (p->offset, p->initial_offset)) 2455 p->can_eliminate = 0; 2456 break; 2457 2458 default: 2459 break; 2460 } 2461 } 2462 2463 /* This function examines every reg that occurs in X and adjusts the 2464 costs for its elimination which are gathered by IRA. INSN is the 2465 insn in which X occurs. We do not recurse into MEM expressions. */ 2466 2467 static void 2468 note_reg_elim_costly (const_rtx x, rtx insn) 2469 { 2470 subrtx_iterator::array_type array; 2471 FOR_EACH_SUBRTX (iter, array, x, NONCONST) 2472 { 2473 const_rtx x = *iter; 2474 if (MEM_P (x)) 2475 iter.skip_subrtxes (); 2476 else if (REG_P (x) 2477 && REGNO (x) >= FIRST_PSEUDO_REGISTER 2478 && reg_equiv_init (REGNO (x)) 2479 && reg_equiv_invariant (REGNO (x))) 2480 { 2481 rtx t = reg_equiv_invariant (REGNO (x)); 2482 rtx new_rtx = eliminate_regs_1 (t, Pmode, insn, true, true); 2483 int cost = set_src_cost (new_rtx, Pmode, 2484 optimize_bb_for_speed_p (elim_bb)); 2485 int freq = REG_FREQ_FROM_BB (elim_bb); 2486 2487 if (cost != 0) 2488 ira_adjust_equiv_reg_cost (REGNO (x), -cost * freq); 2489 } 2490 } 2491 } 2492 2493 /* Scan X and replace any eliminable registers (such as fp) with a 2494 replacement (such as sp), plus an offset. 2495 2496 MEM_MODE is the mode of an enclosing MEM. We need this to know how 2497 much to adjust a register for, e.g., PRE_DEC. Also, if we are inside a 2498 MEM, we are allowed to replace a sum of a register and the constant zero 2499 with the register, which we cannot do outside a MEM. In addition, we need 2500 to record the fact that a register is referenced outside a MEM. 2501 2502 If INSN is an insn, it is the insn containing X. If we replace a REG 2503 in a SET_DEST with an equivalent MEM and INSN is nonzero, write a 2504 CLOBBER of the pseudo after INSN so find_equiv_regs will know that 2505 the REG is being modified. 2506 2507 Alternatively, INSN may be a note (an EXPR_LIST or INSN_LIST). 2508 That's used when we eliminate in expressions stored in notes. 2509 This means, do not set ref_outside_mem even if the reference 2510 is outside of MEMs. 2511 2512 If FOR_COSTS is true, we are being called before reload in order to 2513 estimate the costs of keeping registers with an equivalence unallocated. 2514 2515 REG_EQUIV_MEM and REG_EQUIV_ADDRESS contain address that have had 2516 replacements done assuming all offsets are at their initial values. If 2517 they are not, or if REG_EQUIV_ADDRESS is nonzero for a pseudo we 2518 encounter, return the actual location so that find_reloads will do 2519 the proper thing. */ 2520 2521 static rtx 2522 eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn, 2523 bool may_use_invariant, bool for_costs) 2524 { 2525 enum rtx_code code = GET_CODE (x); 2526 struct elim_table *ep; 2527 int regno; 2528 rtx new_rtx; 2529 int i, j; 2530 const char *fmt; 2531 int copied = 0; 2532 2533 if (! current_function_decl) 2534 return x; 2535 2536 switch (code) 2537 { 2538 CASE_CONST_ANY: 2539 case CONST: 2540 case SYMBOL_REF: 2541 case CODE_LABEL: 2542 case PC: 2543 case CC0: 2544 case ASM_INPUT: 2545 case ADDR_VEC: 2546 case ADDR_DIFF_VEC: 2547 case RETURN: 2548 return x; 2549 2550 case REG: 2551 regno = REGNO (x); 2552 2553 /* First handle the case where we encounter a bare register that 2554 is eliminable. Replace it with a PLUS. */ 2555 if (regno < FIRST_PSEUDO_REGISTER) 2556 { 2557 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2558 ep++) 2559 if (ep->from_rtx == x && ep->can_eliminate) 2560 return plus_constant (Pmode, ep->to_rtx, ep->previous_offset); 2561 2562 } 2563 else if (reg_renumber && reg_renumber[regno] < 0 2564 && reg_equivs 2565 && reg_equiv_invariant (regno)) 2566 { 2567 if (may_use_invariant || (insn && DEBUG_INSN_P (insn))) 2568 return eliminate_regs_1 (copy_rtx (reg_equiv_invariant (regno)), 2569 mem_mode, insn, true, for_costs); 2570 /* There exists at least one use of REGNO that cannot be 2571 eliminated. Prevent the defining insn from being deleted. */ 2572 reg_equiv_init (regno) = NULL; 2573 if (!for_costs) 2574 alter_reg (regno, -1, true); 2575 } 2576 return x; 2577 2578 /* You might think handling MINUS in a manner similar to PLUS is a 2579 good idea. It is not. It has been tried multiple times and every 2580 time the change has had to have been reverted. 2581 2582 Other parts of reload know a PLUS is special (gen_reload for example) 2583 and require special code to handle code a reloaded PLUS operand. 2584 2585 Also consider backends where the flags register is clobbered by a 2586 MINUS, but we can emit a PLUS that does not clobber flags (IA-32, 2587 lea instruction comes to mind). If we try to reload a MINUS, we 2588 may kill the flags register that was holding a useful value. 2589 2590 So, please before trying to handle MINUS, consider reload as a 2591 whole instead of this little section as well as the backend issues. */ 2592 case PLUS: 2593 /* If this is the sum of an eliminable register and a constant, rework 2594 the sum. */ 2595 if (REG_P (XEXP (x, 0)) 2596 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2597 && CONSTANT_P (XEXP (x, 1))) 2598 { 2599 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2600 ep++) 2601 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2602 { 2603 /* The only time we want to replace a PLUS with a REG (this 2604 occurs when the constant operand of the PLUS is the negative 2605 of the offset) is when we are inside a MEM. We won't want 2606 to do so at other times because that would change the 2607 structure of the insn in a way that reload can't handle. 2608 We special-case the commonest situation in 2609 eliminate_regs_in_insn, so just replace a PLUS with a 2610 PLUS here, unless inside a MEM. In DEBUG_INSNs, it is 2611 always ok to replace a PLUS with just a REG. */ 2612 if ((mem_mode != 0 || (insn && DEBUG_INSN_P (insn))) 2613 && CONST_INT_P (XEXP (x, 1)) 2614 && known_eq (INTVAL (XEXP (x, 1)), -ep->previous_offset)) 2615 return ep->to_rtx; 2616 else 2617 return gen_rtx_PLUS (Pmode, ep->to_rtx, 2618 plus_constant (Pmode, XEXP (x, 1), 2619 ep->previous_offset)); 2620 } 2621 2622 /* If the register is not eliminable, we are done since the other 2623 operand is a constant. */ 2624 return x; 2625 } 2626 2627 /* If this is part of an address, we want to bring any constant to the 2628 outermost PLUS. We will do this by doing register replacement in 2629 our operands and seeing if a constant shows up in one of them. 2630 2631 Note that there is no risk of modifying the structure of the insn, 2632 since we only get called for its operands, thus we are either 2633 modifying the address inside a MEM, or something like an address 2634 operand of a load-address insn. */ 2635 2636 { 2637 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true, 2638 for_costs); 2639 rtx new1 = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, 2640 for_costs); 2641 2642 if (reg_renumber && (new0 != XEXP (x, 0) || new1 != XEXP (x, 1))) 2643 { 2644 /* If one side is a PLUS and the other side is a pseudo that 2645 didn't get a hard register but has a reg_equiv_constant, 2646 we must replace the constant here since it may no longer 2647 be in the position of any operand. */ 2648 if (GET_CODE (new0) == PLUS && REG_P (new1) 2649 && REGNO (new1) >= FIRST_PSEUDO_REGISTER 2650 && reg_renumber[REGNO (new1)] < 0 2651 && reg_equivs 2652 && reg_equiv_constant (REGNO (new1)) != 0) 2653 new1 = reg_equiv_constant (REGNO (new1)); 2654 else if (GET_CODE (new1) == PLUS && REG_P (new0) 2655 && REGNO (new0) >= FIRST_PSEUDO_REGISTER 2656 && reg_renumber[REGNO (new0)] < 0 2657 && reg_equiv_constant (REGNO (new0)) != 0) 2658 new0 = reg_equiv_constant (REGNO (new0)); 2659 2660 new_rtx = form_sum (GET_MODE (x), new0, new1); 2661 2662 /* As above, if we are not inside a MEM we do not want to 2663 turn a PLUS into something else. We might try to do so here 2664 for an addition of 0 if we aren't optimizing. */ 2665 if (! mem_mode && GET_CODE (new_rtx) != PLUS) 2666 return gen_rtx_PLUS (GET_MODE (x), new_rtx, const0_rtx); 2667 else 2668 return new_rtx; 2669 } 2670 } 2671 return x; 2672 2673 case MULT: 2674 /* If this is the product of an eliminable register and a 2675 constant, apply the distribute law and move the constant out 2676 so that we have (plus (mult ..) ..). This is needed in order 2677 to keep load-address insns valid. This case is pathological. 2678 We ignore the possibility of overflow here. */ 2679 if (REG_P (XEXP (x, 0)) 2680 && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER 2681 && CONST_INT_P (XEXP (x, 1))) 2682 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2683 ep++) 2684 if (ep->from_rtx == XEXP (x, 0) && ep->can_eliminate) 2685 { 2686 if (! mem_mode 2687 /* Refs inside notes or in DEBUG_INSNs don't count for 2688 this purpose. */ 2689 && ! (insn != 0 && (GET_CODE (insn) == EXPR_LIST 2690 || GET_CODE (insn) == INSN_LIST 2691 || DEBUG_INSN_P (insn)))) 2692 ep->ref_outside_mem = 1; 2693 2694 return 2695 plus_constant (Pmode, 2696 gen_rtx_MULT (Pmode, ep->to_rtx, XEXP (x, 1)), 2697 ep->previous_offset * INTVAL (XEXP (x, 1))); 2698 } 2699 2700 /* fall through */ 2701 2702 case CALL: 2703 case COMPARE: 2704 /* See comments before PLUS about handling MINUS. */ 2705 case MINUS: 2706 case DIV: case UDIV: 2707 case MOD: case UMOD: 2708 case AND: case IOR: case XOR: 2709 case ROTATERT: case ROTATE: 2710 case ASHIFTRT: case LSHIFTRT: case ASHIFT: 2711 case NE: case EQ: 2712 case GE: case GT: case GEU: case GTU: 2713 case LE: case LT: case LEU: case LTU: 2714 { 2715 rtx new0 = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false, 2716 for_costs); 2717 rtx new1 = XEXP (x, 1) 2718 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, false, 2719 for_costs) : 0; 2720 2721 if (new0 != XEXP (x, 0) || new1 != XEXP (x, 1)) 2722 return gen_rtx_fmt_ee (code, GET_MODE (x), new0, new1); 2723 } 2724 return x; 2725 2726 case EXPR_LIST: 2727 /* If we have something in XEXP (x, 0), the usual case, eliminate it. */ 2728 if (XEXP (x, 0)) 2729 { 2730 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, true, 2731 for_costs); 2732 if (new_rtx != XEXP (x, 0)) 2733 { 2734 /* If this is a REG_DEAD note, it is not valid anymore. 2735 Using the eliminated version could result in creating a 2736 REG_DEAD note for the stack or frame pointer. */ 2737 if (REG_NOTE_KIND (x) == REG_DEAD) 2738 return (XEXP (x, 1) 2739 ? eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, 2740 for_costs) 2741 : NULL_RTX); 2742 2743 x = alloc_reg_note (REG_NOTE_KIND (x), new_rtx, XEXP (x, 1)); 2744 } 2745 } 2746 2747 /* fall through */ 2748 2749 case INSN_LIST: 2750 case INT_LIST: 2751 /* Now do eliminations in the rest of the chain. If this was 2752 an EXPR_LIST, this might result in allocating more memory than is 2753 strictly needed, but it simplifies the code. */ 2754 if (XEXP (x, 1)) 2755 { 2756 new_rtx = eliminate_regs_1 (XEXP (x, 1), mem_mode, insn, true, 2757 for_costs); 2758 if (new_rtx != XEXP (x, 1)) 2759 return 2760 gen_rtx_fmt_ee (GET_CODE (x), GET_MODE (x), XEXP (x, 0), new_rtx); 2761 } 2762 return x; 2763 2764 case PRE_INC: 2765 case POST_INC: 2766 case PRE_DEC: 2767 case POST_DEC: 2768 /* We do not support elimination of a register that is modified. 2769 elimination_effects has already make sure that this does not 2770 happen. */ 2771 return x; 2772 2773 case PRE_MODIFY: 2774 case POST_MODIFY: 2775 /* We do not support elimination of a register that is modified. 2776 elimination_effects has already make sure that this does not 2777 happen. The only remaining case we need to consider here is 2778 that the increment value may be an eliminable register. */ 2779 if (GET_CODE (XEXP (x, 1)) == PLUS 2780 && XEXP (XEXP (x, 1), 0) == XEXP (x, 0)) 2781 { 2782 rtx new_rtx = eliminate_regs_1 (XEXP (XEXP (x, 1), 1), mem_mode, 2783 insn, true, for_costs); 2784 2785 if (new_rtx != XEXP (XEXP (x, 1), 1)) 2786 return gen_rtx_fmt_ee (code, GET_MODE (x), XEXP (x, 0), 2787 gen_rtx_PLUS (GET_MODE (x), 2788 XEXP (x, 0), new_rtx)); 2789 } 2790 return x; 2791 2792 case STRICT_LOW_PART: 2793 case NEG: case NOT: 2794 case SIGN_EXTEND: case ZERO_EXTEND: 2795 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: 2796 case FLOAT: case FIX: 2797 case UNSIGNED_FIX: case UNSIGNED_FLOAT: 2798 case ABS: 2799 case SQRT: 2800 case FFS: 2801 case CLZ: 2802 case CTZ: 2803 case POPCOUNT: 2804 case PARITY: 2805 case BSWAP: 2806 new_rtx = eliminate_regs_1 (XEXP (x, 0), mem_mode, insn, false, 2807 for_costs); 2808 if (new_rtx != XEXP (x, 0)) 2809 return gen_rtx_fmt_e (code, GET_MODE (x), new_rtx); 2810 return x; 2811 2812 case SUBREG: 2813 /* Similar to above processing, but preserve SUBREG_BYTE. 2814 Convert (subreg (mem)) to (mem) if not paradoxical. 2815 Also, if we have a non-paradoxical (subreg (pseudo)) and the 2816 pseudo didn't get a hard reg, we must replace this with the 2817 eliminated version of the memory location because push_reload 2818 may do the replacement in certain circumstances. */ 2819 if (REG_P (SUBREG_REG (x)) 2820 && !paradoxical_subreg_p (x) 2821 && reg_equivs 2822 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0) 2823 { 2824 new_rtx = SUBREG_REG (x); 2825 } 2826 else 2827 new_rtx = eliminate_regs_1 (SUBREG_REG (x), mem_mode, insn, false, for_costs); 2828 2829 if (new_rtx != SUBREG_REG (x)) 2830 { 2831 poly_int64 x_size = GET_MODE_SIZE (GET_MODE (x)); 2832 poly_int64 new_size = GET_MODE_SIZE (GET_MODE (new_rtx)); 2833 2834 if (MEM_P (new_rtx) 2835 && ((partial_subreg_p (GET_MODE (x), GET_MODE (new_rtx)) 2836 /* On RISC machines, combine can create rtl of the form 2837 (set (subreg:m1 (reg:m2 R) 0) ...) 2838 where m1 < m2, and expects something interesting to 2839 happen to the entire word. Moreover, it will use the 2840 (reg:m2 R) later, expecting all bits to be preserved. 2841 So if the number of words is the same, preserve the 2842 subreg so that push_reload can see it. */ 2843 && !(WORD_REGISTER_OPERATIONS 2844 && known_equal_after_align_down (x_size - 1, 2845 new_size - 1, 2846 UNITS_PER_WORD))) 2847 || known_eq (x_size, new_size)) 2848 ) 2849 return adjust_address_nv (new_rtx, GET_MODE (x), SUBREG_BYTE (x)); 2850 else if (insn && GET_CODE (insn) == DEBUG_INSN) 2851 return gen_rtx_raw_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x)); 2852 else 2853 return gen_rtx_SUBREG (GET_MODE (x), new_rtx, SUBREG_BYTE (x)); 2854 } 2855 2856 return x; 2857 2858 case MEM: 2859 /* Our only special processing is to pass the mode of the MEM to our 2860 recursive call and copy the flags. While we are here, handle this 2861 case more efficiently. */ 2862 2863 new_rtx = eliminate_regs_1 (XEXP (x, 0), GET_MODE (x), insn, true, 2864 for_costs); 2865 if (for_costs 2866 && memory_address_p (GET_MODE (x), XEXP (x, 0)) 2867 && !memory_address_p (GET_MODE (x), new_rtx)) 2868 note_reg_elim_costly (XEXP (x, 0), insn); 2869 2870 return replace_equiv_address_nv (x, new_rtx); 2871 2872 case USE: 2873 /* Handle insn_list USE that a call to a pure function may generate. */ 2874 new_rtx = eliminate_regs_1 (XEXP (x, 0), VOIDmode, insn, false, 2875 for_costs); 2876 if (new_rtx != XEXP (x, 0)) 2877 return gen_rtx_USE (GET_MODE (x), new_rtx); 2878 return x; 2879 2880 case CLOBBER: 2881 case ASM_OPERANDS: 2882 gcc_assert (insn && DEBUG_INSN_P (insn)); 2883 break; 2884 2885 case SET: 2886 gcc_unreachable (); 2887 2888 default: 2889 break; 2890 } 2891 2892 /* Process each of our operands recursively. If any have changed, make a 2893 copy of the rtx. */ 2894 fmt = GET_RTX_FORMAT (code); 2895 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 2896 { 2897 if (*fmt == 'e') 2898 { 2899 new_rtx = eliminate_regs_1 (XEXP (x, i), mem_mode, insn, false, 2900 for_costs); 2901 if (new_rtx != XEXP (x, i) && ! copied) 2902 { 2903 x = shallow_copy_rtx (x); 2904 copied = 1; 2905 } 2906 XEXP (x, i) = new_rtx; 2907 } 2908 else if (*fmt == 'E') 2909 { 2910 int copied_vec = 0; 2911 for (j = 0; j < XVECLEN (x, i); j++) 2912 { 2913 new_rtx = eliminate_regs_1 (XVECEXP (x, i, j), mem_mode, insn, false, 2914 for_costs); 2915 if (new_rtx != XVECEXP (x, i, j) && ! copied_vec) 2916 { 2917 rtvec new_v = gen_rtvec_v (XVECLEN (x, i), 2918 XVEC (x, i)->elem); 2919 if (! copied) 2920 { 2921 x = shallow_copy_rtx (x); 2922 copied = 1; 2923 } 2924 XVEC (x, i) = new_v; 2925 copied_vec = 1; 2926 } 2927 XVECEXP (x, i, j) = new_rtx; 2928 } 2929 } 2930 } 2931 2932 return x; 2933 } 2934 2935 rtx 2936 eliminate_regs (rtx x, machine_mode mem_mode, rtx insn) 2937 { 2938 if (reg_eliminate == NULL) 2939 { 2940 gcc_assert (targetm.no_register_allocation); 2941 return x; 2942 } 2943 return eliminate_regs_1 (x, mem_mode, insn, false, false); 2944 } 2945 2946 /* Scan rtx X for modifications of elimination target registers. Update 2947 the table of eliminables to reflect the changed state. MEM_MODE is 2948 the mode of an enclosing MEM rtx, or VOIDmode if not within a MEM. */ 2949 2950 static void 2951 elimination_effects (rtx x, machine_mode mem_mode) 2952 { 2953 enum rtx_code code = GET_CODE (x); 2954 struct elim_table *ep; 2955 int regno; 2956 int i, j; 2957 const char *fmt; 2958 2959 switch (code) 2960 { 2961 CASE_CONST_ANY: 2962 case CONST: 2963 case SYMBOL_REF: 2964 case CODE_LABEL: 2965 case PC: 2966 case CC0: 2967 case ASM_INPUT: 2968 case ADDR_VEC: 2969 case ADDR_DIFF_VEC: 2970 case RETURN: 2971 return; 2972 2973 case REG: 2974 regno = REGNO (x); 2975 2976 /* First handle the case where we encounter a bare register that 2977 is eliminable. Replace it with a PLUS. */ 2978 if (regno < FIRST_PSEUDO_REGISTER) 2979 { 2980 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 2981 ep++) 2982 if (ep->from_rtx == x && ep->can_eliminate) 2983 { 2984 if (! mem_mode) 2985 ep->ref_outside_mem = 1; 2986 return; 2987 } 2988 2989 } 2990 else if (reg_renumber[regno] < 0 2991 && reg_equivs 2992 && reg_equiv_constant (regno) 2993 && ! function_invariant_p (reg_equiv_constant (regno))) 2994 elimination_effects (reg_equiv_constant (regno), mem_mode); 2995 return; 2996 2997 case PRE_INC: 2998 case POST_INC: 2999 case PRE_DEC: 3000 case POST_DEC: 3001 case POST_MODIFY: 3002 case PRE_MODIFY: 3003 /* If we modify the source of an elimination rule, disable it. */ 3004 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3005 if (ep->from_rtx == XEXP (x, 0)) 3006 ep->can_eliminate = 0; 3007 3008 /* If we modify the target of an elimination rule by adding a constant, 3009 update its offset. If we modify the target in any other way, we'll 3010 have to disable the rule as well. */ 3011 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3012 if (ep->to_rtx == XEXP (x, 0)) 3013 { 3014 poly_int64 size = GET_MODE_SIZE (mem_mode); 3015 3016 /* If more bytes than MEM_MODE are pushed, account for them. */ 3017 #ifdef PUSH_ROUNDING 3018 if (ep->to_rtx == stack_pointer_rtx) 3019 size = PUSH_ROUNDING (size); 3020 #endif 3021 if (code == PRE_DEC || code == POST_DEC) 3022 ep->offset += size; 3023 else if (code == PRE_INC || code == POST_INC) 3024 ep->offset -= size; 3025 else if (code == PRE_MODIFY || code == POST_MODIFY) 3026 { 3027 if (GET_CODE (XEXP (x, 1)) == PLUS 3028 && XEXP (x, 0) == XEXP (XEXP (x, 1), 0) 3029 && CONST_INT_P (XEXP (XEXP (x, 1), 1))) 3030 ep->offset -= INTVAL (XEXP (XEXP (x, 1), 1)); 3031 else 3032 ep->can_eliminate = 0; 3033 } 3034 } 3035 3036 /* These two aren't unary operators. */ 3037 if (code == POST_MODIFY || code == PRE_MODIFY) 3038 break; 3039 3040 /* Fall through to generic unary operation case. */ 3041 gcc_fallthrough (); 3042 case STRICT_LOW_PART: 3043 case NEG: case NOT: 3044 case SIGN_EXTEND: case ZERO_EXTEND: 3045 case TRUNCATE: case FLOAT_EXTEND: case FLOAT_TRUNCATE: 3046 case FLOAT: case FIX: 3047 case UNSIGNED_FIX: case UNSIGNED_FLOAT: 3048 case ABS: 3049 case SQRT: 3050 case FFS: 3051 case CLZ: 3052 case CTZ: 3053 case POPCOUNT: 3054 case PARITY: 3055 case BSWAP: 3056 elimination_effects (XEXP (x, 0), mem_mode); 3057 return; 3058 3059 case SUBREG: 3060 if (REG_P (SUBREG_REG (x)) 3061 && !paradoxical_subreg_p (x) 3062 && reg_equivs 3063 && reg_equiv_memory_loc (REGNO (SUBREG_REG (x))) != 0) 3064 return; 3065 3066 elimination_effects (SUBREG_REG (x), mem_mode); 3067 return; 3068 3069 case USE: 3070 /* If using a register that is the source of an eliminate we still 3071 think can be performed, note it cannot be performed since we don't 3072 know how this register is used. */ 3073 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3074 if (ep->from_rtx == XEXP (x, 0)) 3075 ep->can_eliminate = 0; 3076 3077 elimination_effects (XEXP (x, 0), mem_mode); 3078 return; 3079 3080 case CLOBBER: 3081 /* If clobbering a register that is the replacement register for an 3082 elimination we still think can be performed, note that it cannot 3083 be performed. Otherwise, we need not be concerned about it. */ 3084 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3085 if (ep->to_rtx == XEXP (x, 0)) 3086 ep->can_eliminate = 0; 3087 3088 elimination_effects (XEXP (x, 0), mem_mode); 3089 return; 3090 3091 case SET: 3092 /* Check for setting a register that we know about. */ 3093 if (REG_P (SET_DEST (x))) 3094 { 3095 /* See if this is setting the replacement register for an 3096 elimination. 3097 3098 If DEST is the hard frame pointer, we do nothing because we 3099 assume that all assignments to the frame pointer are for 3100 non-local gotos and are being done at a time when they are valid 3101 and do not disturb anything else. Some machines want to 3102 eliminate a fake argument pointer (or even a fake frame pointer) 3103 with either the real frame or the stack pointer. Assignments to 3104 the hard frame pointer must not prevent this elimination. */ 3105 3106 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3107 ep++) 3108 if (ep->to_rtx == SET_DEST (x) 3109 && SET_DEST (x) != hard_frame_pointer_rtx) 3110 { 3111 /* If it is being incremented, adjust the offset. Otherwise, 3112 this elimination can't be done. */ 3113 rtx src = SET_SRC (x); 3114 3115 if (GET_CODE (src) == PLUS 3116 && XEXP (src, 0) == SET_DEST (x) 3117 && CONST_INT_P (XEXP (src, 1))) 3118 ep->offset -= INTVAL (XEXP (src, 1)); 3119 else 3120 ep->can_eliminate = 0; 3121 } 3122 } 3123 3124 elimination_effects (SET_DEST (x), VOIDmode); 3125 elimination_effects (SET_SRC (x), VOIDmode); 3126 return; 3127 3128 case MEM: 3129 /* Our only special processing is to pass the mode of the MEM to our 3130 recursive call. */ 3131 elimination_effects (XEXP (x, 0), GET_MODE (x)); 3132 return; 3133 3134 default: 3135 break; 3136 } 3137 3138 fmt = GET_RTX_FORMAT (code); 3139 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 3140 { 3141 if (*fmt == 'e') 3142 elimination_effects (XEXP (x, i), mem_mode); 3143 else if (*fmt == 'E') 3144 for (j = 0; j < XVECLEN (x, i); j++) 3145 elimination_effects (XVECEXP (x, i, j), mem_mode); 3146 } 3147 } 3148 3149 /* Descend through rtx X and verify that no references to eliminable registers 3150 remain. If any do remain, mark the involved register as not 3151 eliminable. */ 3152 3153 static void 3154 check_eliminable_occurrences (rtx x) 3155 { 3156 const char *fmt; 3157 int i; 3158 enum rtx_code code; 3159 3160 if (x == 0) 3161 return; 3162 3163 code = GET_CODE (x); 3164 3165 if (code == REG && REGNO (x) < FIRST_PSEUDO_REGISTER) 3166 { 3167 struct elim_table *ep; 3168 3169 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3170 if (ep->from_rtx == x) 3171 ep->can_eliminate = 0; 3172 return; 3173 } 3174 3175 fmt = GET_RTX_FORMAT (code); 3176 for (i = 0; i < GET_RTX_LENGTH (code); i++, fmt++) 3177 { 3178 if (*fmt == 'e') 3179 check_eliminable_occurrences (XEXP (x, i)); 3180 else if (*fmt == 'E') 3181 { 3182 int j; 3183 for (j = 0; j < XVECLEN (x, i); j++) 3184 check_eliminable_occurrences (XVECEXP (x, i, j)); 3185 } 3186 } 3187 } 3188 3189 /* Scan INSN and eliminate all eliminable registers in it. 3190 3191 If REPLACE is nonzero, do the replacement destructively. Also 3192 delete the insn as dead it if it is setting an eliminable register. 3193 3194 If REPLACE is zero, do all our allocations in reload_obstack. 3195 3196 If no eliminations were done and this insn doesn't require any elimination 3197 processing (these are not identical conditions: it might be updating sp, 3198 but not referencing fp; this needs to be seen during reload_as_needed so 3199 that the offset between fp and sp can be taken into consideration), zero 3200 is returned. Otherwise, 1 is returned. */ 3201 3202 static int 3203 eliminate_regs_in_insn (rtx_insn *insn, int replace) 3204 { 3205 int icode = recog_memoized (insn); 3206 rtx old_body = PATTERN (insn); 3207 int insn_is_asm = asm_noperands (old_body) >= 0; 3208 rtx old_set = single_set (insn); 3209 rtx new_body; 3210 int val = 0; 3211 int i; 3212 rtx substed_operand[MAX_RECOG_OPERANDS]; 3213 rtx orig_operand[MAX_RECOG_OPERANDS]; 3214 struct elim_table *ep; 3215 rtx plus_src, plus_cst_src; 3216 3217 if (! insn_is_asm && icode < 0) 3218 { 3219 gcc_assert (DEBUG_INSN_P (insn) 3220 || GET_CODE (PATTERN (insn)) == USE 3221 || GET_CODE (PATTERN (insn)) == CLOBBER 3222 || GET_CODE (PATTERN (insn)) == ASM_INPUT); 3223 if (DEBUG_BIND_INSN_P (insn)) 3224 INSN_VAR_LOCATION_LOC (insn) 3225 = eliminate_regs (INSN_VAR_LOCATION_LOC (insn), VOIDmode, insn); 3226 return 0; 3227 } 3228 3229 /* We allow one special case which happens to work on all machines we 3230 currently support: a single set with the source or a REG_EQUAL 3231 note being a PLUS of an eliminable register and a constant. */ 3232 plus_src = plus_cst_src = 0; 3233 if (old_set && REG_P (SET_DEST (old_set))) 3234 { 3235 if (GET_CODE (SET_SRC (old_set)) == PLUS) 3236 plus_src = SET_SRC (old_set); 3237 /* First see if the source is of the form (plus (...) CST). */ 3238 if (plus_src 3239 && CONST_INT_P (XEXP (plus_src, 1))) 3240 plus_cst_src = plus_src; 3241 else if (REG_P (SET_SRC (old_set)) 3242 || plus_src) 3243 { 3244 /* Otherwise, see if we have a REG_EQUAL note of the form 3245 (plus (...) CST). */ 3246 rtx links; 3247 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 3248 { 3249 if ((REG_NOTE_KIND (links) == REG_EQUAL 3250 || REG_NOTE_KIND (links) == REG_EQUIV) 3251 && GET_CODE (XEXP (links, 0)) == PLUS 3252 && CONST_INT_P (XEXP (XEXP (links, 0), 1))) 3253 { 3254 plus_cst_src = XEXP (links, 0); 3255 break; 3256 } 3257 } 3258 } 3259 3260 /* Check that the first operand of the PLUS is a hard reg or 3261 the lowpart subreg of one. */ 3262 if (plus_cst_src) 3263 { 3264 rtx reg = XEXP (plus_cst_src, 0); 3265 if (GET_CODE (reg) == SUBREG && subreg_lowpart_p (reg)) 3266 reg = SUBREG_REG (reg); 3267 3268 if (!REG_P (reg) || REGNO (reg) >= FIRST_PSEUDO_REGISTER) 3269 plus_cst_src = 0; 3270 } 3271 } 3272 if (plus_cst_src) 3273 { 3274 rtx reg = XEXP (plus_cst_src, 0); 3275 poly_int64 offset = INTVAL (XEXP (plus_cst_src, 1)); 3276 3277 if (GET_CODE (reg) == SUBREG) 3278 reg = SUBREG_REG (reg); 3279 3280 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3281 if (ep->from_rtx == reg && ep->can_eliminate) 3282 { 3283 rtx to_rtx = ep->to_rtx; 3284 offset += ep->offset; 3285 offset = trunc_int_for_mode (offset, GET_MODE (plus_cst_src)); 3286 3287 if (GET_CODE (XEXP (plus_cst_src, 0)) == SUBREG) 3288 to_rtx = gen_lowpart (GET_MODE (XEXP (plus_cst_src, 0)), 3289 to_rtx); 3290 /* If we have a nonzero offset, and the source is already 3291 a simple REG, the following transformation would 3292 increase the cost of the insn by replacing a simple REG 3293 with (plus (reg sp) CST). So try only when we already 3294 had a PLUS before. */ 3295 if (known_eq (offset, 0) || plus_src) 3296 { 3297 rtx new_src = plus_constant (GET_MODE (to_rtx), 3298 to_rtx, offset); 3299 3300 new_body = old_body; 3301 if (! replace) 3302 { 3303 new_body = copy_insn (old_body); 3304 if (REG_NOTES (insn)) 3305 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); 3306 } 3307 PATTERN (insn) = new_body; 3308 old_set = single_set (insn); 3309 3310 /* First see if this insn remains valid when we make the 3311 change. If not, try to replace the whole pattern with 3312 a simple set (this may help if the original insn was a 3313 PARALLEL that was only recognized as single_set due to 3314 REG_UNUSED notes). If this isn't valid either, keep 3315 the INSN_CODE the same and let reload fix it up. */ 3316 if (!validate_change (insn, &SET_SRC (old_set), new_src, 0)) 3317 { 3318 rtx new_pat = gen_rtx_SET (SET_DEST (old_set), new_src); 3319 3320 if (!validate_change (insn, &PATTERN (insn), new_pat, 0)) 3321 SET_SRC (old_set) = new_src; 3322 } 3323 } 3324 else 3325 break; 3326 3327 val = 1; 3328 /* This can't have an effect on elimination offsets, so skip right 3329 to the end. */ 3330 goto done; 3331 } 3332 } 3333 3334 /* Determine the effects of this insn on elimination offsets. */ 3335 elimination_effects (old_body, VOIDmode); 3336 3337 /* Eliminate all eliminable registers occurring in operands that 3338 can be handled by reload. */ 3339 extract_insn (insn); 3340 for (i = 0; i < recog_data.n_operands; i++) 3341 { 3342 orig_operand[i] = recog_data.operand[i]; 3343 substed_operand[i] = recog_data.operand[i]; 3344 3345 /* For an asm statement, every operand is eliminable. */ 3346 if (insn_is_asm || insn_data[icode].operand[i].eliminable) 3347 { 3348 bool is_set_src, in_plus; 3349 3350 /* Check for setting a register that we know about. */ 3351 if (recog_data.operand_type[i] != OP_IN 3352 && REG_P (orig_operand[i])) 3353 { 3354 /* If we are assigning to a register that can be eliminated, it 3355 must be as part of a PARALLEL, since the code above handles 3356 single SETs. We must indicate that we can no longer 3357 eliminate this reg. */ 3358 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3359 ep++) 3360 if (ep->from_rtx == orig_operand[i]) 3361 ep->can_eliminate = 0; 3362 } 3363 3364 /* Companion to the above plus substitution, we can allow 3365 invariants as the source of a plain move. */ 3366 is_set_src = false; 3367 if (old_set 3368 && recog_data.operand_loc[i] == &SET_SRC (old_set)) 3369 is_set_src = true; 3370 in_plus = false; 3371 if (plus_src 3372 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0) 3373 || recog_data.operand_loc[i] == &XEXP (plus_src, 1))) 3374 in_plus = true; 3375 3376 substed_operand[i] 3377 = eliminate_regs_1 (recog_data.operand[i], VOIDmode, 3378 replace ? insn : NULL_RTX, 3379 is_set_src || in_plus, false); 3380 if (substed_operand[i] != orig_operand[i]) 3381 val = 1; 3382 /* Terminate the search in check_eliminable_occurrences at 3383 this point. */ 3384 *recog_data.operand_loc[i] = 0; 3385 3386 /* If an output operand changed from a REG to a MEM and INSN is an 3387 insn, write a CLOBBER insn. */ 3388 if (recog_data.operand_type[i] != OP_IN 3389 && REG_P (orig_operand[i]) 3390 && MEM_P (substed_operand[i]) 3391 && replace) 3392 emit_insn_after (gen_clobber (orig_operand[i]), insn); 3393 } 3394 } 3395 3396 for (i = 0; i < recog_data.n_dups; i++) 3397 *recog_data.dup_loc[i] 3398 = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; 3399 3400 /* If any eliminable remain, they aren't eliminable anymore. */ 3401 check_eliminable_occurrences (old_body); 3402 3403 /* Substitute the operands; the new values are in the substed_operand 3404 array. */ 3405 for (i = 0; i < recog_data.n_operands; i++) 3406 *recog_data.operand_loc[i] = substed_operand[i]; 3407 for (i = 0; i < recog_data.n_dups; i++) 3408 *recog_data.dup_loc[i] = substed_operand[(int) recog_data.dup_num[i]]; 3409 3410 /* If we are replacing a body that was a (set X (plus Y Z)), try to 3411 re-recognize the insn. We do this in case we had a simple addition 3412 but now can do this as a load-address. This saves an insn in this 3413 common case. 3414 If re-recognition fails, the old insn code number will still be used, 3415 and some register operands may have changed into PLUS expressions. 3416 These will be handled by find_reloads by loading them into a register 3417 again. */ 3418 3419 if (val) 3420 { 3421 /* If we aren't replacing things permanently and we changed something, 3422 make another copy to ensure that all the RTL is new. Otherwise 3423 things can go wrong if find_reload swaps commutative operands 3424 and one is inside RTL that has been copied while the other is not. */ 3425 new_body = old_body; 3426 if (! replace) 3427 { 3428 new_body = copy_insn (old_body); 3429 if (REG_NOTES (insn)) 3430 REG_NOTES (insn) = copy_insn_1 (REG_NOTES (insn)); 3431 } 3432 PATTERN (insn) = new_body; 3433 3434 /* If we had a move insn but now we don't, rerecognize it. This will 3435 cause spurious re-recognition if the old move had a PARALLEL since 3436 the new one still will, but we can't call single_set without 3437 having put NEW_BODY into the insn and the re-recognition won't 3438 hurt in this rare case. */ 3439 /* ??? Why this huge if statement - why don't we just rerecognize the 3440 thing always? */ 3441 if (! insn_is_asm 3442 && old_set != 0 3443 && ((REG_P (SET_SRC (old_set)) 3444 && (GET_CODE (new_body) != SET 3445 || !REG_P (SET_SRC (new_body)))) 3446 /* If this was a load from or store to memory, compare 3447 the MEM in recog_data.operand to the one in the insn. 3448 If they are not equal, then rerecognize the insn. */ 3449 || (old_set != 0 3450 && ((MEM_P (SET_SRC (old_set)) 3451 && SET_SRC (old_set) != recog_data.operand[1]) 3452 || (MEM_P (SET_DEST (old_set)) 3453 && SET_DEST (old_set) != recog_data.operand[0]))) 3454 /* If this was an add insn before, rerecognize. */ 3455 || GET_CODE (SET_SRC (old_set)) == PLUS)) 3456 { 3457 int new_icode = recog (PATTERN (insn), insn, 0); 3458 if (new_icode >= 0) 3459 INSN_CODE (insn) = new_icode; 3460 } 3461 } 3462 3463 /* Restore the old body. If there were any changes to it, we made a copy 3464 of it while the changes were still in place, so we'll correctly return 3465 a modified insn below. */ 3466 if (! replace) 3467 { 3468 /* Restore the old body. */ 3469 for (i = 0; i < recog_data.n_operands; i++) 3470 /* Restoring a top-level match_parallel would clobber the new_body 3471 we installed in the insn. */ 3472 if (recog_data.operand_loc[i] != &PATTERN (insn)) 3473 *recog_data.operand_loc[i] = orig_operand[i]; 3474 for (i = 0; i < recog_data.n_dups; i++) 3475 *recog_data.dup_loc[i] = orig_operand[(int) recog_data.dup_num[i]]; 3476 } 3477 3478 /* Update all elimination pairs to reflect the status after the current 3479 insn. The changes we make were determined by the earlier call to 3480 elimination_effects. 3481 3482 We also detect cases where register elimination cannot be done, 3483 namely, if a register would be both changed and referenced outside a MEM 3484 in the resulting insn since such an insn is often undefined and, even if 3485 not, we cannot know what meaning will be given to it. Note that it is 3486 valid to have a register used in an address in an insn that changes it 3487 (presumably with a pre- or post-increment or decrement). 3488 3489 If anything changes, return nonzero. */ 3490 3491 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3492 { 3493 if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem) 3494 ep->can_eliminate = 0; 3495 3496 ep->ref_outside_mem = 0; 3497 3498 if (maybe_ne (ep->previous_offset, ep->offset)) 3499 val = 1; 3500 } 3501 3502 done: 3503 /* If we changed something, perform elimination in REG_NOTES. This is 3504 needed even when REPLACE is zero because a REG_DEAD note might refer 3505 to a register that we eliminate and could cause a different number 3506 of spill registers to be needed in the final reload pass than in 3507 the pre-passes. */ 3508 if (val && REG_NOTES (insn) != 0) 3509 REG_NOTES (insn) 3510 = eliminate_regs_1 (REG_NOTES (insn), VOIDmode, REG_NOTES (insn), true, 3511 false); 3512 3513 return val; 3514 } 3515 3516 /* Like eliminate_regs_in_insn, but only estimate costs for the use of the 3517 register allocator. INSN is the instruction we need to examine, we perform 3518 eliminations in its operands and record cases where eliminating a reg with 3519 an invariant equivalence would add extra cost. */ 3520 3521 #pragma GCC diagnostic push 3522 #pragma GCC diagnostic warning "-Wmaybe-uninitialized" 3523 static void 3524 elimination_costs_in_insn (rtx_insn *insn) 3525 { 3526 int icode = recog_memoized (insn); 3527 rtx old_body = PATTERN (insn); 3528 int insn_is_asm = asm_noperands (old_body) >= 0; 3529 rtx old_set = single_set (insn); 3530 int i; 3531 rtx orig_operand[MAX_RECOG_OPERANDS]; 3532 rtx orig_dup[MAX_RECOG_OPERANDS]; 3533 struct elim_table *ep; 3534 rtx plus_src, plus_cst_src; 3535 bool sets_reg_p; 3536 3537 if (! insn_is_asm && icode < 0) 3538 { 3539 gcc_assert (DEBUG_INSN_P (insn) 3540 || GET_CODE (PATTERN (insn)) == USE 3541 || GET_CODE (PATTERN (insn)) == CLOBBER 3542 || GET_CODE (PATTERN (insn)) == ASM_INPUT); 3543 return; 3544 } 3545 3546 if (old_set != 0 && REG_P (SET_DEST (old_set)) 3547 && REGNO (SET_DEST (old_set)) < FIRST_PSEUDO_REGISTER) 3548 { 3549 /* Check for setting an eliminable register. */ 3550 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3551 if (ep->from_rtx == SET_DEST (old_set) && ep->can_eliminate) 3552 return; 3553 } 3554 3555 /* We allow one special case which happens to work on all machines we 3556 currently support: a single set with the source or a REG_EQUAL 3557 note being a PLUS of an eliminable register and a constant. */ 3558 plus_src = plus_cst_src = 0; 3559 sets_reg_p = false; 3560 if (old_set && REG_P (SET_DEST (old_set))) 3561 { 3562 sets_reg_p = true; 3563 if (GET_CODE (SET_SRC (old_set)) == PLUS) 3564 plus_src = SET_SRC (old_set); 3565 /* First see if the source is of the form (plus (...) CST). */ 3566 if (plus_src 3567 && CONST_INT_P (XEXP (plus_src, 1))) 3568 plus_cst_src = plus_src; 3569 else if (REG_P (SET_SRC (old_set)) 3570 || plus_src) 3571 { 3572 /* Otherwise, see if we have a REG_EQUAL note of the form 3573 (plus (...) CST). */ 3574 rtx links; 3575 for (links = REG_NOTES (insn); links; links = XEXP (links, 1)) 3576 { 3577 if ((REG_NOTE_KIND (links) == REG_EQUAL 3578 || REG_NOTE_KIND (links) == REG_EQUIV) 3579 && GET_CODE (XEXP (links, 0)) == PLUS 3580 && CONST_INT_P (XEXP (XEXP (links, 0), 1))) 3581 { 3582 plus_cst_src = XEXP (links, 0); 3583 break; 3584 } 3585 } 3586 } 3587 } 3588 3589 /* Determine the effects of this insn on elimination offsets. */ 3590 elimination_effects (old_body, VOIDmode); 3591 3592 /* Eliminate all eliminable registers occurring in operands that 3593 can be handled by reload. */ 3594 extract_insn (insn); 3595 int n_dups = recog_data.n_dups; 3596 for (i = 0; i < n_dups; i++) 3597 orig_dup[i] = *recog_data.dup_loc[i]; 3598 3599 int n_operands = recog_data.n_operands; 3600 for (i = 0; i < n_operands; i++) 3601 { 3602 orig_operand[i] = recog_data.operand[i]; 3603 3604 /* For an asm statement, every operand is eliminable. */ 3605 if (insn_is_asm || insn_data[icode].operand[i].eliminable) 3606 { 3607 bool is_set_src, in_plus; 3608 3609 /* Check for setting a register that we know about. */ 3610 if (recog_data.operand_type[i] != OP_IN 3611 && REG_P (orig_operand[i])) 3612 { 3613 /* If we are assigning to a register that can be eliminated, it 3614 must be as part of a PARALLEL, since the code above handles 3615 single SETs. We must indicate that we can no longer 3616 eliminate this reg. */ 3617 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; 3618 ep++) 3619 if (ep->from_rtx == orig_operand[i]) 3620 ep->can_eliminate = 0; 3621 } 3622 3623 /* Companion to the above plus substitution, we can allow 3624 invariants as the source of a plain move. */ 3625 is_set_src = false; 3626 if (old_set && recog_data.operand_loc[i] == &SET_SRC (old_set)) 3627 is_set_src = true; 3628 if (is_set_src && !sets_reg_p) 3629 note_reg_elim_costly (SET_SRC (old_set), insn); 3630 in_plus = false; 3631 if (plus_src && sets_reg_p 3632 && (recog_data.operand_loc[i] == &XEXP (plus_src, 0) 3633 || recog_data.operand_loc[i] == &XEXP (plus_src, 1))) 3634 in_plus = true; 3635 3636 eliminate_regs_1 (recog_data.operand[i], VOIDmode, 3637 NULL_RTX, 3638 is_set_src || in_plus, true); 3639 /* Terminate the search in check_eliminable_occurrences at 3640 this point. */ 3641 *recog_data.operand_loc[i] = 0; 3642 } 3643 } 3644 3645 for (i = 0; i < n_dups; i++) 3646 *recog_data.dup_loc[i] 3647 = *recog_data.operand_loc[(int) recog_data.dup_num[i]]; 3648 3649 /* If any eliminable remain, they aren't eliminable anymore. */ 3650 check_eliminable_occurrences (old_body); 3651 3652 /* Restore the old body. */ 3653 for (i = 0; i < n_operands; i++) 3654 *recog_data.operand_loc[i] = orig_operand[i]; 3655 for (i = 0; i < n_dups; i++) 3656 *recog_data.dup_loc[i] = orig_dup[i]; 3657 3658 /* Update all elimination pairs to reflect the status after the current 3659 insn. The changes we make were determined by the earlier call to 3660 elimination_effects. */ 3661 3662 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3663 { 3664 if (maybe_ne (ep->previous_offset, ep->offset) && ep->ref_outside_mem) 3665 ep->can_eliminate = 0; 3666 3667 ep->ref_outside_mem = 0; 3668 } 3669 3670 return; 3671 } 3672 #pragma GCC diagnostic pop 3673 3674 /* Loop through all elimination pairs. 3675 Recalculate the number not at initial offset. 3676 3677 Compute the maximum offset (minimum offset if the stack does not 3678 grow downward) for each elimination pair. */ 3679 3680 static void 3681 update_eliminable_offsets (void) 3682 { 3683 struct elim_table *ep; 3684 3685 num_not_at_initial_offset = 0; 3686 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3687 { 3688 ep->previous_offset = ep->offset; 3689 if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset)) 3690 num_not_at_initial_offset++; 3691 } 3692 } 3693 3694 /* Given X, a SET or CLOBBER of DEST, if DEST is the target of a register 3695 replacement we currently believe is valid, mark it as not eliminable if X 3696 modifies DEST in any way other than by adding a constant integer to it. 3697 3698 If DEST is the frame pointer, we do nothing because we assume that 3699 all assignments to the hard frame pointer are nonlocal gotos and are being 3700 done at a time when they are valid and do not disturb anything else. 3701 Some machines want to eliminate a fake argument pointer with either the 3702 frame or stack pointer. Assignments to the hard frame pointer must not 3703 prevent this elimination. 3704 3705 Called via note_stores from reload before starting its passes to scan 3706 the insns of the function. */ 3707 3708 static void 3709 mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) 3710 { 3711 unsigned int i; 3712 3713 /* A SUBREG of a hard register here is just changing its mode. We should 3714 not see a SUBREG of an eliminable hard register, but check just in 3715 case. */ 3716 if (GET_CODE (dest) == SUBREG) 3717 dest = SUBREG_REG (dest); 3718 3719 if (dest == hard_frame_pointer_rtx) 3720 return; 3721 3722 for (i = 0; i < NUM_ELIMINABLE_REGS; i++) 3723 if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx 3724 && (GET_CODE (x) != SET 3725 || GET_CODE (SET_SRC (x)) != PLUS 3726 || XEXP (SET_SRC (x), 0) != dest 3727 || !CONST_INT_P (XEXP (SET_SRC (x), 1)))) 3728 { 3729 reg_eliminate[i].can_eliminate_previous 3730 = reg_eliminate[i].can_eliminate = 0; 3731 num_eliminable--; 3732 } 3733 } 3734 3735 /* Verify that the initial elimination offsets did not change since the 3736 last call to set_initial_elim_offsets. This is used to catch cases 3737 where something illegal happened during reload_as_needed that could 3738 cause incorrect code to be generated if we did not check for it. */ 3739 3740 static bool 3741 verify_initial_elim_offsets (void) 3742 { 3743 poly_int64 t; 3744 struct elim_table *ep; 3745 3746 if (!num_eliminable) 3747 return true; 3748 3749 targetm.compute_frame_layout (); 3750 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3751 { 3752 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, t); 3753 if (maybe_ne (t, ep->initial_offset)) 3754 return false; 3755 } 3756 3757 return true; 3758 } 3759 3760 /* Reset all offsets on eliminable registers to their initial values. */ 3761 3762 static void 3763 set_initial_elim_offsets (void) 3764 { 3765 struct elim_table *ep = reg_eliminate; 3766 3767 targetm.compute_frame_layout (); 3768 for (; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3769 { 3770 INITIAL_ELIMINATION_OFFSET (ep->from, ep->to, ep->initial_offset); 3771 ep->previous_offset = ep->offset = ep->initial_offset; 3772 } 3773 3774 num_not_at_initial_offset = 0; 3775 } 3776 3777 /* Subroutine of set_initial_label_offsets called via for_each_eh_label. */ 3778 3779 static void 3780 set_initial_eh_label_offset (rtx label) 3781 { 3782 set_label_offsets (label, NULL, 1); 3783 } 3784 3785 /* Initialize the known label offsets. 3786 Set a known offset for each forced label to be at the initial offset 3787 of each elimination. We do this because we assume that all 3788 computed jumps occur from a location where each elimination is 3789 at its initial offset. 3790 For all other labels, show that we don't know the offsets. */ 3791 3792 static void 3793 set_initial_label_offsets (void) 3794 { 3795 memset (offsets_known_at, 0, num_labels); 3796 3797 unsigned int i; 3798 rtx_insn *insn; 3799 FOR_EACH_VEC_SAFE_ELT (forced_labels, i, insn) 3800 set_label_offsets (insn, NULL, 1); 3801 3802 for (rtx_insn_list *x = nonlocal_goto_handler_labels; x; x = x->next ()) 3803 if (x->insn ()) 3804 set_label_offsets (x->insn (), NULL, 1); 3805 3806 for_each_eh_label (set_initial_eh_label_offset); 3807 } 3808 3809 /* Set all elimination offsets to the known values for the code label given 3810 by INSN. */ 3811 3812 static void 3813 set_offsets_for_label (rtx_insn *insn) 3814 { 3815 unsigned int i; 3816 int label_nr = CODE_LABEL_NUMBER (insn); 3817 struct elim_table *ep; 3818 3819 num_not_at_initial_offset = 0; 3820 for (i = 0, ep = reg_eliminate; i < NUM_ELIMINABLE_REGS; ep++, i++) 3821 { 3822 ep->offset = ep->previous_offset 3823 = offsets_at[label_nr - first_label_num][i]; 3824 if (ep->can_eliminate && maybe_ne (ep->offset, ep->initial_offset)) 3825 num_not_at_initial_offset++; 3826 } 3827 } 3828 3829 /* See if anything that happened changes which eliminations are valid. 3830 For example, on the SPARC, whether or not the frame pointer can 3831 be eliminated can depend on what registers have been used. We need 3832 not check some conditions again (such as flag_omit_frame_pointer) 3833 since they can't have changed. */ 3834 3835 static void 3836 update_eliminables (HARD_REG_SET *pset) 3837 { 3838 int previous_frame_pointer_needed = frame_pointer_needed; 3839 struct elim_table *ep; 3840 3841 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3842 if ((ep->from == HARD_FRAME_POINTER_REGNUM 3843 && targetm.frame_pointer_required ()) 3844 || ! targetm.can_eliminate (ep->from, ep->to) 3845 ) 3846 ep->can_eliminate = 0; 3847 3848 /* Look for the case where we have discovered that we can't replace 3849 register A with register B and that means that we will now be 3850 trying to replace register A with register C. This means we can 3851 no longer replace register C with register B and we need to disable 3852 such an elimination, if it exists. This occurs often with A == ap, 3853 B == sp, and C == fp. */ 3854 3855 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3856 { 3857 struct elim_table *op; 3858 int new_to = -1; 3859 3860 if (! ep->can_eliminate && ep->can_eliminate_previous) 3861 { 3862 /* Find the current elimination for ep->from, if there is a 3863 new one. */ 3864 for (op = reg_eliminate; 3865 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 3866 if (op->from == ep->from && op->can_eliminate) 3867 { 3868 new_to = op->to; 3869 break; 3870 } 3871 3872 /* See if there is an elimination of NEW_TO -> EP->TO. If so, 3873 disable it. */ 3874 for (op = reg_eliminate; 3875 op < ®_eliminate[NUM_ELIMINABLE_REGS]; op++) 3876 if (op->from == new_to && op->to == ep->to) 3877 op->can_eliminate = 0; 3878 } 3879 } 3880 3881 /* See if any registers that we thought we could eliminate the previous 3882 time are no longer eliminable. If so, something has changed and we 3883 must spill the register. Also, recompute the number of eliminable 3884 registers and see if the frame pointer is needed; it is if there is 3885 no elimination of the frame pointer that we can perform. */ 3886 3887 frame_pointer_needed = 1; 3888 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3889 { 3890 if (ep->can_eliminate 3891 && ep->from == FRAME_POINTER_REGNUM 3892 && ep->to != HARD_FRAME_POINTER_REGNUM 3893 && (! SUPPORTS_STACK_ALIGNMENT 3894 || ! crtl->stack_realign_needed)) 3895 frame_pointer_needed = 0; 3896 3897 if (! ep->can_eliminate && ep->can_eliminate_previous) 3898 { 3899 ep->can_eliminate_previous = 0; 3900 SET_HARD_REG_BIT (*pset, ep->from); 3901 num_eliminable--; 3902 } 3903 } 3904 3905 /* If we didn't need a frame pointer last time, but we do now, spill 3906 the hard frame pointer. */ 3907 if (frame_pointer_needed && ! previous_frame_pointer_needed) 3908 SET_HARD_REG_BIT (*pset, HARD_FRAME_POINTER_REGNUM); 3909 } 3910 3911 /* Call update_eliminables an spill any registers we can't eliminate anymore. 3912 Return true iff a register was spilled. */ 3913 3914 static bool 3915 update_eliminables_and_spill (void) 3916 { 3917 int i; 3918 bool did_spill = false; 3919 HARD_REG_SET to_spill; 3920 CLEAR_HARD_REG_SET (to_spill); 3921 update_eliminables (&to_spill); 3922 used_spill_regs &= ~to_spill; 3923 3924 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3925 if (TEST_HARD_REG_BIT (to_spill, i)) 3926 { 3927 spill_hard_reg (i, 1); 3928 did_spill = true; 3929 3930 /* Regardless of the state of spills, if we previously had 3931 a register that we thought we could eliminate, but now 3932 cannot eliminate, we must run another pass. 3933 3934 Consider pseudos which have an entry in reg_equiv_* which 3935 reference an eliminable register. We must make another pass 3936 to update reg_equiv_* so that we do not substitute in the 3937 old value from when we thought the elimination could be 3938 performed. */ 3939 } 3940 return did_spill; 3941 } 3942 3943 /* Return true if X is used as the target register of an elimination. */ 3944 3945 bool 3946 elimination_target_reg_p (rtx x) 3947 { 3948 struct elim_table *ep; 3949 3950 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3951 if (ep->to_rtx == x && ep->can_eliminate) 3952 return true; 3953 3954 return false; 3955 } 3956 3957 /* Initialize the table of registers to eliminate. 3958 Pre-condition: global flag frame_pointer_needed has been set before 3959 calling this function. */ 3960 3961 static void 3962 init_elim_table (void) 3963 { 3964 struct elim_table *ep; 3965 const struct elim_table_1 *ep1; 3966 3967 if (!reg_eliminate) 3968 reg_eliminate = XCNEWVEC (struct elim_table, NUM_ELIMINABLE_REGS); 3969 3970 num_eliminable = 0; 3971 3972 for (ep = reg_eliminate, ep1 = reg_eliminate_1; 3973 ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++, ep1++) 3974 { 3975 ep->from = ep1->from; 3976 ep->to = ep1->to; 3977 ep->can_eliminate = ep->can_eliminate_previous 3978 = (targetm.can_eliminate (ep->from, ep->to) 3979 && ! (ep->to == STACK_POINTER_REGNUM 3980 && frame_pointer_needed 3981 && (! SUPPORTS_STACK_ALIGNMENT 3982 || ! stack_realign_fp))); 3983 } 3984 3985 /* Count the number of eliminable registers and build the FROM and TO 3986 REG rtx's. Note that code in gen_rtx_REG will cause, e.g., 3987 gen_rtx_REG (Pmode, STACK_POINTER_REGNUM) to equal stack_pointer_rtx. 3988 We depend on this. */ 3989 for (ep = reg_eliminate; ep < ®_eliminate[NUM_ELIMINABLE_REGS]; ep++) 3990 { 3991 num_eliminable += ep->can_eliminate; 3992 ep->from_rtx = gen_rtx_REG (Pmode, ep->from); 3993 ep->to_rtx = gen_rtx_REG (Pmode, ep->to); 3994 } 3995 } 3996 3997 /* Find all the pseudo registers that didn't get hard regs 3998 but do have known equivalent constants or memory slots. 3999 These include parameters (known equivalent to parameter slots) 4000 and cse'd or loop-moved constant memory addresses. 4001 4002 Record constant equivalents in reg_equiv_constant 4003 so they will be substituted by find_reloads. 4004 Record memory equivalents in reg_mem_equiv so they can 4005 be substituted eventually by altering the REG-rtx's. */ 4006 4007 static void 4008 init_eliminable_invariants (rtx_insn *first, bool do_subregs) 4009 { 4010 int i; 4011 rtx_insn *insn; 4012 4013 grow_reg_equivs (); 4014 if (do_subregs) 4015 reg_max_ref_mode = XCNEWVEC (machine_mode, max_regno); 4016 else 4017 reg_max_ref_mode = NULL; 4018 4019 num_eliminable_invariants = 0; 4020 4021 first_label_num = get_first_label_num (); 4022 num_labels = max_label_num () - first_label_num; 4023 4024 /* Allocate the tables used to store offset information at labels. */ 4025 offsets_known_at = XNEWVEC (char, num_labels); 4026 offsets_at = (poly_int64_pod (*)[NUM_ELIMINABLE_REGS]) 4027 xmalloc (num_labels * NUM_ELIMINABLE_REGS * sizeof (poly_int64)); 4028 4029 /* Look for REG_EQUIV notes; record what each pseudo is equivalent 4030 to. If DO_SUBREGS is true, also find all paradoxical subregs and 4031 find largest such for each pseudo. FIRST is the head of the insn 4032 list. */ 4033 4034 for (insn = first; insn; insn = NEXT_INSN (insn)) 4035 { 4036 rtx set = single_set (insn); 4037 4038 /* We may introduce USEs that we want to remove at the end, so 4039 we'll mark them with QImode. Make sure there are no 4040 previously-marked insns left by say regmove. */ 4041 if (INSN_P (insn) && GET_CODE (PATTERN (insn)) == USE 4042 && GET_MODE (insn) != VOIDmode) 4043 PUT_MODE (insn, VOIDmode); 4044 4045 if (do_subregs && NONDEBUG_INSN_P (insn)) 4046 scan_paradoxical_subregs (PATTERN (insn)); 4047 4048 if (set != 0 && REG_P (SET_DEST (set))) 4049 { 4050 rtx note = find_reg_note (insn, REG_EQUIV, NULL_RTX); 4051 rtx x; 4052 4053 if (! note) 4054 continue; 4055 4056 i = REGNO (SET_DEST (set)); 4057 x = XEXP (note, 0); 4058 4059 if (i <= LAST_VIRTUAL_REGISTER) 4060 continue; 4061 4062 /* If flag_pic and we have constant, verify it's legitimate. */ 4063 if (!CONSTANT_P (x) 4064 || !flag_pic || LEGITIMATE_PIC_OPERAND_P (x)) 4065 { 4066 /* It can happen that a REG_EQUIV note contains a MEM 4067 that is not a legitimate memory operand. As later 4068 stages of reload assume that all addresses found 4069 in the reg_equiv_* arrays were originally legitimate, 4070 we ignore such REG_EQUIV notes. */ 4071 if (memory_operand (x, VOIDmode)) 4072 { 4073 /* Always unshare the equivalence, so we can 4074 substitute into this insn without touching the 4075 equivalence. */ 4076 reg_equiv_memory_loc (i) = copy_rtx (x); 4077 } 4078 else if (function_invariant_p (x)) 4079 { 4080 machine_mode mode; 4081 4082 mode = GET_MODE (SET_DEST (set)); 4083 if (GET_CODE (x) == PLUS) 4084 { 4085 /* This is PLUS of frame pointer and a constant, 4086 and might be shared. Unshare it. */ 4087 reg_equiv_invariant (i) = copy_rtx (x); 4088 num_eliminable_invariants++; 4089 } 4090 else if (x == frame_pointer_rtx || x == arg_pointer_rtx) 4091 { 4092 reg_equiv_invariant (i) = x; 4093 num_eliminable_invariants++; 4094 } 4095 else if (targetm.legitimate_constant_p (mode, x)) 4096 reg_equiv_constant (i) = x; 4097 else 4098 { 4099 reg_equiv_memory_loc (i) = force_const_mem (mode, x); 4100 if (! reg_equiv_memory_loc (i)) 4101 reg_equiv_init (i) = NULL; 4102 } 4103 } 4104 else 4105 { 4106 reg_equiv_init (i) = NULL; 4107 continue; 4108 } 4109 } 4110 else 4111 reg_equiv_init (i) = NULL; 4112 } 4113 } 4114 4115 if (dump_file) 4116 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 4117 if (reg_equiv_init (i)) 4118 { 4119 fprintf (dump_file, "init_insns for %u: ", i); 4120 print_inline_rtx (dump_file, reg_equiv_init (i), 20); 4121 fprintf (dump_file, "\n"); 4122 } 4123 } 4124 4125 /* Indicate that we no longer have known memory locations or constants. 4126 Free all data involved in tracking these. */ 4127 4128 static void 4129 free_reg_equiv (void) 4130 { 4131 int i; 4132 4133 free (offsets_known_at); 4134 free (offsets_at); 4135 offsets_at = 0; 4136 offsets_known_at = 0; 4137 4138 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4139 if (reg_equiv_alt_mem_list (i)) 4140 free_EXPR_LIST_list (®_equiv_alt_mem_list (i)); 4141 vec_free (reg_equivs); 4142 } 4143 4144 /* Kick all pseudos out of hard register REGNO. 4145 4146 If CANT_ELIMINATE is nonzero, it means that we are doing this spill 4147 because we found we can't eliminate some register. In the case, no pseudos 4148 are allowed to be in the register, even if they are only in a block that 4149 doesn't require spill registers, unlike the case when we are spilling this 4150 hard reg to produce another spill register. 4151 4152 Return nonzero if any pseudos needed to be kicked out. */ 4153 4154 static void 4155 spill_hard_reg (unsigned int regno, int cant_eliminate) 4156 { 4157 int i; 4158 4159 if (cant_eliminate) 4160 { 4161 SET_HARD_REG_BIT (bad_spill_regs_global, regno); 4162 df_set_regs_ever_live (regno, true); 4163 } 4164 4165 /* Spill every pseudo reg that was allocated to this reg 4166 or to something that overlaps this reg. */ 4167 4168 for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 4169 if (reg_renumber[i] >= 0 4170 && (unsigned int) reg_renumber[i] <= regno 4171 && end_hard_regno (PSEUDO_REGNO_MODE (i), reg_renumber[i]) > regno) 4172 SET_REGNO_REG_SET (&spilled_pseudos, i); 4173 } 4174 4175 /* After spill_hard_reg was called and/or find_reload_regs was run for all 4176 insns that need reloads, this function is used to actually spill pseudo 4177 registers and try to reallocate them. It also sets up the spill_regs 4178 array for use by choose_reload_regs. 4179 4180 GLOBAL nonzero means we should attempt to reallocate any pseudo registers 4181 that we displace from hard registers. */ 4182 4183 static int 4184 finish_spills (int global) 4185 { 4186 class insn_chain *chain; 4187 int something_changed = 0; 4188 unsigned i; 4189 reg_set_iterator rsi; 4190 4191 /* Build the spill_regs array for the function. */ 4192 /* If there are some registers still to eliminate and one of the spill regs 4193 wasn't ever used before, additional stack space may have to be 4194 allocated to store this register. Thus, we may have changed the offset 4195 between the stack and frame pointers, so mark that something has changed. 4196 4197 One might think that we need only set VAL to 1 if this is a call-used 4198 register. However, the set of registers that must be saved by the 4199 prologue is not identical to the call-used set. For example, the 4200 register used by the call insn for the return PC is a call-used register, 4201 but must be saved by the prologue. */ 4202 4203 n_spills = 0; 4204 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4205 if (TEST_HARD_REG_BIT (used_spill_regs, i)) 4206 { 4207 spill_reg_order[i] = n_spills; 4208 spill_regs[n_spills++] = i; 4209 if (num_eliminable && ! df_regs_ever_live_p (i)) 4210 something_changed = 1; 4211 df_set_regs_ever_live (i, true); 4212 } 4213 else 4214 spill_reg_order[i] = -1; 4215 4216 EXECUTE_IF_SET_IN_REG_SET (&spilled_pseudos, FIRST_PSEUDO_REGISTER, i, rsi) 4217 if (reg_renumber[i] >= 0) 4218 { 4219 SET_HARD_REG_BIT (pseudo_previous_regs[i], reg_renumber[i]); 4220 /* Mark it as no longer having a hard register home. */ 4221 reg_renumber[i] = -1; 4222 if (ira_conflicts_p) 4223 /* Inform IRA about the change. */ 4224 ira_mark_allocation_change (i); 4225 /* We will need to scan everything again. */ 4226 something_changed = 1; 4227 } 4228 4229 /* Retry global register allocation if possible. */ 4230 if (global && ira_conflicts_p) 4231 { 4232 unsigned int n; 4233 4234 memset (pseudo_forbidden_regs, 0, max_regno * sizeof (HARD_REG_SET)); 4235 /* For every insn that needs reloads, set the registers used as spill 4236 regs in pseudo_forbidden_regs for every pseudo live across the 4237 insn. */ 4238 for (chain = insns_need_reload; chain; chain = chain->next_need_reload) 4239 { 4240 EXECUTE_IF_SET_IN_REG_SET 4241 (&chain->live_throughout, FIRST_PSEUDO_REGISTER, i, rsi) 4242 { 4243 pseudo_forbidden_regs[i] |= chain->used_spill_regs; 4244 } 4245 EXECUTE_IF_SET_IN_REG_SET 4246 (&chain->dead_or_set, FIRST_PSEUDO_REGISTER, i, rsi) 4247 { 4248 pseudo_forbidden_regs[i] |= chain->used_spill_regs; 4249 } 4250 } 4251 4252 /* Retry allocating the pseudos spilled in IRA and the 4253 reload. For each reg, merge the various reg sets that 4254 indicate which hard regs can't be used, and call 4255 ira_reassign_pseudos. */ 4256 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < (unsigned) max_regno; i++) 4257 if (reg_old_renumber[i] != reg_renumber[i]) 4258 { 4259 if (reg_renumber[i] < 0) 4260 temp_pseudo_reg_arr[n++] = i; 4261 else 4262 CLEAR_REGNO_REG_SET (&spilled_pseudos, i); 4263 } 4264 if (ira_reassign_pseudos (temp_pseudo_reg_arr, n, 4265 bad_spill_regs_global, 4266 pseudo_forbidden_regs, pseudo_previous_regs, 4267 &spilled_pseudos)) 4268 something_changed = 1; 4269 } 4270 /* Fix up the register information in the insn chain. 4271 This involves deleting those of the spilled pseudos which did not get 4272 a new hard register home from the live_{before,after} sets. */ 4273 for (chain = reload_insn_chain; chain; chain = chain->next) 4274 { 4275 HARD_REG_SET used_by_pseudos; 4276 HARD_REG_SET used_by_pseudos2; 4277 4278 if (! ira_conflicts_p) 4279 { 4280 /* Don't do it for IRA because IRA and the reload still can 4281 assign hard registers to the spilled pseudos on next 4282 reload iterations. */ 4283 AND_COMPL_REG_SET (&chain->live_throughout, &spilled_pseudos); 4284 AND_COMPL_REG_SET (&chain->dead_or_set, &spilled_pseudos); 4285 } 4286 /* Mark any unallocated hard regs as available for spills. That 4287 makes inheritance work somewhat better. */ 4288 if (chain->need_reload) 4289 { 4290 REG_SET_TO_HARD_REG_SET (used_by_pseudos, &chain->live_throughout); 4291 REG_SET_TO_HARD_REG_SET (used_by_pseudos2, &chain->dead_or_set); 4292 used_by_pseudos |= used_by_pseudos2; 4293 4294 compute_use_by_pseudos (&used_by_pseudos, &chain->live_throughout); 4295 compute_use_by_pseudos (&used_by_pseudos, &chain->dead_or_set); 4296 /* Value of chain->used_spill_regs from previous iteration 4297 may be not included in the value calculated here because 4298 of possible removing caller-saves insns (see function 4299 delete_caller_save_insns. */ 4300 chain->used_spill_regs = ~used_by_pseudos & used_spill_regs; 4301 } 4302 } 4303 4304 CLEAR_REG_SET (&changed_allocation_pseudos); 4305 /* Let alter_reg modify the reg rtx's for the modified pseudos. */ 4306 for (i = FIRST_PSEUDO_REGISTER; i < (unsigned)max_regno; i++) 4307 { 4308 int regno = reg_renumber[i]; 4309 if (reg_old_renumber[i] == regno) 4310 continue; 4311 4312 SET_REGNO_REG_SET (&changed_allocation_pseudos, i); 4313 4314 alter_reg (i, reg_old_renumber[i], false); 4315 reg_old_renumber[i] = regno; 4316 if (dump_file) 4317 { 4318 if (regno == -1) 4319 fprintf (dump_file, " Register %d now on stack.\n\n", i); 4320 else 4321 fprintf (dump_file, " Register %d now in %d.\n\n", 4322 i, reg_renumber[i]); 4323 } 4324 } 4325 4326 return something_changed; 4327 } 4328 4329 /* Find all paradoxical subregs within X and update reg_max_ref_mode. */ 4330 4331 static void 4332 scan_paradoxical_subregs (rtx x) 4333 { 4334 int i; 4335 const char *fmt; 4336 enum rtx_code code = GET_CODE (x); 4337 4338 switch (code) 4339 { 4340 case REG: 4341 case CONST: 4342 case SYMBOL_REF: 4343 case LABEL_REF: 4344 CASE_CONST_ANY: 4345 case CC0: 4346 case PC: 4347 case USE: 4348 case CLOBBER: 4349 return; 4350 4351 case SUBREG: 4352 if (REG_P (SUBREG_REG (x))) 4353 { 4354 unsigned int regno = REGNO (SUBREG_REG (x)); 4355 if (partial_subreg_p (reg_max_ref_mode[regno], GET_MODE (x))) 4356 { 4357 reg_max_ref_mode[regno] = GET_MODE (x); 4358 mark_home_live_1 (regno, GET_MODE (x)); 4359 } 4360 } 4361 return; 4362 4363 default: 4364 break; 4365 } 4366 4367 fmt = GET_RTX_FORMAT (code); 4368 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4369 { 4370 if (fmt[i] == 'e') 4371 scan_paradoxical_subregs (XEXP (x, i)); 4372 else if (fmt[i] == 'E') 4373 { 4374 int j; 4375 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 4376 scan_paradoxical_subregs (XVECEXP (x, i, j)); 4377 } 4378 } 4379 } 4380 4381 /* *OP_PTR and *OTHER_PTR are two operands to a conceptual reload. 4382 If *OP_PTR is a paradoxical subreg, try to remove that subreg 4383 and apply the corresponding narrowing subreg to *OTHER_PTR. 4384 Return true if the operands were changed, false otherwise. */ 4385 4386 static bool 4387 strip_paradoxical_subreg (rtx *op_ptr, rtx *other_ptr) 4388 { 4389 rtx op, inner, other, tem; 4390 4391 op = *op_ptr; 4392 if (!paradoxical_subreg_p (op)) 4393 return false; 4394 inner = SUBREG_REG (op); 4395 4396 other = *other_ptr; 4397 tem = gen_lowpart_common (GET_MODE (inner), other); 4398 if (!tem) 4399 return false; 4400 4401 /* If the lowpart operation turned a hard register into a subreg, 4402 rather than simplifying it to another hard register, then the 4403 mode change cannot be properly represented. For example, OTHER 4404 might be valid in its current mode, but not in the new one. */ 4405 if (GET_CODE (tem) == SUBREG 4406 && REG_P (other) 4407 && HARD_REGISTER_P (other)) 4408 return false; 4409 4410 *op_ptr = inner; 4411 *other_ptr = tem; 4412 return true; 4413 } 4414 4415 /* A subroutine of reload_as_needed. If INSN has a REG_EH_REGION note, 4416 examine all of the reload insns between PREV and NEXT exclusive, and 4417 annotate all that may trap. */ 4418 4419 static void 4420 fixup_eh_region_note (rtx_insn *insn, rtx_insn *prev, rtx_insn *next) 4421 { 4422 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); 4423 if (note == NULL) 4424 return; 4425 if (!insn_could_throw_p (insn)) 4426 remove_note (insn, note); 4427 copy_reg_eh_region_note_forward (note, NEXT_INSN (prev), next); 4428 } 4429 4430 /* Reload pseudo-registers into hard regs around each insn as needed. 4431 Additional register load insns are output before the insn that needs it 4432 and perhaps store insns after insns that modify the reloaded pseudo reg. 4433 4434 reg_last_reload_reg and reg_reloaded_contents keep track of 4435 which registers are already available in reload registers. 4436 We update these for the reloads that we perform, 4437 as the insns are scanned. */ 4438 4439 static void 4440 reload_as_needed (int live_known) 4441 { 4442 class insn_chain *chain; 4443 #if AUTO_INC_DEC 4444 int i; 4445 #endif 4446 rtx_note *marker; 4447 4448 memset (spill_reg_rtx, 0, sizeof spill_reg_rtx); 4449 memset (spill_reg_store, 0, sizeof spill_reg_store); 4450 reg_last_reload_reg = XCNEWVEC (rtx, max_regno); 4451 INIT_REG_SET (®_has_output_reload); 4452 CLEAR_HARD_REG_SET (reg_reloaded_valid); 4453 4454 set_initial_elim_offsets (); 4455 4456 /* Generate a marker insn that we will move around. */ 4457 marker = emit_note (NOTE_INSN_DELETED); 4458 unlink_insn_chain (marker, marker); 4459 4460 for (chain = reload_insn_chain; chain; chain = chain->next) 4461 { 4462 rtx_insn *prev = 0; 4463 rtx_insn *insn = chain->insn; 4464 rtx_insn *old_next = NEXT_INSN (insn); 4465 #if AUTO_INC_DEC 4466 rtx_insn *old_prev = PREV_INSN (insn); 4467 #endif 4468 4469 if (will_delete_init_insn_p (insn)) 4470 continue; 4471 4472 /* If we pass a label, copy the offsets from the label information 4473 into the current offsets of each elimination. */ 4474 if (LABEL_P (insn)) 4475 set_offsets_for_label (insn); 4476 4477 else if (INSN_P (insn)) 4478 { 4479 regset_head regs_to_forget; 4480 INIT_REG_SET (®s_to_forget); 4481 note_stores (insn, forget_old_reloads_1, ®s_to_forget); 4482 4483 /* If this is a USE and CLOBBER of a MEM, ensure that any 4484 references to eliminable registers have been removed. */ 4485 4486 if ((GET_CODE (PATTERN (insn)) == USE 4487 || GET_CODE (PATTERN (insn)) == CLOBBER) 4488 && MEM_P (XEXP (PATTERN (insn), 0))) 4489 XEXP (XEXP (PATTERN (insn), 0), 0) 4490 = eliminate_regs (XEXP (XEXP (PATTERN (insn), 0), 0), 4491 GET_MODE (XEXP (PATTERN (insn), 0)), 4492 NULL_RTX); 4493 4494 /* If we need to do register elimination processing, do so. 4495 This might delete the insn, in which case we are done. */ 4496 if ((num_eliminable || num_eliminable_invariants) && chain->need_elim) 4497 { 4498 eliminate_regs_in_insn (insn, 1); 4499 if (NOTE_P (insn)) 4500 { 4501 update_eliminable_offsets (); 4502 CLEAR_REG_SET (®s_to_forget); 4503 continue; 4504 } 4505 } 4506 4507 /* If need_elim is nonzero but need_reload is zero, one might think 4508 that we could simply set n_reloads to 0. However, find_reloads 4509 could have done some manipulation of the insn (such as swapping 4510 commutative operands), and these manipulations are lost during 4511 the first pass for every insn that needs register elimination. 4512 So the actions of find_reloads must be redone here. */ 4513 4514 if (! chain->need_elim && ! chain->need_reload 4515 && ! chain->need_operand_change) 4516 n_reloads = 0; 4517 /* First find the pseudo regs that must be reloaded for this insn. 4518 This info is returned in the tables reload_... (see reload.h). 4519 Also modify the body of INSN by substituting RELOAD 4520 rtx's for those pseudo regs. */ 4521 else 4522 { 4523 CLEAR_REG_SET (®_has_output_reload); 4524 CLEAR_HARD_REG_SET (reg_is_output_reload); 4525 4526 find_reloads (insn, 1, spill_indirect_levels, live_known, 4527 spill_reg_order); 4528 } 4529 4530 if (n_reloads > 0) 4531 { 4532 rtx_insn *next = NEXT_INSN (insn); 4533 4534 /* ??? PREV can get deleted by reload inheritance. 4535 Work around this by emitting a marker note. */ 4536 prev = PREV_INSN (insn); 4537 reorder_insns_nobb (marker, marker, prev); 4538 4539 /* Now compute which reload regs to reload them into. Perhaps 4540 reusing reload regs from previous insns, or else output 4541 load insns to reload them. Maybe output store insns too. 4542 Record the choices of reload reg in reload_reg_rtx. */ 4543 choose_reload_regs (chain); 4544 4545 /* Generate the insns to reload operands into or out of 4546 their reload regs. */ 4547 emit_reload_insns (chain); 4548 4549 /* Substitute the chosen reload regs from reload_reg_rtx 4550 into the insn's body (or perhaps into the bodies of other 4551 load and store insn that we just made for reloading 4552 and that we moved the structure into). */ 4553 subst_reloads (insn); 4554 4555 prev = PREV_INSN (marker); 4556 unlink_insn_chain (marker, marker); 4557 4558 /* Adjust the exception region notes for loads and stores. */ 4559 if (cfun->can_throw_non_call_exceptions && !CALL_P (insn)) 4560 fixup_eh_region_note (insn, prev, next); 4561 4562 /* Adjust the location of REG_ARGS_SIZE. */ 4563 rtx p = find_reg_note (insn, REG_ARGS_SIZE, NULL_RTX); 4564 if (p) 4565 { 4566 remove_note (insn, p); 4567 fixup_args_size_notes (prev, PREV_INSN (next), 4568 get_args_size (p)); 4569 } 4570 4571 /* If this was an ASM, make sure that all the reload insns 4572 we have generated are valid. If not, give an error 4573 and delete them. */ 4574 if (asm_noperands (PATTERN (insn)) >= 0) 4575 for (rtx_insn *p = NEXT_INSN (prev); 4576 p != next; 4577 p = NEXT_INSN (p)) 4578 if (p != insn && INSN_P (p) 4579 && GET_CODE (PATTERN (p)) != USE 4580 && (recog_memoized (p) < 0 4581 || (extract_insn (p), 4582 !(constrain_operands (1, 4583 get_enabled_alternatives (p)))))) 4584 { 4585 error_for_asm (insn, 4586 "%<asm%> operand requires " 4587 "impossible reload"); 4588 delete_insn (p); 4589 } 4590 } 4591 4592 if (num_eliminable && chain->need_elim) 4593 update_eliminable_offsets (); 4594 4595 /* Any previously reloaded spilled pseudo reg, stored in this insn, 4596 is no longer validly lying around to save a future reload. 4597 Note that this does not detect pseudos that were reloaded 4598 for this insn in order to be stored in 4599 (obeying register constraints). That is correct; such reload 4600 registers ARE still valid. */ 4601 forget_marked_reloads (®s_to_forget); 4602 CLEAR_REG_SET (®s_to_forget); 4603 4604 /* There may have been CLOBBER insns placed after INSN. So scan 4605 between INSN and NEXT and use them to forget old reloads. */ 4606 for (rtx_insn *x = NEXT_INSN (insn); x != old_next; x = NEXT_INSN (x)) 4607 if (NONJUMP_INSN_P (x) && GET_CODE (PATTERN (x)) == CLOBBER) 4608 note_stores (x, forget_old_reloads_1, NULL); 4609 4610 #if AUTO_INC_DEC 4611 /* Likewise for regs altered by auto-increment in this insn. 4612 REG_INC notes have been changed by reloading: 4613 find_reloads_address_1 records substitutions for them, 4614 which have been performed by subst_reloads above. */ 4615 for (i = n_reloads - 1; i >= 0; i--) 4616 { 4617 rtx in_reg = rld[i].in_reg; 4618 if (in_reg) 4619 { 4620 enum rtx_code code = GET_CODE (in_reg); 4621 /* PRE_INC / PRE_DEC will have the reload register ending up 4622 with the same value as the stack slot, but that doesn't 4623 hold true for POST_INC / POST_DEC. Either we have to 4624 convert the memory access to a true POST_INC / POST_DEC, 4625 or we can't use the reload register for inheritance. */ 4626 if ((code == POST_INC || code == POST_DEC) 4627 && TEST_HARD_REG_BIT (reg_reloaded_valid, 4628 REGNO (rld[i].reg_rtx)) 4629 /* Make sure it is the inc/dec pseudo, and not 4630 some other (e.g. output operand) pseudo. */ 4631 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] 4632 == REGNO (XEXP (in_reg, 0)))) 4633 4634 { 4635 rtx reload_reg = rld[i].reg_rtx; 4636 machine_mode mode = GET_MODE (reload_reg); 4637 int n = 0; 4638 rtx_insn *p; 4639 4640 for (p = PREV_INSN (old_next); p != prev; p = PREV_INSN (p)) 4641 { 4642 /* We really want to ignore REG_INC notes here, so 4643 use PATTERN (p) as argument to reg_set_p . */ 4644 if (reg_set_p (reload_reg, PATTERN (p))) 4645 break; 4646 n = count_occurrences (PATTERN (p), reload_reg, 0); 4647 if (! n) 4648 continue; 4649 if (n == 1) 4650 { 4651 rtx replace_reg 4652 = gen_rtx_fmt_e (code, mode, reload_reg); 4653 4654 validate_replace_rtx_group (reload_reg, 4655 replace_reg, p); 4656 n = verify_changes (0); 4657 4658 /* We must also verify that the constraints 4659 are met after the replacement. Make sure 4660 extract_insn is only called for an insn 4661 where the replacements were found to be 4662 valid so far. */ 4663 if (n) 4664 { 4665 extract_insn (p); 4666 n = constrain_operands (1, 4667 get_enabled_alternatives (p)); 4668 } 4669 4670 /* If the constraints were not met, then 4671 undo the replacement, else confirm it. */ 4672 if (!n) 4673 cancel_changes (0); 4674 else 4675 confirm_change_group (); 4676 } 4677 break; 4678 } 4679 if (n == 1) 4680 { 4681 add_reg_note (p, REG_INC, reload_reg); 4682 /* Mark this as having an output reload so that the 4683 REG_INC processing code below won't invalidate 4684 the reload for inheritance. */ 4685 SET_HARD_REG_BIT (reg_is_output_reload, 4686 REGNO (reload_reg)); 4687 SET_REGNO_REG_SET (®_has_output_reload, 4688 REGNO (XEXP (in_reg, 0))); 4689 } 4690 else 4691 forget_old_reloads_1 (XEXP (in_reg, 0), NULL_RTX, 4692 NULL); 4693 } 4694 else if ((code == PRE_INC || code == PRE_DEC) 4695 && TEST_HARD_REG_BIT (reg_reloaded_valid, 4696 REGNO (rld[i].reg_rtx)) 4697 /* Make sure it is the inc/dec pseudo, and not 4698 some other (e.g. output operand) pseudo. */ 4699 && ((unsigned) reg_reloaded_contents[REGNO (rld[i].reg_rtx)] 4700 == REGNO (XEXP (in_reg, 0)))) 4701 { 4702 SET_HARD_REG_BIT (reg_is_output_reload, 4703 REGNO (rld[i].reg_rtx)); 4704 SET_REGNO_REG_SET (®_has_output_reload, 4705 REGNO (XEXP (in_reg, 0))); 4706 } 4707 else if (code == PRE_INC || code == PRE_DEC 4708 || code == POST_INC || code == POST_DEC) 4709 { 4710 int in_regno = REGNO (XEXP (in_reg, 0)); 4711 4712 if (reg_last_reload_reg[in_regno] != NULL_RTX) 4713 { 4714 int in_hard_regno; 4715 bool forget_p = true; 4716 4717 in_hard_regno = REGNO (reg_last_reload_reg[in_regno]); 4718 if (TEST_HARD_REG_BIT (reg_reloaded_valid, 4719 in_hard_regno)) 4720 { 4721 for (rtx_insn *x = (old_prev ? 4722 NEXT_INSN (old_prev) : insn); 4723 x != old_next; 4724 x = NEXT_INSN (x)) 4725 if (x == reg_reloaded_insn[in_hard_regno]) 4726 { 4727 forget_p = false; 4728 break; 4729 } 4730 } 4731 /* If for some reasons, we didn't set up 4732 reg_last_reload_reg in this insn, 4733 invalidate inheritance from previous 4734 insns for the incremented/decremented 4735 register. Such registers will be not in 4736 reg_has_output_reload. Invalidate it 4737 also if the corresponding element in 4738 reg_reloaded_insn is also 4739 invalidated. */ 4740 if (forget_p) 4741 forget_old_reloads_1 (XEXP (in_reg, 0), 4742 NULL_RTX, NULL); 4743 } 4744 } 4745 } 4746 } 4747 /* If a pseudo that got a hard register is auto-incremented, 4748 we must purge records of copying it into pseudos without 4749 hard registers. */ 4750 for (rtx x = REG_NOTES (insn); x; x = XEXP (x, 1)) 4751 if (REG_NOTE_KIND (x) == REG_INC) 4752 { 4753 /* See if this pseudo reg was reloaded in this insn. 4754 If so, its last-reload info is still valid 4755 because it is based on this insn's reload. */ 4756 for (i = 0; i < n_reloads; i++) 4757 if (rld[i].out == XEXP (x, 0)) 4758 break; 4759 4760 if (i == n_reloads) 4761 forget_old_reloads_1 (XEXP (x, 0), NULL_RTX, NULL); 4762 } 4763 #endif 4764 } 4765 /* A reload reg's contents are unknown after a label. */ 4766 if (LABEL_P (insn)) 4767 CLEAR_HARD_REG_SET (reg_reloaded_valid); 4768 4769 /* Don't assume a reload reg is still good after a call insn 4770 if it is a call-used reg, or if it contains a value that will 4771 be partially clobbered by the call. */ 4772 else if (CALL_P (insn)) 4773 { 4774 reg_reloaded_valid 4775 &= ~insn_callee_abi (insn).full_and_partial_reg_clobbers (); 4776 4777 /* If this is a call to a setjmp-type function, we must not 4778 reuse any reload reg contents across the call; that will 4779 just be clobbered by other uses of the register in later 4780 code, before the longjmp. */ 4781 if (find_reg_note (insn, REG_SETJMP, NULL_RTX)) 4782 CLEAR_HARD_REG_SET (reg_reloaded_valid); 4783 } 4784 } 4785 4786 /* Clean up. */ 4787 free (reg_last_reload_reg); 4788 CLEAR_REG_SET (®_has_output_reload); 4789 } 4790 4791 /* Discard all record of any value reloaded from X, 4792 or reloaded in X from someplace else; 4793 unless X is an output reload reg of the current insn. 4794 4795 X may be a hard reg (the reload reg) 4796 or it may be a pseudo reg that was reloaded from. 4797 4798 When DATA is non-NULL just mark the registers in regset 4799 to be forgotten later. */ 4800 4801 static void 4802 forget_old_reloads_1 (rtx x, const_rtx, void *data) 4803 { 4804 unsigned int regno; 4805 unsigned int nr; 4806 regset regs = (regset) data; 4807 4808 /* note_stores does give us subregs of hard regs, 4809 subreg_regno_offset requires a hard reg. */ 4810 while (GET_CODE (x) == SUBREG) 4811 { 4812 /* We ignore the subreg offset when calculating the regno, 4813 because we are using the entire underlying hard register 4814 below. */ 4815 x = SUBREG_REG (x); 4816 } 4817 4818 if (!REG_P (x)) 4819 return; 4820 4821 regno = REGNO (x); 4822 4823 if (regno >= FIRST_PSEUDO_REGISTER) 4824 nr = 1; 4825 else 4826 { 4827 unsigned int i; 4828 4829 nr = REG_NREGS (x); 4830 /* Storing into a spilled-reg invalidates its contents. 4831 This can happen if a block-local pseudo is allocated to that reg 4832 and it wasn't spilled because this block's total need is 0. 4833 Then some insn might have an optional reload and use this reg. */ 4834 if (!regs) 4835 for (i = 0; i < nr; i++) 4836 /* But don't do this if the reg actually serves as an output 4837 reload reg in the current instruction. */ 4838 if (n_reloads == 0 4839 || ! TEST_HARD_REG_BIT (reg_is_output_reload, regno + i)) 4840 { 4841 CLEAR_HARD_REG_BIT (reg_reloaded_valid, regno + i); 4842 spill_reg_store[regno + i] = 0; 4843 } 4844 } 4845 4846 if (regs) 4847 while (nr-- > 0) 4848 SET_REGNO_REG_SET (regs, regno + nr); 4849 else 4850 { 4851 /* Since value of X has changed, 4852 forget any value previously copied from it. */ 4853 4854 while (nr-- > 0) 4855 /* But don't forget a copy if this is the output reload 4856 that establishes the copy's validity. */ 4857 if (n_reloads == 0 4858 || !REGNO_REG_SET_P (®_has_output_reload, regno + nr)) 4859 reg_last_reload_reg[regno + nr] = 0; 4860 } 4861 } 4862 4863 /* Forget the reloads marked in regset by previous function. */ 4864 static void 4865 forget_marked_reloads (regset regs) 4866 { 4867 unsigned int reg; 4868 reg_set_iterator rsi; 4869 EXECUTE_IF_SET_IN_REG_SET (regs, 0, reg, rsi) 4870 { 4871 if (reg < FIRST_PSEUDO_REGISTER 4872 /* But don't do this if the reg actually serves as an output 4873 reload reg in the current instruction. */ 4874 && (n_reloads == 0 4875 || ! TEST_HARD_REG_BIT (reg_is_output_reload, reg))) 4876 { 4877 CLEAR_HARD_REG_BIT (reg_reloaded_valid, reg); 4878 spill_reg_store[reg] = 0; 4879 } 4880 if (n_reloads == 0 4881 || !REGNO_REG_SET_P (®_has_output_reload, reg)) 4882 reg_last_reload_reg[reg] = 0; 4883 } 4884 } 4885 4886 /* The following HARD_REG_SETs indicate when each hard register is 4887 used for a reload of various parts of the current insn. */ 4888 4889 /* If reg is unavailable for all reloads. */ 4890 static HARD_REG_SET reload_reg_unavailable; 4891 /* If reg is in use as a reload reg for a RELOAD_OTHER reload. */ 4892 static HARD_REG_SET reload_reg_used; 4893 /* If reg is in use for a RELOAD_FOR_INPUT_ADDRESS reload for operand I. */ 4894 static HARD_REG_SET reload_reg_used_in_input_addr[MAX_RECOG_OPERANDS]; 4895 /* If reg is in use for a RELOAD_FOR_INPADDR_ADDRESS reload for operand I. */ 4896 static HARD_REG_SET reload_reg_used_in_inpaddr_addr[MAX_RECOG_OPERANDS]; 4897 /* If reg is in use for a RELOAD_FOR_OUTPUT_ADDRESS reload for operand I. */ 4898 static HARD_REG_SET reload_reg_used_in_output_addr[MAX_RECOG_OPERANDS]; 4899 /* If reg is in use for a RELOAD_FOR_OUTADDR_ADDRESS reload for operand I. */ 4900 static HARD_REG_SET reload_reg_used_in_outaddr_addr[MAX_RECOG_OPERANDS]; 4901 /* If reg is in use for a RELOAD_FOR_INPUT reload for operand I. */ 4902 static HARD_REG_SET reload_reg_used_in_input[MAX_RECOG_OPERANDS]; 4903 /* If reg is in use for a RELOAD_FOR_OUTPUT reload for operand I. */ 4904 static HARD_REG_SET reload_reg_used_in_output[MAX_RECOG_OPERANDS]; 4905 /* If reg is in use for a RELOAD_FOR_OPERAND_ADDRESS reload. */ 4906 static HARD_REG_SET reload_reg_used_in_op_addr; 4907 /* If reg is in use for a RELOAD_FOR_OPADDR_ADDR reload. */ 4908 static HARD_REG_SET reload_reg_used_in_op_addr_reload; 4909 /* If reg is in use for a RELOAD_FOR_INSN reload. */ 4910 static HARD_REG_SET reload_reg_used_in_insn; 4911 /* If reg is in use for a RELOAD_FOR_OTHER_ADDRESS reload. */ 4912 static HARD_REG_SET reload_reg_used_in_other_addr; 4913 4914 /* If reg is in use as a reload reg for any sort of reload. */ 4915 static HARD_REG_SET reload_reg_used_at_all; 4916 4917 /* If reg is use as an inherited reload. We just mark the first register 4918 in the group. */ 4919 static HARD_REG_SET reload_reg_used_for_inherit; 4920 4921 /* Records which hard regs are used in any way, either as explicit use or 4922 by being allocated to a pseudo during any point of the current insn. */ 4923 static HARD_REG_SET reg_used_in_insn; 4924 4925 /* Mark reg REGNO as in use for a reload of the sort spec'd by OPNUM and 4926 TYPE. MODE is used to indicate how many consecutive regs are 4927 actually used. */ 4928 4929 static void 4930 mark_reload_reg_in_use (unsigned int regno, int opnum, enum reload_type type, 4931 machine_mode mode) 4932 { 4933 switch (type) 4934 { 4935 case RELOAD_OTHER: 4936 add_to_hard_reg_set (&reload_reg_used, mode, regno); 4937 break; 4938 4939 case RELOAD_FOR_INPUT_ADDRESS: 4940 add_to_hard_reg_set (&reload_reg_used_in_input_addr[opnum], mode, regno); 4941 break; 4942 4943 case RELOAD_FOR_INPADDR_ADDRESS: 4944 add_to_hard_reg_set (&reload_reg_used_in_inpaddr_addr[opnum], mode, regno); 4945 break; 4946 4947 case RELOAD_FOR_OUTPUT_ADDRESS: 4948 add_to_hard_reg_set (&reload_reg_used_in_output_addr[opnum], mode, regno); 4949 break; 4950 4951 case RELOAD_FOR_OUTADDR_ADDRESS: 4952 add_to_hard_reg_set (&reload_reg_used_in_outaddr_addr[opnum], mode, regno); 4953 break; 4954 4955 case RELOAD_FOR_OPERAND_ADDRESS: 4956 add_to_hard_reg_set (&reload_reg_used_in_op_addr, mode, regno); 4957 break; 4958 4959 case RELOAD_FOR_OPADDR_ADDR: 4960 add_to_hard_reg_set (&reload_reg_used_in_op_addr_reload, mode, regno); 4961 break; 4962 4963 case RELOAD_FOR_OTHER_ADDRESS: 4964 add_to_hard_reg_set (&reload_reg_used_in_other_addr, mode, regno); 4965 break; 4966 4967 case RELOAD_FOR_INPUT: 4968 add_to_hard_reg_set (&reload_reg_used_in_input[opnum], mode, regno); 4969 break; 4970 4971 case RELOAD_FOR_OUTPUT: 4972 add_to_hard_reg_set (&reload_reg_used_in_output[opnum], mode, regno); 4973 break; 4974 4975 case RELOAD_FOR_INSN: 4976 add_to_hard_reg_set (&reload_reg_used_in_insn, mode, regno); 4977 break; 4978 } 4979 4980 add_to_hard_reg_set (&reload_reg_used_at_all, mode, regno); 4981 } 4982 4983 /* Similarly, but show REGNO is no longer in use for a reload. */ 4984 4985 static void 4986 clear_reload_reg_in_use (unsigned int regno, int opnum, 4987 enum reload_type type, machine_mode mode) 4988 { 4989 unsigned int nregs = hard_regno_nregs (regno, mode); 4990 unsigned int start_regno, end_regno, r; 4991 int i; 4992 /* A complication is that for some reload types, inheritance might 4993 allow multiple reloads of the same types to share a reload register. 4994 We set check_opnum if we have to check only reloads with the same 4995 operand number, and check_any if we have to check all reloads. */ 4996 int check_opnum = 0; 4997 int check_any = 0; 4998 HARD_REG_SET *used_in_set; 4999 5000 switch (type) 5001 { 5002 case RELOAD_OTHER: 5003 used_in_set = &reload_reg_used; 5004 break; 5005 5006 case RELOAD_FOR_INPUT_ADDRESS: 5007 used_in_set = &reload_reg_used_in_input_addr[opnum]; 5008 break; 5009 5010 case RELOAD_FOR_INPADDR_ADDRESS: 5011 check_opnum = 1; 5012 used_in_set = &reload_reg_used_in_inpaddr_addr[opnum]; 5013 break; 5014 5015 case RELOAD_FOR_OUTPUT_ADDRESS: 5016 used_in_set = &reload_reg_used_in_output_addr[opnum]; 5017 break; 5018 5019 case RELOAD_FOR_OUTADDR_ADDRESS: 5020 check_opnum = 1; 5021 used_in_set = &reload_reg_used_in_outaddr_addr[opnum]; 5022 break; 5023 5024 case RELOAD_FOR_OPERAND_ADDRESS: 5025 used_in_set = &reload_reg_used_in_op_addr; 5026 break; 5027 5028 case RELOAD_FOR_OPADDR_ADDR: 5029 check_any = 1; 5030 used_in_set = &reload_reg_used_in_op_addr_reload; 5031 break; 5032 5033 case RELOAD_FOR_OTHER_ADDRESS: 5034 used_in_set = &reload_reg_used_in_other_addr; 5035 check_any = 1; 5036 break; 5037 5038 case RELOAD_FOR_INPUT: 5039 used_in_set = &reload_reg_used_in_input[opnum]; 5040 break; 5041 5042 case RELOAD_FOR_OUTPUT: 5043 used_in_set = &reload_reg_used_in_output[opnum]; 5044 break; 5045 5046 case RELOAD_FOR_INSN: 5047 used_in_set = &reload_reg_used_in_insn; 5048 break; 5049 default: 5050 gcc_unreachable (); 5051 } 5052 /* We resolve conflicts with remaining reloads of the same type by 5053 excluding the intervals of reload registers by them from the 5054 interval of freed reload registers. Since we only keep track of 5055 one set of interval bounds, we might have to exclude somewhat 5056 more than what would be necessary if we used a HARD_REG_SET here. 5057 But this should only happen very infrequently, so there should 5058 be no reason to worry about it. */ 5059 5060 start_regno = regno; 5061 end_regno = regno + nregs; 5062 if (check_opnum || check_any) 5063 { 5064 for (i = n_reloads - 1; i >= 0; i--) 5065 { 5066 if (rld[i].when_needed == type 5067 && (check_any || rld[i].opnum == opnum) 5068 && rld[i].reg_rtx) 5069 { 5070 unsigned int conflict_start = true_regnum (rld[i].reg_rtx); 5071 unsigned int conflict_end 5072 = end_hard_regno (rld[i].mode, conflict_start); 5073 5074 /* If there is an overlap with the first to-be-freed register, 5075 adjust the interval start. */ 5076 if (conflict_start <= start_regno && conflict_end > start_regno) 5077 start_regno = conflict_end; 5078 /* Otherwise, if there is a conflict with one of the other 5079 to-be-freed registers, adjust the interval end. */ 5080 if (conflict_start > start_regno && conflict_start < end_regno) 5081 end_regno = conflict_start; 5082 } 5083 } 5084 } 5085 5086 for (r = start_regno; r < end_regno; r++) 5087 CLEAR_HARD_REG_BIT (*used_in_set, r); 5088 } 5089 5090 /* 1 if reg REGNO is free as a reload reg for a reload of the sort 5091 specified by OPNUM and TYPE. */ 5092 5093 static int 5094 reload_reg_free_p (unsigned int regno, int opnum, enum reload_type type) 5095 { 5096 int i; 5097 5098 /* In use for a RELOAD_OTHER means it's not available for anything. */ 5099 if (TEST_HARD_REG_BIT (reload_reg_used, regno) 5100 || TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) 5101 return 0; 5102 5103 switch (type) 5104 { 5105 case RELOAD_OTHER: 5106 /* In use for anything means we can't use it for RELOAD_OTHER. */ 5107 if (TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno) 5108 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 5109 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) 5110 || TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 5111 return 0; 5112 5113 for (i = 0; i < reload_n_operands; i++) 5114 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 5115 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 5116 || TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5117 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 5118 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 5119 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5120 return 0; 5121 5122 return 1; 5123 5124 case RELOAD_FOR_INPUT: 5125 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 5126 || TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)) 5127 return 0; 5128 5129 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 5130 return 0; 5131 5132 /* If it is used for some other input, can't use it. */ 5133 for (i = 0; i < reload_n_operands; i++) 5134 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 5135 return 0; 5136 5137 /* If it is used in a later operand's address, can't use it. */ 5138 for (i = opnum + 1; i < reload_n_operands; i++) 5139 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 5140 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 5141 return 0; 5142 5143 return 1; 5144 5145 case RELOAD_FOR_INPUT_ADDRESS: 5146 /* Can't use a register if it is used for an input address for this 5147 operand or used as an input in an earlier one. */ 5148 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno) 5149 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 5150 return 0; 5151 5152 for (i = 0; i < opnum; i++) 5153 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 5154 return 0; 5155 5156 return 1; 5157 5158 case RELOAD_FOR_INPADDR_ADDRESS: 5159 /* Can't use a register if it is used for an input address 5160 for this operand or used as an input in an earlier 5161 one. */ 5162 if (TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[opnum], regno)) 5163 return 0; 5164 5165 for (i = 0; i < opnum; i++) 5166 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 5167 return 0; 5168 5169 return 1; 5170 5171 case RELOAD_FOR_OUTPUT_ADDRESS: 5172 /* Can't use a register if it is used for an output address for this 5173 operand or used as an output in this or a later operand. Note 5174 that multiple output operands are emitted in reverse order, so 5175 the conflicting ones are those with lower indices. */ 5176 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[opnum], regno)) 5177 return 0; 5178 5179 for (i = 0; i <= opnum; i++) 5180 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5181 return 0; 5182 5183 return 1; 5184 5185 case RELOAD_FOR_OUTADDR_ADDRESS: 5186 /* Can't use a register if it is used for an output address 5187 for this operand or used as an output in this or a 5188 later operand. Note that multiple output operands are 5189 emitted in reverse order, so the conflicting ones are 5190 those with lower indices. */ 5191 if (TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) 5192 return 0; 5193 5194 for (i = 0; i <= opnum; i++) 5195 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5196 return 0; 5197 5198 return 1; 5199 5200 case RELOAD_FOR_OPERAND_ADDRESS: 5201 for (i = 0; i < reload_n_operands; i++) 5202 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 5203 return 0; 5204 5205 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 5206 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 5207 5208 case RELOAD_FOR_OPADDR_ADDR: 5209 for (i = 0; i < reload_n_operands; i++) 5210 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 5211 return 0; 5212 5213 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)); 5214 5215 case RELOAD_FOR_OUTPUT: 5216 /* This cannot share a register with RELOAD_FOR_INSN reloads, other 5217 outputs, or an operand address for this or an earlier output. 5218 Note that multiple output operands are emitted in reverse order, 5219 so the conflicting ones are those with higher indices. */ 5220 if (TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno)) 5221 return 0; 5222 5223 for (i = 0; i < reload_n_operands; i++) 5224 if (TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5225 return 0; 5226 5227 for (i = opnum; i < reload_n_operands; i++) 5228 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5229 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 5230 return 0; 5231 5232 return 1; 5233 5234 case RELOAD_FOR_INSN: 5235 for (i = 0; i < reload_n_operands; i++) 5236 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno) 5237 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5238 return 0; 5239 5240 return (! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 5241 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno)); 5242 5243 case RELOAD_FOR_OTHER_ADDRESS: 5244 return ! TEST_HARD_REG_BIT (reload_reg_used_in_other_addr, regno); 5245 5246 default: 5247 gcc_unreachable (); 5248 } 5249 } 5250 5251 /* Return 1 if the value in reload reg REGNO, as used by the reload with 5252 the number RELOADNUM, is still available in REGNO at the end of the insn. 5253 5254 We can assume that the reload reg was already tested for availability 5255 at the time it is needed, and we should not check this again, 5256 in case the reg has already been marked in use. */ 5257 5258 static int 5259 reload_reg_reaches_end_p (unsigned int regno, int reloadnum) 5260 { 5261 int opnum = rld[reloadnum].opnum; 5262 enum reload_type type = rld[reloadnum].when_needed; 5263 int i; 5264 5265 /* See if there is a reload with the same type for this operand, using 5266 the same register. This case is not handled by the code below. */ 5267 for (i = reloadnum + 1; i < n_reloads; i++) 5268 { 5269 rtx reg; 5270 5271 if (rld[i].opnum != opnum || rld[i].when_needed != type) 5272 continue; 5273 reg = rld[i].reg_rtx; 5274 if (reg == NULL_RTX) 5275 continue; 5276 if (regno >= REGNO (reg) && regno < END_REGNO (reg)) 5277 return 0; 5278 } 5279 5280 switch (type) 5281 { 5282 case RELOAD_OTHER: 5283 /* Since a RELOAD_OTHER reload claims the reg for the entire insn, 5284 its value must reach the end. */ 5285 return 1; 5286 5287 /* If this use is for part of the insn, 5288 its value reaches if no subsequent part uses the same register. 5289 Just like the above function, don't try to do this with lots 5290 of fallthroughs. */ 5291 5292 case RELOAD_FOR_OTHER_ADDRESS: 5293 /* Here we check for everything else, since these don't conflict 5294 with anything else and everything comes later. */ 5295 5296 for (i = 0; i < reload_n_operands; i++) 5297 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5298 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 5299 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno) 5300 || TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 5301 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 5302 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 5303 return 0; 5304 5305 return (! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 5306 && ! TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno) 5307 && ! TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 5308 && ! TEST_HARD_REG_BIT (reload_reg_used, regno)); 5309 5310 case RELOAD_FOR_INPUT_ADDRESS: 5311 case RELOAD_FOR_INPADDR_ADDRESS: 5312 /* Similar, except that we check only for this and subsequent inputs 5313 and the address of only subsequent inputs and we do not need 5314 to check for RELOAD_OTHER objects since they are known not to 5315 conflict. */ 5316 5317 for (i = opnum; i < reload_n_operands; i++) 5318 if (TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 5319 return 0; 5320 5321 /* Reload register of reload with type RELOAD_FOR_INPADDR_ADDRESS 5322 could be killed if the register is also used by reload with type 5323 RELOAD_FOR_INPUT_ADDRESS, so check it. */ 5324 if (type == RELOAD_FOR_INPADDR_ADDRESS 5325 && TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[opnum], regno)) 5326 return 0; 5327 5328 for (i = opnum + 1; i < reload_n_operands; i++) 5329 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 5330 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno)) 5331 return 0; 5332 5333 for (i = 0; i < reload_n_operands; i++) 5334 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5335 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 5336 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5337 return 0; 5338 5339 if (TEST_HARD_REG_BIT (reload_reg_used_in_op_addr_reload, regno)) 5340 return 0; 5341 5342 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 5343 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 5344 && !TEST_HARD_REG_BIT (reload_reg_used, regno)); 5345 5346 case RELOAD_FOR_INPUT: 5347 /* Similar to input address, except we start at the next operand for 5348 both input and input address and we do not check for 5349 RELOAD_FOR_OPERAND_ADDRESS and RELOAD_FOR_INSN since these 5350 would conflict. */ 5351 5352 for (i = opnum + 1; i < reload_n_operands; i++) 5353 if (TEST_HARD_REG_BIT (reload_reg_used_in_input_addr[i], regno) 5354 || TEST_HARD_REG_BIT (reload_reg_used_in_inpaddr_addr[i], regno) 5355 || TEST_HARD_REG_BIT (reload_reg_used_in_input[i], regno)) 5356 return 0; 5357 5358 /* ... fall through ... */ 5359 5360 case RELOAD_FOR_OPERAND_ADDRESS: 5361 /* Check outputs and their addresses. */ 5362 5363 for (i = 0; i < reload_n_operands; i++) 5364 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5365 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 5366 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5367 return 0; 5368 5369 return (!TEST_HARD_REG_BIT (reload_reg_used, regno)); 5370 5371 case RELOAD_FOR_OPADDR_ADDR: 5372 for (i = 0; i < reload_n_operands; i++) 5373 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5374 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno) 5375 || TEST_HARD_REG_BIT (reload_reg_used_in_output[i], regno)) 5376 return 0; 5377 5378 return (!TEST_HARD_REG_BIT (reload_reg_used_in_op_addr, regno) 5379 && !TEST_HARD_REG_BIT (reload_reg_used_in_insn, regno) 5380 && !TEST_HARD_REG_BIT (reload_reg_used, regno)); 5381 5382 case RELOAD_FOR_INSN: 5383 /* These conflict with other outputs with RELOAD_OTHER. So 5384 we need only check for output addresses. */ 5385 5386 opnum = reload_n_operands; 5387 5388 /* fall through */ 5389 5390 case RELOAD_FOR_OUTPUT: 5391 case RELOAD_FOR_OUTPUT_ADDRESS: 5392 case RELOAD_FOR_OUTADDR_ADDRESS: 5393 /* We already know these can't conflict with a later output. So the 5394 only thing to check are later output addresses. 5395 Note that multiple output operands are emitted in reverse order, 5396 so the conflicting ones are those with lower indices. */ 5397 for (i = 0; i < opnum; i++) 5398 if (TEST_HARD_REG_BIT (reload_reg_used_in_output_addr[i], regno) 5399 || TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[i], regno)) 5400 return 0; 5401 5402 /* Reload register of reload with type RELOAD_FOR_OUTADDR_ADDRESS 5403 could be killed if the register is also used by reload with type 5404 RELOAD_FOR_OUTPUT_ADDRESS, so check it. */ 5405 if (type == RELOAD_FOR_OUTADDR_ADDRESS 5406 && TEST_HARD_REG_BIT (reload_reg_used_in_outaddr_addr[opnum], regno)) 5407 return 0; 5408 5409 return 1; 5410 5411 default: 5412 gcc_unreachable (); 5413 } 5414 } 5415 5416 /* Like reload_reg_reaches_end_p, but check that the condition holds for 5417 every register in REG. */ 5418 5419 static bool 5420 reload_reg_rtx_reaches_end_p (rtx reg, int reloadnum) 5421 { 5422 unsigned int i; 5423 5424 for (i = REGNO (reg); i < END_REGNO (reg); i++) 5425 if (!reload_reg_reaches_end_p (i, reloadnum)) 5426 return false; 5427 return true; 5428 } 5429 5430 5431 /* Returns whether R1 and R2 are uniquely chained: the value of one 5432 is used by the other, and that value is not used by any other 5433 reload for this insn. This is used to partially undo the decision 5434 made in find_reloads when in the case of multiple 5435 RELOAD_FOR_OPERAND_ADDRESS reloads it converts all 5436 RELOAD_FOR_OPADDR_ADDR reloads into RELOAD_FOR_OPERAND_ADDRESS 5437 reloads. This code tries to avoid the conflict created by that 5438 change. It might be cleaner to explicitly keep track of which 5439 RELOAD_FOR_OPADDR_ADDR reload is associated with which 5440 RELOAD_FOR_OPERAND_ADDRESS reload, rather than to try to detect 5441 this after the fact. */ 5442 static bool 5443 reloads_unique_chain_p (int r1, int r2) 5444 { 5445 int i; 5446 5447 /* We only check input reloads. */ 5448 if (! rld[r1].in || ! rld[r2].in) 5449 return false; 5450 5451 /* Avoid anything with output reloads. */ 5452 if (rld[r1].out || rld[r2].out) 5453 return false; 5454 5455 /* "chained" means one reload is a component of the other reload, 5456 not the same as the other reload. */ 5457 if (rld[r1].opnum != rld[r2].opnum 5458 || rtx_equal_p (rld[r1].in, rld[r2].in) 5459 || rld[r1].optional || rld[r2].optional 5460 || ! (reg_mentioned_p (rld[r1].in, rld[r2].in) 5461 || reg_mentioned_p (rld[r2].in, rld[r1].in))) 5462 return false; 5463 5464 /* The following loop assumes that r1 is the reload that feeds r2. */ 5465 if (r1 > r2) 5466 std::swap (r1, r2); 5467 5468 for (i = 0; i < n_reloads; i ++) 5469 /* Look for input reloads that aren't our two */ 5470 if (i != r1 && i != r2 && rld[i].in) 5471 { 5472 /* If our reload is mentioned at all, it isn't a simple chain. */ 5473 if (reg_mentioned_p (rld[r1].in, rld[i].in)) 5474 return false; 5475 } 5476 return true; 5477 } 5478 5479 /* The recursive function change all occurrences of WHAT in *WHERE 5480 to REPL. */ 5481 static void 5482 substitute (rtx *where, const_rtx what, rtx repl) 5483 { 5484 const char *fmt; 5485 int i; 5486 enum rtx_code code; 5487 5488 if (*where == 0) 5489 return; 5490 5491 if (*where == what || rtx_equal_p (*where, what)) 5492 { 5493 /* Record the location of the changed rtx. */ 5494 substitute_stack.safe_push (where); 5495 *where = repl; 5496 return; 5497 } 5498 5499 code = GET_CODE (*where); 5500 fmt = GET_RTX_FORMAT (code); 5501 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 5502 { 5503 if (fmt[i] == 'E') 5504 { 5505 int j; 5506 5507 for (j = XVECLEN (*where, i) - 1; j >= 0; j--) 5508 substitute (&XVECEXP (*where, i, j), what, repl); 5509 } 5510 else if (fmt[i] == 'e') 5511 substitute (&XEXP (*where, i), what, repl); 5512 } 5513 } 5514 5515 /* The function returns TRUE if chain of reload R1 and R2 (in any 5516 order) can be evaluated without usage of intermediate register for 5517 the reload containing another reload. It is important to see 5518 gen_reload to understand what the function is trying to do. As an 5519 example, let us have reload chain 5520 5521 r2: const 5522 r1: <something> + const 5523 5524 and reload R2 got reload reg HR. The function returns true if 5525 there is a correct insn HR = HR + <something>. Otherwise, 5526 gen_reload will use intermediate register (and this is the reload 5527 reg for R1) to reload <something>. 5528 5529 We need this function to find a conflict for chain reloads. In our 5530 example, if HR = HR + <something> is incorrect insn, then we cannot 5531 use HR as a reload register for R2. If we do use it then we get a 5532 wrong code: 5533 5534 HR = const 5535 HR = <something> 5536 HR = HR + HR 5537 5538 */ 5539 static bool 5540 gen_reload_chain_without_interm_reg_p (int r1, int r2) 5541 { 5542 /* Assume other cases in gen_reload are not possible for 5543 chain reloads or do need an intermediate hard registers. */ 5544 bool result = true; 5545 int regno, code; 5546 rtx out, in; 5547 rtx_insn *insn; 5548 rtx_insn *last = get_last_insn (); 5549 5550 /* Make r2 a component of r1. */ 5551 if (reg_mentioned_p (rld[r1].in, rld[r2].in)) 5552 std::swap (r1, r2); 5553 5554 gcc_assert (reg_mentioned_p (rld[r2].in, rld[r1].in)); 5555 regno = rld[r1].regno >= 0 ? rld[r1].regno : rld[r2].regno; 5556 gcc_assert (regno >= 0); 5557 out = gen_rtx_REG (rld[r1].mode, regno); 5558 in = rld[r1].in; 5559 substitute (&in, rld[r2].in, gen_rtx_REG (rld[r2].mode, regno)); 5560 5561 /* If IN is a paradoxical SUBREG, remove it and try to put the 5562 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ 5563 strip_paradoxical_subreg (&in, &out); 5564 5565 if (GET_CODE (in) == PLUS 5566 && (REG_P (XEXP (in, 0)) 5567 || GET_CODE (XEXP (in, 0)) == SUBREG 5568 || MEM_P (XEXP (in, 0))) 5569 && (REG_P (XEXP (in, 1)) 5570 || GET_CODE (XEXP (in, 1)) == SUBREG 5571 || CONSTANT_P (XEXP (in, 1)) 5572 || MEM_P (XEXP (in, 1)))) 5573 { 5574 insn = emit_insn (gen_rtx_SET (out, in)); 5575 code = recog_memoized (insn); 5576 result = false; 5577 5578 if (code >= 0) 5579 { 5580 extract_insn (insn); 5581 /* We want constrain operands to treat this insn strictly in 5582 its validity determination, i.e., the way it would after 5583 reload has completed. */ 5584 result = constrain_operands (1, get_enabled_alternatives (insn)); 5585 } 5586 5587 delete_insns_since (last); 5588 } 5589 5590 /* Restore the original value at each changed address within R1. */ 5591 while (!substitute_stack.is_empty ()) 5592 { 5593 rtx *where = substitute_stack.pop (); 5594 *where = rld[r2].in; 5595 } 5596 5597 return result; 5598 } 5599 5600 /* Return 1 if the reloads denoted by R1 and R2 cannot share a register. 5601 Return 0 otherwise. 5602 5603 This function uses the same algorithm as reload_reg_free_p above. */ 5604 5605 static int 5606 reloads_conflict (int r1, int r2) 5607 { 5608 enum reload_type r1_type = rld[r1].when_needed; 5609 enum reload_type r2_type = rld[r2].when_needed; 5610 int r1_opnum = rld[r1].opnum; 5611 int r2_opnum = rld[r2].opnum; 5612 5613 /* RELOAD_OTHER conflicts with everything. */ 5614 if (r2_type == RELOAD_OTHER) 5615 return 1; 5616 5617 /* Otherwise, check conflicts differently for each type. */ 5618 5619 switch (r1_type) 5620 { 5621 case RELOAD_FOR_INPUT: 5622 return (r2_type == RELOAD_FOR_INSN 5623 || r2_type == RELOAD_FOR_OPERAND_ADDRESS 5624 || r2_type == RELOAD_FOR_OPADDR_ADDR 5625 || r2_type == RELOAD_FOR_INPUT 5626 || ((r2_type == RELOAD_FOR_INPUT_ADDRESS 5627 || r2_type == RELOAD_FOR_INPADDR_ADDRESS) 5628 && r2_opnum > r1_opnum)); 5629 5630 case RELOAD_FOR_INPUT_ADDRESS: 5631 return ((r2_type == RELOAD_FOR_INPUT_ADDRESS && r1_opnum == r2_opnum) 5632 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 5633 5634 case RELOAD_FOR_INPADDR_ADDRESS: 5635 return ((r2_type == RELOAD_FOR_INPADDR_ADDRESS && r1_opnum == r2_opnum) 5636 || (r2_type == RELOAD_FOR_INPUT && r2_opnum < r1_opnum)); 5637 5638 case RELOAD_FOR_OUTPUT_ADDRESS: 5639 return ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS && r2_opnum == r1_opnum) 5640 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); 5641 5642 case RELOAD_FOR_OUTADDR_ADDRESS: 5643 return ((r2_type == RELOAD_FOR_OUTADDR_ADDRESS && r2_opnum == r1_opnum) 5644 || (r2_type == RELOAD_FOR_OUTPUT && r2_opnum <= r1_opnum)); 5645 5646 case RELOAD_FOR_OPERAND_ADDRESS: 5647 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_INSN 5648 || (r2_type == RELOAD_FOR_OPERAND_ADDRESS 5649 && (!reloads_unique_chain_p (r1, r2) 5650 || !gen_reload_chain_without_interm_reg_p (r1, r2)))); 5651 5652 case RELOAD_FOR_OPADDR_ADDR: 5653 return (r2_type == RELOAD_FOR_INPUT 5654 || r2_type == RELOAD_FOR_OPADDR_ADDR); 5655 5656 case RELOAD_FOR_OUTPUT: 5657 return (r2_type == RELOAD_FOR_INSN || r2_type == RELOAD_FOR_OUTPUT 5658 || ((r2_type == RELOAD_FOR_OUTPUT_ADDRESS 5659 || r2_type == RELOAD_FOR_OUTADDR_ADDRESS) 5660 && r2_opnum >= r1_opnum)); 5661 5662 case RELOAD_FOR_INSN: 5663 return (r2_type == RELOAD_FOR_INPUT || r2_type == RELOAD_FOR_OUTPUT 5664 || r2_type == RELOAD_FOR_INSN 5665 || r2_type == RELOAD_FOR_OPERAND_ADDRESS); 5666 5667 case RELOAD_FOR_OTHER_ADDRESS: 5668 return r2_type == RELOAD_FOR_OTHER_ADDRESS; 5669 5670 case RELOAD_OTHER: 5671 return 1; 5672 5673 default: 5674 gcc_unreachable (); 5675 } 5676 } 5677 5678 /* Indexed by reload number, 1 if incoming value 5679 inherited from previous insns. */ 5680 static char reload_inherited[MAX_RELOADS]; 5681 5682 /* For an inherited reload, this is the insn the reload was inherited from, 5683 if we know it. Otherwise, this is 0. */ 5684 static rtx_insn *reload_inheritance_insn[MAX_RELOADS]; 5685 5686 /* If nonzero, this is a place to get the value of the reload, 5687 rather than using reload_in. */ 5688 static rtx reload_override_in[MAX_RELOADS]; 5689 5690 /* For each reload, the hard register number of the register used, 5691 or -1 if we did not need a register for this reload. */ 5692 static int reload_spill_index[MAX_RELOADS]; 5693 5694 /* Index X is the value of rld[X].reg_rtx, adjusted for the input mode. */ 5695 static rtx reload_reg_rtx_for_input[MAX_RELOADS]; 5696 5697 /* Index X is the value of rld[X].reg_rtx, adjusted for the output mode. */ 5698 static rtx reload_reg_rtx_for_output[MAX_RELOADS]; 5699 5700 /* Subroutine of free_for_value_p, used to check a single register. 5701 START_REGNO is the starting regno of the full reload register 5702 (possibly comprising multiple hard registers) that we are considering. */ 5703 5704 static int 5705 reload_reg_free_for_value_p (int start_regno, int regno, int opnum, 5706 enum reload_type type, rtx value, rtx out, 5707 int reloadnum, int ignore_address_reloads) 5708 { 5709 int time1; 5710 /* Set if we see an input reload that must not share its reload register 5711 with any new earlyclobber, but might otherwise share the reload 5712 register with an output or input-output reload. */ 5713 int check_earlyclobber = 0; 5714 int i; 5715 int copy = 0; 5716 5717 if (TEST_HARD_REG_BIT (reload_reg_unavailable, regno)) 5718 return 0; 5719 5720 if (out == const0_rtx) 5721 { 5722 copy = 1; 5723 out = NULL_RTX; 5724 } 5725 5726 /* We use some pseudo 'time' value to check if the lifetimes of the 5727 new register use would overlap with the one of a previous reload 5728 that is not read-only or uses a different value. 5729 The 'time' used doesn't have to be linear in any shape or form, just 5730 monotonic. 5731 Some reload types use different 'buckets' for each operand. 5732 So there are MAX_RECOG_OPERANDS different time values for each 5733 such reload type. 5734 We compute TIME1 as the time when the register for the prospective 5735 new reload ceases to be live, and TIME2 for each existing 5736 reload as the time when that the reload register of that reload 5737 becomes live. 5738 Where there is little to be gained by exact lifetime calculations, 5739 we just make conservative assumptions, i.e. a longer lifetime; 5740 this is done in the 'default:' cases. */ 5741 switch (type) 5742 { 5743 case RELOAD_FOR_OTHER_ADDRESS: 5744 /* RELOAD_FOR_OTHER_ADDRESS conflicts with RELOAD_OTHER reloads. */ 5745 time1 = copy ? 0 : 1; 5746 break; 5747 case RELOAD_OTHER: 5748 time1 = copy ? 1 : MAX_RECOG_OPERANDS * 5 + 5; 5749 break; 5750 /* For each input, we may have a sequence of RELOAD_FOR_INPADDR_ADDRESS, 5751 RELOAD_FOR_INPUT_ADDRESS and RELOAD_FOR_INPUT. By adding 0 / 1 / 2 , 5752 respectively, to the time values for these, we get distinct time 5753 values. To get distinct time values for each operand, we have to 5754 multiply opnum by at least three. We round that up to four because 5755 multiply by four is often cheaper. */ 5756 case RELOAD_FOR_INPADDR_ADDRESS: 5757 time1 = opnum * 4 + 2; 5758 break; 5759 case RELOAD_FOR_INPUT_ADDRESS: 5760 time1 = opnum * 4 + 3; 5761 break; 5762 case RELOAD_FOR_INPUT: 5763 /* All RELOAD_FOR_INPUT reloads remain live till the instruction 5764 executes (inclusive). */ 5765 time1 = copy ? opnum * 4 + 4 : MAX_RECOG_OPERANDS * 4 + 3; 5766 break; 5767 case RELOAD_FOR_OPADDR_ADDR: 5768 /* opnum * 4 + 4 5769 <= (MAX_RECOG_OPERANDS - 1) * 4 + 4 == MAX_RECOG_OPERANDS * 4 */ 5770 time1 = MAX_RECOG_OPERANDS * 4 + 1; 5771 break; 5772 case RELOAD_FOR_OPERAND_ADDRESS: 5773 /* RELOAD_FOR_OPERAND_ADDRESS reloads are live even while the insn 5774 is executed. */ 5775 time1 = copy ? MAX_RECOG_OPERANDS * 4 + 2 : MAX_RECOG_OPERANDS * 4 + 3; 5776 break; 5777 case RELOAD_FOR_OUTADDR_ADDRESS: 5778 time1 = MAX_RECOG_OPERANDS * 4 + 4 + opnum; 5779 break; 5780 case RELOAD_FOR_OUTPUT_ADDRESS: 5781 time1 = MAX_RECOG_OPERANDS * 4 + 5 + opnum; 5782 break; 5783 default: 5784 time1 = MAX_RECOG_OPERANDS * 5 + 5; 5785 } 5786 5787 for (i = 0; i < n_reloads; i++) 5788 { 5789 rtx reg = rld[i].reg_rtx; 5790 if (reg && REG_P (reg) 5791 && (unsigned) regno - true_regnum (reg) < REG_NREGS (reg) 5792 && i != reloadnum) 5793 { 5794 rtx other_input = rld[i].in; 5795 5796 /* If the other reload loads the same input value, that 5797 will not cause a conflict only if it's loading it into 5798 the same register. */ 5799 if (true_regnum (reg) != start_regno) 5800 other_input = NULL_RTX; 5801 if (! other_input || ! rtx_equal_p (other_input, value) 5802 || rld[i].out || out) 5803 { 5804 int time2; 5805 switch (rld[i].when_needed) 5806 { 5807 case RELOAD_FOR_OTHER_ADDRESS: 5808 time2 = 0; 5809 break; 5810 case RELOAD_FOR_INPADDR_ADDRESS: 5811 /* find_reloads makes sure that a 5812 RELOAD_FOR_{INP,OP,OUT}ADDR_ADDRESS reload is only used 5813 by at most one - the first - 5814 RELOAD_FOR_{INPUT,OPERAND,OUTPUT}_ADDRESS . If the 5815 address reload is inherited, the address address reload 5816 goes away, so we can ignore this conflict. */ 5817 if (type == RELOAD_FOR_INPUT_ADDRESS && reloadnum == i + 1 5818 && ignore_address_reloads 5819 /* Unless the RELOAD_FOR_INPUT is an auto_inc expression. 5820 Then the address address is still needed to store 5821 back the new address. */ 5822 && ! rld[reloadnum].out) 5823 continue; 5824 /* Likewise, if a RELOAD_FOR_INPUT can inherit a value, its 5825 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS 5826 reloads go away. */ 5827 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum 5828 && ignore_address_reloads 5829 /* Unless we are reloading an auto_inc expression. */ 5830 && ! rld[reloadnum].out) 5831 continue; 5832 time2 = rld[i].opnum * 4 + 2; 5833 break; 5834 case RELOAD_FOR_INPUT_ADDRESS: 5835 if (type == RELOAD_FOR_INPUT && opnum == rld[i].opnum 5836 && ignore_address_reloads 5837 && ! rld[reloadnum].out) 5838 continue; 5839 time2 = rld[i].opnum * 4 + 3; 5840 break; 5841 case RELOAD_FOR_INPUT: 5842 time2 = rld[i].opnum * 4 + 4; 5843 check_earlyclobber = 1; 5844 break; 5845 /* rld[i].opnum * 4 + 4 <= (MAX_RECOG_OPERAND - 1) * 4 + 4 5846 == MAX_RECOG_OPERAND * 4 */ 5847 case RELOAD_FOR_OPADDR_ADDR: 5848 if (type == RELOAD_FOR_OPERAND_ADDRESS && reloadnum == i + 1 5849 && ignore_address_reloads 5850 && ! rld[reloadnum].out) 5851 continue; 5852 time2 = MAX_RECOG_OPERANDS * 4 + 1; 5853 break; 5854 case RELOAD_FOR_OPERAND_ADDRESS: 5855 time2 = MAX_RECOG_OPERANDS * 4 + 2; 5856 check_earlyclobber = 1; 5857 break; 5858 case RELOAD_FOR_INSN: 5859 time2 = MAX_RECOG_OPERANDS * 4 + 3; 5860 break; 5861 case RELOAD_FOR_OUTPUT: 5862 /* All RELOAD_FOR_OUTPUT reloads become live just after the 5863 instruction is executed. */ 5864 time2 = MAX_RECOG_OPERANDS * 4 + 4; 5865 break; 5866 /* The first RELOAD_FOR_OUTADDR_ADDRESS reload conflicts with 5867 the RELOAD_FOR_OUTPUT reloads, so assign it the same time 5868 value. */ 5869 case RELOAD_FOR_OUTADDR_ADDRESS: 5870 if (type == RELOAD_FOR_OUTPUT_ADDRESS && reloadnum == i + 1 5871 && ignore_address_reloads 5872 && ! rld[reloadnum].out) 5873 continue; 5874 time2 = MAX_RECOG_OPERANDS * 4 + 4 + rld[i].opnum; 5875 break; 5876 case RELOAD_FOR_OUTPUT_ADDRESS: 5877 time2 = MAX_RECOG_OPERANDS * 4 + 5 + rld[i].opnum; 5878 break; 5879 case RELOAD_OTHER: 5880 /* If there is no conflict in the input part, handle this 5881 like an output reload. */ 5882 if (! rld[i].in || rtx_equal_p (other_input, value)) 5883 { 5884 time2 = MAX_RECOG_OPERANDS * 4 + 4; 5885 /* Earlyclobbered outputs must conflict with inputs. */ 5886 if (earlyclobber_operand_p (rld[i].out)) 5887 time2 = MAX_RECOG_OPERANDS * 4 + 3; 5888 5889 break; 5890 } 5891 time2 = 1; 5892 /* RELOAD_OTHER might be live beyond instruction execution, 5893 but this is not obvious when we set time2 = 1. So check 5894 here if there might be a problem with the new reload 5895 clobbering the register used by the RELOAD_OTHER. */ 5896 if (out) 5897 return 0; 5898 break; 5899 default: 5900 return 0; 5901 } 5902 if ((time1 >= time2 5903 && (! rld[i].in || rld[i].out 5904 || ! rtx_equal_p (other_input, value))) 5905 || (out && rld[reloadnum].out_reg 5906 && time2 >= MAX_RECOG_OPERANDS * 4 + 3)) 5907 return 0; 5908 } 5909 } 5910 } 5911 5912 /* Earlyclobbered outputs must conflict with inputs. */ 5913 if (check_earlyclobber && out && earlyclobber_operand_p (out)) 5914 return 0; 5915 5916 return 1; 5917 } 5918 5919 /* Return 1 if the value in reload reg REGNO, as used by a reload 5920 needed for the part of the insn specified by OPNUM and TYPE, 5921 may be used to load VALUE into it. 5922 5923 MODE is the mode in which the register is used, this is needed to 5924 determine how many hard regs to test. 5925 5926 Other read-only reloads with the same value do not conflict 5927 unless OUT is nonzero and these other reloads have to live while 5928 output reloads live. 5929 If OUT is CONST0_RTX, this is a special case: it means that the 5930 test should not be for using register REGNO as reload register, but 5931 for copying from register REGNO into the reload register. 5932 5933 RELOADNUM is the number of the reload we want to load this value for; 5934 a reload does not conflict with itself. 5935 5936 When IGNORE_ADDRESS_RELOADS is set, we cannot have conflicts with 5937 reloads that load an address for the very reload we are considering. 5938 5939 The caller has to make sure that there is no conflict with the return 5940 register. */ 5941 5942 static int 5943 free_for_value_p (int regno, machine_mode mode, int opnum, 5944 enum reload_type type, rtx value, rtx out, int reloadnum, 5945 int ignore_address_reloads) 5946 { 5947 int nregs = hard_regno_nregs (regno, mode); 5948 while (nregs-- > 0) 5949 if (! reload_reg_free_for_value_p (regno, regno + nregs, opnum, type, 5950 value, out, reloadnum, 5951 ignore_address_reloads)) 5952 return 0; 5953 return 1; 5954 } 5955 5956 /* Return nonzero if the rtx X is invariant over the current function. */ 5957 /* ??? Actually, the places where we use this expect exactly what is 5958 tested here, and not everything that is function invariant. In 5959 particular, the frame pointer and arg pointer are special cased; 5960 pic_offset_table_rtx is not, and we must not spill these things to 5961 memory. */ 5962 5963 int 5964 function_invariant_p (const_rtx x) 5965 { 5966 if (CONSTANT_P (x)) 5967 return 1; 5968 if (x == frame_pointer_rtx || x == arg_pointer_rtx) 5969 return 1; 5970 if (GET_CODE (x) == PLUS 5971 && (XEXP (x, 0) == frame_pointer_rtx || XEXP (x, 0) == arg_pointer_rtx) 5972 && GET_CODE (XEXP (x, 1)) == CONST_INT) 5973 return 1; 5974 return 0; 5975 } 5976 5977 /* Determine whether the reload reg X overlaps any rtx'es used for 5978 overriding inheritance. Return nonzero if so. */ 5979 5980 static int 5981 conflicts_with_override (rtx x) 5982 { 5983 int i; 5984 for (i = 0; i < n_reloads; i++) 5985 if (reload_override_in[i] 5986 && reg_overlap_mentioned_p (x, reload_override_in[i])) 5987 return 1; 5988 return 0; 5989 } 5990 5991 /* Give an error message saying we failed to find a reload for INSN, 5992 and clear out reload R. */ 5993 static void 5994 failed_reload (rtx_insn *insn, int r) 5995 { 5996 if (asm_noperands (PATTERN (insn)) < 0) 5997 /* It's the compiler's fault. */ 5998 fatal_insn ("could not find a spill register", insn); 5999 6000 /* It's the user's fault; the operand's mode and constraint 6001 don't match. Disable this reload so we don't crash in final. */ 6002 error_for_asm (insn, 6003 "%<asm%> operand constraint incompatible with operand size"); 6004 rld[r].in = 0; 6005 rld[r].out = 0; 6006 rld[r].reg_rtx = 0; 6007 rld[r].optional = 1; 6008 rld[r].secondary_p = 1; 6009 } 6010 6011 /* I is the index in SPILL_REG_RTX of the reload register we are to allocate 6012 for reload R. If it's valid, get an rtx for it. Return nonzero if 6013 successful. */ 6014 static int 6015 set_reload_reg (int i, int r) 6016 { 6017 int regno; 6018 rtx reg = spill_reg_rtx[i]; 6019 6020 if (reg == 0 || GET_MODE (reg) != rld[r].mode) 6021 spill_reg_rtx[i] = reg 6022 = gen_rtx_REG (rld[r].mode, spill_regs[i]); 6023 6024 regno = true_regnum (reg); 6025 6026 /* Detect when the reload reg can't hold the reload mode. 6027 This used to be one `if', but Sequent compiler can't handle that. */ 6028 if (targetm.hard_regno_mode_ok (regno, rld[r].mode)) 6029 { 6030 machine_mode test_mode = VOIDmode; 6031 if (rld[r].in) 6032 test_mode = GET_MODE (rld[r].in); 6033 /* If rld[r].in has VOIDmode, it means we will load it 6034 in whatever mode the reload reg has: to wit, rld[r].mode. 6035 We have already tested that for validity. */ 6036 /* Aside from that, we need to test that the expressions 6037 to reload from or into have modes which are valid for this 6038 reload register. Otherwise the reload insns would be invalid. */ 6039 if (! (rld[r].in != 0 && test_mode != VOIDmode 6040 && !targetm.hard_regno_mode_ok (regno, test_mode))) 6041 if (! (rld[r].out != 0 6042 && !targetm.hard_regno_mode_ok (regno, GET_MODE (rld[r].out)))) 6043 { 6044 /* The reg is OK. */ 6045 last_spill_reg = i; 6046 6047 /* Mark as in use for this insn the reload regs we use 6048 for this. */ 6049 mark_reload_reg_in_use (spill_regs[i], rld[r].opnum, 6050 rld[r].when_needed, rld[r].mode); 6051 6052 rld[r].reg_rtx = reg; 6053 reload_spill_index[r] = spill_regs[i]; 6054 return 1; 6055 } 6056 } 6057 return 0; 6058 } 6059 6060 /* Find a spill register to use as a reload register for reload R. 6061 LAST_RELOAD is nonzero if this is the last reload for the insn being 6062 processed. 6063 6064 Set rld[R].reg_rtx to the register allocated. 6065 6066 We return 1 if successful, or 0 if we couldn't find a spill reg and 6067 we didn't change anything. */ 6068 6069 static int 6070 allocate_reload_reg (class insn_chain *chain ATTRIBUTE_UNUSED, int r, 6071 int last_reload) 6072 { 6073 int i, pass, count; 6074 6075 /* If we put this reload ahead, thinking it is a group, 6076 then insist on finding a group. Otherwise we can grab a 6077 reg that some other reload needs. 6078 (That can happen when we have a 68000 DATA_OR_FP_REG 6079 which is a group of data regs or one fp reg.) 6080 We need not be so restrictive if there are no more reloads 6081 for this insn. 6082 6083 ??? Really it would be nicer to have smarter handling 6084 for that kind of reg class, where a problem like this is normal. 6085 Perhaps those classes should be avoided for reloading 6086 by use of more alternatives. */ 6087 6088 int force_group = rld[r].nregs > 1 && ! last_reload; 6089 6090 /* If we want a single register and haven't yet found one, 6091 take any reg in the right class and not in use. 6092 If we want a consecutive group, here is where we look for it. 6093 6094 We use three passes so we can first look for reload regs to 6095 reuse, which are already in use for other reloads in this insn, 6096 and only then use additional registers which are not "bad", then 6097 finally any register. 6098 6099 I think that maximizing reuse is needed to make sure we don't 6100 run out of reload regs. Suppose we have three reloads, and 6101 reloads A and B can share regs. These need two regs. 6102 Suppose A and B are given different regs. 6103 That leaves none for C. */ 6104 for (pass = 0; pass < 3; pass++) 6105 { 6106 /* I is the index in spill_regs. 6107 We advance it round-robin between insns to use all spill regs 6108 equally, so that inherited reloads have a chance 6109 of leapfrogging each other. */ 6110 6111 i = last_spill_reg; 6112 6113 for (count = 0; count < n_spills; count++) 6114 { 6115 int rclass = (int) rld[r].rclass; 6116 int regnum; 6117 6118 i++; 6119 if (i >= n_spills) 6120 i -= n_spills; 6121 regnum = spill_regs[i]; 6122 6123 if ((reload_reg_free_p (regnum, rld[r].opnum, 6124 rld[r].when_needed) 6125 || (rld[r].in 6126 /* We check reload_reg_used to make sure we 6127 don't clobber the return register. */ 6128 && ! TEST_HARD_REG_BIT (reload_reg_used, regnum) 6129 && free_for_value_p (regnum, rld[r].mode, rld[r].opnum, 6130 rld[r].when_needed, rld[r].in, 6131 rld[r].out, r, 1))) 6132 && TEST_HARD_REG_BIT (reg_class_contents[rclass], regnum) 6133 && targetm.hard_regno_mode_ok (regnum, rld[r].mode) 6134 /* Look first for regs to share, then for unshared. But 6135 don't share regs used for inherited reloads; they are 6136 the ones we want to preserve. */ 6137 && (pass 6138 || (TEST_HARD_REG_BIT (reload_reg_used_at_all, 6139 regnum) 6140 && ! TEST_HARD_REG_BIT (reload_reg_used_for_inherit, 6141 regnum)))) 6142 { 6143 int nr = hard_regno_nregs (regnum, rld[r].mode); 6144 6145 /* During the second pass we want to avoid reload registers 6146 which are "bad" for this reload. */ 6147 if (pass == 1 6148 && ira_bad_reload_regno (regnum, rld[r].in, rld[r].out)) 6149 continue; 6150 6151 /* Avoid the problem where spilling a GENERAL_OR_FP_REG 6152 (on 68000) got us two FP regs. If NR is 1, 6153 we would reject both of them. */ 6154 if (force_group) 6155 nr = rld[r].nregs; 6156 /* If we need only one reg, we have already won. */ 6157 if (nr == 1) 6158 { 6159 /* But reject a single reg if we demand a group. */ 6160 if (force_group) 6161 continue; 6162 break; 6163 } 6164 /* Otherwise check that as many consecutive regs as we need 6165 are available here. */ 6166 while (nr > 1) 6167 { 6168 int regno = regnum + nr - 1; 6169 if (!(TEST_HARD_REG_BIT (reg_class_contents[rclass], regno) 6170 && spill_reg_order[regno] >= 0 6171 && reload_reg_free_p (regno, rld[r].opnum, 6172 rld[r].when_needed))) 6173 break; 6174 nr--; 6175 } 6176 if (nr == 1) 6177 break; 6178 } 6179 } 6180 6181 /* If we found something on the current pass, omit later passes. */ 6182 if (count < n_spills) 6183 break; 6184 } 6185 6186 /* We should have found a spill register by now. */ 6187 if (count >= n_spills) 6188 return 0; 6189 6190 /* I is the index in SPILL_REG_RTX of the reload register we are to 6191 allocate. Get an rtx for it and find its register number. */ 6192 6193 return set_reload_reg (i, r); 6194 } 6195 6196 /* Initialize all the tables needed to allocate reload registers. 6197 CHAIN is the insn currently being processed; SAVE_RELOAD_REG_RTX 6198 is the array we use to restore the reg_rtx field for every reload. */ 6199 6200 static void 6201 choose_reload_regs_init (class insn_chain *chain, rtx *save_reload_reg_rtx) 6202 { 6203 int i; 6204 6205 for (i = 0; i < n_reloads; i++) 6206 rld[i].reg_rtx = save_reload_reg_rtx[i]; 6207 6208 memset (reload_inherited, 0, MAX_RELOADS); 6209 memset (reload_inheritance_insn, 0, MAX_RELOADS * sizeof (rtx)); 6210 memset (reload_override_in, 0, MAX_RELOADS * sizeof (rtx)); 6211 6212 CLEAR_HARD_REG_SET (reload_reg_used); 6213 CLEAR_HARD_REG_SET (reload_reg_used_at_all); 6214 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr); 6215 CLEAR_HARD_REG_SET (reload_reg_used_in_op_addr_reload); 6216 CLEAR_HARD_REG_SET (reload_reg_used_in_insn); 6217 CLEAR_HARD_REG_SET (reload_reg_used_in_other_addr); 6218 6219 CLEAR_HARD_REG_SET (reg_used_in_insn); 6220 { 6221 HARD_REG_SET tmp; 6222 REG_SET_TO_HARD_REG_SET (tmp, &chain->live_throughout); 6223 reg_used_in_insn |= tmp; 6224 REG_SET_TO_HARD_REG_SET (tmp, &chain->dead_or_set); 6225 reg_used_in_insn |= tmp; 6226 compute_use_by_pseudos (®_used_in_insn, &chain->live_throughout); 6227 compute_use_by_pseudos (®_used_in_insn, &chain->dead_or_set); 6228 } 6229 6230 for (i = 0; i < reload_n_operands; i++) 6231 { 6232 CLEAR_HARD_REG_SET (reload_reg_used_in_output[i]); 6233 CLEAR_HARD_REG_SET (reload_reg_used_in_input[i]); 6234 CLEAR_HARD_REG_SET (reload_reg_used_in_input_addr[i]); 6235 CLEAR_HARD_REG_SET (reload_reg_used_in_inpaddr_addr[i]); 6236 CLEAR_HARD_REG_SET (reload_reg_used_in_output_addr[i]); 6237 CLEAR_HARD_REG_SET (reload_reg_used_in_outaddr_addr[i]); 6238 } 6239 6240 reload_reg_unavailable = ~chain->used_spill_regs; 6241 6242 CLEAR_HARD_REG_SET (reload_reg_used_for_inherit); 6243 6244 for (i = 0; i < n_reloads; i++) 6245 /* If we have already decided to use a certain register, 6246 don't use it in another way. */ 6247 if (rld[i].reg_rtx) 6248 mark_reload_reg_in_use (REGNO (rld[i].reg_rtx), rld[i].opnum, 6249 rld[i].when_needed, rld[i].mode); 6250 } 6251 6252 /* If X is not a subreg, return it unmodified. If it is a subreg, 6253 look up whether we made a replacement for the SUBREG_REG. Return 6254 either the replacement or the SUBREG_REG. */ 6255 6256 static rtx 6257 replaced_subreg (rtx x) 6258 { 6259 if (GET_CODE (x) == SUBREG) 6260 return find_replacement (&SUBREG_REG (x)); 6261 return x; 6262 } 6263 6264 /* Compute the offset to pass to subreg_regno_offset, for a pseudo of 6265 mode OUTERMODE that is available in a hard reg of mode INNERMODE. 6266 SUBREG is non-NULL if the pseudo is a subreg whose reg is a pseudo, 6267 otherwise it is NULL. */ 6268 6269 static poly_int64 6270 compute_reload_subreg_offset (machine_mode outermode, 6271 rtx subreg, 6272 machine_mode innermode) 6273 { 6274 poly_int64 outer_offset; 6275 machine_mode middlemode; 6276 6277 if (!subreg) 6278 return subreg_lowpart_offset (outermode, innermode); 6279 6280 outer_offset = SUBREG_BYTE (subreg); 6281 middlemode = GET_MODE (SUBREG_REG (subreg)); 6282 6283 /* If SUBREG is paradoxical then return the normal lowpart offset 6284 for OUTERMODE and INNERMODE. Our caller has already checked 6285 that OUTERMODE fits in INNERMODE. */ 6286 if (paradoxical_subreg_p (outermode, middlemode)) 6287 return subreg_lowpart_offset (outermode, innermode); 6288 6289 /* SUBREG is normal, but may not be lowpart; return OUTER_OFFSET 6290 plus the normal lowpart offset for MIDDLEMODE and INNERMODE. */ 6291 return outer_offset + subreg_lowpart_offset (middlemode, innermode); 6292 } 6293 6294 /* Assign hard reg targets for the pseudo-registers we must reload 6295 into hard regs for this insn. 6296 Also output the instructions to copy them in and out of the hard regs. 6297 6298 For machines with register classes, we are responsible for 6299 finding a reload reg in the proper class. */ 6300 6301 static void 6302 choose_reload_regs (class insn_chain *chain) 6303 { 6304 rtx_insn *insn = chain->insn; 6305 int i, j; 6306 unsigned int max_group_size = 1; 6307 enum reg_class group_class = NO_REGS; 6308 int pass, win, inheritance; 6309 6310 rtx save_reload_reg_rtx[MAX_RELOADS]; 6311 6312 /* In order to be certain of getting the registers we need, 6313 we must sort the reloads into order of increasing register class. 6314 Then our grabbing of reload registers will parallel the process 6315 that provided the reload registers. 6316 6317 Also note whether any of the reloads wants a consecutive group of regs. 6318 If so, record the maximum size of the group desired and what 6319 register class contains all the groups needed by this insn. */ 6320 6321 for (j = 0; j < n_reloads; j++) 6322 { 6323 reload_order[j] = j; 6324 if (rld[j].reg_rtx != NULL_RTX) 6325 { 6326 gcc_assert (REG_P (rld[j].reg_rtx) 6327 && HARD_REGISTER_P (rld[j].reg_rtx)); 6328 reload_spill_index[j] = REGNO (rld[j].reg_rtx); 6329 } 6330 else 6331 reload_spill_index[j] = -1; 6332 6333 if (rld[j].nregs > 1) 6334 { 6335 max_group_size = MAX (rld[j].nregs, max_group_size); 6336 group_class 6337 = reg_class_superunion[(int) rld[j].rclass][(int) group_class]; 6338 } 6339 6340 save_reload_reg_rtx[j] = rld[j].reg_rtx; 6341 } 6342 6343 if (n_reloads > 1) 6344 qsort (reload_order, n_reloads, sizeof (short), reload_reg_class_lower); 6345 6346 /* If -O, try first with inheritance, then turning it off. 6347 If not -O, don't do inheritance. 6348 Using inheritance when not optimizing leads to paradoxes 6349 with fp on the 68k: fp numbers (not NaNs) fail to be equal to themselves 6350 because one side of the comparison might be inherited. */ 6351 win = 0; 6352 for (inheritance = optimize > 0; inheritance >= 0; inheritance--) 6353 { 6354 choose_reload_regs_init (chain, save_reload_reg_rtx); 6355 6356 /* Process the reloads in order of preference just found. 6357 Beyond this point, subregs can be found in reload_reg_rtx. 6358 6359 This used to look for an existing reloaded home for all of the 6360 reloads, and only then perform any new reloads. But that could lose 6361 if the reloads were done out of reg-class order because a later 6362 reload with a looser constraint might have an old home in a register 6363 needed by an earlier reload with a tighter constraint. 6364 6365 To solve this, we make two passes over the reloads, in the order 6366 described above. In the first pass we try to inherit a reload 6367 from a previous insn. If there is a later reload that needs a 6368 class that is a proper subset of the class being processed, we must 6369 also allocate a spill register during the first pass. 6370 6371 Then make a second pass over the reloads to allocate any reloads 6372 that haven't been given registers yet. */ 6373 6374 for (j = 0; j < n_reloads; j++) 6375 { 6376 int r = reload_order[j]; 6377 rtx search_equiv = NULL_RTX; 6378 6379 /* Ignore reloads that got marked inoperative. */ 6380 if (rld[r].out == 0 && rld[r].in == 0 6381 && ! rld[r].secondary_p) 6382 continue; 6383 6384 /* If find_reloads chose to use reload_in or reload_out as a reload 6385 register, we don't need to chose one. Otherwise, try even if it 6386 found one since we might save an insn if we find the value lying 6387 around. 6388 Try also when reload_in is a pseudo without a hard reg. */ 6389 if (rld[r].in != 0 && rld[r].reg_rtx != 0 6390 && (rtx_equal_p (rld[r].in, rld[r].reg_rtx) 6391 || (rtx_equal_p (rld[r].out, rld[r].reg_rtx) 6392 && !MEM_P (rld[r].in) 6393 && true_regnum (rld[r].in) < FIRST_PSEUDO_REGISTER))) 6394 continue; 6395 6396 #if 0 /* No longer needed for correct operation. 6397 It might give better code, or might not; worth an experiment? */ 6398 /* If this is an optional reload, we can't inherit from earlier insns 6399 until we are sure that any non-optional reloads have been allocated. 6400 The following code takes advantage of the fact that optional reloads 6401 are at the end of reload_order. */ 6402 if (rld[r].optional != 0) 6403 for (i = 0; i < j; i++) 6404 if ((rld[reload_order[i]].out != 0 6405 || rld[reload_order[i]].in != 0 6406 || rld[reload_order[i]].secondary_p) 6407 && ! rld[reload_order[i]].optional 6408 && rld[reload_order[i]].reg_rtx == 0) 6409 allocate_reload_reg (chain, reload_order[i], 0); 6410 #endif 6411 6412 /* First see if this pseudo is already available as reloaded 6413 for a previous insn. We cannot try to inherit for reloads 6414 that are smaller than the maximum number of registers needed 6415 for groups unless the register we would allocate cannot be used 6416 for the groups. 6417 6418 We could check here to see if this is a secondary reload for 6419 an object that is already in a register of the desired class. 6420 This would avoid the need for the secondary reload register. 6421 But this is complex because we can't easily determine what 6422 objects might want to be loaded via this reload. So let a 6423 register be allocated here. In `emit_reload_insns' we suppress 6424 one of the loads in the case described above. */ 6425 6426 if (inheritance) 6427 { 6428 poly_int64 byte = 0; 6429 int regno = -1; 6430 machine_mode mode = VOIDmode; 6431 rtx subreg = NULL_RTX; 6432 6433 if (rld[r].in == 0) 6434 ; 6435 else if (REG_P (rld[r].in)) 6436 { 6437 regno = REGNO (rld[r].in); 6438 mode = GET_MODE (rld[r].in); 6439 } 6440 else if (REG_P (rld[r].in_reg)) 6441 { 6442 regno = REGNO (rld[r].in_reg); 6443 mode = GET_MODE (rld[r].in_reg); 6444 } 6445 else if (GET_CODE (rld[r].in_reg) == SUBREG 6446 && REG_P (SUBREG_REG (rld[r].in_reg))) 6447 { 6448 regno = REGNO (SUBREG_REG (rld[r].in_reg)); 6449 if (regno < FIRST_PSEUDO_REGISTER) 6450 regno = subreg_regno (rld[r].in_reg); 6451 else 6452 { 6453 subreg = rld[r].in_reg; 6454 byte = SUBREG_BYTE (subreg); 6455 } 6456 mode = GET_MODE (rld[r].in_reg); 6457 } 6458 #if AUTO_INC_DEC 6459 else if (GET_RTX_CLASS (GET_CODE (rld[r].in_reg)) == RTX_AUTOINC 6460 && REG_P (XEXP (rld[r].in_reg, 0))) 6461 { 6462 regno = REGNO (XEXP (rld[r].in_reg, 0)); 6463 mode = GET_MODE (XEXP (rld[r].in_reg, 0)); 6464 rld[r].out = rld[r].in; 6465 } 6466 #endif 6467 #if 0 6468 /* This won't work, since REGNO can be a pseudo reg number. 6469 Also, it takes much more hair to keep track of all the things 6470 that can invalidate an inherited reload of part of a pseudoreg. */ 6471 else if (GET_CODE (rld[r].in) == SUBREG 6472 && REG_P (SUBREG_REG (rld[r].in))) 6473 regno = subreg_regno (rld[r].in); 6474 #endif 6475 6476 if (regno >= 0 6477 && reg_last_reload_reg[regno] != 0 6478 && (known_ge 6479 (GET_MODE_SIZE (GET_MODE (reg_last_reload_reg[regno])), 6480 GET_MODE_SIZE (mode) + byte)) 6481 /* Verify that the register it's in can be used in 6482 mode MODE. */ 6483 && (REG_CAN_CHANGE_MODE_P 6484 (REGNO (reg_last_reload_reg[regno]), 6485 GET_MODE (reg_last_reload_reg[regno]), 6486 mode))) 6487 { 6488 enum reg_class rclass = rld[r].rclass, last_class; 6489 rtx last_reg = reg_last_reload_reg[regno]; 6490 6491 i = REGNO (last_reg); 6492 byte = compute_reload_subreg_offset (mode, 6493 subreg, 6494 GET_MODE (last_reg)); 6495 i += subreg_regno_offset (i, GET_MODE (last_reg), byte, mode); 6496 last_class = REGNO_REG_CLASS (i); 6497 6498 if (reg_reloaded_contents[i] == regno 6499 && TEST_HARD_REG_BIT (reg_reloaded_valid, i) 6500 && targetm.hard_regno_mode_ok (i, rld[r].mode) 6501 && (TEST_HARD_REG_BIT (reg_class_contents[(int) rclass], i) 6502 /* Even if we can't use this register as a reload 6503 register, we might use it for reload_override_in, 6504 if copying it to the desired class is cheap 6505 enough. */ 6506 || ((register_move_cost (mode, last_class, rclass) 6507 < memory_move_cost (mode, rclass, true)) 6508 && (secondary_reload_class (1, rclass, mode, 6509 last_reg) 6510 == NO_REGS) 6511 && !(targetm.secondary_memory_needed 6512 (mode, last_class, rclass)))) 6513 && (rld[r].nregs == max_group_size 6514 || ! TEST_HARD_REG_BIT (reg_class_contents[(int) group_class], 6515 i)) 6516 && free_for_value_p (i, rld[r].mode, rld[r].opnum, 6517 rld[r].when_needed, rld[r].in, 6518 const0_rtx, r, 1)) 6519 { 6520 /* If a group is needed, verify that all the subsequent 6521 registers still have their values intact. */ 6522 int nr = hard_regno_nregs (i, rld[r].mode); 6523 int k; 6524 6525 for (k = 1; k < nr; k++) 6526 if (reg_reloaded_contents[i + k] != regno 6527 || ! TEST_HARD_REG_BIT (reg_reloaded_valid, i + k)) 6528 break; 6529 6530 if (k == nr) 6531 { 6532 int i1; 6533 int bad_for_class; 6534 6535 last_reg = (GET_MODE (last_reg) == mode 6536 ? last_reg : gen_rtx_REG (mode, i)); 6537 6538 bad_for_class = 0; 6539 for (k = 0; k < nr; k++) 6540 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass], 6541 i+k); 6542 6543 /* We found a register that contains the 6544 value we need. If this register is the 6545 same as an `earlyclobber' operand of the 6546 current insn, just mark it as a place to 6547 reload from since we can't use it as the 6548 reload register itself. */ 6549 6550 for (i1 = 0; i1 < n_earlyclobbers; i1++) 6551 if (reg_overlap_mentioned_for_reload_p 6552 (reg_last_reload_reg[regno], 6553 reload_earlyclobbers[i1])) 6554 break; 6555 6556 if (i1 != n_earlyclobbers 6557 || ! (free_for_value_p (i, rld[r].mode, 6558 rld[r].opnum, 6559 rld[r].when_needed, rld[r].in, 6560 rld[r].out, r, 1)) 6561 /* Don't use it if we'd clobber a pseudo reg. */ 6562 || (TEST_HARD_REG_BIT (reg_used_in_insn, i) 6563 && rld[r].out 6564 && ! TEST_HARD_REG_BIT (reg_reloaded_dead, i)) 6565 /* Don't clobber the frame pointer. */ 6566 || (i == HARD_FRAME_POINTER_REGNUM 6567 && frame_pointer_needed 6568 && rld[r].out) 6569 /* Don't really use the inherited spill reg 6570 if we need it wider than we've got it. */ 6571 || paradoxical_subreg_p (rld[r].mode, mode) 6572 || bad_for_class 6573 6574 /* If find_reloads chose reload_out as reload 6575 register, stay with it - that leaves the 6576 inherited register for subsequent reloads. */ 6577 || (rld[r].out && rld[r].reg_rtx 6578 && rtx_equal_p (rld[r].out, rld[r].reg_rtx))) 6579 { 6580 if (! rld[r].optional) 6581 { 6582 reload_override_in[r] = last_reg; 6583 reload_inheritance_insn[r] 6584 = reg_reloaded_insn[i]; 6585 } 6586 } 6587 else 6588 { 6589 int k; 6590 /* We can use this as a reload reg. */ 6591 /* Mark the register as in use for this part of 6592 the insn. */ 6593 mark_reload_reg_in_use (i, 6594 rld[r].opnum, 6595 rld[r].when_needed, 6596 rld[r].mode); 6597 rld[r].reg_rtx = last_reg; 6598 reload_inherited[r] = 1; 6599 reload_inheritance_insn[r] 6600 = reg_reloaded_insn[i]; 6601 reload_spill_index[r] = i; 6602 for (k = 0; k < nr; k++) 6603 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 6604 i + k); 6605 } 6606 } 6607 } 6608 } 6609 } 6610 6611 /* Here's another way to see if the value is already lying around. */ 6612 if (inheritance 6613 && rld[r].in != 0 6614 && ! reload_inherited[r] 6615 && rld[r].out == 0 6616 && (CONSTANT_P (rld[r].in) 6617 || GET_CODE (rld[r].in) == PLUS 6618 || REG_P (rld[r].in) 6619 || MEM_P (rld[r].in)) 6620 && (rld[r].nregs == max_group_size 6621 || ! reg_classes_intersect_p (rld[r].rclass, group_class))) 6622 search_equiv = rld[r].in; 6623 6624 if (search_equiv) 6625 { 6626 rtx equiv 6627 = find_equiv_reg (search_equiv, insn, rld[r].rclass, 6628 -1, NULL, 0, rld[r].mode); 6629 int regno = 0; 6630 6631 if (equiv != 0) 6632 { 6633 if (REG_P (equiv)) 6634 regno = REGNO (equiv); 6635 else 6636 { 6637 /* This must be a SUBREG of a hard register. 6638 Make a new REG since this might be used in an 6639 address and not all machines support SUBREGs 6640 there. */ 6641 gcc_assert (GET_CODE (equiv) == SUBREG); 6642 regno = subreg_regno (equiv); 6643 equiv = gen_rtx_REG (rld[r].mode, regno); 6644 /* If we choose EQUIV as the reload register, but the 6645 loop below decides to cancel the inheritance, we'll 6646 end up reloading EQUIV in rld[r].mode, not the mode 6647 it had originally. That isn't safe when EQUIV isn't 6648 available as a spill register since its value might 6649 still be live at this point. */ 6650 for (i = regno; i < regno + (int) rld[r].nregs; i++) 6651 if (TEST_HARD_REG_BIT (reload_reg_unavailable, i)) 6652 equiv = 0; 6653 } 6654 } 6655 6656 /* If we found a spill reg, reject it unless it is free 6657 and of the desired class. */ 6658 if (equiv != 0) 6659 { 6660 int regs_used = 0; 6661 int bad_for_class = 0; 6662 int max_regno = regno + rld[r].nregs; 6663 6664 for (i = regno; i < max_regno; i++) 6665 { 6666 regs_used |= TEST_HARD_REG_BIT (reload_reg_used_at_all, 6667 i); 6668 bad_for_class |= ! TEST_HARD_REG_BIT (reg_class_contents[(int) rld[r].rclass], 6669 i); 6670 } 6671 6672 if ((regs_used 6673 && ! free_for_value_p (regno, rld[r].mode, 6674 rld[r].opnum, rld[r].when_needed, 6675 rld[r].in, rld[r].out, r, 1)) 6676 || bad_for_class) 6677 equiv = 0; 6678 } 6679 6680 if (equiv != 0 6681 && !targetm.hard_regno_mode_ok (regno, rld[r].mode)) 6682 equiv = 0; 6683 6684 /* We found a register that contains the value we need. 6685 If this register is the same as an `earlyclobber' operand 6686 of the current insn, just mark it as a place to reload from 6687 since we can't use it as the reload register itself. */ 6688 6689 if (equiv != 0) 6690 for (i = 0; i < n_earlyclobbers; i++) 6691 if (reg_overlap_mentioned_for_reload_p (equiv, 6692 reload_earlyclobbers[i])) 6693 { 6694 if (! rld[r].optional) 6695 reload_override_in[r] = equiv; 6696 equiv = 0; 6697 break; 6698 } 6699 6700 /* If the equiv register we have found is explicitly clobbered 6701 in the current insn, it depends on the reload type if we 6702 can use it, use it for reload_override_in, or not at all. 6703 In particular, we then can't use EQUIV for a 6704 RELOAD_FOR_OUTPUT_ADDRESS reload. */ 6705 6706 if (equiv != 0) 6707 { 6708 if (regno_clobbered_p (regno, insn, rld[r].mode, 2)) 6709 switch (rld[r].when_needed) 6710 { 6711 case RELOAD_FOR_OTHER_ADDRESS: 6712 case RELOAD_FOR_INPADDR_ADDRESS: 6713 case RELOAD_FOR_INPUT_ADDRESS: 6714 case RELOAD_FOR_OPADDR_ADDR: 6715 break; 6716 case RELOAD_OTHER: 6717 case RELOAD_FOR_INPUT: 6718 case RELOAD_FOR_OPERAND_ADDRESS: 6719 if (! rld[r].optional) 6720 reload_override_in[r] = equiv; 6721 /* Fall through. */ 6722 default: 6723 equiv = 0; 6724 break; 6725 } 6726 else if (regno_clobbered_p (regno, insn, rld[r].mode, 1)) 6727 switch (rld[r].when_needed) 6728 { 6729 case RELOAD_FOR_OTHER_ADDRESS: 6730 case RELOAD_FOR_INPADDR_ADDRESS: 6731 case RELOAD_FOR_INPUT_ADDRESS: 6732 case RELOAD_FOR_OPADDR_ADDR: 6733 case RELOAD_FOR_OPERAND_ADDRESS: 6734 case RELOAD_FOR_INPUT: 6735 break; 6736 case RELOAD_OTHER: 6737 if (! rld[r].optional) 6738 reload_override_in[r] = equiv; 6739 /* Fall through. */ 6740 default: 6741 equiv = 0; 6742 break; 6743 } 6744 } 6745 6746 /* If we found an equivalent reg, say no code need be generated 6747 to load it, and use it as our reload reg. */ 6748 if (equiv != 0 6749 && (regno != HARD_FRAME_POINTER_REGNUM 6750 || !frame_pointer_needed)) 6751 { 6752 int nr = hard_regno_nregs (regno, rld[r].mode); 6753 int k; 6754 rld[r].reg_rtx = equiv; 6755 reload_spill_index[r] = regno; 6756 reload_inherited[r] = 1; 6757 6758 /* If reg_reloaded_valid is not set for this register, 6759 there might be a stale spill_reg_store lying around. 6760 We must clear it, since otherwise emit_reload_insns 6761 might delete the store. */ 6762 if (! TEST_HARD_REG_BIT (reg_reloaded_valid, regno)) 6763 spill_reg_store[regno] = NULL; 6764 /* If any of the hard registers in EQUIV are spill 6765 registers, mark them as in use for this insn. */ 6766 for (k = 0; k < nr; k++) 6767 { 6768 i = spill_reg_order[regno + k]; 6769 if (i >= 0) 6770 { 6771 mark_reload_reg_in_use (regno, rld[r].opnum, 6772 rld[r].when_needed, 6773 rld[r].mode); 6774 SET_HARD_REG_BIT (reload_reg_used_for_inherit, 6775 regno + k); 6776 } 6777 } 6778 } 6779 } 6780 6781 /* If we found a register to use already, or if this is an optional 6782 reload, we are done. */ 6783 if (rld[r].reg_rtx != 0 || rld[r].optional != 0) 6784 continue; 6785 6786 #if 0 6787 /* No longer needed for correct operation. Might or might 6788 not give better code on the average. Want to experiment? */ 6789 6790 /* See if there is a later reload that has a class different from our 6791 class that intersects our class or that requires less register 6792 than our reload. If so, we must allocate a register to this 6793 reload now, since that reload might inherit a previous reload 6794 and take the only available register in our class. Don't do this 6795 for optional reloads since they will force all previous reloads 6796 to be allocated. Also don't do this for reloads that have been 6797 turned off. */ 6798 6799 for (i = j + 1; i < n_reloads; i++) 6800 { 6801 int s = reload_order[i]; 6802 6803 if ((rld[s].in == 0 && rld[s].out == 0 6804 && ! rld[s].secondary_p) 6805 || rld[s].optional) 6806 continue; 6807 6808 if ((rld[s].rclass != rld[r].rclass 6809 && reg_classes_intersect_p (rld[r].rclass, 6810 rld[s].rclass)) 6811 || rld[s].nregs < rld[r].nregs) 6812 break; 6813 } 6814 6815 if (i == n_reloads) 6816 continue; 6817 6818 allocate_reload_reg (chain, r, j == n_reloads - 1); 6819 #endif 6820 } 6821 6822 /* Now allocate reload registers for anything non-optional that 6823 didn't get one yet. */ 6824 for (j = 0; j < n_reloads; j++) 6825 { 6826 int r = reload_order[j]; 6827 6828 /* Ignore reloads that got marked inoperative. */ 6829 if (rld[r].out == 0 && rld[r].in == 0 && ! rld[r].secondary_p) 6830 continue; 6831 6832 /* Skip reloads that already have a register allocated or are 6833 optional. */ 6834 if (rld[r].reg_rtx != 0 || rld[r].optional) 6835 continue; 6836 6837 if (! allocate_reload_reg (chain, r, j == n_reloads - 1)) 6838 break; 6839 } 6840 6841 /* If that loop got all the way, we have won. */ 6842 if (j == n_reloads) 6843 { 6844 win = 1; 6845 break; 6846 } 6847 6848 /* Loop around and try without any inheritance. */ 6849 } 6850 6851 if (! win) 6852 { 6853 /* First undo everything done by the failed attempt 6854 to allocate with inheritance. */ 6855 choose_reload_regs_init (chain, save_reload_reg_rtx); 6856 6857 /* Some sanity tests to verify that the reloads found in the first 6858 pass are identical to the ones we have now. */ 6859 gcc_assert (chain->n_reloads == n_reloads); 6860 6861 for (i = 0; i < n_reloads; i++) 6862 { 6863 if (chain->rld[i].regno < 0 || chain->rld[i].reg_rtx != 0) 6864 continue; 6865 gcc_assert (chain->rld[i].when_needed == rld[i].when_needed); 6866 for (j = 0; j < n_spills; j++) 6867 if (spill_regs[j] == chain->rld[i].regno) 6868 if (! set_reload_reg (j, i)) 6869 failed_reload (chain->insn, i); 6870 } 6871 } 6872 6873 /* If we thought we could inherit a reload, because it seemed that 6874 nothing else wanted the same reload register earlier in the insn, 6875 verify that assumption, now that all reloads have been assigned. 6876 Likewise for reloads where reload_override_in has been set. */ 6877 6878 /* If doing expensive optimizations, do one preliminary pass that doesn't 6879 cancel any inheritance, but removes reloads that have been needed only 6880 for reloads that we know can be inherited. */ 6881 for (pass = flag_expensive_optimizations; pass >= 0; pass--) 6882 { 6883 for (j = 0; j < n_reloads; j++) 6884 { 6885 int r = reload_order[j]; 6886 rtx check_reg; 6887 rtx tem; 6888 if (reload_inherited[r] && rld[r].reg_rtx) 6889 check_reg = rld[r].reg_rtx; 6890 else if (reload_override_in[r] 6891 && (REG_P (reload_override_in[r]) 6892 || GET_CODE (reload_override_in[r]) == SUBREG)) 6893 check_reg = reload_override_in[r]; 6894 else 6895 continue; 6896 if (! free_for_value_p (true_regnum (check_reg), rld[r].mode, 6897 rld[r].opnum, rld[r].when_needed, rld[r].in, 6898 (reload_inherited[r] 6899 ? rld[r].out : const0_rtx), 6900 r, 1)) 6901 { 6902 if (pass) 6903 continue; 6904 reload_inherited[r] = 0; 6905 reload_override_in[r] = 0; 6906 } 6907 /* If we can inherit a RELOAD_FOR_INPUT, or can use a 6908 reload_override_in, then we do not need its related 6909 RELOAD_FOR_INPUT_ADDRESS / RELOAD_FOR_INPADDR_ADDRESS reloads; 6910 likewise for other reload types. 6911 We handle this by removing a reload when its only replacement 6912 is mentioned in reload_in of the reload we are going to inherit. 6913 A special case are auto_inc expressions; even if the input is 6914 inherited, we still need the address for the output. We can 6915 recognize them because they have RELOAD_OUT set to RELOAD_IN. 6916 If we succeeded removing some reload and we are doing a preliminary 6917 pass just to remove such reloads, make another pass, since the 6918 removal of one reload might allow us to inherit another one. */ 6919 else if (rld[r].in 6920 && rld[r].out != rld[r].in 6921 && remove_address_replacements (rld[r].in)) 6922 { 6923 if (pass) 6924 pass = 2; 6925 } 6926 /* If we needed a memory location for the reload, we also have to 6927 remove its related reloads. */ 6928 else if (rld[r].in 6929 && rld[r].out != rld[r].in 6930 && (tem = replaced_subreg (rld[r].in), REG_P (tem)) 6931 && REGNO (tem) < FIRST_PSEUDO_REGISTER 6932 && (targetm.secondary_memory_needed 6933 (rld[r].inmode, REGNO_REG_CLASS (REGNO (tem)), 6934 rld[r].rclass)) 6935 && remove_address_replacements 6936 (get_secondary_mem (tem, rld[r].inmode, rld[r].opnum, 6937 rld[r].when_needed))) 6938 { 6939 if (pass) 6940 pass = 2; 6941 } 6942 } 6943 } 6944 6945 /* Now that reload_override_in is known valid, 6946 actually override reload_in. */ 6947 for (j = 0; j < n_reloads; j++) 6948 if (reload_override_in[j]) 6949 rld[j].in = reload_override_in[j]; 6950 6951 /* If this reload won't be done because it has been canceled or is 6952 optional and not inherited, clear reload_reg_rtx so other 6953 routines (such as subst_reloads) don't get confused. */ 6954 for (j = 0; j < n_reloads; j++) 6955 if (rld[j].reg_rtx != 0 6956 && ((rld[j].optional && ! reload_inherited[j]) 6957 || (rld[j].in == 0 && rld[j].out == 0 6958 && ! rld[j].secondary_p))) 6959 { 6960 int regno = true_regnum (rld[j].reg_rtx); 6961 6962 if (spill_reg_order[regno] >= 0) 6963 clear_reload_reg_in_use (regno, rld[j].opnum, 6964 rld[j].when_needed, rld[j].mode); 6965 rld[j].reg_rtx = 0; 6966 reload_spill_index[j] = -1; 6967 } 6968 6969 /* Record which pseudos and which spill regs have output reloads. */ 6970 for (j = 0; j < n_reloads; j++) 6971 { 6972 int r = reload_order[j]; 6973 6974 i = reload_spill_index[r]; 6975 6976 /* I is nonneg if this reload uses a register. 6977 If rld[r].reg_rtx is 0, this is an optional reload 6978 that we opted to ignore. */ 6979 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg) 6980 && rld[r].reg_rtx != 0) 6981 { 6982 int nregno = REGNO (rld[r].out_reg); 6983 int nr = 1; 6984 6985 if (nregno < FIRST_PSEUDO_REGISTER) 6986 nr = hard_regno_nregs (nregno, rld[r].mode); 6987 6988 while (--nr >= 0) 6989 SET_REGNO_REG_SET (®_has_output_reload, 6990 nregno + nr); 6991 6992 if (i >= 0) 6993 add_to_hard_reg_set (®_is_output_reload, rld[r].mode, i); 6994 6995 gcc_assert (rld[r].when_needed == RELOAD_OTHER 6996 || rld[r].when_needed == RELOAD_FOR_OUTPUT 6997 || rld[r].when_needed == RELOAD_FOR_INSN); 6998 } 6999 } 7000 } 7001 7002 /* Deallocate the reload register for reload R. This is called from 7003 remove_address_replacements. */ 7004 7005 void 7006 deallocate_reload_reg (int r) 7007 { 7008 int regno; 7009 7010 if (! rld[r].reg_rtx) 7011 return; 7012 regno = true_regnum (rld[r].reg_rtx); 7013 rld[r].reg_rtx = 0; 7014 if (spill_reg_order[regno] >= 0) 7015 clear_reload_reg_in_use (regno, rld[r].opnum, rld[r].when_needed, 7016 rld[r].mode); 7017 reload_spill_index[r] = -1; 7018 } 7019 7020 /* These arrays are filled by emit_reload_insns and its subroutines. */ 7021 static rtx_insn *input_reload_insns[MAX_RECOG_OPERANDS]; 7022 static rtx_insn *other_input_address_reload_insns = 0; 7023 static rtx_insn *other_input_reload_insns = 0; 7024 static rtx_insn *input_address_reload_insns[MAX_RECOG_OPERANDS]; 7025 static rtx_insn *inpaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 7026 static rtx_insn *output_reload_insns[MAX_RECOG_OPERANDS]; 7027 static rtx_insn *output_address_reload_insns[MAX_RECOG_OPERANDS]; 7028 static rtx_insn *outaddr_address_reload_insns[MAX_RECOG_OPERANDS]; 7029 static rtx_insn *operand_reload_insns = 0; 7030 static rtx_insn *other_operand_reload_insns = 0; 7031 static rtx_insn *other_output_reload_insns[MAX_RECOG_OPERANDS]; 7032 7033 /* Values to be put in spill_reg_store are put here first. Instructions 7034 must only be placed here if the associated reload register reaches 7035 the end of the instruction's reload sequence. */ 7036 static rtx_insn *new_spill_reg_store[FIRST_PSEUDO_REGISTER]; 7037 static HARD_REG_SET reg_reloaded_died; 7038 7039 /* Check if *RELOAD_REG is suitable as an intermediate or scratch register 7040 of class NEW_CLASS with mode NEW_MODE. Or alternatively, if alt_reload_reg 7041 is nonzero, if that is suitable. On success, change *RELOAD_REG to the 7042 adjusted register, and return true. Otherwise, return false. */ 7043 static bool 7044 reload_adjust_reg_for_temp (rtx *reload_reg, rtx alt_reload_reg, 7045 enum reg_class new_class, 7046 machine_mode new_mode) 7047 7048 { 7049 rtx reg; 7050 7051 for (reg = *reload_reg; reg; reg = alt_reload_reg, alt_reload_reg = 0) 7052 { 7053 unsigned regno = REGNO (reg); 7054 7055 if (!TEST_HARD_REG_BIT (reg_class_contents[(int) new_class], regno)) 7056 continue; 7057 if (GET_MODE (reg) != new_mode) 7058 { 7059 if (!targetm.hard_regno_mode_ok (regno, new_mode)) 7060 continue; 7061 if (hard_regno_nregs (regno, new_mode) > REG_NREGS (reg)) 7062 continue; 7063 reg = reload_adjust_reg_for_mode (reg, new_mode); 7064 } 7065 *reload_reg = reg; 7066 return true; 7067 } 7068 return false; 7069 } 7070 7071 /* Check if *RELOAD_REG is suitable as a scratch register for the reload 7072 pattern with insn_code ICODE, or alternatively, if alt_reload_reg is 7073 nonzero, if that is suitable. On success, change *RELOAD_REG to the 7074 adjusted register, and return true. Otherwise, return false. */ 7075 static bool 7076 reload_adjust_reg_for_icode (rtx *reload_reg, rtx alt_reload_reg, 7077 enum insn_code icode) 7078 7079 { 7080 enum reg_class new_class = scratch_reload_class (icode); 7081 machine_mode new_mode = insn_data[(int) icode].operand[2].mode; 7082 7083 return reload_adjust_reg_for_temp (reload_reg, alt_reload_reg, 7084 new_class, new_mode); 7085 } 7086 7087 /* Generate insns to perform reload RL, which is for the insn in CHAIN and 7088 has the number J. OLD contains the value to be used as input. */ 7089 7090 static void 7091 emit_input_reload_insns (class insn_chain *chain, struct reload *rl, 7092 rtx old, int j) 7093 { 7094 rtx_insn *insn = chain->insn; 7095 rtx reloadreg; 7096 rtx oldequiv_reg = 0; 7097 rtx oldequiv = 0; 7098 int special = 0; 7099 machine_mode mode; 7100 rtx_insn **where; 7101 7102 /* delete_output_reload is only invoked properly if old contains 7103 the original pseudo register. Since this is replaced with a 7104 hard reg when RELOAD_OVERRIDE_IN is set, see if we can 7105 find the pseudo in RELOAD_IN_REG. This is also used to 7106 determine whether a secondary reload is needed. */ 7107 if (reload_override_in[j] 7108 && (REG_P (rl->in_reg) 7109 || (GET_CODE (rl->in_reg) == SUBREG 7110 && REG_P (SUBREG_REG (rl->in_reg))))) 7111 { 7112 oldequiv = old; 7113 old = rl->in_reg; 7114 } 7115 if (oldequiv == 0) 7116 oldequiv = old; 7117 else if (REG_P (oldequiv)) 7118 oldequiv_reg = oldequiv; 7119 else if (GET_CODE (oldequiv) == SUBREG) 7120 oldequiv_reg = SUBREG_REG (oldequiv); 7121 7122 reloadreg = reload_reg_rtx_for_input[j]; 7123 mode = GET_MODE (reloadreg); 7124 7125 /* If we are reloading from a register that was recently stored in 7126 with an output-reload, see if we can prove there was 7127 actually no need to store the old value in it. */ 7128 7129 if (optimize && REG_P (oldequiv) 7130 && REGNO (oldequiv) < FIRST_PSEUDO_REGISTER 7131 && spill_reg_store[REGNO (oldequiv)] 7132 && REG_P (old) 7133 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (oldequiv)]) 7134 || rtx_equal_p (spill_reg_stored_to[REGNO (oldequiv)], 7135 rl->out_reg))) 7136 delete_output_reload (insn, j, REGNO (oldequiv), reloadreg); 7137 7138 /* Encapsulate OLDEQUIV into the reload mode, then load RELOADREG from 7139 OLDEQUIV. */ 7140 7141 while (GET_CODE (oldequiv) == SUBREG && GET_MODE (oldequiv) != mode) 7142 oldequiv = SUBREG_REG (oldequiv); 7143 if (GET_MODE (oldequiv) != VOIDmode 7144 && mode != GET_MODE (oldequiv)) 7145 oldequiv = gen_lowpart_SUBREG (mode, oldequiv); 7146 7147 /* Switch to the right place to emit the reload insns. */ 7148 switch (rl->when_needed) 7149 { 7150 case RELOAD_OTHER: 7151 where = &other_input_reload_insns; 7152 break; 7153 case RELOAD_FOR_INPUT: 7154 where = &input_reload_insns[rl->opnum]; 7155 break; 7156 case RELOAD_FOR_INPUT_ADDRESS: 7157 where = &input_address_reload_insns[rl->opnum]; 7158 break; 7159 case RELOAD_FOR_INPADDR_ADDRESS: 7160 where = &inpaddr_address_reload_insns[rl->opnum]; 7161 break; 7162 case RELOAD_FOR_OUTPUT_ADDRESS: 7163 where = &output_address_reload_insns[rl->opnum]; 7164 break; 7165 case RELOAD_FOR_OUTADDR_ADDRESS: 7166 where = &outaddr_address_reload_insns[rl->opnum]; 7167 break; 7168 case RELOAD_FOR_OPERAND_ADDRESS: 7169 where = &operand_reload_insns; 7170 break; 7171 case RELOAD_FOR_OPADDR_ADDR: 7172 where = &other_operand_reload_insns; 7173 break; 7174 case RELOAD_FOR_OTHER_ADDRESS: 7175 where = &other_input_address_reload_insns; 7176 break; 7177 default: 7178 gcc_unreachable (); 7179 } 7180 7181 push_to_sequence (*where); 7182 7183 /* Auto-increment addresses must be reloaded in a special way. */ 7184 if (rl->out && ! rl->out_reg) 7185 { 7186 /* We are not going to bother supporting the case where a 7187 incremented register can't be copied directly from 7188 OLDEQUIV since this seems highly unlikely. */ 7189 gcc_assert (rl->secondary_in_reload < 0); 7190 7191 if (reload_inherited[j]) 7192 oldequiv = reloadreg; 7193 7194 old = XEXP (rl->in_reg, 0); 7195 7196 /* Prevent normal processing of this reload. */ 7197 special = 1; 7198 /* Output a special code sequence for this case. */ 7199 inc_for_reload (reloadreg, oldequiv, rl->out, rl->inc); 7200 } 7201 7202 /* If we are reloading a pseudo-register that was set by the previous 7203 insn, see if we can get rid of that pseudo-register entirely 7204 by redirecting the previous insn into our reload register. */ 7205 7206 else if (optimize && REG_P (old) 7207 && REGNO (old) >= FIRST_PSEUDO_REGISTER 7208 && dead_or_set_p (insn, old) 7209 /* This is unsafe if some other reload 7210 uses the same reg first. */ 7211 && ! conflicts_with_override (reloadreg) 7212 && free_for_value_p (REGNO (reloadreg), rl->mode, rl->opnum, 7213 rl->when_needed, old, rl->out, j, 0)) 7214 { 7215 rtx_insn *temp = PREV_INSN (insn); 7216 while (temp && (NOTE_P (temp) || DEBUG_INSN_P (temp))) 7217 temp = PREV_INSN (temp); 7218 if (temp 7219 && NONJUMP_INSN_P (temp) 7220 && GET_CODE (PATTERN (temp)) == SET 7221 && SET_DEST (PATTERN (temp)) == old 7222 /* Make sure we can access insn_operand_constraint. */ 7223 && asm_noperands (PATTERN (temp)) < 0 7224 /* This is unsafe if operand occurs more than once in current 7225 insn. Perhaps some occurrences aren't reloaded. */ 7226 && count_occurrences (PATTERN (insn), old, 0) == 1) 7227 { 7228 rtx old = SET_DEST (PATTERN (temp)); 7229 /* Store into the reload register instead of the pseudo. */ 7230 SET_DEST (PATTERN (temp)) = reloadreg; 7231 7232 /* Verify that resulting insn is valid. 7233 7234 Note that we have replaced the destination of TEMP with 7235 RELOADREG. If TEMP references RELOADREG within an 7236 autoincrement addressing mode, then the resulting insn 7237 is ill-formed and we must reject this optimization. */ 7238 extract_insn (temp); 7239 if (constrain_operands (1, get_enabled_alternatives (temp)) 7240 && (!AUTO_INC_DEC || ! find_reg_note (temp, REG_INC, reloadreg))) 7241 { 7242 /* If the previous insn is an output reload, the source is 7243 a reload register, and its spill_reg_store entry will 7244 contain the previous destination. This is now 7245 invalid. */ 7246 if (REG_P (SET_SRC (PATTERN (temp))) 7247 && REGNO (SET_SRC (PATTERN (temp))) < FIRST_PSEUDO_REGISTER) 7248 { 7249 spill_reg_store[REGNO (SET_SRC (PATTERN (temp)))] = 0; 7250 spill_reg_stored_to[REGNO (SET_SRC (PATTERN (temp)))] = 0; 7251 } 7252 7253 /* If these are the only uses of the pseudo reg, 7254 pretend for GDB it lives in the reload reg we used. */ 7255 if (REG_N_DEATHS (REGNO (old)) == 1 7256 && REG_N_SETS (REGNO (old)) == 1) 7257 { 7258 reg_renumber[REGNO (old)] = REGNO (reloadreg); 7259 if (ira_conflicts_p) 7260 /* Inform IRA about the change. */ 7261 ira_mark_allocation_change (REGNO (old)); 7262 alter_reg (REGNO (old), -1, false); 7263 } 7264 special = 1; 7265 7266 /* Adjust any debug insns between temp and insn. */ 7267 while ((temp = NEXT_INSN (temp)) != insn) 7268 if (DEBUG_BIND_INSN_P (temp)) 7269 INSN_VAR_LOCATION_LOC (temp) 7270 = simplify_replace_rtx (INSN_VAR_LOCATION_LOC (temp), 7271 old, reloadreg); 7272 else 7273 gcc_assert (DEBUG_INSN_P (temp) || NOTE_P (temp)); 7274 } 7275 else 7276 { 7277 SET_DEST (PATTERN (temp)) = old; 7278 } 7279 } 7280 } 7281 7282 /* We can't do that, so output an insn to load RELOADREG. */ 7283 7284 /* If we have a secondary reload, pick up the secondary register 7285 and icode, if any. If OLDEQUIV and OLD are different or 7286 if this is an in-out reload, recompute whether or not we 7287 still need a secondary register and what the icode should 7288 be. If we still need a secondary register and the class or 7289 icode is different, go back to reloading from OLD if using 7290 OLDEQUIV means that we got the wrong type of register. We 7291 cannot have different class or icode due to an in-out reload 7292 because we don't make such reloads when both the input and 7293 output need secondary reload registers. */ 7294 7295 if (! special && rl->secondary_in_reload >= 0) 7296 { 7297 rtx second_reload_reg = 0; 7298 rtx third_reload_reg = 0; 7299 int secondary_reload = rl->secondary_in_reload; 7300 rtx real_oldequiv = oldequiv; 7301 rtx real_old = old; 7302 rtx tmp; 7303 enum insn_code icode; 7304 enum insn_code tertiary_icode = CODE_FOR_nothing; 7305 7306 /* If OLDEQUIV is a pseudo with a MEM, get the real MEM 7307 and similarly for OLD. 7308 See comments in get_secondary_reload in reload.c. */ 7309 /* If it is a pseudo that cannot be replaced with its 7310 equivalent MEM, we must fall back to reload_in, which 7311 will have all the necessary substitutions registered. 7312 Likewise for a pseudo that can't be replaced with its 7313 equivalent constant. 7314 7315 Take extra care for subregs of such pseudos. Note that 7316 we cannot use reg_equiv_mem in this case because it is 7317 not in the right mode. */ 7318 7319 tmp = oldequiv; 7320 if (GET_CODE (tmp) == SUBREG) 7321 tmp = SUBREG_REG (tmp); 7322 if (REG_P (tmp) 7323 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER 7324 && (reg_equiv_memory_loc (REGNO (tmp)) != 0 7325 || reg_equiv_constant (REGNO (tmp)) != 0)) 7326 { 7327 if (! reg_equiv_mem (REGNO (tmp)) 7328 || num_not_at_initial_offset 7329 || GET_CODE (oldequiv) == SUBREG) 7330 real_oldequiv = rl->in; 7331 else 7332 real_oldequiv = reg_equiv_mem (REGNO (tmp)); 7333 } 7334 7335 tmp = old; 7336 if (GET_CODE (tmp) == SUBREG) 7337 tmp = SUBREG_REG (tmp); 7338 if (REG_P (tmp) 7339 && REGNO (tmp) >= FIRST_PSEUDO_REGISTER 7340 && (reg_equiv_memory_loc (REGNO (tmp)) != 0 7341 || reg_equiv_constant (REGNO (tmp)) != 0)) 7342 { 7343 if (! reg_equiv_mem (REGNO (tmp)) 7344 || num_not_at_initial_offset 7345 || GET_CODE (old) == SUBREG) 7346 real_old = rl->in; 7347 else 7348 real_old = reg_equiv_mem (REGNO (tmp)); 7349 } 7350 7351 second_reload_reg = rld[secondary_reload].reg_rtx; 7352 if (rld[secondary_reload].secondary_in_reload >= 0) 7353 { 7354 int tertiary_reload = rld[secondary_reload].secondary_in_reload; 7355 7356 third_reload_reg = rld[tertiary_reload].reg_rtx; 7357 tertiary_icode = rld[secondary_reload].secondary_in_icode; 7358 /* We'd have to add more code for quartary reloads. */ 7359 gcc_assert (rld[tertiary_reload].secondary_in_reload < 0); 7360 } 7361 icode = rl->secondary_in_icode; 7362 7363 if ((old != oldequiv && ! rtx_equal_p (old, oldequiv)) 7364 || (rl->in != 0 && rl->out != 0)) 7365 { 7366 secondary_reload_info sri, sri2; 7367 enum reg_class new_class, new_t_class; 7368 7369 sri.icode = CODE_FOR_nothing; 7370 sri.prev_sri = NULL; 7371 new_class 7372 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv, 7373 rl->rclass, mode, 7374 &sri); 7375 7376 if (new_class == NO_REGS && sri.icode == CODE_FOR_nothing) 7377 second_reload_reg = 0; 7378 else if (new_class == NO_REGS) 7379 { 7380 if (reload_adjust_reg_for_icode (&second_reload_reg, 7381 third_reload_reg, 7382 (enum insn_code) sri.icode)) 7383 { 7384 icode = (enum insn_code) sri.icode; 7385 third_reload_reg = 0; 7386 } 7387 else 7388 { 7389 oldequiv = old; 7390 real_oldequiv = real_old; 7391 } 7392 } 7393 else if (sri.icode != CODE_FOR_nothing) 7394 /* We currently lack a way to express this in reloads. */ 7395 gcc_unreachable (); 7396 else 7397 { 7398 sri2.icode = CODE_FOR_nothing; 7399 sri2.prev_sri = &sri; 7400 new_t_class 7401 = (enum reg_class) targetm.secondary_reload (1, real_oldequiv, 7402 new_class, mode, 7403 &sri); 7404 if (new_t_class == NO_REGS && sri2.icode == CODE_FOR_nothing) 7405 { 7406 if (reload_adjust_reg_for_temp (&second_reload_reg, 7407 third_reload_reg, 7408 new_class, mode)) 7409 { 7410 third_reload_reg = 0; 7411 tertiary_icode = (enum insn_code) sri2.icode; 7412 } 7413 else 7414 { 7415 oldequiv = old; 7416 real_oldequiv = real_old; 7417 } 7418 } 7419 else if (new_t_class == NO_REGS && sri2.icode != CODE_FOR_nothing) 7420 { 7421 rtx intermediate = second_reload_reg; 7422 7423 if (reload_adjust_reg_for_temp (&intermediate, NULL, 7424 new_class, mode) 7425 && reload_adjust_reg_for_icode (&third_reload_reg, NULL, 7426 ((enum insn_code) 7427 sri2.icode))) 7428 { 7429 second_reload_reg = intermediate; 7430 tertiary_icode = (enum insn_code) sri2.icode; 7431 } 7432 else 7433 { 7434 oldequiv = old; 7435 real_oldequiv = real_old; 7436 } 7437 } 7438 else if (new_t_class != NO_REGS && sri2.icode == CODE_FOR_nothing) 7439 { 7440 rtx intermediate = second_reload_reg; 7441 7442 if (reload_adjust_reg_for_temp (&intermediate, NULL, 7443 new_class, mode) 7444 && reload_adjust_reg_for_temp (&third_reload_reg, NULL, 7445 new_t_class, mode)) 7446 { 7447 second_reload_reg = intermediate; 7448 tertiary_icode = (enum insn_code) sri2.icode; 7449 } 7450 else 7451 { 7452 oldequiv = old; 7453 real_oldequiv = real_old; 7454 } 7455 } 7456 else 7457 { 7458 /* This could be handled more intelligently too. */ 7459 oldequiv = old; 7460 real_oldequiv = real_old; 7461 } 7462 } 7463 } 7464 7465 /* If we still need a secondary reload register, check 7466 to see if it is being used as a scratch or intermediate 7467 register and generate code appropriately. If we need 7468 a scratch register, use REAL_OLDEQUIV since the form of 7469 the insn may depend on the actual address if it is 7470 a MEM. */ 7471 7472 if (second_reload_reg) 7473 { 7474 if (icode != CODE_FOR_nothing) 7475 { 7476 /* We'd have to add extra code to handle this case. */ 7477 gcc_assert (!third_reload_reg); 7478 7479 emit_insn (GEN_FCN (icode) (reloadreg, real_oldequiv, 7480 second_reload_reg)); 7481 special = 1; 7482 } 7483 else 7484 { 7485 /* See if we need a scratch register to load the 7486 intermediate register (a tertiary reload). */ 7487 if (tertiary_icode != CODE_FOR_nothing) 7488 { 7489 emit_insn ((GEN_FCN (tertiary_icode) 7490 (second_reload_reg, real_oldequiv, 7491 third_reload_reg))); 7492 } 7493 else if (third_reload_reg) 7494 { 7495 gen_reload (third_reload_reg, real_oldequiv, 7496 rl->opnum, 7497 rl->when_needed); 7498 gen_reload (second_reload_reg, third_reload_reg, 7499 rl->opnum, 7500 rl->when_needed); 7501 } 7502 else 7503 gen_reload (second_reload_reg, real_oldequiv, 7504 rl->opnum, 7505 rl->when_needed); 7506 7507 oldequiv = second_reload_reg; 7508 } 7509 } 7510 } 7511 7512 if (! special && ! rtx_equal_p (reloadreg, oldequiv)) 7513 { 7514 rtx real_oldequiv = oldequiv; 7515 7516 if ((REG_P (oldequiv) 7517 && REGNO (oldequiv) >= FIRST_PSEUDO_REGISTER 7518 && (reg_equiv_memory_loc (REGNO (oldequiv)) != 0 7519 || reg_equiv_constant (REGNO (oldequiv)) != 0)) 7520 || (GET_CODE (oldequiv) == SUBREG 7521 && REG_P (SUBREG_REG (oldequiv)) 7522 && (REGNO (SUBREG_REG (oldequiv)) 7523 >= FIRST_PSEUDO_REGISTER) 7524 && ((reg_equiv_memory_loc (REGNO (SUBREG_REG (oldequiv))) != 0) 7525 || (reg_equiv_constant (REGNO (SUBREG_REG (oldequiv))) != 0))) 7526 || (CONSTANT_P (oldequiv) 7527 && (targetm.preferred_reload_class (oldequiv, 7528 REGNO_REG_CLASS (REGNO (reloadreg))) 7529 == NO_REGS))) 7530 real_oldequiv = rl->in; 7531 gen_reload (reloadreg, real_oldequiv, rl->opnum, 7532 rl->when_needed); 7533 } 7534 7535 if (cfun->can_throw_non_call_exceptions) 7536 copy_reg_eh_region_note_forward (insn, get_insns (), NULL); 7537 7538 /* End this sequence. */ 7539 *where = get_insns (); 7540 end_sequence (); 7541 7542 /* Update reload_override_in so that delete_address_reloads_1 7543 can see the actual register usage. */ 7544 if (oldequiv_reg) 7545 reload_override_in[j] = oldequiv; 7546 } 7547 7548 /* Generate insns to for the output reload RL, which is for the insn described 7549 by CHAIN and has the number J. */ 7550 static void 7551 emit_output_reload_insns (class insn_chain *chain, struct reload *rl, 7552 int j) 7553 { 7554 rtx reloadreg; 7555 rtx_insn *insn = chain->insn; 7556 int special = 0; 7557 rtx old = rl->out; 7558 machine_mode mode; 7559 rtx_insn *p; 7560 rtx rl_reg_rtx; 7561 7562 if (rl->when_needed == RELOAD_OTHER) 7563 start_sequence (); 7564 else 7565 push_to_sequence (output_reload_insns[rl->opnum]); 7566 7567 rl_reg_rtx = reload_reg_rtx_for_output[j]; 7568 mode = GET_MODE (rl_reg_rtx); 7569 7570 reloadreg = rl_reg_rtx; 7571 7572 /* If we need two reload regs, set RELOADREG to the intermediate 7573 one, since it will be stored into OLD. We might need a secondary 7574 register only for an input reload, so check again here. */ 7575 7576 if (rl->secondary_out_reload >= 0) 7577 { 7578 rtx real_old = old; 7579 int secondary_reload = rl->secondary_out_reload; 7580 int tertiary_reload = rld[secondary_reload].secondary_out_reload; 7581 7582 if (REG_P (old) && REGNO (old) >= FIRST_PSEUDO_REGISTER 7583 && reg_equiv_mem (REGNO (old)) != 0) 7584 real_old = reg_equiv_mem (REGNO (old)); 7585 7586 if (secondary_reload_class (0, rl->rclass, mode, real_old) != NO_REGS) 7587 { 7588 rtx second_reloadreg = reloadreg; 7589 reloadreg = rld[secondary_reload].reg_rtx; 7590 7591 /* See if RELOADREG is to be used as a scratch register 7592 or as an intermediate register. */ 7593 if (rl->secondary_out_icode != CODE_FOR_nothing) 7594 { 7595 /* We'd have to add extra code to handle this case. */ 7596 gcc_assert (tertiary_reload < 0); 7597 7598 emit_insn ((GEN_FCN (rl->secondary_out_icode) 7599 (real_old, second_reloadreg, reloadreg))); 7600 special = 1; 7601 } 7602 else 7603 { 7604 /* See if we need both a scratch and intermediate reload 7605 register. */ 7606 7607 enum insn_code tertiary_icode 7608 = rld[secondary_reload].secondary_out_icode; 7609 7610 /* We'd have to add more code for quartary reloads. */ 7611 gcc_assert (tertiary_reload < 0 7612 || rld[tertiary_reload].secondary_out_reload < 0); 7613 7614 if (GET_MODE (reloadreg) != mode) 7615 reloadreg = reload_adjust_reg_for_mode (reloadreg, mode); 7616 7617 if (tertiary_icode != CODE_FOR_nothing) 7618 { 7619 rtx third_reloadreg = rld[tertiary_reload].reg_rtx; 7620 7621 /* Copy primary reload reg to secondary reload reg. 7622 (Note that these have been swapped above, then 7623 secondary reload reg to OLD using our insn.) */ 7624 7625 /* If REAL_OLD is a paradoxical SUBREG, remove it 7626 and try to put the opposite SUBREG on 7627 RELOADREG. */ 7628 strip_paradoxical_subreg (&real_old, &reloadreg); 7629 7630 gen_reload (reloadreg, second_reloadreg, 7631 rl->opnum, rl->when_needed); 7632 emit_insn ((GEN_FCN (tertiary_icode) 7633 (real_old, reloadreg, third_reloadreg))); 7634 special = 1; 7635 } 7636 7637 else 7638 { 7639 /* Copy between the reload regs here and then to 7640 OUT later. */ 7641 7642 gen_reload (reloadreg, second_reloadreg, 7643 rl->opnum, rl->when_needed); 7644 if (tertiary_reload >= 0) 7645 { 7646 rtx third_reloadreg = rld[tertiary_reload].reg_rtx; 7647 7648 gen_reload (third_reloadreg, reloadreg, 7649 rl->opnum, rl->when_needed); 7650 reloadreg = third_reloadreg; 7651 } 7652 } 7653 } 7654 } 7655 } 7656 7657 /* Output the last reload insn. */ 7658 if (! special) 7659 { 7660 rtx set; 7661 7662 /* Don't output the last reload if OLD is not the dest of 7663 INSN and is in the src and is clobbered by INSN. */ 7664 if (! flag_expensive_optimizations 7665 || !REG_P (old) 7666 || !(set = single_set (insn)) 7667 || rtx_equal_p (old, SET_DEST (set)) 7668 || !reg_mentioned_p (old, SET_SRC (set)) 7669 || !((REGNO (old) < FIRST_PSEUDO_REGISTER) 7670 && regno_clobbered_p (REGNO (old), insn, rl->mode, 0))) 7671 gen_reload (old, reloadreg, rl->opnum, 7672 rl->when_needed); 7673 } 7674 7675 /* Look at all insns we emitted, just to be safe. */ 7676 for (p = get_insns (); p; p = NEXT_INSN (p)) 7677 if (INSN_P (p)) 7678 { 7679 rtx pat = PATTERN (p); 7680 7681 /* If this output reload doesn't come from a spill reg, 7682 clear any memory of reloaded copies of the pseudo reg. 7683 If this output reload comes from a spill reg, 7684 reg_has_output_reload will make this do nothing. */ 7685 note_stores (p, forget_old_reloads_1, NULL); 7686 7687 if (reg_mentioned_p (rl_reg_rtx, pat)) 7688 { 7689 rtx set = single_set (insn); 7690 if (reload_spill_index[j] < 0 7691 && set 7692 && SET_SRC (set) == rl_reg_rtx) 7693 { 7694 int src = REGNO (SET_SRC (set)); 7695 7696 reload_spill_index[j] = src; 7697 SET_HARD_REG_BIT (reg_is_output_reload, src); 7698 if (find_regno_note (insn, REG_DEAD, src)) 7699 SET_HARD_REG_BIT (reg_reloaded_died, src); 7700 } 7701 if (HARD_REGISTER_P (rl_reg_rtx)) 7702 { 7703 int s = rl->secondary_out_reload; 7704 set = single_set (p); 7705 /* If this reload copies only to the secondary reload 7706 register, the secondary reload does the actual 7707 store. */ 7708 if (s >= 0 && set == NULL_RTX) 7709 /* We can't tell what function the secondary reload 7710 has and where the actual store to the pseudo is 7711 made; leave new_spill_reg_store alone. */ 7712 ; 7713 else if (s >= 0 7714 && SET_SRC (set) == rl_reg_rtx 7715 && SET_DEST (set) == rld[s].reg_rtx) 7716 { 7717 /* Usually the next instruction will be the 7718 secondary reload insn; if we can confirm 7719 that it is, setting new_spill_reg_store to 7720 that insn will allow an extra optimization. */ 7721 rtx s_reg = rld[s].reg_rtx; 7722 rtx_insn *next = NEXT_INSN (p); 7723 rld[s].out = rl->out; 7724 rld[s].out_reg = rl->out_reg; 7725 set = single_set (next); 7726 if (set && SET_SRC (set) == s_reg 7727 && reload_reg_rtx_reaches_end_p (s_reg, s)) 7728 { 7729 SET_HARD_REG_BIT (reg_is_output_reload, 7730 REGNO (s_reg)); 7731 new_spill_reg_store[REGNO (s_reg)] = next; 7732 } 7733 } 7734 else if (reload_reg_rtx_reaches_end_p (rl_reg_rtx, j)) 7735 new_spill_reg_store[REGNO (rl_reg_rtx)] = p; 7736 } 7737 } 7738 } 7739 7740 if (rl->when_needed == RELOAD_OTHER) 7741 { 7742 emit_insn (other_output_reload_insns[rl->opnum]); 7743 other_output_reload_insns[rl->opnum] = get_insns (); 7744 } 7745 else 7746 output_reload_insns[rl->opnum] = get_insns (); 7747 7748 if (cfun->can_throw_non_call_exceptions) 7749 copy_reg_eh_region_note_forward (insn, get_insns (), NULL); 7750 7751 end_sequence (); 7752 } 7753 7754 /* Do input reloading for reload RL, which is for the insn described by CHAIN 7755 and has the number J. */ 7756 static void 7757 do_input_reload (class insn_chain *chain, struct reload *rl, int j) 7758 { 7759 rtx_insn *insn = chain->insn; 7760 rtx old = (rl->in && MEM_P (rl->in) 7761 ? rl->in_reg : rl->in); 7762 rtx reg_rtx = rl->reg_rtx; 7763 7764 if (old && reg_rtx) 7765 { 7766 machine_mode mode; 7767 7768 /* Determine the mode to reload in. 7769 This is very tricky because we have three to choose from. 7770 There is the mode the insn operand wants (rl->inmode). 7771 There is the mode of the reload register RELOADREG. 7772 There is the intrinsic mode of the operand, which we could find 7773 by stripping some SUBREGs. 7774 It turns out that RELOADREG's mode is irrelevant: 7775 we can change that arbitrarily. 7776 7777 Consider (SUBREG:SI foo:QI) as an operand that must be SImode; 7778 then the reload reg may not support QImode moves, so use SImode. 7779 If foo is in memory due to spilling a pseudo reg, this is safe, 7780 because the QImode value is in the least significant part of a 7781 slot big enough for a SImode. If foo is some other sort of 7782 memory reference, then it is impossible to reload this case, 7783 so previous passes had better make sure this never happens. 7784 7785 Then consider a one-word union which has SImode and one of its 7786 members is a float, being fetched as (SUBREG:SF union:SI). 7787 We must fetch that as SFmode because we could be loading into 7788 a float-only register. In this case OLD's mode is correct. 7789 7790 Consider an immediate integer: it has VOIDmode. Here we need 7791 to get a mode from something else. 7792 7793 In some cases, there is a fourth mode, the operand's 7794 containing mode. If the insn specifies a containing mode for 7795 this operand, it overrides all others. 7796 7797 I am not sure whether the algorithm here is always right, 7798 but it does the right things in those cases. */ 7799 7800 mode = GET_MODE (old); 7801 if (mode == VOIDmode) 7802 mode = rl->inmode; 7803 7804 /* We cannot use gen_lowpart_common since it can do the wrong thing 7805 when REG_RTX has a multi-word mode. Note that REG_RTX must 7806 always be a REG here. */ 7807 if (GET_MODE (reg_rtx) != mode) 7808 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode); 7809 } 7810 reload_reg_rtx_for_input[j] = reg_rtx; 7811 7812 if (old != 0 7813 /* AUTO_INC reloads need to be handled even if inherited. We got an 7814 AUTO_INC reload if reload_out is set but reload_out_reg isn't. */ 7815 && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) 7816 && ! rtx_equal_p (reg_rtx, old) 7817 && reg_rtx != 0) 7818 emit_input_reload_insns (chain, rld + j, old, j); 7819 7820 /* When inheriting a wider reload, we have a MEM in rl->in, 7821 e.g. inheriting a SImode output reload for 7822 (mem:HI (plus:SI (reg:SI 14 fp) (const_int 10))) */ 7823 if (optimize && reload_inherited[j] && rl->in 7824 && MEM_P (rl->in) 7825 && MEM_P (rl->in_reg) 7826 && reload_spill_index[j] >= 0 7827 && TEST_HARD_REG_BIT (reg_reloaded_valid, reload_spill_index[j])) 7828 rl->in = regno_reg_rtx[reg_reloaded_contents[reload_spill_index[j]]]; 7829 7830 /* If we are reloading a register that was recently stored in with an 7831 output-reload, see if we can prove there was 7832 actually no need to store the old value in it. */ 7833 7834 if (optimize 7835 && (reload_inherited[j] || reload_override_in[j]) 7836 && reg_rtx 7837 && REG_P (reg_rtx) 7838 && spill_reg_store[REGNO (reg_rtx)] != 0 7839 #if 0 7840 /* There doesn't seem to be any reason to restrict this to pseudos 7841 and doing so loses in the case where we are copying from a 7842 register of the wrong class. */ 7843 && !HARD_REGISTER_P (spill_reg_stored_to[REGNO (reg_rtx)]) 7844 #endif 7845 /* The insn might have already some references to stackslots 7846 replaced by MEMs, while reload_out_reg still names the 7847 original pseudo. */ 7848 && (dead_or_set_p (insn, spill_reg_stored_to[REGNO (reg_rtx)]) 7849 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg))) 7850 delete_output_reload (insn, j, REGNO (reg_rtx), reg_rtx); 7851 } 7852 7853 /* Do output reloading for reload RL, which is for the insn described by 7854 CHAIN and has the number J. 7855 ??? At some point we need to support handling output reloads of 7856 JUMP_INSNs or insns that set cc0. */ 7857 static void 7858 do_output_reload (class insn_chain *chain, struct reload *rl, int j) 7859 { 7860 rtx note, old; 7861 rtx_insn *insn = chain->insn; 7862 /* If this is an output reload that stores something that is 7863 not loaded in this same reload, see if we can eliminate a previous 7864 store. */ 7865 rtx pseudo = rl->out_reg; 7866 rtx reg_rtx = rl->reg_rtx; 7867 7868 if (rl->out && reg_rtx) 7869 { 7870 machine_mode mode; 7871 7872 /* Determine the mode to reload in. 7873 See comments above (for input reloading). */ 7874 mode = GET_MODE (rl->out); 7875 if (mode == VOIDmode) 7876 { 7877 /* VOIDmode should never happen for an output. */ 7878 if (asm_noperands (PATTERN (insn)) < 0) 7879 /* It's the compiler's fault. */ 7880 fatal_insn ("VOIDmode on an output", insn); 7881 error_for_asm (insn, "output operand is constant in %<asm%>"); 7882 /* Prevent crash--use something we know is valid. */ 7883 mode = word_mode; 7884 rl->out = gen_rtx_REG (mode, REGNO (reg_rtx)); 7885 } 7886 if (GET_MODE (reg_rtx) != mode) 7887 reg_rtx = reload_adjust_reg_for_mode (reg_rtx, mode); 7888 } 7889 reload_reg_rtx_for_output[j] = reg_rtx; 7890 7891 if (pseudo 7892 && optimize 7893 && REG_P (pseudo) 7894 && ! rtx_equal_p (rl->in_reg, pseudo) 7895 && REGNO (pseudo) >= FIRST_PSEUDO_REGISTER 7896 && reg_last_reload_reg[REGNO (pseudo)]) 7897 { 7898 int pseudo_no = REGNO (pseudo); 7899 int last_regno = REGNO (reg_last_reload_reg[pseudo_no]); 7900 7901 /* We don't need to test full validity of last_regno for 7902 inherit here; we only want to know if the store actually 7903 matches the pseudo. */ 7904 if (TEST_HARD_REG_BIT (reg_reloaded_valid, last_regno) 7905 && reg_reloaded_contents[last_regno] == pseudo_no 7906 && spill_reg_store[last_regno] 7907 && rtx_equal_p (pseudo, spill_reg_stored_to[last_regno])) 7908 delete_output_reload (insn, j, last_regno, reg_rtx); 7909 } 7910 7911 old = rl->out_reg; 7912 if (old == 0 7913 || reg_rtx == 0 7914 || rtx_equal_p (old, reg_rtx)) 7915 return; 7916 7917 /* An output operand that dies right away does need a reload, 7918 but need not be copied from it. Show the new location in the 7919 REG_UNUSED note. */ 7920 if ((REG_P (old) || GET_CODE (old) == SCRATCH) 7921 && (note = find_reg_note (insn, REG_UNUSED, old)) != 0) 7922 { 7923 XEXP (note, 0) = reg_rtx; 7924 return; 7925 } 7926 /* Likewise for a SUBREG of an operand that dies. */ 7927 else if (GET_CODE (old) == SUBREG 7928 && REG_P (SUBREG_REG (old)) 7929 && (note = find_reg_note (insn, REG_UNUSED, 7930 SUBREG_REG (old))) != 0) 7931 { 7932 XEXP (note, 0) = gen_lowpart_common (GET_MODE (old), reg_rtx); 7933 return; 7934 } 7935 else if (GET_CODE (old) == SCRATCH) 7936 /* If we aren't optimizing, there won't be a REG_UNUSED note, 7937 but we don't want to make an output reload. */ 7938 return; 7939 7940 /* If is a JUMP_INSN, we can't support output reloads yet. */ 7941 gcc_assert (NONJUMP_INSN_P (insn)); 7942 7943 emit_output_reload_insns (chain, rld + j, j); 7944 } 7945 7946 /* A reload copies values of MODE from register SRC to register DEST. 7947 Return true if it can be treated for inheritance purposes like a 7948 group of reloads, each one reloading a single hard register. The 7949 caller has already checked that (reg:MODE SRC) and (reg:MODE DEST) 7950 occupy the same number of hard registers. */ 7951 7952 static bool 7953 inherit_piecemeal_p (int dest ATTRIBUTE_UNUSED, 7954 int src ATTRIBUTE_UNUSED, 7955 machine_mode mode ATTRIBUTE_UNUSED) 7956 { 7957 return (REG_CAN_CHANGE_MODE_P (dest, mode, reg_raw_mode[dest]) 7958 && REG_CAN_CHANGE_MODE_P (src, mode, reg_raw_mode[src])); 7959 } 7960 7961 /* Output insns to reload values in and out of the chosen reload regs. */ 7962 7963 static void 7964 emit_reload_insns (class insn_chain *chain) 7965 { 7966 rtx_insn *insn = chain->insn; 7967 7968 int j; 7969 7970 CLEAR_HARD_REG_SET (reg_reloaded_died); 7971 7972 for (j = 0; j < reload_n_operands; j++) 7973 input_reload_insns[j] = input_address_reload_insns[j] 7974 = inpaddr_address_reload_insns[j] 7975 = output_reload_insns[j] = output_address_reload_insns[j] 7976 = outaddr_address_reload_insns[j] 7977 = other_output_reload_insns[j] = 0; 7978 other_input_address_reload_insns = 0; 7979 other_input_reload_insns = 0; 7980 operand_reload_insns = 0; 7981 other_operand_reload_insns = 0; 7982 7983 /* Dump reloads into the dump file. */ 7984 if (dump_file) 7985 { 7986 fprintf (dump_file, "\nReloads for insn # %d\n", INSN_UID (insn)); 7987 debug_reload_to_stream (dump_file); 7988 } 7989 7990 for (j = 0; j < n_reloads; j++) 7991 if (rld[j].reg_rtx && HARD_REGISTER_P (rld[j].reg_rtx)) 7992 { 7993 unsigned int i; 7994 7995 for (i = REGNO (rld[j].reg_rtx); i < END_REGNO (rld[j].reg_rtx); i++) 7996 new_spill_reg_store[i] = 0; 7997 } 7998 7999 /* Now output the instructions to copy the data into and out of the 8000 reload registers. Do these in the order that the reloads were reported, 8001 since reloads of base and index registers precede reloads of operands 8002 and the operands may need the base and index registers reloaded. */ 8003 8004 for (j = 0; j < n_reloads; j++) 8005 { 8006 do_input_reload (chain, rld + j, j); 8007 do_output_reload (chain, rld + j, j); 8008 } 8009 8010 /* Now write all the insns we made for reloads in the order expected by 8011 the allocation functions. Prior to the insn being reloaded, we write 8012 the following reloads: 8013 8014 RELOAD_FOR_OTHER_ADDRESS reloads for input addresses. 8015 8016 RELOAD_OTHER reloads. 8017 8018 For each operand, any RELOAD_FOR_INPADDR_ADDRESS reloads followed 8019 by any RELOAD_FOR_INPUT_ADDRESS reloads followed by the 8020 RELOAD_FOR_INPUT reload for the operand. 8021 8022 RELOAD_FOR_OPADDR_ADDRS reloads. 8023 8024 RELOAD_FOR_OPERAND_ADDRESS reloads. 8025 8026 After the insn being reloaded, we write the following: 8027 8028 For each operand, any RELOAD_FOR_OUTADDR_ADDRESS reloads followed 8029 by any RELOAD_FOR_OUTPUT_ADDRESS reload followed by the 8030 RELOAD_FOR_OUTPUT reload, followed by any RELOAD_OTHER output 8031 reloads for the operand. The RELOAD_OTHER output reloads are 8032 output in descending order by reload number. */ 8033 8034 emit_insn_before (other_input_address_reload_insns, insn); 8035 emit_insn_before (other_input_reload_insns, insn); 8036 8037 for (j = 0; j < reload_n_operands; j++) 8038 { 8039 emit_insn_before (inpaddr_address_reload_insns[j], insn); 8040 emit_insn_before (input_address_reload_insns[j], insn); 8041 emit_insn_before (input_reload_insns[j], insn); 8042 } 8043 8044 emit_insn_before (other_operand_reload_insns, insn); 8045 emit_insn_before (operand_reload_insns, insn); 8046 8047 for (j = 0; j < reload_n_operands; j++) 8048 { 8049 rtx_insn *x = emit_insn_after (outaddr_address_reload_insns[j], insn); 8050 x = emit_insn_after (output_address_reload_insns[j], x); 8051 x = emit_insn_after (output_reload_insns[j], x); 8052 emit_insn_after (other_output_reload_insns[j], x); 8053 } 8054 8055 /* For all the spill regs newly reloaded in this instruction, 8056 record what they were reloaded from, so subsequent instructions 8057 can inherit the reloads. 8058 8059 Update spill_reg_store for the reloads of this insn. 8060 Copy the elements that were updated in the loop above. */ 8061 8062 for (j = 0; j < n_reloads; j++) 8063 { 8064 int r = reload_order[j]; 8065 int i = reload_spill_index[r]; 8066 8067 /* If this is a non-inherited input reload from a pseudo, we must 8068 clear any memory of a previous store to the same pseudo. Only do 8069 something if there will not be an output reload for the pseudo 8070 being reloaded. */ 8071 if (rld[r].in_reg != 0 8072 && ! (reload_inherited[r] || reload_override_in[r])) 8073 { 8074 rtx reg = rld[r].in_reg; 8075 8076 if (GET_CODE (reg) == SUBREG) 8077 reg = SUBREG_REG (reg); 8078 8079 if (REG_P (reg) 8080 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 8081 && !REGNO_REG_SET_P (®_has_output_reload, REGNO (reg))) 8082 { 8083 int nregno = REGNO (reg); 8084 8085 if (reg_last_reload_reg[nregno]) 8086 { 8087 int last_regno = REGNO (reg_last_reload_reg[nregno]); 8088 8089 if (reg_reloaded_contents[last_regno] == nregno) 8090 spill_reg_store[last_regno] = 0; 8091 } 8092 } 8093 } 8094 8095 /* I is nonneg if this reload used a register. 8096 If rld[r].reg_rtx is 0, this is an optional reload 8097 that we opted to ignore. */ 8098 8099 if (i >= 0 && rld[r].reg_rtx != 0) 8100 { 8101 int nr = hard_regno_nregs (i, GET_MODE (rld[r].reg_rtx)); 8102 int k; 8103 8104 /* For a multi register reload, we need to check if all or part 8105 of the value lives to the end. */ 8106 for (k = 0; k < nr; k++) 8107 if (reload_reg_reaches_end_p (i + k, r)) 8108 CLEAR_HARD_REG_BIT (reg_reloaded_valid, i + k); 8109 8110 /* Maybe the spill reg contains a copy of reload_out. */ 8111 if (rld[r].out != 0 8112 && (REG_P (rld[r].out) 8113 || (rld[r].out_reg 8114 ? REG_P (rld[r].out_reg) 8115 /* The reload value is an auto-modification of 8116 some kind. For PRE_INC, POST_INC, PRE_DEC 8117 and POST_DEC, we record an equivalence 8118 between the reload register and the operand 8119 on the optimistic assumption that we can make 8120 the equivalence hold. reload_as_needed must 8121 then either make it hold or invalidate the 8122 equivalence. 8123 8124 PRE_MODIFY and POST_MODIFY addresses are reloaded 8125 somewhat differently, and allowing them here leads 8126 to problems. */ 8127 : (GET_CODE (rld[r].out) != POST_MODIFY 8128 && GET_CODE (rld[r].out) != PRE_MODIFY)))) 8129 { 8130 rtx reg; 8131 8132 reg = reload_reg_rtx_for_output[r]; 8133 if (reload_reg_rtx_reaches_end_p (reg, r)) 8134 { 8135 machine_mode mode = GET_MODE (reg); 8136 int regno = REGNO (reg); 8137 int nregs = REG_NREGS (reg); 8138 rtx out = (REG_P (rld[r].out) 8139 ? rld[r].out 8140 : rld[r].out_reg 8141 ? rld[r].out_reg 8142 /* AUTO_INC */ : XEXP (rld[r].in_reg, 0)); 8143 int out_regno = REGNO (out); 8144 int out_nregs = (!HARD_REGISTER_NUM_P (out_regno) ? 1 8145 : hard_regno_nregs (out_regno, mode)); 8146 bool piecemeal; 8147 8148 spill_reg_store[regno] = new_spill_reg_store[regno]; 8149 spill_reg_stored_to[regno] = out; 8150 reg_last_reload_reg[out_regno] = reg; 8151 8152 piecemeal = (HARD_REGISTER_NUM_P (out_regno) 8153 && nregs == out_nregs 8154 && inherit_piecemeal_p (out_regno, regno, mode)); 8155 8156 /* If OUT_REGNO is a hard register, it may occupy more than 8157 one register. If it does, say what is in the 8158 rest of the registers assuming that both registers 8159 agree on how many words the object takes. If not, 8160 invalidate the subsequent registers. */ 8161 8162 if (HARD_REGISTER_NUM_P (out_regno)) 8163 for (k = 1; k < out_nregs; k++) 8164 reg_last_reload_reg[out_regno + k] 8165 = (piecemeal ? regno_reg_rtx[regno + k] : 0); 8166 8167 /* Now do the inverse operation. */ 8168 for (k = 0; k < nregs; k++) 8169 { 8170 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k); 8171 reg_reloaded_contents[regno + k] 8172 = (!HARD_REGISTER_NUM_P (out_regno) || !piecemeal 8173 ? out_regno 8174 : out_regno + k); 8175 reg_reloaded_insn[regno + k] = insn; 8176 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k); 8177 } 8178 } 8179 } 8180 /* Maybe the spill reg contains a copy of reload_in. Only do 8181 something if there will not be an output reload for 8182 the register being reloaded. */ 8183 else if (rld[r].out_reg == 0 8184 && rld[r].in != 0 8185 && ((REG_P (rld[r].in) 8186 && !HARD_REGISTER_P (rld[r].in) 8187 && !REGNO_REG_SET_P (®_has_output_reload, 8188 REGNO (rld[r].in))) 8189 || (REG_P (rld[r].in_reg) 8190 && !REGNO_REG_SET_P (®_has_output_reload, 8191 REGNO (rld[r].in_reg)))) 8192 && !reg_set_p (reload_reg_rtx_for_input[r], PATTERN (insn))) 8193 { 8194 rtx reg; 8195 8196 reg = reload_reg_rtx_for_input[r]; 8197 if (reload_reg_rtx_reaches_end_p (reg, r)) 8198 { 8199 machine_mode mode; 8200 int regno; 8201 int nregs; 8202 int in_regno; 8203 int in_nregs; 8204 rtx in; 8205 bool piecemeal; 8206 8207 mode = GET_MODE (reg); 8208 regno = REGNO (reg); 8209 nregs = REG_NREGS (reg); 8210 if (REG_P (rld[r].in) 8211 && REGNO (rld[r].in) >= FIRST_PSEUDO_REGISTER) 8212 in = rld[r].in; 8213 else if (REG_P (rld[r].in_reg)) 8214 in = rld[r].in_reg; 8215 else 8216 in = XEXP (rld[r].in_reg, 0); 8217 in_regno = REGNO (in); 8218 8219 in_nregs = (!HARD_REGISTER_NUM_P (in_regno) ? 1 8220 : hard_regno_nregs (in_regno, mode)); 8221 8222 reg_last_reload_reg[in_regno] = reg; 8223 8224 piecemeal = (HARD_REGISTER_NUM_P (in_regno) 8225 && nregs == in_nregs 8226 && inherit_piecemeal_p (regno, in_regno, mode)); 8227 8228 if (HARD_REGISTER_NUM_P (in_regno)) 8229 for (k = 1; k < in_nregs; k++) 8230 reg_last_reload_reg[in_regno + k] 8231 = (piecemeal ? regno_reg_rtx[regno + k] : 0); 8232 8233 /* Unless we inherited this reload, show we haven't 8234 recently done a store. 8235 Previous stores of inherited auto_inc expressions 8236 also have to be discarded. */ 8237 if (! reload_inherited[r] 8238 || (rld[r].out && ! rld[r].out_reg)) 8239 spill_reg_store[regno] = 0; 8240 8241 for (k = 0; k < nregs; k++) 8242 { 8243 CLEAR_HARD_REG_BIT (reg_reloaded_dead, regno + k); 8244 reg_reloaded_contents[regno + k] 8245 = (!HARD_REGISTER_NUM_P (in_regno) || !piecemeal 8246 ? in_regno 8247 : in_regno + k); 8248 reg_reloaded_insn[regno + k] = insn; 8249 SET_HARD_REG_BIT (reg_reloaded_valid, regno + k); 8250 } 8251 } 8252 } 8253 } 8254 8255 /* The following if-statement was #if 0'd in 1.34 (or before...). 8256 It's reenabled in 1.35 because supposedly nothing else 8257 deals with this problem. */ 8258 8259 /* If a register gets output-reloaded from a non-spill register, 8260 that invalidates any previous reloaded copy of it. 8261 But forget_old_reloads_1 won't get to see it, because 8262 it thinks only about the original insn. So invalidate it here. 8263 Also do the same thing for RELOAD_OTHER constraints where the 8264 output is discarded. */ 8265 if (i < 0 8266 && ((rld[r].out != 0 8267 && (REG_P (rld[r].out) 8268 || (MEM_P (rld[r].out) 8269 && REG_P (rld[r].out_reg)))) 8270 || (rld[r].out == 0 && rld[r].out_reg 8271 && REG_P (rld[r].out_reg)))) 8272 { 8273 rtx out = ((rld[r].out && REG_P (rld[r].out)) 8274 ? rld[r].out : rld[r].out_reg); 8275 int out_regno = REGNO (out); 8276 machine_mode mode = GET_MODE (out); 8277 8278 /* REG_RTX is now set or clobbered by the main instruction. 8279 As the comment above explains, forget_old_reloads_1 only 8280 sees the original instruction, and there is no guarantee 8281 that the original instruction also clobbered REG_RTX. 8282 For example, if find_reloads sees that the input side of 8283 a matched operand pair dies in this instruction, it may 8284 use the input register as the reload register. 8285 8286 Calling forget_old_reloads_1 is a waste of effort if 8287 REG_RTX is also the output register. 8288 8289 If we know that REG_RTX holds the value of a pseudo 8290 register, the code after the call will record that fact. */ 8291 if (rld[r].reg_rtx && rld[r].reg_rtx != out) 8292 forget_old_reloads_1 (rld[r].reg_rtx, NULL_RTX, NULL); 8293 8294 if (!HARD_REGISTER_NUM_P (out_regno)) 8295 { 8296 rtx src_reg; 8297 rtx_insn *store_insn = NULL; 8298 8299 reg_last_reload_reg[out_regno] = 0; 8300 8301 /* If we can find a hard register that is stored, record 8302 the storing insn so that we may delete this insn with 8303 delete_output_reload. */ 8304 src_reg = reload_reg_rtx_for_output[r]; 8305 8306 if (src_reg) 8307 { 8308 if (reload_reg_rtx_reaches_end_p (src_reg, r)) 8309 store_insn = new_spill_reg_store[REGNO (src_reg)]; 8310 else 8311 src_reg = NULL_RTX; 8312 } 8313 else 8314 { 8315 /* If this is an optional reload, try to find the 8316 source reg from an input reload. */ 8317 rtx set = single_set (insn); 8318 if (set && SET_DEST (set) == rld[r].out) 8319 { 8320 int k; 8321 8322 src_reg = SET_SRC (set); 8323 store_insn = insn; 8324 for (k = 0; k < n_reloads; k++) 8325 { 8326 if (rld[k].in == src_reg) 8327 { 8328 src_reg = reload_reg_rtx_for_input[k]; 8329 break; 8330 } 8331 } 8332 } 8333 } 8334 if (src_reg && REG_P (src_reg) 8335 && REGNO (src_reg) < FIRST_PSEUDO_REGISTER) 8336 { 8337 int src_regno, src_nregs, k; 8338 rtx note; 8339 8340 gcc_assert (GET_MODE (src_reg) == mode); 8341 src_regno = REGNO (src_reg); 8342 src_nregs = hard_regno_nregs (src_regno, mode); 8343 /* The place where to find a death note varies with 8344 PRESERVE_DEATH_INFO_REGNO_P . The condition is not 8345 necessarily checked exactly in the code that moves 8346 notes, so just check both locations. */ 8347 note = find_regno_note (insn, REG_DEAD, src_regno); 8348 if (! note && store_insn) 8349 note = find_regno_note (store_insn, REG_DEAD, src_regno); 8350 for (k = 0; k < src_nregs; k++) 8351 { 8352 spill_reg_store[src_regno + k] = store_insn; 8353 spill_reg_stored_to[src_regno + k] = out; 8354 reg_reloaded_contents[src_regno + k] = out_regno; 8355 reg_reloaded_insn[src_regno + k] = store_insn; 8356 CLEAR_HARD_REG_BIT (reg_reloaded_dead, src_regno + k); 8357 SET_HARD_REG_BIT (reg_reloaded_valid, src_regno + k); 8358 SET_HARD_REG_BIT (reg_is_output_reload, src_regno + k); 8359 if (note) 8360 SET_HARD_REG_BIT (reg_reloaded_died, src_regno); 8361 else 8362 CLEAR_HARD_REG_BIT (reg_reloaded_died, src_regno); 8363 } 8364 reg_last_reload_reg[out_regno] = src_reg; 8365 /* We have to set reg_has_output_reload here, or else 8366 forget_old_reloads_1 will clear reg_last_reload_reg 8367 right away. */ 8368 SET_REGNO_REG_SET (®_has_output_reload, 8369 out_regno); 8370 } 8371 } 8372 else 8373 { 8374 int k, out_nregs = hard_regno_nregs (out_regno, mode); 8375 8376 for (k = 0; k < out_nregs; k++) 8377 reg_last_reload_reg[out_regno + k] = 0; 8378 } 8379 } 8380 8381 #ifdef NB_FIX_VAX_BACKEND 8382 #if AUTO_INC_DEC 8383 /* Where an output register might be reloaded, and it is a 8384 memory reference, and the address is auto-incremented, any 8385 previously reloaded copy of the address must be 8386 invalidated. */ 8387 if (i < 0 8388 && rld[r].out != 0 8389 && MEM_P (rld[r].out)) 8390 { 8391 rtx out = XEXP (rld[r].out, 0); /* address expression */ 8392 enum rtx_code code = GET_CODE (out); 8393 8394 if (code != POST_INC && code != POST_DEC 8395 && code != PRE_INC && code != PRE_DEC) 8396 { 8397 /* do nothing */ 8398 } 8399 else 8400 { 8401 int out_regno = REGNO (XEXP (out, 0)); 8402 machine_mode mode = GET_MODE (XEXP (out, 0)); 8403 8404 /* for the moment, handle only the case where out_regno 8405 is a hardware register */ 8406 8407 if (HARD_REGISTER_NUM_P (out_regno)) 8408 { 8409 int k, out_nregs = hard_regno_nregs (out_regno, mode); 8410 8411 for (k = 0; k < out_nregs; k++) 8412 reg_last_reload_reg[out_regno + k] = 0; 8413 } 8414 } 8415 } 8416 #endif /* AUTO_INC_DEC */ 8417 #endif 8418 } 8419 reg_reloaded_dead |= reg_reloaded_died; 8420 } 8421 8422 /* Go through the motions to emit INSN and test if it is strictly valid. 8423 Return the emitted insn if valid, else return NULL. */ 8424 8425 static rtx_insn * 8426 emit_insn_if_valid_for_reload (rtx pat) 8427 { 8428 rtx_insn *last = get_last_insn (); 8429 int code; 8430 8431 rtx_insn *insn = emit_insn (pat); 8432 code = recog_memoized (insn); 8433 8434 if (code >= 0) 8435 { 8436 extract_insn (insn); 8437 /* We want constrain operands to treat this insn strictly in its 8438 validity determination, i.e., the way it would after reload has 8439 completed. */ 8440 if (constrain_operands (1, get_enabled_alternatives (insn))) 8441 return insn; 8442 } 8443 8444 delete_insns_since (last); 8445 return NULL; 8446 } 8447 8448 /* Emit code to perform a reload from IN (which may be a reload register) to 8449 OUT (which may also be a reload register). IN or OUT is from operand 8450 OPNUM with reload type TYPE. 8451 8452 Returns first insn emitted. */ 8453 8454 static rtx_insn * 8455 gen_reload (rtx out, rtx in, int opnum, enum reload_type type) 8456 { 8457 rtx_insn *last = get_last_insn (); 8458 rtx_insn *tem; 8459 rtx tem1, tem2; 8460 8461 /* If IN is a paradoxical SUBREG, remove it and try to put the 8462 opposite SUBREG on OUT. Likewise for a paradoxical SUBREG on OUT. */ 8463 if (!strip_paradoxical_subreg (&in, &out)) 8464 strip_paradoxical_subreg (&out, &in); 8465 8466 /* How to do this reload can get quite tricky. Normally, we are being 8467 asked to reload a simple operand, such as a MEM, a constant, or a pseudo 8468 register that didn't get a hard register. In that case we can just 8469 call emit_move_insn. 8470 8471 We can also be asked to reload a PLUS that adds a register or a MEM to 8472 another register, constant or MEM. This can occur during frame pointer 8473 elimination and while reloading addresses. This case is handled by 8474 trying to emit a single insn to perform the add. If it is not valid, 8475 we use a two insn sequence. 8476 8477 Or we can be asked to reload an unary operand that was a fragment of 8478 an addressing mode, into a register. If it isn't recognized as-is, 8479 we try making the unop operand and the reload-register the same: 8480 (set reg:X (unop:X expr:Y)) 8481 -> (set reg:Y expr:Y) (set reg:X (unop:X reg:Y)). 8482 8483 Finally, we could be called to handle an 'o' constraint by putting 8484 an address into a register. In that case, we first try to do this 8485 with a named pattern of "reload_load_address". If no such pattern 8486 exists, we just emit a SET insn and hope for the best (it will normally 8487 be valid on machines that use 'o'). 8488 8489 This entire process is made complex because reload will never 8490 process the insns we generate here and so we must ensure that 8491 they will fit their constraints and also by the fact that parts of 8492 IN might be being reloaded separately and replaced with spill registers. 8493 Because of this, we are, in some sense, just guessing the right approach 8494 here. The one listed above seems to work. 8495 8496 ??? At some point, this whole thing needs to be rethought. */ 8497 8498 if (GET_CODE (in) == PLUS 8499 && (REG_P (XEXP (in, 0)) 8500 || GET_CODE (XEXP (in, 0)) == SUBREG 8501 || MEM_P (XEXP (in, 0))) 8502 && (REG_P (XEXP (in, 1)) 8503 || GET_CODE (XEXP (in, 1)) == SUBREG 8504 || CONSTANT_P (XEXP (in, 1)) 8505 || MEM_P (XEXP (in, 1)))) 8506 { 8507 /* We need to compute the sum of a register or a MEM and another 8508 register, constant, or MEM, and put it into the reload 8509 register. The best possible way of doing this is if the machine 8510 has a three-operand ADD insn that accepts the required operands. 8511 8512 The simplest approach is to try to generate such an insn and see if it 8513 is recognized and matches its constraints. If so, it can be used. 8514 8515 It might be better not to actually emit the insn unless it is valid, 8516 but we need to pass the insn as an operand to `recog' and 8517 `extract_insn' and it is simpler to emit and then delete the insn if 8518 not valid than to dummy things up. */ 8519 8520 rtx op0, op1, tem; 8521 rtx_insn *insn; 8522 enum insn_code code; 8523 8524 op0 = find_replacement (&XEXP (in, 0)); 8525 op1 = find_replacement (&XEXP (in, 1)); 8526 8527 /* Since constraint checking is strict, commutativity won't be 8528 checked, so we need to do that here to avoid spurious failure 8529 if the add instruction is two-address and the second operand 8530 of the add is the same as the reload reg, which is frequently 8531 the case. If the insn would be A = B + A, rearrange it so 8532 it will be A = A + B as constrain_operands expects. */ 8533 8534 if (REG_P (XEXP (in, 1)) 8535 && REGNO (out) == REGNO (XEXP (in, 1))) 8536 tem = op0, op0 = op1, op1 = tem; 8537 8538 if (op0 != XEXP (in, 0) || op1 != XEXP (in, 1)) 8539 in = gen_rtx_PLUS (GET_MODE (in), op0, op1); 8540 8541 insn = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in)); 8542 if (insn) 8543 return insn; 8544 8545 /* If that failed, we must use a conservative two-insn sequence. 8546 8547 Use a move to copy one operand into the reload register. Prefer 8548 to reload a constant, MEM or pseudo since the move patterns can 8549 handle an arbitrary operand. If OP1 is not a constant, MEM or 8550 pseudo and OP1 is not a valid operand for an add instruction, then 8551 reload OP1. 8552 8553 After reloading one of the operands into the reload register, add 8554 the reload register to the output register. 8555 8556 If there is another way to do this for a specific machine, a 8557 DEFINE_PEEPHOLE should be specified that recognizes the sequence 8558 we emit below. */ 8559 8560 code = optab_handler (add_optab, GET_MODE (out)); 8561 8562 if (CONSTANT_P (op1) || MEM_P (op1) || GET_CODE (op1) == SUBREG 8563 || (REG_P (op1) 8564 && REGNO (op1) >= FIRST_PSEUDO_REGISTER) 8565 || (code != CODE_FOR_nothing 8566 && !insn_operand_matches (code, 2, op1))) 8567 tem = op0, op0 = op1, op1 = tem; 8568 8569 gen_reload (out, op0, opnum, type); 8570 8571 /* If OP0 and OP1 are the same, we can use OUT for OP1. 8572 This fixes a problem on the 32K where the stack pointer cannot 8573 be used as an operand of an add insn. */ 8574 8575 if (rtx_equal_p (op0, op1)) 8576 op1 = out; 8577 8578 insn = emit_insn_if_valid_for_reload (gen_add2_insn (out, op1)); 8579 if (insn) 8580 { 8581 /* Add a REG_EQUIV note so that find_equiv_reg can find it. */ 8582 set_dst_reg_note (insn, REG_EQUIV, in, out); 8583 return insn; 8584 } 8585 8586 /* If that failed, copy the address register to the reload register. 8587 Then add the constant to the reload register. */ 8588 8589 gcc_assert (!reg_overlap_mentioned_p (out, op0)); 8590 gen_reload (out, op1, opnum, type); 8591 insn = emit_insn (gen_add2_insn (out, op0)); 8592 set_dst_reg_note (insn, REG_EQUIV, in, out); 8593 } 8594 8595 /* If we need a memory location to do the move, do it that way. */ 8596 else if ((tem1 = replaced_subreg (in), tem2 = replaced_subreg (out), 8597 (REG_P (tem1) && REG_P (tem2))) 8598 && REGNO (tem1) < FIRST_PSEUDO_REGISTER 8599 && REGNO (tem2) < FIRST_PSEUDO_REGISTER 8600 && targetm.secondary_memory_needed (GET_MODE (out), 8601 REGNO_REG_CLASS (REGNO (tem1)), 8602 REGNO_REG_CLASS (REGNO (tem2)))) 8603 { 8604 /* Get the memory to use and rewrite both registers to its mode. */ 8605 rtx loc = get_secondary_mem (in, GET_MODE (out), opnum, type); 8606 8607 if (GET_MODE (loc) != GET_MODE (out)) 8608 out = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (out)); 8609 8610 if (GET_MODE (loc) != GET_MODE (in)) 8611 in = gen_rtx_REG (GET_MODE (loc), reg_or_subregno (in)); 8612 8613 gen_reload (loc, in, opnum, type); 8614 gen_reload (out, loc, opnum, type); 8615 } 8616 else if (REG_P (out) && UNARY_P (in)) 8617 { 8618 rtx op1; 8619 rtx out_moded; 8620 rtx_insn *set; 8621 8622 op1 = find_replacement (&XEXP (in, 0)); 8623 if (op1 != XEXP (in, 0)) 8624 in = gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), op1); 8625 8626 /* First, try a plain SET. */ 8627 set = emit_insn_if_valid_for_reload (gen_rtx_SET (out, in)); 8628 if (set) 8629 return set; 8630 8631 /* If that failed, move the inner operand to the reload 8632 register, and try the same unop with the inner expression 8633 replaced with the reload register. */ 8634 8635 if (GET_MODE (op1) != GET_MODE (out)) 8636 out_moded = gen_rtx_REG (GET_MODE (op1), REGNO (out)); 8637 else 8638 out_moded = out; 8639 8640 gen_reload (out_moded, op1, opnum, type); 8641 8642 rtx temp = gen_rtx_SET (out, gen_rtx_fmt_e (GET_CODE (in), GET_MODE (in), 8643 out_moded)); 8644 rtx_insn *insn = emit_insn_if_valid_for_reload (temp); 8645 if (insn) 8646 { 8647 set_unique_reg_note (insn, REG_EQUIV, in); 8648 return insn; 8649 } 8650 8651 fatal_insn ("failure trying to reload:", set); 8652 } 8653 /* If IN is a simple operand, use gen_move_insn. */ 8654 else if (OBJECT_P (in) || GET_CODE (in) == SUBREG) 8655 { 8656 tem = emit_insn (gen_move_insn (out, in)); 8657 /* IN may contain a LABEL_REF, if so add a REG_LABEL_OPERAND note. */ 8658 mark_jump_label (in, tem, 0); 8659 } 8660 8661 else if (targetm.have_reload_load_address ()) 8662 emit_insn (targetm.gen_reload_load_address (out, in)); 8663 8664 /* Otherwise, just write (set OUT IN) and hope for the best. */ 8665 else 8666 emit_insn (gen_rtx_SET (out, in)); 8667 8668 /* Return the first insn emitted. 8669 We cannot just return get_last_insn, because there may have 8670 been multiple instructions emitted. Also note that gen_move_insn may 8671 emit more than one insn itself, so we cannot assume that there is one 8672 insn emitted per emit_insn_before call. */ 8673 8674 return last ? NEXT_INSN (last) : get_insns (); 8675 } 8676 8677 /* Delete a previously made output-reload whose result we now believe 8678 is not needed. First we double-check. 8679 8680 INSN is the insn now being processed. 8681 LAST_RELOAD_REG is the hard register number for which we want to delete 8682 the last output reload. 8683 J is the reload-number that originally used REG. The caller has made 8684 certain that reload J doesn't use REG any longer for input. 8685 NEW_RELOAD_REG is reload register that reload J is using for REG. */ 8686 8687 static void 8688 delete_output_reload (rtx_insn *insn, int j, int last_reload_reg, 8689 rtx new_reload_reg) 8690 { 8691 rtx_insn *output_reload_insn = spill_reg_store[last_reload_reg]; 8692 rtx reg = spill_reg_stored_to[last_reload_reg]; 8693 int k; 8694 int n_occurrences; 8695 int n_inherited = 0; 8696 rtx substed; 8697 unsigned regno; 8698 int nregs; 8699 8700 /* It is possible that this reload has been only used to set another reload 8701 we eliminated earlier and thus deleted this instruction too. */ 8702 if (output_reload_insn->deleted ()) 8703 return; 8704 8705 /* Get the raw pseudo-register referred to. */ 8706 8707 while (GET_CODE (reg) == SUBREG) 8708 reg = SUBREG_REG (reg); 8709 substed = reg_equiv_memory_loc (REGNO (reg)); 8710 8711 /* This is unsafe if the operand occurs more often in the current 8712 insn than it is inherited. */ 8713 for (k = n_reloads - 1; k >= 0; k--) 8714 { 8715 rtx reg2 = rld[k].in; 8716 if (! reg2) 8717 continue; 8718 if (MEM_P (reg2) || reload_override_in[k]) 8719 reg2 = rld[k].in_reg; 8720 8721 if (AUTO_INC_DEC && rld[k].out && ! rld[k].out_reg) 8722 reg2 = XEXP (rld[k].in_reg, 0); 8723 8724 while (GET_CODE (reg2) == SUBREG) 8725 reg2 = SUBREG_REG (reg2); 8726 if (rtx_equal_p (reg2, reg)) 8727 { 8728 if (reload_inherited[k] || reload_override_in[k] || k == j) 8729 n_inherited++; 8730 else 8731 return; 8732 } 8733 } 8734 n_occurrences = count_occurrences (PATTERN (insn), reg, 0); 8735 if (CALL_P (insn) && CALL_INSN_FUNCTION_USAGE (insn)) 8736 n_occurrences += count_occurrences (CALL_INSN_FUNCTION_USAGE (insn), 8737 reg, 0); 8738 if (substed) 8739 n_occurrences += count_occurrences (PATTERN (insn), 8740 eliminate_regs (substed, VOIDmode, 8741 NULL_RTX), 0); 8742 for (rtx i1 = reg_equiv_alt_mem_list (REGNO (reg)); i1; i1 = XEXP (i1, 1)) 8743 { 8744 gcc_assert (!rtx_equal_p (XEXP (i1, 0), substed)); 8745 n_occurrences += count_occurrences (PATTERN (insn), XEXP (i1, 0), 0); 8746 } 8747 if (n_occurrences > n_inherited) 8748 return; 8749 8750 regno = REGNO (reg); 8751 nregs = REG_NREGS (reg); 8752 8753 /* If the pseudo-reg we are reloading is no longer referenced 8754 anywhere between the store into it and here, 8755 and we're within the same basic block, then the value can only 8756 pass through the reload reg and end up here. 8757 Otherwise, give up--return. */ 8758 for (rtx_insn *i1 = NEXT_INSN (output_reload_insn); 8759 i1 != insn; i1 = NEXT_INSN (i1)) 8760 { 8761 if (NOTE_INSN_BASIC_BLOCK_P (i1)) 8762 return; 8763 if ((NONJUMP_INSN_P (i1) || CALL_P (i1)) 8764 && refers_to_regno_p (regno, regno + nregs, PATTERN (i1), NULL)) 8765 { 8766 /* If this is USE in front of INSN, we only have to check that 8767 there are no more references than accounted for by inheritance. */ 8768 while (NONJUMP_INSN_P (i1) && GET_CODE (PATTERN (i1)) == USE) 8769 { 8770 n_occurrences += rtx_equal_p (reg, XEXP (PATTERN (i1), 0)) != 0; 8771 i1 = NEXT_INSN (i1); 8772 } 8773 if (n_occurrences <= n_inherited && i1 == insn) 8774 break; 8775 return; 8776 } 8777 } 8778 8779 /* We will be deleting the insn. Remove the spill reg information. */ 8780 for (k = hard_regno_nregs (last_reload_reg, GET_MODE (reg)); k-- > 0; ) 8781 { 8782 spill_reg_store[last_reload_reg + k] = 0; 8783 spill_reg_stored_to[last_reload_reg + k] = 0; 8784 } 8785 8786 /* The caller has already checked that REG dies or is set in INSN. 8787 It has also checked that we are optimizing, and thus some 8788 inaccuracies in the debugging information are acceptable. 8789 So we could just delete output_reload_insn. But in some cases 8790 we can improve the debugging information without sacrificing 8791 optimization - maybe even improving the code: See if the pseudo 8792 reg has been completely replaced with reload regs. If so, delete 8793 the store insn and forget we had a stack slot for the pseudo. */ 8794 if (rld[j].out != rld[j].in 8795 && REG_N_DEATHS (REGNO (reg)) == 1 8796 && REG_N_SETS (REGNO (reg)) == 1 8797 && REG_BASIC_BLOCK (REGNO (reg)) >= NUM_FIXED_BLOCKS 8798 && find_regno_note (insn, REG_DEAD, REGNO (reg))) 8799 { 8800 rtx_insn *i2; 8801 8802 /* We know that it was used only between here and the beginning of 8803 the current basic block. (We also know that the last use before 8804 INSN was the output reload we are thinking of deleting, but never 8805 mind that.) Search that range; see if any ref remains. */ 8806 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 8807 { 8808 rtx set = single_set (i2); 8809 8810 /* Uses which just store in the pseudo don't count, 8811 since if they are the only uses, they are dead. */ 8812 if (set != 0 && SET_DEST (set) == reg) 8813 continue; 8814 if (LABEL_P (i2) || JUMP_P (i2)) 8815 break; 8816 if ((NONJUMP_INSN_P (i2) || CALL_P (i2)) 8817 && reg_mentioned_p (reg, PATTERN (i2))) 8818 { 8819 /* Some other ref remains; just delete the output reload we 8820 know to be dead. */ 8821 delete_address_reloads (output_reload_insn, insn); 8822 delete_insn (output_reload_insn); 8823 return; 8824 } 8825 } 8826 8827 /* Delete the now-dead stores into this pseudo. Note that this 8828 loop also takes care of deleting output_reload_insn. */ 8829 for (i2 = PREV_INSN (insn); i2; i2 = PREV_INSN (i2)) 8830 { 8831 rtx set = single_set (i2); 8832 8833 if (set != 0 && SET_DEST (set) == reg) 8834 { 8835 delete_address_reloads (i2, insn); 8836 delete_insn (i2); 8837 } 8838 if (LABEL_P (i2) || JUMP_P (i2)) 8839 break; 8840 } 8841 8842 /* For the debugging info, say the pseudo lives in this reload reg. */ 8843 reg_renumber[REGNO (reg)] = REGNO (new_reload_reg); 8844 if (ira_conflicts_p) 8845 /* Inform IRA about the change. */ 8846 ira_mark_allocation_change (REGNO (reg)); 8847 alter_reg (REGNO (reg), -1, false); 8848 } 8849 else 8850 { 8851 delete_address_reloads (output_reload_insn, insn); 8852 delete_insn (output_reload_insn); 8853 } 8854 } 8855 8856 /* We are going to delete DEAD_INSN. Recursively delete loads of 8857 reload registers used in DEAD_INSN that are not used till CURRENT_INSN. 8858 CURRENT_INSN is being reloaded, so we have to check its reloads too. */ 8859 static void 8860 delete_address_reloads (rtx_insn *dead_insn, rtx_insn *current_insn) 8861 { 8862 rtx set = single_set (dead_insn); 8863 rtx set2, dst; 8864 rtx_insn *prev, *next; 8865 if (set) 8866 { 8867 rtx dst = SET_DEST (set); 8868 if (MEM_P (dst)) 8869 delete_address_reloads_1 (dead_insn, XEXP (dst, 0), current_insn); 8870 } 8871 /* If we deleted the store from a reloaded post_{in,de}c expression, 8872 we can delete the matching adds. */ 8873 prev = PREV_INSN (dead_insn); 8874 next = NEXT_INSN (dead_insn); 8875 if (! prev || ! next) 8876 return; 8877 set = single_set (next); 8878 set2 = single_set (prev); 8879 if (! set || ! set2 8880 || GET_CODE (SET_SRC (set)) != PLUS || GET_CODE (SET_SRC (set2)) != PLUS 8881 || !CONST_INT_P (XEXP (SET_SRC (set), 1)) 8882 || !CONST_INT_P (XEXP (SET_SRC (set2), 1))) 8883 return; 8884 dst = SET_DEST (set); 8885 if (! rtx_equal_p (dst, SET_DEST (set2)) 8886 || ! rtx_equal_p (dst, XEXP (SET_SRC (set), 0)) 8887 || ! rtx_equal_p (dst, XEXP (SET_SRC (set2), 0)) 8888 || (INTVAL (XEXP (SET_SRC (set), 1)) 8889 != -INTVAL (XEXP (SET_SRC (set2), 1)))) 8890 return; 8891 delete_related_insns (prev); 8892 delete_related_insns (next); 8893 } 8894 8895 /* Subfunction of delete_address_reloads: process registers found in X. */ 8896 static void 8897 delete_address_reloads_1 (rtx_insn *dead_insn, rtx x, rtx_insn *current_insn) 8898 { 8899 rtx_insn *prev, *i2; 8900 rtx set, dst; 8901 int i, j; 8902 enum rtx_code code = GET_CODE (x); 8903 8904 if (code != REG) 8905 { 8906 const char *fmt = GET_RTX_FORMAT (code); 8907 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 8908 { 8909 if (fmt[i] == 'e') 8910 delete_address_reloads_1 (dead_insn, XEXP (x, i), current_insn); 8911 else if (fmt[i] == 'E') 8912 { 8913 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 8914 delete_address_reloads_1 (dead_insn, XVECEXP (x, i, j), 8915 current_insn); 8916 } 8917 } 8918 return; 8919 } 8920 8921 if (spill_reg_order[REGNO (x)] < 0) 8922 return; 8923 8924 /* Scan backwards for the insn that sets x. This might be a way back due 8925 to inheritance. */ 8926 for (prev = PREV_INSN (dead_insn); prev; prev = PREV_INSN (prev)) 8927 { 8928 code = GET_CODE (prev); 8929 if (code == CODE_LABEL || code == JUMP_INSN) 8930 return; 8931 if (!INSN_P (prev)) 8932 continue; 8933 if (reg_set_p (x, PATTERN (prev))) 8934 break; 8935 if (reg_referenced_p (x, PATTERN (prev))) 8936 return; 8937 } 8938 if (! prev || INSN_UID (prev) < reload_first_uid) 8939 return; 8940 /* Check that PREV only sets the reload register. */ 8941 set = single_set (prev); 8942 if (! set) 8943 return; 8944 dst = SET_DEST (set); 8945 if (!REG_P (dst) 8946 || ! rtx_equal_p (dst, x)) 8947 return; 8948 if (! reg_set_p (dst, PATTERN (dead_insn))) 8949 { 8950 /* Check if DST was used in a later insn - 8951 it might have been inherited. */ 8952 for (i2 = NEXT_INSN (dead_insn); i2; i2 = NEXT_INSN (i2)) 8953 { 8954 if (LABEL_P (i2)) 8955 break; 8956 if (! INSN_P (i2)) 8957 continue; 8958 if (reg_referenced_p (dst, PATTERN (i2))) 8959 { 8960 /* If there is a reference to the register in the current insn, 8961 it might be loaded in a non-inherited reload. If no other 8962 reload uses it, that means the register is set before 8963 referenced. */ 8964 if (i2 == current_insn) 8965 { 8966 for (j = n_reloads - 1; j >= 0; j--) 8967 if ((rld[j].reg_rtx == dst && reload_inherited[j]) 8968 || reload_override_in[j] == dst) 8969 return; 8970 for (j = n_reloads - 1; j >= 0; j--) 8971 if (rld[j].in && rld[j].reg_rtx == dst) 8972 break; 8973 if (j >= 0) 8974 break; 8975 } 8976 return; 8977 } 8978 if (JUMP_P (i2)) 8979 break; 8980 /* If DST is still live at CURRENT_INSN, check if it is used for 8981 any reload. Note that even if CURRENT_INSN sets DST, we still 8982 have to check the reloads. */ 8983 if (i2 == current_insn) 8984 { 8985 for (j = n_reloads - 1; j >= 0; j--) 8986 if ((rld[j].reg_rtx == dst && reload_inherited[j]) 8987 || reload_override_in[j] == dst) 8988 return; 8989 /* ??? We can't finish the loop here, because dst might be 8990 allocated to a pseudo in this block if no reload in this 8991 block needs any of the classes containing DST - see 8992 spill_hard_reg. There is no easy way to tell this, so we 8993 have to scan till the end of the basic block. */ 8994 } 8995 if (reg_set_p (dst, PATTERN (i2))) 8996 break; 8997 } 8998 } 8999 delete_address_reloads_1 (prev, SET_SRC (set), current_insn); 9000 reg_reloaded_contents[REGNO (dst)] = -1; 9001 delete_insn (prev); 9002 } 9003 9004 /* Output reload-insns to reload VALUE into RELOADREG. 9005 VALUE is an autoincrement or autodecrement RTX whose operand 9006 is a register or memory location; 9007 so reloading involves incrementing that location. 9008 IN is either identical to VALUE, or some cheaper place to reload from. 9009 9010 INC_AMOUNT is the number to increment or decrement by (always positive). 9011 This cannot be deduced from VALUE. */ 9012 9013 static void 9014 inc_for_reload (rtx reloadreg, rtx in, rtx value, poly_int64 inc_amount) 9015 { 9016 /* REG or MEM to be copied and incremented. */ 9017 rtx incloc = find_replacement (&XEXP (value, 0)); 9018 /* Nonzero if increment after copying. */ 9019 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC 9020 || GET_CODE (value) == POST_MODIFY); 9021 rtx_insn *last; 9022 rtx inc; 9023 rtx_insn *add_insn; 9024 int code; 9025 rtx real_in = in == value ? incloc : in; 9026 9027 /* No hard register is equivalent to this register after 9028 inc/dec operation. If REG_LAST_RELOAD_REG were nonzero, 9029 we could inc/dec that register as well (maybe even using it for 9030 the source), but I'm not sure it's worth worrying about. */ 9031 if (REG_P (incloc)) 9032 reg_last_reload_reg[REGNO (incloc)] = 0; 9033 9034 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) 9035 { 9036 gcc_assert (GET_CODE (XEXP (value, 1)) == PLUS); 9037 inc = find_replacement (&XEXP (XEXP (value, 1), 1)); 9038 } 9039 else 9040 { 9041 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) 9042 inc_amount = -inc_amount; 9043 9044 inc = gen_int_mode (inc_amount, Pmode); 9045 } 9046 9047 /* If this is post-increment, first copy the location to the reload reg. */ 9048 if (post && real_in != reloadreg) 9049 emit_insn (gen_move_insn (reloadreg, real_in)); 9050 9051 if (in == value) 9052 { 9053 /* See if we can directly increment INCLOC. Use a method similar to 9054 that in gen_reload. */ 9055 9056 last = get_last_insn (); 9057 add_insn = emit_insn (gen_rtx_SET (incloc, 9058 gen_rtx_PLUS (GET_MODE (incloc), 9059 incloc, inc))); 9060 9061 code = recog_memoized (add_insn); 9062 if (code >= 0) 9063 { 9064 extract_insn (add_insn); 9065 if (constrain_operands (1, get_enabled_alternatives (add_insn))) 9066 { 9067 /* If this is a pre-increment and we have incremented the value 9068 where it lives, copy the incremented value to RELOADREG to 9069 be used as an address. */ 9070 9071 if (! post) 9072 emit_insn (gen_move_insn (reloadreg, incloc)); 9073 return; 9074 } 9075 } 9076 delete_insns_since (last); 9077 } 9078 9079 /* If couldn't do the increment directly, must increment in RELOADREG. 9080 The way we do this depends on whether this is pre- or post-increment. 9081 For pre-increment, copy INCLOC to the reload register, increment it 9082 there, then save back. */ 9083 9084 if (! post) 9085 { 9086 if (in != reloadreg) 9087 emit_insn (gen_move_insn (reloadreg, real_in)); 9088 emit_insn (gen_add2_insn (reloadreg, inc)); 9089 emit_insn (gen_move_insn (incloc, reloadreg)); 9090 } 9091 else 9092 { 9093 /* Postincrement. 9094 Because this might be a jump insn or a compare, and because RELOADREG 9095 may not be available after the insn in an input reload, we must do 9096 the incrementation before the insn being reloaded for. 9097 9098 We have already copied IN to RELOADREG. Increment the copy in 9099 RELOADREG, save that back, then decrement RELOADREG so it has 9100 the original value. */ 9101 9102 emit_insn (gen_add2_insn (reloadreg, inc)); 9103 emit_insn (gen_move_insn (incloc, reloadreg)); 9104 if (CONST_INT_P (inc)) 9105 emit_insn (gen_add2_insn (reloadreg, 9106 gen_int_mode (-INTVAL (inc), 9107 GET_MODE (reloadreg)))); 9108 else 9109 emit_insn (gen_sub2_insn (reloadreg, inc)); 9110 } 9111 } 9112 9113 static void 9114 add_auto_inc_notes (rtx_insn *insn, rtx x) 9115 { 9116 enum rtx_code code = GET_CODE (x); 9117 const char *fmt; 9118 int i, j; 9119 9120 if (code == MEM && auto_inc_p (XEXP (x, 0))) 9121 { 9122 add_reg_note (insn, REG_INC, XEXP (XEXP (x, 0), 0)); 9123 return; 9124 } 9125 9126 /* Scan all the operand sub-expressions. */ 9127 fmt = GET_RTX_FORMAT (code); 9128 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 9129 { 9130 if (fmt[i] == 'e') 9131 add_auto_inc_notes (insn, XEXP (x, i)); 9132 else if (fmt[i] == 'E') 9133 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 9134 add_auto_inc_notes (insn, XVECEXP (x, i, j)); 9135 } 9136 } 9137