1 /* Subroutines used by or related to instruction recognition. 2 Copyright (C) 1987-2018 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 21 #include "config.h" 22 #include "system.h" 23 #include "coretypes.h" 24 #include "backend.h" 25 #include "target.h" 26 #include "rtl.h" 27 #include "tree.h" 28 #include "cfghooks.h" 29 #include "df.h" 30 #include "memmodel.h" 31 #include "tm_p.h" 32 #include "insn-config.h" 33 #include "regs.h" 34 #include "emit-rtl.h" 35 #include "recog.h" 36 #include "insn-attr.h" 37 #include "addresses.h" 38 #include "cfgrtl.h" 39 #include "cfgbuild.h" 40 #include "cfgcleanup.h" 41 #include "reload.h" 42 #include "tree-pass.h" 43 44 #ifndef STACK_POP_CODE 45 #if STACK_GROWS_DOWNWARD 46 #define STACK_POP_CODE POST_INC 47 #else 48 #define STACK_POP_CODE POST_DEC 49 #endif 50 #endif 51 52 static void validate_replace_rtx_1 (rtx *, rtx, rtx, rtx_insn *, bool); 53 static void validate_replace_src_1 (rtx *, void *); 54 static rtx_insn *split_insn (rtx_insn *); 55 56 struct target_recog default_target_recog; 57 #if SWITCHABLE_TARGET 58 struct target_recog *this_target_recog = &default_target_recog; 59 #endif 60 61 /* Nonzero means allow operands to be volatile. 62 This should be 0 if you are generating rtl, such as if you are calling 63 the functions in optabs.c and expmed.c (most of the time). 64 This should be 1 if all valid insns need to be recognized, 65 such as in reginfo.c and final.c and reload.c. 66 67 init_recog and init_recog_no_volatile are responsible for setting this. */ 68 69 int volatile_ok; 70 71 struct recog_data_d recog_data; 72 73 /* Contains a vector of operand_alternative structures, such that 74 operand OP of alternative A is at index A * n_operands + OP. 75 Set up by preprocess_constraints. */ 76 const operand_alternative *recog_op_alt; 77 78 /* Used to provide recog_op_alt for asms. */ 79 static operand_alternative asm_op_alt[MAX_RECOG_OPERANDS 80 * MAX_RECOG_ALTERNATIVES]; 81 82 /* On return from `constrain_operands', indicate which alternative 83 was satisfied. */ 84 85 int which_alternative; 86 87 /* Nonzero after end of reload pass. 88 Set to 1 or 0 by toplev.c. 89 Controls the significance of (SUBREG (MEM)). */ 90 91 int reload_completed; 92 93 /* Nonzero after thread_prologue_and_epilogue_insns has run. */ 94 int epilogue_completed; 95 96 /* Initialize data used by the function `recog'. 97 This must be called once in the compilation of a function 98 before any insn recognition may be done in the function. */ 99 100 void 101 init_recog_no_volatile (void) 102 { 103 volatile_ok = 0; 104 } 105 106 void 107 init_recog (void) 108 { 109 volatile_ok = 1; 110 } 111 112 113 /* Return true if labels in asm operands BODY are LABEL_REFs. */ 114 115 static bool 116 asm_labels_ok (rtx body) 117 { 118 rtx asmop; 119 int i; 120 121 asmop = extract_asm_operands (body); 122 if (asmop == NULL_RTX) 123 return true; 124 125 for (i = 0; i < ASM_OPERANDS_LABEL_LENGTH (asmop); i++) 126 if (GET_CODE (ASM_OPERANDS_LABEL (asmop, i)) != LABEL_REF) 127 return false; 128 129 return true; 130 } 131 132 /* Check that X is an insn-body for an `asm' with operands 133 and that the operands mentioned in it are legitimate. */ 134 135 int 136 check_asm_operands (rtx x) 137 { 138 int noperands; 139 rtx *operands; 140 const char **constraints; 141 int i; 142 143 if (!asm_labels_ok (x)) 144 return 0; 145 146 /* Post-reload, be more strict with things. */ 147 if (reload_completed) 148 { 149 /* ??? Doh! We've not got the wrapping insn. Cook one up. */ 150 rtx_insn *insn = make_insn_raw (x); 151 extract_insn (insn); 152 constrain_operands (1, get_enabled_alternatives (insn)); 153 return which_alternative >= 0; 154 } 155 156 noperands = asm_noperands (x); 157 if (noperands < 0) 158 return 0; 159 if (noperands == 0) 160 return 1; 161 162 operands = XALLOCAVEC (rtx, noperands); 163 constraints = XALLOCAVEC (const char *, noperands); 164 165 decode_asm_operands (x, operands, NULL, constraints, NULL, NULL); 166 167 for (i = 0; i < noperands; i++) 168 { 169 const char *c = constraints[i]; 170 if (c[0] == '%') 171 c++; 172 if (! asm_operand_ok (operands[i], c, constraints)) 173 return 0; 174 } 175 176 return 1; 177 } 178 179 /* Static data for the next two routines. */ 180 181 struct change_t 182 { 183 rtx object; 184 int old_code; 185 bool unshare; 186 rtx *loc; 187 rtx old; 188 }; 189 190 static change_t *changes; 191 static int changes_allocated; 192 193 static int num_changes = 0; 194 195 /* Validate a proposed change to OBJECT. LOC is the location in the rtl 196 at which NEW_RTX will be placed. If OBJECT is zero, no validation is done, 197 the change is simply made. 198 199 Two types of objects are supported: If OBJECT is a MEM, memory_address_p 200 will be called with the address and mode as parameters. If OBJECT is 201 an INSN, CALL_INSN, or JUMP_INSN, the insn will be re-recognized with 202 the change in place. 203 204 IN_GROUP is nonzero if this is part of a group of changes that must be 205 performed as a group. In that case, the changes will be stored. The 206 function `apply_change_group' will validate and apply the changes. 207 208 If IN_GROUP is zero, this is a single change. Try to recognize the insn 209 or validate the memory reference with the change applied. If the result 210 is not valid for the machine, suppress the change and return zero. 211 Otherwise, perform the change and return 1. */ 212 213 static bool 214 validate_change_1 (rtx object, rtx *loc, rtx new_rtx, bool in_group, bool unshare) 215 { 216 rtx old = *loc; 217 218 if (old == new_rtx || rtx_equal_p (old, new_rtx)) 219 return 1; 220 221 gcc_assert (in_group != 0 || num_changes == 0); 222 223 *loc = new_rtx; 224 225 /* Save the information describing this change. */ 226 if (num_changes >= changes_allocated) 227 { 228 if (changes_allocated == 0) 229 /* This value allows for repeated substitutions inside complex 230 indexed addresses, or changes in up to 5 insns. */ 231 changes_allocated = MAX_RECOG_OPERANDS * 5; 232 else 233 changes_allocated *= 2; 234 235 changes = XRESIZEVEC (change_t, changes, changes_allocated); 236 } 237 238 changes[num_changes].object = object; 239 changes[num_changes].loc = loc; 240 changes[num_changes].old = old; 241 changes[num_changes].unshare = unshare; 242 243 if (object && !MEM_P (object)) 244 { 245 /* Set INSN_CODE to force rerecognition of insn. Save old code in 246 case invalid. */ 247 changes[num_changes].old_code = INSN_CODE (object); 248 INSN_CODE (object) = -1; 249 } 250 251 num_changes++; 252 253 /* If we are making a group of changes, return 1. Otherwise, validate the 254 change group we made. */ 255 256 if (in_group) 257 return 1; 258 else 259 return apply_change_group (); 260 } 261 262 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting 263 UNSHARE to false. */ 264 265 bool 266 validate_change (rtx object, rtx *loc, rtx new_rtx, bool in_group) 267 { 268 return validate_change_1 (object, loc, new_rtx, in_group, false); 269 } 270 271 /* Wrapper for validate_change_1 without the UNSHARE argument defaulting 272 UNSHARE to true. */ 273 274 bool 275 validate_unshare_change (rtx object, rtx *loc, rtx new_rtx, bool in_group) 276 { 277 return validate_change_1 (object, loc, new_rtx, in_group, true); 278 } 279 280 281 /* Keep X canonicalized if some changes have made it non-canonical; only 282 modifies the operands of X, not (for example) its code. Simplifications 283 are not the job of this routine. 284 285 Return true if anything was changed. */ 286 bool 287 canonicalize_change_group (rtx_insn *insn, rtx x) 288 { 289 if (COMMUTATIVE_P (x) 290 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 291 { 292 /* Oops, the caller has made X no longer canonical. 293 Let's redo the changes in the correct order. */ 294 rtx tem = XEXP (x, 0); 295 validate_unshare_change (insn, &XEXP (x, 0), XEXP (x, 1), 1); 296 validate_unshare_change (insn, &XEXP (x, 1), tem, 1); 297 return true; 298 } 299 else 300 return false; 301 } 302 303 304 /* This subroutine of apply_change_group verifies whether the changes to INSN 305 were valid; i.e. whether INSN can still be recognized. 306 307 If IN_GROUP is true clobbers which have to be added in order to 308 match the instructions will be added to the current change group. 309 Otherwise the changes will take effect immediately. */ 310 311 int 312 insn_invalid_p (rtx_insn *insn, bool in_group) 313 { 314 rtx pat = PATTERN (insn); 315 int num_clobbers = 0; 316 /* If we are before reload and the pattern is a SET, see if we can add 317 clobbers. */ 318 int icode = recog (pat, insn, 319 (GET_CODE (pat) == SET 320 && ! reload_completed 321 && ! reload_in_progress) 322 ? &num_clobbers : 0); 323 int is_asm = icode < 0 && asm_noperands (PATTERN (insn)) >= 0; 324 325 326 /* If this is an asm and the operand aren't legal, then fail. Likewise if 327 this is not an asm and the insn wasn't recognized. */ 328 if ((is_asm && ! check_asm_operands (PATTERN (insn))) 329 || (!is_asm && icode < 0)) 330 return 1; 331 332 /* If we have to add CLOBBERs, fail if we have to add ones that reference 333 hard registers since our callers can't know if they are live or not. 334 Otherwise, add them. */ 335 if (num_clobbers > 0) 336 { 337 rtx newpat; 338 339 if (added_clobbers_hard_reg_p (icode)) 340 return 1; 341 342 newpat = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (num_clobbers + 1)); 343 XVECEXP (newpat, 0, 0) = pat; 344 add_clobbers (newpat, icode); 345 if (in_group) 346 validate_change (insn, &PATTERN (insn), newpat, 1); 347 else 348 PATTERN (insn) = pat = newpat; 349 } 350 351 /* After reload, verify that all constraints are satisfied. */ 352 if (reload_completed) 353 { 354 extract_insn (insn); 355 356 if (! constrain_operands (1, get_preferred_alternatives (insn))) 357 return 1; 358 } 359 360 INSN_CODE (insn) = icode; 361 return 0; 362 } 363 364 /* Return number of changes made and not validated yet. */ 365 int 366 num_changes_pending (void) 367 { 368 return num_changes; 369 } 370 371 /* Tentatively apply the changes numbered NUM and up. 372 Return 1 if all changes are valid, zero otherwise. */ 373 374 int 375 verify_changes (int num) 376 { 377 int i; 378 rtx last_validated = NULL_RTX; 379 380 /* The changes have been applied and all INSN_CODEs have been reset to force 381 rerecognition. 382 383 The changes are valid if we aren't given an object, or if we are 384 given a MEM and it still is a valid address, or if this is in insn 385 and it is recognized. In the latter case, if reload has completed, 386 we also require that the operands meet the constraints for 387 the insn. */ 388 389 for (i = num; i < num_changes; i++) 390 { 391 rtx object = changes[i].object; 392 393 /* If there is no object to test or if it is the same as the one we 394 already tested, ignore it. */ 395 if (object == 0 || object == last_validated) 396 continue; 397 398 if (MEM_P (object)) 399 { 400 if (! memory_address_addr_space_p (GET_MODE (object), 401 XEXP (object, 0), 402 MEM_ADDR_SPACE (object))) 403 break; 404 } 405 else if (/* changes[i].old might be zero, e.g. when putting a 406 REG_FRAME_RELATED_EXPR into a previously empty list. */ 407 changes[i].old 408 && REG_P (changes[i].old) 409 && asm_noperands (PATTERN (object)) > 0 410 && REG_EXPR (changes[i].old) != NULL_TREE 411 && HAS_DECL_ASSEMBLER_NAME_P (REG_EXPR (changes[i].old)) 412 && DECL_ASSEMBLER_NAME_SET_P (REG_EXPR (changes[i].old)) 413 && DECL_REGISTER (REG_EXPR (changes[i].old))) 414 { 415 /* Don't allow changes of hard register operands to inline 416 assemblies if they have been defined as register asm ("x"). */ 417 break; 418 } 419 else if (DEBUG_INSN_P (object)) 420 continue; 421 else if (insn_invalid_p (as_a <rtx_insn *> (object), true)) 422 { 423 rtx pat = PATTERN (object); 424 425 /* Perhaps we couldn't recognize the insn because there were 426 extra CLOBBERs at the end. If so, try to re-recognize 427 without the last CLOBBER (later iterations will cause each of 428 them to be eliminated, in turn). But don't do this if we 429 have an ASM_OPERAND. */ 430 if (GET_CODE (pat) == PARALLEL 431 && GET_CODE (XVECEXP (pat, 0, XVECLEN (pat, 0) - 1)) == CLOBBER 432 && asm_noperands (PATTERN (object)) < 0) 433 { 434 rtx newpat; 435 436 if (XVECLEN (pat, 0) == 2) 437 newpat = XVECEXP (pat, 0, 0); 438 else 439 { 440 int j; 441 442 newpat 443 = gen_rtx_PARALLEL (VOIDmode, 444 rtvec_alloc (XVECLEN (pat, 0) - 1)); 445 for (j = 0; j < XVECLEN (newpat, 0); j++) 446 XVECEXP (newpat, 0, j) = XVECEXP (pat, 0, j); 447 } 448 449 /* Add a new change to this group to replace the pattern 450 with this new pattern. Then consider this change 451 as having succeeded. The change we added will 452 cause the entire call to fail if things remain invalid. 453 454 Note that this can lose if a later change than the one 455 we are processing specified &XVECEXP (PATTERN (object), 0, X) 456 but this shouldn't occur. */ 457 458 validate_change (object, &PATTERN (object), newpat, 1); 459 continue; 460 } 461 else if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER 462 || GET_CODE (pat) == VAR_LOCATION) 463 /* If this insn is a CLOBBER or USE, it is always valid, but is 464 never recognized. */ 465 continue; 466 else 467 break; 468 } 469 last_validated = object; 470 } 471 472 return (i == num_changes); 473 } 474 475 /* A group of changes has previously been issued with validate_change 476 and verified with verify_changes. Call df_insn_rescan for each of 477 the insn changed and clear num_changes. */ 478 479 void 480 confirm_change_group (void) 481 { 482 int i; 483 rtx last_object = NULL; 484 485 for (i = 0; i < num_changes; i++) 486 { 487 rtx object = changes[i].object; 488 489 if (changes[i].unshare) 490 *changes[i].loc = copy_rtx (*changes[i].loc); 491 492 /* Avoid unnecessary rescanning when multiple changes to same instruction 493 are made. */ 494 if (object) 495 { 496 if (object != last_object && last_object && INSN_P (last_object)) 497 df_insn_rescan (as_a <rtx_insn *> (last_object)); 498 last_object = object; 499 } 500 } 501 502 if (last_object && INSN_P (last_object)) 503 df_insn_rescan (as_a <rtx_insn *> (last_object)); 504 num_changes = 0; 505 } 506 507 /* Apply a group of changes previously issued with `validate_change'. 508 If all changes are valid, call confirm_change_group and return 1, 509 otherwise, call cancel_changes and return 0. */ 510 511 int 512 apply_change_group (void) 513 { 514 if (verify_changes (0)) 515 { 516 confirm_change_group (); 517 return 1; 518 } 519 else 520 { 521 cancel_changes (0); 522 return 0; 523 } 524 } 525 526 527 /* Return the number of changes so far in the current group. */ 528 529 int 530 num_validated_changes (void) 531 { 532 return num_changes; 533 } 534 535 /* Retract the changes numbered NUM and up. */ 536 537 void 538 cancel_changes (int num) 539 { 540 int i; 541 542 /* Back out all the changes. Do this in the opposite order in which 543 they were made. */ 544 for (i = num_changes - 1; i >= num; i--) 545 { 546 *changes[i].loc = changes[i].old; 547 if (changes[i].object && !MEM_P (changes[i].object)) 548 INSN_CODE (changes[i].object) = changes[i].old_code; 549 } 550 num_changes = num; 551 } 552 553 /* Reduce conditional compilation elsewhere. */ 554 /* A subroutine of validate_replace_rtx_1 that tries to simplify the resulting 555 rtx. */ 556 557 static void 558 simplify_while_replacing (rtx *loc, rtx to, rtx_insn *object, 559 machine_mode op0_mode) 560 { 561 rtx x = *loc; 562 enum rtx_code code = GET_CODE (x); 563 rtx new_rtx = NULL_RTX; 564 scalar_int_mode is_mode; 565 566 if (SWAPPABLE_OPERANDS_P (x) 567 && swap_commutative_operands_p (XEXP (x, 0), XEXP (x, 1))) 568 { 569 validate_unshare_change (object, loc, 570 gen_rtx_fmt_ee (COMMUTATIVE_ARITH_P (x) ? code 571 : swap_condition (code), 572 GET_MODE (x), XEXP (x, 1), 573 XEXP (x, 0)), 1); 574 x = *loc; 575 code = GET_CODE (x); 576 } 577 578 /* Canonicalize arithmetics with all constant operands. */ 579 switch (GET_RTX_CLASS (code)) 580 { 581 case RTX_UNARY: 582 if (CONSTANT_P (XEXP (x, 0))) 583 new_rtx = simplify_unary_operation (code, GET_MODE (x), XEXP (x, 0), 584 op0_mode); 585 break; 586 case RTX_COMM_ARITH: 587 case RTX_BIN_ARITH: 588 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1))) 589 new_rtx = simplify_binary_operation (code, GET_MODE (x), XEXP (x, 0), 590 XEXP (x, 1)); 591 break; 592 case RTX_COMPARE: 593 case RTX_COMM_COMPARE: 594 if (CONSTANT_P (XEXP (x, 0)) && CONSTANT_P (XEXP (x, 1))) 595 new_rtx = simplify_relational_operation (code, GET_MODE (x), op0_mode, 596 XEXP (x, 0), XEXP (x, 1)); 597 break; 598 default: 599 break; 600 } 601 if (new_rtx) 602 { 603 validate_change (object, loc, new_rtx, 1); 604 return; 605 } 606 607 switch (code) 608 { 609 case PLUS: 610 /* If we have a PLUS whose second operand is now a CONST_INT, use 611 simplify_gen_binary to try to simplify it. 612 ??? We may want later to remove this, once simplification is 613 separated from this function. */ 614 if (CONST_INT_P (XEXP (x, 1)) && XEXP (x, 1) == to) 615 validate_change (object, loc, 616 simplify_gen_binary 617 (PLUS, GET_MODE (x), XEXP (x, 0), XEXP (x, 1)), 1); 618 break; 619 case MINUS: 620 if (CONST_SCALAR_INT_P (XEXP (x, 1))) 621 validate_change (object, loc, 622 simplify_gen_binary 623 (PLUS, GET_MODE (x), XEXP (x, 0), 624 simplify_gen_unary (NEG, 625 GET_MODE (x), XEXP (x, 1), 626 GET_MODE (x))), 1); 627 break; 628 case ZERO_EXTEND: 629 case SIGN_EXTEND: 630 if (GET_MODE (XEXP (x, 0)) == VOIDmode) 631 { 632 new_rtx = simplify_gen_unary (code, GET_MODE (x), XEXP (x, 0), 633 op0_mode); 634 /* If any of the above failed, substitute in something that 635 we know won't be recognized. */ 636 if (!new_rtx) 637 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 638 validate_change (object, loc, new_rtx, 1); 639 } 640 break; 641 case SUBREG: 642 /* All subregs possible to simplify should be simplified. */ 643 new_rtx = simplify_subreg (GET_MODE (x), SUBREG_REG (x), op0_mode, 644 SUBREG_BYTE (x)); 645 646 /* Subregs of VOIDmode operands are incorrect. */ 647 if (!new_rtx && GET_MODE (SUBREG_REG (x)) == VOIDmode) 648 new_rtx = gen_rtx_CLOBBER (GET_MODE (x), const0_rtx); 649 if (new_rtx) 650 validate_change (object, loc, new_rtx, 1); 651 break; 652 case ZERO_EXTRACT: 653 case SIGN_EXTRACT: 654 /* If we are replacing a register with memory, try to change the memory 655 to be the mode required for memory in extract operations (this isn't 656 likely to be an insertion operation; if it was, nothing bad will 657 happen, we might just fail in some cases). */ 658 659 if (MEM_P (XEXP (x, 0)) 660 && is_a <scalar_int_mode> (GET_MODE (XEXP (x, 0)), &is_mode) 661 && CONST_INT_P (XEXP (x, 1)) 662 && CONST_INT_P (XEXP (x, 2)) 663 && !mode_dependent_address_p (XEXP (XEXP (x, 0), 0), 664 MEM_ADDR_SPACE (XEXP (x, 0))) 665 && !MEM_VOLATILE_P (XEXP (x, 0))) 666 { 667 int pos = INTVAL (XEXP (x, 2)); 668 machine_mode new_mode = is_mode; 669 if (GET_CODE (x) == ZERO_EXTRACT && targetm.have_extzv ()) 670 new_mode = insn_data[targetm.code_for_extzv].operand[1].mode; 671 else if (GET_CODE (x) == SIGN_EXTRACT && targetm.have_extv ()) 672 new_mode = insn_data[targetm.code_for_extv].operand[1].mode; 673 scalar_int_mode wanted_mode = (new_mode == VOIDmode 674 ? word_mode 675 : as_a <scalar_int_mode> (new_mode)); 676 677 /* If we have a narrower mode, we can do something. */ 678 if (GET_MODE_SIZE (wanted_mode) < GET_MODE_SIZE (is_mode)) 679 { 680 int offset = pos / BITS_PER_UNIT; 681 rtx newmem; 682 683 /* If the bytes and bits are counted differently, we 684 must adjust the offset. */ 685 if (BYTES_BIG_ENDIAN != BITS_BIG_ENDIAN) 686 offset = 687 (GET_MODE_SIZE (is_mode) - GET_MODE_SIZE (wanted_mode) - 688 offset); 689 690 gcc_assert (GET_MODE_PRECISION (wanted_mode) 691 == GET_MODE_BITSIZE (wanted_mode)); 692 pos %= GET_MODE_BITSIZE (wanted_mode); 693 694 newmem = adjust_address_nv (XEXP (x, 0), wanted_mode, offset); 695 696 validate_change (object, &XEXP (x, 2), GEN_INT (pos), 1); 697 validate_change (object, &XEXP (x, 0), newmem, 1); 698 } 699 } 700 701 break; 702 703 default: 704 break; 705 } 706 } 707 708 /* Replace every occurrence of FROM in X with TO. Mark each change with 709 validate_change passing OBJECT. */ 710 711 static void 712 validate_replace_rtx_1 (rtx *loc, rtx from, rtx to, rtx_insn *object, 713 bool simplify) 714 { 715 int i, j; 716 const char *fmt; 717 rtx x = *loc; 718 enum rtx_code code; 719 machine_mode op0_mode = VOIDmode; 720 int prev_changes = num_changes; 721 722 if (!x) 723 return; 724 725 code = GET_CODE (x); 726 fmt = GET_RTX_FORMAT (code); 727 if (fmt[0] == 'e') 728 op0_mode = GET_MODE (XEXP (x, 0)); 729 730 /* X matches FROM if it is the same rtx or they are both referring to the 731 same register in the same mode. Avoid calling rtx_equal_p unless the 732 operands look similar. */ 733 734 if (x == from 735 || (REG_P (x) && REG_P (from) 736 && GET_MODE (x) == GET_MODE (from) 737 && REGNO (x) == REGNO (from)) 738 || (GET_CODE (x) == GET_CODE (from) && GET_MODE (x) == GET_MODE (from) 739 && rtx_equal_p (x, from))) 740 { 741 validate_unshare_change (object, loc, to, 1); 742 return; 743 } 744 745 /* Call ourself recursively to perform the replacements. 746 We must not replace inside already replaced expression, otherwise we 747 get infinite recursion for replacements like (reg X)->(subreg (reg X)) 748 so we must special case shared ASM_OPERANDS. */ 749 750 if (GET_CODE (x) == PARALLEL) 751 { 752 for (j = XVECLEN (x, 0) - 1; j >= 0; j--) 753 { 754 if (j && GET_CODE (XVECEXP (x, 0, j)) == SET 755 && GET_CODE (SET_SRC (XVECEXP (x, 0, j))) == ASM_OPERANDS) 756 { 757 /* Verify that operands are really shared. */ 758 gcc_assert (ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP (x, 0, 0))) 759 == ASM_OPERANDS_INPUT_VEC (SET_SRC (XVECEXP 760 (x, 0, j)))); 761 validate_replace_rtx_1 (&SET_DEST (XVECEXP (x, 0, j)), 762 from, to, object, simplify); 763 } 764 else 765 validate_replace_rtx_1 (&XVECEXP (x, 0, j), from, to, object, 766 simplify); 767 } 768 } 769 else 770 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 771 { 772 if (fmt[i] == 'e') 773 validate_replace_rtx_1 (&XEXP (x, i), from, to, object, simplify); 774 else if (fmt[i] == 'E') 775 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 776 validate_replace_rtx_1 (&XVECEXP (x, i, j), from, to, object, 777 simplify); 778 } 779 780 /* If we didn't substitute, there is nothing more to do. */ 781 if (num_changes == prev_changes) 782 return; 783 784 /* ??? The regmove is no more, so is this aberration still necessary? */ 785 /* Allow substituted expression to have different mode. This is used by 786 regmove to change mode of pseudo register. */ 787 if (fmt[0] == 'e' && GET_MODE (XEXP (x, 0)) != VOIDmode) 788 op0_mode = GET_MODE (XEXP (x, 0)); 789 790 /* Do changes needed to keep rtx consistent. Don't do any other 791 simplifications, as it is not our job. */ 792 if (simplify) 793 simplify_while_replacing (loc, to, object, op0_mode); 794 } 795 796 /* Try replacing every occurrence of FROM in subexpression LOC of INSN 797 with TO. After all changes have been made, validate by seeing 798 if INSN is still valid. */ 799 800 int 801 validate_replace_rtx_subexp (rtx from, rtx to, rtx_insn *insn, rtx *loc) 802 { 803 validate_replace_rtx_1 (loc, from, to, insn, true); 804 return apply_change_group (); 805 } 806 807 /* Try replacing every occurrence of FROM in INSN with TO. After all 808 changes have been made, validate by seeing if INSN is still valid. */ 809 810 int 811 validate_replace_rtx (rtx from, rtx to, rtx_insn *insn) 812 { 813 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true); 814 return apply_change_group (); 815 } 816 817 /* Try replacing every occurrence of FROM in WHERE with TO. Assume that WHERE 818 is a part of INSN. After all changes have been made, validate by seeing if 819 INSN is still valid. 820 validate_replace_rtx (from, to, insn) is equivalent to 821 validate_replace_rtx_part (from, to, &PATTERN (insn), insn). */ 822 823 int 824 validate_replace_rtx_part (rtx from, rtx to, rtx *where, rtx_insn *insn) 825 { 826 validate_replace_rtx_1 (where, from, to, insn, true); 827 return apply_change_group (); 828 } 829 830 /* Same as above, but do not simplify rtx afterwards. */ 831 int 832 validate_replace_rtx_part_nosimplify (rtx from, rtx to, rtx *where, 833 rtx_insn *insn) 834 { 835 validate_replace_rtx_1 (where, from, to, insn, false); 836 return apply_change_group (); 837 838 } 839 840 /* Try replacing every occurrence of FROM in INSN with TO. This also 841 will replace in REG_EQUAL and REG_EQUIV notes. */ 842 843 void 844 validate_replace_rtx_group (rtx from, rtx to, rtx_insn *insn) 845 { 846 rtx note; 847 validate_replace_rtx_1 (&PATTERN (insn), from, to, insn, true); 848 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 849 if (REG_NOTE_KIND (note) == REG_EQUAL 850 || REG_NOTE_KIND (note) == REG_EQUIV) 851 validate_replace_rtx_1 (&XEXP (note, 0), from, to, insn, true); 852 } 853 854 /* Function called by note_uses to replace used subexpressions. */ 855 struct validate_replace_src_data 856 { 857 rtx from; /* Old RTX */ 858 rtx to; /* New RTX */ 859 rtx_insn *insn; /* Insn in which substitution is occurring. */ 860 }; 861 862 static void 863 validate_replace_src_1 (rtx *x, void *data) 864 { 865 struct validate_replace_src_data *d 866 = (struct validate_replace_src_data *) data; 867 868 validate_replace_rtx_1 (x, d->from, d->to, d->insn, true); 869 } 870 871 /* Try replacing every occurrence of FROM in INSN with TO, avoiding 872 SET_DESTs. */ 873 874 void 875 validate_replace_src_group (rtx from, rtx to, rtx_insn *insn) 876 { 877 struct validate_replace_src_data d; 878 879 d.from = from; 880 d.to = to; 881 d.insn = insn; 882 note_uses (&PATTERN (insn), validate_replace_src_1, &d); 883 } 884 885 /* Try simplify INSN. 886 Invoke simplify_rtx () on every SET_SRC and SET_DEST inside the INSN's 887 pattern and return true if something was simplified. */ 888 889 bool 890 validate_simplify_insn (rtx_insn *insn) 891 { 892 int i; 893 rtx pat = NULL; 894 rtx newpat = NULL; 895 896 pat = PATTERN (insn); 897 898 if (GET_CODE (pat) == SET) 899 { 900 newpat = simplify_rtx (SET_SRC (pat)); 901 if (newpat && !rtx_equal_p (SET_SRC (pat), newpat)) 902 validate_change (insn, &SET_SRC (pat), newpat, 1); 903 newpat = simplify_rtx (SET_DEST (pat)); 904 if (newpat && !rtx_equal_p (SET_DEST (pat), newpat)) 905 validate_change (insn, &SET_DEST (pat), newpat, 1); 906 } 907 else if (GET_CODE (pat) == PARALLEL) 908 for (i = 0; i < XVECLEN (pat, 0); i++) 909 { 910 rtx s = XVECEXP (pat, 0, i); 911 912 if (GET_CODE (XVECEXP (pat, 0, i)) == SET) 913 { 914 newpat = simplify_rtx (SET_SRC (s)); 915 if (newpat && !rtx_equal_p (SET_SRC (s), newpat)) 916 validate_change (insn, &SET_SRC (s), newpat, 1); 917 newpat = simplify_rtx (SET_DEST (s)); 918 if (newpat && !rtx_equal_p (SET_DEST (s), newpat)) 919 validate_change (insn, &SET_DEST (s), newpat, 1); 920 } 921 } 922 return ((num_changes_pending () > 0) && (apply_change_group () > 0)); 923 } 924 925 /* Return 1 if the insn using CC0 set by INSN does not contain 926 any ordered tests applied to the condition codes. 927 EQ and NE tests do not count. */ 928 929 int 930 next_insn_tests_no_inequality (rtx_insn *insn) 931 { 932 rtx_insn *next = next_cc0_user (insn); 933 934 /* If there is no next insn, we have to take the conservative choice. */ 935 if (next == 0) 936 return 0; 937 938 return (INSN_P (next) 939 && ! inequality_comparisons_p (PATTERN (next))); 940 } 941 942 /* Return 1 if OP is a valid general operand for machine mode MODE. 943 This is either a register reference, a memory reference, 944 or a constant. In the case of a memory reference, the address 945 is checked for general validity for the target machine. 946 947 Register and memory references must have mode MODE in order to be valid, 948 but some constants have no machine mode and are valid for any mode. 949 950 If MODE is VOIDmode, OP is checked for validity for whatever mode 951 it has. 952 953 The main use of this function is as a predicate in match_operand 954 expressions in the machine description. */ 955 956 int 957 general_operand (rtx op, machine_mode mode) 958 { 959 enum rtx_code code = GET_CODE (op); 960 961 if (mode == VOIDmode) 962 mode = GET_MODE (op); 963 964 /* Don't accept CONST_INT or anything similar 965 if the caller wants something floating. */ 966 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 967 && GET_MODE_CLASS (mode) != MODE_INT 968 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 969 return 0; 970 971 if (CONST_INT_P (op) 972 && mode != VOIDmode 973 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) 974 return 0; 975 976 if (CONSTANT_P (op)) 977 return ((GET_MODE (op) == VOIDmode || GET_MODE (op) == mode 978 || mode == VOIDmode) 979 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 980 && targetm.legitimate_constant_p (mode == VOIDmode 981 ? GET_MODE (op) 982 : mode, op)); 983 984 /* Except for certain constants with VOIDmode, already checked for, 985 OP's mode must match MODE if MODE specifies a mode. */ 986 987 if (GET_MODE (op) != mode) 988 return 0; 989 990 if (code == SUBREG) 991 { 992 rtx sub = SUBREG_REG (op); 993 994 #ifdef INSN_SCHEDULING 995 /* On machines that have insn scheduling, we want all memory 996 reference to be explicit, so outlaw paradoxical SUBREGs. 997 However, we must allow them after reload so that they can 998 get cleaned up by cleanup_subreg_operands. */ 999 if (!reload_completed && MEM_P (sub) 1000 && paradoxical_subreg_p (op)) 1001 return 0; 1002 #endif 1003 /* Avoid memories with nonzero SUBREG_BYTE, as offsetting the memory 1004 may result in incorrect reference. We should simplify all valid 1005 subregs of MEM anyway. But allow this after reload because we 1006 might be called from cleanup_subreg_operands. 1007 1008 ??? This is a kludge. */ 1009 if (!reload_completed 1010 && maybe_ne (SUBREG_BYTE (op), 0) 1011 && MEM_P (sub)) 1012 return 0; 1013 1014 if (REG_P (sub) 1015 && REGNO (sub) < FIRST_PSEUDO_REGISTER 1016 && !REG_CAN_CHANGE_MODE_P (REGNO (sub), GET_MODE (sub), mode) 1017 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_INT 1018 && GET_MODE_CLASS (GET_MODE (sub)) != MODE_COMPLEX_FLOAT 1019 /* LRA can generate some invalid SUBREGS just for matched 1020 operand reload presentation. LRA needs to treat them as 1021 valid. */ 1022 && ! LRA_SUBREG_P (op)) 1023 return 0; 1024 1025 /* FLOAT_MODE subregs can't be paradoxical. Combine will occasionally 1026 create such rtl, and we must reject it. */ 1027 if (SCALAR_FLOAT_MODE_P (GET_MODE (op)) 1028 /* LRA can use subreg to store a floating point value in an 1029 integer mode. Although the floating point and the 1030 integer modes need the same number of hard registers, the 1031 size of floating point mode can be less than the integer 1032 mode. */ 1033 && ! lra_in_progress 1034 && paradoxical_subreg_p (op)) 1035 return 0; 1036 1037 op = sub; 1038 code = GET_CODE (op); 1039 } 1040 1041 if (code == REG) 1042 return (REGNO (op) >= FIRST_PSEUDO_REGISTER 1043 || in_hard_reg_set_p (operand_reg_set, GET_MODE (op), REGNO (op))); 1044 1045 if (code == MEM) 1046 { 1047 rtx y = XEXP (op, 0); 1048 1049 if (! volatile_ok && MEM_VOLATILE_P (op)) 1050 return 0; 1051 1052 /* Use the mem's mode, since it will be reloaded thus. LRA can 1053 generate move insn with invalid addresses which is made valid 1054 and efficiently calculated by LRA through further numerous 1055 transformations. */ 1056 if (lra_in_progress 1057 || memory_address_addr_space_p (GET_MODE (op), y, MEM_ADDR_SPACE (op))) 1058 return 1; 1059 } 1060 1061 return 0; 1062 } 1063 1064 /* Return 1 if OP is a valid memory address for a memory reference 1065 of mode MODE. 1066 1067 The main use of this function is as a predicate in match_operand 1068 expressions in the machine description. */ 1069 1070 int 1071 address_operand (rtx op, machine_mode mode) 1072 { 1073 /* Wrong mode for an address expr. */ 1074 if (GET_MODE (op) != VOIDmode 1075 && ! SCALAR_INT_MODE_P (GET_MODE (op))) 1076 return false; 1077 1078 return memory_address_p (mode, op); 1079 } 1080 1081 /* Return 1 if OP is a register reference of mode MODE. 1082 If MODE is VOIDmode, accept a register in any mode. 1083 1084 The main use of this function is as a predicate in match_operand 1085 expressions in the machine description. */ 1086 1087 int 1088 register_operand (rtx op, machine_mode mode) 1089 { 1090 if (GET_CODE (op) == SUBREG) 1091 { 1092 rtx sub = SUBREG_REG (op); 1093 1094 /* Before reload, we can allow (SUBREG (MEM...)) as a register operand 1095 because it is guaranteed to be reloaded into one. 1096 Just make sure the MEM is valid in itself. 1097 (Ideally, (SUBREG (MEM)...) should not exist after reload, 1098 but currently it does result from (SUBREG (REG)...) where the 1099 reg went on the stack.) */ 1100 if (!REG_P (sub) && (reload_completed || !MEM_P (sub))) 1101 return 0; 1102 } 1103 else if (!REG_P (op)) 1104 return 0; 1105 return general_operand (op, mode); 1106 } 1107 1108 /* Return 1 for a register in Pmode; ignore the tested mode. */ 1109 1110 int 1111 pmode_register_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) 1112 { 1113 return register_operand (op, Pmode); 1114 } 1115 1116 /* Return 1 if OP should match a MATCH_SCRATCH, i.e., if it is a SCRATCH 1117 or a hard register. */ 1118 1119 int 1120 scratch_operand (rtx op, machine_mode mode) 1121 { 1122 if (GET_MODE (op) != mode && mode != VOIDmode) 1123 return 0; 1124 1125 return (GET_CODE (op) == SCRATCH 1126 || (REG_P (op) 1127 && (lra_in_progress 1128 || (REGNO (op) < FIRST_PSEUDO_REGISTER 1129 && REGNO_REG_CLASS (REGNO (op)) != NO_REGS)))); 1130 } 1131 1132 /* Return 1 if OP is a valid immediate operand for mode MODE. 1133 1134 The main use of this function is as a predicate in match_operand 1135 expressions in the machine description. */ 1136 1137 int 1138 immediate_operand (rtx op, machine_mode mode) 1139 { 1140 /* Don't accept CONST_INT or anything similar 1141 if the caller wants something floating. */ 1142 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1143 && GET_MODE_CLASS (mode) != MODE_INT 1144 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 1145 return 0; 1146 1147 if (CONST_INT_P (op) 1148 && mode != VOIDmode 1149 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) 1150 return 0; 1151 1152 return (CONSTANT_P (op) 1153 && (GET_MODE (op) == mode || mode == VOIDmode 1154 || GET_MODE (op) == VOIDmode) 1155 && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (op)) 1156 && targetm.legitimate_constant_p (mode == VOIDmode 1157 ? GET_MODE (op) 1158 : mode, op)); 1159 } 1160 1161 /* Returns 1 if OP is an operand that is a CONST_INT of mode MODE. */ 1162 1163 int 1164 const_int_operand (rtx op, machine_mode mode) 1165 { 1166 if (!CONST_INT_P (op)) 1167 return 0; 1168 1169 if (mode != VOIDmode 1170 && trunc_int_for_mode (INTVAL (op), mode) != INTVAL (op)) 1171 return 0; 1172 1173 return 1; 1174 } 1175 1176 #if TARGET_SUPPORTS_WIDE_INT 1177 /* Returns 1 if OP is an operand that is a CONST_INT or CONST_WIDE_INT 1178 of mode MODE. */ 1179 int 1180 const_scalar_int_operand (rtx op, machine_mode mode) 1181 { 1182 if (!CONST_SCALAR_INT_P (op)) 1183 return 0; 1184 1185 if (CONST_INT_P (op)) 1186 return const_int_operand (op, mode); 1187 1188 if (mode != VOIDmode) 1189 { 1190 scalar_int_mode int_mode = as_a <scalar_int_mode> (mode); 1191 int prec = GET_MODE_PRECISION (int_mode); 1192 int bitsize = GET_MODE_BITSIZE (int_mode); 1193 1194 if (CONST_WIDE_INT_NUNITS (op) * HOST_BITS_PER_WIDE_INT > bitsize) 1195 return 0; 1196 1197 if (prec == bitsize) 1198 return 1; 1199 else 1200 { 1201 /* Multiword partial int. */ 1202 HOST_WIDE_INT x 1203 = CONST_WIDE_INT_ELT (op, CONST_WIDE_INT_NUNITS (op) - 1); 1204 return (sext_hwi (x, prec & (HOST_BITS_PER_WIDE_INT - 1)) == x); 1205 } 1206 } 1207 return 1; 1208 } 1209 1210 /* Returns 1 if OP is an operand that is a constant integer or constant 1211 floating-point number of MODE. */ 1212 1213 int 1214 const_double_operand (rtx op, machine_mode mode) 1215 { 1216 return (GET_CODE (op) == CONST_DOUBLE) 1217 && (GET_MODE (op) == mode || mode == VOIDmode); 1218 } 1219 #else 1220 /* Returns 1 if OP is an operand that is a constant integer or constant 1221 floating-point number of MODE. */ 1222 1223 int 1224 const_double_operand (rtx op, machine_mode mode) 1225 { 1226 /* Don't accept CONST_INT or anything similar 1227 if the caller wants something floating. */ 1228 if (GET_MODE (op) == VOIDmode && mode != VOIDmode 1229 && GET_MODE_CLASS (mode) != MODE_INT 1230 && GET_MODE_CLASS (mode) != MODE_PARTIAL_INT) 1231 return 0; 1232 1233 return ((CONST_DOUBLE_P (op) || CONST_INT_P (op)) 1234 && (mode == VOIDmode || GET_MODE (op) == mode 1235 || GET_MODE (op) == VOIDmode)); 1236 } 1237 #endif 1238 /* Return 1 if OP is a general operand that is not an immediate 1239 operand of mode MODE. */ 1240 1241 int 1242 nonimmediate_operand (rtx op, machine_mode mode) 1243 { 1244 return (general_operand (op, mode) && ! CONSTANT_P (op)); 1245 } 1246 1247 /* Return 1 if OP is a register reference or immediate value of mode MODE. */ 1248 1249 int 1250 nonmemory_operand (rtx op, machine_mode mode) 1251 { 1252 if (CONSTANT_P (op)) 1253 return immediate_operand (op, mode); 1254 return register_operand (op, mode); 1255 } 1256 1257 /* Return 1 if OP is a valid operand that stands for pushing a 1258 value of mode MODE onto the stack. 1259 1260 The main use of this function is as a predicate in match_operand 1261 expressions in the machine description. */ 1262 1263 int 1264 push_operand (rtx op, machine_mode mode) 1265 { 1266 if (!MEM_P (op)) 1267 return 0; 1268 1269 if (mode != VOIDmode && GET_MODE (op) != mode) 1270 return 0; 1271 1272 poly_int64 rounded_size = GET_MODE_SIZE (mode); 1273 1274 #ifdef PUSH_ROUNDING 1275 rounded_size = PUSH_ROUNDING (MACRO_INT (rounded_size)); 1276 #endif 1277 1278 op = XEXP (op, 0); 1279 1280 if (known_eq (rounded_size, GET_MODE_SIZE (mode))) 1281 { 1282 if (GET_CODE (op) != STACK_PUSH_CODE) 1283 return 0; 1284 } 1285 else 1286 { 1287 poly_int64 offset; 1288 if (GET_CODE (op) != PRE_MODIFY 1289 || GET_CODE (XEXP (op, 1)) != PLUS 1290 || XEXP (XEXP (op, 1), 0) != XEXP (op, 0) 1291 || !poly_int_rtx_p (XEXP (XEXP (op, 1), 1), &offset) 1292 || (STACK_GROWS_DOWNWARD 1293 ? maybe_ne (offset, -rounded_size) 1294 : maybe_ne (offset, rounded_size))) 1295 return 0; 1296 } 1297 1298 return XEXP (op, 0) == stack_pointer_rtx; 1299 } 1300 1301 /* Return 1 if OP is a valid operand that stands for popping a 1302 value of mode MODE off the stack. 1303 1304 The main use of this function is as a predicate in match_operand 1305 expressions in the machine description. */ 1306 1307 int 1308 pop_operand (rtx op, machine_mode mode) 1309 { 1310 if (!MEM_P (op)) 1311 return 0; 1312 1313 if (mode != VOIDmode && GET_MODE (op) != mode) 1314 return 0; 1315 1316 op = XEXP (op, 0); 1317 1318 if (GET_CODE (op) != STACK_POP_CODE) 1319 return 0; 1320 1321 return XEXP (op, 0) == stack_pointer_rtx; 1322 } 1323 1324 /* Return 1 if ADDR is a valid memory address 1325 for mode MODE in address space AS. */ 1326 1327 int 1328 memory_address_addr_space_p (machine_mode mode ATTRIBUTE_UNUSED, 1329 rtx addr, addr_space_t as) 1330 { 1331 #ifdef GO_IF_LEGITIMATE_ADDRESS 1332 gcc_assert (ADDR_SPACE_GENERIC_P (as)); 1333 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); 1334 return 0; 1335 1336 win: 1337 return 1; 1338 #else 1339 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); 1340 #endif 1341 } 1342 1343 /* Return 1 if OP is a valid memory reference with mode MODE, 1344 including a valid address. 1345 1346 The main use of this function is as a predicate in match_operand 1347 expressions in the machine description. */ 1348 1349 int 1350 memory_operand (rtx op, machine_mode mode) 1351 { 1352 rtx inner; 1353 1354 if (! reload_completed) 1355 /* Note that no SUBREG is a memory operand before end of reload pass, 1356 because (SUBREG (MEM...)) forces reloading into a register. */ 1357 return MEM_P (op) && general_operand (op, mode); 1358 1359 if (mode != VOIDmode && GET_MODE (op) != mode) 1360 return 0; 1361 1362 inner = op; 1363 if (GET_CODE (inner) == SUBREG) 1364 inner = SUBREG_REG (inner); 1365 1366 return (MEM_P (inner) && general_operand (op, mode)); 1367 } 1368 1369 /* Return 1 if OP is a valid indirect memory reference with mode MODE; 1370 that is, a memory reference whose address is a general_operand. */ 1371 1372 int 1373 indirect_operand (rtx op, machine_mode mode) 1374 { 1375 /* Before reload, a SUBREG isn't in memory (see memory_operand, above). */ 1376 if (! reload_completed 1377 && GET_CODE (op) == SUBREG && MEM_P (SUBREG_REG (op))) 1378 { 1379 if (mode != VOIDmode && GET_MODE (op) != mode) 1380 return 0; 1381 1382 /* The only way that we can have a general_operand as the resulting 1383 address is if OFFSET is zero and the address already is an operand 1384 or if the address is (plus Y (const_int -OFFSET)) and Y is an 1385 operand. */ 1386 poly_int64 offset; 1387 rtx addr = strip_offset (XEXP (SUBREG_REG (op), 0), &offset); 1388 return (known_eq (offset + SUBREG_BYTE (op), 0) 1389 && general_operand (addr, Pmode)); 1390 } 1391 1392 return (MEM_P (op) 1393 && memory_operand (op, mode) 1394 && general_operand (XEXP (op, 0), Pmode)); 1395 } 1396 1397 /* Return 1 if this is an ordered comparison operator (not including 1398 ORDERED and UNORDERED). */ 1399 1400 int 1401 ordered_comparison_operator (rtx op, machine_mode mode) 1402 { 1403 if (mode != VOIDmode && GET_MODE (op) != mode) 1404 return false; 1405 switch (GET_CODE (op)) 1406 { 1407 case EQ: 1408 case NE: 1409 case LT: 1410 case LTU: 1411 case LE: 1412 case LEU: 1413 case GT: 1414 case GTU: 1415 case GE: 1416 case GEU: 1417 return true; 1418 default: 1419 return false; 1420 } 1421 } 1422 1423 /* Return 1 if this is a comparison operator. This allows the use of 1424 MATCH_OPERATOR to recognize all the branch insns. */ 1425 1426 int 1427 comparison_operator (rtx op, machine_mode mode) 1428 { 1429 return ((mode == VOIDmode || GET_MODE (op) == mode) 1430 && COMPARISON_P (op)); 1431 } 1432 1433 /* If BODY is an insn body that uses ASM_OPERANDS, return it. */ 1434 1435 rtx 1436 extract_asm_operands (rtx body) 1437 { 1438 rtx tmp; 1439 switch (GET_CODE (body)) 1440 { 1441 case ASM_OPERANDS: 1442 return body; 1443 1444 case SET: 1445 /* Single output operand: BODY is (set OUTPUT (asm_operands ...)). */ 1446 tmp = SET_SRC (body); 1447 if (GET_CODE (tmp) == ASM_OPERANDS) 1448 return tmp; 1449 break; 1450 1451 case PARALLEL: 1452 tmp = XVECEXP (body, 0, 0); 1453 if (GET_CODE (tmp) == ASM_OPERANDS) 1454 return tmp; 1455 if (GET_CODE (tmp) == SET) 1456 { 1457 tmp = SET_SRC (tmp); 1458 if (GET_CODE (tmp) == ASM_OPERANDS) 1459 return tmp; 1460 } 1461 break; 1462 1463 default: 1464 break; 1465 } 1466 return NULL; 1467 } 1468 1469 /* If BODY is an insn body that uses ASM_OPERANDS, 1470 return the number of operands (both input and output) in the insn. 1471 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL, 1472 return 0. 1473 Otherwise return -1. */ 1474 1475 int 1476 asm_noperands (const_rtx body) 1477 { 1478 rtx asm_op = extract_asm_operands (CONST_CAST_RTX (body)); 1479 int i, n_sets = 0; 1480 1481 if (asm_op == NULL) 1482 { 1483 if (GET_CODE (body) == PARALLEL && XVECLEN (body, 0) >= 2 1484 && GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT) 1485 { 1486 /* body is [(asm_input ...) (clobber (reg ...))...]. */ 1487 for (i = XVECLEN (body, 0) - 1; i > 0; i--) 1488 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) 1489 return -1; 1490 return 0; 1491 } 1492 return -1; 1493 } 1494 1495 if (GET_CODE (body) == SET) 1496 n_sets = 1; 1497 else if (GET_CODE (body) == PARALLEL) 1498 { 1499 if (GET_CODE (XVECEXP (body, 0, 0)) == SET) 1500 { 1501 /* Multiple output operands, or 1 output plus some clobbers: 1502 body is 1503 [(set OUTPUT (asm_operands ...))... (clobber (reg ...))...]. */ 1504 /* Count backwards through CLOBBERs to determine number of SETs. */ 1505 for (i = XVECLEN (body, 0); i > 0; i--) 1506 { 1507 if (GET_CODE (XVECEXP (body, 0, i - 1)) == SET) 1508 break; 1509 if (GET_CODE (XVECEXP (body, 0, i - 1)) != CLOBBER) 1510 return -1; 1511 } 1512 1513 /* N_SETS is now number of output operands. */ 1514 n_sets = i; 1515 1516 /* Verify that all the SETs we have 1517 came from a single original asm_operands insn 1518 (so that invalid combinations are blocked). */ 1519 for (i = 0; i < n_sets; i++) 1520 { 1521 rtx elt = XVECEXP (body, 0, i); 1522 if (GET_CODE (elt) != SET) 1523 return -1; 1524 if (GET_CODE (SET_SRC (elt)) != ASM_OPERANDS) 1525 return -1; 1526 /* If these ASM_OPERANDS rtx's came from different original insns 1527 then they aren't allowed together. */ 1528 if (ASM_OPERANDS_INPUT_VEC (SET_SRC (elt)) 1529 != ASM_OPERANDS_INPUT_VEC (asm_op)) 1530 return -1; 1531 } 1532 } 1533 else 1534 { 1535 /* 0 outputs, but some clobbers: 1536 body is [(asm_operands ...) (clobber (reg ...))...]. */ 1537 /* Make sure all the other parallel things really are clobbers. */ 1538 for (i = XVECLEN (body, 0) - 1; i > 0; i--) 1539 if (GET_CODE (XVECEXP (body, 0, i)) != CLOBBER) 1540 return -1; 1541 } 1542 } 1543 1544 return (ASM_OPERANDS_INPUT_LENGTH (asm_op) 1545 + ASM_OPERANDS_LABEL_LENGTH (asm_op) + n_sets); 1546 } 1547 1548 /* Assuming BODY is an insn body that uses ASM_OPERANDS, 1549 copy its operands (both input and output) into the vector OPERANDS, 1550 the locations of the operands within the insn into the vector OPERAND_LOCS, 1551 and the constraints for the operands into CONSTRAINTS. 1552 Write the modes of the operands into MODES. 1553 Write the location info into LOC. 1554 Return the assembler-template. 1555 If BODY is an insn body that uses ASM_INPUT with CLOBBERS in PARALLEL, 1556 return the basic assembly string. 1557 1558 If LOC, MODES, OPERAND_LOCS, CONSTRAINTS or OPERANDS is 0, 1559 we don't store that info. */ 1560 1561 const char * 1562 decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs, 1563 const char **constraints, machine_mode *modes, 1564 location_t *loc) 1565 { 1566 int nbase = 0, n, i; 1567 rtx asmop; 1568 1569 switch (GET_CODE (body)) 1570 { 1571 case ASM_OPERANDS: 1572 /* Zero output asm: BODY is (asm_operands ...). */ 1573 asmop = body; 1574 break; 1575 1576 case SET: 1577 /* Single output asm: BODY is (set OUTPUT (asm_operands ...)). */ 1578 asmop = SET_SRC (body); 1579 1580 /* The output is in the SET. 1581 Its constraint is in the ASM_OPERANDS itself. */ 1582 if (operands) 1583 operands[0] = SET_DEST (body); 1584 if (operand_locs) 1585 operand_locs[0] = &SET_DEST (body); 1586 if (constraints) 1587 constraints[0] = ASM_OPERANDS_OUTPUT_CONSTRAINT (asmop); 1588 if (modes) 1589 modes[0] = GET_MODE (SET_DEST (body)); 1590 nbase = 1; 1591 break; 1592 1593 case PARALLEL: 1594 { 1595 int nparallel = XVECLEN (body, 0); /* Includes CLOBBERs. */ 1596 1597 asmop = XVECEXP (body, 0, 0); 1598 if (GET_CODE (asmop) == SET) 1599 { 1600 asmop = SET_SRC (asmop); 1601 1602 /* At least one output, plus some CLOBBERs. The outputs are in 1603 the SETs. Their constraints are in the ASM_OPERANDS itself. */ 1604 for (i = 0; i < nparallel; i++) 1605 { 1606 if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) 1607 break; /* Past last SET */ 1608 if (operands) 1609 operands[i] = SET_DEST (XVECEXP (body, 0, i)); 1610 if (operand_locs) 1611 operand_locs[i] = &SET_DEST (XVECEXP (body, 0, i)); 1612 if (constraints) 1613 constraints[i] = XSTR (SET_SRC (XVECEXP (body, 0, i)), 1); 1614 if (modes) 1615 modes[i] = GET_MODE (SET_DEST (XVECEXP (body, 0, i))); 1616 } 1617 nbase = i; 1618 } 1619 else if (GET_CODE (asmop) == ASM_INPUT) 1620 { 1621 if (loc) 1622 *loc = ASM_INPUT_SOURCE_LOCATION (asmop); 1623 return XSTR (asmop, 0); 1624 } 1625 break; 1626 } 1627 1628 default: 1629 gcc_unreachable (); 1630 } 1631 1632 n = ASM_OPERANDS_INPUT_LENGTH (asmop); 1633 for (i = 0; i < n; i++) 1634 { 1635 if (operand_locs) 1636 operand_locs[nbase + i] = &ASM_OPERANDS_INPUT (asmop, i); 1637 if (operands) 1638 operands[nbase + i] = ASM_OPERANDS_INPUT (asmop, i); 1639 if (constraints) 1640 constraints[nbase + i] = ASM_OPERANDS_INPUT_CONSTRAINT (asmop, i); 1641 if (modes) 1642 modes[nbase + i] = ASM_OPERANDS_INPUT_MODE (asmop, i); 1643 } 1644 nbase += n; 1645 1646 n = ASM_OPERANDS_LABEL_LENGTH (asmop); 1647 for (i = 0; i < n; i++) 1648 { 1649 if (operand_locs) 1650 operand_locs[nbase + i] = &ASM_OPERANDS_LABEL (asmop, i); 1651 if (operands) 1652 operands[nbase + i] = ASM_OPERANDS_LABEL (asmop, i); 1653 if (constraints) 1654 constraints[nbase + i] = ""; 1655 if (modes) 1656 modes[nbase + i] = Pmode; 1657 } 1658 1659 if (loc) 1660 *loc = ASM_OPERANDS_SOURCE_LOCATION (asmop); 1661 1662 return ASM_OPERANDS_TEMPLATE (asmop); 1663 } 1664 1665 /* Parse inline assembly string STRING and determine which operands are 1666 referenced by % markers. For the first NOPERANDS operands, set USED[I] 1667 to true if operand I is referenced. 1668 1669 This is intended to distinguish barrier-like asms such as: 1670 1671 asm ("" : "=m" (...)); 1672 1673 from real references such as: 1674 1675 asm ("sw\t$0, %0" : "=m" (...)); */ 1676 1677 void 1678 get_referenced_operands (const char *string, bool *used, 1679 unsigned int noperands) 1680 { 1681 memset (used, 0, sizeof (bool) * noperands); 1682 const char *p = string; 1683 while (*p) 1684 switch (*p) 1685 { 1686 case '%': 1687 p += 1; 1688 /* A letter followed by a digit indicates an operand number. */ 1689 if (ISALPHA (p[0]) && ISDIGIT (p[1])) 1690 p += 1; 1691 if (ISDIGIT (*p)) 1692 { 1693 char *endptr; 1694 unsigned long opnum = strtoul (p, &endptr, 10); 1695 if (endptr != p && opnum < noperands) 1696 used[opnum] = true; 1697 p = endptr; 1698 } 1699 else 1700 p += 1; 1701 break; 1702 1703 default: 1704 p++; 1705 break; 1706 } 1707 } 1708 1709 /* Check if an asm_operand matches its constraints. 1710 Return > 0 if ok, = 0 if bad, < 0 if inconclusive. */ 1711 1712 int 1713 asm_operand_ok (rtx op, const char *constraint, const char **constraints) 1714 { 1715 int result = 0; 1716 bool incdec_ok = false; 1717 1718 /* Use constrain_operands after reload. */ 1719 gcc_assert (!reload_completed); 1720 1721 /* Empty constraint string is the same as "X,...,X", i.e. X for as 1722 many alternatives as required to match the other operands. */ 1723 if (*constraint == '\0') 1724 result = 1; 1725 1726 while (*constraint) 1727 { 1728 enum constraint_num cn; 1729 char c = *constraint; 1730 int len; 1731 switch (c) 1732 { 1733 case ',': 1734 constraint++; 1735 continue; 1736 1737 case '0': case '1': case '2': case '3': case '4': 1738 case '5': case '6': case '7': case '8': case '9': 1739 /* If caller provided constraints pointer, look up 1740 the matching constraint. Otherwise, our caller should have 1741 given us the proper matching constraint, but we can't 1742 actually fail the check if they didn't. Indicate that 1743 results are inconclusive. */ 1744 if (constraints) 1745 { 1746 char *end; 1747 unsigned long match; 1748 1749 match = strtoul (constraint, &end, 10); 1750 if (!result) 1751 result = asm_operand_ok (op, constraints[match], NULL); 1752 constraint = (const char *) end; 1753 } 1754 else 1755 { 1756 do 1757 constraint++; 1758 while (ISDIGIT (*constraint)); 1759 if (! result) 1760 result = -1; 1761 } 1762 continue; 1763 1764 /* The rest of the compiler assumes that reloading the address 1765 of a MEM into a register will make it fit an 'o' constraint. 1766 That is, if it sees a MEM operand for an 'o' constraint, 1767 it assumes that (mem (base-reg)) will fit. 1768 1769 That assumption fails on targets that don't have offsettable 1770 addresses at all. We therefore need to treat 'o' asm 1771 constraints as a special case and only accept operands that 1772 are already offsettable, thus proving that at least one 1773 offsettable address exists. */ 1774 case 'o': /* offsettable */ 1775 if (offsettable_nonstrict_memref_p (op)) 1776 result = 1; 1777 break; 1778 1779 case 'g': 1780 if (general_operand (op, VOIDmode)) 1781 result = 1; 1782 break; 1783 1784 case '<': 1785 case '>': 1786 /* ??? Before auto-inc-dec, auto inc/dec insns are not supposed 1787 to exist, excepting those that expand_call created. Further, 1788 on some machines which do not have generalized auto inc/dec, 1789 an inc/dec is not a memory_operand. 1790 1791 Match any memory and hope things are resolved after reload. */ 1792 incdec_ok = true; 1793 /* FALLTHRU */ 1794 default: 1795 cn = lookup_constraint (constraint); 1796 switch (get_constraint_type (cn)) 1797 { 1798 case CT_REGISTER: 1799 if (!result 1800 && reg_class_for_constraint (cn) != NO_REGS 1801 && GET_MODE (op) != BLKmode 1802 && register_operand (op, VOIDmode)) 1803 result = 1; 1804 break; 1805 1806 case CT_CONST_INT: 1807 if (!result 1808 && CONST_INT_P (op) 1809 && insn_const_int_ok_for_constraint (INTVAL (op), cn)) 1810 result = 1; 1811 break; 1812 1813 case CT_MEMORY: 1814 case CT_SPECIAL_MEMORY: 1815 /* Every memory operand can be reloaded to fit. */ 1816 result = result || memory_operand (op, VOIDmode); 1817 break; 1818 1819 case CT_ADDRESS: 1820 /* Every address operand can be reloaded to fit. */ 1821 result = result || address_operand (op, VOIDmode); 1822 break; 1823 1824 case CT_FIXED_FORM: 1825 result = result || constraint_satisfied_p (op, cn); 1826 break; 1827 } 1828 break; 1829 } 1830 len = CONSTRAINT_LEN (c, constraint); 1831 do 1832 constraint++; 1833 while (--len && *constraint && *constraint != ','); 1834 if (len) 1835 return 0; 1836 } 1837 1838 /* For operands without < or > constraints reject side-effects. */ 1839 if (AUTO_INC_DEC && !incdec_ok && result && MEM_P (op)) 1840 switch (GET_CODE (XEXP (op, 0))) 1841 { 1842 case PRE_INC: 1843 case POST_INC: 1844 case PRE_DEC: 1845 case POST_DEC: 1846 case PRE_MODIFY: 1847 case POST_MODIFY: 1848 return 0; 1849 default: 1850 break; 1851 } 1852 1853 return result; 1854 } 1855 1856 /* Given an rtx *P, if it is a sum containing an integer constant term, 1857 return the location (type rtx *) of the pointer to that constant term. 1858 Otherwise, return a null pointer. */ 1859 1860 rtx * 1861 find_constant_term_loc (rtx *p) 1862 { 1863 rtx *tem; 1864 enum rtx_code code = GET_CODE (*p); 1865 1866 /* If *P IS such a constant term, P is its location. */ 1867 1868 if (code == CONST_INT || code == SYMBOL_REF || code == LABEL_REF 1869 || code == CONST) 1870 return p; 1871 1872 /* Otherwise, if not a sum, it has no constant term. */ 1873 1874 if (GET_CODE (*p) != PLUS) 1875 return 0; 1876 1877 /* If one of the summands is constant, return its location. */ 1878 1879 if (XEXP (*p, 0) && CONSTANT_P (XEXP (*p, 0)) 1880 && XEXP (*p, 1) && CONSTANT_P (XEXP (*p, 1))) 1881 return p; 1882 1883 /* Otherwise, check each summand for containing a constant term. */ 1884 1885 if (XEXP (*p, 0) != 0) 1886 { 1887 tem = find_constant_term_loc (&XEXP (*p, 0)); 1888 if (tem != 0) 1889 return tem; 1890 } 1891 1892 if (XEXP (*p, 1) != 0) 1893 { 1894 tem = find_constant_term_loc (&XEXP (*p, 1)); 1895 if (tem != 0) 1896 return tem; 1897 } 1898 1899 return 0; 1900 } 1901 1902 /* Return 1 if OP is a memory reference 1903 whose address contains no side effects 1904 and remains valid after the addition 1905 of a positive integer less than the 1906 size of the object being referenced. 1907 1908 We assume that the original address is valid and do not check it. 1909 1910 This uses strict_memory_address_p as a subroutine, so 1911 don't use it before reload. */ 1912 1913 int 1914 offsettable_memref_p (rtx op) 1915 { 1916 return ((MEM_P (op)) 1917 && offsettable_address_addr_space_p (1, GET_MODE (op), XEXP (op, 0), 1918 MEM_ADDR_SPACE (op))); 1919 } 1920 1921 /* Similar, but don't require a strictly valid mem ref: 1922 consider pseudo-regs valid as index or base regs. */ 1923 1924 int 1925 offsettable_nonstrict_memref_p (rtx op) 1926 { 1927 return ((MEM_P (op)) 1928 && offsettable_address_addr_space_p (0, GET_MODE (op), XEXP (op, 0), 1929 MEM_ADDR_SPACE (op))); 1930 } 1931 1932 /* Return 1 if Y is a memory address which contains no side effects 1933 and would remain valid for address space AS after the addition of 1934 a positive integer less than the size of that mode. 1935 1936 We assume that the original address is valid and do not check it. 1937 We do check that it is valid for narrower modes. 1938 1939 If STRICTP is nonzero, we require a strictly valid address, 1940 for the sake of use in reload.c. */ 1941 1942 int 1943 offsettable_address_addr_space_p (int strictp, machine_mode mode, rtx y, 1944 addr_space_t as) 1945 { 1946 enum rtx_code ycode = GET_CODE (y); 1947 rtx z; 1948 rtx y1 = y; 1949 rtx *y2; 1950 int (*addressp) (machine_mode, rtx, addr_space_t) = 1951 (strictp ? strict_memory_address_addr_space_p 1952 : memory_address_addr_space_p); 1953 poly_int64 mode_sz = GET_MODE_SIZE (mode); 1954 1955 if (CONSTANT_ADDRESS_P (y)) 1956 return 1; 1957 1958 /* Adjusting an offsettable address involves changing to a narrower mode. 1959 Make sure that's OK. */ 1960 1961 if (mode_dependent_address_p (y, as)) 1962 return 0; 1963 1964 machine_mode address_mode = GET_MODE (y); 1965 if (address_mode == VOIDmode) 1966 address_mode = targetm.addr_space.address_mode (as); 1967 #ifdef POINTERS_EXTEND_UNSIGNED 1968 machine_mode pointer_mode = targetm.addr_space.pointer_mode (as); 1969 #endif 1970 1971 /* ??? How much offset does an offsettable BLKmode reference need? 1972 Clearly that depends on the situation in which it's being used. 1973 However, the current situation in which we test 0xffffffff is 1974 less than ideal. Caveat user. */ 1975 if (known_eq (mode_sz, 0)) 1976 mode_sz = BIGGEST_ALIGNMENT / BITS_PER_UNIT; 1977 1978 /* If the expression contains a constant term, 1979 see if it remains valid when max possible offset is added. */ 1980 1981 if ((ycode == PLUS) && (y2 = find_constant_term_loc (&y1))) 1982 { 1983 int good; 1984 1985 y1 = *y2; 1986 *y2 = plus_constant (address_mode, *y2, mode_sz - 1); 1987 /* Use QImode because an odd displacement may be automatically invalid 1988 for any wider mode. But it should be valid for a single byte. */ 1989 good = (*addressp) (QImode, y, as); 1990 1991 /* In any case, restore old contents of memory. */ 1992 *y2 = y1; 1993 return good; 1994 } 1995 1996 if (GET_RTX_CLASS (ycode) == RTX_AUTOINC) 1997 return 0; 1998 1999 /* The offset added here is chosen as the maximum offset that 2000 any instruction could need to add when operating on something 2001 of the specified mode. We assume that if Y and Y+c are 2002 valid addresses then so is Y+d for all 0<d<c. adjust_address will 2003 go inside a LO_SUM here, so we do so as well. */ 2004 if (GET_CODE (y) == LO_SUM 2005 && mode != BLKmode 2006 && known_le (mode_sz, GET_MODE_ALIGNMENT (mode) / BITS_PER_UNIT)) 2007 z = gen_rtx_LO_SUM (address_mode, XEXP (y, 0), 2008 plus_constant (address_mode, XEXP (y, 1), 2009 mode_sz - 1)); 2010 #ifdef POINTERS_EXTEND_UNSIGNED 2011 /* Likewise for a ZERO_EXTEND from pointer_mode. */ 2012 else if (POINTERS_EXTEND_UNSIGNED > 0 2013 && GET_CODE (y) == ZERO_EXTEND 2014 && GET_MODE (XEXP (y, 0)) == pointer_mode) 2015 z = gen_rtx_ZERO_EXTEND (address_mode, 2016 plus_constant (pointer_mode, XEXP (y, 0), 2017 mode_sz - 1)); 2018 #endif 2019 else 2020 z = plus_constant (address_mode, y, mode_sz - 1); 2021 2022 /* Use QImode because an odd displacement may be automatically invalid 2023 for any wider mode. But it should be valid for a single byte. */ 2024 return (*addressp) (QImode, z, as); 2025 } 2026 2027 /* Return 1 if ADDR is an address-expression whose effect depends 2028 on the mode of the memory reference it is used in. 2029 2030 ADDRSPACE is the address space associated with the address. 2031 2032 Autoincrement addressing is a typical example of mode-dependence 2033 because the amount of the increment depends on the mode. */ 2034 2035 bool 2036 mode_dependent_address_p (rtx addr, addr_space_t addrspace) 2037 { 2038 /* Auto-increment addressing with anything other than post_modify 2039 or pre_modify always introduces a mode dependency. Catch such 2040 cases now instead of deferring to the target. */ 2041 if (GET_CODE (addr) == PRE_INC 2042 || GET_CODE (addr) == POST_INC 2043 || GET_CODE (addr) == PRE_DEC 2044 || GET_CODE (addr) == POST_DEC) 2045 return true; 2046 2047 return targetm.mode_dependent_address_p (addr, addrspace); 2048 } 2049 2050 /* Return true if boolean attribute ATTR is supported. */ 2051 2052 static bool 2053 have_bool_attr (bool_attr attr) 2054 { 2055 switch (attr) 2056 { 2057 case BA_ENABLED: 2058 return HAVE_ATTR_enabled; 2059 case BA_PREFERRED_FOR_SIZE: 2060 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_size; 2061 case BA_PREFERRED_FOR_SPEED: 2062 return HAVE_ATTR_enabled || HAVE_ATTR_preferred_for_speed; 2063 } 2064 gcc_unreachable (); 2065 } 2066 2067 /* Return the value of ATTR for instruction INSN. */ 2068 2069 static bool 2070 get_bool_attr (rtx_insn *insn, bool_attr attr) 2071 { 2072 switch (attr) 2073 { 2074 case BA_ENABLED: 2075 return get_attr_enabled (insn); 2076 case BA_PREFERRED_FOR_SIZE: 2077 return get_attr_enabled (insn) && get_attr_preferred_for_size (insn); 2078 case BA_PREFERRED_FOR_SPEED: 2079 return get_attr_enabled (insn) && get_attr_preferred_for_speed (insn); 2080 } 2081 gcc_unreachable (); 2082 } 2083 2084 /* Like get_bool_attr_mask, but don't use the cache. */ 2085 2086 static alternative_mask 2087 get_bool_attr_mask_uncached (rtx_insn *insn, bool_attr attr) 2088 { 2089 /* Temporarily install enough information for get_attr_<foo> to assume 2090 that the insn operands are already cached. As above, the attribute 2091 mustn't depend on the values of operands, so we don't provide their 2092 real values here. */ 2093 rtx_insn *old_insn = recog_data.insn; 2094 int old_alternative = which_alternative; 2095 2096 recog_data.insn = insn; 2097 alternative_mask mask = ALL_ALTERNATIVES; 2098 int n_alternatives = insn_data[INSN_CODE (insn)].n_alternatives; 2099 for (int i = 0; i < n_alternatives; i++) 2100 { 2101 which_alternative = i; 2102 if (!get_bool_attr (insn, attr)) 2103 mask &= ~ALTERNATIVE_BIT (i); 2104 } 2105 2106 recog_data.insn = old_insn; 2107 which_alternative = old_alternative; 2108 return mask; 2109 } 2110 2111 /* Return the mask of operand alternatives that are allowed for INSN 2112 by boolean attribute ATTR. This mask depends only on INSN and on 2113 the current target; it does not depend on things like the values of 2114 operands. */ 2115 2116 static alternative_mask 2117 get_bool_attr_mask (rtx_insn *insn, bool_attr attr) 2118 { 2119 /* Quick exit for asms and for targets that don't use these attributes. */ 2120 int code = INSN_CODE (insn); 2121 if (code < 0 || !have_bool_attr (attr)) 2122 return ALL_ALTERNATIVES; 2123 2124 /* Calling get_attr_<foo> can be expensive, so cache the mask 2125 for speed. */ 2126 if (!this_target_recog->x_bool_attr_masks[code][attr]) 2127 this_target_recog->x_bool_attr_masks[code][attr] 2128 = get_bool_attr_mask_uncached (insn, attr); 2129 return this_target_recog->x_bool_attr_masks[code][attr]; 2130 } 2131 2132 /* Return the set of alternatives of INSN that are allowed by the current 2133 target. */ 2134 2135 alternative_mask 2136 get_enabled_alternatives (rtx_insn *insn) 2137 { 2138 return get_bool_attr_mask (insn, BA_ENABLED); 2139 } 2140 2141 /* Return the set of alternatives of INSN that are allowed by the current 2142 target and are preferred for the current size/speed optimization 2143 choice. */ 2144 2145 alternative_mask 2146 get_preferred_alternatives (rtx_insn *insn) 2147 { 2148 if (optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn))) 2149 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED); 2150 else 2151 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE); 2152 } 2153 2154 /* Return the set of alternatives of INSN that are allowed by the current 2155 target and are preferred for the size/speed optimization choice 2156 associated with BB. Passing a separate BB is useful if INSN has not 2157 been emitted yet or if we are considering moving it to a different 2158 block. */ 2159 2160 alternative_mask 2161 get_preferred_alternatives (rtx_insn *insn, basic_block bb) 2162 { 2163 if (optimize_bb_for_speed_p (bb)) 2164 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SPEED); 2165 else 2166 return get_bool_attr_mask (insn, BA_PREFERRED_FOR_SIZE); 2167 } 2168 2169 /* Assert that the cached boolean attributes for INSN are still accurate. 2170 The backend is required to define these attributes in a way that only 2171 depends on the current target (rather than operands, compiler phase, 2172 etc.). */ 2173 2174 bool 2175 check_bool_attrs (rtx_insn *insn) 2176 { 2177 int code = INSN_CODE (insn); 2178 if (code >= 0) 2179 for (int i = 0; i <= BA_LAST; ++i) 2180 { 2181 enum bool_attr attr = (enum bool_attr) i; 2182 if (this_target_recog->x_bool_attr_masks[code][attr]) 2183 gcc_assert (this_target_recog->x_bool_attr_masks[code][attr] 2184 == get_bool_attr_mask_uncached (insn, attr)); 2185 } 2186 return true; 2187 } 2188 2189 /* Like extract_insn, but save insn extracted and don't extract again, when 2190 called again for the same insn expecting that recog_data still contain the 2191 valid information. This is used primary by gen_attr infrastructure that 2192 often does extract insn again and again. */ 2193 void 2194 extract_insn_cached (rtx_insn *insn) 2195 { 2196 if (recog_data.insn == insn && INSN_CODE (insn) >= 0) 2197 return; 2198 extract_insn (insn); 2199 recog_data.insn = insn; 2200 } 2201 2202 /* Do uncached extract_insn, constrain_operands and complain about failures. 2203 This should be used when extracting a pre-existing constrained instruction 2204 if the caller wants to know which alternative was chosen. */ 2205 void 2206 extract_constrain_insn (rtx_insn *insn) 2207 { 2208 extract_insn (insn); 2209 if (!constrain_operands (reload_completed, get_enabled_alternatives (insn))) 2210 fatal_insn_not_found (insn); 2211 } 2212 2213 /* Do cached extract_insn, constrain_operands and complain about failures. 2214 Used by insn_attrtab. */ 2215 void 2216 extract_constrain_insn_cached (rtx_insn *insn) 2217 { 2218 extract_insn_cached (insn); 2219 if (which_alternative == -1 2220 && !constrain_operands (reload_completed, 2221 get_enabled_alternatives (insn))) 2222 fatal_insn_not_found (insn); 2223 } 2224 2225 /* Do cached constrain_operands on INSN and complain about failures. */ 2226 int 2227 constrain_operands_cached (rtx_insn *insn, int strict) 2228 { 2229 if (which_alternative == -1) 2230 return constrain_operands (strict, get_enabled_alternatives (insn)); 2231 else 2232 return 1; 2233 } 2234 2235 /* Analyze INSN and fill in recog_data. */ 2236 2237 void 2238 extract_insn (rtx_insn *insn) 2239 { 2240 int i; 2241 int icode; 2242 int noperands; 2243 rtx body = PATTERN (insn); 2244 2245 recog_data.n_operands = 0; 2246 recog_data.n_alternatives = 0; 2247 recog_data.n_dups = 0; 2248 recog_data.is_asm = false; 2249 2250 switch (GET_CODE (body)) 2251 { 2252 case USE: 2253 case CLOBBER: 2254 case ASM_INPUT: 2255 case ADDR_VEC: 2256 case ADDR_DIFF_VEC: 2257 case VAR_LOCATION: 2258 case DEBUG_MARKER: 2259 return; 2260 2261 case SET: 2262 if (GET_CODE (SET_SRC (body)) == ASM_OPERANDS) 2263 goto asm_insn; 2264 else 2265 goto normal_insn; 2266 case PARALLEL: 2267 if ((GET_CODE (XVECEXP (body, 0, 0)) == SET 2268 && GET_CODE (SET_SRC (XVECEXP (body, 0, 0))) == ASM_OPERANDS) 2269 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_OPERANDS 2270 || GET_CODE (XVECEXP (body, 0, 0)) == ASM_INPUT) 2271 goto asm_insn; 2272 else 2273 goto normal_insn; 2274 case ASM_OPERANDS: 2275 asm_insn: 2276 recog_data.n_operands = noperands = asm_noperands (body); 2277 if (noperands >= 0) 2278 { 2279 /* This insn is an `asm' with operands. */ 2280 2281 /* expand_asm_operands makes sure there aren't too many operands. */ 2282 gcc_assert (noperands <= MAX_RECOG_OPERANDS); 2283 2284 /* Now get the operand values and constraints out of the insn. */ 2285 decode_asm_operands (body, recog_data.operand, 2286 recog_data.operand_loc, 2287 recog_data.constraints, 2288 recog_data.operand_mode, NULL); 2289 memset (recog_data.is_operator, 0, sizeof recog_data.is_operator); 2290 if (noperands > 0) 2291 { 2292 const char *p = recog_data.constraints[0]; 2293 recog_data.n_alternatives = 1; 2294 while (*p) 2295 recog_data.n_alternatives += (*p++ == ','); 2296 } 2297 recog_data.is_asm = true; 2298 break; 2299 } 2300 fatal_insn_not_found (insn); 2301 2302 default: 2303 normal_insn: 2304 /* Ordinary insn: recognize it, get the operands via insn_extract 2305 and get the constraints. */ 2306 2307 icode = recog_memoized (insn); 2308 if (icode < 0) 2309 fatal_insn_not_found (insn); 2310 2311 recog_data.n_operands = noperands = insn_data[icode].n_operands; 2312 recog_data.n_alternatives = insn_data[icode].n_alternatives; 2313 recog_data.n_dups = insn_data[icode].n_dups; 2314 2315 insn_extract (insn); 2316 2317 for (i = 0; i < noperands; i++) 2318 { 2319 recog_data.constraints[i] = insn_data[icode].operand[i].constraint; 2320 recog_data.is_operator[i] = insn_data[icode].operand[i].is_operator; 2321 recog_data.operand_mode[i] = insn_data[icode].operand[i].mode; 2322 /* VOIDmode match_operands gets mode from their real operand. */ 2323 if (recog_data.operand_mode[i] == VOIDmode) 2324 recog_data.operand_mode[i] = GET_MODE (recog_data.operand[i]); 2325 } 2326 } 2327 for (i = 0; i < noperands; i++) 2328 recog_data.operand_type[i] 2329 = (recog_data.constraints[i][0] == '=' ? OP_OUT 2330 : recog_data.constraints[i][0] == '+' ? OP_INOUT 2331 : OP_IN); 2332 2333 gcc_assert (recog_data.n_alternatives <= MAX_RECOG_ALTERNATIVES); 2334 2335 recog_data.insn = NULL; 2336 which_alternative = -1; 2337 } 2338 2339 /* Fill in OP_ALT_BASE for an instruction that has N_OPERANDS 2340 operands, N_ALTERNATIVES alternatives and constraint strings 2341 CONSTRAINTS. OP_ALT_BASE has N_ALTERNATIVES * N_OPERANDS entries 2342 and CONSTRAINTS has N_OPERANDS entries. OPLOC should be passed in 2343 if the insn is an asm statement and preprocessing should take the 2344 asm operands into account, e.g. to determine whether they could be 2345 addresses in constraints that require addresses; it should then 2346 point to an array of pointers to each operand. */ 2347 2348 void 2349 preprocess_constraints (int n_operands, int n_alternatives, 2350 const char **constraints, 2351 operand_alternative *op_alt_base, 2352 rtx **oploc) 2353 { 2354 for (int i = 0; i < n_operands; i++) 2355 { 2356 int j; 2357 struct operand_alternative *op_alt; 2358 const char *p = constraints[i]; 2359 2360 op_alt = op_alt_base; 2361 2362 for (j = 0; j < n_alternatives; j++, op_alt += n_operands) 2363 { 2364 op_alt[i].cl = NO_REGS; 2365 op_alt[i].constraint = p; 2366 op_alt[i].matches = -1; 2367 op_alt[i].matched = -1; 2368 2369 if (*p == '\0' || *p == ',') 2370 { 2371 op_alt[i].anything_ok = 1; 2372 continue; 2373 } 2374 2375 for (;;) 2376 { 2377 char c = *p; 2378 if (c == '#') 2379 do 2380 c = *++p; 2381 while (c != ',' && c != '\0'); 2382 if (c == ',' || c == '\0') 2383 { 2384 p++; 2385 break; 2386 } 2387 2388 switch (c) 2389 { 2390 case '?': 2391 op_alt[i].reject += 6; 2392 break; 2393 case '!': 2394 op_alt[i].reject += 600; 2395 break; 2396 case '&': 2397 op_alt[i].earlyclobber = 1; 2398 break; 2399 2400 case '0': case '1': case '2': case '3': case '4': 2401 case '5': case '6': case '7': case '8': case '9': 2402 { 2403 char *end; 2404 op_alt[i].matches = strtoul (p, &end, 10); 2405 op_alt[op_alt[i].matches].matched = i; 2406 p = end; 2407 } 2408 continue; 2409 2410 case 'X': 2411 op_alt[i].anything_ok = 1; 2412 break; 2413 2414 case 'g': 2415 op_alt[i].cl = 2416 reg_class_subunion[(int) op_alt[i].cl][(int) GENERAL_REGS]; 2417 break; 2418 2419 default: 2420 enum constraint_num cn = lookup_constraint (p); 2421 enum reg_class cl; 2422 switch (get_constraint_type (cn)) 2423 { 2424 case CT_REGISTER: 2425 cl = reg_class_for_constraint (cn); 2426 if (cl != NO_REGS) 2427 op_alt[i].cl = reg_class_subunion[op_alt[i].cl][cl]; 2428 break; 2429 2430 case CT_CONST_INT: 2431 break; 2432 2433 case CT_MEMORY: 2434 case CT_SPECIAL_MEMORY: 2435 op_alt[i].memory_ok = 1; 2436 break; 2437 2438 case CT_ADDRESS: 2439 if (oploc && !address_operand (*oploc[i], VOIDmode)) 2440 break; 2441 2442 op_alt[i].is_address = 1; 2443 op_alt[i].cl 2444 = (reg_class_subunion 2445 [(int) op_alt[i].cl] 2446 [(int) base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 2447 ADDRESS, SCRATCH)]); 2448 break; 2449 2450 case CT_FIXED_FORM: 2451 break; 2452 } 2453 break; 2454 } 2455 p += CONSTRAINT_LEN (c, p); 2456 } 2457 } 2458 } 2459 } 2460 2461 /* Return an array of operand_alternative instructions for 2462 instruction ICODE. */ 2463 2464 const operand_alternative * 2465 preprocess_insn_constraints (unsigned int icode) 2466 { 2467 gcc_checking_assert (IN_RANGE (icode, 0, NUM_INSN_CODES - 1)); 2468 if (this_target_recog->x_op_alt[icode]) 2469 return this_target_recog->x_op_alt[icode]; 2470 2471 int n_operands = insn_data[icode].n_operands; 2472 if (n_operands == 0) 2473 return 0; 2474 /* Always provide at least one alternative so that which_op_alt () 2475 works correctly. If the instruction has 0 alternatives (i.e. all 2476 constraint strings are empty) then each operand in this alternative 2477 will have anything_ok set. */ 2478 int n_alternatives = MAX (insn_data[icode].n_alternatives, 1); 2479 int n_entries = n_operands * n_alternatives; 2480 2481 operand_alternative *op_alt = XCNEWVEC (operand_alternative, n_entries); 2482 const char **constraints = XALLOCAVEC (const char *, n_operands); 2483 2484 for (int i = 0; i < n_operands; ++i) 2485 constraints[i] = insn_data[icode].operand[i].constraint; 2486 preprocess_constraints (n_operands, n_alternatives, constraints, op_alt, 2487 NULL); 2488 2489 this_target_recog->x_op_alt[icode] = op_alt; 2490 return op_alt; 2491 } 2492 2493 /* After calling extract_insn, you can use this function to extract some 2494 information from the constraint strings into a more usable form. 2495 The collected data is stored in recog_op_alt. */ 2496 2497 void 2498 preprocess_constraints (rtx_insn *insn) 2499 { 2500 int icode = INSN_CODE (insn); 2501 if (icode >= 0) 2502 recog_op_alt = preprocess_insn_constraints (icode); 2503 else 2504 { 2505 int n_operands = recog_data.n_operands; 2506 int n_alternatives = recog_data.n_alternatives; 2507 int n_entries = n_operands * n_alternatives; 2508 memset (asm_op_alt, 0, n_entries * sizeof (operand_alternative)); 2509 preprocess_constraints (n_operands, n_alternatives, 2510 recog_data.constraints, asm_op_alt, 2511 NULL); 2512 recog_op_alt = asm_op_alt; 2513 } 2514 } 2515 2516 /* Check the operands of an insn against the insn's operand constraints 2517 and return 1 if they match any of the alternatives in ALTERNATIVES. 2518 2519 The information about the insn's operands, constraints, operand modes 2520 etc. is obtained from the global variables set up by extract_insn. 2521 2522 WHICH_ALTERNATIVE is set to a number which indicates which 2523 alternative of constraints was matched: 0 for the first alternative, 2524 1 for the next, etc. 2525 2526 In addition, when two operands are required to match 2527 and it happens that the output operand is (reg) while the 2528 input operand is --(reg) or ++(reg) (a pre-inc or pre-dec), 2529 make the output operand look like the input. 2530 This is because the output operand is the one the template will print. 2531 2532 This is used in final, just before printing the assembler code and by 2533 the routines that determine an insn's attribute. 2534 2535 If STRICT is a positive nonzero value, it means that we have been 2536 called after reload has been completed. In that case, we must 2537 do all checks strictly. If it is zero, it means that we have been called 2538 before reload has completed. In that case, we first try to see if we can 2539 find an alternative that matches strictly. If not, we try again, this 2540 time assuming that reload will fix up the insn. This provides a "best 2541 guess" for the alternative and is used to compute attributes of insns prior 2542 to reload. A negative value of STRICT is used for this internal call. */ 2543 2544 struct funny_match 2545 { 2546 int this_op, other; 2547 }; 2548 2549 int 2550 constrain_operands (int strict, alternative_mask alternatives) 2551 { 2552 const char *constraints[MAX_RECOG_OPERANDS]; 2553 int matching_operands[MAX_RECOG_OPERANDS]; 2554 int earlyclobber[MAX_RECOG_OPERANDS]; 2555 int c; 2556 2557 struct funny_match funny_match[MAX_RECOG_OPERANDS]; 2558 int funny_match_index; 2559 2560 which_alternative = 0; 2561 if (recog_data.n_operands == 0 || recog_data.n_alternatives == 0) 2562 return 1; 2563 2564 for (c = 0; c < recog_data.n_operands; c++) 2565 { 2566 constraints[c] = recog_data.constraints[c]; 2567 matching_operands[c] = -1; 2568 } 2569 2570 do 2571 { 2572 int seen_earlyclobber_at = -1; 2573 int opno; 2574 int lose = 0; 2575 funny_match_index = 0; 2576 2577 if (!TEST_BIT (alternatives, which_alternative)) 2578 { 2579 int i; 2580 2581 for (i = 0; i < recog_data.n_operands; i++) 2582 constraints[i] = skip_alternative (constraints[i]); 2583 2584 which_alternative++; 2585 continue; 2586 } 2587 2588 for (opno = 0; opno < recog_data.n_operands; opno++) 2589 { 2590 rtx op = recog_data.operand[opno]; 2591 machine_mode mode = GET_MODE (op); 2592 const char *p = constraints[opno]; 2593 int offset = 0; 2594 int win = 0; 2595 int val; 2596 int len; 2597 2598 earlyclobber[opno] = 0; 2599 2600 /* A unary operator may be accepted by the predicate, but it 2601 is irrelevant for matching constraints. */ 2602 if (UNARY_P (op)) 2603 op = XEXP (op, 0); 2604 2605 if (GET_CODE (op) == SUBREG) 2606 { 2607 if (REG_P (SUBREG_REG (op)) 2608 && REGNO (SUBREG_REG (op)) < FIRST_PSEUDO_REGISTER) 2609 offset = subreg_regno_offset (REGNO (SUBREG_REG (op)), 2610 GET_MODE (SUBREG_REG (op)), 2611 SUBREG_BYTE (op), 2612 GET_MODE (op)); 2613 op = SUBREG_REG (op); 2614 } 2615 2616 /* An empty constraint or empty alternative 2617 allows anything which matched the pattern. */ 2618 if (*p == 0 || *p == ',') 2619 win = 1; 2620 2621 do 2622 switch (c = *p, len = CONSTRAINT_LEN (c, p), c) 2623 { 2624 case '\0': 2625 len = 0; 2626 break; 2627 case ',': 2628 c = '\0'; 2629 break; 2630 2631 case '#': 2632 /* Ignore rest of this alternative as far as 2633 constraint checking is concerned. */ 2634 do 2635 p++; 2636 while (*p && *p != ','); 2637 len = 0; 2638 break; 2639 2640 case '&': 2641 earlyclobber[opno] = 1; 2642 if (seen_earlyclobber_at < 0) 2643 seen_earlyclobber_at = opno; 2644 break; 2645 2646 case '0': case '1': case '2': case '3': case '4': 2647 case '5': case '6': case '7': case '8': case '9': 2648 { 2649 /* This operand must be the same as a previous one. 2650 This kind of constraint is used for instructions such 2651 as add when they take only two operands. 2652 2653 Note that the lower-numbered operand is passed first. 2654 2655 If we are not testing strictly, assume that this 2656 constraint will be satisfied. */ 2657 2658 char *end; 2659 int match; 2660 2661 match = strtoul (p, &end, 10); 2662 p = end; 2663 2664 if (strict < 0) 2665 val = 1; 2666 else 2667 { 2668 rtx op1 = recog_data.operand[match]; 2669 rtx op2 = recog_data.operand[opno]; 2670 2671 /* A unary operator may be accepted by the predicate, 2672 but it is irrelevant for matching constraints. */ 2673 if (UNARY_P (op1)) 2674 op1 = XEXP (op1, 0); 2675 if (UNARY_P (op2)) 2676 op2 = XEXP (op2, 0); 2677 2678 val = operands_match_p (op1, op2); 2679 } 2680 2681 matching_operands[opno] = match; 2682 matching_operands[match] = opno; 2683 2684 if (val != 0) 2685 win = 1; 2686 2687 /* If output is *x and input is *--x, arrange later 2688 to change the output to *--x as well, since the 2689 output op is the one that will be printed. */ 2690 if (val == 2 && strict > 0) 2691 { 2692 funny_match[funny_match_index].this_op = opno; 2693 funny_match[funny_match_index++].other = match; 2694 } 2695 } 2696 len = 0; 2697 break; 2698 2699 case 'p': 2700 /* p is used for address_operands. When we are called by 2701 gen_reload, no one will have checked that the address is 2702 strictly valid, i.e., that all pseudos requiring hard regs 2703 have gotten them. We also want to make sure we have a 2704 valid mode. */ 2705 if ((GET_MODE (op) == VOIDmode 2706 || SCALAR_INT_MODE_P (GET_MODE (op))) 2707 && (strict <= 0 2708 || (strict_memory_address_p 2709 (recog_data.operand_mode[opno], op)))) 2710 win = 1; 2711 break; 2712 2713 /* No need to check general_operand again; 2714 it was done in insn-recog.c. Well, except that reload 2715 doesn't check the validity of its replacements, but 2716 that should only matter when there's a bug. */ 2717 case 'g': 2718 /* Anything goes unless it is a REG and really has a hard reg 2719 but the hard reg is not in the class GENERAL_REGS. */ 2720 if (REG_P (op)) 2721 { 2722 if (strict < 0 2723 || GENERAL_REGS == ALL_REGS 2724 || (reload_in_progress 2725 && REGNO (op) >= FIRST_PSEUDO_REGISTER) 2726 || reg_fits_class_p (op, GENERAL_REGS, offset, mode)) 2727 win = 1; 2728 } 2729 else if (strict < 0 || general_operand (op, mode)) 2730 win = 1; 2731 break; 2732 2733 default: 2734 { 2735 enum constraint_num cn = lookup_constraint (p); 2736 enum reg_class cl = reg_class_for_constraint (cn); 2737 if (cl != NO_REGS) 2738 { 2739 if (strict < 0 2740 || (strict == 0 2741 && REG_P (op) 2742 && REGNO (op) >= FIRST_PSEUDO_REGISTER) 2743 || (strict == 0 && GET_CODE (op) == SCRATCH) 2744 || (REG_P (op) 2745 && reg_fits_class_p (op, cl, offset, mode))) 2746 win = 1; 2747 } 2748 2749 else if (constraint_satisfied_p (op, cn)) 2750 win = 1; 2751 2752 else if (insn_extra_memory_constraint (cn) 2753 /* Every memory operand can be reloaded to fit. */ 2754 && ((strict < 0 && MEM_P (op)) 2755 /* Before reload, accept what reload can turn 2756 into a mem. */ 2757 || (strict < 0 && CONSTANT_P (op)) 2758 /* Before reload, accept a pseudo, 2759 since LRA can turn it into a mem. */ 2760 || (strict < 0 && targetm.lra_p () && REG_P (op) 2761 && REGNO (op) >= FIRST_PSEUDO_REGISTER) 2762 /* During reload, accept a pseudo */ 2763 || (reload_in_progress && REG_P (op) 2764 && REGNO (op) >= FIRST_PSEUDO_REGISTER))) 2765 win = 1; 2766 else if (insn_extra_address_constraint (cn) 2767 /* Every address operand can be reloaded to fit. */ 2768 && strict < 0) 2769 win = 1; 2770 /* Cater to architectures like IA-64 that define extra memory 2771 constraints without using define_memory_constraint. */ 2772 else if (reload_in_progress 2773 && REG_P (op) 2774 && REGNO (op) >= FIRST_PSEUDO_REGISTER 2775 && reg_renumber[REGNO (op)] < 0 2776 && reg_equiv_mem (REGNO (op)) != 0 2777 && constraint_satisfied_p 2778 (reg_equiv_mem (REGNO (op)), cn)) 2779 win = 1; 2780 break; 2781 } 2782 } 2783 while (p += len, c); 2784 2785 constraints[opno] = p; 2786 /* If this operand did not win somehow, 2787 this alternative loses. */ 2788 if (! win) 2789 lose = 1; 2790 } 2791 /* This alternative won; the operands are ok. 2792 Change whichever operands this alternative says to change. */ 2793 if (! lose) 2794 { 2795 int opno, eopno; 2796 2797 /* See if any earlyclobber operand conflicts with some other 2798 operand. */ 2799 2800 if (strict > 0 && seen_earlyclobber_at >= 0) 2801 for (eopno = seen_earlyclobber_at; 2802 eopno < recog_data.n_operands; 2803 eopno++) 2804 /* Ignore earlyclobber operands now in memory, 2805 because we would often report failure when we have 2806 two memory operands, one of which was formerly a REG. */ 2807 if (earlyclobber[eopno] 2808 && REG_P (recog_data.operand[eopno])) 2809 for (opno = 0; opno < recog_data.n_operands; opno++) 2810 if ((MEM_P (recog_data.operand[opno]) 2811 || recog_data.operand_type[opno] != OP_OUT) 2812 && opno != eopno 2813 /* Ignore things like match_operator operands. */ 2814 && *recog_data.constraints[opno] != 0 2815 && ! (matching_operands[opno] == eopno 2816 && operands_match_p (recog_data.operand[opno], 2817 recog_data.operand[eopno])) 2818 && ! safe_from_earlyclobber (recog_data.operand[opno], 2819 recog_data.operand[eopno])) 2820 lose = 1; 2821 2822 if (! lose) 2823 { 2824 while (--funny_match_index >= 0) 2825 { 2826 recog_data.operand[funny_match[funny_match_index].other] 2827 = recog_data.operand[funny_match[funny_match_index].this_op]; 2828 } 2829 2830 /* For operands without < or > constraints reject side-effects. */ 2831 if (AUTO_INC_DEC && recog_data.is_asm) 2832 { 2833 for (opno = 0; opno < recog_data.n_operands; opno++) 2834 if (MEM_P (recog_data.operand[opno])) 2835 switch (GET_CODE (XEXP (recog_data.operand[opno], 0))) 2836 { 2837 case PRE_INC: 2838 case POST_INC: 2839 case PRE_DEC: 2840 case POST_DEC: 2841 case PRE_MODIFY: 2842 case POST_MODIFY: 2843 if (strchr (recog_data.constraints[opno], '<') == NULL 2844 && strchr (recog_data.constraints[opno], '>') 2845 == NULL) 2846 return 0; 2847 break; 2848 default: 2849 break; 2850 } 2851 } 2852 2853 return 1; 2854 } 2855 } 2856 2857 which_alternative++; 2858 } 2859 while (which_alternative < recog_data.n_alternatives); 2860 2861 which_alternative = -1; 2862 /* If we are about to reject this, but we are not to test strictly, 2863 try a very loose test. Only return failure if it fails also. */ 2864 if (strict == 0) 2865 return constrain_operands (-1, alternatives); 2866 else 2867 return 0; 2868 } 2869 2870 /* Return true iff OPERAND (assumed to be a REG rtx) 2871 is a hard reg in class CLASS when its regno is offset by OFFSET 2872 and changed to mode MODE. 2873 If REG occupies multiple hard regs, all of them must be in CLASS. */ 2874 2875 bool 2876 reg_fits_class_p (const_rtx operand, reg_class_t cl, int offset, 2877 machine_mode mode) 2878 { 2879 unsigned int regno = REGNO (operand); 2880 2881 if (cl == NO_REGS) 2882 return false; 2883 2884 /* Regno must not be a pseudo register. Offset may be negative. */ 2885 return (HARD_REGISTER_NUM_P (regno) 2886 && HARD_REGISTER_NUM_P (regno + offset) 2887 && in_hard_reg_set_p (reg_class_contents[(int) cl], mode, 2888 regno + offset)); 2889 } 2890 2891 /* Split single instruction. Helper function for split_all_insns and 2892 split_all_insns_noflow. Return last insn in the sequence if successful, 2893 or NULL if unsuccessful. */ 2894 2895 static rtx_insn * 2896 split_insn (rtx_insn *insn) 2897 { 2898 /* Split insns here to get max fine-grain parallelism. */ 2899 rtx_insn *first = PREV_INSN (insn); 2900 rtx_insn *last = try_split (PATTERN (insn), insn, 1); 2901 rtx insn_set, last_set, note; 2902 2903 if (last == insn) 2904 return NULL; 2905 2906 /* If the original instruction was a single set that was known to be 2907 equivalent to a constant, see if we can say the same about the last 2908 instruction in the split sequence. The two instructions must set 2909 the same destination. */ 2910 insn_set = single_set (insn); 2911 if (insn_set) 2912 { 2913 last_set = single_set (last); 2914 if (last_set && rtx_equal_p (SET_DEST (last_set), SET_DEST (insn_set))) 2915 { 2916 note = find_reg_equal_equiv_note (insn); 2917 if (note && CONSTANT_P (XEXP (note, 0))) 2918 set_unique_reg_note (last, REG_EQUAL, XEXP (note, 0)); 2919 else if (CONSTANT_P (SET_SRC (insn_set))) 2920 set_unique_reg_note (last, REG_EQUAL, 2921 copy_rtx (SET_SRC (insn_set))); 2922 } 2923 } 2924 2925 /* try_split returns the NOTE that INSN became. */ 2926 SET_INSN_DELETED (insn); 2927 2928 /* ??? Coddle to md files that generate subregs in post-reload 2929 splitters instead of computing the proper hard register. */ 2930 if (reload_completed && first != last) 2931 { 2932 first = NEXT_INSN (first); 2933 for (;;) 2934 { 2935 if (INSN_P (first)) 2936 cleanup_subreg_operands (first); 2937 if (first == last) 2938 break; 2939 first = NEXT_INSN (first); 2940 } 2941 } 2942 2943 return last; 2944 } 2945 2946 /* Split all insns in the function. If UPD_LIFE, update life info after. */ 2947 2948 void 2949 split_all_insns (void) 2950 { 2951 bool changed; 2952 bool need_cfg_cleanup = false; 2953 basic_block bb; 2954 2955 auto_sbitmap blocks (last_basic_block_for_fn (cfun)); 2956 bitmap_clear (blocks); 2957 changed = false; 2958 2959 FOR_EACH_BB_REVERSE_FN (bb, cfun) 2960 { 2961 rtx_insn *insn, *next; 2962 bool finish = false; 2963 2964 rtl_profile_for_bb (bb); 2965 for (insn = BB_HEAD (bb); !finish ; insn = next) 2966 { 2967 /* Can't use `next_real_insn' because that might go across 2968 CODE_LABELS and short-out basic blocks. */ 2969 next = NEXT_INSN (insn); 2970 finish = (insn == BB_END (bb)); 2971 2972 /* If INSN has a REG_EH_REGION note and we split INSN, the 2973 resulting split may not have/need REG_EH_REGION notes. 2974 2975 If that happens and INSN was the last reference to the 2976 given EH region, then the EH region will become unreachable. 2977 We can not leave the unreachable blocks in the CFG as that 2978 will trigger a checking failure. 2979 2980 So track if INSN has a REG_EH_REGION note. If so and we 2981 split INSN, then trigger a CFG cleanup. */ 2982 rtx note = find_reg_note (insn, REG_EH_REGION, NULL_RTX); 2983 if (INSN_P (insn)) 2984 { 2985 rtx set = single_set (insn); 2986 2987 /* Don't split no-op move insns. These should silently 2988 disappear later in final. Splitting such insns would 2989 break the code that handles LIBCALL blocks. */ 2990 if (set && set_noop_p (set)) 2991 { 2992 /* Nops get in the way while scheduling, so delete them 2993 now if register allocation has already been done. It 2994 is too risky to try to do this before register 2995 allocation, and there are unlikely to be very many 2996 nops then anyways. */ 2997 if (reload_completed) 2998 delete_insn_and_edges (insn); 2999 if (note) 3000 need_cfg_cleanup = true; 3001 } 3002 else 3003 { 3004 if (split_insn (insn)) 3005 { 3006 bitmap_set_bit (blocks, bb->index); 3007 changed = true; 3008 if (note) 3009 need_cfg_cleanup = true; 3010 } 3011 } 3012 } 3013 } 3014 } 3015 3016 default_rtl_profile (); 3017 if (changed) 3018 { 3019 find_many_sub_basic_blocks (blocks); 3020 3021 /* Splitting could drop an REG_EH_REGION if it potentially 3022 trapped in its original form, but does not in its split 3023 form. Consider a FLOAT_TRUNCATE which splits into a memory 3024 store/load pair and -fnon-call-exceptions. */ 3025 if (need_cfg_cleanup) 3026 cleanup_cfg (0); 3027 } 3028 3029 checking_verify_flow_info (); 3030 } 3031 3032 /* Same as split_all_insns, but do not expect CFG to be available. 3033 Used by machine dependent reorg passes. */ 3034 3035 unsigned int 3036 split_all_insns_noflow (void) 3037 { 3038 rtx_insn *next, *insn; 3039 3040 for (insn = get_insns (); insn; insn = next) 3041 { 3042 next = NEXT_INSN (insn); 3043 if (INSN_P (insn)) 3044 { 3045 /* Don't split no-op move insns. These should silently 3046 disappear later in final. Splitting such insns would 3047 break the code that handles LIBCALL blocks. */ 3048 rtx set = single_set (insn); 3049 if (set && set_noop_p (set)) 3050 { 3051 /* Nops get in the way while scheduling, so delete them 3052 now if register allocation has already been done. It 3053 is too risky to try to do this before register 3054 allocation, and there are unlikely to be very many 3055 nops then anyways. 3056 3057 ??? Should we use delete_insn when the CFG isn't valid? */ 3058 if (reload_completed) 3059 delete_insn_and_edges (insn); 3060 } 3061 else 3062 split_insn (insn); 3063 } 3064 } 3065 return 0; 3066 } 3067 3068 struct peep2_insn_data 3069 { 3070 rtx_insn *insn; 3071 regset live_before; 3072 }; 3073 3074 static struct peep2_insn_data peep2_insn_data[MAX_INSNS_PER_PEEP2 + 1]; 3075 static int peep2_current; 3076 3077 static bool peep2_do_rebuild_jump_labels; 3078 static bool peep2_do_cleanup_cfg; 3079 3080 /* The number of instructions available to match a peep2. */ 3081 int peep2_current_count; 3082 3083 /* A marker indicating the last insn of the block. The live_before regset 3084 for this element is correct, indicating DF_LIVE_OUT for the block. */ 3085 #define PEEP2_EOB invalid_insn_rtx 3086 3087 /* Wrap N to fit into the peep2_insn_data buffer. */ 3088 3089 static int 3090 peep2_buf_position (int n) 3091 { 3092 if (n >= MAX_INSNS_PER_PEEP2 + 1) 3093 n -= MAX_INSNS_PER_PEEP2 + 1; 3094 return n; 3095 } 3096 3097 /* Return the Nth non-note insn after `current', or return NULL_RTX if it 3098 does not exist. Used by the recognizer to find the next insn to match 3099 in a multi-insn pattern. */ 3100 3101 rtx_insn * 3102 peep2_next_insn (int n) 3103 { 3104 gcc_assert (n <= peep2_current_count); 3105 3106 n = peep2_buf_position (peep2_current + n); 3107 3108 return peep2_insn_data[n].insn; 3109 } 3110 3111 /* Return true if REGNO is dead before the Nth non-note insn 3112 after `current'. */ 3113 3114 int 3115 peep2_regno_dead_p (int ofs, int regno) 3116 { 3117 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); 3118 3119 ofs = peep2_buf_position (peep2_current + ofs); 3120 3121 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); 3122 3123 return ! REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno); 3124 } 3125 3126 /* Similarly for a REG. */ 3127 3128 int 3129 peep2_reg_dead_p (int ofs, rtx reg) 3130 { 3131 gcc_assert (ofs < MAX_INSNS_PER_PEEP2 + 1); 3132 3133 ofs = peep2_buf_position (peep2_current + ofs); 3134 3135 gcc_assert (peep2_insn_data[ofs].insn != NULL_RTX); 3136 3137 unsigned int end_regno = END_REGNO (reg); 3138 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno) 3139 if (REGNO_REG_SET_P (peep2_insn_data[ofs].live_before, regno)) 3140 return 0; 3141 return 1; 3142 } 3143 3144 /* Regno offset to be used in the register search. */ 3145 static int search_ofs; 3146 3147 /* Try to find a hard register of mode MODE, matching the register class in 3148 CLASS_STR, which is available at the beginning of insn CURRENT_INSN and 3149 remains available until the end of LAST_INSN. LAST_INSN may be NULL_RTX, 3150 in which case the only condition is that the register must be available 3151 before CURRENT_INSN. 3152 Registers that already have bits set in REG_SET will not be considered. 3153 3154 If an appropriate register is available, it will be returned and the 3155 corresponding bit(s) in REG_SET will be set; otherwise, NULL_RTX is 3156 returned. */ 3157 3158 rtx 3159 peep2_find_free_register (int from, int to, const char *class_str, 3160 machine_mode mode, HARD_REG_SET *reg_set) 3161 { 3162 enum reg_class cl; 3163 HARD_REG_SET live; 3164 df_ref def; 3165 int i; 3166 3167 gcc_assert (from < MAX_INSNS_PER_PEEP2 + 1); 3168 gcc_assert (to < MAX_INSNS_PER_PEEP2 + 1); 3169 3170 from = peep2_buf_position (peep2_current + from); 3171 to = peep2_buf_position (peep2_current + to); 3172 3173 gcc_assert (peep2_insn_data[from].insn != NULL_RTX); 3174 REG_SET_TO_HARD_REG_SET (live, peep2_insn_data[from].live_before); 3175 3176 while (from != to) 3177 { 3178 gcc_assert (peep2_insn_data[from].insn != NULL_RTX); 3179 3180 /* Don't use registers set or clobbered by the insn. */ 3181 FOR_EACH_INSN_DEF (def, peep2_insn_data[from].insn) 3182 SET_HARD_REG_BIT (live, DF_REF_REGNO (def)); 3183 3184 from = peep2_buf_position (from + 1); 3185 } 3186 3187 cl = reg_class_for_constraint (lookup_constraint (class_str)); 3188 3189 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 3190 { 3191 int raw_regno, regno, success, j; 3192 3193 /* Distribute the free registers as much as possible. */ 3194 raw_regno = search_ofs + i; 3195 if (raw_regno >= FIRST_PSEUDO_REGISTER) 3196 raw_regno -= FIRST_PSEUDO_REGISTER; 3197 #ifdef REG_ALLOC_ORDER 3198 regno = reg_alloc_order[raw_regno]; 3199 #else 3200 regno = raw_regno; 3201 #endif 3202 3203 /* Can it support the mode we need? */ 3204 if (!targetm.hard_regno_mode_ok (regno, mode)) 3205 continue; 3206 3207 success = 1; 3208 for (j = 0; success && j < hard_regno_nregs (regno, mode); j++) 3209 { 3210 /* Don't allocate fixed registers. */ 3211 if (fixed_regs[regno + j]) 3212 { 3213 success = 0; 3214 break; 3215 } 3216 /* Don't allocate global registers. */ 3217 if (global_regs[regno + j]) 3218 { 3219 success = 0; 3220 break; 3221 } 3222 /* Make sure the register is of the right class. */ 3223 if (! TEST_HARD_REG_BIT (reg_class_contents[cl], regno + j)) 3224 { 3225 success = 0; 3226 break; 3227 } 3228 /* And that we don't create an extra save/restore. */ 3229 if (! call_used_regs[regno + j] && ! df_regs_ever_live_p (regno + j)) 3230 { 3231 success = 0; 3232 break; 3233 } 3234 3235 if (! targetm.hard_regno_scratch_ok (regno + j)) 3236 { 3237 success = 0; 3238 break; 3239 } 3240 3241 /* And we don't clobber traceback for noreturn functions. */ 3242 if ((regno + j == FRAME_POINTER_REGNUM 3243 || regno + j == HARD_FRAME_POINTER_REGNUM) 3244 && (! reload_completed || frame_pointer_needed)) 3245 { 3246 success = 0; 3247 break; 3248 } 3249 3250 if (TEST_HARD_REG_BIT (*reg_set, regno + j) 3251 || TEST_HARD_REG_BIT (live, regno + j)) 3252 { 3253 success = 0; 3254 break; 3255 } 3256 } 3257 3258 if (success) 3259 { 3260 add_to_hard_reg_set (reg_set, mode, regno); 3261 3262 /* Start the next search with the next register. */ 3263 if (++raw_regno >= FIRST_PSEUDO_REGISTER) 3264 raw_regno = 0; 3265 search_ofs = raw_regno; 3266 3267 return gen_rtx_REG (mode, regno); 3268 } 3269 } 3270 3271 search_ofs = 0; 3272 return NULL_RTX; 3273 } 3274 3275 /* Forget all currently tracked instructions, only remember current 3276 LIVE regset. */ 3277 3278 static void 3279 peep2_reinit_state (regset live) 3280 { 3281 int i; 3282 3283 /* Indicate that all slots except the last holds invalid data. */ 3284 for (i = 0; i < MAX_INSNS_PER_PEEP2; ++i) 3285 peep2_insn_data[i].insn = NULL; 3286 peep2_current_count = 0; 3287 3288 /* Indicate that the last slot contains live_after data. */ 3289 peep2_insn_data[MAX_INSNS_PER_PEEP2].insn = PEEP2_EOB; 3290 peep2_current = MAX_INSNS_PER_PEEP2; 3291 3292 COPY_REG_SET (peep2_insn_data[MAX_INSNS_PER_PEEP2].live_before, live); 3293 } 3294 3295 /* While scanning basic block BB, we found a match of length MATCH_LEN, 3296 starting at INSN. Perform the replacement, removing the old insns and 3297 replacing them with ATTEMPT. Returns the last insn emitted, or NULL 3298 if the replacement is rejected. */ 3299 3300 static rtx_insn * 3301 peep2_attempt (basic_block bb, rtx_insn *insn, int match_len, rtx_insn *attempt) 3302 { 3303 int i; 3304 rtx_insn *last, *before_try, *x; 3305 rtx eh_note, as_note; 3306 rtx_insn *old_insn; 3307 rtx_insn *new_insn; 3308 bool was_call = false; 3309 3310 /* If we are splitting an RTX_FRAME_RELATED_P insn, do not allow it to 3311 match more than one insn, or to be split into more than one insn. */ 3312 old_insn = peep2_insn_data[peep2_current].insn; 3313 if (RTX_FRAME_RELATED_P (old_insn)) 3314 { 3315 bool any_note = false; 3316 rtx note; 3317 3318 if (match_len != 0) 3319 return NULL; 3320 3321 /* Look for one "active" insn. I.e. ignore any "clobber" insns that 3322 may be in the stream for the purpose of register allocation. */ 3323 if (active_insn_p (attempt)) 3324 new_insn = attempt; 3325 else 3326 new_insn = next_active_insn (attempt); 3327 if (next_active_insn (new_insn)) 3328 return NULL; 3329 3330 /* We have a 1-1 replacement. Copy over any frame-related info. */ 3331 RTX_FRAME_RELATED_P (new_insn) = 1; 3332 3333 /* Allow the backend to fill in a note during the split. */ 3334 for (note = REG_NOTES (new_insn); note ; note = XEXP (note, 1)) 3335 switch (REG_NOTE_KIND (note)) 3336 { 3337 case REG_FRAME_RELATED_EXPR: 3338 case REG_CFA_DEF_CFA: 3339 case REG_CFA_ADJUST_CFA: 3340 case REG_CFA_OFFSET: 3341 case REG_CFA_REGISTER: 3342 case REG_CFA_EXPRESSION: 3343 case REG_CFA_RESTORE: 3344 case REG_CFA_SET_VDRAP: 3345 any_note = true; 3346 break; 3347 default: 3348 break; 3349 } 3350 3351 /* If the backend didn't supply a note, copy one over. */ 3352 if (!any_note) 3353 for (note = REG_NOTES (old_insn); note ; note = XEXP (note, 1)) 3354 switch (REG_NOTE_KIND (note)) 3355 { 3356 case REG_FRAME_RELATED_EXPR: 3357 case REG_CFA_DEF_CFA: 3358 case REG_CFA_ADJUST_CFA: 3359 case REG_CFA_OFFSET: 3360 case REG_CFA_REGISTER: 3361 case REG_CFA_EXPRESSION: 3362 case REG_CFA_RESTORE: 3363 case REG_CFA_SET_VDRAP: 3364 add_reg_note (new_insn, REG_NOTE_KIND (note), XEXP (note, 0)); 3365 any_note = true; 3366 break; 3367 default: 3368 break; 3369 } 3370 3371 /* If there still isn't a note, make sure the unwind info sees the 3372 same expression as before the split. */ 3373 if (!any_note) 3374 { 3375 rtx old_set, new_set; 3376 3377 /* The old insn had better have been simple, or annotated. */ 3378 old_set = single_set (old_insn); 3379 gcc_assert (old_set != NULL); 3380 3381 new_set = single_set (new_insn); 3382 if (!new_set || !rtx_equal_p (new_set, old_set)) 3383 add_reg_note (new_insn, REG_FRAME_RELATED_EXPR, old_set); 3384 } 3385 3386 /* Copy prologue/epilogue status. This is required in order to keep 3387 proper placement of EPILOGUE_BEG and the DW_CFA_remember_state. */ 3388 maybe_copy_prologue_epilogue_insn (old_insn, new_insn); 3389 } 3390 3391 /* If we are splitting a CALL_INSN, look for the CALL_INSN 3392 in SEQ and copy our CALL_INSN_FUNCTION_USAGE and other 3393 cfg-related call notes. */ 3394 for (i = 0; i <= match_len; ++i) 3395 { 3396 int j; 3397 rtx note; 3398 3399 j = peep2_buf_position (peep2_current + i); 3400 old_insn = peep2_insn_data[j].insn; 3401 if (!CALL_P (old_insn)) 3402 continue; 3403 was_call = true; 3404 3405 new_insn = attempt; 3406 while (new_insn != NULL_RTX) 3407 { 3408 if (CALL_P (new_insn)) 3409 break; 3410 new_insn = NEXT_INSN (new_insn); 3411 } 3412 3413 gcc_assert (new_insn != NULL_RTX); 3414 3415 CALL_INSN_FUNCTION_USAGE (new_insn) 3416 = CALL_INSN_FUNCTION_USAGE (old_insn); 3417 SIBLING_CALL_P (new_insn) = SIBLING_CALL_P (old_insn); 3418 3419 for (note = REG_NOTES (old_insn); 3420 note; 3421 note = XEXP (note, 1)) 3422 switch (REG_NOTE_KIND (note)) 3423 { 3424 case REG_NORETURN: 3425 case REG_SETJMP: 3426 case REG_TM: 3427 case REG_CALL_NOCF_CHECK: 3428 add_reg_note (new_insn, REG_NOTE_KIND (note), 3429 XEXP (note, 0)); 3430 break; 3431 default: 3432 /* Discard all other reg notes. */ 3433 break; 3434 } 3435 3436 /* Croak if there is another call in the sequence. */ 3437 while (++i <= match_len) 3438 { 3439 j = peep2_buf_position (peep2_current + i); 3440 old_insn = peep2_insn_data[j].insn; 3441 gcc_assert (!CALL_P (old_insn)); 3442 } 3443 break; 3444 } 3445 3446 /* If we matched any instruction that had a REG_ARGS_SIZE, then 3447 move those notes over to the new sequence. */ 3448 as_note = NULL; 3449 for (i = match_len; i >= 0; --i) 3450 { 3451 int j = peep2_buf_position (peep2_current + i); 3452 old_insn = peep2_insn_data[j].insn; 3453 3454 as_note = find_reg_note (old_insn, REG_ARGS_SIZE, NULL); 3455 if (as_note) 3456 break; 3457 } 3458 3459 i = peep2_buf_position (peep2_current + match_len); 3460 eh_note = find_reg_note (peep2_insn_data[i].insn, REG_EH_REGION, NULL_RTX); 3461 3462 /* Replace the old sequence with the new. */ 3463 rtx_insn *peepinsn = peep2_insn_data[i].insn; 3464 last = emit_insn_after_setloc (attempt, 3465 peep2_insn_data[i].insn, 3466 INSN_LOCATION (peepinsn)); 3467 if (JUMP_P (peepinsn) && JUMP_P (last)) 3468 CROSSING_JUMP_P (last) = CROSSING_JUMP_P (peepinsn); 3469 before_try = PREV_INSN (insn); 3470 delete_insn_chain (insn, peep2_insn_data[i].insn, false); 3471 3472 /* Re-insert the EH_REGION notes. */ 3473 if (eh_note || (was_call && nonlocal_goto_handler_labels)) 3474 { 3475 edge eh_edge; 3476 edge_iterator ei; 3477 3478 FOR_EACH_EDGE (eh_edge, ei, bb->succs) 3479 if (eh_edge->flags & (EDGE_EH | EDGE_ABNORMAL_CALL)) 3480 break; 3481 3482 if (eh_note) 3483 copy_reg_eh_region_note_backward (eh_note, last, before_try); 3484 3485 if (eh_edge) 3486 for (x = last; x != before_try; x = PREV_INSN (x)) 3487 if (x != BB_END (bb) 3488 && (can_throw_internal (x) 3489 || can_nonlocal_goto (x))) 3490 { 3491 edge nfte, nehe; 3492 int flags; 3493 3494 nfte = split_block (bb, x); 3495 flags = (eh_edge->flags 3496 & (EDGE_EH | EDGE_ABNORMAL)); 3497 if (CALL_P (x)) 3498 flags |= EDGE_ABNORMAL_CALL; 3499 nehe = make_edge (nfte->src, eh_edge->dest, 3500 flags); 3501 3502 nehe->probability = eh_edge->probability; 3503 nfte->probability = nehe->probability.invert (); 3504 3505 peep2_do_cleanup_cfg |= purge_dead_edges (nfte->dest); 3506 bb = nfte->src; 3507 eh_edge = nehe; 3508 } 3509 3510 /* Converting possibly trapping insn to non-trapping is 3511 possible. Zap dummy outgoing edges. */ 3512 peep2_do_cleanup_cfg |= purge_dead_edges (bb); 3513 } 3514 3515 /* Re-insert the ARGS_SIZE notes. */ 3516 if (as_note) 3517 fixup_args_size_notes (before_try, last, get_args_size (as_note)); 3518 3519 /* If we generated a jump instruction, it won't have 3520 JUMP_LABEL set. Recompute after we're done. */ 3521 for (x = last; x != before_try; x = PREV_INSN (x)) 3522 if (JUMP_P (x)) 3523 { 3524 peep2_do_rebuild_jump_labels = true; 3525 break; 3526 } 3527 3528 return last; 3529 } 3530 3531 /* After performing a replacement in basic block BB, fix up the life 3532 information in our buffer. LAST is the last of the insns that we 3533 emitted as a replacement. PREV is the insn before the start of 3534 the replacement. MATCH_LEN is the number of instructions that were 3535 matched, and which now need to be replaced in the buffer. */ 3536 3537 static void 3538 peep2_update_life (basic_block bb, int match_len, rtx_insn *last, 3539 rtx_insn *prev) 3540 { 3541 int i = peep2_buf_position (peep2_current + match_len + 1); 3542 rtx_insn *x; 3543 regset_head live; 3544 3545 INIT_REG_SET (&live); 3546 COPY_REG_SET (&live, peep2_insn_data[i].live_before); 3547 3548 gcc_assert (peep2_current_count >= match_len + 1); 3549 peep2_current_count -= match_len + 1; 3550 3551 x = last; 3552 do 3553 { 3554 if (INSN_P (x)) 3555 { 3556 df_insn_rescan (x); 3557 if (peep2_current_count < MAX_INSNS_PER_PEEP2) 3558 { 3559 peep2_current_count++; 3560 if (--i < 0) 3561 i = MAX_INSNS_PER_PEEP2; 3562 peep2_insn_data[i].insn = x; 3563 df_simulate_one_insn_backwards (bb, x, &live); 3564 COPY_REG_SET (peep2_insn_data[i].live_before, &live); 3565 } 3566 } 3567 x = PREV_INSN (x); 3568 } 3569 while (x != prev); 3570 CLEAR_REG_SET (&live); 3571 3572 peep2_current = i; 3573 } 3574 3575 /* Add INSN, which is in BB, at the end of the peep2 insn buffer if possible. 3576 Return true if we added it, false otherwise. The caller will try to match 3577 peepholes against the buffer if we return false; otherwise it will try to 3578 add more instructions to the buffer. */ 3579 3580 static bool 3581 peep2_fill_buffer (basic_block bb, rtx_insn *insn, regset live) 3582 { 3583 int pos; 3584 3585 /* Once we have filled the maximum number of insns the buffer can hold, 3586 allow the caller to match the insns against peepholes. We wait until 3587 the buffer is full in case the target has similar peepholes of different 3588 length; we always want to match the longest if possible. */ 3589 if (peep2_current_count == MAX_INSNS_PER_PEEP2) 3590 return false; 3591 3592 /* If an insn has RTX_FRAME_RELATED_P set, do not allow it to be matched with 3593 any other pattern, lest it change the semantics of the frame info. */ 3594 if (RTX_FRAME_RELATED_P (insn)) 3595 { 3596 /* Let the buffer drain first. */ 3597 if (peep2_current_count > 0) 3598 return false; 3599 /* Now the insn will be the only thing in the buffer. */ 3600 } 3601 3602 pos = peep2_buf_position (peep2_current + peep2_current_count); 3603 peep2_insn_data[pos].insn = insn; 3604 COPY_REG_SET (peep2_insn_data[pos].live_before, live); 3605 peep2_current_count++; 3606 3607 df_simulate_one_insn_forwards (bb, insn, live); 3608 return true; 3609 } 3610 3611 /* Perform the peephole2 optimization pass. */ 3612 3613 static void 3614 peephole2_optimize (void) 3615 { 3616 rtx_insn *insn; 3617 bitmap live; 3618 int i; 3619 basic_block bb; 3620 3621 peep2_do_cleanup_cfg = false; 3622 peep2_do_rebuild_jump_labels = false; 3623 3624 df_set_flags (DF_LR_RUN_DCE); 3625 df_note_add_problem (); 3626 df_analyze (); 3627 3628 /* Initialize the regsets we're going to use. */ 3629 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) 3630 peep2_insn_data[i].live_before = BITMAP_ALLOC (®_obstack); 3631 search_ofs = 0; 3632 live = BITMAP_ALLOC (®_obstack); 3633 3634 FOR_EACH_BB_REVERSE_FN (bb, cfun) 3635 { 3636 bool past_end = false; 3637 int pos; 3638 3639 rtl_profile_for_bb (bb); 3640 3641 /* Start up propagation. */ 3642 bitmap_copy (live, DF_LR_IN (bb)); 3643 df_simulate_initialize_forwards (bb, live); 3644 peep2_reinit_state (live); 3645 3646 insn = BB_HEAD (bb); 3647 for (;;) 3648 { 3649 rtx_insn *attempt, *head; 3650 int match_len; 3651 3652 if (!past_end && !NONDEBUG_INSN_P (insn)) 3653 { 3654 next_insn: 3655 insn = NEXT_INSN (insn); 3656 if (insn == NEXT_INSN (BB_END (bb))) 3657 past_end = true; 3658 continue; 3659 } 3660 if (!past_end && peep2_fill_buffer (bb, insn, live)) 3661 goto next_insn; 3662 3663 /* If we did not fill an empty buffer, it signals the end of the 3664 block. */ 3665 if (peep2_current_count == 0) 3666 break; 3667 3668 /* The buffer filled to the current maximum, so try to match. */ 3669 3670 pos = peep2_buf_position (peep2_current + peep2_current_count); 3671 peep2_insn_data[pos].insn = PEEP2_EOB; 3672 COPY_REG_SET (peep2_insn_data[pos].live_before, live); 3673 3674 /* Match the peephole. */ 3675 head = peep2_insn_data[peep2_current].insn; 3676 attempt = peephole2_insns (PATTERN (head), head, &match_len); 3677 if (attempt != NULL) 3678 { 3679 rtx_insn *last = peep2_attempt (bb, head, match_len, attempt); 3680 if (last) 3681 { 3682 peep2_update_life (bb, match_len, last, PREV_INSN (attempt)); 3683 continue; 3684 } 3685 } 3686 3687 /* No match: advance the buffer by one insn. */ 3688 peep2_current = peep2_buf_position (peep2_current + 1); 3689 peep2_current_count--; 3690 } 3691 } 3692 3693 default_rtl_profile (); 3694 for (i = 0; i < MAX_INSNS_PER_PEEP2 + 1; ++i) 3695 BITMAP_FREE (peep2_insn_data[i].live_before); 3696 BITMAP_FREE (live); 3697 if (peep2_do_rebuild_jump_labels) 3698 rebuild_jump_labels (get_insns ()); 3699 if (peep2_do_cleanup_cfg) 3700 cleanup_cfg (CLEANUP_CFG_CHANGED); 3701 } 3702 3703 /* Common predicates for use with define_bypass. */ 3704 3705 /* Helper function for store_data_bypass_p, handle just a single SET 3706 IN_SET. */ 3707 3708 static bool 3709 store_data_bypass_p_1 (rtx_insn *out_insn, rtx in_set) 3710 { 3711 if (!MEM_P (SET_DEST (in_set))) 3712 return false; 3713 3714 rtx out_set = single_set (out_insn); 3715 if (out_set) 3716 return !reg_mentioned_p (SET_DEST (out_set), SET_DEST (in_set)); 3717 3718 rtx out_pat = PATTERN (out_insn); 3719 if (GET_CODE (out_pat) != PARALLEL) 3720 return false; 3721 3722 for (int i = 0; i < XVECLEN (out_pat, 0); i++) 3723 { 3724 rtx out_exp = XVECEXP (out_pat, 0, i); 3725 3726 if (GET_CODE (out_exp) == CLOBBER || GET_CODE (out_exp) == USE) 3727 continue; 3728 3729 gcc_assert (GET_CODE (out_exp) == SET); 3730 3731 if (reg_mentioned_p (SET_DEST (out_exp), SET_DEST (in_set))) 3732 return false; 3733 } 3734 3735 return true; 3736 } 3737 3738 /* True if the dependency between OUT_INSN and IN_INSN is on the store 3739 data not the address operand(s) of the store. IN_INSN and OUT_INSN 3740 must be either a single_set or a PARALLEL with SETs inside. */ 3741 3742 int 3743 store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) 3744 { 3745 rtx in_set = single_set (in_insn); 3746 if (in_set) 3747 return store_data_bypass_p_1 (out_insn, in_set); 3748 3749 rtx in_pat = PATTERN (in_insn); 3750 if (GET_CODE (in_pat) != PARALLEL) 3751 return false; 3752 3753 for (int i = 0; i < XVECLEN (in_pat, 0); i++) 3754 { 3755 rtx in_exp = XVECEXP (in_pat, 0, i); 3756 3757 if (GET_CODE (in_exp) == CLOBBER || GET_CODE (in_exp) == USE) 3758 continue; 3759 3760 gcc_assert (GET_CODE (in_exp) == SET); 3761 3762 if (!store_data_bypass_p_1 (out_insn, in_exp)) 3763 return false; 3764 } 3765 3766 return true; 3767 } 3768 3769 /* True if the dependency between OUT_INSN and IN_INSN is in the IF_THEN_ELSE 3770 condition, and not the THEN or ELSE branch. OUT_INSN may be either a single 3771 or multiple set; IN_INSN should be single_set for truth, but for convenience 3772 of insn categorization may be any JUMP or CALL insn. */ 3773 3774 int 3775 if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) 3776 { 3777 rtx out_set, in_set; 3778 3779 in_set = single_set (in_insn); 3780 if (! in_set) 3781 { 3782 gcc_assert (JUMP_P (in_insn) || CALL_P (in_insn)); 3783 return false; 3784 } 3785 3786 if (GET_CODE (SET_SRC (in_set)) != IF_THEN_ELSE) 3787 return false; 3788 in_set = SET_SRC (in_set); 3789 3790 out_set = single_set (out_insn); 3791 if (out_set) 3792 { 3793 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1)) 3794 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2))) 3795 return false; 3796 } 3797 else 3798 { 3799 rtx out_pat; 3800 int i; 3801 3802 out_pat = PATTERN (out_insn); 3803 gcc_assert (GET_CODE (out_pat) == PARALLEL); 3804 3805 for (i = 0; i < XVECLEN (out_pat, 0); i++) 3806 { 3807 rtx exp = XVECEXP (out_pat, 0, i); 3808 3809 if (GET_CODE (exp) == CLOBBER) 3810 continue; 3811 3812 gcc_assert (GET_CODE (exp) == SET); 3813 3814 if (reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 1)) 3815 || reg_mentioned_p (SET_DEST (out_set), XEXP (in_set, 2))) 3816 return false; 3817 } 3818 } 3819 3820 return true; 3821 } 3822 3823 static unsigned int 3824 rest_of_handle_peephole2 (void) 3825 { 3826 if (HAVE_peephole2) 3827 peephole2_optimize (); 3828 3829 return 0; 3830 } 3831 3832 namespace { 3833 3834 const pass_data pass_data_peephole2 = 3835 { 3836 RTL_PASS, /* type */ 3837 "peephole2", /* name */ 3838 OPTGROUP_NONE, /* optinfo_flags */ 3839 TV_PEEPHOLE2, /* tv_id */ 3840 0, /* properties_required */ 3841 0, /* properties_provided */ 3842 0, /* properties_destroyed */ 3843 0, /* todo_flags_start */ 3844 TODO_df_finish, /* todo_flags_finish */ 3845 }; 3846 3847 class pass_peephole2 : public rtl_opt_pass 3848 { 3849 public: 3850 pass_peephole2 (gcc::context *ctxt) 3851 : rtl_opt_pass (pass_data_peephole2, ctxt) 3852 {} 3853 3854 /* opt_pass methods: */ 3855 /* The epiphany backend creates a second instance of this pass, so we need 3856 a clone method. */ 3857 opt_pass * clone () { return new pass_peephole2 (m_ctxt); } 3858 virtual bool gate (function *) { return (optimize > 0 && flag_peephole2); } 3859 virtual unsigned int execute (function *) 3860 { 3861 return rest_of_handle_peephole2 (); 3862 } 3863 3864 }; // class pass_peephole2 3865 3866 } // anon namespace 3867 3868 rtl_opt_pass * 3869 make_pass_peephole2 (gcc::context *ctxt) 3870 { 3871 return new pass_peephole2 (ctxt); 3872 } 3873 3874 namespace { 3875 3876 const pass_data pass_data_split_all_insns = 3877 { 3878 RTL_PASS, /* type */ 3879 "split1", /* name */ 3880 OPTGROUP_NONE, /* optinfo_flags */ 3881 TV_NONE, /* tv_id */ 3882 0, /* properties_required */ 3883 PROP_rtl_split_insns, /* properties_provided */ 3884 0, /* properties_destroyed */ 3885 0, /* todo_flags_start */ 3886 0, /* todo_flags_finish */ 3887 }; 3888 3889 class pass_split_all_insns : public rtl_opt_pass 3890 { 3891 public: 3892 pass_split_all_insns (gcc::context *ctxt) 3893 : rtl_opt_pass (pass_data_split_all_insns, ctxt) 3894 {} 3895 3896 /* opt_pass methods: */ 3897 /* The epiphany backend creates a second instance of this pass, so 3898 we need a clone method. */ 3899 opt_pass * clone () { return new pass_split_all_insns (m_ctxt); } 3900 virtual unsigned int execute (function *) 3901 { 3902 split_all_insns (); 3903 return 0; 3904 } 3905 3906 }; // class pass_split_all_insns 3907 3908 } // anon namespace 3909 3910 rtl_opt_pass * 3911 make_pass_split_all_insns (gcc::context *ctxt) 3912 { 3913 return new pass_split_all_insns (ctxt); 3914 } 3915 3916 namespace { 3917 3918 const pass_data pass_data_split_after_reload = 3919 { 3920 RTL_PASS, /* type */ 3921 "split2", /* name */ 3922 OPTGROUP_NONE, /* optinfo_flags */ 3923 TV_NONE, /* tv_id */ 3924 0, /* properties_required */ 3925 0, /* properties_provided */ 3926 0, /* properties_destroyed */ 3927 0, /* todo_flags_start */ 3928 0, /* todo_flags_finish */ 3929 }; 3930 3931 class pass_split_after_reload : public rtl_opt_pass 3932 { 3933 public: 3934 pass_split_after_reload (gcc::context *ctxt) 3935 : rtl_opt_pass (pass_data_split_after_reload, ctxt) 3936 {} 3937 3938 /* opt_pass methods: */ 3939 virtual bool gate (function *) 3940 { 3941 /* If optimizing, then go ahead and split insns now. */ 3942 if (optimize > 0) 3943 return true; 3944 3945 #ifdef STACK_REGS 3946 return true; 3947 #else 3948 return false; 3949 #endif 3950 } 3951 3952 virtual unsigned int execute (function *) 3953 { 3954 split_all_insns (); 3955 return 0; 3956 } 3957 3958 }; // class pass_split_after_reload 3959 3960 } // anon namespace 3961 3962 rtl_opt_pass * 3963 make_pass_split_after_reload (gcc::context *ctxt) 3964 { 3965 return new pass_split_after_reload (ctxt); 3966 } 3967 3968 namespace { 3969 3970 const pass_data pass_data_split_before_regstack = 3971 { 3972 RTL_PASS, /* type */ 3973 "split3", /* name */ 3974 OPTGROUP_NONE, /* optinfo_flags */ 3975 TV_NONE, /* tv_id */ 3976 0, /* properties_required */ 3977 0, /* properties_provided */ 3978 0, /* properties_destroyed */ 3979 0, /* todo_flags_start */ 3980 0, /* todo_flags_finish */ 3981 }; 3982 3983 class pass_split_before_regstack : public rtl_opt_pass 3984 { 3985 public: 3986 pass_split_before_regstack (gcc::context *ctxt) 3987 : rtl_opt_pass (pass_data_split_before_regstack, ctxt) 3988 {} 3989 3990 /* opt_pass methods: */ 3991 virtual bool gate (function *); 3992 virtual unsigned int execute (function *) 3993 { 3994 split_all_insns (); 3995 return 0; 3996 } 3997 3998 }; // class pass_split_before_regstack 3999 4000 bool 4001 pass_split_before_regstack::gate (function *) 4002 { 4003 #if HAVE_ATTR_length && defined (STACK_REGS) 4004 /* If flow2 creates new instructions which need splitting 4005 and scheduling after reload is not done, they might not be 4006 split until final which doesn't allow splitting 4007 if HAVE_ATTR_length. */ 4008 # ifdef INSN_SCHEDULING 4009 return (optimize && !flag_schedule_insns_after_reload); 4010 # else 4011 return (optimize); 4012 # endif 4013 #else 4014 return 0; 4015 #endif 4016 } 4017 4018 } // anon namespace 4019 4020 rtl_opt_pass * 4021 make_pass_split_before_regstack (gcc::context *ctxt) 4022 { 4023 return new pass_split_before_regstack (ctxt); 4024 } 4025 4026 static unsigned int 4027 rest_of_handle_split_before_sched2 (void) 4028 { 4029 #ifdef INSN_SCHEDULING 4030 split_all_insns (); 4031 #endif 4032 return 0; 4033 } 4034 4035 namespace { 4036 4037 const pass_data pass_data_split_before_sched2 = 4038 { 4039 RTL_PASS, /* type */ 4040 "split4", /* name */ 4041 OPTGROUP_NONE, /* optinfo_flags */ 4042 TV_NONE, /* tv_id */ 4043 0, /* properties_required */ 4044 0, /* properties_provided */ 4045 0, /* properties_destroyed */ 4046 0, /* todo_flags_start */ 4047 0, /* todo_flags_finish */ 4048 }; 4049 4050 class pass_split_before_sched2 : public rtl_opt_pass 4051 { 4052 public: 4053 pass_split_before_sched2 (gcc::context *ctxt) 4054 : rtl_opt_pass (pass_data_split_before_sched2, ctxt) 4055 {} 4056 4057 /* opt_pass methods: */ 4058 virtual bool gate (function *) 4059 { 4060 #ifdef INSN_SCHEDULING 4061 return optimize > 0 && flag_schedule_insns_after_reload; 4062 #else 4063 return false; 4064 #endif 4065 } 4066 4067 virtual unsigned int execute (function *) 4068 { 4069 return rest_of_handle_split_before_sched2 (); 4070 } 4071 4072 }; // class pass_split_before_sched2 4073 4074 } // anon namespace 4075 4076 rtl_opt_pass * 4077 make_pass_split_before_sched2 (gcc::context *ctxt) 4078 { 4079 return new pass_split_before_sched2 (ctxt); 4080 } 4081 4082 namespace { 4083 4084 const pass_data pass_data_split_for_shorten_branches = 4085 { 4086 RTL_PASS, /* type */ 4087 "split5", /* name */ 4088 OPTGROUP_NONE, /* optinfo_flags */ 4089 TV_NONE, /* tv_id */ 4090 0, /* properties_required */ 4091 0, /* properties_provided */ 4092 0, /* properties_destroyed */ 4093 0, /* todo_flags_start */ 4094 0, /* todo_flags_finish */ 4095 }; 4096 4097 class pass_split_for_shorten_branches : public rtl_opt_pass 4098 { 4099 public: 4100 pass_split_for_shorten_branches (gcc::context *ctxt) 4101 : rtl_opt_pass (pass_data_split_for_shorten_branches, ctxt) 4102 {} 4103 4104 /* opt_pass methods: */ 4105 virtual bool gate (function *) 4106 { 4107 /* The placement of the splitting that we do for shorten_branches 4108 depends on whether regstack is used by the target or not. */ 4109 #if HAVE_ATTR_length && !defined (STACK_REGS) 4110 return true; 4111 #else 4112 return false; 4113 #endif 4114 } 4115 4116 virtual unsigned int execute (function *) 4117 { 4118 return split_all_insns_noflow (); 4119 } 4120 4121 }; // class pass_split_for_shorten_branches 4122 4123 } // anon namespace 4124 4125 rtl_opt_pass * 4126 make_pass_split_for_shorten_branches (gcc::context *ctxt) 4127 { 4128 return new pass_split_for_shorten_branches (ctxt); 4129 } 4130 4131 /* (Re)initialize the target information after a change in target. */ 4132 4133 void 4134 recog_init () 4135 { 4136 /* The information is zero-initialized, so we don't need to do anything 4137 first time round. */ 4138 if (!this_target_recog->x_initialized) 4139 { 4140 this_target_recog->x_initialized = true; 4141 return; 4142 } 4143 memset (this_target_recog->x_bool_attr_masks, 0, 4144 sizeof (this_target_recog->x_bool_attr_masks)); 4145 for (unsigned int i = 0; i < NUM_INSN_CODES; ++i) 4146 if (this_target_recog->x_op_alt[i]) 4147 { 4148 free (this_target_recog->x_op_alt[i]); 4149 this_target_recog->x_op_alt[i] = 0; 4150 } 4151 } 4152