1 /* Perform simple optimizations to clean up the result of reload. 2 Copyright (C) 1987-2017 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "backend.h" 24 #include "target.h" 25 #include "rtl.h" 26 #include "tree.h" 27 #include "predict.h" 28 #include "df.h" 29 #include "memmodel.h" 30 #include "tm_p.h" 31 #include "optabs.h" 32 #include "regs.h" 33 #include "emit-rtl.h" 34 #include "recog.h" 35 36 #include "cfgrtl.h" 37 #include "cfgbuild.h" 38 #include "cfgcleanup.h" 39 #include "reload.h" 40 #include "cselib.h" 41 #include "tree-pass.h" 42 #include "dbgcnt.h" 43 44 static int reload_cse_noop_set_p (rtx); 45 static bool reload_cse_simplify (rtx_insn *, rtx); 46 static void reload_cse_regs_1 (void); 47 static int reload_cse_simplify_set (rtx, rtx_insn *); 48 static int reload_cse_simplify_operands (rtx_insn *, rtx); 49 50 static void reload_combine (void); 51 static void reload_combine_note_use (rtx *, rtx_insn *, int, rtx); 52 static void reload_combine_note_store (rtx, const_rtx, void *); 53 54 static bool reload_cse_move2add (rtx_insn *); 55 static void move2add_note_store (rtx, const_rtx, void *); 56 57 /* Call cse / combine like post-reload optimization phases. 58 FIRST is the first instruction. */ 59 60 static void 61 reload_cse_regs (rtx_insn *first ATTRIBUTE_UNUSED) 62 { 63 bool moves_converted; 64 reload_cse_regs_1 (); 65 reload_combine (); 66 moves_converted = reload_cse_move2add (first); 67 if (flag_expensive_optimizations) 68 { 69 if (moves_converted) 70 reload_combine (); 71 reload_cse_regs_1 (); 72 } 73 } 74 75 /* See whether a single set SET is a noop. */ 76 static int 77 reload_cse_noop_set_p (rtx set) 78 { 79 if (cselib_reg_set_mode (SET_DEST (set)) != GET_MODE (SET_DEST (set))) 80 return 0; 81 82 return rtx_equal_for_cselib_p (SET_DEST (set), SET_SRC (set)); 83 } 84 85 /* Try to simplify INSN. Return true if the CFG may have changed. */ 86 static bool 87 reload_cse_simplify (rtx_insn *insn, rtx testreg) 88 { 89 rtx body = PATTERN (insn); 90 basic_block insn_bb = BLOCK_FOR_INSN (insn); 91 unsigned insn_bb_succs = EDGE_COUNT (insn_bb->succs); 92 93 /* If NO_FUNCTION_CSE has been set by the target, then we should not try 94 to cse function calls. */ 95 if (NO_FUNCTION_CSE && CALL_P (insn)) 96 return false; 97 98 if (GET_CODE (body) == SET) 99 { 100 int count = 0; 101 102 /* Simplify even if we may think it is a no-op. 103 We may think a memory load of a value smaller than WORD_SIZE 104 is redundant because we haven't taken into account possible 105 implicit extension. reload_cse_simplify_set() will bring 106 this out, so it's safer to simplify before we delete. */ 107 count += reload_cse_simplify_set (body, insn); 108 109 if (!count && reload_cse_noop_set_p (body)) 110 { 111 if (check_for_inc_dec (insn)) 112 delete_insn_and_edges (insn); 113 /* We're done with this insn. */ 114 goto done; 115 } 116 117 if (count > 0) 118 apply_change_group (); 119 else 120 reload_cse_simplify_operands (insn, testreg); 121 } 122 else if (GET_CODE (body) == PARALLEL) 123 { 124 int i; 125 int count = 0; 126 rtx value = NULL_RTX; 127 128 /* Registers mentioned in the clobber list for an asm cannot be reused 129 within the body of the asm. Invalidate those registers now so that 130 we don't try to substitute values for them. */ 131 if (asm_noperands (body) >= 0) 132 { 133 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 134 { 135 rtx part = XVECEXP (body, 0, i); 136 if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0))) 137 cselib_invalidate_rtx (XEXP (part, 0)); 138 } 139 } 140 141 /* If every action in a PARALLEL is a noop, we can delete 142 the entire PARALLEL. */ 143 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 144 { 145 rtx part = XVECEXP (body, 0, i); 146 if (GET_CODE (part) == SET) 147 { 148 if (! reload_cse_noop_set_p (part)) 149 break; 150 if (REG_P (SET_DEST (part)) 151 && REG_FUNCTION_VALUE_P (SET_DEST (part))) 152 { 153 if (value) 154 break; 155 value = SET_DEST (part); 156 } 157 } 158 else if (GET_CODE (part) != CLOBBER 159 && GET_CODE (part) != USE) 160 break; 161 } 162 163 if (i < 0) 164 { 165 if (check_for_inc_dec (insn)) 166 delete_insn_and_edges (insn); 167 /* We're done with this insn. */ 168 goto done; 169 } 170 171 /* It's not a no-op, but we can try to simplify it. */ 172 for (i = XVECLEN (body, 0) - 1; i >= 0; --i) 173 if (GET_CODE (XVECEXP (body, 0, i)) == SET) 174 count += reload_cse_simplify_set (XVECEXP (body, 0, i), insn); 175 176 if (count > 0) 177 apply_change_group (); 178 else 179 reload_cse_simplify_operands (insn, testreg); 180 } 181 182 done: 183 return (EDGE_COUNT (insn_bb->succs) != insn_bb_succs); 184 } 185 186 /* Do a very simple CSE pass over the hard registers. 187 188 This function detects no-op moves where we happened to assign two 189 different pseudo-registers to the same hard register, and then 190 copied one to the other. Reload will generate a useless 191 instruction copying a register to itself. 192 193 This function also detects cases where we load a value from memory 194 into two different registers, and (if memory is more expensive than 195 registers) changes it to simply copy the first register into the 196 second register. 197 198 Another optimization is performed that scans the operands of each 199 instruction to see whether the value is already available in a 200 hard register. It then replaces the operand with the hard register 201 if possible, much like an optional reload would. */ 202 203 static void 204 reload_cse_regs_1 (void) 205 { 206 bool cfg_changed = false; 207 basic_block bb; 208 rtx_insn *insn; 209 rtx testreg = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); 210 211 cselib_init (CSELIB_RECORD_MEMORY); 212 init_alias_analysis (); 213 214 FOR_EACH_BB_FN (bb, cfun) 215 FOR_BB_INSNS (bb, insn) 216 { 217 if (INSN_P (insn)) 218 cfg_changed |= reload_cse_simplify (insn, testreg); 219 220 cselib_process_insn (insn); 221 } 222 223 /* Clean up. */ 224 end_alias_analysis (); 225 cselib_finish (); 226 if (cfg_changed) 227 cleanup_cfg (0); 228 } 229 230 /* Try to simplify a single SET instruction. SET is the set pattern. 231 INSN is the instruction it came from. 232 This function only handles one case: if we set a register to a value 233 which is not a register, we try to find that value in some other register 234 and change the set into a register copy. */ 235 236 static int 237 reload_cse_simplify_set (rtx set, rtx_insn *insn) 238 { 239 int did_change = 0; 240 int dreg; 241 rtx src; 242 reg_class_t dclass; 243 int old_cost; 244 cselib_val *val; 245 struct elt_loc_list *l; 246 enum rtx_code extend_op = UNKNOWN; 247 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); 248 249 dreg = true_regnum (SET_DEST (set)); 250 if (dreg < 0) 251 return 0; 252 253 src = SET_SRC (set); 254 if (side_effects_p (src) || true_regnum (src) >= 0) 255 return 0; 256 257 dclass = REGNO_REG_CLASS (dreg); 258 259 /* When replacing a memory with a register, we need to honor assumptions 260 that combine made wrt the contents of sign bits. We'll do this by 261 generating an extend instruction instead of a reg->reg copy. Thus 262 the destination must be a register that we can widen. */ 263 if (MEM_P (src) 264 && (extend_op = load_extend_op (GET_MODE (src))) != UNKNOWN 265 && !REG_P (SET_DEST (set))) 266 return 0; 267 268 val = cselib_lookup (src, GET_MODE (SET_DEST (set)), 0, VOIDmode); 269 if (! val) 270 return 0; 271 272 /* If memory loads are cheaper than register copies, don't change them. */ 273 if (MEM_P (src)) 274 old_cost = memory_move_cost (GET_MODE (src), dclass, true); 275 else if (REG_P (src)) 276 old_cost = register_move_cost (GET_MODE (src), 277 REGNO_REG_CLASS (REGNO (src)), dclass); 278 else 279 old_cost = set_src_cost (src, GET_MODE (SET_DEST (set)), speed); 280 281 for (l = val->locs; l; l = l->next) 282 { 283 rtx this_rtx = l->loc; 284 int this_cost; 285 286 if (CONSTANT_P (this_rtx) && ! references_value_p (this_rtx, 0)) 287 { 288 if (extend_op != UNKNOWN) 289 { 290 wide_int result; 291 292 if (!CONST_SCALAR_INT_P (this_rtx)) 293 continue; 294 295 switch (extend_op) 296 { 297 case ZERO_EXTEND: 298 result = wide_int::from (rtx_mode_t (this_rtx, 299 GET_MODE (src)), 300 BITS_PER_WORD, UNSIGNED); 301 break; 302 case SIGN_EXTEND: 303 result = wide_int::from (rtx_mode_t (this_rtx, 304 GET_MODE (src)), 305 BITS_PER_WORD, SIGNED); 306 break; 307 default: 308 gcc_unreachable (); 309 } 310 this_rtx = immed_wide_int_const (result, word_mode); 311 } 312 313 this_cost = set_src_cost (this_rtx, GET_MODE (SET_DEST (set)), speed); 314 } 315 else if (REG_P (this_rtx)) 316 { 317 if (extend_op != UNKNOWN) 318 { 319 this_rtx = gen_rtx_fmt_e (extend_op, word_mode, this_rtx); 320 this_cost = set_src_cost (this_rtx, word_mode, speed); 321 } 322 else 323 this_cost = register_move_cost (GET_MODE (this_rtx), 324 REGNO_REG_CLASS (REGNO (this_rtx)), 325 dclass); 326 } 327 else 328 continue; 329 330 /* If equal costs, prefer registers over anything else. That 331 tends to lead to smaller instructions on some machines. */ 332 if (this_cost < old_cost 333 || (this_cost == old_cost 334 && REG_P (this_rtx) 335 && !REG_P (SET_SRC (set)))) 336 { 337 if (extend_op != UNKNOWN 338 #ifdef CANNOT_CHANGE_MODE_CLASS 339 && !CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), 340 word_mode, 341 REGNO_REG_CLASS (REGNO (SET_DEST (set)))) 342 #endif 343 ) 344 { 345 rtx wide_dest = gen_rtx_REG (word_mode, REGNO (SET_DEST (set))); 346 ORIGINAL_REGNO (wide_dest) = ORIGINAL_REGNO (SET_DEST (set)); 347 validate_change (insn, &SET_DEST (set), wide_dest, 1); 348 } 349 350 validate_unshare_change (insn, &SET_SRC (set), this_rtx, 1); 351 old_cost = this_cost, did_change = 1; 352 } 353 } 354 355 return did_change; 356 } 357 358 /* Try to replace operands in INSN with equivalent values that are already 359 in registers. This can be viewed as optional reloading. 360 361 For each non-register operand in the insn, see if any hard regs are 362 known to be equivalent to that operand. Record the alternatives which 363 can accept these hard registers. Among all alternatives, select the 364 ones which are better or equal to the one currently matching, where 365 "better" is in terms of '?' and '!' constraints. Among the remaining 366 alternatives, select the one which replaces most operands with 367 hard registers. */ 368 369 static int 370 reload_cse_simplify_operands (rtx_insn *insn, rtx testreg) 371 { 372 int i, j; 373 374 /* For each operand, all registers that are equivalent to it. */ 375 HARD_REG_SET equiv_regs[MAX_RECOG_OPERANDS]; 376 377 const char *constraints[MAX_RECOG_OPERANDS]; 378 379 /* Vector recording how bad an alternative is. */ 380 int *alternative_reject; 381 /* Vector recording how many registers can be introduced by choosing 382 this alternative. */ 383 int *alternative_nregs; 384 /* Array of vectors recording, for each operand and each alternative, 385 which hard register to substitute, or -1 if the operand should be 386 left as it is. */ 387 int *op_alt_regno[MAX_RECOG_OPERANDS]; 388 /* Array of alternatives, sorted in order of decreasing desirability. */ 389 int *alternative_order; 390 391 extract_constrain_insn (insn); 392 393 if (recog_data.n_alternatives == 0 || recog_data.n_operands == 0) 394 return 0; 395 396 alternative_reject = XALLOCAVEC (int, recog_data.n_alternatives); 397 alternative_nregs = XALLOCAVEC (int, recog_data.n_alternatives); 398 alternative_order = XALLOCAVEC (int, recog_data.n_alternatives); 399 memset (alternative_reject, 0, recog_data.n_alternatives * sizeof (int)); 400 memset (alternative_nregs, 0, recog_data.n_alternatives * sizeof (int)); 401 402 /* For each operand, find out which regs are equivalent. */ 403 for (i = 0; i < recog_data.n_operands; i++) 404 { 405 cselib_val *v; 406 struct elt_loc_list *l; 407 rtx op; 408 409 CLEAR_HARD_REG_SET (equiv_regs[i]); 410 411 /* cselib blows up on CODE_LABELs. Trying to fix that doesn't seem 412 right, so avoid the problem here. Likewise if we have a constant 413 and the insn pattern doesn't tell us the mode we need. */ 414 if (LABEL_P (recog_data.operand[i]) 415 || (CONSTANT_P (recog_data.operand[i]) 416 && recog_data.operand_mode[i] == VOIDmode)) 417 continue; 418 419 op = recog_data.operand[i]; 420 if (MEM_P (op) && load_extend_op (GET_MODE (op)) != UNKNOWN) 421 { 422 rtx set = single_set (insn); 423 424 /* We might have multiple sets, some of which do implicit 425 extension. Punt on this for now. */ 426 if (! set) 427 continue; 428 /* If the destination is also a MEM or a STRICT_LOW_PART, no 429 extension applies. 430 Also, if there is an explicit extension, we don't have to 431 worry about an implicit one. */ 432 else if (MEM_P (SET_DEST (set)) 433 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART 434 || GET_CODE (SET_SRC (set)) == ZERO_EXTEND 435 || GET_CODE (SET_SRC (set)) == SIGN_EXTEND) 436 ; /* Continue ordinary processing. */ 437 #ifdef CANNOT_CHANGE_MODE_CLASS 438 /* If the register cannot change mode to word_mode, it follows that 439 it cannot have been used in word_mode. */ 440 else if (REG_P (SET_DEST (set)) 441 && CANNOT_CHANGE_MODE_CLASS (GET_MODE (SET_DEST (set)), 442 word_mode, 443 REGNO_REG_CLASS (REGNO (SET_DEST (set))))) 444 ; /* Continue ordinary processing. */ 445 #endif 446 /* If this is a straight load, make the extension explicit. */ 447 else if (REG_P (SET_DEST (set)) 448 && recog_data.n_operands == 2 449 && SET_SRC (set) == op 450 && SET_DEST (set) == recog_data.operand[1-i]) 451 { 452 validate_change (insn, recog_data.operand_loc[i], 453 gen_rtx_fmt_e (load_extend_op (GET_MODE (op)), 454 word_mode, op), 455 1); 456 validate_change (insn, recog_data.operand_loc[1-i], 457 gen_rtx_REG (word_mode, REGNO (SET_DEST (set))), 458 1); 459 if (! apply_change_group ()) 460 return 0; 461 return reload_cse_simplify_operands (insn, testreg); 462 } 463 else 464 /* ??? There might be arithmetic operations with memory that are 465 safe to optimize, but is it worth the trouble? */ 466 continue; 467 } 468 469 if (side_effects_p (op)) 470 continue; 471 v = cselib_lookup (op, recog_data.operand_mode[i], 0, VOIDmode); 472 if (! v) 473 continue; 474 475 for (l = v->locs; l; l = l->next) 476 if (REG_P (l->loc)) 477 SET_HARD_REG_BIT (equiv_regs[i], REGNO (l->loc)); 478 } 479 480 alternative_mask preferred = get_preferred_alternatives (insn); 481 for (i = 0; i < recog_data.n_operands; i++) 482 { 483 machine_mode mode; 484 int regno; 485 const char *p; 486 487 op_alt_regno[i] = XALLOCAVEC (int, recog_data.n_alternatives); 488 for (j = 0; j < recog_data.n_alternatives; j++) 489 op_alt_regno[i][j] = -1; 490 491 p = constraints[i] = recog_data.constraints[i]; 492 mode = recog_data.operand_mode[i]; 493 494 /* Add the reject values for each alternative given by the constraints 495 for this operand. */ 496 j = 0; 497 while (*p != '\0') 498 { 499 char c = *p++; 500 if (c == ',') 501 j++; 502 else if (c == '?') 503 alternative_reject[j] += 3; 504 else if (c == '!') 505 alternative_reject[j] += 300; 506 } 507 508 /* We won't change operands which are already registers. We 509 also don't want to modify output operands. */ 510 regno = true_regnum (recog_data.operand[i]); 511 if (regno >= 0 512 || constraints[i][0] == '=' 513 || constraints[i][0] == '+') 514 continue; 515 516 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 517 { 518 enum reg_class rclass = NO_REGS; 519 520 if (! TEST_HARD_REG_BIT (equiv_regs[i], regno)) 521 continue; 522 523 set_mode_and_regno (testreg, mode, regno); 524 525 /* We found a register equal to this operand. Now look for all 526 alternatives that can accept this register and have not been 527 assigned a register they can use yet. */ 528 j = 0; 529 p = constraints[i]; 530 for (;;) 531 { 532 char c = *p; 533 534 switch (c) 535 { 536 case 'g': 537 rclass = reg_class_subunion[rclass][GENERAL_REGS]; 538 break; 539 540 default: 541 rclass 542 = (reg_class_subunion 543 [rclass] 544 [reg_class_for_constraint (lookup_constraint (p))]); 545 break; 546 547 case ',': case '\0': 548 /* See if REGNO fits this alternative, and set it up as the 549 replacement register if we don't have one for this 550 alternative yet and the operand being replaced is not 551 a cheap CONST_INT. */ 552 if (op_alt_regno[i][j] == -1 553 && TEST_BIT (preferred, j) 554 && reg_fits_class_p (testreg, rclass, 0, mode) 555 && (!CONST_INT_P (recog_data.operand[i]) 556 || (set_src_cost (recog_data.operand[i], mode, 557 optimize_bb_for_speed_p 558 (BLOCK_FOR_INSN (insn))) 559 > set_src_cost (testreg, mode, 560 optimize_bb_for_speed_p 561 (BLOCK_FOR_INSN (insn)))))) 562 { 563 alternative_nregs[j]++; 564 op_alt_regno[i][j] = regno; 565 } 566 j++; 567 rclass = NO_REGS; 568 break; 569 } 570 p += CONSTRAINT_LEN (c, p); 571 572 if (c == '\0') 573 break; 574 } 575 } 576 } 577 578 /* Record all alternatives which are better or equal to the currently 579 matching one in the alternative_order array. */ 580 for (i = j = 0; i < recog_data.n_alternatives; i++) 581 if (alternative_reject[i] <= alternative_reject[which_alternative]) 582 alternative_order[j++] = i; 583 recog_data.n_alternatives = j; 584 585 /* Sort it. Given a small number of alternatives, a dumb algorithm 586 won't hurt too much. */ 587 for (i = 0; i < recog_data.n_alternatives - 1; i++) 588 { 589 int best = i; 590 int best_reject = alternative_reject[alternative_order[i]]; 591 int best_nregs = alternative_nregs[alternative_order[i]]; 592 593 for (j = i + 1; j < recog_data.n_alternatives; j++) 594 { 595 int this_reject = alternative_reject[alternative_order[j]]; 596 int this_nregs = alternative_nregs[alternative_order[j]]; 597 598 if (this_reject < best_reject 599 || (this_reject == best_reject && this_nregs > best_nregs)) 600 { 601 best = j; 602 best_reject = this_reject; 603 best_nregs = this_nregs; 604 } 605 } 606 607 std::swap (alternative_order[best], alternative_order[i]); 608 } 609 610 /* Substitute the operands as determined by op_alt_regno for the best 611 alternative. */ 612 j = alternative_order[0]; 613 614 for (i = 0; i < recog_data.n_operands; i++) 615 { 616 machine_mode mode = recog_data.operand_mode[i]; 617 if (op_alt_regno[i][j] == -1) 618 continue; 619 620 validate_change (insn, recog_data.operand_loc[i], 621 gen_rtx_REG (mode, op_alt_regno[i][j]), 1); 622 } 623 624 for (i = recog_data.n_dups - 1; i >= 0; i--) 625 { 626 int op = recog_data.dup_num[i]; 627 machine_mode mode = recog_data.operand_mode[op]; 628 629 if (op_alt_regno[op][j] == -1) 630 continue; 631 632 validate_change (insn, recog_data.dup_loc[i], 633 gen_rtx_REG (mode, op_alt_regno[op][j]), 1); 634 } 635 636 return apply_change_group (); 637 } 638 639 /* If reload couldn't use reg+reg+offset addressing, try to use reg+reg 640 addressing now. 641 This code might also be useful when reload gave up on reg+reg addressing 642 because of clashes between the return register and INDEX_REG_CLASS. */ 643 644 /* The maximum number of uses of a register we can keep track of to 645 replace them with reg+reg addressing. */ 646 #define RELOAD_COMBINE_MAX_USES 16 647 648 /* Describes a recorded use of a register. */ 649 struct reg_use 650 { 651 /* The insn where a register has been used. */ 652 rtx_insn *insn; 653 /* Points to the memory reference enclosing the use, if any, NULL_RTX 654 otherwise. */ 655 rtx containing_mem; 656 /* Location of the register within INSN. */ 657 rtx *usep; 658 /* The reverse uid of the insn. */ 659 int ruid; 660 }; 661 662 /* If the register is used in some unknown fashion, USE_INDEX is negative. 663 If it is dead, USE_INDEX is RELOAD_COMBINE_MAX_USES, and STORE_RUID 664 indicates where it is first set or clobbered. 665 Otherwise, USE_INDEX is the index of the last encountered use of the 666 register (which is first among these we have seen since we scan backwards). 667 USE_RUID indicates the first encountered, i.e. last, of these uses. 668 If ALL_OFFSETS_MATCH is true, all encountered uses were inside a PLUS 669 with a constant offset; OFFSET contains this constant in that case. 670 STORE_RUID is always meaningful if we only want to use a value in a 671 register in a different place: it denotes the next insn in the insn 672 stream (i.e. the last encountered) that sets or clobbers the register. 673 REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ 674 static struct 675 { 676 struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; 677 rtx offset; 678 int use_index; 679 int store_ruid; 680 int real_store_ruid; 681 int use_ruid; 682 bool all_offsets_match; 683 } reg_state[FIRST_PSEUDO_REGISTER]; 684 685 /* Reverse linear uid. This is increased in reload_combine while scanning 686 the instructions from last to first. It is used to set last_label_ruid 687 and the store_ruid / use_ruid fields in reg_state. */ 688 static int reload_combine_ruid; 689 690 /* The RUID of the last label we encountered in reload_combine. */ 691 static int last_label_ruid; 692 693 /* The RUID of the last jump we encountered in reload_combine. */ 694 static int last_jump_ruid; 695 696 /* The register numbers of the first and last index register. A value of 697 -1 in LAST_INDEX_REG indicates that we've previously computed these 698 values and found no suitable index registers. */ 699 static int first_index_reg = -1; 700 static int last_index_reg; 701 702 #define LABEL_LIVE(LABEL) \ 703 (label_live[CODE_LABEL_NUMBER (LABEL) - min_labelno]) 704 705 /* Subroutine of reload_combine_split_ruids, called to fix up a single 706 ruid pointed to by *PRUID if it is higher than SPLIT_RUID. */ 707 708 static inline void 709 reload_combine_split_one_ruid (int *pruid, int split_ruid) 710 { 711 if (*pruid > split_ruid) 712 (*pruid)++; 713 } 714 715 /* Called when we insert a new insn in a position we've already passed in 716 the scan. Examine all our state, increasing all ruids that are higher 717 than SPLIT_RUID by one in order to make room for a new insn. */ 718 719 static void 720 reload_combine_split_ruids (int split_ruid) 721 { 722 unsigned i; 723 724 reload_combine_split_one_ruid (&reload_combine_ruid, split_ruid); 725 reload_combine_split_one_ruid (&last_label_ruid, split_ruid); 726 reload_combine_split_one_ruid (&last_jump_ruid, split_ruid); 727 728 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 729 { 730 int j, idx = reg_state[i].use_index; 731 reload_combine_split_one_ruid (®_state[i].use_ruid, split_ruid); 732 reload_combine_split_one_ruid (®_state[i].store_ruid, split_ruid); 733 reload_combine_split_one_ruid (®_state[i].real_store_ruid, 734 split_ruid); 735 if (idx < 0) 736 continue; 737 for (j = idx; j < RELOAD_COMBINE_MAX_USES; j++) 738 { 739 reload_combine_split_one_ruid (®_state[i].reg_use[j].ruid, 740 split_ruid); 741 } 742 } 743 } 744 745 /* Called when we are about to rescan a previously encountered insn with 746 reload_combine_note_use after modifying some part of it. This clears all 747 information about uses in that particular insn. */ 748 749 static void 750 reload_combine_purge_insn_uses (rtx_insn *insn) 751 { 752 unsigned i; 753 754 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 755 { 756 int j, k, idx = reg_state[i].use_index; 757 if (idx < 0) 758 continue; 759 j = k = RELOAD_COMBINE_MAX_USES; 760 while (j-- > idx) 761 { 762 if (reg_state[i].reg_use[j].insn != insn) 763 { 764 k--; 765 if (k != j) 766 reg_state[i].reg_use[k] = reg_state[i].reg_use[j]; 767 } 768 } 769 reg_state[i].use_index = k; 770 } 771 } 772 773 /* Called when we need to forget about all uses of REGNO after an insn 774 which is identified by RUID. */ 775 776 static void 777 reload_combine_purge_reg_uses_after_ruid (unsigned regno, int ruid) 778 { 779 int j, k, idx = reg_state[regno].use_index; 780 if (idx < 0) 781 return; 782 j = k = RELOAD_COMBINE_MAX_USES; 783 while (j-- > idx) 784 { 785 if (reg_state[regno].reg_use[j].ruid >= ruid) 786 { 787 k--; 788 if (k != j) 789 reg_state[regno].reg_use[k] = reg_state[regno].reg_use[j]; 790 } 791 } 792 reg_state[regno].use_index = k; 793 } 794 795 /* Find the use of REGNO with the ruid that is highest among those 796 lower than RUID_LIMIT, and return it if it is the only use of this 797 reg in the insn. Return NULL otherwise. */ 798 799 static struct reg_use * 800 reload_combine_closest_single_use (unsigned regno, int ruid_limit) 801 { 802 int i, best_ruid = 0; 803 int use_idx = reg_state[regno].use_index; 804 struct reg_use *retval; 805 806 if (use_idx < 0) 807 return NULL; 808 retval = NULL; 809 for (i = use_idx; i < RELOAD_COMBINE_MAX_USES; i++) 810 { 811 struct reg_use *use = reg_state[regno].reg_use + i; 812 int this_ruid = use->ruid; 813 if (this_ruid >= ruid_limit) 814 continue; 815 if (this_ruid > best_ruid) 816 { 817 best_ruid = this_ruid; 818 retval = use; 819 } 820 else if (this_ruid == best_ruid) 821 retval = NULL; 822 } 823 if (last_label_ruid >= best_ruid) 824 return NULL; 825 return retval; 826 } 827 828 /* After we've moved an add insn, fix up any debug insns that occur 829 between the old location of the add and the new location. REG is 830 the destination register of the add insn; REPLACEMENT is the 831 SET_SRC of the add. FROM and TO specify the range in which we 832 should make this change on debug insns. */ 833 834 static void 835 fixup_debug_insns (rtx reg, rtx replacement, rtx_insn *from, rtx_insn *to) 836 { 837 rtx_insn *insn; 838 for (insn = from; insn != to; insn = NEXT_INSN (insn)) 839 { 840 rtx t; 841 842 if (!DEBUG_INSN_P (insn)) 843 continue; 844 845 t = INSN_VAR_LOCATION_LOC (insn); 846 t = simplify_replace_rtx (t, reg, replacement); 847 validate_change (insn, &INSN_VAR_LOCATION_LOC (insn), t, 0); 848 } 849 } 850 851 /* Subroutine of reload_combine_recognize_const_pattern. Try to replace REG 852 with SRC in the insn described by USE, taking costs into account. Return 853 true if we made the replacement. */ 854 855 static bool 856 try_replace_in_use (struct reg_use *use, rtx reg, rtx src) 857 { 858 rtx_insn *use_insn = use->insn; 859 rtx mem = use->containing_mem; 860 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (use_insn)); 861 862 if (mem != NULL_RTX) 863 { 864 addr_space_t as = MEM_ADDR_SPACE (mem); 865 rtx oldaddr = XEXP (mem, 0); 866 rtx newaddr = NULL_RTX; 867 int old_cost = address_cost (oldaddr, GET_MODE (mem), as, speed); 868 int new_cost; 869 870 newaddr = simplify_replace_rtx (oldaddr, reg, src); 871 if (memory_address_addr_space_p (GET_MODE (mem), newaddr, as)) 872 { 873 XEXP (mem, 0) = newaddr; 874 new_cost = address_cost (newaddr, GET_MODE (mem), as, speed); 875 XEXP (mem, 0) = oldaddr; 876 if (new_cost <= old_cost 877 && validate_change (use_insn, 878 &XEXP (mem, 0), newaddr, 0)) 879 return true; 880 } 881 } 882 else 883 { 884 rtx new_set = single_set (use_insn); 885 if (new_set 886 && REG_P (SET_DEST (new_set)) 887 && GET_CODE (SET_SRC (new_set)) == PLUS 888 && REG_P (XEXP (SET_SRC (new_set), 0)) 889 && CONSTANT_P (XEXP (SET_SRC (new_set), 1))) 890 { 891 rtx new_src; 892 machine_mode mode = GET_MODE (SET_DEST (new_set)); 893 int old_cost = set_src_cost (SET_SRC (new_set), mode, speed); 894 895 gcc_assert (rtx_equal_p (XEXP (SET_SRC (new_set), 0), reg)); 896 new_src = simplify_replace_rtx (SET_SRC (new_set), reg, src); 897 898 if (set_src_cost (new_src, mode, speed) <= old_cost 899 && validate_change (use_insn, &SET_SRC (new_set), 900 new_src, 0)) 901 return true; 902 } 903 } 904 return false; 905 } 906 907 /* Called by reload_combine when scanning INSN. This function tries to detect 908 patterns where a constant is added to a register, and the result is used 909 in an address. 910 Return true if no further processing is needed on INSN; false if it wasn't 911 recognized and should be handled normally. */ 912 913 static bool 914 reload_combine_recognize_const_pattern (rtx_insn *insn) 915 { 916 int from_ruid = reload_combine_ruid; 917 rtx set, pat, reg, src, addreg; 918 unsigned int regno; 919 struct reg_use *use; 920 bool must_move_add; 921 rtx_insn *add_moved_after_insn = NULL; 922 int add_moved_after_ruid = 0; 923 int clobbered_regno = -1; 924 925 set = single_set (insn); 926 if (set == NULL_RTX) 927 return false; 928 929 reg = SET_DEST (set); 930 src = SET_SRC (set); 931 if (!REG_P (reg) 932 || REG_NREGS (reg) != 1 933 || GET_MODE (reg) != Pmode 934 || reg == stack_pointer_rtx) 935 return false; 936 937 regno = REGNO (reg); 938 939 /* We look for a REG1 = REG2 + CONSTANT insn, followed by either 940 uses of REG1 inside an address, or inside another add insn. If 941 possible and profitable, merge the addition into subsequent 942 uses. */ 943 if (GET_CODE (src) != PLUS 944 || !REG_P (XEXP (src, 0)) 945 || !CONSTANT_P (XEXP (src, 1))) 946 return false; 947 948 addreg = XEXP (src, 0); 949 must_move_add = rtx_equal_p (reg, addreg); 950 951 pat = PATTERN (insn); 952 if (must_move_add && set != pat) 953 { 954 /* We have to be careful when moving the add; apart from the 955 single_set there may also be clobbers. Recognize one special 956 case, that of one clobber alongside the set (likely a clobber 957 of the CC register). */ 958 gcc_assert (GET_CODE (PATTERN (insn)) == PARALLEL); 959 if (XVECLEN (pat, 0) != 2 || XVECEXP (pat, 0, 0) != set 960 || GET_CODE (XVECEXP (pat, 0, 1)) != CLOBBER 961 || !REG_P (XEXP (XVECEXP (pat, 0, 1), 0))) 962 return false; 963 clobbered_regno = REGNO (XEXP (XVECEXP (pat, 0, 1), 0)); 964 } 965 966 do 967 { 968 use = reload_combine_closest_single_use (regno, from_ruid); 969 970 if (use) 971 /* Start the search for the next use from here. */ 972 from_ruid = use->ruid; 973 974 if (use && GET_MODE (*use->usep) == Pmode) 975 { 976 bool delete_add = false; 977 rtx_insn *use_insn = use->insn; 978 int use_ruid = use->ruid; 979 980 /* Avoid moving the add insn past a jump. */ 981 if (must_move_add && use_ruid <= last_jump_ruid) 982 break; 983 984 /* If the add clobbers another hard reg in parallel, don't move 985 it past a real set of this hard reg. */ 986 if (must_move_add && clobbered_regno >= 0 987 && reg_state[clobbered_regno].real_store_ruid >= use_ruid) 988 break; 989 990 /* Do not separate cc0 setter and cc0 user on HAVE_cc0 targets. */ 991 if (HAVE_cc0 && must_move_add && sets_cc0_p (PATTERN (use_insn))) 992 break; 993 994 gcc_assert (reg_state[regno].store_ruid <= use_ruid); 995 /* Avoid moving a use of ADDREG past a point where it is stored. */ 996 if (reg_state[REGNO (addreg)].store_ruid > use_ruid) 997 break; 998 999 /* We also must not move the addition past an insn that sets 1000 the same register, unless we can combine two add insns. */ 1001 if (must_move_add && reg_state[regno].store_ruid == use_ruid) 1002 { 1003 if (use->containing_mem == NULL_RTX) 1004 delete_add = true; 1005 else 1006 break; 1007 } 1008 1009 if (try_replace_in_use (use, reg, src)) 1010 { 1011 reload_combine_purge_insn_uses (use_insn); 1012 reload_combine_note_use (&PATTERN (use_insn), use_insn, 1013 use_ruid, NULL_RTX); 1014 1015 if (delete_add) 1016 { 1017 fixup_debug_insns (reg, src, insn, use_insn); 1018 delete_insn (insn); 1019 return true; 1020 } 1021 if (must_move_add) 1022 { 1023 add_moved_after_insn = use_insn; 1024 add_moved_after_ruid = use_ruid; 1025 } 1026 continue; 1027 } 1028 } 1029 /* If we get here, we couldn't handle this use. */ 1030 if (must_move_add) 1031 break; 1032 } 1033 while (use); 1034 1035 if (!must_move_add || add_moved_after_insn == NULL_RTX) 1036 /* Process the add normally. */ 1037 return false; 1038 1039 fixup_debug_insns (reg, src, insn, add_moved_after_insn); 1040 1041 reorder_insns (insn, insn, add_moved_after_insn); 1042 reload_combine_purge_reg_uses_after_ruid (regno, add_moved_after_ruid); 1043 reload_combine_split_ruids (add_moved_after_ruid - 1); 1044 reload_combine_note_use (&PATTERN (insn), insn, 1045 add_moved_after_ruid, NULL_RTX); 1046 reg_state[regno].store_ruid = add_moved_after_ruid; 1047 1048 return true; 1049 } 1050 1051 /* Called by reload_combine when scanning INSN. Try to detect a pattern we 1052 can handle and improve. Return true if no further processing is needed on 1053 INSN; false if it wasn't recognized and should be handled normally. */ 1054 1055 static bool 1056 reload_combine_recognize_pattern (rtx_insn *insn) 1057 { 1058 rtx set, reg, src; 1059 1060 set = single_set (insn); 1061 if (set == NULL_RTX) 1062 return false; 1063 1064 reg = SET_DEST (set); 1065 src = SET_SRC (set); 1066 if (!REG_P (reg) || REG_NREGS (reg) != 1) 1067 return false; 1068 1069 unsigned int regno = REGNO (reg); 1070 machine_mode mode = GET_MODE (reg); 1071 1072 if (reg_state[regno].use_index < 0 1073 || reg_state[regno].use_index >= RELOAD_COMBINE_MAX_USES) 1074 return false; 1075 1076 for (int i = reg_state[regno].use_index; 1077 i < RELOAD_COMBINE_MAX_USES; i++) 1078 { 1079 struct reg_use *use = reg_state[regno].reg_use + i; 1080 if (GET_MODE (*use->usep) != mode) 1081 return false; 1082 } 1083 1084 /* Look for (set (REGX) (CONST_INT)) 1085 (set (REGX) (PLUS (REGX) (REGY))) 1086 ... 1087 ... (MEM (REGX)) ... 1088 and convert it to 1089 (set (REGZ) (CONST_INT)) 1090 ... 1091 ... (MEM (PLUS (REGZ) (REGY)))... . 1092 1093 First, check that we have (set (REGX) (PLUS (REGX) (REGY))) 1094 and that we know all uses of REGX before it dies. 1095 Also, explicitly check that REGX != REGY; our life information 1096 does not yet show whether REGY changes in this insn. */ 1097 1098 if (GET_CODE (src) == PLUS 1099 && reg_state[regno].all_offsets_match 1100 && last_index_reg != -1 1101 && REG_P (XEXP (src, 1)) 1102 && rtx_equal_p (XEXP (src, 0), reg) 1103 && !rtx_equal_p (XEXP (src, 1), reg) 1104 && last_label_ruid < reg_state[regno].use_ruid) 1105 { 1106 rtx base = XEXP (src, 1); 1107 rtx_insn *prev = prev_nonnote_nondebug_insn (insn); 1108 rtx prev_set = prev ? single_set (prev) : NULL_RTX; 1109 rtx index_reg = NULL_RTX; 1110 rtx reg_sum = NULL_RTX; 1111 int i; 1112 1113 /* Now we need to set INDEX_REG to an index register (denoted as 1114 REGZ in the illustration above) and REG_SUM to the expression 1115 register+register that we want to use to substitute uses of REG 1116 (typically in MEMs) with. First check REG and BASE for being 1117 index registers; we can use them even if they are not dead. */ 1118 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], regno) 1119 || TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], 1120 REGNO (base))) 1121 { 1122 index_reg = reg; 1123 reg_sum = src; 1124 } 1125 else 1126 { 1127 /* Otherwise, look for a free index register. Since we have 1128 checked above that neither REG nor BASE are index registers, 1129 if we find anything at all, it will be different from these 1130 two registers. */ 1131 for (i = first_index_reg; i <= last_index_reg; i++) 1132 { 1133 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], i) 1134 && reg_state[i].use_index == RELOAD_COMBINE_MAX_USES 1135 && reg_state[i].store_ruid <= reg_state[regno].use_ruid 1136 && (call_used_regs[i] || df_regs_ever_live_p (i)) 1137 && (!frame_pointer_needed || i != HARD_FRAME_POINTER_REGNUM) 1138 && !fixed_regs[i] && !global_regs[i] 1139 && hard_regno_nregs[i][GET_MODE (reg)] == 1 1140 && targetm.hard_regno_scratch_ok (i)) 1141 { 1142 index_reg = gen_rtx_REG (GET_MODE (reg), i); 1143 reg_sum = gen_rtx_PLUS (GET_MODE (reg), index_reg, base); 1144 break; 1145 } 1146 } 1147 } 1148 1149 /* Check that PREV_SET is indeed (set (REGX) (CONST_INT)) and that 1150 (REGY), i.e. BASE, is not clobbered before the last use we'll 1151 create. */ 1152 if (reg_sum 1153 && prev_set 1154 && CONST_INT_P (SET_SRC (prev_set)) 1155 && rtx_equal_p (SET_DEST (prev_set), reg) 1156 && (reg_state[REGNO (base)].store_ruid 1157 <= reg_state[regno].use_ruid)) 1158 { 1159 /* Change destination register and, if necessary, the constant 1160 value in PREV, the constant loading instruction. */ 1161 validate_change (prev, &SET_DEST (prev_set), index_reg, 1); 1162 if (reg_state[regno].offset != const0_rtx) 1163 { 1164 HOST_WIDE_INT c 1165 = trunc_int_for_mode (UINTVAL (SET_SRC (prev_set)) 1166 + UINTVAL (reg_state[regno].offset), 1167 GET_MODE (index_reg)); 1168 validate_change (prev, &SET_SRC (prev_set), GEN_INT (c), 1); 1169 } 1170 1171 /* Now for every use of REG that we have recorded, replace REG 1172 with REG_SUM. */ 1173 for (i = reg_state[regno].use_index; 1174 i < RELOAD_COMBINE_MAX_USES; i++) 1175 validate_unshare_change (reg_state[regno].reg_use[i].insn, 1176 reg_state[regno].reg_use[i].usep, 1177 /* Each change must have its own 1178 replacement. */ 1179 reg_sum, 1); 1180 1181 if (apply_change_group ()) 1182 { 1183 struct reg_use *lowest_ruid = NULL; 1184 1185 /* For every new use of REG_SUM, we have to record the use 1186 of BASE therein, i.e. operand 1. */ 1187 for (i = reg_state[regno].use_index; 1188 i < RELOAD_COMBINE_MAX_USES; i++) 1189 { 1190 struct reg_use *use = reg_state[regno].reg_use + i; 1191 reload_combine_note_use (&XEXP (*use->usep, 1), use->insn, 1192 use->ruid, use->containing_mem); 1193 if (lowest_ruid == NULL || use->ruid < lowest_ruid->ruid) 1194 lowest_ruid = use; 1195 } 1196 1197 fixup_debug_insns (reg, reg_sum, insn, lowest_ruid->insn); 1198 1199 /* Delete the reg-reg addition. */ 1200 delete_insn (insn); 1201 1202 if (reg_state[regno].offset != const0_rtx 1203 /* Previous REG_EQUIV / REG_EQUAL notes for PREV 1204 are now invalid. */ 1205 && remove_reg_equal_equiv_notes (prev)) 1206 df_notes_rescan (prev); 1207 1208 reg_state[regno].use_index = RELOAD_COMBINE_MAX_USES; 1209 return true; 1210 } 1211 } 1212 } 1213 return false; 1214 } 1215 1216 static void 1217 reload_combine (void) 1218 { 1219 rtx_insn *insn, *prev; 1220 basic_block bb; 1221 unsigned int r; 1222 int min_labelno, n_labels; 1223 HARD_REG_SET ever_live_at_start, *label_live; 1224 1225 /* To avoid wasting too much time later searching for an index register, 1226 determine the minimum and maximum index register numbers. */ 1227 if (INDEX_REG_CLASS == NO_REGS) 1228 last_index_reg = -1; 1229 else if (first_index_reg == -1 && last_index_reg == 0) 1230 { 1231 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 1232 if (TEST_HARD_REG_BIT (reg_class_contents[INDEX_REG_CLASS], r)) 1233 { 1234 if (first_index_reg == -1) 1235 first_index_reg = r; 1236 1237 last_index_reg = r; 1238 } 1239 1240 /* If no index register is available, we can quit now. Set LAST_INDEX_REG 1241 to -1 so we'll know to quit early the next time we get here. */ 1242 if (first_index_reg == -1) 1243 { 1244 last_index_reg = -1; 1245 return; 1246 } 1247 } 1248 1249 /* Set up LABEL_LIVE and EVER_LIVE_AT_START. The register lifetime 1250 information is a bit fuzzy immediately after reload, but it's 1251 still good enough to determine which registers are live at a jump 1252 destination. */ 1253 min_labelno = get_first_label_num (); 1254 n_labels = max_label_num () - min_labelno; 1255 label_live = XNEWVEC (HARD_REG_SET, n_labels); 1256 CLEAR_HARD_REG_SET (ever_live_at_start); 1257 1258 FOR_EACH_BB_REVERSE_FN (bb, cfun) 1259 { 1260 insn = BB_HEAD (bb); 1261 if (LABEL_P (insn)) 1262 { 1263 HARD_REG_SET live; 1264 bitmap live_in = df_get_live_in (bb); 1265 1266 REG_SET_TO_HARD_REG_SET (live, live_in); 1267 compute_use_by_pseudos (&live, live_in); 1268 COPY_HARD_REG_SET (LABEL_LIVE (insn), live); 1269 IOR_HARD_REG_SET (ever_live_at_start, live); 1270 } 1271 } 1272 1273 /* Initialize last_label_ruid, reload_combine_ruid and reg_state. */ 1274 last_label_ruid = last_jump_ruid = reload_combine_ruid = 0; 1275 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 1276 { 1277 reg_state[r].store_ruid = 0; 1278 reg_state[r].real_store_ruid = 0; 1279 if (fixed_regs[r]) 1280 reg_state[r].use_index = -1; 1281 else 1282 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; 1283 } 1284 1285 for (insn = get_last_insn (); insn; insn = prev) 1286 { 1287 bool control_flow_insn; 1288 rtx note; 1289 1290 prev = PREV_INSN (insn); 1291 1292 /* We cannot do our optimization across labels. Invalidating all the use 1293 information we have would be costly, so we just note where the label 1294 is and then later disable any optimization that would cross it. */ 1295 if (LABEL_P (insn)) 1296 last_label_ruid = reload_combine_ruid; 1297 else if (BARRIER_P (insn)) 1298 { 1299 /* Crossing a barrier resets all the use information. */ 1300 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 1301 if (! fixed_regs[r]) 1302 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; 1303 } 1304 else if (INSN_P (insn) && volatile_insn_p (PATTERN (insn))) 1305 /* Optimizations across insns being marked as volatile must be 1306 prevented. All the usage information is invalidated 1307 here. */ 1308 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 1309 if (! fixed_regs[r] 1310 && reg_state[r].use_index != RELOAD_COMBINE_MAX_USES) 1311 reg_state[r].use_index = -1; 1312 1313 if (! NONDEBUG_INSN_P (insn)) 1314 continue; 1315 1316 reload_combine_ruid++; 1317 1318 control_flow_insn = control_flow_insn_p (insn); 1319 if (control_flow_insn) 1320 last_jump_ruid = reload_combine_ruid; 1321 1322 if (reload_combine_recognize_const_pattern (insn) 1323 || reload_combine_recognize_pattern (insn)) 1324 continue; 1325 1326 note_stores (PATTERN (insn), reload_combine_note_store, NULL); 1327 1328 if (CALL_P (insn)) 1329 { 1330 rtx link; 1331 HARD_REG_SET used_regs; 1332 1333 get_call_reg_set_usage (insn, &used_regs, call_used_reg_set); 1334 1335 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 1336 if (TEST_HARD_REG_BIT (used_regs, r)) 1337 { 1338 reg_state[r].use_index = RELOAD_COMBINE_MAX_USES; 1339 reg_state[r].store_ruid = reload_combine_ruid; 1340 } 1341 1342 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; 1343 link = XEXP (link, 1)) 1344 { 1345 rtx setuse = XEXP (link, 0); 1346 rtx usage_rtx = XEXP (setuse, 0); 1347 if ((GET_CODE (setuse) == USE || GET_CODE (setuse) == CLOBBER) 1348 && REG_P (usage_rtx)) 1349 { 1350 unsigned int end_regno = END_REGNO (usage_rtx); 1351 for (unsigned int i = REGNO (usage_rtx); i < end_regno; ++i) 1352 if (GET_CODE (XEXP (link, 0)) == CLOBBER) 1353 { 1354 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; 1355 reg_state[i].store_ruid = reload_combine_ruid; 1356 } 1357 else 1358 reg_state[i].use_index = -1; 1359 } 1360 } 1361 } 1362 1363 if (control_flow_insn && !ANY_RETURN_P (PATTERN (insn))) 1364 { 1365 /* Non-spill registers might be used at the call destination in 1366 some unknown fashion, so we have to mark the unknown use. */ 1367 HARD_REG_SET *live; 1368 1369 if ((condjump_p (insn) || condjump_in_parallel_p (insn)) 1370 && JUMP_LABEL (insn)) 1371 { 1372 if (ANY_RETURN_P (JUMP_LABEL (insn))) 1373 live = NULL; 1374 else 1375 live = &LABEL_LIVE (JUMP_LABEL (insn)); 1376 } 1377 else 1378 live = &ever_live_at_start; 1379 1380 if (live) 1381 for (r = 0; r < FIRST_PSEUDO_REGISTER; r++) 1382 if (TEST_HARD_REG_BIT (*live, r)) 1383 reg_state[r].use_index = -1; 1384 } 1385 1386 reload_combine_note_use (&PATTERN (insn), insn, reload_combine_ruid, 1387 NULL_RTX); 1388 1389 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 1390 { 1391 if (REG_NOTE_KIND (note) == REG_INC && REG_P (XEXP (note, 0))) 1392 { 1393 int regno = REGNO (XEXP (note, 0)); 1394 reg_state[regno].store_ruid = reload_combine_ruid; 1395 reg_state[regno].real_store_ruid = reload_combine_ruid; 1396 reg_state[regno].use_index = -1; 1397 } 1398 } 1399 } 1400 1401 free (label_live); 1402 } 1403 1404 /* Check if DST is a register or a subreg of a register; if it is, 1405 update store_ruid, real_store_ruid and use_index in the reg_state 1406 structure accordingly. Called via note_stores from reload_combine. */ 1407 1408 static void 1409 reload_combine_note_store (rtx dst, const_rtx set, void *data ATTRIBUTE_UNUSED) 1410 { 1411 int regno = 0; 1412 int i; 1413 machine_mode mode = GET_MODE (dst); 1414 1415 if (GET_CODE (dst) == SUBREG) 1416 { 1417 regno = subreg_regno_offset (REGNO (SUBREG_REG (dst)), 1418 GET_MODE (SUBREG_REG (dst)), 1419 SUBREG_BYTE (dst), 1420 GET_MODE (dst)); 1421 dst = SUBREG_REG (dst); 1422 } 1423 1424 /* Some targets do argument pushes without adding REG_INC notes. */ 1425 1426 if (MEM_P (dst)) 1427 { 1428 dst = XEXP (dst, 0); 1429 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC 1430 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC 1431 || GET_CODE (dst) == PRE_MODIFY || GET_CODE (dst) == POST_MODIFY) 1432 { 1433 unsigned int end_regno = END_REGNO (XEXP (dst, 0)); 1434 for (unsigned int i = REGNO (XEXP (dst, 0)); i < end_regno; ++i) 1435 { 1436 /* We could probably do better, but for now mark the register 1437 as used in an unknown fashion and set/clobbered at this 1438 insn. */ 1439 reg_state[i].use_index = -1; 1440 reg_state[i].store_ruid = reload_combine_ruid; 1441 reg_state[i].real_store_ruid = reload_combine_ruid; 1442 } 1443 } 1444 else 1445 return; 1446 } 1447 1448 if (!REG_P (dst)) 1449 return; 1450 regno += REGNO (dst); 1451 1452 /* note_stores might have stripped a STRICT_LOW_PART, so we have to be 1453 careful with registers / register parts that are not full words. 1454 Similarly for ZERO_EXTRACT. */ 1455 if (GET_CODE (SET_DEST (set)) == ZERO_EXTRACT 1456 || GET_CODE (SET_DEST (set)) == STRICT_LOW_PART) 1457 { 1458 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) 1459 { 1460 reg_state[i].use_index = -1; 1461 reg_state[i].store_ruid = reload_combine_ruid; 1462 reg_state[i].real_store_ruid = reload_combine_ruid; 1463 } 1464 } 1465 else 1466 { 1467 for (i = hard_regno_nregs[regno][mode] - 1 + regno; i >= regno; i--) 1468 { 1469 reg_state[i].store_ruid = reload_combine_ruid; 1470 if (GET_CODE (set) == SET) 1471 reg_state[i].real_store_ruid = reload_combine_ruid; 1472 reg_state[i].use_index = RELOAD_COMBINE_MAX_USES; 1473 } 1474 } 1475 } 1476 1477 /* XP points to a piece of rtl that has to be checked for any uses of 1478 registers. 1479 *XP is the pattern of INSN, or a part of it. 1480 Called from reload_combine, and recursively by itself. */ 1481 static void 1482 reload_combine_note_use (rtx *xp, rtx_insn *insn, int ruid, rtx containing_mem) 1483 { 1484 rtx x = *xp; 1485 enum rtx_code code = x->code; 1486 const char *fmt; 1487 int i, j; 1488 rtx offset = const0_rtx; /* For the REG case below. */ 1489 1490 switch (code) 1491 { 1492 case SET: 1493 if (REG_P (SET_DEST (x))) 1494 { 1495 reload_combine_note_use (&SET_SRC (x), insn, ruid, NULL_RTX); 1496 return; 1497 } 1498 break; 1499 1500 case USE: 1501 /* If this is the USE of a return value, we can't change it. */ 1502 if (REG_P (XEXP (x, 0)) && REG_FUNCTION_VALUE_P (XEXP (x, 0))) 1503 { 1504 /* Mark the return register as used in an unknown fashion. */ 1505 rtx reg = XEXP (x, 0); 1506 unsigned int end_regno = END_REGNO (reg); 1507 for (unsigned int regno = REGNO (reg); regno < end_regno; ++regno) 1508 reg_state[regno].use_index = -1; 1509 return; 1510 } 1511 break; 1512 1513 case CLOBBER: 1514 if (REG_P (SET_DEST (x))) 1515 { 1516 /* No spurious CLOBBERs of pseudo registers may remain. */ 1517 gcc_assert (REGNO (SET_DEST (x)) < FIRST_PSEUDO_REGISTER); 1518 return; 1519 } 1520 break; 1521 1522 case PLUS: 1523 /* We are interested in (plus (reg) (const_int)) . */ 1524 if (!REG_P (XEXP (x, 0)) 1525 || !CONST_INT_P (XEXP (x, 1))) 1526 break; 1527 offset = XEXP (x, 1); 1528 x = XEXP (x, 0); 1529 /* Fall through. */ 1530 case REG: 1531 { 1532 int regno = REGNO (x); 1533 int use_index; 1534 int nregs; 1535 1536 /* No spurious USEs of pseudo registers may remain. */ 1537 gcc_assert (regno < FIRST_PSEUDO_REGISTER); 1538 1539 nregs = REG_NREGS (x); 1540 1541 /* We can't substitute into multi-hard-reg uses. */ 1542 if (nregs > 1) 1543 { 1544 while (--nregs >= 0) 1545 reg_state[regno + nregs].use_index = -1; 1546 return; 1547 } 1548 1549 /* We may be called to update uses in previously seen insns. 1550 Don't add uses beyond the last store we saw. */ 1551 if (ruid < reg_state[regno].store_ruid) 1552 return; 1553 1554 /* If this register is already used in some unknown fashion, we 1555 can't do anything. 1556 If we decrement the index from zero to -1, we can't store more 1557 uses, so this register becomes used in an unknown fashion. */ 1558 use_index = --reg_state[regno].use_index; 1559 if (use_index < 0) 1560 return; 1561 1562 if (use_index == RELOAD_COMBINE_MAX_USES - 1) 1563 { 1564 /* This is the first use of this register we have seen since we 1565 marked it as dead. */ 1566 reg_state[regno].offset = offset; 1567 reg_state[regno].all_offsets_match = true; 1568 reg_state[regno].use_ruid = ruid; 1569 } 1570 else 1571 { 1572 if (reg_state[regno].use_ruid > ruid) 1573 reg_state[regno].use_ruid = ruid; 1574 1575 if (! rtx_equal_p (offset, reg_state[regno].offset)) 1576 reg_state[regno].all_offsets_match = false; 1577 } 1578 1579 reg_state[regno].reg_use[use_index].insn = insn; 1580 reg_state[regno].reg_use[use_index].ruid = ruid; 1581 reg_state[regno].reg_use[use_index].containing_mem = containing_mem; 1582 reg_state[regno].reg_use[use_index].usep = xp; 1583 return; 1584 } 1585 1586 case MEM: 1587 containing_mem = x; 1588 break; 1589 1590 default: 1591 break; 1592 } 1593 1594 /* Recursively process the components of X. */ 1595 fmt = GET_RTX_FORMAT (code); 1596 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1597 { 1598 if (fmt[i] == 'e') 1599 reload_combine_note_use (&XEXP (x, i), insn, ruid, containing_mem); 1600 else if (fmt[i] == 'E') 1601 { 1602 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1603 reload_combine_note_use (&XVECEXP (x, i, j), insn, ruid, 1604 containing_mem); 1605 } 1606 } 1607 } 1608 1609 /* See if we can reduce the cost of a constant by replacing a move 1610 with an add. We track situations in which a register is set to a 1611 constant or to a register plus a constant. */ 1612 /* We cannot do our optimization across labels. Invalidating all the 1613 information about register contents we have would be costly, so we 1614 use move2add_last_label_luid to note where the label is and then 1615 later disable any optimization that would cross it. 1616 reg_offset[n] / reg_base_reg[n] / reg_symbol_ref[n] / reg_mode[n] 1617 are only valid if reg_set_luid[n] is greater than 1618 move2add_last_label_luid. 1619 For a set that established a new (potential) base register with 1620 non-constant value, we use move2add_luid from the place where the 1621 setting insn is encountered; registers based off that base then 1622 get the same reg_set_luid. Constants all get 1623 move2add_last_label_luid + 1 as their reg_set_luid. */ 1624 static int reg_set_luid[FIRST_PSEUDO_REGISTER]; 1625 1626 /* If reg_base_reg[n] is negative, register n has been set to 1627 reg_offset[n] or reg_symbol_ref[n] + reg_offset[n] in mode reg_mode[n]. 1628 If reg_base_reg[n] is non-negative, register n has been set to the 1629 sum of reg_offset[n] and the value of register reg_base_reg[n] 1630 before reg_set_luid[n], calculated in mode reg_mode[n] . 1631 For multi-hard-register registers, all but the first one are 1632 recorded as BLKmode in reg_mode. Setting reg_mode to VOIDmode 1633 marks it as invalid. */ 1634 static HOST_WIDE_INT reg_offset[FIRST_PSEUDO_REGISTER]; 1635 static int reg_base_reg[FIRST_PSEUDO_REGISTER]; 1636 static rtx reg_symbol_ref[FIRST_PSEUDO_REGISTER]; 1637 static machine_mode reg_mode[FIRST_PSEUDO_REGISTER]; 1638 1639 /* move2add_luid is linearly increased while scanning the instructions 1640 from first to last. It is used to set reg_set_luid in 1641 reload_cse_move2add and move2add_note_store. */ 1642 static int move2add_luid; 1643 1644 /* move2add_last_label_luid is set whenever a label is found. Labels 1645 invalidate all previously collected reg_offset data. */ 1646 static int move2add_last_label_luid; 1647 1648 /* ??? We don't know how zero / sign extension is handled, hence we 1649 can't go from a narrower to a wider mode. */ 1650 #define MODES_OK_FOR_MOVE2ADD(OUTMODE, INMODE) \ 1651 (GET_MODE_SIZE (OUTMODE) == GET_MODE_SIZE (INMODE) \ 1652 || (GET_MODE_SIZE (OUTMODE) <= GET_MODE_SIZE (INMODE) \ 1653 && TRULY_NOOP_TRUNCATION_MODES_P (OUTMODE, INMODE))) 1654 1655 /* Record that REG is being set to a value with the mode of REG. */ 1656 1657 static void 1658 move2add_record_mode (rtx reg) 1659 { 1660 int regno, nregs; 1661 machine_mode mode = GET_MODE (reg); 1662 1663 if (GET_CODE (reg) == SUBREG) 1664 { 1665 regno = subreg_regno (reg); 1666 nregs = subreg_nregs (reg); 1667 } 1668 else if (REG_P (reg)) 1669 { 1670 regno = REGNO (reg); 1671 nregs = REG_NREGS (reg); 1672 } 1673 else 1674 gcc_unreachable (); 1675 for (int i = nregs - 1; i > 0; i--) 1676 reg_mode[regno + i] = BLKmode; 1677 reg_mode[regno] = mode; 1678 } 1679 1680 /* Record that REG is being set to the sum of SYM and OFF. */ 1681 1682 static void 1683 move2add_record_sym_value (rtx reg, rtx sym, rtx off) 1684 { 1685 int regno = REGNO (reg); 1686 1687 move2add_record_mode (reg); 1688 reg_set_luid[regno] = move2add_luid; 1689 reg_base_reg[regno] = -1; 1690 reg_symbol_ref[regno] = sym; 1691 reg_offset[regno] = INTVAL (off); 1692 } 1693 1694 /* Check if REGNO contains a valid value in MODE. */ 1695 1696 static bool 1697 move2add_valid_value_p (int regno, machine_mode mode) 1698 { 1699 if (reg_set_luid[regno] <= move2add_last_label_luid) 1700 return false; 1701 1702 if (mode != reg_mode[regno]) 1703 { 1704 if (!MODES_OK_FOR_MOVE2ADD (mode, reg_mode[regno])) 1705 return false; 1706 /* The value loaded into regno in reg_mode[regno] is also valid in 1707 mode after truncation only if (REG:mode regno) is the lowpart of 1708 (REG:reg_mode[regno] regno). Now, for big endian, the starting 1709 regno of the lowpart might be different. */ 1710 int s_off = subreg_lowpart_offset (mode, reg_mode[regno]); 1711 s_off = subreg_regno_offset (regno, reg_mode[regno], s_off, mode); 1712 if (s_off != 0) 1713 /* We could in principle adjust regno, check reg_mode[regno] to be 1714 BLKmode, and return s_off to the caller (vs. -1 for failure), 1715 but we currently have no callers that could make use of this 1716 information. */ 1717 return false; 1718 } 1719 1720 for (int i = hard_regno_nregs[regno][mode] - 1; i > 0; i--) 1721 if (reg_mode[regno + i] != BLKmode) 1722 return false; 1723 return true; 1724 } 1725 1726 /* This function is called with INSN that sets REG to (SYM + OFF), 1727 while REG is known to already have value (SYM + offset). 1728 This function tries to change INSN into an add instruction 1729 (set (REG) (plus (REG) (OFF - offset))) using the known value. 1730 It also updates the information about REG's known value. 1731 Return true if we made a change. */ 1732 1733 static bool 1734 move2add_use_add2_insn (rtx reg, rtx sym, rtx off, rtx_insn *insn) 1735 { 1736 rtx pat = PATTERN (insn); 1737 rtx src = SET_SRC (pat); 1738 int regno = REGNO (reg); 1739 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[regno], 1740 GET_MODE (reg)); 1741 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); 1742 bool changed = false; 1743 1744 /* (set (reg) (plus (reg) (const_int 0))) is not canonical; 1745 use (set (reg) (reg)) instead. 1746 We don't delete this insn, nor do we convert it into a 1747 note, to avoid losing register notes or the return 1748 value flag. jump2 already knows how to get rid of 1749 no-op moves. */ 1750 if (new_src == const0_rtx) 1751 { 1752 /* If the constants are different, this is a 1753 truncation, that, if turned into (set (reg) 1754 (reg)), would be discarded. Maybe we should 1755 try a truncMN pattern? */ 1756 if (INTVAL (off) == reg_offset [regno]) 1757 changed = validate_change (insn, &SET_SRC (pat), reg, 0); 1758 } 1759 else 1760 { 1761 struct full_rtx_costs oldcst, newcst; 1762 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); 1763 1764 get_full_set_rtx_cost (pat, &oldcst); 1765 SET_SRC (pat) = tem; 1766 get_full_set_rtx_cost (pat, &newcst); 1767 SET_SRC (pat) = src; 1768 1769 if (costs_lt_p (&newcst, &oldcst, speed) 1770 && have_add2_insn (reg, new_src)) 1771 changed = validate_change (insn, &SET_SRC (pat), tem, 0); 1772 else if (sym == NULL_RTX && GET_MODE (reg) != BImode) 1773 { 1774 machine_mode narrow_mode; 1775 for (narrow_mode = GET_CLASS_NARROWEST_MODE (MODE_INT); 1776 narrow_mode != VOIDmode 1777 && narrow_mode != GET_MODE (reg); 1778 narrow_mode = GET_MODE_WIDER_MODE (narrow_mode)) 1779 { 1780 if (have_insn_for (STRICT_LOW_PART, narrow_mode) 1781 && ((reg_offset[regno] & ~GET_MODE_MASK (narrow_mode)) 1782 == (INTVAL (off) & ~GET_MODE_MASK (narrow_mode)))) 1783 { 1784 rtx narrow_reg = gen_lowpart_common (narrow_mode, reg); 1785 rtx narrow_src = gen_int_mode (INTVAL (off), 1786 narrow_mode); 1787 rtx new_set 1788 = gen_rtx_SET (gen_rtx_STRICT_LOW_PART (VOIDmode, 1789 narrow_reg), 1790 narrow_src); 1791 get_full_set_rtx_cost (new_set, &newcst); 1792 if (costs_lt_p (&newcst, &oldcst, speed)) 1793 { 1794 changed = validate_change (insn, &PATTERN (insn), 1795 new_set, 0); 1796 if (changed) 1797 break; 1798 } 1799 } 1800 } 1801 } 1802 } 1803 move2add_record_sym_value (reg, sym, off); 1804 return changed; 1805 } 1806 1807 1808 /* This function is called with INSN that sets REG to (SYM + OFF), 1809 but REG doesn't have known value (SYM + offset). This function 1810 tries to find another register which is known to already have 1811 value (SYM + offset) and change INSN into an add instruction 1812 (set (REG) (plus (the found register) (OFF - offset))) if such 1813 a register is found. It also updates the information about 1814 REG's known value. 1815 Return true iff we made a change. */ 1816 1817 static bool 1818 move2add_use_add3_insn (rtx reg, rtx sym, rtx off, rtx_insn *insn) 1819 { 1820 rtx pat = PATTERN (insn); 1821 rtx src = SET_SRC (pat); 1822 int regno = REGNO (reg); 1823 int min_regno = 0; 1824 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); 1825 int i; 1826 bool changed = false; 1827 struct full_rtx_costs oldcst, newcst, mincst; 1828 rtx plus_expr; 1829 1830 init_costs_to_max (&mincst); 1831 get_full_set_rtx_cost (pat, &oldcst); 1832 1833 plus_expr = gen_rtx_PLUS (GET_MODE (reg), reg, const0_rtx); 1834 SET_SRC (pat) = plus_expr; 1835 1836 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1837 if (move2add_valid_value_p (i, GET_MODE (reg)) 1838 && reg_base_reg[i] < 0 1839 && reg_symbol_ref[i] != NULL_RTX 1840 && rtx_equal_p (sym, reg_symbol_ref[i])) 1841 { 1842 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[i], 1843 GET_MODE (reg)); 1844 /* (set (reg) (plus (reg) (const_int 0))) is not canonical; 1845 use (set (reg) (reg)) instead. 1846 We don't delete this insn, nor do we convert it into a 1847 note, to avoid losing register notes or the return 1848 value flag. jump2 already knows how to get rid of 1849 no-op moves. */ 1850 if (new_src == const0_rtx) 1851 { 1852 init_costs_to_zero (&mincst); 1853 min_regno = i; 1854 break; 1855 } 1856 else 1857 { 1858 XEXP (plus_expr, 1) = new_src; 1859 get_full_set_rtx_cost (pat, &newcst); 1860 1861 if (costs_lt_p (&newcst, &mincst, speed)) 1862 { 1863 mincst = newcst; 1864 min_regno = i; 1865 } 1866 } 1867 } 1868 SET_SRC (pat) = src; 1869 1870 if (costs_lt_p (&mincst, &oldcst, speed)) 1871 { 1872 rtx tem; 1873 1874 tem = gen_rtx_REG (GET_MODE (reg), min_regno); 1875 if (i != min_regno) 1876 { 1877 rtx new_src = gen_int_mode (UINTVAL (off) - reg_offset[min_regno], 1878 GET_MODE (reg)); 1879 tem = gen_rtx_PLUS (GET_MODE (reg), tem, new_src); 1880 } 1881 if (validate_change (insn, &SET_SRC (pat), tem, 0)) 1882 changed = true; 1883 } 1884 reg_set_luid[regno] = move2add_luid; 1885 move2add_record_sym_value (reg, sym, off); 1886 return changed; 1887 } 1888 1889 /* Convert move insns with constant inputs to additions if they are cheaper. 1890 Return true if any changes were made. */ 1891 static bool 1892 reload_cse_move2add (rtx_insn *first) 1893 { 1894 int i; 1895 rtx_insn *insn; 1896 bool changed = false; 1897 1898 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) 1899 { 1900 reg_set_luid[i] = 0; 1901 reg_offset[i] = 0; 1902 reg_base_reg[i] = 0; 1903 reg_symbol_ref[i] = NULL_RTX; 1904 reg_mode[i] = VOIDmode; 1905 } 1906 1907 move2add_last_label_luid = 0; 1908 move2add_luid = 2; 1909 for (insn = first; insn; insn = NEXT_INSN (insn), move2add_luid++) 1910 { 1911 rtx pat, note; 1912 1913 if (LABEL_P (insn)) 1914 { 1915 move2add_last_label_luid = move2add_luid; 1916 /* We're going to increment move2add_luid twice after a 1917 label, so that we can use move2add_last_label_luid + 1 as 1918 the luid for constants. */ 1919 move2add_luid++; 1920 continue; 1921 } 1922 if (! INSN_P (insn)) 1923 continue; 1924 pat = PATTERN (insn); 1925 /* For simplicity, we only perform this optimization on 1926 straightforward SETs. */ 1927 if (GET_CODE (pat) == SET 1928 && REG_P (SET_DEST (pat))) 1929 { 1930 rtx reg = SET_DEST (pat); 1931 int regno = REGNO (reg); 1932 rtx src = SET_SRC (pat); 1933 1934 /* Check if we have valid information on the contents of this 1935 register in the mode of REG. */ 1936 if (move2add_valid_value_p (regno, GET_MODE (reg)) 1937 && dbg_cnt (cse2_move2add)) 1938 { 1939 /* Try to transform (set (REGX) (CONST_INT A)) 1940 ... 1941 (set (REGX) (CONST_INT B)) 1942 to 1943 (set (REGX) (CONST_INT A)) 1944 ... 1945 (set (REGX) (plus (REGX) (CONST_INT B-A))) 1946 or 1947 (set (REGX) (CONST_INT A)) 1948 ... 1949 (set (STRICT_LOW_PART (REGX)) (CONST_INT B)) 1950 */ 1951 1952 if (CONST_INT_P (src) 1953 && reg_base_reg[regno] < 0 1954 && reg_symbol_ref[regno] == NULL_RTX) 1955 { 1956 changed |= move2add_use_add2_insn (reg, NULL_RTX, src, insn); 1957 continue; 1958 } 1959 1960 /* Try to transform (set (REGX) (REGY)) 1961 (set (REGX) (PLUS (REGX) (CONST_INT A))) 1962 ... 1963 (set (REGX) (REGY)) 1964 (set (REGX) (PLUS (REGX) (CONST_INT B))) 1965 to 1966 (set (REGX) (REGY)) 1967 (set (REGX) (PLUS (REGX) (CONST_INT A))) 1968 ... 1969 (set (REGX) (plus (REGX) (CONST_INT B-A))) */ 1970 else if (REG_P (src) 1971 && reg_set_luid[regno] == reg_set_luid[REGNO (src)] 1972 && reg_base_reg[regno] == reg_base_reg[REGNO (src)] 1973 && move2add_valid_value_p (REGNO (src), GET_MODE (reg))) 1974 { 1975 rtx_insn *next = next_nonnote_nondebug_insn (insn); 1976 rtx set = NULL_RTX; 1977 if (next) 1978 set = single_set (next); 1979 if (set 1980 && SET_DEST (set) == reg 1981 && GET_CODE (SET_SRC (set)) == PLUS 1982 && XEXP (SET_SRC (set), 0) == reg 1983 && CONST_INT_P (XEXP (SET_SRC (set), 1))) 1984 { 1985 rtx src3 = XEXP (SET_SRC (set), 1); 1986 unsigned HOST_WIDE_INT added_offset = UINTVAL (src3); 1987 HOST_WIDE_INT base_offset = reg_offset[REGNO (src)]; 1988 HOST_WIDE_INT regno_offset = reg_offset[regno]; 1989 rtx new_src = 1990 gen_int_mode (added_offset 1991 + base_offset 1992 - regno_offset, 1993 GET_MODE (reg)); 1994 bool success = false; 1995 bool speed = optimize_bb_for_speed_p (BLOCK_FOR_INSN (insn)); 1996 1997 if (new_src == const0_rtx) 1998 /* See above why we create (set (reg) (reg)) here. */ 1999 success 2000 = validate_change (next, &SET_SRC (set), reg, 0); 2001 else 2002 { 2003 rtx old_src = SET_SRC (set); 2004 struct full_rtx_costs oldcst, newcst; 2005 rtx tem = gen_rtx_PLUS (GET_MODE (reg), reg, new_src); 2006 2007 get_full_set_rtx_cost (set, &oldcst); 2008 SET_SRC (set) = tem; 2009 get_full_set_src_cost (tem, GET_MODE (reg), &newcst); 2010 SET_SRC (set) = old_src; 2011 costs_add_n_insns (&oldcst, 1); 2012 2013 if (costs_lt_p (&newcst, &oldcst, speed) 2014 && have_add2_insn (reg, new_src)) 2015 { 2016 rtx newpat = gen_rtx_SET (reg, tem); 2017 success 2018 = validate_change (next, &PATTERN (next), 2019 newpat, 0); 2020 } 2021 } 2022 if (success) 2023 delete_insn (insn); 2024 changed |= success; 2025 insn = next; 2026 move2add_record_mode (reg); 2027 reg_offset[regno] 2028 = trunc_int_for_mode (added_offset + base_offset, 2029 GET_MODE (reg)); 2030 continue; 2031 } 2032 } 2033 } 2034 2035 /* Try to transform 2036 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) 2037 ... 2038 (set (REGY) (CONST (PLUS (SYMBOL_REF) (CONST_INT B)))) 2039 to 2040 (set (REGX) (CONST (PLUS (SYMBOL_REF) (CONST_INT A)))) 2041 ... 2042 (set (REGY) (CONST (PLUS (REGX) (CONST_INT B-A)))) */ 2043 if ((GET_CODE (src) == SYMBOL_REF 2044 || (GET_CODE (src) == CONST 2045 && GET_CODE (XEXP (src, 0)) == PLUS 2046 && GET_CODE (XEXP (XEXP (src, 0), 0)) == SYMBOL_REF 2047 && CONST_INT_P (XEXP (XEXP (src, 0), 1)))) 2048 && dbg_cnt (cse2_move2add)) 2049 { 2050 rtx sym, off; 2051 2052 if (GET_CODE (src) == SYMBOL_REF) 2053 { 2054 sym = src; 2055 off = const0_rtx; 2056 } 2057 else 2058 { 2059 sym = XEXP (XEXP (src, 0), 0); 2060 off = XEXP (XEXP (src, 0), 1); 2061 } 2062 2063 /* If the reg already contains the value which is sum of 2064 sym and some constant value, we can use an add2 insn. */ 2065 if (move2add_valid_value_p (regno, GET_MODE (reg)) 2066 && reg_base_reg[regno] < 0 2067 && reg_symbol_ref[regno] != NULL_RTX 2068 && rtx_equal_p (sym, reg_symbol_ref[regno])) 2069 changed |= move2add_use_add2_insn (reg, sym, off, insn); 2070 2071 /* Otherwise, we have to find a register whose value is sum 2072 of sym and some constant value. */ 2073 else 2074 changed |= move2add_use_add3_insn (reg, sym, off, insn); 2075 2076 continue; 2077 } 2078 } 2079 2080 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 2081 { 2082 if (REG_NOTE_KIND (note) == REG_INC 2083 && REG_P (XEXP (note, 0))) 2084 { 2085 /* Reset the information about this register. */ 2086 int regno = REGNO (XEXP (note, 0)); 2087 if (regno < FIRST_PSEUDO_REGISTER) 2088 { 2089 move2add_record_mode (XEXP (note, 0)); 2090 reg_mode[regno] = VOIDmode; 2091 } 2092 } 2093 } 2094 note_stores (PATTERN (insn), move2add_note_store, insn); 2095 2096 /* If INSN is a conditional branch, we try to extract an 2097 implicit set out of it. */ 2098 if (any_condjump_p (insn)) 2099 { 2100 rtx cnd = fis_get_condition (insn); 2101 2102 if (cnd != NULL_RTX 2103 && GET_CODE (cnd) == NE 2104 && REG_P (XEXP (cnd, 0)) 2105 && !reg_set_p (XEXP (cnd, 0), insn) 2106 /* The following two checks, which are also in 2107 move2add_note_store, are intended to reduce the 2108 number of calls to gen_rtx_SET to avoid memory 2109 allocation if possible. */ 2110 && SCALAR_INT_MODE_P (GET_MODE (XEXP (cnd, 0))) 2111 && REG_NREGS (XEXP (cnd, 0)) == 1 2112 && CONST_INT_P (XEXP (cnd, 1))) 2113 { 2114 rtx implicit_set = 2115 gen_rtx_SET (XEXP (cnd, 0), XEXP (cnd, 1)); 2116 move2add_note_store (SET_DEST (implicit_set), implicit_set, insn); 2117 } 2118 } 2119 2120 /* If this is a CALL_INSN, all call used registers are stored with 2121 unknown values. */ 2122 if (CALL_P (insn)) 2123 { 2124 rtx link; 2125 2126 for (i = FIRST_PSEUDO_REGISTER - 1; i >= 0; i--) 2127 { 2128 if (call_used_regs[i]) 2129 /* Reset the information about this register. */ 2130 reg_mode[i] = VOIDmode; 2131 } 2132 2133 for (link = CALL_INSN_FUNCTION_USAGE (insn); link; 2134 link = XEXP (link, 1)) 2135 { 2136 rtx setuse = XEXP (link, 0); 2137 rtx usage_rtx = XEXP (setuse, 0); 2138 if (GET_CODE (setuse) == CLOBBER 2139 && REG_P (usage_rtx)) 2140 { 2141 unsigned int end_regno = END_REGNO (usage_rtx); 2142 for (unsigned int r = REGNO (usage_rtx); r < end_regno; ++r) 2143 /* Reset the information about this register. */ 2144 reg_mode[r] = VOIDmode; 2145 } 2146 } 2147 } 2148 } 2149 return changed; 2150 } 2151 2152 /* SET is a SET or CLOBBER that sets DST. DATA is the insn which 2153 contains SET. 2154 Update reg_set_luid, reg_offset and reg_base_reg accordingly. 2155 Called from reload_cse_move2add via note_stores. */ 2156 2157 static void 2158 move2add_note_store (rtx dst, const_rtx set, void *data) 2159 { 2160 rtx_insn *insn = (rtx_insn *) data; 2161 unsigned int regno = 0; 2162 machine_mode mode = GET_MODE (dst); 2163 2164 /* Some targets do argument pushes without adding REG_INC notes. */ 2165 2166 if (MEM_P (dst)) 2167 { 2168 dst = XEXP (dst, 0); 2169 if (GET_CODE (dst) == PRE_INC || GET_CODE (dst) == POST_INC 2170 || GET_CODE (dst) == PRE_DEC || GET_CODE (dst) == POST_DEC) 2171 reg_mode[REGNO (XEXP (dst, 0))] = VOIDmode; 2172 return; 2173 } 2174 2175 if (GET_CODE (dst) == SUBREG) 2176 regno = subreg_regno (dst); 2177 else if (REG_P (dst)) 2178 regno = REGNO (dst); 2179 else 2180 return; 2181 2182 if (SCALAR_INT_MODE_P (mode) 2183 && GET_CODE (set) == SET) 2184 { 2185 rtx note, sym = NULL_RTX; 2186 rtx off; 2187 2188 note = find_reg_equal_equiv_note (insn); 2189 if (note && GET_CODE (XEXP (note, 0)) == SYMBOL_REF) 2190 { 2191 sym = XEXP (note, 0); 2192 off = const0_rtx; 2193 } 2194 else if (note && GET_CODE (XEXP (note, 0)) == CONST 2195 && GET_CODE (XEXP (XEXP (note, 0), 0)) == PLUS 2196 && GET_CODE (XEXP (XEXP (XEXP (note, 0), 0), 0)) == SYMBOL_REF 2197 && CONST_INT_P (XEXP (XEXP (XEXP (note, 0), 0), 1))) 2198 { 2199 sym = XEXP (XEXP (XEXP (note, 0), 0), 0); 2200 off = XEXP (XEXP (XEXP (note, 0), 0), 1); 2201 } 2202 2203 if (sym != NULL_RTX) 2204 { 2205 move2add_record_sym_value (dst, sym, off); 2206 return; 2207 } 2208 } 2209 2210 if (SCALAR_INT_MODE_P (mode) 2211 && GET_CODE (set) == SET 2212 && GET_CODE (SET_DEST (set)) != ZERO_EXTRACT 2213 && GET_CODE (SET_DEST (set)) != STRICT_LOW_PART) 2214 { 2215 rtx src = SET_SRC (set); 2216 rtx base_reg; 2217 unsigned HOST_WIDE_INT offset; 2218 int base_regno; 2219 2220 switch (GET_CODE (src)) 2221 { 2222 case PLUS: 2223 if (REG_P (XEXP (src, 0))) 2224 { 2225 base_reg = XEXP (src, 0); 2226 2227 if (CONST_INT_P (XEXP (src, 1))) 2228 offset = UINTVAL (XEXP (src, 1)); 2229 else if (REG_P (XEXP (src, 1)) 2230 && move2add_valid_value_p (REGNO (XEXP (src, 1)), mode)) 2231 { 2232 if (reg_base_reg[REGNO (XEXP (src, 1))] < 0 2233 && reg_symbol_ref[REGNO (XEXP (src, 1))] == NULL_RTX) 2234 offset = reg_offset[REGNO (XEXP (src, 1))]; 2235 /* Maybe the first register is known to be a 2236 constant. */ 2237 else if (move2add_valid_value_p (REGNO (base_reg), mode) 2238 && reg_base_reg[REGNO (base_reg)] < 0 2239 && reg_symbol_ref[REGNO (base_reg)] == NULL_RTX) 2240 { 2241 offset = reg_offset[REGNO (base_reg)]; 2242 base_reg = XEXP (src, 1); 2243 } 2244 else 2245 goto invalidate; 2246 } 2247 else 2248 goto invalidate; 2249 2250 break; 2251 } 2252 2253 goto invalidate; 2254 2255 case REG: 2256 base_reg = src; 2257 offset = 0; 2258 break; 2259 2260 case CONST_INT: 2261 /* Start tracking the register as a constant. */ 2262 reg_base_reg[regno] = -1; 2263 reg_symbol_ref[regno] = NULL_RTX; 2264 reg_offset[regno] = INTVAL (SET_SRC (set)); 2265 /* We assign the same luid to all registers set to constants. */ 2266 reg_set_luid[regno] = move2add_last_label_luid + 1; 2267 move2add_record_mode (dst); 2268 return; 2269 2270 default: 2271 goto invalidate; 2272 } 2273 2274 base_regno = REGNO (base_reg); 2275 /* If information about the base register is not valid, set it 2276 up as a new base register, pretending its value is known 2277 starting from the current insn. */ 2278 if (!move2add_valid_value_p (base_regno, mode)) 2279 { 2280 reg_base_reg[base_regno] = base_regno; 2281 reg_symbol_ref[base_regno] = NULL_RTX; 2282 reg_offset[base_regno] = 0; 2283 reg_set_luid[base_regno] = move2add_luid; 2284 gcc_assert (GET_MODE (base_reg) == mode); 2285 move2add_record_mode (base_reg); 2286 } 2287 2288 /* Copy base information from our base register. */ 2289 reg_set_luid[regno] = reg_set_luid[base_regno]; 2290 reg_base_reg[regno] = reg_base_reg[base_regno]; 2291 reg_symbol_ref[regno] = reg_symbol_ref[base_regno]; 2292 2293 /* Compute the sum of the offsets or constants. */ 2294 reg_offset[regno] 2295 = trunc_int_for_mode (offset + reg_offset[base_regno], mode); 2296 2297 move2add_record_mode (dst); 2298 } 2299 else 2300 { 2301 invalidate: 2302 /* Invalidate the contents of the register. */ 2303 move2add_record_mode (dst); 2304 reg_mode[regno] = VOIDmode; 2305 } 2306 } 2307 2308 namespace { 2309 2310 const pass_data pass_data_postreload_cse = 2311 { 2312 RTL_PASS, /* type */ 2313 "postreload", /* name */ 2314 OPTGROUP_NONE, /* optinfo_flags */ 2315 TV_RELOAD_CSE_REGS, /* tv_id */ 2316 0, /* properties_required */ 2317 0, /* properties_provided */ 2318 0, /* properties_destroyed */ 2319 0, /* todo_flags_start */ 2320 TODO_df_finish, /* todo_flags_finish */ 2321 }; 2322 2323 class pass_postreload_cse : public rtl_opt_pass 2324 { 2325 public: 2326 pass_postreload_cse (gcc::context *ctxt) 2327 : rtl_opt_pass (pass_data_postreload_cse, ctxt) 2328 {} 2329 2330 /* opt_pass methods: */ 2331 virtual bool gate (function *) { return (optimize > 0 && reload_completed); } 2332 2333 virtual unsigned int execute (function *); 2334 2335 }; // class pass_postreload_cse 2336 2337 unsigned int 2338 pass_postreload_cse::execute (function *fun) 2339 { 2340 if (!dbg_cnt (postreload_cse)) 2341 return 0; 2342 2343 /* Do a very simple CSE pass over just the hard registers. */ 2344 reload_cse_regs (get_insns ()); 2345 /* Reload_cse_regs can eliminate potentially-trapping MEMs. 2346 Remove any EH edges associated with them. */ 2347 if (fun->can_throw_non_call_exceptions 2348 && purge_all_dead_edges ()) 2349 cleanup_cfg (0); 2350 2351 return 0; 2352 } 2353 2354 } // anon namespace 2355 2356 rtl_opt_pass * 2357 make_pass_postreload_cse (gcc::context *ctxt) 2358 { 2359 return new pass_postreload_cse (ctxt); 2360 } 2361