1 /* Code for RTL transformations to satisfy insn constraints. 2 Copyright (C) 2010-2013 Free Software Foundation, Inc. 3 Contributed by Vladimir Makarov <vmakarov@redhat.com>. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it under 8 the terms of the GNU General Public License as published by the Free 9 Software Foundation; either version 3, or (at your option) any later 10 version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 /* This file contains code for 3 passes: constraint pass, 23 inheritance/split pass, and pass for undoing failed inheritance and 24 split. 25 26 The major goal of constraint pass is to transform RTL to satisfy 27 insn and address constraints by: 28 o choosing insn alternatives; 29 o generating *reload insns* (or reloads in brief) and *reload 30 pseudos* which will get necessary hard registers later; 31 o substituting pseudos with equivalent values and removing the 32 instructions that initialized those pseudos. 33 34 The constraint pass has biggest and most complicated code in LRA. 35 There are a lot of important details like: 36 o reuse of input reload pseudos to simplify reload pseudo 37 allocations; 38 o some heuristics to choose insn alternative to improve the 39 inheritance; 40 o early clobbers etc. 41 42 The pass is mimicking former reload pass in alternative choosing 43 because the reload pass is oriented to current machine description 44 model. It might be changed if the machine description model is 45 changed. 46 47 There is special code for preventing all LRA and this pass cycling 48 in case of bugs. 49 50 On the first iteration of the pass we process every instruction and 51 choose an alternative for each one. On subsequent iterations we try 52 to avoid reprocessing instructions if we can be sure that the old 53 choice is still valid. 54 55 The inheritance/spilt pass is to transform code to achieve 56 ineheritance and live range splitting. It is done on backward 57 traversal of EBBs. 58 59 The inheritance optimization goal is to reuse values in hard 60 registers. There is analogous optimization in old reload pass. The 61 inheritance is achieved by following transformation: 62 63 reload_p1 <- p reload_p1 <- p 64 ... new_p <- reload_p1 65 ... => ... 66 reload_p2 <- p reload_p2 <- new_p 67 68 where p is spilled and not changed between the insns. Reload_p1 is 69 also called *original pseudo* and new_p is called *inheritance 70 pseudo*. 71 72 The subsequent assignment pass will try to assign the same (or 73 another if it is not possible) hard register to new_p as to 74 reload_p1 or reload_p2. 75 76 If the assignment pass fails to assign a hard register to new_p, 77 this file will undo the inheritance and restore the original code. 78 This is because implementing the above sequence with a spilled 79 new_p would make the code much worse. The inheritance is done in 80 EBB scope. The above is just a simplified example to get an idea 81 of the inheritance as the inheritance is also done for non-reload 82 insns. 83 84 Splitting (transformation) is also done in EBB scope on the same 85 pass as the inheritance: 86 87 r <- ... or ... <- r r <- ... or ... <- r 88 ... s <- r (new insn -- save) 89 ... => 90 ... r <- s (new insn -- restore) 91 ... <- r ... <- r 92 93 The *split pseudo* s is assigned to the hard register of the 94 original pseudo or hard register r. 95 96 Splitting is done: 97 o In EBBs with high register pressure for global pseudos (living 98 in at least 2 BBs) and assigned to hard registers when there 99 are more one reloads needing the hard registers; 100 o for pseudos needing save/restore code around calls. 101 102 If the split pseudo still has the same hard register as the 103 original pseudo after the subsequent assignment pass or the 104 original pseudo was split, the opposite transformation is done on 105 the same pass for undoing inheritance. */ 106 107 #undef REG_OK_STRICT 108 109 #include "config.h" 110 #include "system.h" 111 #include "coretypes.h" 112 #include "tm.h" 113 #include "hard-reg-set.h" 114 #include "rtl.h" 115 #include "tm_p.h" 116 #include "regs.h" 117 #include "insn-config.h" 118 #include "insn-codes.h" 119 #include "recog.h" 120 #include "output.h" 121 #include "addresses.h" 122 #include "target.h" 123 #include "function.h" 124 #include "expr.h" 125 #include "basic-block.h" 126 #include "except.h" 127 #include "optabs.h" 128 #include "df.h" 129 #include "ira.h" 130 #include "rtl-error.h" 131 #include "lra-int.h" 132 133 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current 134 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted 135 reload insns. */ 136 static int bb_reload_num; 137 138 /* The current insn being processed and corresponding its data (basic 139 block, the insn data, the insn static data, and the mode of each 140 operand). */ 141 static rtx curr_insn; 142 static basic_block curr_bb; 143 static lra_insn_recog_data_t curr_id; 144 static struct lra_static_insn_data *curr_static_id; 145 static enum machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; 146 147 148 149 /* Start numbers for new registers and insns at the current constraints 150 pass start. */ 151 static int new_regno_start; 152 static int new_insn_uid_start; 153 154 /* If LOC is nonnull, strip any outer subreg from it. */ 155 static inline rtx * 156 strip_subreg (rtx *loc) 157 { 158 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; 159 } 160 161 /* Return hard regno of REGNO or if it is was not assigned to a hard 162 register, use a hard register from its allocno class. */ 163 static int 164 get_try_hard_regno (int regno) 165 { 166 int hard_regno; 167 enum reg_class rclass; 168 169 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) 170 hard_regno = lra_get_regno_hard_regno (regno); 171 if (hard_regno >= 0) 172 return hard_regno; 173 rclass = lra_get_allocno_class (regno); 174 if (rclass == NO_REGS) 175 return -1; 176 return ira_class_hard_regs[rclass][0]; 177 } 178 179 /* Return final hard regno (plus offset) which will be after 180 elimination. We do this for matching constraints because the final 181 hard regno could have a different class. */ 182 static int 183 get_final_hard_regno (int hard_regno, int offset) 184 { 185 if (hard_regno < 0) 186 return hard_regno; 187 hard_regno = lra_get_elimination_hard_regno (hard_regno); 188 return hard_regno + offset; 189 } 190 191 /* Return hard regno of X after removing subreg and making 192 elimination. If X is not a register or subreg of register, return 193 -1. For pseudo use its assignment. */ 194 static int 195 get_hard_regno (rtx x) 196 { 197 rtx reg; 198 int offset, hard_regno; 199 200 reg = x; 201 if (GET_CODE (x) == SUBREG) 202 reg = SUBREG_REG (x); 203 if (! REG_P (reg)) 204 return -1; 205 if ((hard_regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) 206 hard_regno = lra_get_regno_hard_regno (hard_regno); 207 if (hard_regno < 0) 208 return -1; 209 offset = 0; 210 if (GET_CODE (x) == SUBREG) 211 offset += subreg_regno_offset (hard_regno, GET_MODE (reg), 212 SUBREG_BYTE (x), GET_MODE (x)); 213 return get_final_hard_regno (hard_regno, offset); 214 } 215 216 /* If REGNO is a hard register or has been allocated a hard register, 217 return the class of that register. If REGNO is a reload pseudo 218 created by the current constraints pass, return its allocno class. 219 Return NO_REGS otherwise. */ 220 static enum reg_class 221 get_reg_class (int regno) 222 { 223 int hard_regno; 224 225 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) 226 hard_regno = lra_get_regno_hard_regno (regno); 227 if (hard_regno >= 0) 228 { 229 hard_regno = get_final_hard_regno (hard_regno, 0); 230 return REGNO_REG_CLASS (hard_regno); 231 } 232 if (regno >= new_regno_start) 233 return lra_get_allocno_class (regno); 234 return NO_REGS; 235 } 236 237 /* Return true if REG satisfies (or will satisfy) reg class constraint 238 CL. Use elimination first if REG is a hard register. If REG is a 239 reload pseudo created by this constraints pass, assume that it will 240 be allocated a hard register from its allocno class, but allow that 241 class to be narrowed to CL if it is currently a superset of CL. 242 243 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of 244 REGNO (reg), or NO_REGS if no change in its class was needed. */ 245 static bool 246 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) 247 { 248 enum reg_class rclass, common_class; 249 enum machine_mode reg_mode; 250 int class_size, hard_regno, nregs, i, j; 251 int regno = REGNO (reg); 252 253 if (new_class != NULL) 254 *new_class = NO_REGS; 255 if (regno < FIRST_PSEUDO_REGISTER) 256 { 257 rtx final_reg = reg; 258 rtx *final_loc = &final_reg; 259 260 lra_eliminate_reg_if_possible (final_loc); 261 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); 262 } 263 reg_mode = GET_MODE (reg); 264 rclass = get_reg_class (regno); 265 if (regno < new_regno_start 266 /* Do not allow the constraints for reload instructions to 267 influence the classes of new pseudos. These reloads are 268 typically moves that have many alternatives, and restricting 269 reload pseudos for one alternative may lead to situations 270 where other reload pseudos are no longer allocatable. */ 271 || INSN_UID (curr_insn) >= new_insn_uid_start) 272 /* When we don't know what class will be used finally for reload 273 pseudos, we use ALL_REGS. */ 274 return ((regno >= new_regno_start && rclass == ALL_REGS) 275 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] 276 && ! hard_reg_set_subset_p (reg_class_contents[cl], 277 lra_no_alloc_regs))); 278 else 279 { 280 common_class = ira_reg_class_subset[rclass][cl]; 281 if (new_class != NULL) 282 *new_class = common_class; 283 if (hard_reg_set_subset_p (reg_class_contents[common_class], 284 lra_no_alloc_regs)) 285 return false; 286 /* Check that there are enough allocatable regs. */ 287 class_size = ira_class_hard_regs_num[common_class]; 288 for (i = 0; i < class_size; i++) 289 { 290 hard_regno = ira_class_hard_regs[common_class][i]; 291 nregs = hard_regno_nregs[hard_regno][reg_mode]; 292 if (nregs == 1) 293 return true; 294 for (j = 0; j < nregs; j++) 295 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) 296 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], 297 hard_regno + j)) 298 break; 299 if (j >= nregs) 300 return true; 301 } 302 return false; 303 } 304 } 305 306 /* Return true if REGNO satisfies a memory constraint. */ 307 static bool 308 in_mem_p (int regno) 309 { 310 return get_reg_class (regno) == NO_REGS; 311 } 312 313 /* If we have decided to substitute X with another value, return that 314 value, otherwise return X. */ 315 static rtx 316 get_equiv_substitution (rtx x) 317 { 318 int regno; 319 rtx res; 320 321 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER 322 || ! ira_reg_equiv[regno].defined_p 323 || ! ira_reg_equiv[regno].profitable_p 324 || lra_get_regno_hard_regno (regno) >= 0) 325 return x; 326 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) 327 return res; 328 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) 329 return res; 330 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) 331 return res; 332 gcc_unreachable (); 333 } 334 335 /* Set up curr_operand_mode. */ 336 static void 337 init_curr_operand_mode (void) 338 { 339 int nop = curr_static_id->n_operands; 340 for (int i = 0; i < nop; i++) 341 { 342 enum machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); 343 if (mode == VOIDmode) 344 { 345 /* The .md mode for address operands is the mode of the 346 addressed value rather than the mode of the address itself. */ 347 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) 348 mode = Pmode; 349 else 350 mode = curr_static_id->operand[i].mode; 351 } 352 curr_operand_mode[i] = mode; 353 } 354 } 355 356 357 358 /* The page contains code to reuse input reloads. */ 359 360 /* Structure describes input reload of the current insns. */ 361 struct input_reload 362 { 363 /* Reloaded value. */ 364 rtx input; 365 /* Reload pseudo used. */ 366 rtx reg; 367 }; 368 369 /* The number of elements in the following array. */ 370 static int curr_insn_input_reloads_num; 371 /* Array containing info about input reloads. It is used to find the 372 same input reload and reuse the reload pseudo in this case. */ 373 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; 374 375 /* Initiate data concerning reuse of input reloads for the current 376 insn. */ 377 static void 378 init_curr_insn_input_reloads (void) 379 { 380 curr_insn_input_reloads_num = 0; 381 } 382 383 /* Change class of pseudo REGNO to NEW_CLASS. Print info about it 384 using TITLE. Output a new line if NL_P. */ 385 static void 386 change_class (int regno, enum reg_class new_class, 387 const char *title, bool nl_p) 388 { 389 lra_assert (regno >= FIRST_PSEUDO_REGISTER); 390 if (lra_dump_file != NULL) 391 fprintf (lra_dump_file, "%s to class %s for r%d", 392 title, reg_class_names[new_class], regno); 393 setup_reg_classes (regno, new_class, NO_REGS, new_class); 394 if (lra_dump_file != NULL && nl_p) 395 fprintf (lra_dump_file, "\n"); 396 } 397 398 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already 399 created input reload pseudo (only if TYPE is not OP_OUT). The 400 result pseudo is returned through RESULT_REG. Return TRUE if we 401 created a new pseudo, FALSE if we reused the already created input 402 reload pseudo. Use TITLE to describe new registers for debug 403 purposes. */ 404 static bool 405 get_reload_reg (enum op_type type, enum machine_mode mode, rtx original, 406 enum reg_class rclass, const char *title, rtx *result_reg) 407 { 408 int i, regno; 409 enum reg_class new_class; 410 411 if (type == OP_OUT) 412 { 413 *result_reg 414 = lra_create_new_reg_with_unique_value (mode, original, rclass, title); 415 return true; 416 } 417 /* Prevent reuse value of expression with side effects, 418 e.g. volatile memory. */ 419 if (! side_effects_p (original)) 420 for (i = 0; i < curr_insn_input_reloads_num; i++) 421 if (rtx_equal_p (curr_insn_input_reloads[i].input, original) 422 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) 423 { 424 rtx reg = curr_insn_input_reloads[i].reg; 425 regno = REGNO (reg); 426 /* If input is equal to original and both are VOIDmode, 427 GET_MODE (reg) might be still different from mode. 428 Ensure we don't return *result_reg with wrong mode. */ 429 if (GET_MODE (reg) != mode) 430 { 431 if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode)) 432 continue; 433 reg = lowpart_subreg (mode, reg, GET_MODE (reg)); 434 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) 435 continue; 436 } 437 *result_reg = reg; 438 if (lra_dump_file != NULL) 439 { 440 fprintf (lra_dump_file, " Reuse r%d for reload ", regno); 441 dump_value_slim (lra_dump_file, original, 1); 442 } 443 if (new_class != lra_get_allocno_class (regno)) 444 change_class (regno, new_class, ", change", false); 445 if (lra_dump_file != NULL) 446 fprintf (lra_dump_file, "\n"); 447 return false; 448 } 449 *result_reg = lra_create_new_reg (mode, original, rclass, title); 450 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); 451 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; 452 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; 453 return true; 454 } 455 456 457 458 /* The page contains code to extract memory address parts. */ 459 460 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */ 461 static inline bool 462 ok_for_index_p_nonstrict (rtx reg) 463 { 464 unsigned regno = REGNO (reg); 465 466 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); 467 } 468 469 /* A version of regno_ok_for_base_p for use here, when all pseudos 470 should count as OK. Arguments as for regno_ok_for_base_p. */ 471 static inline bool 472 ok_for_base_p_nonstrict (rtx reg, enum machine_mode mode, addr_space_t as, 473 enum rtx_code outer_code, enum rtx_code index_code) 474 { 475 unsigned regno = REGNO (reg); 476 477 if (regno >= FIRST_PSEUDO_REGISTER) 478 return true; 479 return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); 480 } 481 482 483 484 /* The page contains major code to choose the current insn alternative 485 and generate reloads for it. */ 486 487 /* Return the offset from REGNO of the least significant register 488 in (reg:MODE REGNO). 489 490 This function is used to tell whether two registers satisfy 491 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: 492 493 REGNO1 + lra_constraint_offset (REGNO1, MODE1) 494 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ 495 int 496 lra_constraint_offset (int regno, enum machine_mode mode) 497 { 498 lra_assert (regno < FIRST_PSEUDO_REGISTER); 499 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (mode) > UNITS_PER_WORD 500 && SCALAR_INT_MODE_P (mode)) 501 return hard_regno_nregs[regno][mode] - 1; 502 return 0; 503 } 504 505 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match 506 if they are the same hard reg, and has special hacks for 507 auto-increment and auto-decrement. This is specifically intended for 508 process_alt_operands to use in determining whether two operands 509 match. X is the operand whose number is the lower of the two. 510 511 It is supposed that X is the output operand and Y is the input 512 operand. Y_HARD_REGNO is the final hard regno of register Y or 513 register in subreg Y as we know it now. Otherwise, it is a 514 negative value. */ 515 static bool 516 operands_match_p (rtx x, rtx y, int y_hard_regno) 517 { 518 int i; 519 RTX_CODE code = GET_CODE (x); 520 const char *fmt; 521 522 if (x == y) 523 return true; 524 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) 525 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) 526 { 527 int j; 528 529 i = get_hard_regno (x); 530 if (i < 0) 531 goto slow; 532 533 if ((j = y_hard_regno) < 0) 534 goto slow; 535 536 i += lra_constraint_offset (i, GET_MODE (x)); 537 j += lra_constraint_offset (j, GET_MODE (y)); 538 539 return i == j; 540 } 541 542 /* If two operands must match, because they are really a single 543 operand of an assembler insn, then two post-increments are invalid 544 because the assembler insn would increment only once. On the 545 other hand, a post-increment matches ordinary indexing if the 546 post-increment is the output operand. */ 547 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) 548 return operands_match_p (XEXP (x, 0), y, y_hard_regno); 549 550 /* Two pre-increments are invalid because the assembler insn would 551 increment only once. On the other hand, a pre-increment matches 552 ordinary indexing if the pre-increment is the input operand. */ 553 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC 554 || GET_CODE (y) == PRE_MODIFY) 555 return operands_match_p (x, XEXP (y, 0), -1); 556 557 slow: 558 559 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) 560 && x == SUBREG_REG (y)) 561 return true; 562 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) 563 && SUBREG_REG (x) == y) 564 return true; 565 566 /* Now we have disposed of all the cases in which different rtx 567 codes can match. */ 568 if (code != GET_CODE (y)) 569 return false; 570 571 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ 572 if (GET_MODE (x) != GET_MODE (y)) 573 return false; 574 575 switch (code) 576 { 577 CASE_CONST_UNIQUE: 578 return false; 579 580 case LABEL_REF: 581 return XEXP (x, 0) == XEXP (y, 0); 582 case SYMBOL_REF: 583 return XSTR (x, 0) == XSTR (y, 0); 584 585 default: 586 break; 587 } 588 589 /* Compare the elements. If any pair of corresponding elements fail 590 to match, return false for the whole things. */ 591 592 fmt = GET_RTX_FORMAT (code); 593 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 594 { 595 int val, j; 596 switch (fmt[i]) 597 { 598 case 'w': 599 if (XWINT (x, i) != XWINT (y, i)) 600 return false; 601 break; 602 603 case 'i': 604 if (XINT (x, i) != XINT (y, i)) 605 return false; 606 break; 607 608 case 'e': 609 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); 610 if (val == 0) 611 return false; 612 break; 613 614 case '0': 615 break; 616 617 case 'E': 618 if (XVECLEN (x, i) != XVECLEN (y, i)) 619 return false; 620 for (j = XVECLEN (x, i) - 1; j >= 0; --j) 621 { 622 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); 623 if (val == 0) 624 return false; 625 } 626 break; 627 628 /* It is believed that rtx's at this level will never 629 contain anything but integers and other rtx's, except for 630 within LABEL_REFs and SYMBOL_REFs. */ 631 default: 632 gcc_unreachable (); 633 } 634 } 635 return true; 636 } 637 638 /* True if X is a constant that can be forced into the constant pool. 639 MODE is the mode of the operand, or VOIDmode if not known. */ 640 #define CONST_POOL_OK_P(MODE, X) \ 641 ((MODE) != VOIDmode \ 642 && CONSTANT_P (X) \ 643 && GET_CODE (X) != HIGH \ 644 && !targetm.cannot_force_const_mem (MODE, X)) 645 646 /* True if C is a non-empty register class that has too few registers 647 to be safely used as a reload target class. */ 648 #define SMALL_REGISTER_CLASS_P(C) \ 649 (reg_class_size [(C)] == 1 \ 650 || (reg_class_size [(C)] >= 1 && targetm.class_likely_spilled_p (C))) 651 652 /* If REG is a reload pseudo, try to make its class satisfying CL. */ 653 static void 654 narrow_reload_pseudo_class (rtx reg, enum reg_class cl) 655 { 656 enum reg_class rclass; 657 658 /* Do not make more accurate class from reloads generated. They are 659 mostly moves with a lot of constraints. Making more accurate 660 class may results in very narrow class and impossibility of find 661 registers for several reloads of one insn. */ 662 if (INSN_UID (curr_insn) >= new_insn_uid_start) 663 return; 664 if (GET_CODE (reg) == SUBREG) 665 reg = SUBREG_REG (reg); 666 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) 667 return; 668 if (in_class_p (reg, cl, &rclass) && rclass != cl) 669 change_class (REGNO (reg), rclass, " Change", true); 670 } 671 672 /* Generate reloads for matching OUT and INS (array of input operand 673 numbers with end marker -1) with reg class GOAL_CLASS. Add input 674 and output reloads correspondingly to the lists *BEFORE and *AFTER. 675 OUT might be negative. In this case we generate input reloads for 676 matched input operands INS. */ 677 static void 678 match_reload (signed char out, signed char *ins, enum reg_class goal_class, 679 rtx *before, rtx *after) 680 { 681 int i, in; 682 rtx new_in_reg, new_out_reg, reg, clobber; 683 enum machine_mode inmode, outmode; 684 rtx in_rtx = *curr_id->operand_loc[ins[0]]; 685 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; 686 687 inmode = curr_operand_mode[ins[0]]; 688 outmode = out < 0 ? inmode : curr_operand_mode[out]; 689 push_to_sequence (*before); 690 if (inmode != outmode) 691 { 692 if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) 693 { 694 reg = new_in_reg 695 = lra_create_new_reg_with_unique_value (inmode, in_rtx, 696 goal_class, ""); 697 if (SCALAR_INT_MODE_P (inmode)) 698 new_out_reg = gen_lowpart_SUBREG (outmode, reg); 699 else 700 new_out_reg = gen_rtx_SUBREG (outmode, reg, 0); 701 /* If the input reg is dying here, we can use the same hard 702 register for REG and IN_RTX. We do it only for original 703 pseudos as reload pseudos can die although original 704 pseudos still live where reload pseudos dies. */ 705 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start 706 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx))) 707 lra_reg_info[REGNO (reg)].val = lra_reg_info[REGNO (in_rtx)].val; 708 } 709 else 710 { 711 reg = new_out_reg 712 = lra_create_new_reg_with_unique_value (outmode, out_rtx, 713 goal_class, ""); 714 if (SCALAR_INT_MODE_P (outmode)) 715 new_in_reg = gen_lowpart_SUBREG (inmode, reg); 716 else 717 new_in_reg = gen_rtx_SUBREG (inmode, reg, 0); 718 /* NEW_IN_REG is non-paradoxical subreg. We don't want 719 NEW_OUT_REG living above. We add clobber clause for 720 this. This is just a temporary clobber. We can remove 721 it at the end of LRA work. */ 722 clobber = emit_clobber (new_out_reg); 723 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; 724 if (GET_CODE (in_rtx) == SUBREG) 725 { 726 rtx subreg_reg = SUBREG_REG (in_rtx); 727 728 /* If SUBREG_REG is dying here and sub-registers IN_RTX 729 and NEW_IN_REG are similar, we can use the same hard 730 register for REG and SUBREG_REG. */ 731 if (REG_P (subreg_reg) 732 && (int) REGNO (subreg_reg) < lra_new_regno_start 733 && GET_MODE (subreg_reg) == outmode 734 && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg) 735 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg))) 736 lra_reg_info[REGNO (reg)].val 737 = lra_reg_info[REGNO (subreg_reg)].val; 738 } 739 } 740 } 741 else 742 { 743 /* Pseudos have values -- see comments for lra_reg_info. 744 Different pseudos with the same value do not conflict even if 745 they live in the same place. When we create a pseudo we 746 assign value of original pseudo (if any) from which we 747 created the new pseudo. If we create the pseudo from the 748 input pseudo, the new pseudo will no conflict with the input 749 pseudo which is wrong when the input pseudo lives after the 750 insn and as the new pseudo value is changed by the insn 751 output. Therefore we create the new pseudo from the output. 752 753 We cannot reuse the current output register because we might 754 have a situation like "a <- a op b", where the constraints 755 force the second input operand ("b") to match the output 756 operand ("a"). "b" must then be copied into a new register 757 so that it doesn't clobber the current value of "a". */ 758 759 new_in_reg = new_out_reg 760 = lra_create_new_reg_with_unique_value (outmode, out_rtx, 761 goal_class, ""); 762 } 763 /* In operand can be got from transformations before processing insn 764 constraints. One example of such transformations is subreg 765 reloading (see function simplify_operand_subreg). The new 766 pseudos created by the transformations might have inaccurate 767 class (ALL_REGS) and we should make their classes more 768 accurate. */ 769 narrow_reload_pseudo_class (in_rtx, goal_class); 770 lra_emit_move (copy_rtx (new_in_reg), in_rtx); 771 *before = get_insns (); 772 end_sequence (); 773 for (i = 0; (in = ins[i]) >= 0; i++) 774 { 775 lra_assert 776 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode 777 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); 778 *curr_id->operand_loc[in] = new_in_reg; 779 } 780 lra_update_dups (curr_id, ins); 781 if (out < 0) 782 return; 783 /* See a comment for the input operand above. */ 784 narrow_reload_pseudo_class (out_rtx, goal_class); 785 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) 786 { 787 start_sequence (); 788 lra_emit_move (out_rtx, copy_rtx (new_out_reg)); 789 emit_insn (*after); 790 *after = get_insns (); 791 end_sequence (); 792 } 793 *curr_id->operand_loc[out] = new_out_reg; 794 lra_update_dup (curr_id, out); 795 } 796 797 /* Return register class which is union of all reg classes in insn 798 constraint alternative string starting with P. */ 799 static enum reg_class 800 reg_class_from_constraints (const char *p) 801 { 802 int c, len; 803 enum reg_class op_class = NO_REGS; 804 805 do 806 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) 807 { 808 case '#': 809 case ',': 810 return op_class; 811 812 case 'p': 813 op_class = (reg_class_subunion 814 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 815 ADDRESS, SCRATCH)]); 816 break; 817 818 case 'g': 819 case 'r': 820 op_class = reg_class_subunion[op_class][GENERAL_REGS]; 821 break; 822 823 default: 824 if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS) 825 { 826 #ifdef EXTRA_CONSTRAINT_STR 827 if (EXTRA_ADDRESS_CONSTRAINT (c, p)) 828 op_class 829 = (reg_class_subunion 830 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 831 ADDRESS, SCRATCH)]); 832 #endif 833 break; 834 } 835 836 op_class 837 = reg_class_subunion[op_class][REG_CLASS_FROM_CONSTRAINT (c, p)]; 838 break; 839 } 840 while ((p += len), c); 841 return op_class; 842 } 843 844 /* If OP is a register, return the class of the register as per 845 get_reg_class, otherwise return NO_REGS. */ 846 static inline enum reg_class 847 get_op_class (rtx op) 848 { 849 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; 850 } 851 852 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo 853 otherwise. If modes of MEM_PSEUDO and VAL are different, use 854 SUBREG for VAL to make them equal. */ 855 static rtx 856 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) 857 { 858 if (GET_MODE (mem_pseudo) != GET_MODE (val)) 859 val = gen_rtx_SUBREG (GET_MODE (mem_pseudo), 860 GET_CODE (val) == SUBREG ? SUBREG_REG (val) : val, 861 0); 862 return (to_p 863 ? gen_move_insn (mem_pseudo, val) 864 : gen_move_insn (val, mem_pseudo)); 865 } 866 867 /* Process a special case insn (register move), return true if we 868 don't need to process it anymore. Return that RTL was changed 869 through CHANGE_P and macro SECONDARY_MEMORY_NEEDED says to use 870 secondary memory through SEC_MEM_P. */ 871 static bool 872 check_and_process_move (bool *change_p, bool *sec_mem_p) 873 { 874 int sregno, dregno; 875 rtx set, dest, src, dreg, sreg, old_sreg, new_reg, before, scratch_reg; 876 enum reg_class dclass, sclass, secondary_class; 877 enum machine_mode sreg_mode; 878 secondary_reload_info sri; 879 880 *sec_mem_p = *change_p = false; 881 if ((set = single_set (curr_insn)) == NULL) 882 return false; 883 dreg = dest = SET_DEST (set); 884 sreg = src = SET_SRC (set); 885 /* Quick check on the right move insn which does not need 886 reloads. */ 887 if ((dclass = get_op_class (dest)) != NO_REGS 888 && (sclass = get_op_class (src)) != NO_REGS 889 /* The backend guarantees that register moves of cost 2 never 890 need reloads. */ 891 && targetm.register_move_cost (GET_MODE (src), dclass, sclass) == 2) 892 return true; 893 if (GET_CODE (dest) == SUBREG) 894 dreg = SUBREG_REG (dest); 895 if (GET_CODE (src) == SUBREG) 896 sreg = SUBREG_REG (src); 897 if (! REG_P (dreg) || ! REG_P (sreg)) 898 return false; 899 sclass = dclass = NO_REGS; 900 dreg = get_equiv_substitution (dreg); 901 if (REG_P (dreg)) 902 dclass = get_reg_class (REGNO (dreg)); 903 if (dclass == ALL_REGS) 904 /* ALL_REGS is used for new pseudos created by transformations 905 like reload of SUBREG_REG (see function 906 simplify_operand_subreg). We don't know their class yet. We 907 should figure out the class from processing the insn 908 constraints not in this fast path function. Even if ALL_REGS 909 were a right class for the pseudo, secondary_... hooks usually 910 are not define for ALL_REGS. */ 911 return false; 912 sreg_mode = GET_MODE (sreg); 913 old_sreg = sreg; 914 sreg = get_equiv_substitution (sreg); 915 if (REG_P (sreg)) 916 sclass = get_reg_class (REGNO (sreg)); 917 if (sclass == ALL_REGS) 918 /* See comments above. */ 919 return false; 920 #ifdef SECONDARY_MEMORY_NEEDED 921 if (dclass != NO_REGS && sclass != NO_REGS 922 && SECONDARY_MEMORY_NEEDED (sclass, dclass, GET_MODE (src))) 923 { 924 *sec_mem_p = true; 925 return false; 926 } 927 #endif 928 sri.prev_sri = NULL; 929 sri.icode = CODE_FOR_nothing; 930 sri.extra_cost = 0; 931 secondary_class = NO_REGS; 932 /* Set up hard register for a reload pseudo for hook 933 secondary_reload because some targets just ignore unassigned 934 pseudos in the hook. */ 935 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) 936 { 937 dregno = REGNO (dreg); 938 reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; 939 } 940 else 941 dregno = -1; 942 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) 943 { 944 sregno = REGNO (sreg); 945 reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; 946 } 947 else 948 sregno = -1; 949 if (sclass != NO_REGS) 950 secondary_class 951 = (enum reg_class) targetm.secondary_reload (false, dest, 952 (reg_class_t) sclass, 953 GET_MODE (src), &sri); 954 if (sclass == NO_REGS 955 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) 956 && dclass != NO_REGS)) 957 { 958 enum reg_class old_sclass = secondary_class; 959 secondary_reload_info old_sri = sri; 960 961 sri.prev_sri = NULL; 962 sri.icode = CODE_FOR_nothing; 963 sri.extra_cost = 0; 964 secondary_class 965 = (enum reg_class) targetm.secondary_reload (true, sreg, 966 (reg_class_t) dclass, 967 sreg_mode, &sri); 968 /* Check the target hook consistency. */ 969 lra_assert 970 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) 971 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) 972 || (secondary_class == old_sclass && sri.icode == old_sri.icode)); 973 } 974 if (sregno >= 0) 975 reg_renumber [sregno] = -1; 976 if (dregno >= 0) 977 reg_renumber [dregno] = -1; 978 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) 979 return false; 980 *change_p = true; 981 new_reg = NULL_RTX; 982 if (secondary_class != NO_REGS) 983 new_reg = lra_create_new_reg_with_unique_value (sreg_mode, NULL_RTX, 984 secondary_class, 985 "secondary"); 986 start_sequence (); 987 if (old_sreg != sreg) 988 sreg = copy_rtx (sreg); 989 if (sri.icode == CODE_FOR_nothing) 990 lra_emit_move (new_reg, sreg); 991 else 992 { 993 enum reg_class scratch_class; 994 995 scratch_class = (reg_class_from_constraints 996 (insn_data[sri.icode].operand[2].constraint)); 997 scratch_reg = (lra_create_new_reg_with_unique_value 998 (insn_data[sri.icode].operand[2].mode, NULL_RTX, 999 scratch_class, "scratch")); 1000 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, 1001 sreg, scratch_reg)); 1002 } 1003 before = get_insns (); 1004 end_sequence (); 1005 lra_process_new_insns (curr_insn, before, NULL_RTX, "Inserting the move"); 1006 if (new_reg != NULL_RTX) 1007 { 1008 if (GET_CODE (src) == SUBREG) 1009 SUBREG_REG (src) = new_reg; 1010 else 1011 SET_SRC (set) = new_reg; 1012 } 1013 else 1014 { 1015 if (lra_dump_file != NULL) 1016 { 1017 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); 1018 dump_insn_slim (lra_dump_file, curr_insn); 1019 } 1020 lra_set_insn_deleted (curr_insn); 1021 return true; 1022 } 1023 return false; 1024 } 1025 1026 /* The following data describe the result of process_alt_operands. 1027 The data are used in curr_insn_transform to generate reloads. */ 1028 1029 /* The chosen reg classes which should be used for the corresponding 1030 operands. */ 1031 static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; 1032 /* True if the operand should be the same as another operand and that 1033 other operand does not need a reload. */ 1034 static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; 1035 /* True if the operand does not need a reload. */ 1036 static bool goal_alt_win[MAX_RECOG_OPERANDS]; 1037 /* True if the operand can be offsetable memory. */ 1038 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; 1039 /* The number of an operand to which given operand can be matched to. */ 1040 static int goal_alt_matches[MAX_RECOG_OPERANDS]; 1041 /* The number of elements in the following array. */ 1042 static int goal_alt_dont_inherit_ops_num; 1043 /* Numbers of operands whose reload pseudos should not be inherited. */ 1044 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; 1045 /* True if the insn commutative operands should be swapped. */ 1046 static bool goal_alt_swapped; 1047 /* The chosen insn alternative. */ 1048 static int goal_alt_number; 1049 1050 /* The following five variables are used to choose the best insn 1051 alternative. They reflect final characteristics of the best 1052 alternative. */ 1053 1054 /* Number of necessary reloads and overall cost reflecting the 1055 previous value and other unpleasantness of the best alternative. */ 1056 static int best_losers, best_overall; 1057 /* Overall number hard registers used for reloads. For example, on 1058 some targets we need 2 general registers to reload DFmode and only 1059 one floating point register. */ 1060 static int best_reload_nregs; 1061 /* Overall number reflecting distances of previous reloading the same 1062 value. The distances are counted from the current BB start. It is 1063 used to improve inheritance chances. */ 1064 static int best_reload_sum; 1065 1066 /* True if the current insn should have no correspondingly input or 1067 output reloads. */ 1068 static bool no_input_reloads_p, no_output_reloads_p; 1069 1070 /* True if we swapped the commutative operands in the current 1071 insn. */ 1072 static int curr_swapped; 1073 1074 /* Arrange for address element *LOC to be a register of class CL. 1075 Add any input reloads to list BEFORE. AFTER is nonnull if *LOC is an 1076 automodified value; handle that case by adding the required output 1077 reloads to list AFTER. Return true if the RTL was changed. */ 1078 static bool 1079 process_addr_reg (rtx *loc, rtx *before, rtx *after, enum reg_class cl) 1080 { 1081 int regno; 1082 enum reg_class rclass, new_class; 1083 rtx reg; 1084 rtx new_reg; 1085 enum machine_mode mode; 1086 bool before_p = false; 1087 1088 loc = strip_subreg (loc); 1089 reg = *loc; 1090 mode = GET_MODE (reg); 1091 if (! REG_P (reg)) 1092 { 1093 /* Always reload memory in an address even if the target supports 1094 such addresses. */ 1095 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); 1096 before_p = true; 1097 } 1098 else 1099 { 1100 regno = REGNO (reg); 1101 rclass = get_reg_class (regno); 1102 if ((*loc = get_equiv_substitution (reg)) != reg) 1103 { 1104 if (lra_dump_file != NULL) 1105 { 1106 fprintf (lra_dump_file, 1107 "Changing pseudo %d in address of insn %u on equiv ", 1108 REGNO (reg), INSN_UID (curr_insn)); 1109 dump_value_slim (lra_dump_file, *loc, 1); 1110 fprintf (lra_dump_file, "\n"); 1111 } 1112 *loc = copy_rtx (*loc); 1113 } 1114 if (*loc != reg || ! in_class_p (reg, cl, &new_class)) 1115 { 1116 reg = *loc; 1117 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, 1118 mode, reg, cl, "address", &new_reg)) 1119 before_p = true; 1120 } 1121 else if (new_class != NO_REGS && rclass != new_class) 1122 { 1123 change_class (regno, new_class, " Change", true); 1124 return false; 1125 } 1126 else 1127 return false; 1128 } 1129 if (before_p) 1130 { 1131 push_to_sequence (*before); 1132 lra_emit_move (new_reg, reg); 1133 *before = get_insns (); 1134 end_sequence (); 1135 } 1136 *loc = new_reg; 1137 if (after != NULL) 1138 { 1139 start_sequence (); 1140 lra_emit_move (reg, new_reg); 1141 emit_insn (*after); 1142 *after = get_insns (); 1143 end_sequence (); 1144 } 1145 return true; 1146 } 1147 1148 /* Make reloads for subreg in operand NOP with internal subreg mode 1149 REG_MODE, add new reloads for further processing. Return true if 1150 any reload was generated. */ 1151 static bool 1152 simplify_operand_subreg (int nop, enum machine_mode reg_mode) 1153 { 1154 int hard_regno; 1155 rtx before, after; 1156 enum machine_mode mode; 1157 rtx reg, new_reg; 1158 rtx operand = *curr_id->operand_loc[nop]; 1159 enum reg_class regclass; 1160 enum op_type type; 1161 1162 before = after = NULL_RTX; 1163 1164 if (GET_CODE (operand) != SUBREG) 1165 return false; 1166 1167 mode = GET_MODE (operand); 1168 reg = SUBREG_REG (operand); 1169 type = curr_static_id->operand[nop].type; 1170 /* If we change address for paradoxical subreg of memory, the 1171 address might violate the necessary alignment or the access might 1172 be slow. So take this into consideration. We should not worry 1173 about access beyond allocated memory for paradoxical memory 1174 subregs as we don't substitute such equiv memory (see processing 1175 equivalences in function lra_constraints) and because for spilled 1176 pseudos we allocate stack memory enough for the biggest 1177 corresponding paradoxical subreg. */ 1178 if ((MEM_P (reg) 1179 && (! SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (reg)) 1180 || MEM_ALIGN (reg) >= GET_MODE_ALIGNMENT (mode))) 1181 || (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER)) 1182 { 1183 alter_subreg (curr_id->operand_loc[nop], false); 1184 return true; 1185 } 1186 /* Put constant into memory when we have mixed modes. It generates 1187 a better code in most cases as it does not need a secondary 1188 reload memory. It also prevents LRA looping when LRA is using 1189 secondary reload memory again and again. */ 1190 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) 1191 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) 1192 { 1193 SUBREG_REG (operand) = force_const_mem (reg_mode, reg); 1194 alter_subreg (curr_id->operand_loc[nop], false); 1195 return true; 1196 } 1197 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or 1198 if there may be a problem accessing OPERAND in the outer 1199 mode. */ 1200 if ((REG_P (reg) 1201 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 1202 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 1203 /* Don't reload paradoxical subregs because we could be looping 1204 having repeatedly final regno out of hard regs range. */ 1205 && (hard_regno_nregs[hard_regno][GET_MODE (reg)] 1206 >= hard_regno_nregs[hard_regno][mode]) 1207 && simplify_subreg_regno (hard_regno, GET_MODE (reg), 1208 SUBREG_BYTE (operand), mode) < 0) 1209 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) 1210 { 1211 enum op_type type = curr_static_id->operand[nop].type; 1212 /* The class will be defined later in curr_insn_transform. */ 1213 enum reg_class rclass 1214 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1215 1216 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, 1217 rclass, "subreg reg", &new_reg)) 1218 { 1219 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (new_reg)); 1220 if (type != OP_OUT 1221 || GET_MODE_SIZE (GET_MODE (reg)) > GET_MODE_SIZE (mode)) 1222 { 1223 push_to_sequence (before); 1224 lra_emit_move (new_reg, reg); 1225 before = get_insns (); 1226 end_sequence (); 1227 } 1228 if (type != OP_IN) 1229 { 1230 start_sequence (); 1231 lra_emit_move (reg, new_reg); 1232 emit_insn (after); 1233 after = get_insns (); 1234 end_sequence (); 1235 } 1236 } 1237 SUBREG_REG (operand) = new_reg; 1238 lra_process_new_insns (curr_insn, before, after, 1239 "Inserting subreg reload"); 1240 return true; 1241 } 1242 /* Force a reload for a paradoxical subreg. For paradoxical subreg, 1243 IRA allocates hardreg to the inner pseudo reg according to its mode 1244 instead of the outermode, so the size of the hardreg may not be enough 1245 to contain the outermode operand, in that case we may need to insert 1246 reload for the reg. For the following two types of paradoxical subreg, 1247 we need to insert reload: 1248 1. If the op_type is OP_IN, and the hardreg could not be paired with 1249 other hardreg to contain the outermode operand 1250 (checked by in_hard_reg_set_p), we need to insert the reload. 1251 2. If the op_type is OP_OUT or OP_INOUT. */ 1252 else if (REG_P (reg) 1253 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 1254 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 1255 && (hard_regno_nregs[hard_regno][GET_MODE (reg)] 1256 < hard_regno_nregs[hard_regno][mode]) 1257 && (regclass = lra_get_allocno_class (REGNO (reg))) 1258 && (type != OP_IN 1259 || !in_hard_reg_set_p (reg_class_contents[regclass], 1260 mode, hard_regno))) 1261 { 1262 /* The class will be defined later in curr_insn_transform. */ 1263 enum reg_class rclass 1264 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1265 rtx subreg; 1266 1267 new_reg = lra_create_new_reg_with_unique_value (mode, reg, rclass, 1268 "paradoxical subreg"); 1269 PUT_MODE (new_reg, mode); 1270 subreg = simplify_gen_subreg (GET_MODE (reg), new_reg, mode, 0); 1271 if (type != OP_OUT) 1272 { 1273 push_to_sequence (before); 1274 lra_emit_move (subreg, reg); 1275 before = get_insns (); 1276 end_sequence (); 1277 } 1278 if (type != OP_IN) 1279 { 1280 start_sequence (); 1281 lra_emit_move (reg, subreg); 1282 emit_insn (after); 1283 after = get_insns (); 1284 end_sequence (); 1285 } 1286 SUBREG_REG (operand) = new_reg; 1287 lra_process_new_insns (curr_insn, before, after, 1288 "Inserting paradoxical subreg reload"); 1289 return true; 1290 } 1291 return false; 1292 } 1293 1294 /* Return TRUE if X refers for a hard register from SET. */ 1295 static bool 1296 uses_hard_regs_p (rtx x, HARD_REG_SET set) 1297 { 1298 int i, j, x_hard_regno; 1299 enum machine_mode mode; 1300 const char *fmt; 1301 enum rtx_code code; 1302 1303 if (x == NULL_RTX) 1304 return false; 1305 code = GET_CODE (x); 1306 mode = GET_MODE (x); 1307 if (code == SUBREG) 1308 { 1309 x = SUBREG_REG (x); 1310 code = GET_CODE (x); 1311 if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) 1312 mode = GET_MODE (x); 1313 } 1314 1315 if (REG_P (x)) 1316 { 1317 x_hard_regno = get_hard_regno (x); 1318 return (x_hard_regno >= 0 1319 && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); 1320 } 1321 if (MEM_P (x)) 1322 { 1323 struct address_info ad; 1324 1325 decompose_mem_address (&ad, x); 1326 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) 1327 return true; 1328 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) 1329 return true; 1330 } 1331 fmt = GET_RTX_FORMAT (code); 1332 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1333 { 1334 if (fmt[i] == 'e') 1335 { 1336 if (uses_hard_regs_p (XEXP (x, i), set)) 1337 return true; 1338 } 1339 else if (fmt[i] == 'E') 1340 { 1341 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1342 if (uses_hard_regs_p (XVECEXP (x, i, j), set)) 1343 return true; 1344 } 1345 } 1346 return false; 1347 } 1348 1349 /* Return true if OP is a spilled pseudo. */ 1350 static inline bool 1351 spilled_pseudo_p (rtx op) 1352 { 1353 return (REG_P (op) 1354 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); 1355 } 1356 1357 /* Return true if X is a general constant. */ 1358 static inline bool 1359 general_constant_p (rtx x) 1360 { 1361 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); 1362 } 1363 1364 /* Major function to choose the current insn alternative and what 1365 operands should be reloaded and how. If ONLY_ALTERNATIVE is not 1366 negative we should consider only this alternative. Return false if 1367 we can not choose the alternative or find how to reload the 1368 operands. */ 1369 static bool 1370 process_alt_operands (int only_alternative) 1371 { 1372 bool ok_p = false; 1373 int nop, overall, nalt; 1374 int n_alternatives = curr_static_id->n_alternatives; 1375 int n_operands = curr_static_id->n_operands; 1376 /* LOSERS counts the operands that don't fit this alternative and 1377 would require loading. */ 1378 int losers; 1379 /* REJECT is a count of how undesirable this alternative says it is 1380 if any reloading is required. If the alternative matches exactly 1381 then REJECT is ignored, but otherwise it gets this much counted 1382 against it in addition to the reloading needed. */ 1383 int reject; 1384 /* The number of elements in the following array. */ 1385 int early_clobbered_regs_num; 1386 /* Numbers of operands which are early clobber registers. */ 1387 int early_clobbered_nops[MAX_RECOG_OPERANDS]; 1388 enum reg_class curr_alt[MAX_RECOG_OPERANDS]; 1389 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; 1390 bool curr_alt_match_win[MAX_RECOG_OPERANDS]; 1391 bool curr_alt_win[MAX_RECOG_OPERANDS]; 1392 bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; 1393 int curr_alt_matches[MAX_RECOG_OPERANDS]; 1394 /* The number of elements in the following array. */ 1395 int curr_alt_dont_inherit_ops_num; 1396 /* Numbers of operands whose reload pseudos should not be inherited. */ 1397 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; 1398 rtx op; 1399 /* The register when the operand is a subreg of register, otherwise the 1400 operand itself. */ 1401 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; 1402 /* The register if the operand is a register or subreg of register, 1403 otherwise NULL. */ 1404 rtx operand_reg[MAX_RECOG_OPERANDS]; 1405 int hard_regno[MAX_RECOG_OPERANDS]; 1406 enum machine_mode biggest_mode[MAX_RECOG_OPERANDS]; 1407 int reload_nregs, reload_sum; 1408 bool costly_p; 1409 enum reg_class cl; 1410 1411 /* Calculate some data common for all alternatives to speed up the 1412 function. */ 1413 for (nop = 0; nop < n_operands; nop++) 1414 { 1415 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; 1416 /* The real hard regno of the operand after the allocation. */ 1417 hard_regno[nop] = get_hard_regno (op); 1418 1419 operand_reg[nop] = op; 1420 biggest_mode[nop] = GET_MODE (operand_reg[nop]); 1421 if (GET_CODE (operand_reg[nop]) == SUBREG) 1422 { 1423 operand_reg[nop] = SUBREG_REG (operand_reg[nop]); 1424 if (GET_MODE_SIZE (biggest_mode[nop]) 1425 < GET_MODE_SIZE (GET_MODE (operand_reg[nop]))) 1426 biggest_mode[nop] = GET_MODE (operand_reg[nop]); 1427 } 1428 if (REG_P (operand_reg[nop])) 1429 no_subreg_reg_operand[nop] = operand_reg[nop]; 1430 else 1431 operand_reg[nop] = NULL_RTX; 1432 } 1433 1434 /* The constraints are made of several alternatives. Each operand's 1435 constraint looks like foo,bar,... with commas separating the 1436 alternatives. The first alternatives for all operands go 1437 together, the second alternatives go together, etc. 1438 1439 First loop over alternatives. */ 1440 for (nalt = 0; nalt < n_alternatives; nalt++) 1441 { 1442 /* Loop over operands for one constraint alternative. */ 1443 #if HAVE_ATTR_enabled 1444 if (curr_id->alternative_enabled_p != NULL 1445 && ! curr_id->alternative_enabled_p[nalt]) 1446 continue; 1447 #endif 1448 1449 if (only_alternative >= 0 && nalt != only_alternative) 1450 continue; 1451 1452 1453 overall = losers = reject = reload_nregs = reload_sum = 0; 1454 for (nop = 0; nop < n_operands; nop++) 1455 reject += (curr_static_id 1456 ->operand_alternative[nalt * n_operands + nop].reject); 1457 early_clobbered_regs_num = 0; 1458 1459 for (nop = 0; nop < n_operands; nop++) 1460 { 1461 const char *p; 1462 char *end; 1463 int len, c, m, i, opalt_num, this_alternative_matches; 1464 bool win, did_match, offmemok, early_clobber_p; 1465 /* false => this operand can be reloaded somehow for this 1466 alternative. */ 1467 bool badop; 1468 /* true => this operand can be reloaded if the alternative 1469 allows regs. */ 1470 bool winreg; 1471 /* True if a constant forced into memory would be OK for 1472 this operand. */ 1473 bool constmemok; 1474 enum reg_class this_alternative, this_costly_alternative; 1475 HARD_REG_SET this_alternative_set, this_costly_alternative_set; 1476 bool this_alternative_match_win, this_alternative_win; 1477 bool this_alternative_offmemok; 1478 enum machine_mode mode; 1479 1480 opalt_num = nalt * n_operands + nop; 1481 if (curr_static_id->operand_alternative[opalt_num].anything_ok) 1482 { 1483 /* Fast track for no constraints at all. */ 1484 curr_alt[nop] = NO_REGS; 1485 CLEAR_HARD_REG_SET (curr_alt_set[nop]); 1486 curr_alt_win[nop] = true; 1487 curr_alt_match_win[nop] = false; 1488 curr_alt_offmemok[nop] = false; 1489 curr_alt_matches[nop] = -1; 1490 continue; 1491 } 1492 1493 op = no_subreg_reg_operand[nop]; 1494 mode = curr_operand_mode[nop]; 1495 1496 win = did_match = winreg = offmemok = constmemok = false; 1497 badop = true; 1498 1499 early_clobber_p = false; 1500 p = curr_static_id->operand_alternative[opalt_num].constraint; 1501 1502 this_costly_alternative = this_alternative = NO_REGS; 1503 /* We update set of possible hard regs besides its class 1504 because reg class might be inaccurate. For example, 1505 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM 1506 is translated in HI_REGS because classes are merged by 1507 pairs and there is no accurate intermediate class. */ 1508 CLEAR_HARD_REG_SET (this_alternative_set); 1509 CLEAR_HARD_REG_SET (this_costly_alternative_set); 1510 this_alternative_win = false; 1511 this_alternative_match_win = false; 1512 this_alternative_offmemok = false; 1513 this_alternative_matches = -1; 1514 1515 /* An empty constraint should be excluded by the fast 1516 track. */ 1517 lra_assert (*p != 0 && *p != ','); 1518 1519 /* Scan this alternative's specs for this operand; set WIN 1520 if the operand fits any letter in this alternative. 1521 Otherwise, clear BADOP if this operand could fit some 1522 letter after reloads, or set WINREG if this operand could 1523 fit after reloads provided the constraint allows some 1524 registers. */ 1525 costly_p = false; 1526 do 1527 { 1528 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) 1529 { 1530 case '\0': 1531 len = 0; 1532 break; 1533 case ',': 1534 c = '\0'; 1535 break; 1536 1537 case '=': case '+': case '?': case '*': case '!': 1538 case ' ': case '\t': 1539 break; 1540 1541 case '%': 1542 /* We only support one commutative marker, the first 1543 one. We already set commutative above. */ 1544 break; 1545 1546 case '&': 1547 early_clobber_p = true; 1548 break; 1549 1550 case '#': 1551 /* Ignore rest of this alternative. */ 1552 c = '\0'; 1553 break; 1554 1555 case '0': case '1': case '2': case '3': case '4': 1556 case '5': case '6': case '7': case '8': case '9': 1557 { 1558 int m_hregno; 1559 bool match_p; 1560 1561 m = strtoul (p, &end, 10); 1562 p = end; 1563 len = 0; 1564 lra_assert (nop > m); 1565 1566 this_alternative_matches = m; 1567 m_hregno = get_hard_regno (*curr_id->operand_loc[m]); 1568 /* We are supposed to match a previous operand. 1569 If we do, we win if that one did. If we do 1570 not, count both of the operands as losers. 1571 (This is too conservative, since most of the 1572 time only a single reload insn will be needed 1573 to make the two operands win. As a result, 1574 this alternative may be rejected when it is 1575 actually desirable.) */ 1576 match_p = false; 1577 if (operands_match_p (*curr_id->operand_loc[nop], 1578 *curr_id->operand_loc[m], m_hregno)) 1579 { 1580 /* We should reject matching of an early 1581 clobber operand if the matching operand is 1582 not dying in the insn. */ 1583 if (! curr_static_id->operand[m].early_clobber 1584 || operand_reg[nop] == NULL_RTX 1585 || (find_regno_note (curr_insn, REG_DEAD, 1586 REGNO (op)) 1587 || REGNO (op) == REGNO (operand_reg[m]))) 1588 match_p = true; 1589 } 1590 if (match_p) 1591 { 1592 /* If we are matching a non-offsettable 1593 address where an offsettable address was 1594 expected, then we must reject this 1595 combination, because we can't reload 1596 it. */ 1597 if (curr_alt_offmemok[m] 1598 && MEM_P (*curr_id->operand_loc[m]) 1599 && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) 1600 continue; 1601 1602 } 1603 else 1604 { 1605 /* Operands don't match. Both operands must 1606 allow a reload register, otherwise we 1607 cannot make them match. */ 1608 if (curr_alt[m] == NO_REGS) 1609 break; 1610 /* Retroactively mark the operand we had to 1611 match as a loser, if it wasn't already and 1612 it wasn't matched to a register constraint 1613 (e.g it might be matched by memory). */ 1614 if (curr_alt_win[m] 1615 && (operand_reg[m] == NULL_RTX 1616 || hard_regno[m] < 0)) 1617 { 1618 losers++; 1619 reload_nregs 1620 += (ira_reg_class_max_nregs[curr_alt[m]] 1621 [GET_MODE (*curr_id->operand_loc[m])]); 1622 } 1623 1624 /* We prefer no matching alternatives because 1625 it gives more freedom in RA. */ 1626 if (operand_reg[nop] == NULL_RTX 1627 || (find_regno_note (curr_insn, REG_DEAD, 1628 REGNO (operand_reg[nop])) 1629 == NULL_RTX)) 1630 reject += 2; 1631 } 1632 /* If we have to reload this operand and some 1633 previous operand also had to match the same 1634 thing as this operand, we don't know how to do 1635 that. */ 1636 if (!match_p || !curr_alt_win[m]) 1637 { 1638 for (i = 0; i < nop; i++) 1639 if (curr_alt_matches[i] == m) 1640 break; 1641 if (i < nop) 1642 break; 1643 } 1644 else 1645 did_match = true; 1646 1647 /* This can be fixed with reloads if the operand 1648 we are supposed to match can be fixed with 1649 reloads. */ 1650 badop = false; 1651 this_alternative = curr_alt[m]; 1652 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); 1653 winreg = this_alternative != NO_REGS; 1654 break; 1655 } 1656 1657 case 'p': 1658 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 1659 ADDRESS, SCRATCH); 1660 this_alternative = reg_class_subunion[this_alternative][cl]; 1661 IOR_HARD_REG_SET (this_alternative_set, 1662 reg_class_contents[cl]); 1663 if (costly_p) 1664 { 1665 this_costly_alternative 1666 = reg_class_subunion[this_costly_alternative][cl]; 1667 IOR_HARD_REG_SET (this_costly_alternative_set, 1668 reg_class_contents[cl]); 1669 } 1670 win = true; 1671 badop = false; 1672 break; 1673 1674 case TARGET_MEM_CONSTRAINT: 1675 if (MEM_P (op) || spilled_pseudo_p (op)) 1676 win = true; 1677 /* We can put constant or pseudo value into memory 1678 to satisfy the constraint. */ 1679 if (CONST_POOL_OK_P (mode, op) || REG_P (op)) 1680 badop = false; 1681 constmemok = true; 1682 break; 1683 1684 case '<': 1685 if (MEM_P (op) 1686 && (GET_CODE (XEXP (op, 0)) == PRE_DEC 1687 || GET_CODE (XEXP (op, 0)) == POST_DEC)) 1688 win = true; 1689 break; 1690 1691 case '>': 1692 if (MEM_P (op) 1693 && (GET_CODE (XEXP (op, 0)) == PRE_INC 1694 || GET_CODE (XEXP (op, 0)) == POST_INC)) 1695 win = true; 1696 break; 1697 1698 /* Memory op whose address is not offsettable. */ 1699 case 'V': 1700 if (MEM_P (op) 1701 && ! offsettable_nonstrict_memref_p (op)) 1702 win = true; 1703 break; 1704 1705 /* Memory operand whose address is offsettable. */ 1706 case 'o': 1707 if ((MEM_P (op) 1708 && offsettable_nonstrict_memref_p (op)) 1709 || spilled_pseudo_p (op)) 1710 win = true; 1711 /* We can put constant or pseudo value into memory 1712 or make memory address offsetable to satisfy the 1713 constraint. */ 1714 if (CONST_POOL_OK_P (mode, op) || MEM_P (op) || REG_P (op)) 1715 badop = false; 1716 constmemok = true; 1717 offmemok = true; 1718 break; 1719 1720 case 'E': 1721 case 'F': 1722 if (GET_CODE (op) == CONST_DOUBLE 1723 || (GET_CODE (op) == CONST_VECTOR 1724 && (GET_MODE_CLASS (mode) == MODE_VECTOR_FLOAT))) 1725 win = true; 1726 break; 1727 1728 case 'G': 1729 case 'H': 1730 if (GET_CODE (op) == CONST_DOUBLE 1731 && CONST_DOUBLE_OK_FOR_CONSTRAINT_P (op, c, p)) 1732 win = true; 1733 break; 1734 1735 case 's': 1736 if (CONST_INT_P (op) 1737 || (GET_CODE (op) == CONST_DOUBLE && mode == VOIDmode)) 1738 break; 1739 1740 case 'i': 1741 if (general_constant_p (op)) 1742 win = true; 1743 break; 1744 1745 case 'n': 1746 if (CONST_INT_P (op) 1747 || (GET_CODE (op) == CONST_DOUBLE && mode == VOIDmode)) 1748 win = true; 1749 break; 1750 1751 case 'I': 1752 case 'J': 1753 case 'K': 1754 case 'L': 1755 case 'M': 1756 case 'N': 1757 case 'O': 1758 case 'P': 1759 if (CONST_INT_P (op) 1760 && CONST_OK_FOR_CONSTRAINT_P (INTVAL (op), c, p)) 1761 win = true; 1762 break; 1763 1764 case 'X': 1765 /* This constraint should be excluded by the fast 1766 track. */ 1767 gcc_unreachable (); 1768 break; 1769 1770 case 'g': 1771 if (MEM_P (op) 1772 || general_constant_p (op) 1773 || spilled_pseudo_p (op)) 1774 win = true; 1775 /* Drop through into 'r' case. */ 1776 1777 case 'r': 1778 this_alternative 1779 = reg_class_subunion[this_alternative][GENERAL_REGS]; 1780 IOR_HARD_REG_SET (this_alternative_set, 1781 reg_class_contents[GENERAL_REGS]); 1782 if (costly_p) 1783 { 1784 this_costly_alternative 1785 = (reg_class_subunion 1786 [this_costly_alternative][GENERAL_REGS]); 1787 IOR_HARD_REG_SET (this_costly_alternative_set, 1788 reg_class_contents[GENERAL_REGS]); 1789 } 1790 goto reg; 1791 1792 default: 1793 if (REG_CLASS_FROM_CONSTRAINT (c, p) == NO_REGS) 1794 { 1795 #ifdef EXTRA_CONSTRAINT_STR 1796 if (EXTRA_MEMORY_CONSTRAINT (c, p)) 1797 { 1798 if (EXTRA_CONSTRAINT_STR (op, c, p)) 1799 win = true; 1800 else if (spilled_pseudo_p (op)) 1801 win = true; 1802 1803 /* If we didn't already win, we can reload 1804 constants via force_const_mem or put the 1805 pseudo value into memory, or make other 1806 memory by reloading the address like for 1807 'o'. */ 1808 if (CONST_POOL_OK_P (mode, op) 1809 || MEM_P (op) || REG_P (op)) 1810 badop = false; 1811 constmemok = true; 1812 offmemok = true; 1813 break; 1814 } 1815 if (EXTRA_ADDRESS_CONSTRAINT (c, p)) 1816 { 1817 if (EXTRA_CONSTRAINT_STR (op, c, p)) 1818 win = true; 1819 1820 /* If we didn't already win, we can reload 1821 the address into a base register. */ 1822 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 1823 ADDRESS, SCRATCH); 1824 this_alternative 1825 = reg_class_subunion[this_alternative][cl]; 1826 IOR_HARD_REG_SET (this_alternative_set, 1827 reg_class_contents[cl]); 1828 if (costly_p) 1829 { 1830 this_costly_alternative 1831 = (reg_class_subunion 1832 [this_costly_alternative][cl]); 1833 IOR_HARD_REG_SET (this_costly_alternative_set, 1834 reg_class_contents[cl]); 1835 } 1836 badop = false; 1837 break; 1838 } 1839 1840 if (EXTRA_CONSTRAINT_STR (op, c, p)) 1841 win = true; 1842 #endif 1843 break; 1844 } 1845 1846 cl = REG_CLASS_FROM_CONSTRAINT (c, p); 1847 this_alternative = reg_class_subunion[this_alternative][cl]; 1848 IOR_HARD_REG_SET (this_alternative_set, 1849 reg_class_contents[cl]); 1850 if (costly_p) 1851 { 1852 this_costly_alternative 1853 = reg_class_subunion[this_costly_alternative][cl]; 1854 IOR_HARD_REG_SET (this_costly_alternative_set, 1855 reg_class_contents[cl]); 1856 } 1857 reg: 1858 if (mode == BLKmode) 1859 break; 1860 winreg = true; 1861 if (REG_P (op)) 1862 { 1863 if (hard_regno[nop] >= 0 1864 && in_hard_reg_set_p (this_alternative_set, 1865 mode, hard_regno[nop])) 1866 win = true; 1867 else if (hard_regno[nop] < 0 1868 && in_class_p (op, this_alternative, NULL)) 1869 win = true; 1870 } 1871 break; 1872 } 1873 if (c != ' ' && c != '\t') 1874 costly_p = c == '*'; 1875 } 1876 while ((p += len), c); 1877 1878 /* Record which operands fit this alternative. */ 1879 if (win) 1880 { 1881 this_alternative_win = true; 1882 if (operand_reg[nop] != NULL_RTX) 1883 { 1884 if (hard_regno[nop] >= 0) 1885 { 1886 if (in_hard_reg_set_p (this_costly_alternative_set, 1887 mode, hard_regno[nop])) 1888 reject++; 1889 } 1890 else 1891 { 1892 /* Prefer won reg to spilled pseudo under other equal 1893 conditions. */ 1894 reject++; 1895 if (in_class_p (operand_reg[nop], 1896 this_costly_alternative, NULL)) 1897 reject++; 1898 } 1899 /* We simulate the behaviour of old reload here. 1900 Although scratches need hard registers and it 1901 might result in spilling other pseudos, no reload 1902 insns are generated for the scratches. So it 1903 might cost something but probably less than old 1904 reload pass believes. */ 1905 if (lra_former_scratch_p (REGNO (operand_reg[nop]))) 1906 reject += LRA_LOSER_COST_FACTOR; 1907 } 1908 } 1909 else if (did_match) 1910 this_alternative_match_win = true; 1911 else 1912 { 1913 int const_to_mem = 0; 1914 bool no_regs_p; 1915 1916 /* If this alternative asks for a specific reg class, see if there 1917 is at least one allocatable register in that class. */ 1918 no_regs_p 1919 = (this_alternative == NO_REGS 1920 || (hard_reg_set_subset_p 1921 (reg_class_contents[this_alternative], 1922 lra_no_alloc_regs))); 1923 1924 /* For asms, verify that the class for this alternative is possible 1925 for the mode that is specified. */ 1926 if (!no_regs_p && REG_P (op) && INSN_CODE (curr_insn) < 0) 1927 { 1928 int i; 1929 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1930 if (HARD_REGNO_MODE_OK (i, mode) 1931 && in_hard_reg_set_p (reg_class_contents[this_alternative], mode, i)) 1932 break; 1933 if (i == FIRST_PSEUDO_REGISTER) 1934 winreg = false; 1935 } 1936 1937 /* If this operand accepts a register, and if the 1938 register class has at least one allocatable register, 1939 then this operand can be reloaded. */ 1940 if (winreg && !no_regs_p) 1941 badop = false; 1942 1943 if (badop) 1944 goto fail; 1945 1946 this_alternative_offmemok = offmemok; 1947 if (this_costly_alternative != NO_REGS) 1948 reject++; 1949 /* If the operand is dying, has a matching constraint, 1950 and satisfies constraints of the matched operand 1951 which failed to satisfy the own constraints, we do 1952 not need to generate a reload insn for this 1953 operand. */ 1954 if (!(this_alternative_matches >= 0 1955 && !curr_alt_win[this_alternative_matches] 1956 && REG_P (op) 1957 && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) 1958 && (hard_regno[nop] >= 0 1959 ? in_hard_reg_set_p (this_alternative_set, 1960 mode, hard_regno[nop]) 1961 : in_class_p (op, this_alternative, NULL)))) 1962 { 1963 /* Strict_low_part requires to reload the register 1964 not the sub-register. In this case we should 1965 check that a final reload hard reg can hold the 1966 value mode. */ 1967 if (curr_static_id->operand[nop].strict_low 1968 && REG_P (op) 1969 && hard_regno[nop] < 0 1970 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG 1971 && ira_class_hard_regs_num[this_alternative] > 0 1972 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs 1973 [this_alternative][0], 1974 GET_MODE (op))) 1975 goto fail; 1976 losers++; 1977 } 1978 if (operand_reg[nop] != NULL_RTX 1979 /* Output operands and matched input operands are 1980 not inherited. The following conditions do not 1981 exactly describe the previous statement but they 1982 are pretty close. */ 1983 && curr_static_id->operand[nop].type != OP_OUT 1984 && (this_alternative_matches < 0 1985 || curr_static_id->operand[nop].type != OP_IN)) 1986 { 1987 int last_reload = (lra_reg_info[ORIGINAL_REGNO 1988 (operand_reg[nop])] 1989 .last_reload); 1990 1991 if (last_reload > bb_reload_num) 1992 reload_sum += last_reload - bb_reload_num; 1993 } 1994 /* If this is a constant that is reloaded into the 1995 desired class by copying it to memory first, count 1996 that as another reload. This is consistent with 1997 other code and is required to avoid choosing another 1998 alternative when the constant is moved into memory. 1999 Note that the test here is precisely the same as in 2000 the code below that calls force_const_mem. */ 2001 if (CONST_POOL_OK_P (mode, op) 2002 && ((targetm.preferred_reload_class 2003 (op, this_alternative) == NO_REGS) 2004 || no_input_reloads_p)) 2005 { 2006 const_to_mem = 1; 2007 if (! no_regs_p) 2008 losers++; 2009 } 2010 2011 /* Alternative loses if it requires a type of reload not 2012 permitted for this insn. We can always reload 2013 objects with a REG_UNUSED note. */ 2014 if ((curr_static_id->operand[nop].type != OP_IN 2015 && no_output_reloads_p 2016 && ! find_reg_note (curr_insn, REG_UNUSED, op)) 2017 || (curr_static_id->operand[nop].type != OP_OUT 2018 && no_input_reloads_p && ! const_to_mem)) 2019 goto fail; 2020 2021 /* Check strong discouragement of reload of non-constant 2022 into class THIS_ALTERNATIVE. */ 2023 if (! CONSTANT_P (op) && ! no_regs_p 2024 && (targetm.preferred_reload_class 2025 (op, this_alternative) == NO_REGS 2026 || (curr_static_id->operand[nop].type == OP_OUT 2027 && (targetm.preferred_output_reload_class 2028 (op, this_alternative) == NO_REGS)))) 2029 reject += LRA_MAX_REJECT; 2030 2031 if (MEM_P (op) && offmemok) 2032 { 2033 /* If we know offset and this non-offsetable memory, 2034 something wrong with this memory and it is better 2035 to try other memory possibilities. */ 2036 if (MEM_OFFSET_KNOWN_P (op)) 2037 reject += LRA_MAX_REJECT; 2038 } 2039 else if (! (const_to_mem && constmemok)) 2040 { 2041 /* We prefer to reload pseudos over reloading other 2042 things, since such reloads may be able to be 2043 eliminated later. So bump REJECT in other cases. 2044 Don't do this in the case where we are forcing a 2045 constant into memory and it will then win since 2046 we don't want to have a different alternative 2047 match then. */ 2048 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) 2049 reject += 2; 2050 2051 if (! no_regs_p) 2052 reload_nregs 2053 += ira_reg_class_max_nregs[this_alternative][mode]; 2054 2055 if (SMALL_REGISTER_CLASS_P (this_alternative)) 2056 reject += LRA_LOSER_COST_FACTOR / 2; 2057 } 2058 2059 /* We are trying to spill pseudo into memory. It is 2060 usually more costly than moving to a hard register 2061 although it might takes the same number of 2062 reloads. */ 2063 if (no_regs_p && REG_P (op)) 2064 reject += 2; 2065 2066 #ifdef SECONDARY_MEMORY_NEEDED 2067 /* If reload requires moving value through secondary 2068 memory, it will need one more insn at least. */ 2069 if (this_alternative != NO_REGS 2070 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS 2071 && ((curr_static_id->operand[nop].type != OP_OUT 2072 && SECONDARY_MEMORY_NEEDED (cl, this_alternative, 2073 GET_MODE (op))) 2074 || (curr_static_id->operand[nop].type != OP_IN 2075 && SECONDARY_MEMORY_NEEDED (this_alternative, cl, 2076 GET_MODE (op))))) 2077 losers++; 2078 #endif 2079 /* Input reloads can be inherited more often than output 2080 reloads can be removed, so penalize output 2081 reloads. */ 2082 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) 2083 reject++; 2084 2085 } 2086 2087 if (early_clobber_p) 2088 reject++; 2089 /* ??? We check early clobbers after processing all operands 2090 (see loop below) and there we update the costs more. 2091 Should we update the cost (may be approximately) here 2092 because of early clobber register reloads or it is a rare 2093 or non-important thing to be worth to do it. */ 2094 overall = losers * LRA_LOSER_COST_FACTOR + reject; 2095 if ((best_losers == 0 || losers != 0) && best_overall < overall) 2096 { 2097 if (lra_dump_file != NULL) 2098 fprintf (lra_dump_file, 2099 " alt=%d,overall=%d,losers=%d -- reject\n", 2100 nalt, overall, losers); 2101 goto fail; 2102 } 2103 2104 curr_alt[nop] = this_alternative; 2105 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); 2106 curr_alt_win[nop] = this_alternative_win; 2107 curr_alt_match_win[nop] = this_alternative_match_win; 2108 curr_alt_offmemok[nop] = this_alternative_offmemok; 2109 curr_alt_matches[nop] = this_alternative_matches; 2110 2111 if (this_alternative_matches >= 0 2112 && !did_match && !this_alternative_win) 2113 curr_alt_win[this_alternative_matches] = false; 2114 2115 if (early_clobber_p && operand_reg[nop] != NULL_RTX) 2116 early_clobbered_nops[early_clobbered_regs_num++] = nop; 2117 } 2118 ok_p = true; 2119 curr_alt_dont_inherit_ops_num = 0; 2120 for (nop = 0; nop < early_clobbered_regs_num; nop++) 2121 { 2122 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; 2123 HARD_REG_SET temp_set; 2124 2125 i = early_clobbered_nops[nop]; 2126 if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) 2127 || hard_regno[i] < 0) 2128 continue; 2129 lra_assert (operand_reg[i] != NULL_RTX); 2130 clobbered_hard_regno = hard_regno[i]; 2131 CLEAR_HARD_REG_SET (temp_set); 2132 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); 2133 first_conflict_j = last_conflict_j = -1; 2134 for (j = 0; j < n_operands; j++) 2135 if (j == i 2136 /* We don't want process insides of match_operator and 2137 match_parallel because otherwise we would process 2138 their operands once again generating a wrong 2139 code. */ 2140 || curr_static_id->operand[j].is_operator) 2141 continue; 2142 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) 2143 || (curr_alt_matches[i] == j && curr_alt_match_win[i])) 2144 continue; 2145 /* If we don't reload j-th operand, check conflicts. */ 2146 else if ((curr_alt_win[j] || curr_alt_match_win[j]) 2147 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) 2148 { 2149 if (first_conflict_j < 0) 2150 first_conflict_j = j; 2151 last_conflict_j = j; 2152 } 2153 if (last_conflict_j < 0) 2154 continue; 2155 /* If earlyclobber operand conflicts with another 2156 non-matching operand which is actually the same register 2157 as the earlyclobber operand, it is better to reload the 2158 another operand as an operand matching the earlyclobber 2159 operand can be also the same. */ 2160 if (first_conflict_j == last_conflict_j 2161 && operand_reg[last_conflict_j] 2162 != NULL_RTX && ! curr_alt_match_win[last_conflict_j] 2163 && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j])) 2164 { 2165 curr_alt_win[last_conflict_j] = false; 2166 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] 2167 = last_conflict_j; 2168 losers++; 2169 /* Early clobber was already reflected in REJECT. */ 2170 lra_assert (reject > 0); 2171 reject--; 2172 overall += LRA_LOSER_COST_FACTOR - 1; 2173 } 2174 else 2175 { 2176 /* We need to reload early clobbered register and the 2177 matched registers. */ 2178 for (j = 0; j < n_operands; j++) 2179 if (curr_alt_matches[j] == i) 2180 { 2181 curr_alt_match_win[j] = false; 2182 losers++; 2183 overall += LRA_LOSER_COST_FACTOR; 2184 } 2185 if (! curr_alt_match_win[i]) 2186 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; 2187 else 2188 { 2189 /* Remember pseudos used for match reloads are never 2190 inherited. */ 2191 lra_assert (curr_alt_matches[i] >= 0); 2192 curr_alt_win[curr_alt_matches[i]] = false; 2193 } 2194 curr_alt_win[i] = curr_alt_match_win[i] = false; 2195 losers++; 2196 /* Early clobber was already reflected in REJECT. */ 2197 lra_assert (reject > 0); 2198 reject--; 2199 overall += LRA_LOSER_COST_FACTOR - 1; 2200 } 2201 } 2202 if (lra_dump_file != NULL) 2203 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", 2204 nalt, overall, losers, reload_nregs); 2205 2206 /* If this alternative can be made to work by reloading, and it 2207 needs less reloading than the others checked so far, record 2208 it as the chosen goal for reloading. */ 2209 if ((best_losers != 0 && losers == 0) 2210 || (((best_losers == 0 && losers == 0) 2211 || (best_losers != 0 && losers != 0)) 2212 && (best_overall > overall 2213 || (best_overall == overall 2214 /* If the cost of the reloads is the same, 2215 prefer alternative which requires minimal 2216 number of reload regs. */ 2217 && (reload_nregs < best_reload_nregs 2218 || (reload_nregs == best_reload_nregs 2219 && (best_reload_sum < reload_sum 2220 || (best_reload_sum == reload_sum 2221 && nalt < goal_alt_number)))))))) 2222 { 2223 for (nop = 0; nop < n_operands; nop++) 2224 { 2225 goal_alt_win[nop] = curr_alt_win[nop]; 2226 goal_alt_match_win[nop] = curr_alt_match_win[nop]; 2227 goal_alt_matches[nop] = curr_alt_matches[nop]; 2228 goal_alt[nop] = curr_alt[nop]; 2229 goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; 2230 } 2231 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; 2232 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) 2233 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; 2234 goal_alt_swapped = curr_swapped; 2235 best_overall = overall; 2236 best_losers = losers; 2237 best_reload_nregs = reload_nregs; 2238 best_reload_sum = reload_sum; 2239 goal_alt_number = nalt; 2240 } 2241 if (losers == 0) 2242 /* Everything is satisfied. Do not process alternatives 2243 anymore. */ 2244 break; 2245 fail: 2246 ; 2247 } 2248 return ok_p; 2249 } 2250 2251 /* Return 1 if ADDR is a valid memory address for mode MODE in address 2252 space AS, and check that each pseudo has the proper kind of hard 2253 reg. */ 2254 static int 2255 valid_address_p (enum machine_mode mode ATTRIBUTE_UNUSED, 2256 rtx addr, addr_space_t as) 2257 { 2258 #ifdef GO_IF_LEGITIMATE_ADDRESS 2259 lra_assert (ADDR_SPACE_GENERIC_P (as)); 2260 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); 2261 return 0; 2262 2263 win: 2264 return 1; 2265 #else 2266 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); 2267 #endif 2268 } 2269 2270 /* Return whether address AD is valid. */ 2271 2272 static bool 2273 valid_address_p (struct address_info *ad) 2274 { 2275 /* Some ports do not check displacements for eliminable registers, 2276 so we replace them temporarily with the elimination target. */ 2277 rtx saved_base_reg = NULL_RTX; 2278 rtx saved_index_reg = NULL_RTX; 2279 rtx *base_term = strip_subreg (ad->base_term); 2280 rtx *index_term = strip_subreg (ad->index_term); 2281 if (base_term != NULL) 2282 { 2283 saved_base_reg = *base_term; 2284 lra_eliminate_reg_if_possible (base_term); 2285 if (ad->base_term2 != NULL) 2286 *ad->base_term2 = *ad->base_term; 2287 } 2288 if (index_term != NULL) 2289 { 2290 saved_index_reg = *index_term; 2291 lra_eliminate_reg_if_possible (index_term); 2292 } 2293 bool ok_p = valid_address_p (ad->mode, *ad->outer, ad->as); 2294 if (saved_base_reg != NULL_RTX) 2295 { 2296 *base_term = saved_base_reg; 2297 if (ad->base_term2 != NULL) 2298 *ad->base_term2 = *ad->base_term; 2299 } 2300 if (saved_index_reg != NULL_RTX) 2301 *index_term = saved_index_reg; 2302 return ok_p; 2303 } 2304 2305 /* Make reload base reg + disp from address AD. Return the new pseudo. */ 2306 static rtx 2307 base_plus_disp_to_reg (struct address_info *ad) 2308 { 2309 enum reg_class cl; 2310 rtx new_reg; 2311 2312 lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term); 2313 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, 2314 get_index_code (ad)); 2315 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, 2316 cl, "base + disp"); 2317 lra_emit_add (new_reg, *ad->base_term, *ad->disp_term); 2318 return new_reg; 2319 } 2320 2321 /* Return true if we can add a displacement to address AD, even if that 2322 makes the address invalid. The fix-up code requires any new address 2323 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ 2324 static bool 2325 can_add_disp_p (struct address_info *ad) 2326 { 2327 return (!ad->autoinc_p 2328 && ad->segment == NULL 2329 && ad->base == ad->base_term 2330 && ad->disp == ad->disp_term); 2331 } 2332 2333 /* Make equiv substitution in address AD. Return true if a substitution 2334 was made. */ 2335 static bool 2336 equiv_address_substitution (struct address_info *ad) 2337 { 2338 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; 2339 HOST_WIDE_INT disp, scale; 2340 bool change_p; 2341 2342 base_term = strip_subreg (ad->base_term); 2343 if (base_term == NULL) 2344 base_reg = new_base_reg = NULL_RTX; 2345 else 2346 { 2347 base_reg = *base_term; 2348 new_base_reg = get_equiv_substitution (base_reg); 2349 } 2350 index_term = strip_subreg (ad->index_term); 2351 if (index_term == NULL) 2352 index_reg = new_index_reg = NULL_RTX; 2353 else 2354 { 2355 index_reg = *index_term; 2356 new_index_reg = get_equiv_substitution (index_reg); 2357 } 2358 if (base_reg == new_base_reg && index_reg == new_index_reg) 2359 return false; 2360 disp = 0; 2361 change_p = false; 2362 if (lra_dump_file != NULL) 2363 { 2364 fprintf (lra_dump_file, "Changing address in insn %d ", 2365 INSN_UID (curr_insn)); 2366 dump_value_slim (lra_dump_file, *ad->outer, 1); 2367 } 2368 if (base_reg != new_base_reg) 2369 { 2370 if (REG_P (new_base_reg)) 2371 { 2372 *base_term = new_base_reg; 2373 change_p = true; 2374 } 2375 else if (GET_CODE (new_base_reg) == PLUS 2376 && REG_P (XEXP (new_base_reg, 0)) 2377 && CONST_INT_P (XEXP (new_base_reg, 1)) 2378 && can_add_disp_p (ad)) 2379 { 2380 disp += INTVAL (XEXP (new_base_reg, 1)); 2381 *base_term = XEXP (new_base_reg, 0); 2382 change_p = true; 2383 } 2384 if (ad->base_term2 != NULL) 2385 *ad->base_term2 = *ad->base_term; 2386 } 2387 if (index_reg != new_index_reg) 2388 { 2389 if (REG_P (new_index_reg)) 2390 { 2391 *index_term = new_index_reg; 2392 change_p = true; 2393 } 2394 else if (GET_CODE (new_index_reg) == PLUS 2395 && REG_P (XEXP (new_index_reg, 0)) 2396 && CONST_INT_P (XEXP (new_index_reg, 1)) 2397 && can_add_disp_p (ad) 2398 && (scale = get_index_scale (ad))) 2399 { 2400 disp += INTVAL (XEXP (new_index_reg, 1)) * scale; 2401 *index_term = XEXP (new_index_reg, 0); 2402 change_p = true; 2403 } 2404 } 2405 if (disp != 0) 2406 { 2407 if (ad->disp != NULL) 2408 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); 2409 else 2410 { 2411 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); 2412 update_address (ad); 2413 } 2414 change_p = true; 2415 } 2416 if (lra_dump_file != NULL) 2417 { 2418 if (! change_p) 2419 fprintf (lra_dump_file, " -- no change\n"); 2420 else 2421 { 2422 fprintf (lra_dump_file, " on equiv "); 2423 dump_value_slim (lra_dump_file, *ad->outer, 1); 2424 fprintf (lra_dump_file, "\n"); 2425 } 2426 } 2427 return change_p; 2428 } 2429 2430 /* Major function to make reloads for an address in operand NOP. 2431 The supported cases are: 2432 2433 1) an address that existed before LRA started, at which point it must 2434 have been valid. These addresses are subject to elimination and 2435 may have become invalid due to the elimination offset being out 2436 of range. 2437 2438 2) an address created by forcing a constant to memory (force_const_to_mem). 2439 The initial form of these addresses might not be valid, and it is this 2440 function's job to make them valid. 2441 2442 3) a frame address formed from a register and a (possibly zero) 2443 constant offset. As above, these addresses might not be valid 2444 and this function must make them so. 2445 2446 Add reloads to the lists *BEFORE and *AFTER. We might need to add 2447 reloads to *AFTER because of inc/dec, {pre, post} modify in the 2448 address. Return true for any RTL change. */ 2449 static bool 2450 process_address (int nop, rtx *before, rtx *after) 2451 { 2452 struct address_info ad; 2453 rtx new_reg; 2454 rtx op = *curr_id->operand_loc[nop]; 2455 const char *constraint = curr_static_id->operand[nop].constraint; 2456 bool change_p; 2457 2458 if (constraint[0] == 'p' 2459 || EXTRA_ADDRESS_CONSTRAINT (constraint[0], constraint)) 2460 decompose_lea_address (&ad, curr_id->operand_loc[nop]); 2461 else if (MEM_P (op)) 2462 decompose_mem_address (&ad, op); 2463 else if (GET_CODE (op) == SUBREG 2464 && MEM_P (SUBREG_REG (op))) 2465 decompose_mem_address (&ad, SUBREG_REG (op)); 2466 else 2467 return false; 2468 change_p = equiv_address_substitution (&ad); 2469 if (ad.base_term != NULL 2470 && (process_addr_reg 2471 (ad.base_term, before, 2472 (ad.autoinc_p 2473 && !(REG_P (*ad.base_term) 2474 && find_regno_note (curr_insn, REG_DEAD, 2475 REGNO (*ad.base_term)) != NULL_RTX) 2476 ? after : NULL), 2477 base_reg_class (ad.mode, ad.as, ad.base_outer_code, 2478 get_index_code (&ad))))) 2479 { 2480 change_p = true; 2481 if (ad.base_term2 != NULL) 2482 *ad.base_term2 = *ad.base_term; 2483 } 2484 if (ad.index_term != NULL 2485 && process_addr_reg (ad.index_term, before, NULL, INDEX_REG_CLASS)) 2486 change_p = true; 2487 2488 /* There are three cases where the shape of *AD.INNER may now be invalid: 2489 2490 1) the original address was valid, but either elimination or 2491 equiv_address_substitution applied a displacement that made 2492 it invalid. 2493 2494 2) the address is an invalid symbolic address created by 2495 force_const_to_mem. 2496 2497 3) the address is a frame address with an invalid offset. 2498 2499 All these cases involve a displacement and a non-autoinc address, 2500 so there is no point revalidating other types. */ 2501 if (ad.disp == NULL || ad.autoinc_p || valid_address_p (&ad)) 2502 return change_p; 2503 2504 /* Any index existed before LRA started, so we can assume that the 2505 presence and shape of the index is valid. */ 2506 push_to_sequence (*before); 2507 gcc_assert (ad.segment == NULL); 2508 gcc_assert (ad.disp == ad.disp_term); 2509 if (ad.base == NULL) 2510 { 2511 if (ad.index == NULL) 2512 { 2513 int code = -1; 2514 enum reg_class cl = base_reg_class (ad.mode, ad.as, 2515 SCRATCH, SCRATCH); 2516 rtx disp = *ad.disp; 2517 2518 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); 2519 #ifdef HAVE_lo_sum 2520 { 2521 rtx insn; 2522 rtx last = get_last_insn (); 2523 2524 /* disp => lo_sum (new_base, disp), case (2) above. */ 2525 insn = emit_insn (gen_rtx_SET 2526 (VOIDmode, new_reg, 2527 gen_rtx_HIGH (Pmode, copy_rtx (disp)))); 2528 code = recog_memoized (insn); 2529 if (code >= 0) 2530 { 2531 *ad.disp = gen_rtx_LO_SUM (Pmode, new_reg, disp); 2532 if (! valid_address_p (ad.mode, *ad.outer, ad.as)) 2533 { 2534 *ad.disp = disp; 2535 code = -1; 2536 } 2537 } 2538 if (code < 0) 2539 delete_insns_since (last); 2540 } 2541 #endif 2542 if (code < 0) 2543 { 2544 /* disp => new_base, case (2) above. */ 2545 lra_emit_move (new_reg, disp); 2546 *ad.disp = new_reg; 2547 } 2548 } 2549 else 2550 { 2551 /* index * scale + disp => new base + index * scale, 2552 case (1) above. */ 2553 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, 2554 GET_CODE (*ad.index)); 2555 2556 lra_assert (INDEX_REG_CLASS != NO_REGS); 2557 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); 2558 lra_emit_move (new_reg, *ad.disp); 2559 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), 2560 new_reg, *ad.index); 2561 } 2562 } 2563 else if (ad.index == NULL) 2564 { 2565 /* base + disp => new base, cases (1) and (3) above. */ 2566 /* Another option would be to reload the displacement into an 2567 index register. However, postreload has code to optimize 2568 address reloads that have the same base and different 2569 displacements, so reloading into an index register would 2570 not necessarily be a win. */ 2571 new_reg = base_plus_disp_to_reg (&ad); 2572 *ad.inner = new_reg; 2573 } 2574 else 2575 { 2576 /* base + scale * index + disp => new base + scale * index, 2577 case (1) above. */ 2578 new_reg = base_plus_disp_to_reg (&ad); 2579 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), 2580 new_reg, *ad.index); 2581 } 2582 *before = get_insns (); 2583 end_sequence (); 2584 return true; 2585 } 2586 2587 /* Emit insns to reload VALUE into a new register. VALUE is an 2588 auto-increment or auto-decrement RTX whose operand is a register or 2589 memory location; so reloading involves incrementing that location. 2590 IN is either identical to VALUE, or some cheaper place to reload 2591 value being incremented/decremented from. 2592 2593 INC_AMOUNT is the number to increment or decrement by (always 2594 positive and ignored for POST_MODIFY/PRE_MODIFY). 2595 2596 Return pseudo containing the result. */ 2597 static rtx 2598 emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount) 2599 { 2600 /* REG or MEM to be copied and incremented. */ 2601 rtx incloc = XEXP (value, 0); 2602 /* Nonzero if increment after copying. */ 2603 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC 2604 || GET_CODE (value) == POST_MODIFY); 2605 rtx last; 2606 rtx inc; 2607 rtx add_insn; 2608 int code; 2609 rtx real_in = in == value ? incloc : in; 2610 rtx result; 2611 bool plus_p = true; 2612 2613 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) 2614 { 2615 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS 2616 || GET_CODE (XEXP (value, 1)) == MINUS); 2617 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); 2618 plus_p = GET_CODE (XEXP (value, 1)) == PLUS; 2619 inc = XEXP (XEXP (value, 1), 1); 2620 } 2621 else 2622 { 2623 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) 2624 inc_amount = -inc_amount; 2625 2626 inc = GEN_INT (inc_amount); 2627 } 2628 2629 if (! post && REG_P (incloc)) 2630 result = incloc; 2631 else 2632 result = lra_create_new_reg (GET_MODE (value), value, new_rclass, 2633 "INC/DEC result"); 2634 2635 if (real_in != result) 2636 { 2637 /* First copy the location to the result register. */ 2638 lra_assert (REG_P (result)); 2639 emit_insn (gen_move_insn (result, real_in)); 2640 } 2641 2642 /* We suppose that there are insns to add/sub with the constant 2643 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the 2644 old reload worked with this assumption. If the assumption 2645 becomes wrong, we should use approach in function 2646 base_plus_disp_to_reg. */ 2647 if (in == value) 2648 { 2649 /* See if we can directly increment INCLOC. */ 2650 last = get_last_insn (); 2651 add_insn = emit_insn (plus_p 2652 ? gen_add2_insn (incloc, inc) 2653 : gen_sub2_insn (incloc, inc)); 2654 2655 code = recog_memoized (add_insn); 2656 if (code >= 0) 2657 { 2658 if (! post && result != incloc) 2659 emit_insn (gen_move_insn (result, incloc)); 2660 return result; 2661 } 2662 delete_insns_since (last); 2663 } 2664 2665 /* If couldn't do the increment directly, must increment in RESULT. 2666 The way we do this depends on whether this is pre- or 2667 post-increment. For pre-increment, copy INCLOC to the reload 2668 register, increment it there, then save back. */ 2669 if (! post) 2670 { 2671 if (real_in != result) 2672 emit_insn (gen_move_insn (result, real_in)); 2673 if (plus_p) 2674 emit_insn (gen_add2_insn (result, inc)); 2675 else 2676 emit_insn (gen_sub2_insn (result, inc)); 2677 if (result != incloc) 2678 emit_insn (gen_move_insn (incloc, result)); 2679 } 2680 else 2681 { 2682 /* Post-increment. 2683 2684 Because this might be a jump insn or a compare, and because 2685 RESULT may not be available after the insn in an input 2686 reload, we must do the incrementing before the insn being 2687 reloaded for. 2688 2689 We have already copied IN to RESULT. Increment the copy in 2690 RESULT, save that back, then decrement RESULT so it has 2691 the original value. */ 2692 if (plus_p) 2693 emit_insn (gen_add2_insn (result, inc)); 2694 else 2695 emit_insn (gen_sub2_insn (result, inc)); 2696 emit_insn (gen_move_insn (incloc, result)); 2697 /* Restore non-modified value for the result. We prefer this 2698 way because it does not require an additional hard 2699 register. */ 2700 if (plus_p) 2701 { 2702 if (CONST_INT_P (inc)) 2703 emit_insn (gen_add2_insn (result, GEN_INT (-INTVAL (inc)))); 2704 else 2705 emit_insn (gen_sub2_insn (result, inc)); 2706 } 2707 else 2708 emit_insn (gen_add2_insn (result, inc)); 2709 } 2710 return result; 2711 } 2712 2713 /* Swap operands NOP and NOP + 1. */ 2714 static inline void 2715 swap_operands (int nop) 2716 { 2717 enum machine_mode mode = curr_operand_mode[nop]; 2718 curr_operand_mode[nop] = curr_operand_mode[nop + 1]; 2719 curr_operand_mode[nop + 1] = mode; 2720 rtx x = *curr_id->operand_loc[nop]; 2721 *curr_id->operand_loc[nop] = *curr_id->operand_loc[nop + 1]; 2722 *curr_id->operand_loc[nop + 1] = x; 2723 /* Swap the duplicates too. */ 2724 lra_update_dup (curr_id, nop); 2725 lra_update_dup (curr_id, nop + 1); 2726 } 2727 2728 /* Main entry point of the constraint code: search the body of the 2729 current insn to choose the best alternative. It is mimicking insn 2730 alternative cost calculation model of former reload pass. That is 2731 because machine descriptions were written to use this model. This 2732 model can be changed in future. Make commutative operand exchange 2733 if it is chosen. 2734 2735 Return true if some RTL changes happened during function call. */ 2736 static bool 2737 curr_insn_transform (void) 2738 { 2739 int i, j, k; 2740 int n_operands; 2741 int n_alternatives; 2742 int commutative; 2743 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; 2744 signed char match_inputs[MAX_RECOG_OPERANDS + 1]; 2745 rtx before, after; 2746 bool alt_p = false; 2747 /* Flag that the insn has been changed through a transformation. */ 2748 bool change_p; 2749 bool sec_mem_p; 2750 #ifdef SECONDARY_MEMORY_NEEDED 2751 bool use_sec_mem_p; 2752 #endif 2753 int max_regno_before; 2754 int reused_alternative_num; 2755 2756 no_input_reloads_p = no_output_reloads_p = false; 2757 goal_alt_number = -1; 2758 2759 if (check_and_process_move (&change_p, &sec_mem_p)) 2760 return change_p; 2761 2762 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output 2763 reloads; neither are insns that SET cc0. Insns that use CC0 are 2764 not allowed to have any input reloads. */ 2765 if (JUMP_P (curr_insn) || CALL_P (curr_insn)) 2766 no_output_reloads_p = true; 2767 2768 #ifdef HAVE_cc0 2769 if (reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) 2770 no_input_reloads_p = true; 2771 if (reg_set_p (cc0_rtx, PATTERN (curr_insn))) 2772 no_output_reloads_p = true; 2773 #endif 2774 2775 n_operands = curr_static_id->n_operands; 2776 n_alternatives = curr_static_id->n_alternatives; 2777 2778 /* Just return "no reloads" if insn has no operands with 2779 constraints. */ 2780 if (n_operands == 0 || n_alternatives == 0) 2781 return false; 2782 2783 max_regno_before = max_reg_num (); 2784 2785 for (i = 0; i < n_operands; i++) 2786 { 2787 goal_alt_matched[i][0] = -1; 2788 goal_alt_matches[i] = -1; 2789 } 2790 2791 commutative = curr_static_id->commutative; 2792 2793 /* Now see what we need for pseudos that didn't get hard regs or got 2794 the wrong kind of hard reg. For this, we must consider all the 2795 operands together against the register constraints. */ 2796 2797 best_losers = best_overall = INT_MAX; 2798 best_reload_sum = 0; 2799 2800 curr_swapped = false; 2801 goal_alt_swapped = false; 2802 2803 /* Make equivalence substitution and memory subreg elimination 2804 before address processing because an address legitimacy can 2805 depend on memory mode. */ 2806 for (i = 0; i < n_operands; i++) 2807 { 2808 rtx op = *curr_id->operand_loc[i]; 2809 rtx subst, old = op; 2810 bool op_change_p = false; 2811 2812 if (GET_CODE (old) == SUBREG) 2813 old = SUBREG_REG (old); 2814 subst = get_equiv_substitution (old); 2815 if (subst != old) 2816 { 2817 subst = copy_rtx (subst); 2818 lra_assert (REG_P (old)); 2819 if (GET_CODE (op) == SUBREG) 2820 SUBREG_REG (op) = subst; 2821 else 2822 *curr_id->operand_loc[i] = subst; 2823 if (lra_dump_file != NULL) 2824 { 2825 fprintf (lra_dump_file, 2826 "Changing pseudo %d in operand %i of insn %u on equiv ", 2827 REGNO (old), i, INSN_UID (curr_insn)); 2828 dump_value_slim (lra_dump_file, subst, 1); 2829 fprintf (lra_dump_file, "\n"); 2830 } 2831 op_change_p = change_p = true; 2832 } 2833 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) 2834 { 2835 change_p = true; 2836 lra_update_dup (curr_id, i); 2837 } 2838 } 2839 2840 /* Reload address registers and displacements. We do it before 2841 finding an alternative because of memory constraints. */ 2842 before = after = NULL_RTX; 2843 for (i = 0; i < n_operands; i++) 2844 if (! curr_static_id->operand[i].is_operator 2845 && process_address (i, &before, &after)) 2846 { 2847 change_p = true; 2848 lra_update_dup (curr_id, i); 2849 } 2850 2851 if (change_p) 2852 /* If we've changed the instruction then any alternative that 2853 we chose previously may no longer be valid. */ 2854 lra_set_used_insn_alternative (curr_insn, -1); 2855 2856 try_swapped: 2857 2858 reused_alternative_num = curr_id->used_insn_alternative; 2859 if (lra_dump_file != NULL && reused_alternative_num >= 0) 2860 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", 2861 reused_alternative_num, INSN_UID (curr_insn)); 2862 2863 if (process_alt_operands (reused_alternative_num)) 2864 alt_p = true; 2865 2866 /* If insn is commutative (it's safe to exchange a certain pair of 2867 operands) then we need to try each alternative twice, the second 2868 time matching those two operands as if we had exchanged them. To 2869 do this, really exchange them in operands. 2870 2871 If we have just tried the alternatives the second time, return 2872 operands to normal and drop through. */ 2873 2874 if (reused_alternative_num < 0 && commutative >= 0) 2875 { 2876 curr_swapped = !curr_swapped; 2877 if (curr_swapped) 2878 { 2879 swap_operands (commutative); 2880 goto try_swapped; 2881 } 2882 else 2883 swap_operands (commutative); 2884 } 2885 2886 if (! alt_p && ! sec_mem_p) 2887 { 2888 /* No alternative works with reloads?? */ 2889 if (INSN_CODE (curr_insn) >= 0) 2890 fatal_insn ("unable to generate reloads for:", curr_insn); 2891 error_for_asm (curr_insn, 2892 "inconsistent operand constraints in an %<asm%>"); 2893 /* Avoid further trouble with this insn. */ 2894 PATTERN (curr_insn) = gen_rtx_USE (VOIDmode, const0_rtx); 2895 lra_invalidate_insn_data (curr_insn); 2896 return true; 2897 } 2898 2899 /* If the best alternative is with operands 1 and 2 swapped, swap 2900 them. Update the operand numbers of any reloads already 2901 pushed. */ 2902 2903 if (goal_alt_swapped) 2904 { 2905 if (lra_dump_file != NULL) 2906 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", 2907 INSN_UID (curr_insn)); 2908 2909 /* Swap the duplicates too. */ 2910 swap_operands (commutative); 2911 change_p = true; 2912 } 2913 2914 #ifdef SECONDARY_MEMORY_NEEDED 2915 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined 2916 too conservatively. So we use the secondary memory only if there 2917 is no any alternative without reloads. */ 2918 use_sec_mem_p = false; 2919 if (! alt_p) 2920 use_sec_mem_p = true; 2921 else if (sec_mem_p) 2922 { 2923 for (i = 0; i < n_operands; i++) 2924 if (! goal_alt_win[i] && ! goal_alt_match_win[i]) 2925 break; 2926 use_sec_mem_p = i < n_operands; 2927 } 2928 2929 if (use_sec_mem_p) 2930 { 2931 rtx new_reg, src, dest, rld; 2932 enum machine_mode sec_mode, rld_mode; 2933 2934 lra_assert (sec_mem_p); 2935 lra_assert (curr_static_id->operand[0].type == OP_OUT 2936 && curr_static_id->operand[1].type == OP_IN); 2937 dest = *curr_id->operand_loc[0]; 2938 src = *curr_id->operand_loc[1]; 2939 rld = (GET_MODE_SIZE (GET_MODE (dest)) <= GET_MODE_SIZE (GET_MODE (src)) 2940 ? dest : src); 2941 rld_mode = GET_MODE (rld); 2942 #ifdef SECONDARY_MEMORY_NEEDED_MODE 2943 sec_mode = SECONDARY_MEMORY_NEEDED_MODE (rld_mode); 2944 #else 2945 sec_mode = rld_mode; 2946 #endif 2947 new_reg = lra_create_new_reg (sec_mode, NULL_RTX, 2948 NO_REGS, "secondary"); 2949 /* If the mode is changed, it should be wider. */ 2950 lra_assert (GET_MODE_SIZE (sec_mode) >= GET_MODE_SIZE (rld_mode)); 2951 if (sec_mode != rld_mode) 2952 { 2953 /* If the target says specifically to use another mode for 2954 secondary memory moves we can not reuse the original 2955 insn. */ 2956 after = emit_spill_move (false, new_reg, dest); 2957 lra_process_new_insns (curr_insn, NULL_RTX, after, 2958 "Inserting the sec. move"); 2959 before = emit_spill_move (true, new_reg, src); 2960 lra_process_new_insns (curr_insn, before, NULL_RTX, "Changing on"); 2961 lra_set_insn_deleted (curr_insn); 2962 } 2963 else if (dest == rld) 2964 { 2965 *curr_id->operand_loc[0] = new_reg; 2966 after = emit_spill_move (false, new_reg, dest); 2967 lra_process_new_insns (curr_insn, NULL_RTX, after, 2968 "Inserting the sec. move"); 2969 } 2970 else 2971 { 2972 *curr_id->operand_loc[1] = new_reg; 2973 before = emit_spill_move (true, new_reg, src); 2974 lra_process_new_insns (curr_insn, before, NULL_RTX, 2975 "Inserting the sec. move"); 2976 } 2977 lra_update_insn_regno_info (curr_insn); 2978 return true; 2979 } 2980 #endif 2981 2982 lra_assert (goal_alt_number >= 0); 2983 lra_set_used_insn_alternative (curr_insn, goal_alt_number); 2984 2985 if (lra_dump_file != NULL) 2986 { 2987 const char *p; 2988 2989 fprintf (lra_dump_file, " Choosing alt %d in insn %u:", 2990 goal_alt_number, INSN_UID (curr_insn)); 2991 for (i = 0; i < n_operands; i++) 2992 { 2993 p = (curr_static_id->operand_alternative 2994 [goal_alt_number * n_operands + i].constraint); 2995 if (*p == '\0') 2996 continue; 2997 fprintf (lra_dump_file, " (%d) ", i); 2998 for (; *p != '\0' && *p != ',' && *p != '#'; p++) 2999 fputc (*p, lra_dump_file); 3000 } 3001 if (INSN_CODE (curr_insn) >= 0 3002 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) 3003 fprintf (lra_dump_file, " {%s}", p); 3004 fprintf (lra_dump_file, "\n"); 3005 } 3006 3007 /* Right now, for any pair of operands I and J that are required to 3008 match, with J < I, goal_alt_matches[I] is J. Add I to 3009 goal_alt_matched[J]. */ 3010 3011 for (i = 0; i < n_operands; i++) 3012 if ((j = goal_alt_matches[i]) >= 0) 3013 { 3014 for (k = 0; goal_alt_matched[j][k] >= 0; k++) 3015 ; 3016 /* We allow matching one output operand and several input 3017 operands. */ 3018 lra_assert (k == 0 3019 || (curr_static_id->operand[j].type == OP_OUT 3020 && curr_static_id->operand[i].type == OP_IN 3021 && (curr_static_id->operand 3022 [goal_alt_matched[j][0]].type == OP_IN))); 3023 goal_alt_matched[j][k] = i; 3024 goal_alt_matched[j][k + 1] = -1; 3025 } 3026 3027 for (i = 0; i < n_operands; i++) 3028 goal_alt_win[i] |= goal_alt_match_win[i]; 3029 3030 /* Any constants that aren't allowed and can't be reloaded into 3031 registers are here changed into memory references. */ 3032 for (i = 0; i < n_operands; i++) 3033 if (goal_alt_win[i]) 3034 { 3035 int regno; 3036 enum reg_class new_class; 3037 rtx reg = *curr_id->operand_loc[i]; 3038 3039 if (GET_CODE (reg) == SUBREG) 3040 reg = SUBREG_REG (reg); 3041 3042 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) 3043 { 3044 bool ok_p = in_class_p (reg, goal_alt[i], &new_class); 3045 3046 if (new_class != NO_REGS && get_reg_class (regno) != new_class) 3047 { 3048 lra_assert (ok_p); 3049 change_class (regno, new_class, " Change", true); 3050 } 3051 } 3052 } 3053 else 3054 { 3055 const char *constraint; 3056 char c; 3057 rtx op = *curr_id->operand_loc[i]; 3058 rtx subreg = NULL_RTX; 3059 enum machine_mode mode = curr_operand_mode[i]; 3060 3061 if (GET_CODE (op) == SUBREG) 3062 { 3063 subreg = op; 3064 op = SUBREG_REG (op); 3065 mode = GET_MODE (op); 3066 } 3067 3068 if (CONST_POOL_OK_P (mode, op) 3069 && ((targetm.preferred_reload_class 3070 (op, (enum reg_class) goal_alt[i]) == NO_REGS) 3071 || no_input_reloads_p)) 3072 { 3073 rtx tem = force_const_mem (mode, op); 3074 3075 change_p = true; 3076 if (subreg != NULL_RTX) 3077 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); 3078 3079 *curr_id->operand_loc[i] = tem; 3080 lra_update_dup (curr_id, i); 3081 process_address (i, &before, &after); 3082 3083 /* If the alternative accepts constant pool refs directly 3084 there will be no reload needed at all. */ 3085 if (subreg != NULL_RTX) 3086 continue; 3087 /* Skip alternatives before the one requested. */ 3088 constraint = (curr_static_id->operand_alternative 3089 [goal_alt_number * n_operands + i].constraint); 3090 for (; 3091 (c = *constraint) && c != ',' && c != '#'; 3092 constraint += CONSTRAINT_LEN (c, constraint)) 3093 { 3094 if (c == TARGET_MEM_CONSTRAINT || c == 'o') 3095 break; 3096 #ifdef EXTRA_CONSTRAINT_STR 3097 if (EXTRA_MEMORY_CONSTRAINT (c, constraint) 3098 && EXTRA_CONSTRAINT_STR (tem, c, constraint)) 3099 break; 3100 #endif 3101 } 3102 if (c == '\0' || c == ',' || c == '#') 3103 continue; 3104 3105 goal_alt_win[i] = true; 3106 } 3107 } 3108 3109 for (i = 0; i < n_operands; i++) 3110 { 3111 rtx old, new_reg; 3112 rtx op = *curr_id->operand_loc[i]; 3113 3114 if (goal_alt_win[i]) 3115 { 3116 if (goal_alt[i] == NO_REGS 3117 && REG_P (op) 3118 /* When we assign NO_REGS it means that we will not 3119 assign a hard register to the scratch pseudo by 3120 assigment pass and the scratch pseudo will be 3121 spilled. Spilled scratch pseudos are transformed 3122 back to scratches at the LRA end. */ 3123 && lra_former_scratch_operand_p (curr_insn, i)) 3124 { 3125 int regno = REGNO (op); 3126 change_class (regno, NO_REGS, " Change", true); 3127 if (lra_get_regno_hard_regno (regno) >= 0) 3128 /* We don't have to mark all insn affected by the 3129 spilled pseudo as there is only one such insn, the 3130 current one. */ 3131 reg_renumber[regno] = -1; 3132 } 3133 continue; 3134 } 3135 3136 /* Operands that match previous ones have already been handled. */ 3137 if (goal_alt_matches[i] >= 0) 3138 continue; 3139 3140 /* We should not have an operand with a non-offsettable address 3141 appearing where an offsettable address will do. It also may 3142 be a case when the address should be special in other words 3143 not a general one (e.g. it needs no index reg). */ 3144 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) 3145 { 3146 enum reg_class rclass; 3147 rtx *loc = &XEXP (op, 0); 3148 enum rtx_code code = GET_CODE (*loc); 3149 3150 push_to_sequence (before); 3151 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), 3152 MEM, SCRATCH); 3153 if (GET_RTX_CLASS (code) == RTX_AUTOINC) 3154 new_reg = emit_inc (rclass, *loc, *loc, 3155 /* This value does not matter for MODIFY. */ 3156 GET_MODE_SIZE (GET_MODE (op))); 3157 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, 3158 "offsetable address", &new_reg)) 3159 lra_emit_move (new_reg, *loc); 3160 before = get_insns (); 3161 end_sequence (); 3162 *loc = new_reg; 3163 lra_update_dup (curr_id, i); 3164 } 3165 else if (goal_alt_matched[i][0] == -1) 3166 { 3167 enum machine_mode mode; 3168 rtx reg, *loc; 3169 int hard_regno, byte; 3170 enum op_type type = curr_static_id->operand[i].type; 3171 3172 loc = curr_id->operand_loc[i]; 3173 mode = curr_operand_mode[i]; 3174 if (GET_CODE (*loc) == SUBREG) 3175 { 3176 reg = SUBREG_REG (*loc); 3177 byte = SUBREG_BYTE (*loc); 3178 if (REG_P (reg) 3179 /* Strict_low_part requires reload the register not 3180 the sub-register. */ 3181 && (curr_static_id->operand[i].strict_low 3182 || (GET_MODE_SIZE (mode) 3183 <= GET_MODE_SIZE (GET_MODE (reg)) 3184 && (hard_regno 3185 = get_try_hard_regno (REGNO (reg))) >= 0 3186 && (simplify_subreg_regno 3187 (hard_regno, 3188 GET_MODE (reg), byte, mode) < 0) 3189 && (goal_alt[i] == NO_REGS 3190 || (simplify_subreg_regno 3191 (ira_class_hard_regs[goal_alt[i]][0], 3192 GET_MODE (reg), byte, mode) >= 0))))) 3193 { 3194 loc = &SUBREG_REG (*loc); 3195 mode = GET_MODE (*loc); 3196 } 3197 } 3198 old = *loc; 3199 if (get_reload_reg (type, mode, old, goal_alt[i], "", &new_reg) 3200 && type != OP_OUT) 3201 { 3202 push_to_sequence (before); 3203 lra_emit_move (new_reg, old); 3204 before = get_insns (); 3205 end_sequence (); 3206 } 3207 *loc = new_reg; 3208 if (type != OP_IN 3209 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) 3210 { 3211 start_sequence (); 3212 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); 3213 emit_insn (after); 3214 after = get_insns (); 3215 end_sequence (); 3216 *loc = new_reg; 3217 } 3218 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) 3219 if (goal_alt_dont_inherit_ops[j] == i) 3220 { 3221 lra_set_regno_unique_value (REGNO (new_reg)); 3222 break; 3223 } 3224 lra_update_dup (curr_id, i); 3225 } 3226 else if (curr_static_id->operand[i].type == OP_IN 3227 && (curr_static_id->operand[goal_alt_matched[i][0]].type 3228 == OP_OUT)) 3229 { 3230 /* generate reloads for input and matched outputs. */ 3231 match_inputs[0] = i; 3232 match_inputs[1] = -1; 3233 match_reload (goal_alt_matched[i][0], match_inputs, 3234 goal_alt[i], &before, &after); 3235 } 3236 else if (curr_static_id->operand[i].type == OP_OUT 3237 && (curr_static_id->operand[goal_alt_matched[i][0]].type 3238 == OP_IN)) 3239 /* Generate reloads for output and matched inputs. */ 3240 match_reload (i, goal_alt_matched[i], goal_alt[i], &before, &after); 3241 else if (curr_static_id->operand[i].type == OP_IN 3242 && (curr_static_id->operand[goal_alt_matched[i][0]].type 3243 == OP_IN)) 3244 { 3245 /* Generate reloads for matched inputs. */ 3246 match_inputs[0] = i; 3247 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) 3248 match_inputs[j + 1] = k; 3249 match_inputs[j + 1] = -1; 3250 match_reload (-1, match_inputs, goal_alt[i], &before, &after); 3251 } 3252 else 3253 /* We must generate code in any case when function 3254 process_alt_operands decides that it is possible. */ 3255 gcc_unreachable (); 3256 } 3257 if (before != NULL_RTX || after != NULL_RTX 3258 || max_regno_before != max_reg_num ()) 3259 change_p = true; 3260 if (change_p) 3261 { 3262 lra_update_operator_dups (curr_id); 3263 /* Something changes -- process the insn. */ 3264 lra_update_insn_regno_info (curr_insn); 3265 } 3266 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); 3267 return change_p; 3268 } 3269 3270 /* Return true if X is in LIST. */ 3271 static bool 3272 in_list_p (rtx x, rtx list) 3273 { 3274 for (; list != NULL_RTX; list = XEXP (list, 1)) 3275 if (XEXP (list, 0) == x) 3276 return true; 3277 return false; 3278 } 3279 3280 /* Return true if X contains an allocatable hard register (if 3281 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ 3282 static bool 3283 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) 3284 { 3285 int i, j; 3286 const char *fmt; 3287 enum rtx_code code; 3288 3289 code = GET_CODE (x); 3290 if (REG_P (x)) 3291 { 3292 int regno = REGNO (x); 3293 HARD_REG_SET alloc_regs; 3294 3295 if (hard_reg_p) 3296 { 3297 if (regno >= FIRST_PSEUDO_REGISTER) 3298 regno = lra_get_regno_hard_regno (regno); 3299 if (regno < 0) 3300 return false; 3301 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); 3302 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); 3303 } 3304 else 3305 { 3306 if (regno < FIRST_PSEUDO_REGISTER) 3307 return false; 3308 if (! spilled_p) 3309 return true; 3310 return lra_get_regno_hard_regno (regno) < 0; 3311 } 3312 } 3313 fmt = GET_RTX_FORMAT (code); 3314 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3315 { 3316 if (fmt[i] == 'e') 3317 { 3318 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) 3319 return true; 3320 } 3321 else if (fmt[i] == 'E') 3322 { 3323 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3324 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) 3325 return true; 3326 } 3327 } 3328 return false; 3329 } 3330 3331 /* Process all regs in location *LOC and change them on equivalent 3332 substitution. Return true if any change was done. */ 3333 static bool 3334 loc_equivalence_change_p (rtx *loc) 3335 { 3336 rtx subst, reg, x = *loc; 3337 bool result = false; 3338 enum rtx_code code = GET_CODE (x); 3339 const char *fmt; 3340 int i, j; 3341 3342 if (code == SUBREG) 3343 { 3344 reg = SUBREG_REG (x); 3345 if ((subst = get_equiv_substitution (reg)) != reg 3346 && GET_MODE (subst) == VOIDmode) 3347 { 3348 /* We cannot reload debug location. Simplify subreg here 3349 while we know the inner mode. */ 3350 *loc = simplify_gen_subreg (GET_MODE (x), subst, 3351 GET_MODE (reg), SUBREG_BYTE (x)); 3352 return true; 3353 } 3354 } 3355 if (code == REG && (subst = get_equiv_substitution (x)) != x) 3356 { 3357 *loc = subst; 3358 return true; 3359 } 3360 3361 /* Scan all the operand sub-expressions. */ 3362 fmt = GET_RTX_FORMAT (code); 3363 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3364 { 3365 if (fmt[i] == 'e') 3366 result = loc_equivalence_change_p (&XEXP (x, i)) || result; 3367 else if (fmt[i] == 'E') 3368 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3369 result 3370 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; 3371 } 3372 return result; 3373 } 3374 3375 /* Similar to loc_equivalence_change_p, but for use as 3376 simplify_replace_fn_rtx callback. */ 3377 static rtx 3378 loc_equivalence_callback (rtx loc, const_rtx, void *) 3379 { 3380 if (!REG_P (loc)) 3381 return NULL_RTX; 3382 3383 rtx subst = get_equiv_substitution (loc); 3384 if (subst != loc) 3385 return subst; 3386 3387 return NULL_RTX; 3388 } 3389 3390 /* Maximum number of generated reload insns per an insn. It is for 3391 preventing this pass cycling in a bug case. */ 3392 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS 3393 3394 /* The current iteration number of this LRA pass. */ 3395 int lra_constraint_iter; 3396 3397 /* The current iteration number of this LRA pass after the last spill 3398 pass. */ 3399 int lra_constraint_iter_after_spill; 3400 3401 /* True if we substituted equiv which needs checking register 3402 allocation correctness because the equivalent value contains 3403 allocatable hard registers or when we restore multi-register 3404 pseudo. */ 3405 bool lra_risky_transformations_p; 3406 3407 /* Return true if REGNO is referenced in more than one block. */ 3408 static bool 3409 multi_block_pseudo_p (int regno) 3410 { 3411 basic_block bb = NULL; 3412 unsigned int uid; 3413 bitmap_iterator bi; 3414 3415 if (regno < FIRST_PSEUDO_REGISTER) 3416 return false; 3417 3418 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) 3419 if (bb == NULL) 3420 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); 3421 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) 3422 return true; 3423 return false; 3424 } 3425 3426 /* Return true if LIST contains a deleted insn. */ 3427 static bool 3428 contains_deleted_insn_p (rtx list) 3429 { 3430 for (; list != NULL_RTX; list = XEXP (list, 1)) 3431 if (NOTE_P (XEXP (list, 0)) 3432 && NOTE_KIND (XEXP (list, 0)) == NOTE_INSN_DELETED) 3433 return true; 3434 return false; 3435 } 3436 3437 /* Return true if X contains a pseudo dying in INSN. */ 3438 static bool 3439 dead_pseudo_p (rtx x, rtx insn) 3440 { 3441 int i, j; 3442 const char *fmt; 3443 enum rtx_code code; 3444 3445 if (REG_P (x)) 3446 return (insn != NULL_RTX 3447 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); 3448 code = GET_CODE (x); 3449 fmt = GET_RTX_FORMAT (code); 3450 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3451 { 3452 if (fmt[i] == 'e') 3453 { 3454 if (dead_pseudo_p (XEXP (x, i), insn)) 3455 return true; 3456 } 3457 else if (fmt[i] == 'E') 3458 { 3459 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3460 if (dead_pseudo_p (XVECEXP (x, i, j), insn)) 3461 return true; 3462 } 3463 } 3464 return false; 3465 } 3466 3467 /* Return true if INSN contains a dying pseudo in INSN right hand 3468 side. */ 3469 static bool 3470 insn_rhs_dead_pseudo_p (rtx insn) 3471 { 3472 rtx set = single_set (insn); 3473 3474 gcc_assert (set != NULL); 3475 return dead_pseudo_p (SET_SRC (set), insn); 3476 } 3477 3478 /* Return true if any init insn of REGNO contains a dying pseudo in 3479 insn right hand side. */ 3480 static bool 3481 init_insn_rhs_dead_pseudo_p (int regno) 3482 { 3483 rtx insns = ira_reg_equiv[regno].init_insns; 3484 3485 if (insns == NULL) 3486 return false; 3487 if (INSN_P (insns)) 3488 return insn_rhs_dead_pseudo_p (insns); 3489 for (; insns != NULL_RTX; insns = XEXP (insns, 1)) 3490 if (insn_rhs_dead_pseudo_p (XEXP (insns, 0))) 3491 return true; 3492 return false; 3493 } 3494 3495 /* Entry function of LRA constraint pass. Return true if the 3496 constraint pass did change the code. */ 3497 bool 3498 lra_constraints (bool first_p) 3499 { 3500 bool changed_p; 3501 int i, hard_regno, new_insns_num; 3502 unsigned int min_len, new_min_len, uid; 3503 rtx set, x, reg, dest_reg; 3504 basic_block last_bb; 3505 bitmap_head equiv_insn_bitmap; 3506 bitmap_iterator bi; 3507 3508 lra_constraint_iter++; 3509 if (lra_dump_file != NULL) 3510 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", 3511 lra_constraint_iter); 3512 lra_constraint_iter_after_spill++; 3513 if (lra_constraint_iter_after_spill > LRA_MAX_CONSTRAINT_ITERATION_NUMBER) 3514 internal_error 3515 ("Maximum number of LRA constraint passes is achieved (%d)\n", 3516 LRA_MAX_CONSTRAINT_ITERATION_NUMBER); 3517 changed_p = false; 3518 lra_risky_transformations_p = false; 3519 new_insn_uid_start = get_max_uid (); 3520 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); 3521 bitmap_initialize (&equiv_insn_bitmap, ®_obstack); 3522 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 3523 if (lra_reg_info[i].nrefs != 0) 3524 { 3525 ira_reg_equiv[i].profitable_p = true; 3526 reg = regno_reg_rtx[i]; 3527 if ((hard_regno = lra_get_regno_hard_regno (i)) >= 0) 3528 { 3529 int j, nregs; 3530 3531 nregs = hard_regno_nregs[hard_regno][lra_reg_info[i].biggest_mode]; 3532 for (j = 0; j < nregs; j++) 3533 df_set_regs_ever_live (hard_regno + j, true); 3534 } 3535 else if ((x = get_equiv_substitution (reg)) != reg) 3536 { 3537 bool pseudo_p = contains_reg_p (x, false, false); 3538 rtx set, insn; 3539 3540 /* After RTL transformation, we can not guarantee that 3541 pseudo in the substitution was not reloaded which might 3542 make equivalence invalid. For example, in reverse 3543 equiv of p0 3544 3545 p0 <- ... 3546 ... 3547 equiv_mem <- p0 3548 3549 the memory address register was reloaded before the 2nd 3550 insn. */ 3551 if ((! first_p && pseudo_p) 3552 /* We don't use DF for compilation speed sake. So it 3553 is problematic to update live info when we use an 3554 equivalence containing pseudos in more than one 3555 BB. */ 3556 || (pseudo_p && multi_block_pseudo_p (i)) 3557 /* If an init insn was deleted for some reason, cancel 3558 the equiv. We could update the equiv insns after 3559 transformations including an equiv insn deletion 3560 but it is not worthy as such cases are extremely 3561 rare. */ 3562 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) 3563 /* If it is not a reverse equivalence, we check that a 3564 pseudo in rhs of the init insn is not dying in the 3565 insn. Otherwise, the live info at the beginning of 3566 the corresponding BB might be wrong after we 3567 removed the insn. When the equiv can be a 3568 constant, the right hand side of the init insn can 3569 be a pseudo. */ 3570 || (! ((insn = ira_reg_equiv[i].init_insns) != NULL_RTX 3571 && INSN_P (insn) 3572 && (set = single_set (insn)) != NULL_RTX 3573 && REG_P (SET_DEST (set)) 3574 && (int) REGNO (SET_DEST (set)) == i) 3575 && init_insn_rhs_dead_pseudo_p (i)) 3576 /* Prevent access beyond equivalent memory for 3577 paradoxical subregs. */ 3578 || (MEM_P (x) 3579 && (GET_MODE_SIZE (lra_reg_info[i].biggest_mode) 3580 > GET_MODE_SIZE (GET_MODE (x))))) 3581 ira_reg_equiv[i].defined_p = false; 3582 if (contains_reg_p (x, false, true)) 3583 ira_reg_equiv[i].profitable_p = false; 3584 if (get_equiv_substitution (reg) != reg) 3585 bitmap_ior_into (&equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); 3586 } 3587 } 3588 /* We should add all insns containing pseudos which should be 3589 substituted by their equivalences. */ 3590 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap, 0, uid, bi) 3591 lra_push_insn_by_uid (uid); 3592 lra_eliminate (false); 3593 min_len = lra_insn_stack_length (); 3594 new_insns_num = 0; 3595 last_bb = NULL; 3596 changed_p = false; 3597 while ((new_min_len = lra_insn_stack_length ()) != 0) 3598 { 3599 curr_insn = lra_pop_insn (); 3600 --new_min_len; 3601 curr_bb = BLOCK_FOR_INSN (curr_insn); 3602 if (curr_bb != last_bb) 3603 { 3604 last_bb = curr_bb; 3605 bb_reload_num = lra_curr_reload_num; 3606 } 3607 if (min_len > new_min_len) 3608 { 3609 min_len = new_min_len; 3610 new_insns_num = 0; 3611 } 3612 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) 3613 internal_error 3614 ("Max. number of generated reload insns per insn is achieved (%d)\n", 3615 MAX_RELOAD_INSNS_NUMBER); 3616 new_insns_num++; 3617 if (DEBUG_INSN_P (curr_insn)) 3618 { 3619 /* We need to check equivalence in debug insn and change 3620 pseudo to the equivalent value if necessary. */ 3621 curr_id = lra_get_insn_recog_data (curr_insn); 3622 if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn))) 3623 { 3624 rtx old = *curr_id->operand_loc[0]; 3625 *curr_id->operand_loc[0] 3626 = simplify_replace_fn_rtx (old, NULL_RTX, 3627 loc_equivalence_callback, NULL); 3628 if (old != *curr_id->operand_loc[0]) 3629 { 3630 lra_update_insn_regno_info (curr_insn); 3631 changed_p = true; 3632 } 3633 } 3634 } 3635 else if (INSN_P (curr_insn)) 3636 { 3637 if ((set = single_set (curr_insn)) != NULL_RTX) 3638 { 3639 dest_reg = SET_DEST (set); 3640 /* The equivalence pseudo could be set up as SUBREG in a 3641 case when it is a call restore insn in a mode 3642 different from the pseudo mode. */ 3643 if (GET_CODE (dest_reg) == SUBREG) 3644 dest_reg = SUBREG_REG (dest_reg); 3645 if ((REG_P (dest_reg) 3646 && (x = get_equiv_substitution (dest_reg)) != dest_reg 3647 /* Remove insns which set up a pseudo whose value 3648 can not be changed. Such insns might be not in 3649 init_insns because we don't update equiv data 3650 during insn transformations. 3651 3652 As an example, let suppose that a pseudo got 3653 hard register and on the 1st pass was not 3654 changed to equivalent constant. We generate an 3655 additional insn setting up the pseudo because of 3656 secondary memory movement. Then the pseudo is 3657 spilled and we use the equiv constant. In this 3658 case we should remove the additional insn and 3659 this insn is not init_insns list. */ 3660 && (! MEM_P (x) || MEM_READONLY_P (x) 3661 || in_list_p (curr_insn, 3662 ira_reg_equiv 3663 [REGNO (dest_reg)].init_insns))) 3664 || (((x = get_equiv_substitution (SET_SRC (set))) 3665 != SET_SRC (set)) 3666 && in_list_p (curr_insn, 3667 ira_reg_equiv 3668 [REGNO (SET_SRC (set))].init_insns))) 3669 { 3670 /* This is equiv init insn of pseudo which did not get a 3671 hard register -- remove the insn. */ 3672 if (lra_dump_file != NULL) 3673 { 3674 fprintf (lra_dump_file, 3675 " Removing equiv init insn %i (freq=%d)\n", 3676 INSN_UID (curr_insn), 3677 BLOCK_FOR_INSN (curr_insn)->frequency); 3678 dump_insn_slim (lra_dump_file, curr_insn); 3679 } 3680 if (contains_reg_p (x, true, false)) 3681 lra_risky_transformations_p = true; 3682 lra_set_insn_deleted (curr_insn); 3683 continue; 3684 } 3685 } 3686 curr_id = lra_get_insn_recog_data (curr_insn); 3687 curr_static_id = curr_id->insn_static_data; 3688 init_curr_insn_input_reloads (); 3689 init_curr_operand_mode (); 3690 if (curr_insn_transform ()) 3691 changed_p = true; 3692 /* Check non-transformed insns too for equiv change as USE 3693 or CLOBBER don't need reloads but can contain pseudos 3694 being changed on their equivalences. */ 3695 else if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn)) 3696 && loc_equivalence_change_p (&PATTERN (curr_insn))) 3697 { 3698 lra_update_insn_regno_info (curr_insn); 3699 changed_p = true; 3700 } 3701 } 3702 } 3703 bitmap_clear (&equiv_insn_bitmap); 3704 /* If we used a new hard regno, changed_p should be true because the 3705 hard reg is assigned to a new pseudo. */ 3706 #ifdef ENABLE_CHECKING 3707 if (! changed_p) 3708 { 3709 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 3710 if (lra_reg_info[i].nrefs != 0 3711 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) 3712 { 3713 int j, nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (i)]; 3714 3715 for (j = 0; j < nregs; j++) 3716 lra_assert (df_regs_ever_live_p (hard_regno + j)); 3717 } 3718 } 3719 #endif 3720 return changed_p; 3721 } 3722 3723 /* Initiate the LRA constraint pass. It is done once per 3724 function. */ 3725 void 3726 lra_constraints_init (void) 3727 { 3728 } 3729 3730 /* Finalize the LRA constraint pass. It is done once per 3731 function. */ 3732 void 3733 lra_constraints_finish (void) 3734 { 3735 } 3736 3737 3738 3739 /* This page contains code to do inheritance/split 3740 transformations. */ 3741 3742 /* Number of reloads passed so far in current EBB. */ 3743 static int reloads_num; 3744 3745 /* Number of calls passed so far in current EBB. */ 3746 static int calls_num; 3747 3748 /* Current reload pseudo check for validity of elements in 3749 USAGE_INSNS. */ 3750 static int curr_usage_insns_check; 3751 3752 /* Info about last usage of registers in EBB to do inheritance/split 3753 transformation. Inheritance transformation is done from a spilled 3754 pseudo and split transformations from a hard register or a pseudo 3755 assigned to a hard register. */ 3756 struct usage_insns 3757 { 3758 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member 3759 value INSNS is valid. The insns is chain of optional debug insns 3760 and a finishing non-debug insn using the corresponding reg. */ 3761 int check; 3762 /* Value of global reloads_num at the last insn in INSNS. */ 3763 int reloads_num; 3764 /* Value of global reloads_nums at the last insn in INSNS. */ 3765 int calls_num; 3766 /* It can be true only for splitting. And it means that the restore 3767 insn should be put after insn given by the following member. */ 3768 bool after_p; 3769 /* Next insns in the current EBB which use the original reg and the 3770 original reg value is not changed between the current insn and 3771 the next insns. In order words, e.g. for inheritance, if we need 3772 to use the original reg value again in the next insns we can try 3773 to use the value in a hard register from a reload insn of the 3774 current insn. */ 3775 rtx insns; 3776 }; 3777 3778 /* Map: regno -> corresponding pseudo usage insns. */ 3779 static struct usage_insns *usage_insns; 3780 3781 static void 3782 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) 3783 { 3784 usage_insns[regno].check = curr_usage_insns_check; 3785 usage_insns[regno].insns = insn; 3786 usage_insns[regno].reloads_num = reloads_num; 3787 usage_insns[regno].calls_num = calls_num; 3788 usage_insns[regno].after_p = after_p; 3789 } 3790 3791 /* The function is used to form list REGNO usages which consists of 3792 optional debug insns finished by a non-debug insn using REGNO. 3793 RELOADS_NUM is current number of reload insns processed so far. */ 3794 static void 3795 add_next_usage_insn (int regno, rtx insn, int reloads_num) 3796 { 3797 rtx next_usage_insns; 3798 3799 if (usage_insns[regno].check == curr_usage_insns_check 3800 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX 3801 && DEBUG_INSN_P (insn)) 3802 { 3803 /* Check that we did not add the debug insn yet. */ 3804 if (next_usage_insns != insn 3805 && (GET_CODE (next_usage_insns) != INSN_LIST 3806 || XEXP (next_usage_insns, 0) != insn)) 3807 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, 3808 next_usage_insns); 3809 } 3810 else if (NONDEBUG_INSN_P (insn)) 3811 setup_next_usage_insn (regno, insn, reloads_num, false); 3812 else 3813 usage_insns[regno].check = 0; 3814 } 3815 3816 /* Replace all references to register OLD_REGNO in *LOC with pseudo 3817 register NEW_REG. Return true if any change was made. */ 3818 static bool 3819 substitute_pseudo (rtx *loc, int old_regno, rtx new_reg) 3820 { 3821 rtx x = *loc; 3822 bool result = false; 3823 enum rtx_code code; 3824 const char *fmt; 3825 int i, j; 3826 3827 if (x == NULL_RTX) 3828 return false; 3829 3830 code = GET_CODE (x); 3831 if (code == REG && (int) REGNO (x) == old_regno) 3832 { 3833 enum machine_mode mode = GET_MODE (*loc); 3834 enum machine_mode inner_mode = GET_MODE (new_reg); 3835 3836 if (mode != inner_mode) 3837 { 3838 if (GET_MODE_SIZE (mode) >= GET_MODE_SIZE (inner_mode) 3839 || ! SCALAR_INT_MODE_P (inner_mode)) 3840 new_reg = gen_rtx_SUBREG (mode, new_reg, 0); 3841 else 3842 new_reg = gen_lowpart_SUBREG (mode, new_reg); 3843 } 3844 *loc = new_reg; 3845 return true; 3846 } 3847 3848 /* Scan all the operand sub-expressions. */ 3849 fmt = GET_RTX_FORMAT (code); 3850 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3851 { 3852 if (fmt[i] == 'e') 3853 { 3854 if (substitute_pseudo (&XEXP (x, i), old_regno, new_reg)) 3855 result = true; 3856 } 3857 else if (fmt[i] == 'E') 3858 { 3859 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3860 if (substitute_pseudo (&XVECEXP (x, i, j), old_regno, new_reg)) 3861 result = true; 3862 } 3863 } 3864 return result; 3865 } 3866 3867 /* Return first non-debug insn in list USAGE_INSNS. */ 3868 static rtx 3869 skip_usage_debug_insns (rtx usage_insns) 3870 { 3871 rtx insn; 3872 3873 /* Skip debug insns. */ 3874 for (insn = usage_insns; 3875 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; 3876 insn = XEXP (insn, 1)) 3877 ; 3878 return insn; 3879 } 3880 3881 /* Return true if we need secondary memory moves for insn in 3882 USAGE_INSNS after inserting inherited pseudo of class INHER_CL 3883 into the insn. */ 3884 static bool 3885 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, 3886 rtx usage_insns ATTRIBUTE_UNUSED) 3887 { 3888 #ifndef SECONDARY_MEMORY_NEEDED 3889 return false; 3890 #else 3891 rtx insn, set, dest; 3892 enum reg_class cl; 3893 3894 if (inher_cl == ALL_REGS 3895 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) 3896 return false; 3897 lra_assert (INSN_P (insn)); 3898 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) 3899 return false; 3900 dest = SET_DEST (set); 3901 if (! REG_P (dest)) 3902 return false; 3903 lra_assert (inher_cl != NO_REGS); 3904 cl = get_reg_class (REGNO (dest)); 3905 return (cl != NO_REGS && cl != ALL_REGS 3906 && SECONDARY_MEMORY_NEEDED (inher_cl, cl, GET_MODE (dest))); 3907 #endif 3908 } 3909 3910 /* Registers involved in inheritance/split in the current EBB 3911 (inheritance/split pseudos and original registers). */ 3912 static bitmap_head check_only_regs; 3913 3914 /* Do inheritance transformations for insn INSN, which defines (if 3915 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which 3916 instruction in the EBB next uses ORIGINAL_REGNO; it has the same 3917 form as the "insns" field of usage_insns. Return true if we 3918 succeed in such transformation. 3919 3920 The transformations look like: 3921 3922 p <- ... i <- ... 3923 ... p <- i (new insn) 3924 ... => 3925 <- ... p ... <- ... i ... 3926 or 3927 ... i <- p (new insn) 3928 <- ... p ... <- ... i ... 3929 ... => 3930 <- ... p ... <- ... i ... 3931 where p is a spilled original pseudo and i is a new inheritance pseudo. 3932 3933 3934 The inheritance pseudo has the smallest class of two classes CL and 3935 class of ORIGINAL REGNO. */ 3936 static bool 3937 inherit_reload_reg (bool def_p, int original_regno, 3938 enum reg_class cl, rtx insn, rtx next_usage_insns) 3939 { 3940 enum reg_class rclass = lra_get_allocno_class (original_regno); 3941 rtx original_reg = regno_reg_rtx[original_regno]; 3942 rtx new_reg, new_insns, usage_insn; 3943 3944 lra_assert (! usage_insns[original_regno].after_p); 3945 if (lra_dump_file != NULL) 3946 fprintf (lra_dump_file, 3947 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); 3948 if (! ira_reg_classes_intersect_p[cl][rclass]) 3949 { 3950 if (lra_dump_file != NULL) 3951 { 3952 fprintf (lra_dump_file, 3953 " Rejecting inheritance for %d " 3954 "because of disjoint classes %s and %s\n", 3955 original_regno, reg_class_names[cl], 3956 reg_class_names[rclass]); 3957 fprintf (lra_dump_file, 3958 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 3959 } 3960 return false; 3961 } 3962 if ((ira_class_subset_p[cl][rclass] && cl != rclass) 3963 /* We don't use a subset of two classes because it can be 3964 NO_REGS. This transformation is still profitable in most 3965 cases even if the classes are not intersected as register 3966 move is probably cheaper than a memory load. */ 3967 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) 3968 { 3969 if (lra_dump_file != NULL) 3970 fprintf (lra_dump_file, " Use smallest class of %s and %s\n", 3971 reg_class_names[cl], reg_class_names[rclass]); 3972 3973 rclass = cl; 3974 } 3975 if (check_secondary_memory_needed_p (rclass, next_usage_insns)) 3976 { 3977 /* Reject inheritance resulting in secondary memory moves. 3978 Otherwise, there is a danger in LRA cycling. Also such 3979 transformation will be unprofitable. */ 3980 if (lra_dump_file != NULL) 3981 { 3982 rtx insn = skip_usage_debug_insns (next_usage_insns); 3983 rtx set = single_set (insn); 3984 3985 lra_assert (set != NULL_RTX); 3986 3987 rtx dest = SET_DEST (set); 3988 3989 lra_assert (REG_P (dest)); 3990 fprintf (lra_dump_file, 3991 " Rejecting inheritance for insn %d(%s)<-%d(%s) " 3992 "as secondary mem is needed\n", 3993 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], 3994 original_regno, reg_class_names[rclass]); 3995 fprintf (lra_dump_file, 3996 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 3997 } 3998 return false; 3999 } 4000 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, 4001 rclass, "inheritance"); 4002 start_sequence (); 4003 if (def_p) 4004 emit_move_insn (original_reg, new_reg); 4005 else 4006 emit_move_insn (new_reg, original_reg); 4007 new_insns = get_insns (); 4008 end_sequence (); 4009 if (NEXT_INSN (new_insns) != NULL_RTX) 4010 { 4011 if (lra_dump_file != NULL) 4012 { 4013 fprintf (lra_dump_file, 4014 " Rejecting inheritance %d->%d " 4015 "as it results in 2 or more insns:\n", 4016 original_regno, REGNO (new_reg)); 4017 dump_rtl_slim (lra_dump_file, new_insns, NULL_RTX, -1, 0); 4018 fprintf (lra_dump_file, 4019 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 4020 } 4021 return false; 4022 } 4023 substitute_pseudo (&insn, original_regno, new_reg); 4024 lra_update_insn_regno_info (insn); 4025 if (! def_p) 4026 /* We now have a new usage insn for original regno. */ 4027 setup_next_usage_insn (original_regno, new_insns, reloads_num, false); 4028 if (lra_dump_file != NULL) 4029 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", 4030 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); 4031 lra_reg_info[REGNO (new_reg)].restore_regno = original_regno; 4032 bitmap_set_bit (&check_only_regs, REGNO (new_reg)); 4033 bitmap_set_bit (&check_only_regs, original_regno); 4034 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); 4035 if (def_p) 4036 lra_process_new_insns (insn, NULL_RTX, new_insns, 4037 "Add original<-inheritance"); 4038 else 4039 lra_process_new_insns (insn, new_insns, NULL_RTX, 4040 "Add inheritance<-original"); 4041 while (next_usage_insns != NULL_RTX) 4042 { 4043 if (GET_CODE (next_usage_insns) != INSN_LIST) 4044 { 4045 usage_insn = next_usage_insns; 4046 lra_assert (NONDEBUG_INSN_P (usage_insn)); 4047 next_usage_insns = NULL; 4048 } 4049 else 4050 { 4051 usage_insn = XEXP (next_usage_insns, 0); 4052 lra_assert (DEBUG_INSN_P (usage_insn)); 4053 next_usage_insns = XEXP (next_usage_insns, 1); 4054 } 4055 substitute_pseudo (&usage_insn, original_regno, new_reg); 4056 lra_update_insn_regno_info (usage_insn); 4057 if (lra_dump_file != NULL) 4058 { 4059 fprintf (lra_dump_file, 4060 " Inheritance reuse change %d->%d (bb%d):\n", 4061 original_regno, REGNO (new_reg), 4062 BLOCK_FOR_INSN (usage_insn)->index); 4063 dump_insn_slim (lra_dump_file, usage_insn); 4064 } 4065 } 4066 if (lra_dump_file != NULL) 4067 fprintf (lra_dump_file, 4068 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 4069 return true; 4070 } 4071 4072 /* Return true if we need a caller save/restore for pseudo REGNO which 4073 was assigned to a hard register. */ 4074 static inline bool 4075 need_for_call_save_p (int regno) 4076 { 4077 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); 4078 return (usage_insns[regno].calls_num < calls_num 4079 && (overlaps_hard_reg_set_p 4080 (call_used_reg_set, 4081 PSEUDO_REGNO_MODE (regno), reg_renumber[regno]))); 4082 } 4083 4084 /* Global registers occuring in the current EBB. */ 4085 static bitmap_head ebb_global_regs; 4086 4087 /* Return true if we need a split for hard register REGNO or pseudo 4088 REGNO which was assigned to a hard register. 4089 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be 4090 used for reloads since the EBB end. It is an approximation of the 4091 used hard registers in the split range. The exact value would 4092 require expensive calculations. If we were aggressive with 4093 splitting because of the approximation, the split pseudo will save 4094 the same hard register assignment and will be removed in the undo 4095 pass. We still need the approximation because too aggressive 4096 splitting would result in too inaccurate cost calculation in the 4097 assignment pass because of too many generated moves which will be 4098 probably removed in the undo pass. */ 4099 static inline bool 4100 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) 4101 { 4102 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; 4103 4104 lra_assert (hard_regno >= 0); 4105 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) 4106 /* Don't split eliminable hard registers, otherwise we can 4107 split hard registers like hard frame pointer, which 4108 lives on BB start/end according to DF-infrastructure, 4109 when there is a pseudo assigned to the register and 4110 living in the same BB. */ 4111 && (regno >= FIRST_PSEUDO_REGISTER 4112 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) 4113 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) 4114 /* We need at least 2 reloads to make pseudo splitting 4115 profitable. We should provide hard regno splitting in 4116 any case to solve 1st insn scheduling problem when 4117 moving hard register definition up might result in 4118 impossibility to find hard register for reload pseudo of 4119 small register class. */ 4120 && (usage_insns[regno].reloads_num 4121 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 2) < reloads_num) 4122 && (regno < FIRST_PSEUDO_REGISTER 4123 /* For short living pseudos, spilling + inheritance can 4124 be considered a substitution for splitting. 4125 Therefore we do not splitting for local pseudos. It 4126 decreases also aggressiveness of splitting. The 4127 minimal number of references is chosen taking into 4128 account that for 2 references splitting has no sense 4129 as we can just spill the pseudo. */ 4130 || (regno >= FIRST_PSEUDO_REGISTER 4131 && lra_reg_info[regno].nrefs > 3 4132 && bitmap_bit_p (&ebb_global_regs, regno)))) 4133 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); 4134 } 4135 4136 /* Return class for the split pseudo created from original pseudo with 4137 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We 4138 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and 4139 results in no secondary memory movements. */ 4140 static enum reg_class 4141 choose_split_class (enum reg_class allocno_class, 4142 int hard_regno ATTRIBUTE_UNUSED, 4143 enum machine_mode mode ATTRIBUTE_UNUSED) 4144 { 4145 #ifndef SECONDARY_MEMORY_NEEDED 4146 return allocno_class; 4147 #else 4148 int i; 4149 enum reg_class cl, best_cl = NO_REGS; 4150 enum reg_class hard_reg_class ATTRIBUTE_UNUSED 4151 = REGNO_REG_CLASS (hard_regno); 4152 4153 if (! SECONDARY_MEMORY_NEEDED (allocno_class, allocno_class, mode) 4154 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) 4155 return allocno_class; 4156 for (i = 0; 4157 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; 4158 i++) 4159 if (! SECONDARY_MEMORY_NEEDED (cl, hard_reg_class, mode) 4160 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class, cl, mode) 4161 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) 4162 && (best_cl == NO_REGS 4163 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) 4164 best_cl = cl; 4165 return best_cl; 4166 #endif 4167 } 4168 4169 /* Do split transformations for insn INSN, which defines or uses 4170 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in 4171 the EBB next uses ORIGINAL_REGNO; it has the same form as the 4172 "insns" field of usage_insns. 4173 4174 The transformations look like: 4175 4176 p <- ... p <- ... 4177 ... s <- p (new insn -- save) 4178 ... => 4179 ... p <- s (new insn -- restore) 4180 <- ... p ... <- ... p ... 4181 or 4182 <- ... p ... <- ... p ... 4183 ... s <- p (new insn -- save) 4184 ... => 4185 ... p <- s (new insn -- restore) 4186 <- ... p ... <- ... p ... 4187 4188 where p is an original pseudo got a hard register or a hard 4189 register and s is a new split pseudo. The save is put before INSN 4190 if BEFORE_P is true. Return true if we succeed in such 4191 transformation. */ 4192 static bool 4193 split_reg (bool before_p, int original_regno, rtx insn, rtx next_usage_insns) 4194 { 4195 enum reg_class rclass; 4196 rtx original_reg; 4197 int hard_regno, nregs; 4198 rtx new_reg, save, restore, usage_insn; 4199 bool after_p; 4200 bool call_save_p; 4201 4202 if (original_regno < FIRST_PSEUDO_REGISTER) 4203 { 4204 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; 4205 hard_regno = original_regno; 4206 call_save_p = false; 4207 nregs = 1; 4208 } 4209 else 4210 { 4211 hard_regno = reg_renumber[original_regno]; 4212 nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (original_regno)]; 4213 rclass = lra_get_allocno_class (original_regno); 4214 original_reg = regno_reg_rtx[original_regno]; 4215 call_save_p = need_for_call_save_p (original_regno); 4216 } 4217 original_reg = regno_reg_rtx[original_regno]; 4218 lra_assert (hard_regno >= 0); 4219 if (lra_dump_file != NULL) 4220 fprintf (lra_dump_file, 4221 " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); 4222 if (call_save_p) 4223 { 4224 enum machine_mode sec_mode; 4225 4226 #ifdef SECONDARY_MEMORY_NEEDED_MODE 4227 sec_mode = SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (original_reg)); 4228 #else 4229 sec_mode = GET_MODE (original_reg); 4230 #endif 4231 new_reg = lra_create_new_reg (sec_mode, NULL_RTX, 4232 NO_REGS, "save"); 4233 } 4234 else 4235 { 4236 rclass = choose_split_class (rclass, hard_regno, 4237 GET_MODE (original_reg)); 4238 if (rclass == NO_REGS) 4239 { 4240 if (lra_dump_file != NULL) 4241 { 4242 fprintf (lra_dump_file, 4243 " Rejecting split of %d(%s): " 4244 "no good reg class for %d(%s)\n", 4245 original_regno, 4246 reg_class_names[lra_get_allocno_class (original_regno)], 4247 hard_regno, 4248 reg_class_names[REGNO_REG_CLASS (hard_regno)]); 4249 fprintf 4250 (lra_dump_file, 4251 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 4252 } 4253 return false; 4254 } 4255 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, 4256 rclass, "split"); 4257 reg_renumber[REGNO (new_reg)] = hard_regno; 4258 } 4259 save = emit_spill_move (true, new_reg, original_reg); 4260 if (NEXT_INSN (save) != NULL_RTX) 4261 { 4262 lra_assert (! call_save_p); 4263 if (lra_dump_file != NULL) 4264 { 4265 fprintf 4266 (lra_dump_file, 4267 " Rejecting split %d->%d resulting in > 2 %s save insns:\n", 4268 original_regno, REGNO (new_reg), call_save_p ? "call" : ""); 4269 dump_rtl_slim (lra_dump_file, save, NULL_RTX, -1, 0); 4270 fprintf (lra_dump_file, 4271 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 4272 } 4273 return false; 4274 } 4275 restore = emit_spill_move (false, new_reg, original_reg); 4276 if (NEXT_INSN (restore) != NULL_RTX) 4277 { 4278 lra_assert (! call_save_p); 4279 if (lra_dump_file != NULL) 4280 { 4281 fprintf (lra_dump_file, 4282 " Rejecting split %d->%d " 4283 "resulting in > 2 %s restore insns:\n", 4284 original_regno, REGNO (new_reg), call_save_p ? "call" : ""); 4285 dump_rtl_slim (lra_dump_file, restore, NULL_RTX, -1, 0); 4286 fprintf (lra_dump_file, 4287 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 4288 } 4289 return false; 4290 } 4291 after_p = usage_insns[original_regno].after_p; 4292 lra_reg_info[REGNO (new_reg)].restore_regno = original_regno; 4293 bitmap_set_bit (&check_only_regs, REGNO (new_reg)); 4294 bitmap_set_bit (&check_only_regs, original_regno); 4295 bitmap_set_bit (&lra_split_regs, REGNO (new_reg)); 4296 for (;;) 4297 { 4298 if (GET_CODE (next_usage_insns) != INSN_LIST) 4299 { 4300 usage_insn = next_usage_insns; 4301 break; 4302 } 4303 usage_insn = XEXP (next_usage_insns, 0); 4304 lra_assert (DEBUG_INSN_P (usage_insn)); 4305 next_usage_insns = XEXP (next_usage_insns, 1); 4306 substitute_pseudo (&usage_insn, original_regno, new_reg); 4307 lra_update_insn_regno_info (usage_insn); 4308 if (lra_dump_file != NULL) 4309 { 4310 fprintf (lra_dump_file, " Split reuse change %d->%d:\n", 4311 original_regno, REGNO (new_reg)); 4312 dump_insn_slim (lra_dump_file, usage_insn); 4313 } 4314 } 4315 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); 4316 lra_assert (usage_insn != insn || (after_p && before_p)); 4317 lra_process_new_insns (usage_insn, after_p ? NULL_RTX : restore, 4318 after_p ? restore : NULL_RTX, 4319 call_save_p 4320 ? "Add reg<-save" : "Add reg<-split"); 4321 lra_process_new_insns (insn, before_p ? save : NULL_RTX, 4322 before_p ? NULL_RTX : save, 4323 call_save_p 4324 ? "Add save<-reg" : "Add split<-reg"); 4325 if (nregs > 1) 4326 /* If we are trying to split multi-register. We should check 4327 conflicts on the next assignment sub-pass. IRA can allocate on 4328 sub-register levels, LRA do this on pseudos level right now and 4329 this discrepancy may create allocation conflicts after 4330 splitting. */ 4331 lra_risky_transformations_p = true; 4332 if (lra_dump_file != NULL) 4333 fprintf (lra_dump_file, 4334 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 4335 return true; 4336 } 4337 4338 /* Recognize that we need a split transformation for insn INSN, which 4339 defines or uses REGNO in its insn biggest MODE (we use it only if 4340 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains 4341 hard registers which might be used for reloads since the EBB end. 4342 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla 4343 uid before starting INSN processing. Return true if we succeed in 4344 such transformation. */ 4345 static bool 4346 split_if_necessary (int regno, enum machine_mode mode, 4347 HARD_REG_SET potential_reload_hard_regs, 4348 bool before_p, rtx insn, int max_uid) 4349 { 4350 bool res = false; 4351 int i, nregs = 1; 4352 rtx next_usage_insns; 4353 4354 if (regno < FIRST_PSEUDO_REGISTER) 4355 nregs = hard_regno_nregs[regno][mode]; 4356 for (i = 0; i < nregs; i++) 4357 if (usage_insns[regno + i].check == curr_usage_insns_check 4358 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX 4359 /* To avoid processing the register twice or more. */ 4360 && ((GET_CODE (next_usage_insns) != INSN_LIST 4361 && INSN_UID (next_usage_insns) < max_uid) 4362 || (GET_CODE (next_usage_insns) == INSN_LIST 4363 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) 4364 && need_for_split_p (potential_reload_hard_regs, regno + i) 4365 && split_reg (before_p, regno + i, insn, next_usage_insns)) 4366 res = true; 4367 return res; 4368 } 4369 4370 /* Check only registers living at the current program point in the 4371 current EBB. */ 4372 static bitmap_head live_regs; 4373 4374 /* Update live info in EBB given by its HEAD and TAIL insns after 4375 inheritance/split transformation. The function removes dead moves 4376 too. */ 4377 static void 4378 update_ebb_live_info (rtx head, rtx tail) 4379 { 4380 unsigned int j; 4381 int regno; 4382 bool live_p; 4383 rtx prev_insn, set; 4384 bool remove_p; 4385 basic_block last_bb, prev_bb, curr_bb; 4386 bitmap_iterator bi; 4387 struct lra_insn_reg *reg; 4388 edge e; 4389 edge_iterator ei; 4390 4391 last_bb = BLOCK_FOR_INSN (tail); 4392 prev_bb = NULL; 4393 for (curr_insn = tail; 4394 curr_insn != PREV_INSN (head); 4395 curr_insn = prev_insn) 4396 { 4397 prev_insn = PREV_INSN (curr_insn); 4398 /* We need to process empty blocks too. They contain 4399 NOTE_INSN_BASIC_BLOCK referring for the basic block. */ 4400 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) 4401 continue; 4402 curr_bb = BLOCK_FOR_INSN (curr_insn); 4403 if (curr_bb != prev_bb) 4404 { 4405 if (prev_bb != NULL) 4406 { 4407 /* Update df_get_live_in (prev_bb): */ 4408 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) 4409 if (bitmap_bit_p (&live_regs, j)) 4410 bitmap_set_bit (df_get_live_in (prev_bb), j); 4411 else 4412 bitmap_clear_bit (df_get_live_in (prev_bb), j); 4413 } 4414 if (curr_bb != last_bb) 4415 { 4416 /* Update df_get_live_out (curr_bb): */ 4417 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) 4418 { 4419 live_p = bitmap_bit_p (&live_regs, j); 4420 if (! live_p) 4421 FOR_EACH_EDGE (e, ei, curr_bb->succs) 4422 if (bitmap_bit_p (df_get_live_in (e->dest), j)) 4423 { 4424 live_p = true; 4425 break; 4426 } 4427 if (live_p) 4428 bitmap_set_bit (df_get_live_out (curr_bb), j); 4429 else 4430 bitmap_clear_bit (df_get_live_out (curr_bb), j); 4431 } 4432 } 4433 prev_bb = curr_bb; 4434 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); 4435 } 4436 if (! NONDEBUG_INSN_P (curr_insn)) 4437 continue; 4438 curr_id = lra_get_insn_recog_data (curr_insn); 4439 remove_p = false; 4440 if ((set = single_set (curr_insn)) != NULL_RTX && REG_P (SET_DEST (set)) 4441 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER 4442 && bitmap_bit_p (&check_only_regs, regno) 4443 && ! bitmap_bit_p (&live_regs, regno)) 4444 remove_p = true; 4445 /* See which defined values die here. */ 4446 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 4447 if (reg->type == OP_OUT && ! reg->subreg_p) 4448 bitmap_clear_bit (&live_regs, reg->regno); 4449 /* Mark each used value as live. */ 4450 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 4451 if (reg->type != OP_OUT 4452 && bitmap_bit_p (&check_only_regs, reg->regno)) 4453 bitmap_set_bit (&live_regs, reg->regno); 4454 /* It is quite important to remove dead move insns because it 4455 means removing dead store. We don't need to process them for 4456 constraints. */ 4457 if (remove_p) 4458 { 4459 if (lra_dump_file != NULL) 4460 { 4461 fprintf (lra_dump_file, " Removing dead insn:\n "); 4462 dump_insn_slim (lra_dump_file, curr_insn); 4463 } 4464 lra_set_insn_deleted (curr_insn); 4465 } 4466 } 4467 } 4468 4469 /* The structure describes info to do an inheritance for the current 4470 insn. We need to collect such info first before doing the 4471 transformations because the transformations change the insn 4472 internal representation. */ 4473 struct to_inherit 4474 { 4475 /* Original regno. */ 4476 int regno; 4477 /* Subsequent insns which can inherit original reg value. */ 4478 rtx insns; 4479 }; 4480 4481 /* Array containing all info for doing inheritance from the current 4482 insn. */ 4483 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; 4484 4485 /* Number elements in the previous array. */ 4486 static int to_inherit_num; 4487 4488 /* Add inheritance info REGNO and INSNS. Their meaning is described in 4489 structure to_inherit. */ 4490 static void 4491 add_to_inherit (int regno, rtx insns) 4492 { 4493 int i; 4494 4495 for (i = 0; i < to_inherit_num; i++) 4496 if (to_inherit[i].regno == regno) 4497 return; 4498 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); 4499 to_inherit[to_inherit_num].regno = regno; 4500 to_inherit[to_inherit_num++].insns = insns; 4501 } 4502 4503 /* Return the last non-debug insn in basic block BB, or the block begin 4504 note if none. */ 4505 static rtx 4506 get_last_insertion_point (basic_block bb) 4507 { 4508 rtx insn; 4509 4510 FOR_BB_INSNS_REVERSE (bb, insn) 4511 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) 4512 return insn; 4513 gcc_unreachable (); 4514 } 4515 4516 /* Set up RES by registers living on edges FROM except the edge (FROM, 4517 TO) or by registers set up in a jump insn in BB FROM. */ 4518 static void 4519 get_live_on_other_edges (basic_block from, basic_block to, bitmap res) 4520 { 4521 rtx last; 4522 struct lra_insn_reg *reg; 4523 edge e; 4524 edge_iterator ei; 4525 4526 lra_assert (to != NULL); 4527 bitmap_clear (res); 4528 FOR_EACH_EDGE (e, ei, from->succs) 4529 if (e->dest != to) 4530 bitmap_ior_into (res, df_get_live_in (e->dest)); 4531 last = get_last_insertion_point (from); 4532 if (! JUMP_P (last)) 4533 return; 4534 curr_id = lra_get_insn_recog_data (last); 4535 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 4536 if (reg->type != OP_IN) 4537 bitmap_set_bit (res, reg->regno); 4538 } 4539 4540 /* Used as a temporary results of some bitmap calculations. */ 4541 static bitmap_head temp_bitmap; 4542 4543 /* Do inheritance/split transformations in EBB starting with HEAD and 4544 finishing on TAIL. We process EBB insns in the reverse order. 4545 Return true if we did any inheritance/split transformation in the 4546 EBB. 4547 4548 We should avoid excessive splitting which results in worse code 4549 because of inaccurate cost calculations for spilling new split 4550 pseudos in such case. To achieve this we do splitting only if 4551 register pressure is high in given basic block and there are reload 4552 pseudos requiring hard registers. We could do more register 4553 pressure calculations at any given program point to avoid necessary 4554 splitting even more but it is to expensive and the current approach 4555 works well enough. */ 4556 static bool 4557 inherit_in_ebb (rtx head, rtx tail) 4558 { 4559 int i, src_regno, dst_regno, nregs; 4560 bool change_p, succ_p; 4561 rtx prev_insn, next_usage_insns, set, last_insn; 4562 enum reg_class cl; 4563 struct lra_insn_reg *reg; 4564 basic_block last_processed_bb, curr_bb = NULL; 4565 HARD_REG_SET potential_reload_hard_regs, live_hard_regs; 4566 bitmap to_process; 4567 unsigned int j; 4568 bitmap_iterator bi; 4569 bool head_p, after_p; 4570 4571 change_p = false; 4572 curr_usage_insns_check++; 4573 reloads_num = calls_num = 0; 4574 bitmap_clear (&check_only_regs); 4575 last_processed_bb = NULL; 4576 CLEAR_HARD_REG_SET (potential_reload_hard_regs); 4577 CLEAR_HARD_REG_SET (live_hard_regs); 4578 /* We don't process new insns generated in the loop. */ 4579 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) 4580 { 4581 prev_insn = PREV_INSN (curr_insn); 4582 if (BLOCK_FOR_INSN (curr_insn) != NULL) 4583 curr_bb = BLOCK_FOR_INSN (curr_insn); 4584 if (last_processed_bb != curr_bb) 4585 { 4586 /* We are at the end of BB. Add qualified living 4587 pseudos for potential splitting. */ 4588 to_process = df_get_live_out (curr_bb); 4589 if (last_processed_bb != NULL) 4590 { 4591 /* We are somewhere in the middle of EBB. */ 4592 get_live_on_other_edges (curr_bb, last_processed_bb, 4593 &temp_bitmap); 4594 to_process = &temp_bitmap; 4595 } 4596 last_processed_bb = curr_bb; 4597 last_insn = get_last_insertion_point (curr_bb); 4598 after_p = (! JUMP_P (last_insn) 4599 && (! CALL_P (last_insn) 4600 || (find_reg_note (last_insn, 4601 REG_NORETURN, NULL_RTX) == NULL_RTX 4602 && ! SIBLING_CALL_P (last_insn)))); 4603 REG_SET_TO_HARD_REG_SET (live_hard_regs, df_get_live_out (curr_bb)); 4604 IOR_HARD_REG_SET (live_hard_regs, eliminable_regset); 4605 IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); 4606 CLEAR_HARD_REG_SET (potential_reload_hard_regs); 4607 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) 4608 { 4609 if ((int) j >= lra_constraint_new_regno_start) 4610 break; 4611 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) 4612 { 4613 if (j < FIRST_PSEUDO_REGISTER) 4614 SET_HARD_REG_BIT (live_hard_regs, j); 4615 else 4616 add_to_hard_reg_set (&live_hard_regs, 4617 PSEUDO_REGNO_MODE (j), 4618 reg_renumber[j]); 4619 setup_next_usage_insn (j, last_insn, reloads_num, after_p); 4620 } 4621 } 4622 } 4623 src_regno = dst_regno = -1; 4624 if (NONDEBUG_INSN_P (curr_insn) 4625 && (set = single_set (curr_insn)) != NULL_RTX 4626 && REG_P (SET_DEST (set)) && REG_P (SET_SRC (set))) 4627 { 4628 src_regno = REGNO (SET_SRC (set)); 4629 dst_regno = REGNO (SET_DEST (set)); 4630 } 4631 if (src_regno < lra_constraint_new_regno_start 4632 && src_regno >= FIRST_PSEUDO_REGISTER 4633 && reg_renumber[src_regno] < 0 4634 && dst_regno >= lra_constraint_new_regno_start 4635 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) 4636 { 4637 /* 'reload_pseudo <- original_pseudo'. */ 4638 reloads_num++; 4639 succ_p = false; 4640 if (usage_insns[src_regno].check == curr_usage_insns_check 4641 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) 4642 succ_p = inherit_reload_reg (false, src_regno, cl, 4643 curr_insn, next_usage_insns); 4644 if (succ_p) 4645 change_p = true; 4646 else 4647 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); 4648 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 4649 IOR_HARD_REG_SET (potential_reload_hard_regs, 4650 reg_class_contents[cl]); 4651 } 4652 else if (src_regno >= lra_constraint_new_regno_start 4653 && dst_regno < lra_constraint_new_regno_start 4654 && dst_regno >= FIRST_PSEUDO_REGISTER 4655 && reg_renumber[dst_regno] < 0 4656 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS 4657 && usage_insns[dst_regno].check == curr_usage_insns_check 4658 && (next_usage_insns 4659 = usage_insns[dst_regno].insns) != NULL_RTX) 4660 { 4661 reloads_num++; 4662 /* 'original_pseudo <- reload_pseudo'. */ 4663 if (! JUMP_P (curr_insn) 4664 && inherit_reload_reg (true, dst_regno, cl, 4665 curr_insn, next_usage_insns)) 4666 change_p = true; 4667 /* Invalidate. */ 4668 usage_insns[dst_regno].check = 0; 4669 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 4670 IOR_HARD_REG_SET (potential_reload_hard_regs, 4671 reg_class_contents[cl]); 4672 } 4673 else if (INSN_P (curr_insn)) 4674 { 4675 int max_uid = get_max_uid (); 4676 4677 curr_id = lra_get_insn_recog_data (curr_insn); 4678 to_inherit_num = 0; 4679 /* Process insn definitions. */ 4680 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 4681 if (reg->type != OP_IN 4682 && (dst_regno = reg->regno) < lra_constraint_new_regno_start) 4683 { 4684 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT 4685 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p 4686 && usage_insns[dst_regno].check == curr_usage_insns_check 4687 && (next_usage_insns 4688 = usage_insns[dst_regno].insns) != NULL_RTX) 4689 { 4690 struct lra_insn_reg *r; 4691 4692 for (r = curr_id->regs; r != NULL; r = r->next) 4693 if (r->type != OP_OUT && r->regno == dst_regno) 4694 break; 4695 /* Don't do inheritance if the pseudo is also 4696 used in the insn. */ 4697 if (r == NULL) 4698 /* We can not do inheritance right now 4699 because the current insn reg info (chain 4700 regs) can change after that. */ 4701 add_to_inherit (dst_regno, next_usage_insns); 4702 } 4703 /* We can not process one reg twice here because of 4704 usage_insns invalidation. */ 4705 if ((dst_regno < FIRST_PSEUDO_REGISTER 4706 || reg_renumber[dst_regno] >= 0) 4707 && ! reg->subreg_p && reg->type == OP_OUT) 4708 { 4709 HARD_REG_SET s; 4710 4711 if (split_if_necessary (dst_regno, reg->biggest_mode, 4712 potential_reload_hard_regs, 4713 false, curr_insn, max_uid)) 4714 change_p = true; 4715 CLEAR_HARD_REG_SET (s); 4716 if (dst_regno < FIRST_PSEUDO_REGISTER) 4717 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); 4718 else 4719 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), 4720 reg_renumber[dst_regno]); 4721 AND_COMPL_HARD_REG_SET (live_hard_regs, s); 4722 } 4723 /* We should invalidate potential inheritance or 4724 splitting for the current insn usages to the next 4725 usage insns (see code below) as the output pseudo 4726 prevents this. */ 4727 if ((dst_regno >= FIRST_PSEUDO_REGISTER 4728 && reg_renumber[dst_regno] < 0) 4729 || (reg->type == OP_OUT && ! reg->subreg_p 4730 && (dst_regno < FIRST_PSEUDO_REGISTER 4731 || reg_renumber[dst_regno] >= 0))) 4732 { 4733 /* Invalidate. */ 4734 if (dst_regno >= FIRST_PSEUDO_REGISTER) 4735 usage_insns[dst_regno].check = 0; 4736 else 4737 { 4738 nregs = hard_regno_nregs[dst_regno][reg->biggest_mode]; 4739 for (i = 0; i < nregs; i++) 4740 usage_insns[dst_regno + i].check = 0; 4741 } 4742 } 4743 } 4744 if (! JUMP_P (curr_insn)) 4745 for (i = 0; i < to_inherit_num; i++) 4746 if (inherit_reload_reg (true, to_inherit[i].regno, 4747 ALL_REGS, curr_insn, 4748 to_inherit[i].insns)) 4749 change_p = true; 4750 if (CALL_P (curr_insn)) 4751 { 4752 rtx cheap, pat, dest, restore; 4753 int regno, hard_regno; 4754 4755 calls_num++; 4756 if ((cheap = find_reg_note (curr_insn, 4757 REG_RETURNED, NULL_RTX)) != NULL_RTX 4758 && ((cheap = XEXP (cheap, 0)), true) 4759 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER 4760 && (hard_regno = reg_renumber[regno]) >= 0 4761 /* If there are pending saves/restores, the 4762 optimization is not worth. */ 4763 && usage_insns[regno].calls_num == calls_num - 1 4764 && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) 4765 { 4766 /* Restore the pseudo from the call result as 4767 REG_RETURNED note says that the pseudo value is 4768 in the call result and the pseudo is an argument 4769 of the call. */ 4770 pat = PATTERN (curr_insn); 4771 if (GET_CODE (pat) == PARALLEL) 4772 pat = XVECEXP (pat, 0, 0); 4773 dest = SET_DEST (pat); 4774 start_sequence (); 4775 emit_move_insn (cheap, copy_rtx (dest)); 4776 restore = get_insns (); 4777 end_sequence (); 4778 lra_process_new_insns (curr_insn, NULL, restore, 4779 "Inserting call parameter restore"); 4780 /* We don't need to save/restore of the pseudo from 4781 this call. */ 4782 usage_insns[regno].calls_num = calls_num; 4783 bitmap_set_bit (&check_only_regs, regno); 4784 } 4785 } 4786 to_inherit_num = 0; 4787 /* Process insn usages. */ 4788 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 4789 if ((reg->type != OP_OUT 4790 || (reg->type == OP_OUT && reg->subreg_p)) 4791 && (src_regno = reg->regno) < lra_constraint_new_regno_start) 4792 { 4793 if (src_regno >= FIRST_PSEUDO_REGISTER 4794 && reg_renumber[src_regno] < 0 && reg->type == OP_IN) 4795 { 4796 if (usage_insns[src_regno].check == curr_usage_insns_check 4797 && (next_usage_insns 4798 = usage_insns[src_regno].insns) != NULL_RTX 4799 && NONDEBUG_INSN_P (curr_insn)) 4800 add_to_inherit (src_regno, next_usage_insns); 4801 else 4802 /* Add usages. */ 4803 add_next_usage_insn (src_regno, curr_insn, reloads_num); 4804 } 4805 else if (src_regno < FIRST_PSEUDO_REGISTER 4806 || reg_renumber[src_regno] >= 0) 4807 { 4808 bool before_p; 4809 rtx use_insn = curr_insn; 4810 4811 before_p = (JUMP_P (curr_insn) 4812 || (CALL_P (curr_insn) && reg->type == OP_IN)); 4813 if (NONDEBUG_INSN_P (curr_insn) 4814 && split_if_necessary (src_regno, reg->biggest_mode, 4815 potential_reload_hard_regs, 4816 before_p, curr_insn, max_uid)) 4817 { 4818 if (reg->subreg_p) 4819 lra_risky_transformations_p = true; 4820 change_p = true; 4821 /* Invalidate. */ 4822 usage_insns[src_regno].check = 0; 4823 if (before_p) 4824 use_insn = PREV_INSN (curr_insn); 4825 } 4826 if (NONDEBUG_INSN_P (curr_insn)) 4827 { 4828 if (src_regno < FIRST_PSEUDO_REGISTER) 4829 add_to_hard_reg_set (&live_hard_regs, 4830 reg->biggest_mode, src_regno); 4831 else 4832 add_to_hard_reg_set (&live_hard_regs, 4833 PSEUDO_REGNO_MODE (src_regno), 4834 reg_renumber[src_regno]); 4835 } 4836 add_next_usage_insn (src_regno, use_insn, reloads_num); 4837 } 4838 } 4839 for (i = 0; i < to_inherit_num; i++) 4840 { 4841 src_regno = to_inherit[i].regno; 4842 if (inherit_reload_reg (false, src_regno, ALL_REGS, 4843 curr_insn, to_inherit[i].insns)) 4844 change_p = true; 4845 else 4846 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); 4847 } 4848 } 4849 /* We reached the start of the current basic block. */ 4850 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) 4851 || BLOCK_FOR_INSN (prev_insn) != curr_bb) 4852 { 4853 /* We reached the beginning of the current block -- do 4854 rest of spliting in the current BB. */ 4855 to_process = df_get_live_in (curr_bb); 4856 if (BLOCK_FOR_INSN (head) != curr_bb) 4857 { 4858 /* We are somewhere in the middle of EBB. */ 4859 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, 4860 curr_bb, &temp_bitmap); 4861 to_process = &temp_bitmap; 4862 } 4863 head_p = true; 4864 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) 4865 { 4866 if ((int) j >= lra_constraint_new_regno_start) 4867 break; 4868 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) 4869 && usage_insns[j].check == curr_usage_insns_check 4870 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) 4871 { 4872 if (need_for_split_p (potential_reload_hard_regs, j)) 4873 { 4874 if (lra_dump_file != NULL && head_p) 4875 { 4876 fprintf (lra_dump_file, 4877 " ----------------------------------\n"); 4878 head_p = false; 4879 } 4880 if (split_reg (false, j, bb_note (curr_bb), 4881 next_usage_insns)) 4882 change_p = true; 4883 } 4884 usage_insns[j].check = 0; 4885 } 4886 } 4887 } 4888 } 4889 return change_p; 4890 } 4891 4892 /* This value affects EBB forming. If probability of edge from EBB to 4893 a BB is not greater than the following value, we don't add the BB 4894 to EBB. */ 4895 #define EBB_PROBABILITY_CUTOFF (REG_BR_PROB_BASE / 2) 4896 4897 /* Current number of inheritance/split iteration. */ 4898 int lra_inheritance_iter; 4899 4900 /* Entry function for inheritance/split pass. */ 4901 void 4902 lra_inheritance (void) 4903 { 4904 int i; 4905 basic_block bb, start_bb; 4906 edge e; 4907 4908 lra_inheritance_iter++; 4909 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) 4910 return; 4911 timevar_push (TV_LRA_INHERITANCE); 4912 if (lra_dump_file != NULL) 4913 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", 4914 lra_inheritance_iter); 4915 curr_usage_insns_check = 0; 4916 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); 4917 for (i = 0; i < lra_constraint_new_regno_start; i++) 4918 usage_insns[i].check = 0; 4919 bitmap_initialize (&check_only_regs, ®_obstack); 4920 bitmap_initialize (&live_regs, ®_obstack); 4921 bitmap_initialize (&temp_bitmap, ®_obstack); 4922 bitmap_initialize (&ebb_global_regs, ®_obstack); 4923 FOR_EACH_BB (bb) 4924 { 4925 start_bb = bb; 4926 if (lra_dump_file != NULL) 4927 fprintf (lra_dump_file, "EBB"); 4928 /* Form a EBB starting with BB. */ 4929 bitmap_clear (&ebb_global_regs); 4930 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); 4931 for (;;) 4932 { 4933 if (lra_dump_file != NULL) 4934 fprintf (lra_dump_file, " %d", bb->index); 4935 if (bb->next_bb == EXIT_BLOCK_PTR || LABEL_P (BB_HEAD (bb->next_bb))) 4936 break; 4937 e = find_fallthru_edge (bb->succs); 4938 if (! e) 4939 break; 4940 if (e->probability <= EBB_PROBABILITY_CUTOFF) 4941 break; 4942 bb = bb->next_bb; 4943 } 4944 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); 4945 if (lra_dump_file != NULL) 4946 fprintf (lra_dump_file, "\n"); 4947 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) 4948 /* Remember that the EBB head and tail can change in 4949 inherit_in_ebb. */ 4950 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); 4951 } 4952 bitmap_clear (&ebb_global_regs); 4953 bitmap_clear (&temp_bitmap); 4954 bitmap_clear (&live_regs); 4955 bitmap_clear (&check_only_regs); 4956 free (usage_insns); 4957 4958 timevar_pop (TV_LRA_INHERITANCE); 4959 } 4960 4961 4962 4963 /* This page contains code to undo failed inheritance/split 4964 transformations. */ 4965 4966 /* Current number of iteration undoing inheritance/split. */ 4967 int lra_undo_inheritance_iter; 4968 4969 /* Fix BB live info LIVE after removing pseudos created on pass doing 4970 inheritance/split which are REMOVED_PSEUDOS. */ 4971 static void 4972 fix_bb_live_info (bitmap live, bitmap removed_pseudos) 4973 { 4974 unsigned int regno; 4975 bitmap_iterator bi; 4976 4977 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) 4978 if (bitmap_clear_bit (live, regno)) 4979 bitmap_set_bit (live, lra_reg_info[regno].restore_regno); 4980 } 4981 4982 /* Return regno of the (subreg of) REG. Otherwise, return a negative 4983 number. */ 4984 static int 4985 get_regno (rtx reg) 4986 { 4987 if (GET_CODE (reg) == SUBREG) 4988 reg = SUBREG_REG (reg); 4989 if (REG_P (reg)) 4990 return REGNO (reg); 4991 return -1; 4992 } 4993 4994 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and 4995 return true if we did any change. The undo transformations for 4996 inheritance looks like 4997 i <- i2 4998 p <- i => p <- i2 4999 or removing 5000 p <- i, i <- p, and i <- i3 5001 where p is original pseudo from which inheritance pseudo i was 5002 created, i and i3 are removed inheritance pseudos, i2 is another 5003 not removed inheritance pseudo. All split pseudos or other 5004 occurrences of removed inheritance pseudos are changed on the 5005 corresponding original pseudos. 5006 5007 The function also schedules insns changed and created during 5008 inheritance/split pass for processing by the subsequent constraint 5009 pass. */ 5010 static bool 5011 remove_inheritance_pseudos (bitmap remove_pseudos) 5012 { 5013 basic_block bb; 5014 int regno, sregno, prev_sregno, dregno, restore_regno; 5015 rtx set, prev_set, prev_insn; 5016 bool change_p, done_p; 5017 5018 change_p = ! bitmap_empty_p (remove_pseudos); 5019 /* We can not finish the function right away if CHANGE_P is true 5020 because we need to marks insns affected by previous 5021 inheritance/split pass for processing by the subsequent 5022 constraint pass. */ 5023 FOR_EACH_BB (bb) 5024 { 5025 fix_bb_live_info (df_get_live_in (bb), remove_pseudos); 5026 fix_bb_live_info (df_get_live_out (bb), remove_pseudos); 5027 FOR_BB_INSNS_REVERSE (bb, curr_insn) 5028 { 5029 if (! INSN_P (curr_insn)) 5030 continue; 5031 done_p = false; 5032 sregno = dregno = -1; 5033 if (change_p && NONDEBUG_INSN_P (curr_insn) 5034 && (set = single_set (curr_insn)) != NULL_RTX) 5035 { 5036 dregno = get_regno (SET_DEST (set)); 5037 sregno = get_regno (SET_SRC (set)); 5038 } 5039 5040 if (sregno >= 0 && dregno >= 0) 5041 { 5042 if ((bitmap_bit_p (remove_pseudos, sregno) 5043 && (lra_reg_info[sregno].restore_regno == dregno 5044 || (bitmap_bit_p (remove_pseudos, dregno) 5045 && (lra_reg_info[sregno].restore_regno 5046 == lra_reg_info[dregno].restore_regno)))) 5047 || (bitmap_bit_p (remove_pseudos, dregno) 5048 && lra_reg_info[dregno].restore_regno == sregno)) 5049 /* One of the following cases: 5050 original <- removed inheritance pseudo 5051 removed inherit pseudo <- another removed inherit pseudo 5052 removed inherit pseudo <- original pseudo 5053 Or 5054 removed_split_pseudo <- original_reg 5055 original_reg <- removed_split_pseudo */ 5056 { 5057 if (lra_dump_file != NULL) 5058 { 5059 fprintf (lra_dump_file, " Removing %s:\n", 5060 bitmap_bit_p (&lra_split_regs, sregno) 5061 || bitmap_bit_p (&lra_split_regs, dregno) 5062 ? "split" : "inheritance"); 5063 dump_insn_slim (lra_dump_file, curr_insn); 5064 } 5065 lra_set_insn_deleted (curr_insn); 5066 done_p = true; 5067 } 5068 else if (bitmap_bit_p (remove_pseudos, sregno) 5069 && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) 5070 { 5071 /* Search the following pattern: 5072 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 5073 original_pseudo <- inherit_or_split_pseudo1 5074 where the 2nd insn is the current insn and 5075 inherit_or_split_pseudo2 is not removed. If it is found, 5076 change the current insn onto: 5077 original_pseudo <- inherit_or_split_pseudo2. */ 5078 for (prev_insn = PREV_INSN (curr_insn); 5079 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); 5080 prev_insn = PREV_INSN (prev_insn)) 5081 ; 5082 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb 5083 && (prev_set = single_set (prev_insn)) != NULL_RTX 5084 /* There should be no subregs in insn we are 5085 searching because only the original reg might 5086 be in subreg when we changed the mode of 5087 load/store for splitting. */ 5088 && REG_P (SET_DEST (prev_set)) 5089 && REG_P (SET_SRC (prev_set)) 5090 && (int) REGNO (SET_DEST (prev_set)) == sregno 5091 && ((prev_sregno = REGNO (SET_SRC (prev_set))) 5092 >= FIRST_PSEUDO_REGISTER) 5093 /* As we consider chain of inheritance or 5094 splitting described in above comment we should 5095 check that sregno and prev_sregno were 5096 inheritance/split pseudos created from the 5097 same original regno. */ 5098 && (lra_reg_info[sregno].restore_regno 5099 == lra_reg_info[prev_sregno].restore_regno) 5100 && ! bitmap_bit_p (remove_pseudos, prev_sregno)) 5101 { 5102 lra_assert (GET_MODE (SET_SRC (prev_set)) 5103 == GET_MODE (regno_reg_rtx[sregno])); 5104 if (GET_CODE (SET_SRC (set)) == SUBREG) 5105 SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set); 5106 else 5107 SET_SRC (set) = SET_SRC (prev_set); 5108 lra_push_insn_and_update_insn_regno_info (curr_insn); 5109 lra_set_used_insn_alternative_by_uid 5110 (INSN_UID (curr_insn), -1); 5111 done_p = true; 5112 if (lra_dump_file != NULL) 5113 { 5114 fprintf (lra_dump_file, " Change reload insn:\n"); 5115 dump_insn_slim (lra_dump_file, curr_insn); 5116 } 5117 } 5118 } 5119 } 5120 if (! done_p) 5121 { 5122 struct lra_insn_reg *reg; 5123 bool restored_regs_p = false; 5124 bool kept_regs_p = false; 5125 5126 curr_id = lra_get_insn_recog_data (curr_insn); 5127 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 5128 { 5129 regno = reg->regno; 5130 restore_regno = lra_reg_info[regno].restore_regno; 5131 if (restore_regno >= 0) 5132 { 5133 if (change_p && bitmap_bit_p (remove_pseudos, regno)) 5134 { 5135 substitute_pseudo (&curr_insn, regno, 5136 regno_reg_rtx[restore_regno]); 5137 restored_regs_p = true; 5138 } 5139 else 5140 kept_regs_p = true; 5141 } 5142 } 5143 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) 5144 { 5145 /* The instruction has changed since the previous 5146 constraints pass. */ 5147 lra_push_insn_and_update_insn_regno_info (curr_insn); 5148 lra_set_used_insn_alternative_by_uid 5149 (INSN_UID (curr_insn), -1); 5150 } 5151 else if (restored_regs_p) 5152 /* The instruction has been restored to the form that 5153 it had during the previous constraints pass. */ 5154 lra_update_insn_regno_info (curr_insn); 5155 if (restored_regs_p && lra_dump_file != NULL) 5156 { 5157 fprintf (lra_dump_file, " Insn after restoring regs:\n"); 5158 dump_insn_slim (lra_dump_file, curr_insn); 5159 } 5160 } 5161 } 5162 } 5163 return change_p; 5164 } 5165 5166 /* Entry function for undoing inheritance/split transformation. Return true 5167 if we did any RTL change in this pass. */ 5168 bool 5169 lra_undo_inheritance (void) 5170 { 5171 unsigned int regno; 5172 int restore_regno, hard_regno; 5173 int n_all_inherit, n_inherit, n_all_split, n_split; 5174 bitmap_head remove_pseudos; 5175 bitmap_iterator bi; 5176 bool change_p; 5177 5178 lra_undo_inheritance_iter++; 5179 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) 5180 return false; 5181 if (lra_dump_file != NULL) 5182 fprintf (lra_dump_file, 5183 "\n********** Undoing inheritance #%d: **********\n\n", 5184 lra_undo_inheritance_iter); 5185 bitmap_initialize (&remove_pseudos, ®_obstack); 5186 n_inherit = n_all_inherit = 0; 5187 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) 5188 if (lra_reg_info[regno].restore_regno >= 0) 5189 { 5190 n_all_inherit++; 5191 if (reg_renumber[regno] < 0) 5192 bitmap_set_bit (&remove_pseudos, regno); 5193 else 5194 n_inherit++; 5195 } 5196 if (lra_dump_file != NULL && n_all_inherit != 0) 5197 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", 5198 n_inherit, n_all_inherit, 5199 (double) n_inherit / n_all_inherit * 100); 5200 n_split = n_all_split = 0; 5201 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) 5202 if ((restore_regno = lra_reg_info[regno].restore_regno) >= 0) 5203 { 5204 n_all_split++; 5205 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER 5206 ? reg_renumber[restore_regno] : restore_regno); 5207 if (hard_regno < 0 || reg_renumber[regno] == hard_regno) 5208 bitmap_set_bit (&remove_pseudos, regno); 5209 else 5210 { 5211 n_split++; 5212 if (lra_dump_file != NULL) 5213 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", 5214 regno, restore_regno); 5215 } 5216 } 5217 if (lra_dump_file != NULL && n_all_split != 0) 5218 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", 5219 n_split, n_all_split, 5220 (double) n_split / n_all_split * 100); 5221 change_p = remove_inheritance_pseudos (&remove_pseudos); 5222 bitmap_clear (&remove_pseudos); 5223 /* Clear restore_regnos. */ 5224 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) 5225 lra_reg_info[regno].restore_regno = -1; 5226 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) 5227 lra_reg_info[regno].restore_regno = -1; 5228 return change_p; 5229 } 5230