1 /* Code for RTL transformations to satisfy insn constraints. 2 Copyright (C) 2010-2017 Free Software Foundation, Inc. 3 Contributed by Vladimir Makarov <vmakarov@redhat.com>. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it under 8 the terms of the GNU General Public License as published by the Free 9 Software Foundation; either version 3, or (at your option) any later 10 version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 /* This file contains code for 3 passes: constraint pass, 23 inheritance/split pass, and pass for undoing failed inheritance and 24 split. 25 26 The major goal of constraint pass is to transform RTL to satisfy 27 insn and address constraints by: 28 o choosing insn alternatives; 29 o generating *reload insns* (or reloads in brief) and *reload 30 pseudos* which will get necessary hard registers later; 31 o substituting pseudos with equivalent values and removing the 32 instructions that initialized those pseudos. 33 34 The constraint pass has biggest and most complicated code in LRA. 35 There are a lot of important details like: 36 o reuse of input reload pseudos to simplify reload pseudo 37 allocations; 38 o some heuristics to choose insn alternative to improve the 39 inheritance; 40 o early clobbers etc. 41 42 The pass is mimicking former reload pass in alternative choosing 43 because the reload pass is oriented to current machine description 44 model. It might be changed if the machine description model is 45 changed. 46 47 There is special code for preventing all LRA and this pass cycling 48 in case of bugs. 49 50 On the first iteration of the pass we process every instruction and 51 choose an alternative for each one. On subsequent iterations we try 52 to avoid reprocessing instructions if we can be sure that the old 53 choice is still valid. 54 55 The inheritance/spilt pass is to transform code to achieve 56 ineheritance and live range splitting. It is done on backward 57 traversal of EBBs. 58 59 The inheritance optimization goal is to reuse values in hard 60 registers. There is analogous optimization in old reload pass. The 61 inheritance is achieved by following transformation: 62 63 reload_p1 <- p reload_p1 <- p 64 ... new_p <- reload_p1 65 ... => ... 66 reload_p2 <- p reload_p2 <- new_p 67 68 where p is spilled and not changed between the insns. Reload_p1 is 69 also called *original pseudo* and new_p is called *inheritance 70 pseudo*. 71 72 The subsequent assignment pass will try to assign the same (or 73 another if it is not possible) hard register to new_p as to 74 reload_p1 or reload_p2. 75 76 If the assignment pass fails to assign a hard register to new_p, 77 this file will undo the inheritance and restore the original code. 78 This is because implementing the above sequence with a spilled 79 new_p would make the code much worse. The inheritance is done in 80 EBB scope. The above is just a simplified example to get an idea 81 of the inheritance as the inheritance is also done for non-reload 82 insns. 83 84 Splitting (transformation) is also done in EBB scope on the same 85 pass as the inheritance: 86 87 r <- ... or ... <- r r <- ... or ... <- r 88 ... s <- r (new insn -- save) 89 ... => 90 ... r <- s (new insn -- restore) 91 ... <- r ... <- r 92 93 The *split pseudo* s is assigned to the hard register of the 94 original pseudo or hard register r. 95 96 Splitting is done: 97 o In EBBs with high register pressure for global pseudos (living 98 in at least 2 BBs) and assigned to hard registers when there 99 are more one reloads needing the hard registers; 100 o for pseudos needing save/restore code around calls. 101 102 If the split pseudo still has the same hard register as the 103 original pseudo after the subsequent assignment pass or the 104 original pseudo was split, the opposite transformation is done on 105 the same pass for undoing inheritance. */ 106 107 #undef REG_OK_STRICT 108 109 #include "config.h" 110 #include "system.h" 111 #include "coretypes.h" 112 #include "backend.h" 113 #include "target.h" 114 #include "rtl.h" 115 #include "tree.h" 116 #include "predict.h" 117 #include "df.h" 118 #include "memmodel.h" 119 #include "tm_p.h" 120 #include "expmed.h" 121 #include "optabs.h" 122 #include "regs.h" 123 #include "ira.h" 124 #include "recog.h" 125 #include "output.h" 126 #include "addresses.h" 127 #include "expr.h" 128 #include "cfgrtl.h" 129 #include "rtl-error.h" 130 #include "params.h" 131 #include "lra.h" 132 #include "lra-int.h" 133 #include "print-rtl.h" 134 135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current 136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted 137 reload insns. */ 138 static int bb_reload_num; 139 140 /* The current insn being processed and corresponding its single set 141 (NULL otherwise), its data (basic block, the insn data, the insn 142 static data, and the mode of each operand). */ 143 static rtx_insn *curr_insn; 144 static rtx curr_insn_set; 145 static basic_block curr_bb; 146 static lra_insn_recog_data_t curr_id; 147 static struct lra_static_insn_data *curr_static_id; 148 static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; 149 /* Mode of the register substituted by its equivalence with VOIDmode 150 (e.g. constant) and whose subreg is given operand of the current 151 insn. VOIDmode in all other cases. */ 152 static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; 153 154 155 156 /* Start numbers for new registers and insns at the current constraints 157 pass start. */ 158 static int new_regno_start; 159 static int new_insn_uid_start; 160 161 /* If LOC is nonnull, strip any outer subreg from it. */ 162 static inline rtx * 163 strip_subreg (rtx *loc) 164 { 165 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; 166 } 167 168 /* Return hard regno of REGNO or if it is was not assigned to a hard 169 register, use a hard register from its allocno class. */ 170 static int 171 get_try_hard_regno (int regno) 172 { 173 int hard_regno; 174 enum reg_class rclass; 175 176 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) 177 hard_regno = lra_get_regno_hard_regno (regno); 178 if (hard_regno >= 0) 179 return hard_regno; 180 rclass = lra_get_allocno_class (regno); 181 if (rclass == NO_REGS) 182 return -1; 183 return ira_class_hard_regs[rclass][0]; 184 } 185 186 /* Return the hard regno of X after removing its subreg. If X is not 187 a register or a subreg of a register, return -1. If X is a pseudo, 188 use its assignment. If FINAL_P return the final hard regno which will 189 be after elimination. */ 190 static int 191 get_hard_regno (rtx x, bool final_p) 192 { 193 rtx reg; 194 int hard_regno; 195 196 reg = x; 197 if (SUBREG_P (x)) 198 reg = SUBREG_REG (x); 199 if (! REG_P (reg)) 200 return -1; 201 if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))) 202 hard_regno = lra_get_regno_hard_regno (hard_regno); 203 if (hard_regno < 0) 204 return -1; 205 if (final_p) 206 hard_regno = lra_get_elimination_hard_regno (hard_regno); 207 if (SUBREG_P (x)) 208 hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg), 209 SUBREG_BYTE (x), GET_MODE (x)); 210 return hard_regno; 211 } 212 213 /* If REGNO is a hard register or has been allocated a hard register, 214 return the class of that register. If REGNO is a reload pseudo 215 created by the current constraints pass, return its allocno class. 216 Return NO_REGS otherwise. */ 217 static enum reg_class 218 get_reg_class (int regno) 219 { 220 int hard_regno; 221 222 if (! HARD_REGISTER_NUM_P (hard_regno = regno)) 223 hard_regno = lra_get_regno_hard_regno (regno); 224 if (hard_regno >= 0) 225 { 226 hard_regno = lra_get_elimination_hard_regno (hard_regno); 227 return REGNO_REG_CLASS (hard_regno); 228 } 229 if (regno >= new_regno_start) 230 return lra_get_allocno_class (regno); 231 return NO_REGS; 232 } 233 234 /* Return true if REG satisfies (or will satisfy) reg class constraint 235 CL. Use elimination first if REG is a hard register. If REG is a 236 reload pseudo created by this constraints pass, assume that it will 237 be allocated a hard register from its allocno class, but allow that 238 class to be narrowed to CL if it is currently a superset of CL. 239 240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of 241 REGNO (reg), or NO_REGS if no change in its class was needed. */ 242 static bool 243 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) 244 { 245 enum reg_class rclass, common_class; 246 machine_mode reg_mode; 247 int class_size, hard_regno, nregs, i, j; 248 int regno = REGNO (reg); 249 250 if (new_class != NULL) 251 *new_class = NO_REGS; 252 if (regno < FIRST_PSEUDO_REGISTER) 253 { 254 rtx final_reg = reg; 255 rtx *final_loc = &final_reg; 256 257 lra_eliminate_reg_if_possible (final_loc); 258 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); 259 } 260 reg_mode = GET_MODE (reg); 261 rclass = get_reg_class (regno); 262 if (regno < new_regno_start 263 /* Do not allow the constraints for reload instructions to 264 influence the classes of new pseudos. These reloads are 265 typically moves that have many alternatives, and restricting 266 reload pseudos for one alternative may lead to situations 267 where other reload pseudos are no longer allocatable. */ 268 || (INSN_UID (curr_insn) >= new_insn_uid_start 269 && curr_insn_set != NULL 270 && ((OBJECT_P (SET_SRC (curr_insn_set)) 271 && ! CONSTANT_P (SET_SRC (curr_insn_set))) 272 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG 273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))) 274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) 275 /* When we don't know what class will be used finally for reload 276 pseudos, we use ALL_REGS. */ 277 return ((regno >= new_regno_start && rclass == ALL_REGS) 278 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] 279 && ! hard_reg_set_subset_p (reg_class_contents[cl], 280 lra_no_alloc_regs))); 281 else 282 { 283 common_class = ira_reg_class_subset[rclass][cl]; 284 if (new_class != NULL) 285 *new_class = common_class; 286 if (hard_reg_set_subset_p (reg_class_contents[common_class], 287 lra_no_alloc_regs)) 288 return false; 289 /* Check that there are enough allocatable regs. */ 290 class_size = ira_class_hard_regs_num[common_class]; 291 for (i = 0; i < class_size; i++) 292 { 293 hard_regno = ira_class_hard_regs[common_class][i]; 294 nregs = hard_regno_nregs[hard_regno][reg_mode]; 295 if (nregs == 1) 296 return true; 297 for (j = 0; j < nregs; j++) 298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) 299 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], 300 hard_regno + j)) 301 break; 302 if (j >= nregs) 303 return true; 304 } 305 return false; 306 } 307 } 308 309 /* Return true if REGNO satisfies a memory constraint. */ 310 static bool 311 in_mem_p (int regno) 312 { 313 return get_reg_class (regno) == NO_REGS; 314 } 315 316 /* Return 1 if ADDR is a valid memory address for mode MODE in address 317 space AS, and check that each pseudo has the proper kind of hard 318 reg. */ 319 static int 320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, 321 rtx addr, addr_space_t as) 322 { 323 #ifdef GO_IF_LEGITIMATE_ADDRESS 324 lra_assert (ADDR_SPACE_GENERIC_P (as)); 325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); 326 return 0; 327 328 win: 329 return 1; 330 #else 331 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); 332 #endif 333 } 334 335 namespace { 336 /* Temporarily eliminates registers in an address (for the lifetime of 337 the object). */ 338 class address_eliminator { 339 public: 340 address_eliminator (struct address_info *ad); 341 ~address_eliminator (); 342 343 private: 344 struct address_info *m_ad; 345 rtx *m_base_loc; 346 rtx m_base_reg; 347 rtx *m_index_loc; 348 rtx m_index_reg; 349 }; 350 } 351 352 address_eliminator::address_eliminator (struct address_info *ad) 353 : m_ad (ad), 354 m_base_loc (strip_subreg (ad->base_term)), 355 m_base_reg (NULL_RTX), 356 m_index_loc (strip_subreg (ad->index_term)), 357 m_index_reg (NULL_RTX) 358 { 359 if (m_base_loc != NULL) 360 { 361 m_base_reg = *m_base_loc; 362 lra_eliminate_reg_if_possible (m_base_loc); 363 if (m_ad->base_term2 != NULL) 364 *m_ad->base_term2 = *m_ad->base_term; 365 } 366 if (m_index_loc != NULL) 367 { 368 m_index_reg = *m_index_loc; 369 lra_eliminate_reg_if_possible (m_index_loc); 370 } 371 } 372 373 address_eliminator::~address_eliminator () 374 { 375 if (m_base_loc && *m_base_loc != m_base_reg) 376 { 377 *m_base_loc = m_base_reg; 378 if (m_ad->base_term2 != NULL) 379 *m_ad->base_term2 = *m_ad->base_term; 380 } 381 if (m_index_loc && *m_index_loc != m_index_reg) 382 *m_index_loc = m_index_reg; 383 } 384 385 /* Return true if the eliminated form of AD is a legitimate target address. */ 386 static bool 387 valid_address_p (struct address_info *ad) 388 { 389 address_eliminator eliminator (ad); 390 return valid_address_p (ad->mode, *ad->outer, ad->as); 391 } 392 393 /* Return true if the eliminated form of memory reference OP satisfies 394 extra (special) memory constraint CONSTRAINT. */ 395 static bool 396 satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) 397 { 398 struct address_info ad; 399 400 decompose_mem_address (&ad, op); 401 address_eliminator eliminator (&ad); 402 return constraint_satisfied_p (op, constraint); 403 } 404 405 /* Return true if the eliminated form of address AD satisfies extra 406 address constraint CONSTRAINT. */ 407 static bool 408 satisfies_address_constraint_p (struct address_info *ad, 409 enum constraint_num constraint) 410 { 411 address_eliminator eliminator (ad); 412 return constraint_satisfied_p (*ad->outer, constraint); 413 } 414 415 /* Return true if the eliminated form of address OP satisfies extra 416 address constraint CONSTRAINT. */ 417 static bool 418 satisfies_address_constraint_p (rtx op, enum constraint_num constraint) 419 { 420 struct address_info ad; 421 422 decompose_lea_address (&ad, &op); 423 return satisfies_address_constraint_p (&ad, constraint); 424 } 425 426 /* Initiate equivalences for LRA. As we keep original equivalences 427 before any elimination, we need to make copies otherwise any change 428 in insns might change the equivalences. */ 429 void 430 lra_init_equiv (void) 431 { 432 ira_expand_reg_equiv (); 433 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) 434 { 435 rtx res; 436 437 if ((res = ira_reg_equiv[i].memory) != NULL_RTX) 438 ira_reg_equiv[i].memory = copy_rtx (res); 439 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) 440 ira_reg_equiv[i].invariant = copy_rtx (res); 441 } 442 } 443 444 static rtx loc_equivalence_callback (rtx, const_rtx, void *); 445 446 /* Update equivalence for REGNO. We need to this as the equivalence 447 might contain other pseudos which are changed by their 448 equivalences. */ 449 static void 450 update_equiv (int regno) 451 { 452 rtx x; 453 454 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) 455 ira_reg_equiv[regno].memory 456 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, 457 NULL_RTX); 458 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) 459 ira_reg_equiv[regno].invariant 460 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, 461 NULL_RTX); 462 } 463 464 /* If we have decided to substitute X with another value, return that 465 value, otherwise return X. */ 466 static rtx 467 get_equiv (rtx x) 468 { 469 int regno; 470 rtx res; 471 472 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER 473 || ! ira_reg_equiv[regno].defined_p 474 || ! ira_reg_equiv[regno].profitable_p 475 || lra_get_regno_hard_regno (regno) >= 0) 476 return x; 477 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) 478 { 479 if (targetm.cannot_substitute_mem_equiv_p (res)) 480 return x; 481 return res; 482 } 483 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) 484 return res; 485 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) 486 return res; 487 gcc_unreachable (); 488 } 489 490 /* If we have decided to substitute X with the equivalent value, 491 return that value after elimination for INSN, otherwise return 492 X. */ 493 static rtx 494 get_equiv_with_elimination (rtx x, rtx_insn *insn) 495 { 496 rtx res = get_equiv (x); 497 498 if (x == res || CONSTANT_P (res)) 499 return res; 500 return lra_eliminate_regs_1 (insn, res, GET_MODE (res), 501 false, false, 0, true); 502 } 503 504 /* Set up curr_operand_mode. */ 505 static void 506 init_curr_operand_mode (void) 507 { 508 int nop = curr_static_id->n_operands; 509 for (int i = 0; i < nop; i++) 510 { 511 machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); 512 if (mode == VOIDmode) 513 { 514 /* The .md mode for address operands is the mode of the 515 addressed value rather than the mode of the address itself. */ 516 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) 517 mode = Pmode; 518 else 519 mode = curr_static_id->operand[i].mode; 520 } 521 curr_operand_mode[i] = mode; 522 } 523 } 524 525 526 527 /* The page contains code to reuse input reloads. */ 528 529 /* Structure describes input reload of the current insns. */ 530 struct input_reload 531 { 532 /* True for input reload of matched operands. */ 533 bool match_p; 534 /* Reloaded value. */ 535 rtx input; 536 /* Reload pseudo used. */ 537 rtx reg; 538 }; 539 540 /* The number of elements in the following array. */ 541 static int curr_insn_input_reloads_num; 542 /* Array containing info about input reloads. It is used to find the 543 same input reload and reuse the reload pseudo in this case. */ 544 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; 545 546 /* Initiate data concerning reuse of input reloads for the current 547 insn. */ 548 static void 549 init_curr_insn_input_reloads (void) 550 { 551 curr_insn_input_reloads_num = 0; 552 } 553 554 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already 555 created input reload pseudo (only if TYPE is not OP_OUT). Don't 556 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be 557 wrapped up in SUBREG. The result pseudo is returned through 558 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we 559 reused the already created input reload pseudo. Use TITLE to 560 describe new registers for debug purposes. */ 561 static bool 562 get_reload_reg (enum op_type type, machine_mode mode, rtx original, 563 enum reg_class rclass, bool in_subreg_p, 564 const char *title, rtx *result_reg) 565 { 566 int i, regno; 567 enum reg_class new_class; 568 bool unique_p = false; 569 570 if (type == OP_OUT) 571 { 572 *result_reg 573 = lra_create_new_reg_with_unique_value (mode, original, rclass, title); 574 return true; 575 } 576 /* Prevent reuse value of expression with side effects, 577 e.g. volatile memory. */ 578 if (! side_effects_p (original)) 579 for (i = 0; i < curr_insn_input_reloads_num; i++) 580 { 581 if (! curr_insn_input_reloads[i].match_p 582 && rtx_equal_p (curr_insn_input_reloads[i].input, original) 583 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) 584 { 585 rtx reg = curr_insn_input_reloads[i].reg; 586 regno = REGNO (reg); 587 /* If input is equal to original and both are VOIDmode, 588 GET_MODE (reg) might be still different from mode. 589 Ensure we don't return *result_reg with wrong mode. */ 590 if (GET_MODE (reg) != mode) 591 { 592 if (in_subreg_p) 593 continue; 594 if (GET_MODE_SIZE (GET_MODE (reg)) < GET_MODE_SIZE (mode)) 595 continue; 596 reg = lowpart_subreg (mode, reg, GET_MODE (reg)); 597 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) 598 continue; 599 } 600 *result_reg = reg; 601 if (lra_dump_file != NULL) 602 { 603 fprintf (lra_dump_file, " Reuse r%d for reload ", regno); 604 dump_value_slim (lra_dump_file, original, 1); 605 } 606 if (new_class != lra_get_allocno_class (regno)) 607 lra_change_class (regno, new_class, ", change to", false); 608 if (lra_dump_file != NULL) 609 fprintf (lra_dump_file, "\n"); 610 return false; 611 } 612 /* If we have an input reload with a different mode, make sure it 613 will get a different hard reg. */ 614 else if (REG_P (original) 615 && REG_P (curr_insn_input_reloads[i].input) 616 && REGNO (original) == REGNO (curr_insn_input_reloads[i].input) 617 && (GET_MODE (original) 618 != GET_MODE (curr_insn_input_reloads[i].input))) 619 unique_p = true; 620 } 621 *result_reg = (unique_p 622 ? lra_create_new_reg_with_unique_value 623 : lra_create_new_reg) (mode, original, rclass, title); 624 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); 625 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; 626 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false; 627 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; 628 return true; 629 } 630 631 632 633 /* The page contains code to extract memory address parts. */ 634 635 /* Wrapper around REGNO_OK_FOR_INDEX_P, to allow pseudos. */ 636 static inline bool 637 ok_for_index_p_nonstrict (rtx reg) 638 { 639 unsigned regno = REGNO (reg); 640 641 return regno >= FIRST_PSEUDO_REGISTER || REGNO_OK_FOR_INDEX_P (regno); 642 } 643 644 /* A version of regno_ok_for_base_p for use here, when all pseudos 645 should count as OK. Arguments as for regno_ok_for_base_p. */ 646 static inline bool 647 ok_for_base_p_nonstrict (rtx reg, machine_mode mode, addr_space_t as, 648 enum rtx_code outer_code, enum rtx_code index_code) 649 { 650 unsigned regno = REGNO (reg); 651 652 if (regno >= FIRST_PSEUDO_REGISTER) 653 return true; 654 return ok_for_base_p_1 (regno, mode, as, outer_code, index_code); 655 } 656 657 658 659 /* The page contains major code to choose the current insn alternative 660 and generate reloads for it. */ 661 662 /* Return the offset from REGNO of the least significant register 663 in (reg:MODE REGNO). 664 665 This function is used to tell whether two registers satisfy 666 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: 667 668 REGNO1 + lra_constraint_offset (REGNO1, MODE1) 669 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ 670 int 671 lra_constraint_offset (int regno, machine_mode mode) 672 { 673 lra_assert (regno < FIRST_PSEUDO_REGISTER); 674 if (WORDS_BIG_ENDIAN && GET_MODE_SIZE (mode) > UNITS_PER_WORD 675 && SCALAR_INT_MODE_P (mode)) 676 return hard_regno_nregs[regno][mode] - 1; 677 return 0; 678 } 679 680 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match 681 if they are the same hard reg, and has special hacks for 682 auto-increment and auto-decrement. This is specifically intended for 683 process_alt_operands to use in determining whether two operands 684 match. X is the operand whose number is the lower of the two. 685 686 It is supposed that X is the output operand and Y is the input 687 operand. Y_HARD_REGNO is the final hard regno of register Y or 688 register in subreg Y as we know it now. Otherwise, it is a 689 negative value. */ 690 static bool 691 operands_match_p (rtx x, rtx y, int y_hard_regno) 692 { 693 int i; 694 RTX_CODE code = GET_CODE (x); 695 const char *fmt; 696 697 if (x == y) 698 return true; 699 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) 700 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) 701 { 702 int j; 703 704 i = get_hard_regno (x, false); 705 if (i < 0) 706 goto slow; 707 708 if ((j = y_hard_regno) < 0) 709 goto slow; 710 711 i += lra_constraint_offset (i, GET_MODE (x)); 712 j += lra_constraint_offset (j, GET_MODE (y)); 713 714 return i == j; 715 } 716 717 /* If two operands must match, because they are really a single 718 operand of an assembler insn, then two post-increments are invalid 719 because the assembler insn would increment only once. On the 720 other hand, a post-increment matches ordinary indexing if the 721 post-increment is the output operand. */ 722 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) 723 return operands_match_p (XEXP (x, 0), y, y_hard_regno); 724 725 /* Two pre-increments are invalid because the assembler insn would 726 increment only once. On the other hand, a pre-increment matches 727 ordinary indexing if the pre-increment is the input operand. */ 728 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC 729 || GET_CODE (y) == PRE_MODIFY) 730 return operands_match_p (x, XEXP (y, 0), -1); 731 732 slow: 733 734 if (code == REG && REG_P (y)) 735 return REGNO (x) == REGNO (y); 736 737 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) 738 && x == SUBREG_REG (y)) 739 return true; 740 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) 741 && SUBREG_REG (x) == y) 742 return true; 743 744 /* Now we have disposed of all the cases in which different rtx 745 codes can match. */ 746 if (code != GET_CODE (y)) 747 return false; 748 749 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ 750 if (GET_MODE (x) != GET_MODE (y)) 751 return false; 752 753 switch (code) 754 { 755 CASE_CONST_UNIQUE: 756 return false; 757 758 case LABEL_REF: 759 return label_ref_label (x) == label_ref_label (y); 760 case SYMBOL_REF: 761 return XSTR (x, 0) == XSTR (y, 0); 762 763 default: 764 break; 765 } 766 767 /* Compare the elements. If any pair of corresponding elements fail 768 to match, return false for the whole things. */ 769 770 fmt = GET_RTX_FORMAT (code); 771 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 772 { 773 int val, j; 774 switch (fmt[i]) 775 { 776 case 'w': 777 if (XWINT (x, i) != XWINT (y, i)) 778 return false; 779 break; 780 781 case 'i': 782 if (XINT (x, i) != XINT (y, i)) 783 return false; 784 break; 785 786 case 'e': 787 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); 788 if (val == 0) 789 return false; 790 break; 791 792 case '0': 793 break; 794 795 case 'E': 796 if (XVECLEN (x, i) != XVECLEN (y, i)) 797 return false; 798 for (j = XVECLEN (x, i) - 1; j >= 0; --j) 799 { 800 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); 801 if (val == 0) 802 return false; 803 } 804 break; 805 806 /* It is believed that rtx's at this level will never 807 contain anything but integers and other rtx's, except for 808 within LABEL_REFs and SYMBOL_REFs. */ 809 default: 810 gcc_unreachable (); 811 } 812 } 813 return true; 814 } 815 816 /* True if X is a constant that can be forced into the constant pool. 817 MODE is the mode of the operand, or VOIDmode if not known. */ 818 #define CONST_POOL_OK_P(MODE, X) \ 819 ((MODE) != VOIDmode \ 820 && CONSTANT_P (X) \ 821 && GET_CODE (X) != HIGH \ 822 && !targetm.cannot_force_const_mem (MODE, X)) 823 824 /* True if C is a non-empty register class that has too few registers 825 to be safely used as a reload target class. */ 826 #define SMALL_REGISTER_CLASS_P(C) \ 827 (ira_class_hard_regs_num [(C)] == 1 \ 828 || (ira_class_hard_regs_num [(C)] >= 1 \ 829 && targetm.class_likely_spilled_p (C))) 830 831 /* If REG is a reload pseudo, try to make its class satisfying CL. */ 832 static void 833 narrow_reload_pseudo_class (rtx reg, enum reg_class cl) 834 { 835 enum reg_class rclass; 836 837 /* Do not make more accurate class from reloads generated. They are 838 mostly moves with a lot of constraints. Making more accurate 839 class may results in very narrow class and impossibility of find 840 registers for several reloads of one insn. */ 841 if (INSN_UID (curr_insn) >= new_insn_uid_start) 842 return; 843 if (GET_CODE (reg) == SUBREG) 844 reg = SUBREG_REG (reg); 845 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) 846 return; 847 if (in_class_p (reg, cl, &rclass) && rclass != cl) 848 lra_change_class (REGNO (reg), rclass, " Change to", true); 849 } 850 851 /* Searches X for any reference to a reg with the same value as REGNO, 852 returning the rtx of the reference found if any. Otherwise, 853 returns NULL_RTX. */ 854 static rtx 855 regno_val_use_in (unsigned int regno, rtx x) 856 { 857 const char *fmt; 858 int i, j; 859 rtx tem; 860 861 if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val) 862 return x; 863 864 fmt = GET_RTX_FORMAT (GET_CODE (x)); 865 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 866 { 867 if (fmt[i] == 'e') 868 { 869 if ((tem = regno_val_use_in (regno, XEXP (x, i)))) 870 return tem; 871 } 872 else if (fmt[i] == 'E') 873 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 874 if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)))) 875 return tem; 876 } 877 878 return NULL_RTX; 879 } 880 881 /* Return true if all current insn non-output operands except INS (it 882 has a negaitve end marker) do not use pseudos with the same value 883 as REGNO. */ 884 static bool 885 check_conflict_input_operands (int regno, signed char *ins) 886 { 887 int in; 888 int n_operands = curr_static_id->n_operands; 889 890 for (int nop = 0; nop < n_operands; nop++) 891 if (! curr_static_id->operand[nop].is_operator 892 && curr_static_id->operand[nop].type != OP_OUT) 893 { 894 for (int i = 0; (in = ins[i]) >= 0; i++) 895 if (in == nop) 896 break; 897 if (in < 0 898 && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX) 899 return false; 900 } 901 return true; 902 } 903 904 /* Generate reloads for matching OUT and INS (array of input operand 905 numbers with end marker -1) with reg class GOAL_CLASS, considering 906 output operands OUTS (similar array to INS) needing to be in different 907 registers. Add input and output reloads correspondingly to the lists 908 *BEFORE and *AFTER. OUT might be negative. In this case we generate 909 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag 910 that the output operand is early clobbered for chosen alternative. */ 911 static void 912 match_reload (signed char out, signed char *ins, signed char *outs, 913 enum reg_class goal_class, rtx_insn **before, 914 rtx_insn **after, bool early_clobber_p) 915 { 916 bool out_conflict; 917 int i, in; 918 rtx new_in_reg, new_out_reg, reg; 919 machine_mode inmode, outmode; 920 rtx in_rtx = *curr_id->operand_loc[ins[0]]; 921 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; 922 923 inmode = curr_operand_mode[ins[0]]; 924 outmode = out < 0 ? inmode : curr_operand_mode[out]; 925 push_to_sequence (*before); 926 if (inmode != outmode) 927 { 928 if (GET_MODE_SIZE (inmode) > GET_MODE_SIZE (outmode)) 929 { 930 reg = new_in_reg 931 = lra_create_new_reg_with_unique_value (inmode, in_rtx, 932 goal_class, ""); 933 if (SCALAR_INT_MODE_P (inmode)) 934 new_out_reg = gen_lowpart_SUBREG (outmode, reg); 935 else 936 new_out_reg = gen_rtx_SUBREG (outmode, reg, 0); 937 LRA_SUBREG_P (new_out_reg) = 1; 938 /* If the input reg is dying here, we can use the same hard 939 register for REG and IN_RTX. We do it only for original 940 pseudos as reload pseudos can die although original 941 pseudos still live where reload pseudos dies. */ 942 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start 943 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) 944 && (!early_clobber_p 945 || check_conflict_input_operands(REGNO (in_rtx), ins))) 946 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); 947 } 948 else 949 { 950 reg = new_out_reg 951 = lra_create_new_reg_with_unique_value (outmode, out_rtx, 952 goal_class, ""); 953 if (SCALAR_INT_MODE_P (outmode)) 954 new_in_reg = gen_lowpart_SUBREG (inmode, reg); 955 else 956 new_in_reg = gen_rtx_SUBREG (inmode, reg, 0); 957 /* NEW_IN_REG is non-paradoxical subreg. We don't want 958 NEW_OUT_REG living above. We add clobber clause for 959 this. This is just a temporary clobber. We can remove 960 it at the end of LRA work. */ 961 rtx_insn *clobber = emit_clobber (new_out_reg); 962 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; 963 LRA_SUBREG_P (new_in_reg) = 1; 964 if (GET_CODE (in_rtx) == SUBREG) 965 { 966 rtx subreg_reg = SUBREG_REG (in_rtx); 967 968 /* If SUBREG_REG is dying here and sub-registers IN_RTX 969 and NEW_IN_REG are similar, we can use the same hard 970 register for REG and SUBREG_REG. */ 971 if (REG_P (subreg_reg) 972 && (int) REGNO (subreg_reg) < lra_new_regno_start 973 && GET_MODE (subreg_reg) == outmode 974 && SUBREG_BYTE (in_rtx) == SUBREG_BYTE (new_in_reg) 975 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)) 976 && (! early_clobber_p 977 || check_conflict_input_operands (REGNO (subreg_reg), 978 ins))) 979 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); 980 } 981 } 982 } 983 else 984 { 985 /* Pseudos have values -- see comments for lra_reg_info. 986 Different pseudos with the same value do not conflict even if 987 they live in the same place. When we create a pseudo we 988 assign value of original pseudo (if any) from which we 989 created the new pseudo. If we create the pseudo from the 990 input pseudo, the new pseudo will have no conflict with the 991 input pseudo which is wrong when the input pseudo lives after 992 the insn and as the new pseudo value is changed by the insn 993 output. Therefore we create the new pseudo from the output 994 except the case when we have single matched dying input 995 pseudo. 996 997 We cannot reuse the current output register because we might 998 have a situation like "a <- a op b", where the constraints 999 force the second input operand ("b") to match the output 1000 operand ("a"). "b" must then be copied into a new register 1001 so that it doesn't clobber the current value of "a". 1002 1003 We can not use the same value if the output pseudo is 1004 early clobbered or the input pseudo is mentioned in the 1005 output, e.g. as an address part in memory, because 1006 output reload will actually extend the pseudo liveness. 1007 We don't care about eliminable hard regs here as we are 1008 interesting only in pseudos. */ 1009 1010 /* Matching input's register value is the same as one of the other 1011 output operand. Output operands in a parallel insn must be in 1012 different registers. */ 1013 out_conflict = false; 1014 if (REG_P (in_rtx)) 1015 { 1016 for (i = 0; outs[i] >= 0; i++) 1017 { 1018 rtx other_out_rtx = *curr_id->operand_loc[outs[i]]; 1019 if (REG_P (other_out_rtx) 1020 && (regno_val_use_in (REGNO (in_rtx), other_out_rtx) 1021 != NULL_RTX)) 1022 { 1023 out_conflict = true; 1024 break; 1025 } 1026 } 1027 } 1028 1029 new_in_reg = new_out_reg 1030 = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) 1031 && (int) REGNO (in_rtx) < lra_new_regno_start 1032 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) 1033 && (! early_clobber_p 1034 || check_conflict_input_operands (REGNO (in_rtx), ins)) 1035 && (out < 0 1036 || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) 1037 && !out_conflict 1038 ? lra_create_new_reg (inmode, in_rtx, goal_class, "") 1039 : lra_create_new_reg_with_unique_value (outmode, out_rtx, 1040 goal_class, "")); 1041 } 1042 /* In operand can be got from transformations before processing insn 1043 constraints. One example of such transformations is subreg 1044 reloading (see function simplify_operand_subreg). The new 1045 pseudos created by the transformations might have inaccurate 1046 class (ALL_REGS) and we should make their classes more 1047 accurate. */ 1048 narrow_reload_pseudo_class (in_rtx, goal_class); 1049 lra_emit_move (copy_rtx (new_in_reg), in_rtx); 1050 *before = get_insns (); 1051 end_sequence (); 1052 /* Add the new pseudo to consider values of subsequent input reload 1053 pseudos. */ 1054 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); 1055 curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx; 1056 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; 1057 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; 1058 for (i = 0; (in = ins[i]) >= 0; i++) 1059 { 1060 lra_assert 1061 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode 1062 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); 1063 *curr_id->operand_loc[in] = new_in_reg; 1064 } 1065 lra_update_dups (curr_id, ins); 1066 if (out < 0) 1067 return; 1068 /* See a comment for the input operand above. */ 1069 narrow_reload_pseudo_class (out_rtx, goal_class); 1070 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) 1071 { 1072 start_sequence (); 1073 lra_emit_move (out_rtx, copy_rtx (new_out_reg)); 1074 emit_insn (*after); 1075 *after = get_insns (); 1076 end_sequence (); 1077 } 1078 *curr_id->operand_loc[out] = new_out_reg; 1079 lra_update_dup (curr_id, out); 1080 } 1081 1082 /* Return register class which is union of all reg classes in insn 1083 constraint alternative string starting with P. */ 1084 static enum reg_class 1085 reg_class_from_constraints (const char *p) 1086 { 1087 int c, len; 1088 enum reg_class op_class = NO_REGS; 1089 1090 do 1091 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) 1092 { 1093 case '#': 1094 case ',': 1095 return op_class; 1096 1097 case 'g': 1098 op_class = reg_class_subunion[op_class][GENERAL_REGS]; 1099 break; 1100 1101 default: 1102 enum constraint_num cn = lookup_constraint (p); 1103 enum reg_class cl = reg_class_for_constraint (cn); 1104 if (cl == NO_REGS) 1105 { 1106 if (insn_extra_address_constraint (cn)) 1107 op_class 1108 = (reg_class_subunion 1109 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 1110 ADDRESS, SCRATCH)]); 1111 break; 1112 } 1113 1114 op_class = reg_class_subunion[op_class][cl]; 1115 break; 1116 } 1117 while ((p += len), c); 1118 return op_class; 1119 } 1120 1121 /* If OP is a register, return the class of the register as per 1122 get_reg_class, otherwise return NO_REGS. */ 1123 static inline enum reg_class 1124 get_op_class (rtx op) 1125 { 1126 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; 1127 } 1128 1129 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo 1130 otherwise. If modes of MEM_PSEUDO and VAL are different, use 1131 SUBREG for VAL to make them equal. */ 1132 static rtx_insn * 1133 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) 1134 { 1135 if (GET_MODE (mem_pseudo) != GET_MODE (val)) 1136 { 1137 /* Usually size of mem_pseudo is greater than val size but in 1138 rare cases it can be less as it can be defined by target 1139 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ 1140 if (! MEM_P (val)) 1141 { 1142 val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo), 1143 GET_CODE (val) == SUBREG 1144 ? SUBREG_REG (val) : val); 1145 LRA_SUBREG_P (val) = 1; 1146 } 1147 else 1148 { 1149 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); 1150 LRA_SUBREG_P (mem_pseudo) = 1; 1151 } 1152 } 1153 return to_p ? gen_move_insn (mem_pseudo, val) 1154 : gen_move_insn (val, mem_pseudo); 1155 } 1156 1157 /* Process a special case insn (register move), return true if we 1158 don't need to process it anymore. INSN should be a single set 1159 insn. Set up that RTL was changed through CHANGE_P and macro 1160 SECONDARY_MEMORY_NEEDED says to use secondary memory through 1161 SEC_MEM_P. */ 1162 static bool 1163 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) 1164 { 1165 int sregno, dregno; 1166 rtx dest, src, dreg, sreg, new_reg, scratch_reg; 1167 rtx_insn *before; 1168 enum reg_class dclass, sclass, secondary_class; 1169 secondary_reload_info sri; 1170 1171 lra_assert (curr_insn_set != NULL_RTX); 1172 dreg = dest = SET_DEST (curr_insn_set); 1173 sreg = src = SET_SRC (curr_insn_set); 1174 if (GET_CODE (dest) == SUBREG) 1175 dreg = SUBREG_REG (dest); 1176 if (GET_CODE (src) == SUBREG) 1177 sreg = SUBREG_REG (src); 1178 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) 1179 return false; 1180 sclass = dclass = NO_REGS; 1181 if (REG_P (dreg)) 1182 dclass = get_reg_class (REGNO (dreg)); 1183 gcc_assert (dclass < LIM_REG_CLASSES); 1184 if (dclass == ALL_REGS) 1185 /* ALL_REGS is used for new pseudos created by transformations 1186 like reload of SUBREG_REG (see function 1187 simplify_operand_subreg). We don't know their class yet. We 1188 should figure out the class from processing the insn 1189 constraints not in this fast path function. Even if ALL_REGS 1190 were a right class for the pseudo, secondary_... hooks usually 1191 are not define for ALL_REGS. */ 1192 return false; 1193 if (REG_P (sreg)) 1194 sclass = get_reg_class (REGNO (sreg)); 1195 gcc_assert (sclass < LIM_REG_CLASSES); 1196 if (sclass == ALL_REGS) 1197 /* See comments above. */ 1198 return false; 1199 if (sclass == NO_REGS && dclass == NO_REGS) 1200 return false; 1201 #ifdef SECONDARY_MEMORY_NEEDED 1202 if (SECONDARY_MEMORY_NEEDED (sclass, dclass, GET_MODE (src)) 1203 #ifdef SECONDARY_MEMORY_NEEDED_MODE 1204 && ((sclass != NO_REGS && dclass != NO_REGS) 1205 || GET_MODE (src) != SECONDARY_MEMORY_NEEDED_MODE (GET_MODE (src))) 1206 #endif 1207 ) 1208 { 1209 *sec_mem_p = true; 1210 return false; 1211 } 1212 #endif 1213 if (! REG_P (dreg) || ! REG_P (sreg)) 1214 return false; 1215 sri.prev_sri = NULL; 1216 sri.icode = CODE_FOR_nothing; 1217 sri.extra_cost = 0; 1218 secondary_class = NO_REGS; 1219 /* Set up hard register for a reload pseudo for hook 1220 secondary_reload because some targets just ignore unassigned 1221 pseudos in the hook. */ 1222 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) 1223 { 1224 dregno = REGNO (dreg); 1225 reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; 1226 } 1227 else 1228 dregno = -1; 1229 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) 1230 { 1231 sregno = REGNO (sreg); 1232 reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; 1233 } 1234 else 1235 sregno = -1; 1236 if (sclass != NO_REGS) 1237 secondary_class 1238 = (enum reg_class) targetm.secondary_reload (false, dest, 1239 (reg_class_t) sclass, 1240 GET_MODE (src), &sri); 1241 if (sclass == NO_REGS 1242 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) 1243 && dclass != NO_REGS)) 1244 { 1245 enum reg_class old_sclass = secondary_class; 1246 secondary_reload_info old_sri = sri; 1247 1248 sri.prev_sri = NULL; 1249 sri.icode = CODE_FOR_nothing; 1250 sri.extra_cost = 0; 1251 secondary_class 1252 = (enum reg_class) targetm.secondary_reload (true, src, 1253 (reg_class_t) dclass, 1254 GET_MODE (src), &sri); 1255 /* Check the target hook consistency. */ 1256 lra_assert 1257 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) 1258 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) 1259 || (secondary_class == old_sclass && sri.icode == old_sri.icode)); 1260 } 1261 if (sregno >= 0) 1262 reg_renumber [sregno] = -1; 1263 if (dregno >= 0) 1264 reg_renumber [dregno] = -1; 1265 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) 1266 return false; 1267 *change_p = true; 1268 new_reg = NULL_RTX; 1269 if (secondary_class != NO_REGS) 1270 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, 1271 secondary_class, 1272 "secondary"); 1273 start_sequence (); 1274 if (sri.icode == CODE_FOR_nothing) 1275 lra_emit_move (new_reg, src); 1276 else 1277 { 1278 enum reg_class scratch_class; 1279 1280 scratch_class = (reg_class_from_constraints 1281 (insn_data[sri.icode].operand[2].constraint)); 1282 scratch_reg = (lra_create_new_reg_with_unique_value 1283 (insn_data[sri.icode].operand[2].mode, NULL_RTX, 1284 scratch_class, "scratch")); 1285 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, 1286 src, scratch_reg)); 1287 } 1288 before = get_insns (); 1289 end_sequence (); 1290 lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); 1291 if (new_reg != NULL_RTX) 1292 SET_SRC (curr_insn_set) = new_reg; 1293 else 1294 { 1295 if (lra_dump_file != NULL) 1296 { 1297 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); 1298 dump_insn_slim (lra_dump_file, curr_insn); 1299 } 1300 lra_set_insn_deleted (curr_insn); 1301 return true; 1302 } 1303 return false; 1304 } 1305 1306 /* The following data describe the result of process_alt_operands. 1307 The data are used in curr_insn_transform to generate reloads. */ 1308 1309 /* The chosen reg classes which should be used for the corresponding 1310 operands. */ 1311 static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; 1312 /* True if the operand should be the same as another operand and that 1313 other operand does not need a reload. */ 1314 static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; 1315 /* True if the operand does not need a reload. */ 1316 static bool goal_alt_win[MAX_RECOG_OPERANDS]; 1317 /* True if the operand can be offsetable memory. */ 1318 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; 1319 /* The number of an operand to which given operand can be matched to. */ 1320 static int goal_alt_matches[MAX_RECOG_OPERANDS]; 1321 /* The number of elements in the following array. */ 1322 static int goal_alt_dont_inherit_ops_num; 1323 /* Numbers of operands whose reload pseudos should not be inherited. */ 1324 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; 1325 /* True if the insn commutative operands should be swapped. */ 1326 static bool goal_alt_swapped; 1327 /* The chosen insn alternative. */ 1328 static int goal_alt_number; 1329 1330 /* True if the corresponding operand is the result of an equivalence 1331 substitution. */ 1332 static bool equiv_substition_p[MAX_RECOG_OPERANDS]; 1333 1334 /* The following five variables are used to choose the best insn 1335 alternative. They reflect final characteristics of the best 1336 alternative. */ 1337 1338 /* Number of necessary reloads and overall cost reflecting the 1339 previous value and other unpleasantness of the best alternative. */ 1340 static int best_losers, best_overall; 1341 /* Overall number hard registers used for reloads. For example, on 1342 some targets we need 2 general registers to reload DFmode and only 1343 one floating point register. */ 1344 static int best_reload_nregs; 1345 /* Overall number reflecting distances of previous reloading the same 1346 value. The distances are counted from the current BB start. It is 1347 used to improve inheritance chances. */ 1348 static int best_reload_sum; 1349 1350 /* True if the current insn should have no correspondingly input or 1351 output reloads. */ 1352 static bool no_input_reloads_p, no_output_reloads_p; 1353 1354 /* True if we swapped the commutative operands in the current 1355 insn. */ 1356 static int curr_swapped; 1357 1358 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a 1359 register of class CL. Add any input reloads to list BEFORE. AFTER 1360 is nonnull if *LOC is an automodified value; handle that case by 1361 adding the required output reloads to list AFTER. Return true if 1362 the RTL was changed. 1363 1364 if CHECK_ONLY_P is true, check that the *LOC is a correct address 1365 register. Return false if the address register is correct. */ 1366 static bool 1367 process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, 1368 enum reg_class cl) 1369 { 1370 int regno; 1371 enum reg_class rclass, new_class; 1372 rtx reg; 1373 rtx new_reg; 1374 machine_mode mode; 1375 bool subreg_p, before_p = false; 1376 1377 subreg_p = GET_CODE (*loc) == SUBREG; 1378 if (subreg_p) 1379 { 1380 reg = SUBREG_REG (*loc); 1381 mode = GET_MODE (reg); 1382 1383 /* For mode with size bigger than ptr_mode, there unlikely to be "mov" 1384 between two registers with different classes, but there normally will 1385 be "mov" which transfers element of vector register into the general 1386 register, and this normally will be a subreg which should be reloaded 1387 as a whole. This is particularly likely to be triggered when 1388 -fno-split-wide-types specified. */ 1389 if (!REG_P (reg) 1390 || in_class_p (reg, cl, &new_class) 1391 || GET_MODE_SIZE (mode) <= GET_MODE_SIZE (ptr_mode)) 1392 loc = &SUBREG_REG (*loc); 1393 } 1394 1395 reg = *loc; 1396 mode = GET_MODE (reg); 1397 if (! REG_P (reg)) 1398 { 1399 if (check_only_p) 1400 return true; 1401 /* Always reload memory in an address even if the target supports 1402 such addresses. */ 1403 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); 1404 before_p = true; 1405 } 1406 else 1407 { 1408 regno = REGNO (reg); 1409 rclass = get_reg_class (regno); 1410 if (! check_only_p 1411 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) 1412 { 1413 if (lra_dump_file != NULL) 1414 { 1415 fprintf (lra_dump_file, 1416 "Changing pseudo %d in address of insn %u on equiv ", 1417 REGNO (reg), INSN_UID (curr_insn)); 1418 dump_value_slim (lra_dump_file, *loc, 1); 1419 fprintf (lra_dump_file, "\n"); 1420 } 1421 *loc = copy_rtx (*loc); 1422 } 1423 if (*loc != reg || ! in_class_p (reg, cl, &new_class)) 1424 { 1425 if (check_only_p) 1426 return true; 1427 reg = *loc; 1428 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, 1429 mode, reg, cl, subreg_p, "address", &new_reg)) 1430 before_p = true; 1431 } 1432 else if (new_class != NO_REGS && rclass != new_class) 1433 { 1434 if (check_only_p) 1435 return true; 1436 lra_change_class (regno, new_class, " Change to", true); 1437 return false; 1438 } 1439 else 1440 return false; 1441 } 1442 if (before_p) 1443 { 1444 push_to_sequence (*before); 1445 lra_emit_move (new_reg, reg); 1446 *before = get_insns (); 1447 end_sequence (); 1448 } 1449 *loc = new_reg; 1450 if (after != NULL) 1451 { 1452 start_sequence (); 1453 lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); 1454 emit_insn (*after); 1455 *after = get_insns (); 1456 end_sequence (); 1457 } 1458 return true; 1459 } 1460 1461 /* Insert move insn in simplify_operand_subreg. BEFORE returns 1462 the insn to be inserted before curr insn. AFTER returns the 1463 the insn to be inserted after curr insn. ORIGREG and NEWREG 1464 are the original reg and new reg for reload. */ 1465 static void 1466 insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, 1467 rtx newreg) 1468 { 1469 if (before) 1470 { 1471 push_to_sequence (*before); 1472 lra_emit_move (newreg, origreg); 1473 *before = get_insns (); 1474 end_sequence (); 1475 } 1476 if (after) 1477 { 1478 start_sequence (); 1479 lra_emit_move (origreg, newreg); 1480 emit_insn (*after); 1481 *after = get_insns (); 1482 end_sequence (); 1483 } 1484 } 1485 1486 static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); 1487 static bool process_address (int, bool, rtx_insn **, rtx_insn **); 1488 1489 /* Make reloads for subreg in operand NOP with internal subreg mode 1490 REG_MODE, add new reloads for further processing. Return true if 1491 any change was done. */ 1492 static bool 1493 simplify_operand_subreg (int nop, machine_mode reg_mode) 1494 { 1495 int hard_regno; 1496 rtx_insn *before, *after; 1497 machine_mode mode, innermode; 1498 rtx reg, new_reg; 1499 rtx operand = *curr_id->operand_loc[nop]; 1500 enum reg_class regclass; 1501 enum op_type type; 1502 1503 before = after = NULL; 1504 1505 if (GET_CODE (operand) != SUBREG) 1506 return false; 1507 1508 mode = GET_MODE (operand); 1509 reg = SUBREG_REG (operand); 1510 innermode = GET_MODE (reg); 1511 type = curr_static_id->operand[nop].type; 1512 if (MEM_P (reg)) 1513 { 1514 const bool addr_was_valid 1515 = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg)); 1516 alter_subreg (curr_id->operand_loc[nop], false); 1517 rtx subst = *curr_id->operand_loc[nop]; 1518 lra_assert (MEM_P (subst)); 1519 1520 if (!addr_was_valid 1521 || valid_address_p (GET_MODE (subst), XEXP (subst, 0), 1522 MEM_ADDR_SPACE (subst)) 1523 || ((get_constraint_type (lookup_constraint 1524 (curr_static_id->operand[nop].constraint)) 1525 != CT_SPECIAL_MEMORY) 1526 /* We still can reload address and if the address is 1527 valid, we can remove subreg without reloading its 1528 inner memory. */ 1529 && valid_address_p (GET_MODE (subst), 1530 regno_reg_rtx 1531 [ira_class_hard_regs 1532 [base_reg_class (GET_MODE (subst), 1533 MEM_ADDR_SPACE (subst), 1534 ADDRESS, SCRATCH)][0]], 1535 MEM_ADDR_SPACE (subst)))) 1536 { 1537 /* If we change the address for a paradoxical subreg of memory, the 1538 new address might violate the necessary alignment or the access 1539 might be slow; take this into consideration. We need not worry 1540 about accesses beyond allocated memory for paradoxical memory 1541 subregs as we don't substitute such equiv memory (see processing 1542 equivalences in function lra_constraints) and because for spilled 1543 pseudos we allocate stack memory enough for the biggest 1544 corresponding paradoxical subreg. 1545 1546 However, do not blindly simplify a (subreg (mem ...)) for 1547 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk 1548 data into a register when the inner is narrower than outer or 1549 missing important data from memory when the inner is wider than 1550 outer. This rule only applies to modes that are no wider than 1551 a word. */ 1552 if (!(GET_MODE_PRECISION (mode) != GET_MODE_PRECISION (innermode) 1553 && GET_MODE_SIZE (mode) <= UNITS_PER_WORD 1554 && GET_MODE_SIZE (innermode) <= UNITS_PER_WORD 1555 && WORD_REGISTER_OPERATIONS) 1556 && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode) 1557 && SLOW_UNALIGNED_ACCESS (mode, MEM_ALIGN (subst))) 1558 || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) 1559 && SLOW_UNALIGNED_ACCESS (innermode, MEM_ALIGN (reg))))) 1560 return true; 1561 1562 *curr_id->operand_loc[nop] = operand; 1563 1564 /* But if the address was not valid, we cannot reload the MEM without 1565 reloading the address first. */ 1566 if (!addr_was_valid) 1567 process_address (nop, false, &before, &after); 1568 1569 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */ 1570 enum reg_class rclass 1571 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1572 if (get_reload_reg (curr_static_id->operand[nop].type, innermode, 1573 reg, rclass, TRUE, "slow mem", &new_reg)) 1574 { 1575 bool insert_before, insert_after; 1576 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); 1577 1578 insert_before = (type != OP_OUT 1579 || GET_MODE_SIZE (innermode) 1580 > GET_MODE_SIZE (mode)); 1581 insert_after = type != OP_IN; 1582 insert_move_for_subreg (insert_before ? &before : NULL, 1583 insert_after ? &after : NULL, 1584 reg, new_reg); 1585 } 1586 SUBREG_REG (operand) = new_reg; 1587 1588 /* Convert to MODE. */ 1589 reg = operand; 1590 rclass 1591 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1592 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, 1593 rclass, TRUE, "slow mem", &new_reg)) 1594 { 1595 bool insert_before, insert_after; 1596 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); 1597 1598 insert_before = type != OP_OUT; 1599 insert_after = type != OP_IN; 1600 insert_move_for_subreg (insert_before ? &before : NULL, 1601 insert_after ? &after : NULL, 1602 reg, new_reg); 1603 } 1604 *curr_id->operand_loc[nop] = new_reg; 1605 lra_process_new_insns (curr_insn, before, after, 1606 "Inserting slow mem reload"); 1607 return true; 1608 } 1609 1610 /* If the address was valid and became invalid, prefer to reload 1611 the memory. Typical case is when the index scale should 1612 correspond the memory. */ 1613 *curr_id->operand_loc[nop] = operand; 1614 /* Do not return false here as the MEM_P (reg) will be processed 1615 later in this function. */ 1616 } 1617 else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) 1618 { 1619 alter_subreg (curr_id->operand_loc[nop], false); 1620 return true; 1621 } 1622 else if (CONSTANT_P (reg)) 1623 { 1624 /* Try to simplify subreg of constant. It is usually result of 1625 equivalence substitution. */ 1626 if (innermode == VOIDmode 1627 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) 1628 innermode = curr_static_id->operand[nop].mode; 1629 if ((new_reg = simplify_subreg (mode, reg, innermode, 1630 SUBREG_BYTE (operand))) != NULL_RTX) 1631 { 1632 *curr_id->operand_loc[nop] = new_reg; 1633 return true; 1634 } 1635 } 1636 /* Put constant into memory when we have mixed modes. It generates 1637 a better code in most cases as it does not need a secondary 1638 reload memory. It also prevents LRA looping when LRA is using 1639 secondary reload memory again and again. */ 1640 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) 1641 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) 1642 { 1643 SUBREG_REG (operand) = force_const_mem (reg_mode, reg); 1644 alter_subreg (curr_id->operand_loc[nop], false); 1645 return true; 1646 } 1647 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or 1648 if there may be a problem accessing OPERAND in the outer 1649 mode. */ 1650 if ((REG_P (reg) 1651 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 1652 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 1653 /* Don't reload paradoxical subregs because we could be looping 1654 having repeatedly final regno out of hard regs range. */ 1655 && (hard_regno_nregs[hard_regno][innermode] 1656 >= hard_regno_nregs[hard_regno][mode]) 1657 && simplify_subreg_regno (hard_regno, innermode, 1658 SUBREG_BYTE (operand), mode) < 0 1659 /* Don't reload subreg for matching reload. It is actually 1660 valid subreg in LRA. */ 1661 && ! LRA_SUBREG_P (operand)) 1662 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) 1663 { 1664 enum reg_class rclass; 1665 1666 if (REG_P (reg)) 1667 /* There is a big probability that we will get the same class 1668 for the new pseudo and we will get the same insn which 1669 means infinite looping. So spill the new pseudo. */ 1670 rclass = NO_REGS; 1671 else 1672 /* The class will be defined later in curr_insn_transform. */ 1673 rclass 1674 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1675 1676 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, 1677 rclass, TRUE, "subreg reg", &new_reg)) 1678 { 1679 bool insert_before, insert_after; 1680 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); 1681 1682 insert_before = (type != OP_OUT 1683 || GET_MODE_SIZE (innermode) > GET_MODE_SIZE (mode)); 1684 insert_after = (type != OP_IN); 1685 insert_move_for_subreg (insert_before ? &before : NULL, 1686 insert_after ? &after : NULL, 1687 reg, new_reg); 1688 } 1689 SUBREG_REG (operand) = new_reg; 1690 lra_process_new_insns (curr_insn, before, after, 1691 "Inserting subreg reload"); 1692 return true; 1693 } 1694 /* Force a reload for a paradoxical subreg. For paradoxical subreg, 1695 IRA allocates hardreg to the inner pseudo reg according to its mode 1696 instead of the outermode, so the size of the hardreg may not be enough 1697 to contain the outermode operand, in that case we may need to insert 1698 reload for the reg. For the following two types of paradoxical subreg, 1699 we need to insert reload: 1700 1. If the op_type is OP_IN, and the hardreg could not be paired with 1701 other hardreg to contain the outermode operand 1702 (checked by in_hard_reg_set_p), we need to insert the reload. 1703 2. If the op_type is OP_OUT or OP_INOUT. 1704 1705 Here is a paradoxical subreg example showing how the reload is generated: 1706 1707 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) 1708 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} 1709 1710 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example 1711 here, if reg107 is assigned to hardreg R15, because R15 is the last 1712 hardreg, compiler cannot find another hardreg to pair with R15 to 1713 contain TImode data. So we insert a TImode reload reg180 for it. 1714 After reload is inserted: 1715 1716 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) 1717 (reg:DI 107 [ __comp ])) -1 1718 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) 1719 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} 1720 1721 Two reload hard registers will be allocated to reg180 to save TImode data 1722 in LRA_assign. */ 1723 else if (REG_P (reg) 1724 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 1725 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 1726 && (hard_regno_nregs[hard_regno][innermode] 1727 < hard_regno_nregs[hard_regno][mode]) 1728 && (regclass = lra_get_allocno_class (REGNO (reg))) 1729 && (type != OP_IN 1730 || !in_hard_reg_set_p (reg_class_contents[regclass], 1731 mode, hard_regno))) 1732 { 1733 /* The class will be defined later in curr_insn_transform. */ 1734 enum reg_class rclass 1735 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1736 1737 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, 1738 rclass, TRUE, "paradoxical subreg", &new_reg)) 1739 { 1740 rtx subreg; 1741 bool insert_before, insert_after; 1742 1743 PUT_MODE (new_reg, mode); 1744 subreg = gen_lowpart_SUBREG (innermode, new_reg); 1745 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); 1746 1747 insert_before = (type != OP_OUT); 1748 insert_after = (type != OP_IN); 1749 insert_move_for_subreg (insert_before ? &before : NULL, 1750 insert_after ? &after : NULL, 1751 reg, subreg); 1752 } 1753 SUBREG_REG (operand) = new_reg; 1754 lra_process_new_insns (curr_insn, before, after, 1755 "Inserting paradoxical subreg reload"); 1756 return true; 1757 } 1758 return false; 1759 } 1760 1761 /* Return TRUE if X refers for a hard register from SET. */ 1762 static bool 1763 uses_hard_regs_p (rtx x, HARD_REG_SET set) 1764 { 1765 int i, j, x_hard_regno; 1766 machine_mode mode; 1767 const char *fmt; 1768 enum rtx_code code; 1769 1770 if (x == NULL_RTX) 1771 return false; 1772 code = GET_CODE (x); 1773 mode = GET_MODE (x); 1774 if (code == SUBREG) 1775 { 1776 x = SUBREG_REG (x); 1777 code = GET_CODE (x); 1778 if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) 1779 mode = GET_MODE (x); 1780 } 1781 1782 if (REG_P (x)) 1783 { 1784 x_hard_regno = get_hard_regno (x, true); 1785 return (x_hard_regno >= 0 1786 && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); 1787 } 1788 if (MEM_P (x)) 1789 { 1790 struct address_info ad; 1791 1792 decompose_mem_address (&ad, x); 1793 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) 1794 return true; 1795 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) 1796 return true; 1797 } 1798 fmt = GET_RTX_FORMAT (code); 1799 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1800 { 1801 if (fmt[i] == 'e') 1802 { 1803 if (uses_hard_regs_p (XEXP (x, i), set)) 1804 return true; 1805 } 1806 else if (fmt[i] == 'E') 1807 { 1808 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1809 if (uses_hard_regs_p (XVECEXP (x, i, j), set)) 1810 return true; 1811 } 1812 } 1813 return false; 1814 } 1815 1816 /* Return true if OP is a spilled pseudo. */ 1817 static inline bool 1818 spilled_pseudo_p (rtx op) 1819 { 1820 return (REG_P (op) 1821 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); 1822 } 1823 1824 /* Return true if X is a general constant. */ 1825 static inline bool 1826 general_constant_p (rtx x) 1827 { 1828 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); 1829 } 1830 1831 static bool 1832 reg_in_class_p (rtx reg, enum reg_class cl) 1833 { 1834 if (cl == NO_REGS) 1835 return get_reg_class (REGNO (reg)) == NO_REGS; 1836 return in_class_p (reg, cl, NULL); 1837 } 1838 1839 /* Return true if SET of RCLASS contains no hard regs which can be 1840 used in MODE. */ 1841 static bool 1842 prohibited_class_reg_set_mode_p (enum reg_class rclass, 1843 HARD_REG_SET &set, 1844 enum machine_mode mode) 1845 { 1846 HARD_REG_SET temp; 1847 1848 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); 1849 COPY_HARD_REG_SET (temp, set); 1850 AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs); 1851 return (hard_reg_set_subset_p 1852 (temp, ira_prohibited_class_mode_regs[rclass][mode])); 1853 } 1854 1855 1856 /* Used to check validity info about small class input operands. It 1857 should be incremented at start of processing an insn 1858 alternative. */ 1859 static unsigned int curr_small_class_check = 0; 1860 1861 /* Update number of used inputs of class OP_CLASS for operand NOP. 1862 Return true if we have more such class operands than the number of 1863 available regs. */ 1864 static bool 1865 update_and_check_small_class_inputs (int nop, enum reg_class op_class) 1866 { 1867 static unsigned int small_class_check[LIM_REG_CLASSES]; 1868 static int small_class_input_nums[LIM_REG_CLASSES]; 1869 1870 if (SMALL_REGISTER_CLASS_P (op_class) 1871 /* We are interesting in classes became small because of fixing 1872 some hard regs, e.g. by an user through GCC options. */ 1873 && hard_reg_set_intersect_p (reg_class_contents[op_class], 1874 ira_no_alloc_regs) 1875 && (curr_static_id->operand[nop].type != OP_OUT 1876 || curr_static_id->operand[nop].early_clobber)) 1877 { 1878 if (small_class_check[op_class] == curr_small_class_check) 1879 small_class_input_nums[op_class]++; 1880 else 1881 { 1882 small_class_check[op_class] = curr_small_class_check; 1883 small_class_input_nums[op_class] = 1; 1884 } 1885 if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class]) 1886 return true; 1887 } 1888 return false; 1889 } 1890 1891 /* Major function to choose the current insn alternative and what 1892 operands should be reloaded and how. If ONLY_ALTERNATIVE is not 1893 negative we should consider only this alternative. Return false if 1894 we can not choose the alternative or find how to reload the 1895 operands. */ 1896 static bool 1897 process_alt_operands (int only_alternative) 1898 { 1899 bool ok_p = false; 1900 int nop, overall, nalt; 1901 int n_alternatives = curr_static_id->n_alternatives; 1902 int n_operands = curr_static_id->n_operands; 1903 /* LOSERS counts the operands that don't fit this alternative and 1904 would require loading. */ 1905 int losers; 1906 int addr_losers; 1907 /* REJECT is a count of how undesirable this alternative says it is 1908 if any reloading is required. If the alternative matches exactly 1909 then REJECT is ignored, but otherwise it gets this much counted 1910 against it in addition to the reloading needed. */ 1911 int reject; 1912 /* This is defined by '!' or '?' alternative constraint and added to 1913 reject. But in some cases it can be ignored. */ 1914 int static_reject; 1915 int op_reject; 1916 /* The number of elements in the following array. */ 1917 int early_clobbered_regs_num; 1918 /* Numbers of operands which are early clobber registers. */ 1919 int early_clobbered_nops[MAX_RECOG_OPERANDS]; 1920 enum reg_class curr_alt[MAX_RECOG_OPERANDS]; 1921 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; 1922 bool curr_alt_match_win[MAX_RECOG_OPERANDS]; 1923 bool curr_alt_win[MAX_RECOG_OPERANDS]; 1924 bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; 1925 int curr_alt_matches[MAX_RECOG_OPERANDS]; 1926 /* The number of elements in the following array. */ 1927 int curr_alt_dont_inherit_ops_num; 1928 /* Numbers of operands whose reload pseudos should not be inherited. */ 1929 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; 1930 rtx op; 1931 /* The register when the operand is a subreg of register, otherwise the 1932 operand itself. */ 1933 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; 1934 /* The register if the operand is a register or subreg of register, 1935 otherwise NULL. */ 1936 rtx operand_reg[MAX_RECOG_OPERANDS]; 1937 int hard_regno[MAX_RECOG_OPERANDS]; 1938 machine_mode biggest_mode[MAX_RECOG_OPERANDS]; 1939 int reload_nregs, reload_sum; 1940 bool costly_p; 1941 enum reg_class cl; 1942 1943 /* Calculate some data common for all alternatives to speed up the 1944 function. */ 1945 for (nop = 0; nop < n_operands; nop++) 1946 { 1947 rtx reg; 1948 1949 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; 1950 /* The real hard regno of the operand after the allocation. */ 1951 hard_regno[nop] = get_hard_regno (op, true); 1952 1953 operand_reg[nop] = reg = op; 1954 biggest_mode[nop] = GET_MODE (op); 1955 if (GET_CODE (op) == SUBREG) 1956 { 1957 operand_reg[nop] = reg = SUBREG_REG (op); 1958 if (GET_MODE_SIZE (biggest_mode[nop]) 1959 < GET_MODE_SIZE (GET_MODE (reg))) 1960 biggest_mode[nop] = GET_MODE (reg); 1961 } 1962 if (! REG_P (reg)) 1963 operand_reg[nop] = NULL_RTX; 1964 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER 1965 || ((int) REGNO (reg) 1966 == lra_get_elimination_hard_regno (REGNO (reg)))) 1967 no_subreg_reg_operand[nop] = reg; 1968 else 1969 operand_reg[nop] = no_subreg_reg_operand[nop] 1970 /* Just use natural mode for elimination result. It should 1971 be enough for extra constraints hooks. */ 1972 = regno_reg_rtx[hard_regno[nop]]; 1973 } 1974 1975 /* The constraints are made of several alternatives. Each operand's 1976 constraint looks like foo,bar,... with commas separating the 1977 alternatives. The first alternatives for all operands go 1978 together, the second alternatives go together, etc. 1979 1980 First loop over alternatives. */ 1981 alternative_mask preferred = curr_id->preferred_alternatives; 1982 if (only_alternative >= 0) 1983 preferred &= ALTERNATIVE_BIT (only_alternative); 1984 1985 for (nalt = 0; nalt < n_alternatives; nalt++) 1986 { 1987 /* Loop over operands for one constraint alternative. */ 1988 if (!TEST_BIT (preferred, nalt)) 1989 continue; 1990 1991 curr_small_class_check++; 1992 overall = losers = addr_losers = 0; 1993 static_reject = reject = reload_nregs = reload_sum = 0; 1994 for (nop = 0; nop < n_operands; nop++) 1995 { 1996 int inc = (curr_static_id 1997 ->operand_alternative[nalt * n_operands + nop].reject); 1998 if (lra_dump_file != NULL && inc != 0) 1999 fprintf (lra_dump_file, 2000 " Staticly defined alt reject+=%d\n", inc); 2001 static_reject += inc; 2002 } 2003 reject += static_reject; 2004 early_clobbered_regs_num = 0; 2005 2006 for (nop = 0; nop < n_operands; nop++) 2007 { 2008 const char *p; 2009 char *end; 2010 int len, c, m, i, opalt_num, this_alternative_matches; 2011 bool win, did_match, offmemok, early_clobber_p; 2012 /* false => this operand can be reloaded somehow for this 2013 alternative. */ 2014 bool badop; 2015 /* true => this operand can be reloaded if the alternative 2016 allows regs. */ 2017 bool winreg; 2018 /* True if a constant forced into memory would be OK for 2019 this operand. */ 2020 bool constmemok; 2021 enum reg_class this_alternative, this_costly_alternative; 2022 HARD_REG_SET this_alternative_set, this_costly_alternative_set; 2023 bool this_alternative_match_win, this_alternative_win; 2024 bool this_alternative_offmemok; 2025 bool scratch_p; 2026 machine_mode mode; 2027 enum constraint_num cn; 2028 2029 opalt_num = nalt * n_operands + nop; 2030 if (curr_static_id->operand_alternative[opalt_num].anything_ok) 2031 { 2032 /* Fast track for no constraints at all. */ 2033 curr_alt[nop] = NO_REGS; 2034 CLEAR_HARD_REG_SET (curr_alt_set[nop]); 2035 curr_alt_win[nop] = true; 2036 curr_alt_match_win[nop] = false; 2037 curr_alt_offmemok[nop] = false; 2038 curr_alt_matches[nop] = -1; 2039 continue; 2040 } 2041 2042 op = no_subreg_reg_operand[nop]; 2043 mode = curr_operand_mode[nop]; 2044 2045 win = did_match = winreg = offmemok = constmemok = false; 2046 badop = true; 2047 2048 early_clobber_p = false; 2049 p = curr_static_id->operand_alternative[opalt_num].constraint; 2050 2051 this_costly_alternative = this_alternative = NO_REGS; 2052 /* We update set of possible hard regs besides its class 2053 because reg class might be inaccurate. For example, 2054 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM 2055 is translated in HI_REGS because classes are merged by 2056 pairs and there is no accurate intermediate class. */ 2057 CLEAR_HARD_REG_SET (this_alternative_set); 2058 CLEAR_HARD_REG_SET (this_costly_alternative_set); 2059 this_alternative_win = false; 2060 this_alternative_match_win = false; 2061 this_alternative_offmemok = false; 2062 this_alternative_matches = -1; 2063 2064 /* An empty constraint should be excluded by the fast 2065 track. */ 2066 lra_assert (*p != 0 && *p != ','); 2067 2068 op_reject = 0; 2069 /* Scan this alternative's specs for this operand; set WIN 2070 if the operand fits any letter in this alternative. 2071 Otherwise, clear BADOP if this operand could fit some 2072 letter after reloads, or set WINREG if this operand could 2073 fit after reloads provided the constraint allows some 2074 registers. */ 2075 costly_p = false; 2076 do 2077 { 2078 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) 2079 { 2080 case '\0': 2081 len = 0; 2082 break; 2083 case ',': 2084 c = '\0'; 2085 break; 2086 2087 case '&': 2088 early_clobber_p = true; 2089 break; 2090 2091 case '$': 2092 op_reject += LRA_MAX_REJECT; 2093 break; 2094 case '^': 2095 op_reject += LRA_LOSER_COST_FACTOR; 2096 break; 2097 2098 case '#': 2099 /* Ignore rest of this alternative. */ 2100 c = '\0'; 2101 break; 2102 2103 case '0': case '1': case '2': case '3': case '4': 2104 case '5': case '6': case '7': case '8': case '9': 2105 { 2106 int m_hregno; 2107 bool match_p; 2108 2109 m = strtoul (p, &end, 10); 2110 p = end; 2111 len = 0; 2112 lra_assert (nop > m); 2113 2114 this_alternative_matches = m; 2115 m_hregno = get_hard_regno (*curr_id->operand_loc[m], false); 2116 /* We are supposed to match a previous operand. 2117 If we do, we win if that one did. If we do 2118 not, count both of the operands as losers. 2119 (This is too conservative, since most of the 2120 time only a single reload insn will be needed 2121 to make the two operands win. As a result, 2122 this alternative may be rejected when it is 2123 actually desirable.) */ 2124 match_p = false; 2125 if (operands_match_p (*curr_id->operand_loc[nop], 2126 *curr_id->operand_loc[m], m_hregno)) 2127 { 2128 /* We should reject matching of an early 2129 clobber operand if the matching operand is 2130 not dying in the insn. */ 2131 if (! curr_static_id->operand[m].early_clobber 2132 || operand_reg[nop] == NULL_RTX 2133 || (find_regno_note (curr_insn, REG_DEAD, 2134 REGNO (op)) 2135 || REGNO (op) == REGNO (operand_reg[m]))) 2136 match_p = true; 2137 } 2138 if (match_p) 2139 { 2140 /* If we are matching a non-offsettable 2141 address where an offsettable address was 2142 expected, then we must reject this 2143 combination, because we can't reload 2144 it. */ 2145 if (curr_alt_offmemok[m] 2146 && MEM_P (*curr_id->operand_loc[m]) 2147 && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) 2148 continue; 2149 } 2150 else 2151 { 2152 /* Operands don't match. Both operands must 2153 allow a reload register, otherwise we 2154 cannot make them match. */ 2155 if (curr_alt[m] == NO_REGS) 2156 break; 2157 /* Retroactively mark the operand we had to 2158 match as a loser, if it wasn't already and 2159 it wasn't matched to a register constraint 2160 (e.g it might be matched by memory). */ 2161 if (curr_alt_win[m] 2162 && (operand_reg[m] == NULL_RTX 2163 || hard_regno[m] < 0)) 2164 { 2165 losers++; 2166 reload_nregs 2167 += (ira_reg_class_max_nregs[curr_alt[m]] 2168 [GET_MODE (*curr_id->operand_loc[m])]); 2169 } 2170 2171 /* Prefer matching earlyclobber alternative as 2172 it results in less hard regs required for 2173 the insn than a non-matching earlyclobber 2174 alternative. */ 2175 if (curr_static_id->operand[m].early_clobber) 2176 { 2177 if (lra_dump_file != NULL) 2178 fprintf 2179 (lra_dump_file, 2180 " %d Matching earlyclobber alt:" 2181 " reject--\n", 2182 nop); 2183 reject--; 2184 } 2185 /* Otherwise we prefer no matching 2186 alternatives because it gives more freedom 2187 in RA. */ 2188 else if (operand_reg[nop] == NULL_RTX 2189 || (find_regno_note (curr_insn, REG_DEAD, 2190 REGNO (operand_reg[nop])) 2191 == NULL_RTX)) 2192 { 2193 if (lra_dump_file != NULL) 2194 fprintf 2195 (lra_dump_file, 2196 " %d Matching alt: reject+=2\n", 2197 nop); 2198 reject += 2; 2199 } 2200 } 2201 /* If we have to reload this operand and some 2202 previous operand also had to match the same 2203 thing as this operand, we don't know how to do 2204 that. */ 2205 if (!match_p || !curr_alt_win[m]) 2206 { 2207 for (i = 0; i < nop; i++) 2208 if (curr_alt_matches[i] == m) 2209 break; 2210 if (i < nop) 2211 break; 2212 } 2213 else 2214 did_match = true; 2215 2216 /* This can be fixed with reloads if the operand 2217 we are supposed to match can be fixed with 2218 reloads. */ 2219 badop = false; 2220 this_alternative = curr_alt[m]; 2221 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); 2222 winreg = this_alternative != NO_REGS; 2223 break; 2224 } 2225 2226 case 'g': 2227 if (MEM_P (op) 2228 || general_constant_p (op) 2229 || spilled_pseudo_p (op)) 2230 win = true; 2231 cl = GENERAL_REGS; 2232 goto reg; 2233 2234 default: 2235 cn = lookup_constraint (p); 2236 switch (get_constraint_type (cn)) 2237 { 2238 case CT_REGISTER: 2239 cl = reg_class_for_constraint (cn); 2240 if (cl != NO_REGS) 2241 goto reg; 2242 break; 2243 2244 case CT_CONST_INT: 2245 if (CONST_INT_P (op) 2246 && insn_const_int_ok_for_constraint (INTVAL (op), cn)) 2247 win = true; 2248 break; 2249 2250 case CT_MEMORY: 2251 if (MEM_P (op) 2252 && satisfies_memory_constraint_p (op, cn)) 2253 win = true; 2254 else if (spilled_pseudo_p (op)) 2255 win = true; 2256 2257 /* If we didn't already win, we can reload constants 2258 via force_const_mem or put the pseudo value into 2259 memory, or make other memory by reloading the 2260 address like for 'o'. */ 2261 if (CONST_POOL_OK_P (mode, op) 2262 || MEM_P (op) || REG_P (op) 2263 /* We can restore the equiv insn by a 2264 reload. */ 2265 || equiv_substition_p[nop]) 2266 badop = false; 2267 constmemok = true; 2268 offmemok = true; 2269 break; 2270 2271 case CT_ADDRESS: 2272 /* If we didn't already win, we can reload the address 2273 into a base register. */ 2274 if (satisfies_address_constraint_p (op, cn)) 2275 win = true; 2276 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 2277 ADDRESS, SCRATCH); 2278 badop = false; 2279 goto reg; 2280 2281 case CT_FIXED_FORM: 2282 if (constraint_satisfied_p (op, cn)) 2283 win = true; 2284 break; 2285 2286 case CT_SPECIAL_MEMORY: 2287 if (MEM_P (op) 2288 && satisfies_memory_constraint_p (op, cn)) 2289 win = true; 2290 else if (spilled_pseudo_p (op)) 2291 win = true; 2292 break; 2293 } 2294 break; 2295 2296 reg: 2297 this_alternative = reg_class_subunion[this_alternative][cl]; 2298 IOR_HARD_REG_SET (this_alternative_set, 2299 reg_class_contents[cl]); 2300 if (costly_p) 2301 { 2302 this_costly_alternative 2303 = reg_class_subunion[this_costly_alternative][cl]; 2304 IOR_HARD_REG_SET (this_costly_alternative_set, 2305 reg_class_contents[cl]); 2306 } 2307 if (mode == BLKmode) 2308 break; 2309 winreg = true; 2310 if (REG_P (op)) 2311 { 2312 if (hard_regno[nop] >= 0 2313 && in_hard_reg_set_p (this_alternative_set, 2314 mode, hard_regno[nop])) 2315 win = true; 2316 else if (hard_regno[nop] < 0 2317 && in_class_p (op, this_alternative, NULL)) 2318 win = true; 2319 } 2320 break; 2321 } 2322 if (c != ' ' && c != '\t') 2323 costly_p = c == '*'; 2324 } 2325 while ((p += len), c); 2326 2327 scratch_p = (operand_reg[nop] != NULL_RTX 2328 && lra_former_scratch_p (REGNO (operand_reg[nop]))); 2329 /* Record which operands fit this alternative. */ 2330 if (win) 2331 { 2332 this_alternative_win = true; 2333 if (operand_reg[nop] != NULL_RTX) 2334 { 2335 if (hard_regno[nop] >= 0) 2336 { 2337 if (in_hard_reg_set_p (this_costly_alternative_set, 2338 mode, hard_regno[nop])) 2339 { 2340 if (lra_dump_file != NULL) 2341 fprintf (lra_dump_file, 2342 " %d Costly set: reject++\n", 2343 nop); 2344 reject++; 2345 } 2346 } 2347 else 2348 { 2349 /* Prefer won reg to spilled pseudo under other 2350 equal conditions for possibe inheritance. */ 2351 if (! scratch_p) 2352 { 2353 if (lra_dump_file != NULL) 2354 fprintf 2355 (lra_dump_file, 2356 " %d Non pseudo reload: reject++\n", 2357 nop); 2358 reject++; 2359 } 2360 if (in_class_p (operand_reg[nop], 2361 this_costly_alternative, NULL)) 2362 { 2363 if (lra_dump_file != NULL) 2364 fprintf 2365 (lra_dump_file, 2366 " %d Non pseudo costly reload:" 2367 " reject++\n", 2368 nop); 2369 reject++; 2370 } 2371 } 2372 /* We simulate the behavior of old reload here. 2373 Although scratches need hard registers and it 2374 might result in spilling other pseudos, no reload 2375 insns are generated for the scratches. So it 2376 might cost something but probably less than old 2377 reload pass believes. */ 2378 if (scratch_p) 2379 { 2380 if (lra_dump_file != NULL) 2381 fprintf (lra_dump_file, 2382 " %d Scratch win: reject+=2\n", 2383 nop); 2384 reject += 2; 2385 } 2386 } 2387 } 2388 else if (did_match) 2389 this_alternative_match_win = true; 2390 else 2391 { 2392 int const_to_mem = 0; 2393 bool no_regs_p; 2394 2395 reject += op_reject; 2396 /* Never do output reload of stack pointer. It makes 2397 impossible to do elimination when SP is changed in 2398 RTL. */ 2399 if (op == stack_pointer_rtx && ! frame_pointer_needed 2400 && curr_static_id->operand[nop].type != OP_IN) 2401 goto fail; 2402 2403 /* If this alternative asks for a specific reg class, see if there 2404 is at least one allocatable register in that class. */ 2405 no_regs_p 2406 = (this_alternative == NO_REGS 2407 || (hard_reg_set_subset_p 2408 (reg_class_contents[this_alternative], 2409 lra_no_alloc_regs))); 2410 2411 /* For asms, verify that the class for this alternative is possible 2412 for the mode that is specified. */ 2413 if (!no_regs_p && INSN_CODE (curr_insn) < 0) 2414 { 2415 int i; 2416 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2417 if (HARD_REGNO_MODE_OK (i, mode) 2418 && in_hard_reg_set_p (reg_class_contents[this_alternative], 2419 mode, i)) 2420 break; 2421 if (i == FIRST_PSEUDO_REGISTER) 2422 winreg = false; 2423 } 2424 2425 /* If this operand accepts a register, and if the 2426 register class has at least one allocatable register, 2427 then this operand can be reloaded. */ 2428 if (winreg && !no_regs_p) 2429 badop = false; 2430 2431 if (badop) 2432 { 2433 if (lra_dump_file != NULL) 2434 fprintf (lra_dump_file, 2435 " alt=%d: Bad operand -- refuse\n", 2436 nalt); 2437 goto fail; 2438 } 2439 2440 if (this_alternative != NO_REGS) 2441 { 2442 HARD_REG_SET available_regs; 2443 2444 COPY_HARD_REG_SET (available_regs, 2445 reg_class_contents[this_alternative]); 2446 AND_COMPL_HARD_REG_SET 2447 (available_regs, 2448 ira_prohibited_class_mode_regs[this_alternative][mode]); 2449 AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs); 2450 if (hard_reg_set_empty_p (available_regs)) 2451 { 2452 /* There are no hard regs holding a value of given 2453 mode. */ 2454 if (offmemok) 2455 { 2456 this_alternative = NO_REGS; 2457 if (lra_dump_file != NULL) 2458 fprintf (lra_dump_file, 2459 " %d Using memory because of" 2460 " a bad mode: reject+=2\n", 2461 nop); 2462 reject += 2; 2463 } 2464 else 2465 { 2466 if (lra_dump_file != NULL) 2467 fprintf (lra_dump_file, 2468 " alt=%d: Wrong mode -- refuse\n", 2469 nalt); 2470 goto fail; 2471 } 2472 } 2473 } 2474 2475 /* If not assigned pseudo has a class which a subset of 2476 required reg class, it is a less costly alternative 2477 as the pseudo still can get a hard reg of necessary 2478 class. */ 2479 if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 2480 && (cl = get_reg_class (REGNO (op))) != NO_REGS 2481 && ira_class_subset_p[this_alternative][cl]) 2482 { 2483 if (lra_dump_file != NULL) 2484 fprintf 2485 (lra_dump_file, 2486 " %d Super set class reg: reject-=3\n", nop); 2487 reject -= 3; 2488 } 2489 2490 this_alternative_offmemok = offmemok; 2491 if (this_costly_alternative != NO_REGS) 2492 { 2493 if (lra_dump_file != NULL) 2494 fprintf (lra_dump_file, 2495 " %d Costly loser: reject++\n", nop); 2496 reject++; 2497 } 2498 /* If the operand is dying, has a matching constraint, 2499 and satisfies constraints of the matched operand 2500 which failed to satisfy the own constraints, most probably 2501 the reload for this operand will be gone. */ 2502 if (this_alternative_matches >= 0 2503 && !curr_alt_win[this_alternative_matches] 2504 && REG_P (op) 2505 && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) 2506 && (hard_regno[nop] >= 0 2507 ? in_hard_reg_set_p (this_alternative_set, 2508 mode, hard_regno[nop]) 2509 : in_class_p (op, this_alternative, NULL))) 2510 { 2511 if (lra_dump_file != NULL) 2512 fprintf 2513 (lra_dump_file, 2514 " %d Dying matched operand reload: reject++\n", 2515 nop); 2516 reject++; 2517 } 2518 else 2519 { 2520 /* Strict_low_part requires to reload the register 2521 not the sub-register. In this case we should 2522 check that a final reload hard reg can hold the 2523 value mode. */ 2524 if (curr_static_id->operand[nop].strict_low 2525 && REG_P (op) 2526 && hard_regno[nop] < 0 2527 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG 2528 && ira_class_hard_regs_num[this_alternative] > 0 2529 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs 2530 [this_alternative][0], 2531 GET_MODE 2532 (*curr_id->operand_loc[nop]))) 2533 { 2534 if (lra_dump_file != NULL) 2535 fprintf 2536 (lra_dump_file, 2537 " alt=%d: Strict low subreg reload -- refuse\n", 2538 nalt); 2539 goto fail; 2540 } 2541 losers++; 2542 } 2543 if (operand_reg[nop] != NULL_RTX 2544 /* Output operands and matched input operands are 2545 not inherited. The following conditions do not 2546 exactly describe the previous statement but they 2547 are pretty close. */ 2548 && curr_static_id->operand[nop].type != OP_OUT 2549 && (this_alternative_matches < 0 2550 || curr_static_id->operand[nop].type != OP_IN)) 2551 { 2552 int last_reload = (lra_reg_info[ORIGINAL_REGNO 2553 (operand_reg[nop])] 2554 .last_reload); 2555 2556 /* The value of reload_sum has sense only if we 2557 process insns in their order. It happens only on 2558 the first constraints sub-pass when we do most of 2559 reload work. */ 2560 if (lra_constraint_iter == 1 && last_reload > bb_reload_num) 2561 reload_sum += last_reload - bb_reload_num; 2562 } 2563 /* If this is a constant that is reloaded into the 2564 desired class by copying it to memory first, count 2565 that as another reload. This is consistent with 2566 other code and is required to avoid choosing another 2567 alternative when the constant is moved into memory. 2568 Note that the test here is precisely the same as in 2569 the code below that calls force_const_mem. */ 2570 if (CONST_POOL_OK_P (mode, op) 2571 && ((targetm.preferred_reload_class 2572 (op, this_alternative) == NO_REGS) 2573 || no_input_reloads_p)) 2574 { 2575 const_to_mem = 1; 2576 if (! no_regs_p) 2577 losers++; 2578 } 2579 2580 /* Alternative loses if it requires a type of reload not 2581 permitted for this insn. We can always reload 2582 objects with a REG_UNUSED note. */ 2583 if ((curr_static_id->operand[nop].type != OP_IN 2584 && no_output_reloads_p 2585 && ! find_reg_note (curr_insn, REG_UNUSED, op)) 2586 || (curr_static_id->operand[nop].type != OP_OUT 2587 && no_input_reloads_p && ! const_to_mem) 2588 || (this_alternative_matches >= 0 2589 && (no_input_reloads_p 2590 || (no_output_reloads_p 2591 && (curr_static_id->operand 2592 [this_alternative_matches].type != OP_IN) 2593 && ! find_reg_note (curr_insn, REG_UNUSED, 2594 no_subreg_reg_operand 2595 [this_alternative_matches]))))) 2596 { 2597 if (lra_dump_file != NULL) 2598 fprintf 2599 (lra_dump_file, 2600 " alt=%d: No input/otput reload -- refuse\n", 2601 nalt); 2602 goto fail; 2603 } 2604 2605 /* Alternative loses if it required class pseudo can not 2606 hold value of required mode. Such insns can be 2607 described by insn definitions with mode iterators. */ 2608 if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode 2609 && ! hard_reg_set_empty_p (this_alternative_set) 2610 /* It is common practice for constraints to use a 2611 class which does not have actually enough regs to 2612 hold the value (e.g. x86 AREG for mode requiring 2613 more one general reg). Therefore we have 2 2614 conditions to check that the reload pseudo can 2615 not hold the mode value. */ 2616 && ! HARD_REGNO_MODE_OK (ira_class_hard_regs 2617 [this_alternative][0], 2618 GET_MODE (*curr_id->operand_loc[nop])) 2619 /* The above condition is not enough as the first 2620 reg in ira_class_hard_regs can be not aligned for 2621 multi-words mode values. */ 2622 && (prohibited_class_reg_set_mode_p 2623 (this_alternative, this_alternative_set, 2624 GET_MODE (*curr_id->operand_loc[nop])))) 2625 { 2626 if (lra_dump_file != NULL) 2627 fprintf (lra_dump_file, 2628 " alt=%d: reload pseudo for op %d " 2629 " can not hold the mode value -- refuse\n", 2630 nalt, nop); 2631 goto fail; 2632 } 2633 2634 /* Check strong discouragement of reload of non-constant 2635 into class THIS_ALTERNATIVE. */ 2636 if (! CONSTANT_P (op) && ! no_regs_p 2637 && (targetm.preferred_reload_class 2638 (op, this_alternative) == NO_REGS 2639 || (curr_static_id->operand[nop].type == OP_OUT 2640 && (targetm.preferred_output_reload_class 2641 (op, this_alternative) == NO_REGS)))) 2642 { 2643 if (lra_dump_file != NULL) 2644 fprintf (lra_dump_file, 2645 " %d Non-prefered reload: reject+=%d\n", 2646 nop, LRA_MAX_REJECT); 2647 reject += LRA_MAX_REJECT; 2648 } 2649 2650 if (! (MEM_P (op) && offmemok) 2651 && ! (const_to_mem && constmemok)) 2652 { 2653 /* We prefer to reload pseudos over reloading other 2654 things, since such reloads may be able to be 2655 eliminated later. So bump REJECT in other cases. 2656 Don't do this in the case where we are forcing a 2657 constant into memory and it will then win since 2658 we don't want to have a different alternative 2659 match then. */ 2660 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) 2661 { 2662 if (lra_dump_file != NULL) 2663 fprintf 2664 (lra_dump_file, 2665 " %d Non-pseudo reload: reject+=2\n", 2666 nop); 2667 reject += 2; 2668 } 2669 2670 if (! no_regs_p) 2671 reload_nregs 2672 += ira_reg_class_max_nregs[this_alternative][mode]; 2673 2674 if (SMALL_REGISTER_CLASS_P (this_alternative)) 2675 { 2676 if (lra_dump_file != NULL) 2677 fprintf 2678 (lra_dump_file, 2679 " %d Small class reload: reject+=%d\n", 2680 nop, LRA_LOSER_COST_FACTOR / 2); 2681 reject += LRA_LOSER_COST_FACTOR / 2; 2682 } 2683 } 2684 2685 /* We are trying to spill pseudo into memory. It is 2686 usually more costly than moving to a hard register 2687 although it might takes the same number of 2688 reloads. 2689 2690 Non-pseudo spill may happen also. Suppose a target allows both 2691 register and memory in the operand constraint alternatives, 2692 then it's typical that an eliminable register has a substition 2693 of "base + offset" which can either be reloaded by a simple 2694 "new_reg <= base + offset" which will match the register 2695 constraint, or a similar reg addition followed by further spill 2696 to and reload from memory which will match the memory 2697 constraint, but this memory spill will be much more costly 2698 usually. 2699 2700 Code below increases the reject for both pseudo and non-pseudo 2701 spill. */ 2702 if (no_regs_p 2703 && !(MEM_P (op) && offmemok) 2704 && !(REG_P (op) && hard_regno[nop] < 0)) 2705 { 2706 if (lra_dump_file != NULL) 2707 fprintf 2708 (lra_dump_file, 2709 " %d Spill %spseudo into memory: reject+=3\n", 2710 nop, REG_P (op) ? "" : "Non-"); 2711 reject += 3; 2712 if (VECTOR_MODE_P (mode)) 2713 { 2714 /* Spilling vectors into memory is usually more 2715 costly as they contain big values. */ 2716 if (lra_dump_file != NULL) 2717 fprintf 2718 (lra_dump_file, 2719 " %d Spill vector pseudo: reject+=2\n", 2720 nop); 2721 reject += 2; 2722 } 2723 } 2724 2725 /* When we use an operand requiring memory in given 2726 alternative, the insn should write *and* read the 2727 value to/from memory it is costly in comparison with 2728 an insn alternative which does not use memory 2729 (e.g. register or immediate operand). We exclude 2730 memory operand for such case as we can satisfy the 2731 memory constraints by reloading address. */ 2732 if (no_regs_p && offmemok && !MEM_P (op)) 2733 { 2734 if (lra_dump_file != NULL) 2735 fprintf 2736 (lra_dump_file, 2737 " Using memory insn operand %d: reject+=3\n", 2738 nop); 2739 reject += 3; 2740 } 2741 2742 #ifdef SECONDARY_MEMORY_NEEDED 2743 /* If reload requires moving value through secondary 2744 memory, it will need one more insn at least. */ 2745 if (this_alternative != NO_REGS 2746 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS 2747 && ((curr_static_id->operand[nop].type != OP_OUT 2748 && SECONDARY_MEMORY_NEEDED (cl, this_alternative, 2749 GET_MODE (op))) 2750 || (curr_static_id->operand[nop].type != OP_IN 2751 && SECONDARY_MEMORY_NEEDED (this_alternative, cl, 2752 GET_MODE (op))))) 2753 losers++; 2754 #endif 2755 /* Input reloads can be inherited more often than output 2756 reloads can be removed, so penalize output 2757 reloads. */ 2758 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) 2759 { 2760 if (lra_dump_file != NULL) 2761 fprintf 2762 (lra_dump_file, 2763 " %d Non input pseudo reload: reject++\n", 2764 nop); 2765 reject++; 2766 } 2767 2768 if (MEM_P (op) && offmemok) 2769 addr_losers++; 2770 else if (curr_static_id->operand[nop].type == OP_INOUT) 2771 { 2772 if (lra_dump_file != NULL) 2773 fprintf 2774 (lra_dump_file, 2775 " %d Input/Output reload: reject+=%d\n", 2776 nop, LRA_LOSER_COST_FACTOR); 2777 reject += LRA_LOSER_COST_FACTOR; 2778 } 2779 } 2780 2781 if (early_clobber_p && ! scratch_p) 2782 { 2783 if (lra_dump_file != NULL) 2784 fprintf (lra_dump_file, 2785 " %d Early clobber: reject++\n", nop); 2786 reject++; 2787 } 2788 /* ??? We check early clobbers after processing all operands 2789 (see loop below) and there we update the costs more. 2790 Should we update the cost (may be approximately) here 2791 because of early clobber register reloads or it is a rare 2792 or non-important thing to be worth to do it. */ 2793 overall = (losers * LRA_LOSER_COST_FACTOR + reject 2794 - (addr_losers == losers ? static_reject : 0)); 2795 if ((best_losers == 0 || losers != 0) && best_overall < overall) 2796 { 2797 if (lra_dump_file != NULL) 2798 fprintf (lra_dump_file, 2799 " alt=%d,overall=%d,losers=%d -- refuse\n", 2800 nalt, overall, losers); 2801 goto fail; 2802 } 2803 2804 if (update_and_check_small_class_inputs (nop, this_alternative)) 2805 { 2806 if (lra_dump_file != NULL) 2807 fprintf (lra_dump_file, 2808 " alt=%d, not enough small class regs -- refuse\n", 2809 nalt); 2810 goto fail; 2811 } 2812 curr_alt[nop] = this_alternative; 2813 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); 2814 curr_alt_win[nop] = this_alternative_win; 2815 curr_alt_match_win[nop] = this_alternative_match_win; 2816 curr_alt_offmemok[nop] = this_alternative_offmemok; 2817 curr_alt_matches[nop] = this_alternative_matches; 2818 2819 if (this_alternative_matches >= 0 2820 && !did_match && !this_alternative_win) 2821 curr_alt_win[this_alternative_matches] = false; 2822 2823 if (early_clobber_p && operand_reg[nop] != NULL_RTX) 2824 early_clobbered_nops[early_clobbered_regs_num++] = nop; 2825 } 2826 2827 if (curr_insn_set != NULL_RTX && n_operands == 2 2828 /* Prevent processing non-move insns. */ 2829 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG 2830 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) 2831 && ((! curr_alt_win[0] && ! curr_alt_win[1] 2832 && REG_P (no_subreg_reg_operand[0]) 2833 && REG_P (no_subreg_reg_operand[1]) 2834 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) 2835 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) 2836 || (! curr_alt_win[0] && curr_alt_win[1] 2837 && REG_P (no_subreg_reg_operand[1]) 2838 /* Check that we reload memory not the memory 2839 address. */ 2840 && ! (curr_alt_offmemok[0] 2841 && MEM_P (no_subreg_reg_operand[0])) 2842 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) 2843 || (curr_alt_win[0] && ! curr_alt_win[1] 2844 && REG_P (no_subreg_reg_operand[0]) 2845 /* Check that we reload memory not the memory 2846 address. */ 2847 && ! (curr_alt_offmemok[1] 2848 && MEM_P (no_subreg_reg_operand[1])) 2849 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) 2850 && (! CONST_POOL_OK_P (curr_operand_mode[1], 2851 no_subreg_reg_operand[1]) 2852 || (targetm.preferred_reload_class 2853 (no_subreg_reg_operand[1], 2854 (enum reg_class) curr_alt[1]) != NO_REGS)) 2855 /* If it is a result of recent elimination in move 2856 insn we can transform it into an add still by 2857 using this alternative. */ 2858 && GET_CODE (no_subreg_reg_operand[1]) != PLUS))) 2859 { 2860 /* We have a move insn and a new reload insn will be similar 2861 to the current insn. We should avoid such situation as 2862 it results in LRA cycling. */ 2863 if (lra_dump_file != NULL) 2864 fprintf (lra_dump_file, 2865 " Cycle danger: overall += LRA_MAX_REJECT\n"); 2866 overall += LRA_MAX_REJECT; 2867 } 2868 ok_p = true; 2869 curr_alt_dont_inherit_ops_num = 0; 2870 for (nop = 0; nop < early_clobbered_regs_num; nop++) 2871 { 2872 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; 2873 HARD_REG_SET temp_set; 2874 2875 i = early_clobbered_nops[nop]; 2876 if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) 2877 || hard_regno[i] < 0) 2878 continue; 2879 lra_assert (operand_reg[i] != NULL_RTX); 2880 clobbered_hard_regno = hard_regno[i]; 2881 CLEAR_HARD_REG_SET (temp_set); 2882 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); 2883 first_conflict_j = last_conflict_j = -1; 2884 for (j = 0; j < n_operands; j++) 2885 if (j == i 2886 /* We don't want process insides of match_operator and 2887 match_parallel because otherwise we would process 2888 their operands once again generating a wrong 2889 code. */ 2890 || curr_static_id->operand[j].is_operator) 2891 continue; 2892 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) 2893 || (curr_alt_matches[i] == j && curr_alt_match_win[i])) 2894 continue; 2895 /* If we don't reload j-th operand, check conflicts. */ 2896 else if ((curr_alt_win[j] || curr_alt_match_win[j]) 2897 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) 2898 { 2899 if (first_conflict_j < 0) 2900 first_conflict_j = j; 2901 last_conflict_j = j; 2902 } 2903 if (last_conflict_j < 0) 2904 continue; 2905 /* If earlyclobber operand conflicts with another 2906 non-matching operand which is actually the same register 2907 as the earlyclobber operand, it is better to reload the 2908 another operand as an operand matching the earlyclobber 2909 operand can be also the same. */ 2910 if (first_conflict_j == last_conflict_j 2911 && operand_reg[last_conflict_j] != NULL_RTX 2912 && ! curr_alt_match_win[last_conflict_j] 2913 && REGNO (operand_reg[i]) == REGNO (operand_reg[last_conflict_j])) 2914 { 2915 curr_alt_win[last_conflict_j] = false; 2916 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] 2917 = last_conflict_j; 2918 losers++; 2919 /* Early clobber was already reflected in REJECT. */ 2920 lra_assert (reject > 0); 2921 if (lra_dump_file != NULL) 2922 fprintf 2923 (lra_dump_file, 2924 " %d Conflict early clobber reload: reject--\n", 2925 i); 2926 reject--; 2927 overall += LRA_LOSER_COST_FACTOR - 1; 2928 } 2929 else 2930 { 2931 /* We need to reload early clobbered register and the 2932 matched registers. */ 2933 for (j = 0; j < n_operands; j++) 2934 if (curr_alt_matches[j] == i) 2935 { 2936 curr_alt_match_win[j] = false; 2937 losers++; 2938 overall += LRA_LOSER_COST_FACTOR; 2939 } 2940 if (! curr_alt_match_win[i]) 2941 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; 2942 else 2943 { 2944 /* Remember pseudos used for match reloads are never 2945 inherited. */ 2946 lra_assert (curr_alt_matches[i] >= 0); 2947 curr_alt_win[curr_alt_matches[i]] = false; 2948 } 2949 curr_alt_win[i] = curr_alt_match_win[i] = false; 2950 losers++; 2951 /* Early clobber was already reflected in REJECT. */ 2952 lra_assert (reject > 0); 2953 if (lra_dump_file != NULL) 2954 fprintf 2955 (lra_dump_file, 2956 " %d Matched conflict early clobber reloads: " 2957 "reject--\n", 2958 i); 2959 reject--; 2960 overall += LRA_LOSER_COST_FACTOR - 1; 2961 } 2962 } 2963 if (lra_dump_file != NULL) 2964 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", 2965 nalt, overall, losers, reload_nregs); 2966 2967 /* If this alternative can be made to work by reloading, and it 2968 needs less reloading than the others checked so far, record 2969 it as the chosen goal for reloading. */ 2970 if ((best_losers != 0 && losers == 0) 2971 || (((best_losers == 0 && losers == 0) 2972 || (best_losers != 0 && losers != 0)) 2973 && (best_overall > overall 2974 || (best_overall == overall 2975 /* If the cost of the reloads is the same, 2976 prefer alternative which requires minimal 2977 number of reload regs. */ 2978 && (reload_nregs < best_reload_nregs 2979 || (reload_nregs == best_reload_nregs 2980 && (best_reload_sum < reload_sum 2981 || (best_reload_sum == reload_sum 2982 && nalt < goal_alt_number)))))))) 2983 { 2984 for (nop = 0; nop < n_operands; nop++) 2985 { 2986 goal_alt_win[nop] = curr_alt_win[nop]; 2987 goal_alt_match_win[nop] = curr_alt_match_win[nop]; 2988 goal_alt_matches[nop] = curr_alt_matches[nop]; 2989 goal_alt[nop] = curr_alt[nop]; 2990 goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; 2991 } 2992 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; 2993 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) 2994 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; 2995 goal_alt_swapped = curr_swapped; 2996 best_overall = overall; 2997 best_losers = losers; 2998 best_reload_nregs = reload_nregs; 2999 best_reload_sum = reload_sum; 3000 goal_alt_number = nalt; 3001 } 3002 if (losers == 0) 3003 /* Everything is satisfied. Do not process alternatives 3004 anymore. */ 3005 break; 3006 fail: 3007 ; 3008 } 3009 return ok_p; 3010 } 3011 3012 /* Make reload base reg from address AD. */ 3013 static rtx 3014 base_to_reg (struct address_info *ad) 3015 { 3016 enum reg_class cl; 3017 int code = -1; 3018 rtx new_inner = NULL_RTX; 3019 rtx new_reg = NULL_RTX; 3020 rtx_insn *insn; 3021 rtx_insn *last_insn = get_last_insn(); 3022 3023 lra_assert (ad->disp == ad->disp_term); 3024 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, 3025 get_index_code (ad)); 3026 new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX, 3027 cl, "base"); 3028 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, 3029 ad->disp_term == NULL 3030 ? const0_rtx 3031 : *ad->disp_term); 3032 if (!valid_address_p (ad->mode, new_inner, ad->as)) 3033 return NULL_RTX; 3034 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base)); 3035 code = recog_memoized (insn); 3036 if (code < 0) 3037 { 3038 delete_insns_since (last_insn); 3039 return NULL_RTX; 3040 } 3041 3042 return new_inner; 3043 } 3044 3045 /* Make reload base reg + disp from address AD. Return the new pseudo. */ 3046 static rtx 3047 base_plus_disp_to_reg (struct address_info *ad) 3048 { 3049 enum reg_class cl; 3050 rtx new_reg; 3051 3052 lra_assert (ad->base == ad->base_term && ad->disp == ad->disp_term); 3053 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, 3054 get_index_code (ad)); 3055 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, 3056 cl, "base + disp"); 3057 lra_emit_add (new_reg, *ad->base_term, *ad->disp_term); 3058 return new_reg; 3059 } 3060 3061 /* Make reload of index part of address AD. Return the new 3062 pseudo. */ 3063 static rtx 3064 index_part_to_reg (struct address_info *ad) 3065 { 3066 rtx new_reg; 3067 3068 new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, 3069 INDEX_REG_CLASS, "index term"); 3070 expand_mult (GET_MODE (*ad->index), *ad->index_term, 3071 GEN_INT (get_index_scale (ad)), new_reg, 1); 3072 return new_reg; 3073 } 3074 3075 /* Return true if we can add a displacement to address AD, even if that 3076 makes the address invalid. The fix-up code requires any new address 3077 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ 3078 static bool 3079 can_add_disp_p (struct address_info *ad) 3080 { 3081 return (!ad->autoinc_p 3082 && ad->segment == NULL 3083 && ad->base == ad->base_term 3084 && ad->disp == ad->disp_term); 3085 } 3086 3087 /* Make equiv substitution in address AD. Return true if a substitution 3088 was made. */ 3089 static bool 3090 equiv_address_substitution (struct address_info *ad) 3091 { 3092 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; 3093 HOST_WIDE_INT disp, scale; 3094 bool change_p; 3095 3096 base_term = strip_subreg (ad->base_term); 3097 if (base_term == NULL) 3098 base_reg = new_base_reg = NULL_RTX; 3099 else 3100 { 3101 base_reg = *base_term; 3102 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); 3103 } 3104 index_term = strip_subreg (ad->index_term); 3105 if (index_term == NULL) 3106 index_reg = new_index_reg = NULL_RTX; 3107 else 3108 { 3109 index_reg = *index_term; 3110 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); 3111 } 3112 if (base_reg == new_base_reg && index_reg == new_index_reg) 3113 return false; 3114 disp = 0; 3115 change_p = false; 3116 if (lra_dump_file != NULL) 3117 { 3118 fprintf (lra_dump_file, "Changing address in insn %d ", 3119 INSN_UID (curr_insn)); 3120 dump_value_slim (lra_dump_file, *ad->outer, 1); 3121 } 3122 if (base_reg != new_base_reg) 3123 { 3124 if (REG_P (new_base_reg)) 3125 { 3126 *base_term = new_base_reg; 3127 change_p = true; 3128 } 3129 else if (GET_CODE (new_base_reg) == PLUS 3130 && REG_P (XEXP (new_base_reg, 0)) 3131 && CONST_INT_P (XEXP (new_base_reg, 1)) 3132 && can_add_disp_p (ad)) 3133 { 3134 disp += INTVAL (XEXP (new_base_reg, 1)); 3135 *base_term = XEXP (new_base_reg, 0); 3136 change_p = true; 3137 } 3138 if (ad->base_term2 != NULL) 3139 *ad->base_term2 = *ad->base_term; 3140 } 3141 if (index_reg != new_index_reg) 3142 { 3143 if (REG_P (new_index_reg)) 3144 { 3145 *index_term = new_index_reg; 3146 change_p = true; 3147 } 3148 else if (GET_CODE (new_index_reg) == PLUS 3149 && REG_P (XEXP (new_index_reg, 0)) 3150 && CONST_INT_P (XEXP (new_index_reg, 1)) 3151 && can_add_disp_p (ad) 3152 && (scale = get_index_scale (ad))) 3153 { 3154 disp += INTVAL (XEXP (new_index_reg, 1)) * scale; 3155 *index_term = XEXP (new_index_reg, 0); 3156 change_p = true; 3157 } 3158 } 3159 if (disp != 0) 3160 { 3161 if (ad->disp != NULL) 3162 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); 3163 else 3164 { 3165 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); 3166 update_address (ad); 3167 } 3168 change_p = true; 3169 } 3170 if (lra_dump_file != NULL) 3171 { 3172 if (! change_p) 3173 fprintf (lra_dump_file, " -- no change\n"); 3174 else 3175 { 3176 fprintf (lra_dump_file, " on equiv "); 3177 dump_value_slim (lra_dump_file, *ad->outer, 1); 3178 fprintf (lra_dump_file, "\n"); 3179 } 3180 } 3181 return change_p; 3182 } 3183 3184 /* Major function to make reloads for an address in operand NOP or 3185 check its correctness (If CHECK_ONLY_P is true). The supported 3186 cases are: 3187 3188 1) an address that existed before LRA started, at which point it 3189 must have been valid. These addresses are subject to elimination 3190 and may have become invalid due to the elimination offset being out 3191 of range. 3192 3193 2) an address created by forcing a constant to memory 3194 (force_const_to_mem). The initial form of these addresses might 3195 not be valid, and it is this function's job to make them valid. 3196 3197 3) a frame address formed from a register and a (possibly zero) 3198 constant offset. As above, these addresses might not be valid and 3199 this function must make them so. 3200 3201 Add reloads to the lists *BEFORE and *AFTER. We might need to add 3202 reloads to *AFTER because of inc/dec, {pre, post} modify in the 3203 address. Return true for any RTL change. 3204 3205 The function is a helper function which does not produce all 3206 transformations (when CHECK_ONLY_P is false) which can be 3207 necessary. It does just basic steps. To do all necessary 3208 transformations use function process_address. */ 3209 static bool 3210 process_address_1 (int nop, bool check_only_p, 3211 rtx_insn **before, rtx_insn **after) 3212 { 3213 struct address_info ad; 3214 rtx new_reg; 3215 HOST_WIDE_INT scale; 3216 rtx op = *curr_id->operand_loc[nop]; 3217 const char *constraint = curr_static_id->operand[nop].constraint; 3218 enum constraint_num cn = lookup_constraint (constraint); 3219 bool change_p = false; 3220 3221 if (MEM_P (op) 3222 && GET_MODE (op) == BLKmode 3223 && GET_CODE (XEXP (op, 0)) == SCRATCH) 3224 return false; 3225 3226 if (insn_extra_address_constraint (cn)) 3227 decompose_lea_address (&ad, curr_id->operand_loc[nop]); 3228 /* Do not attempt to decompose arbitrary addresses generated by combine 3229 for asm operands with loose constraints, e.g 'X'. */ 3230 else if (MEM_P (op) 3231 && !(get_constraint_type (cn) == CT_FIXED_FORM 3232 && constraint_satisfied_p (op, cn))) 3233 decompose_mem_address (&ad, op); 3234 else if (GET_CODE (op) == SUBREG 3235 && MEM_P (SUBREG_REG (op))) 3236 decompose_mem_address (&ad, SUBREG_REG (op)); 3237 else 3238 return false; 3239 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to 3240 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both 3241 when INDEX_REG_CLASS is a single register class. */ 3242 if (ad.base_term != NULL 3243 && ad.index_term != NULL 3244 && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 3245 && REG_P (*ad.base_term) 3246 && REG_P (*ad.index_term) 3247 && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) 3248 && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) 3249 { 3250 std::swap (ad.base, ad.index); 3251 std::swap (ad.base_term, ad.index_term); 3252 } 3253 if (! check_only_p) 3254 change_p = equiv_address_substitution (&ad); 3255 if (ad.base_term != NULL 3256 && (process_addr_reg 3257 (ad.base_term, check_only_p, before, 3258 (ad.autoinc_p 3259 && !(REG_P (*ad.base_term) 3260 && find_regno_note (curr_insn, REG_DEAD, 3261 REGNO (*ad.base_term)) != NULL_RTX) 3262 ? after : NULL), 3263 base_reg_class (ad.mode, ad.as, ad.base_outer_code, 3264 get_index_code (&ad))))) 3265 { 3266 change_p = true; 3267 if (ad.base_term2 != NULL) 3268 *ad.base_term2 = *ad.base_term; 3269 } 3270 if (ad.index_term != NULL 3271 && process_addr_reg (ad.index_term, check_only_p, 3272 before, NULL, INDEX_REG_CLASS)) 3273 change_p = true; 3274 3275 /* Target hooks sometimes don't treat extra-constraint addresses as 3276 legitimate address_operands, so handle them specially. */ 3277 if (insn_extra_address_constraint (cn) 3278 && satisfies_address_constraint_p (&ad, cn)) 3279 return change_p; 3280 3281 if (check_only_p) 3282 return change_p; 3283 3284 /* There are three cases where the shape of *AD.INNER may now be invalid: 3285 3286 1) the original address was valid, but either elimination or 3287 equiv_address_substitution was applied and that made 3288 the address invalid. 3289 3290 2) the address is an invalid symbolic address created by 3291 force_const_to_mem. 3292 3293 3) the address is a frame address with an invalid offset. 3294 3295 4) the address is a frame address with an invalid base. 3296 3297 All these cases involve a non-autoinc address, so there is no 3298 point revalidating other types. */ 3299 if (ad.autoinc_p || valid_address_p (&ad)) 3300 return change_p; 3301 3302 /* Any index existed before LRA started, so we can assume that the 3303 presence and shape of the index is valid. */ 3304 push_to_sequence (*before); 3305 lra_assert (ad.disp == ad.disp_term); 3306 if (ad.base == NULL) 3307 { 3308 if (ad.index == NULL) 3309 { 3310 rtx_insn *insn; 3311 rtx_insn *last = get_last_insn (); 3312 int code = -1; 3313 enum reg_class cl = base_reg_class (ad.mode, ad.as, 3314 SCRATCH, SCRATCH); 3315 rtx addr = *ad.inner; 3316 3317 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); 3318 if (HAVE_lo_sum) 3319 { 3320 /* addr => lo_sum (new_base, addr), case (2) above. */ 3321 insn = emit_insn (gen_rtx_SET 3322 (new_reg, 3323 gen_rtx_HIGH (Pmode, copy_rtx (addr)))); 3324 code = recog_memoized (insn); 3325 if (code >= 0) 3326 { 3327 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); 3328 if (! valid_address_p (ad.mode, *ad.outer, ad.as)) 3329 { 3330 /* Try to put lo_sum into register. */ 3331 insn = emit_insn (gen_rtx_SET 3332 (new_reg, 3333 gen_rtx_LO_SUM (Pmode, new_reg, addr))); 3334 code = recog_memoized (insn); 3335 if (code >= 0) 3336 { 3337 *ad.inner = new_reg; 3338 if (! valid_address_p (ad.mode, *ad.outer, ad.as)) 3339 { 3340 *ad.inner = addr; 3341 code = -1; 3342 } 3343 } 3344 3345 } 3346 } 3347 if (code < 0) 3348 delete_insns_since (last); 3349 } 3350 3351 if (code < 0) 3352 { 3353 /* addr => new_base, case (2) above. */ 3354 lra_emit_move (new_reg, addr); 3355 3356 for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); 3357 insn != NULL_RTX; 3358 insn = NEXT_INSN (insn)) 3359 if (recog_memoized (insn) < 0) 3360 break; 3361 if (insn != NULL_RTX) 3362 { 3363 /* Do nothing if we cannot generate right insns. 3364 This is analogous to reload pass behavior. */ 3365 delete_insns_since (last); 3366 end_sequence (); 3367 return false; 3368 } 3369 *ad.inner = new_reg; 3370 } 3371 } 3372 else 3373 { 3374 /* index * scale + disp => new base + index * scale, 3375 case (1) above. */ 3376 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, 3377 GET_CODE (*ad.index)); 3378 3379 lra_assert (INDEX_REG_CLASS != NO_REGS); 3380 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); 3381 lra_emit_move (new_reg, *ad.disp); 3382 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), 3383 new_reg, *ad.index); 3384 } 3385 } 3386 else if (ad.index == NULL) 3387 { 3388 int regno; 3389 enum reg_class cl; 3390 rtx set; 3391 rtx_insn *insns, *last_insn; 3392 /* Try to reload base into register only if the base is invalid 3393 for the address but with valid offset, case (4) above. */ 3394 start_sequence (); 3395 new_reg = base_to_reg (&ad); 3396 3397 /* base + disp => new base, cases (1) and (3) above. */ 3398 /* Another option would be to reload the displacement into an 3399 index register. However, postreload has code to optimize 3400 address reloads that have the same base and different 3401 displacements, so reloading into an index register would 3402 not necessarily be a win. */ 3403 if (new_reg == NULL_RTX) 3404 new_reg = base_plus_disp_to_reg (&ad); 3405 insns = get_insns (); 3406 last_insn = get_last_insn (); 3407 /* If we generated at least two insns, try last insn source as 3408 an address. If we succeed, we generate one less insn. */ 3409 if (last_insn != insns && (set = single_set (last_insn)) != NULL_RTX 3410 && GET_CODE (SET_SRC (set)) == PLUS 3411 && REG_P (XEXP (SET_SRC (set), 0)) 3412 && CONSTANT_P (XEXP (SET_SRC (set), 1))) 3413 { 3414 *ad.inner = SET_SRC (set); 3415 if (valid_address_p (ad.mode, *ad.outer, ad.as)) 3416 { 3417 *ad.base_term = XEXP (SET_SRC (set), 0); 3418 *ad.disp_term = XEXP (SET_SRC (set), 1); 3419 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, 3420 get_index_code (&ad)); 3421 regno = REGNO (*ad.base_term); 3422 if (regno >= FIRST_PSEUDO_REGISTER 3423 && cl != lra_get_allocno_class (regno)) 3424 lra_change_class (regno, cl, " Change to", true); 3425 new_reg = SET_SRC (set); 3426 delete_insns_since (PREV_INSN (last_insn)); 3427 } 3428 } 3429 /* Try if target can split displacement into legitimite new disp 3430 and offset. If it's the case, we replace the last insn with 3431 insns for base + offset => new_reg and set new_reg + new disp 3432 to *ad.inner. */ 3433 last_insn = get_last_insn (); 3434 if ((set = single_set (last_insn)) != NULL_RTX 3435 && GET_CODE (SET_SRC (set)) == PLUS 3436 && REG_P (XEXP (SET_SRC (set), 0)) 3437 && REGNO (XEXP (SET_SRC (set), 0)) < FIRST_PSEUDO_REGISTER 3438 && CONST_INT_P (XEXP (SET_SRC (set), 1))) 3439 { 3440 rtx addend, disp = XEXP (SET_SRC (set), 1); 3441 if (targetm.legitimize_address_displacement (&disp, &addend, 3442 ad.mode)) 3443 { 3444 rtx_insn *new_insns; 3445 start_sequence (); 3446 lra_emit_add (new_reg, XEXP (SET_SRC (set), 0), addend); 3447 new_insns = get_insns (); 3448 end_sequence (); 3449 new_reg = gen_rtx_PLUS (Pmode, new_reg, disp); 3450 delete_insns_since (PREV_INSN (last_insn)); 3451 add_insn (new_insns); 3452 insns = get_insns (); 3453 } 3454 } 3455 end_sequence (); 3456 emit_insn (insns); 3457 *ad.inner = new_reg; 3458 } 3459 else if (ad.disp_term != NULL) 3460 { 3461 /* base + scale * index + disp => new base + scale * index, 3462 case (1) above. */ 3463 new_reg = base_plus_disp_to_reg (&ad); 3464 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), 3465 new_reg, *ad.index); 3466 } 3467 else if ((scale = get_index_scale (&ad)) == 1) 3468 { 3469 /* The last transformation to one reg will be made in 3470 curr_insn_transform function. */ 3471 end_sequence (); 3472 return false; 3473 } 3474 else if (scale != 0) 3475 { 3476 /* base + scale * index => base + new_reg, 3477 case (1) above. 3478 Index part of address may become invalid. For example, we 3479 changed pseudo on the equivalent memory and a subreg of the 3480 pseudo onto the memory of different mode for which the scale is 3481 prohibitted. */ 3482 new_reg = index_part_to_reg (&ad); 3483 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), 3484 *ad.base_term, new_reg); 3485 } 3486 else 3487 { 3488 enum reg_class cl = base_reg_class (ad.mode, ad.as, 3489 SCRATCH, SCRATCH); 3490 rtx addr = *ad.inner; 3491 3492 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); 3493 /* addr => new_base. */ 3494 lra_emit_move (new_reg, addr); 3495 *ad.inner = new_reg; 3496 } 3497 *before = get_insns (); 3498 end_sequence (); 3499 return true; 3500 } 3501 3502 /* If CHECK_ONLY_P is false, do address reloads until it is necessary. 3503 Use process_address_1 as a helper function. Return true for any 3504 RTL changes. 3505 3506 If CHECK_ONLY_P is true, just check address correctness. Return 3507 false if the address correct. */ 3508 static bool 3509 process_address (int nop, bool check_only_p, 3510 rtx_insn **before, rtx_insn **after) 3511 { 3512 bool res = false; 3513 3514 while (process_address_1 (nop, check_only_p, before, after)) 3515 { 3516 if (check_only_p) 3517 return true; 3518 res = true; 3519 } 3520 return res; 3521 } 3522 3523 /* Emit insns to reload VALUE into a new register. VALUE is an 3524 auto-increment or auto-decrement RTX whose operand is a register or 3525 memory location; so reloading involves incrementing that location. 3526 IN is either identical to VALUE, or some cheaper place to reload 3527 value being incremented/decremented from. 3528 3529 INC_AMOUNT is the number to increment or decrement by (always 3530 positive and ignored for POST_MODIFY/PRE_MODIFY). 3531 3532 Return pseudo containing the result. */ 3533 static rtx 3534 emit_inc (enum reg_class new_rclass, rtx in, rtx value, int inc_amount) 3535 { 3536 /* REG or MEM to be copied and incremented. */ 3537 rtx incloc = XEXP (value, 0); 3538 /* Nonzero if increment after copying. */ 3539 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC 3540 || GET_CODE (value) == POST_MODIFY); 3541 rtx_insn *last; 3542 rtx inc; 3543 rtx_insn *add_insn; 3544 int code; 3545 rtx real_in = in == value ? incloc : in; 3546 rtx result; 3547 bool plus_p = true; 3548 3549 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) 3550 { 3551 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS 3552 || GET_CODE (XEXP (value, 1)) == MINUS); 3553 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); 3554 plus_p = GET_CODE (XEXP (value, 1)) == PLUS; 3555 inc = XEXP (XEXP (value, 1), 1); 3556 } 3557 else 3558 { 3559 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) 3560 inc_amount = -inc_amount; 3561 3562 inc = GEN_INT (inc_amount); 3563 } 3564 3565 if (! post && REG_P (incloc)) 3566 result = incloc; 3567 else 3568 result = lra_create_new_reg (GET_MODE (value), value, new_rclass, 3569 "INC/DEC result"); 3570 3571 if (real_in != result) 3572 { 3573 /* First copy the location to the result register. */ 3574 lra_assert (REG_P (result)); 3575 emit_insn (gen_move_insn (result, real_in)); 3576 } 3577 3578 /* We suppose that there are insns to add/sub with the constant 3579 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the 3580 old reload worked with this assumption. If the assumption 3581 becomes wrong, we should use approach in function 3582 base_plus_disp_to_reg. */ 3583 if (in == value) 3584 { 3585 /* See if we can directly increment INCLOC. */ 3586 last = get_last_insn (); 3587 add_insn = emit_insn (plus_p 3588 ? gen_add2_insn (incloc, inc) 3589 : gen_sub2_insn (incloc, inc)); 3590 3591 code = recog_memoized (add_insn); 3592 if (code >= 0) 3593 { 3594 if (! post && result != incloc) 3595 emit_insn (gen_move_insn (result, incloc)); 3596 return result; 3597 } 3598 delete_insns_since (last); 3599 } 3600 3601 /* If couldn't do the increment directly, must increment in RESULT. 3602 The way we do this depends on whether this is pre- or 3603 post-increment. For pre-increment, copy INCLOC to the reload 3604 register, increment it there, then save back. */ 3605 if (! post) 3606 { 3607 if (real_in != result) 3608 emit_insn (gen_move_insn (result, real_in)); 3609 if (plus_p) 3610 emit_insn (gen_add2_insn (result, inc)); 3611 else 3612 emit_insn (gen_sub2_insn (result, inc)); 3613 if (result != incloc) 3614 emit_insn (gen_move_insn (incloc, result)); 3615 } 3616 else 3617 { 3618 /* Post-increment. 3619 3620 Because this might be a jump insn or a compare, and because 3621 RESULT may not be available after the insn in an input 3622 reload, we must do the incrementing before the insn being 3623 reloaded for. 3624 3625 We have already copied IN to RESULT. Increment the copy in 3626 RESULT, save that back, then decrement RESULT so it has 3627 the original value. */ 3628 if (plus_p) 3629 emit_insn (gen_add2_insn (result, inc)); 3630 else 3631 emit_insn (gen_sub2_insn (result, inc)); 3632 emit_insn (gen_move_insn (incloc, result)); 3633 /* Restore non-modified value for the result. We prefer this 3634 way because it does not require an additional hard 3635 register. */ 3636 if (plus_p) 3637 { 3638 if (CONST_INT_P (inc)) 3639 emit_insn (gen_add2_insn (result, 3640 gen_int_mode (-INTVAL (inc), 3641 GET_MODE (result)))); 3642 else 3643 emit_insn (gen_sub2_insn (result, inc)); 3644 } 3645 else 3646 emit_insn (gen_add2_insn (result, inc)); 3647 } 3648 return result; 3649 } 3650 3651 /* Return true if the current move insn does not need processing as we 3652 already know that it satisfies its constraints. */ 3653 static bool 3654 simple_move_p (void) 3655 { 3656 rtx dest, src; 3657 enum reg_class dclass, sclass; 3658 3659 lra_assert (curr_insn_set != NULL_RTX); 3660 dest = SET_DEST (curr_insn_set); 3661 src = SET_SRC (curr_insn_set); 3662 3663 /* If the instruction has multiple sets we need to process it even if it 3664 is single_set. This can happen if one or more of the SETs are dead. 3665 See PR73650. */ 3666 if (multiple_sets (curr_insn)) 3667 return false; 3668 3669 return ((dclass = get_op_class (dest)) != NO_REGS 3670 && (sclass = get_op_class (src)) != NO_REGS 3671 /* The backend guarantees that register moves of cost 2 3672 never need reloads. */ 3673 && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); 3674 } 3675 3676 /* Swap operands NOP and NOP + 1. */ 3677 static inline void 3678 swap_operands (int nop) 3679 { 3680 std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); 3681 std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); 3682 std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); 3683 std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]); 3684 /* Swap the duplicates too. */ 3685 lra_update_dup (curr_id, nop); 3686 lra_update_dup (curr_id, nop + 1); 3687 } 3688 3689 /* Main entry point of the constraint code: search the body of the 3690 current insn to choose the best alternative. It is mimicking insn 3691 alternative cost calculation model of former reload pass. That is 3692 because machine descriptions were written to use this model. This 3693 model can be changed in future. Make commutative operand exchange 3694 if it is chosen. 3695 3696 if CHECK_ONLY_P is false, do RTL changes to satisfy the 3697 constraints. Return true if any change happened during function 3698 call. 3699 3700 If CHECK_ONLY_P is true then don't do any transformation. Just 3701 check that the insn satisfies all constraints. If the insn does 3702 not satisfy any constraint, return true. */ 3703 static bool 3704 curr_insn_transform (bool check_only_p) 3705 { 3706 int i, j, k; 3707 int n_operands; 3708 int n_alternatives; 3709 int n_outputs; 3710 int commutative; 3711 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; 3712 signed char match_inputs[MAX_RECOG_OPERANDS + 1]; 3713 signed char outputs[MAX_RECOG_OPERANDS + 1]; 3714 rtx_insn *before, *after; 3715 bool alt_p = false; 3716 /* Flag that the insn has been changed through a transformation. */ 3717 bool change_p; 3718 bool sec_mem_p; 3719 #ifdef SECONDARY_MEMORY_NEEDED 3720 bool use_sec_mem_p; 3721 #endif 3722 int max_regno_before; 3723 int reused_alternative_num; 3724 3725 curr_insn_set = single_set (curr_insn); 3726 if (curr_insn_set != NULL_RTX && simple_move_p ()) 3727 { 3728 /* We assume that the corresponding insn alternative has no 3729 earlier clobbers. If it is not the case, don't define move 3730 cost equal to 2 for the corresponding register classes. */ 3731 lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT); 3732 return false; 3733 } 3734 3735 no_input_reloads_p = no_output_reloads_p = false; 3736 goal_alt_number = -1; 3737 change_p = sec_mem_p = false; 3738 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output 3739 reloads; neither are insns that SET cc0. Insns that use CC0 are 3740 not allowed to have any input reloads. */ 3741 if (JUMP_P (curr_insn) || CALL_P (curr_insn)) 3742 no_output_reloads_p = true; 3743 3744 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) 3745 no_input_reloads_p = true; 3746 if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn))) 3747 no_output_reloads_p = true; 3748 3749 n_operands = curr_static_id->n_operands; 3750 n_alternatives = curr_static_id->n_alternatives; 3751 3752 /* Just return "no reloads" if insn has no operands with 3753 constraints. */ 3754 if (n_operands == 0 || n_alternatives == 0) 3755 return false; 3756 3757 max_regno_before = max_reg_num (); 3758 3759 for (i = 0; i < n_operands; i++) 3760 { 3761 goal_alt_matched[i][0] = -1; 3762 goal_alt_matches[i] = -1; 3763 } 3764 3765 commutative = curr_static_id->commutative; 3766 3767 /* Now see what we need for pseudos that didn't get hard regs or got 3768 the wrong kind of hard reg. For this, we must consider all the 3769 operands together against the register constraints. */ 3770 3771 best_losers = best_overall = INT_MAX; 3772 best_reload_sum = 0; 3773 3774 curr_swapped = false; 3775 goal_alt_swapped = false; 3776 3777 if (! check_only_p) 3778 /* Make equivalence substitution and memory subreg elimination 3779 before address processing because an address legitimacy can 3780 depend on memory mode. */ 3781 for (i = 0; i < n_operands; i++) 3782 { 3783 rtx op, subst, old; 3784 bool op_change_p = false; 3785 3786 if (curr_static_id->operand[i].is_operator) 3787 continue; 3788 3789 old = op = *curr_id->operand_loc[i]; 3790 if (GET_CODE (old) == SUBREG) 3791 old = SUBREG_REG (old); 3792 subst = get_equiv_with_elimination (old, curr_insn); 3793 original_subreg_reg_mode[i] = VOIDmode; 3794 equiv_substition_p[i] = false; 3795 if (subst != old) 3796 { 3797 equiv_substition_p[i] = true; 3798 subst = copy_rtx (subst); 3799 lra_assert (REG_P (old)); 3800 if (GET_CODE (op) != SUBREG) 3801 *curr_id->operand_loc[i] = subst; 3802 else 3803 { 3804 SUBREG_REG (op) = subst; 3805 if (GET_MODE (subst) == VOIDmode) 3806 original_subreg_reg_mode[i] = GET_MODE (old); 3807 } 3808 if (lra_dump_file != NULL) 3809 { 3810 fprintf (lra_dump_file, 3811 "Changing pseudo %d in operand %i of insn %u on equiv ", 3812 REGNO (old), i, INSN_UID (curr_insn)); 3813 dump_value_slim (lra_dump_file, subst, 1); 3814 fprintf (lra_dump_file, "\n"); 3815 } 3816 op_change_p = change_p = true; 3817 } 3818 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) 3819 { 3820 change_p = true; 3821 lra_update_dup (curr_id, i); 3822 } 3823 } 3824 3825 /* Reload address registers and displacements. We do it before 3826 finding an alternative because of memory constraints. */ 3827 before = after = NULL; 3828 for (i = 0; i < n_operands; i++) 3829 if (! curr_static_id->operand[i].is_operator 3830 && process_address (i, check_only_p, &before, &after)) 3831 { 3832 if (check_only_p) 3833 return true; 3834 change_p = true; 3835 lra_update_dup (curr_id, i); 3836 } 3837 3838 if (change_p) 3839 /* If we've changed the instruction then any alternative that 3840 we chose previously may no longer be valid. */ 3841 lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT); 3842 3843 if (! check_only_p && curr_insn_set != NULL_RTX 3844 && check_and_process_move (&change_p, &sec_mem_p)) 3845 return change_p; 3846 3847 try_swapped: 3848 3849 reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative; 3850 if (lra_dump_file != NULL && reused_alternative_num >= 0) 3851 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", 3852 reused_alternative_num, INSN_UID (curr_insn)); 3853 3854 if (process_alt_operands (reused_alternative_num)) 3855 alt_p = true; 3856 3857 if (check_only_p) 3858 return ! alt_p || best_losers != 0; 3859 3860 /* If insn is commutative (it's safe to exchange a certain pair of 3861 operands) then we need to try each alternative twice, the second 3862 time matching those two operands as if we had exchanged them. To 3863 do this, really exchange them in operands. 3864 3865 If we have just tried the alternatives the second time, return 3866 operands to normal and drop through. */ 3867 3868 if (reused_alternative_num < 0 && commutative >= 0) 3869 { 3870 curr_swapped = !curr_swapped; 3871 if (curr_swapped) 3872 { 3873 swap_operands (commutative); 3874 goto try_swapped; 3875 } 3876 else 3877 swap_operands (commutative); 3878 } 3879 3880 if (! alt_p && ! sec_mem_p) 3881 { 3882 /* No alternative works with reloads?? */ 3883 if (INSN_CODE (curr_insn) >= 0) 3884 fatal_insn ("unable to generate reloads for:", curr_insn); 3885 error_for_asm (curr_insn, 3886 "inconsistent operand constraints in an %<asm%>"); 3887 /* Avoid further trouble with this insn. Don't generate use 3888 pattern here as we could use the insn SP offset. */ 3889 lra_set_insn_deleted (curr_insn); 3890 return true; 3891 } 3892 3893 /* If the best alternative is with operands 1 and 2 swapped, swap 3894 them. Update the operand numbers of any reloads already 3895 pushed. */ 3896 3897 if (goal_alt_swapped) 3898 { 3899 if (lra_dump_file != NULL) 3900 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", 3901 INSN_UID (curr_insn)); 3902 3903 /* Swap the duplicates too. */ 3904 swap_operands (commutative); 3905 change_p = true; 3906 } 3907 3908 #ifdef SECONDARY_MEMORY_NEEDED 3909 /* Some target macros SECONDARY_MEMORY_NEEDED (e.g. x86) are defined 3910 too conservatively. So we use the secondary memory only if there 3911 is no any alternative without reloads. */ 3912 use_sec_mem_p = false; 3913 if (! alt_p) 3914 use_sec_mem_p = true; 3915 else if (sec_mem_p) 3916 { 3917 for (i = 0; i < n_operands; i++) 3918 if (! goal_alt_win[i] && ! goal_alt_match_win[i]) 3919 break; 3920 use_sec_mem_p = i < n_operands; 3921 } 3922 3923 if (use_sec_mem_p) 3924 { 3925 int in = -1, out = -1; 3926 rtx new_reg, src, dest, rld; 3927 machine_mode sec_mode, rld_mode; 3928 3929 lra_assert (curr_insn_set != NULL_RTX && sec_mem_p); 3930 dest = SET_DEST (curr_insn_set); 3931 src = SET_SRC (curr_insn_set); 3932 for (i = 0; i < n_operands; i++) 3933 if (*curr_id->operand_loc[i] == dest) 3934 out = i; 3935 else if (*curr_id->operand_loc[i] == src) 3936 in = i; 3937 for (i = 0; i < curr_static_id->n_dups; i++) 3938 if (out < 0 && *curr_id->dup_loc[i] == dest) 3939 out = curr_static_id->dup_num[i]; 3940 else if (in < 0 && *curr_id->dup_loc[i] == src) 3941 in = curr_static_id->dup_num[i]; 3942 lra_assert (out >= 0 && in >= 0 3943 && curr_static_id->operand[out].type == OP_OUT 3944 && curr_static_id->operand[in].type == OP_IN); 3945 rld = (GET_MODE_SIZE (GET_MODE (dest)) <= GET_MODE_SIZE (GET_MODE (src)) 3946 ? dest : src); 3947 rld_mode = GET_MODE (rld); 3948 #ifdef SECONDARY_MEMORY_NEEDED_MODE 3949 sec_mode = SECONDARY_MEMORY_NEEDED_MODE (rld_mode); 3950 #else 3951 sec_mode = rld_mode; 3952 #endif 3953 new_reg = lra_create_new_reg (sec_mode, NULL_RTX, 3954 NO_REGS, "secondary"); 3955 /* If the mode is changed, it should be wider. */ 3956 lra_assert (GET_MODE_SIZE (sec_mode) >= GET_MODE_SIZE (rld_mode)); 3957 if (sec_mode != rld_mode) 3958 { 3959 /* If the target says specifically to use another mode for 3960 secondary memory moves we can not reuse the original 3961 insn. */ 3962 after = emit_spill_move (false, new_reg, dest); 3963 lra_process_new_insns (curr_insn, NULL, after, 3964 "Inserting the sec. move"); 3965 /* We may have non null BEFORE here (e.g. after address 3966 processing. */ 3967 push_to_sequence (before); 3968 before = emit_spill_move (true, new_reg, src); 3969 emit_insn (before); 3970 before = get_insns (); 3971 end_sequence (); 3972 lra_process_new_insns (curr_insn, before, NULL, "Changing on"); 3973 lra_set_insn_deleted (curr_insn); 3974 } 3975 else if (dest == rld) 3976 { 3977 *curr_id->operand_loc[out] = new_reg; 3978 lra_update_dup (curr_id, out); 3979 after = emit_spill_move (false, new_reg, dest); 3980 lra_process_new_insns (curr_insn, NULL, after, 3981 "Inserting the sec. move"); 3982 } 3983 else 3984 { 3985 *curr_id->operand_loc[in] = new_reg; 3986 lra_update_dup (curr_id, in); 3987 /* See comments above. */ 3988 push_to_sequence (before); 3989 before = emit_spill_move (true, new_reg, src); 3990 emit_insn (before); 3991 before = get_insns (); 3992 end_sequence (); 3993 lra_process_new_insns (curr_insn, before, NULL, 3994 "Inserting the sec. move"); 3995 } 3996 lra_update_insn_regno_info (curr_insn); 3997 return true; 3998 } 3999 #endif 4000 4001 lra_assert (goal_alt_number >= 0); 4002 lra_set_used_insn_alternative (curr_insn, goal_alt_number); 4003 4004 if (lra_dump_file != NULL) 4005 { 4006 const char *p; 4007 4008 fprintf (lra_dump_file, " Choosing alt %d in insn %u:", 4009 goal_alt_number, INSN_UID (curr_insn)); 4010 for (i = 0; i < n_operands; i++) 4011 { 4012 p = (curr_static_id->operand_alternative 4013 [goal_alt_number * n_operands + i].constraint); 4014 if (*p == '\0') 4015 continue; 4016 fprintf (lra_dump_file, " (%d) ", i); 4017 for (; *p != '\0' && *p != ',' && *p != '#'; p++) 4018 fputc (*p, lra_dump_file); 4019 } 4020 if (INSN_CODE (curr_insn) >= 0 4021 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) 4022 fprintf (lra_dump_file, " {%s}", p); 4023 if (curr_id->sp_offset != 0) 4024 fprintf (lra_dump_file, " (sp_off=%" HOST_WIDE_INT_PRINT "d)", 4025 curr_id->sp_offset); 4026 fprintf (lra_dump_file, "\n"); 4027 } 4028 4029 /* Right now, for any pair of operands I and J that are required to 4030 match, with J < I, goal_alt_matches[I] is J. Add I to 4031 goal_alt_matched[J]. */ 4032 4033 for (i = 0; i < n_operands; i++) 4034 if ((j = goal_alt_matches[i]) >= 0) 4035 { 4036 for (k = 0; goal_alt_matched[j][k] >= 0; k++) 4037 ; 4038 /* We allow matching one output operand and several input 4039 operands. */ 4040 lra_assert (k == 0 4041 || (curr_static_id->operand[j].type == OP_OUT 4042 && curr_static_id->operand[i].type == OP_IN 4043 && (curr_static_id->operand 4044 [goal_alt_matched[j][0]].type == OP_IN))); 4045 goal_alt_matched[j][k] = i; 4046 goal_alt_matched[j][k + 1] = -1; 4047 } 4048 4049 for (i = 0; i < n_operands; i++) 4050 goal_alt_win[i] |= goal_alt_match_win[i]; 4051 4052 /* Any constants that aren't allowed and can't be reloaded into 4053 registers are here changed into memory references. */ 4054 for (i = 0; i < n_operands; i++) 4055 if (goal_alt_win[i]) 4056 { 4057 int regno; 4058 enum reg_class new_class; 4059 rtx reg = *curr_id->operand_loc[i]; 4060 4061 if (GET_CODE (reg) == SUBREG) 4062 reg = SUBREG_REG (reg); 4063 4064 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) 4065 { 4066 bool ok_p = in_class_p (reg, goal_alt[i], &new_class); 4067 4068 if (new_class != NO_REGS && get_reg_class (regno) != new_class) 4069 { 4070 lra_assert (ok_p); 4071 lra_change_class (regno, new_class, " Change to", true); 4072 } 4073 } 4074 } 4075 else 4076 { 4077 const char *constraint; 4078 char c; 4079 rtx op = *curr_id->operand_loc[i]; 4080 rtx subreg = NULL_RTX; 4081 machine_mode mode = curr_operand_mode[i]; 4082 4083 if (GET_CODE (op) == SUBREG) 4084 { 4085 subreg = op; 4086 op = SUBREG_REG (op); 4087 mode = GET_MODE (op); 4088 } 4089 4090 if (CONST_POOL_OK_P (mode, op) 4091 && ((targetm.preferred_reload_class 4092 (op, (enum reg_class) goal_alt[i]) == NO_REGS) 4093 || no_input_reloads_p)) 4094 { 4095 rtx tem = force_const_mem (mode, op); 4096 4097 change_p = true; 4098 if (subreg != NULL_RTX) 4099 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); 4100 4101 *curr_id->operand_loc[i] = tem; 4102 lra_update_dup (curr_id, i); 4103 process_address (i, false, &before, &after); 4104 4105 /* If the alternative accepts constant pool refs directly 4106 there will be no reload needed at all. */ 4107 if (subreg != NULL_RTX) 4108 continue; 4109 /* Skip alternatives before the one requested. */ 4110 constraint = (curr_static_id->operand_alternative 4111 [goal_alt_number * n_operands + i].constraint); 4112 for (; 4113 (c = *constraint) && c != ',' && c != '#'; 4114 constraint += CONSTRAINT_LEN (c, constraint)) 4115 { 4116 enum constraint_num cn = lookup_constraint (constraint); 4117 if ((insn_extra_memory_constraint (cn) 4118 || insn_extra_special_memory_constraint (cn)) 4119 && satisfies_memory_constraint_p (tem, cn)) 4120 break; 4121 } 4122 if (c == '\0' || c == ',' || c == '#') 4123 continue; 4124 4125 goal_alt_win[i] = true; 4126 } 4127 } 4128 4129 n_outputs = 0; 4130 outputs[0] = -1; 4131 for (i = 0; i < n_operands; i++) 4132 { 4133 int regno; 4134 bool optional_p = false; 4135 rtx old, new_reg; 4136 rtx op = *curr_id->operand_loc[i]; 4137 4138 if (goal_alt_win[i]) 4139 { 4140 if (goal_alt[i] == NO_REGS 4141 && REG_P (op) 4142 /* When we assign NO_REGS it means that we will not 4143 assign a hard register to the scratch pseudo by 4144 assigment pass and the scratch pseudo will be 4145 spilled. Spilled scratch pseudos are transformed 4146 back to scratches at the LRA end. */ 4147 && lra_former_scratch_operand_p (curr_insn, i) 4148 && lra_former_scratch_p (REGNO (op))) 4149 { 4150 int regno = REGNO (op); 4151 lra_change_class (regno, NO_REGS, " Change to", true); 4152 if (lra_get_regno_hard_regno (regno) >= 0) 4153 /* We don't have to mark all insn affected by the 4154 spilled pseudo as there is only one such insn, the 4155 current one. */ 4156 reg_renumber[regno] = -1; 4157 lra_assert (bitmap_single_bit_set_p 4158 (&lra_reg_info[REGNO (op)].insn_bitmap)); 4159 } 4160 /* We can do an optional reload. If the pseudo got a hard 4161 reg, we might improve the code through inheritance. If 4162 it does not get a hard register we coalesce memory/memory 4163 moves later. Ignore move insns to avoid cycling. */ 4164 if (! lra_simple_p 4165 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES 4166 && goal_alt[i] != NO_REGS && REG_P (op) 4167 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER 4168 && regno < new_regno_start 4169 && ! lra_former_scratch_p (regno) 4170 && reg_renumber[regno] < 0 4171 /* Check that the optional reload pseudo will be able to 4172 hold given mode value. */ 4173 && ! (prohibited_class_reg_set_mode_p 4174 (goal_alt[i], reg_class_contents[goal_alt[i]], 4175 PSEUDO_REGNO_MODE (regno))) 4176 && (curr_insn_set == NULL_RTX 4177 || !((REG_P (SET_SRC (curr_insn_set)) 4178 || MEM_P (SET_SRC (curr_insn_set)) 4179 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) 4180 && (REG_P (SET_DEST (curr_insn_set)) 4181 || MEM_P (SET_DEST (curr_insn_set)) 4182 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) 4183 optional_p = true; 4184 else 4185 continue; 4186 } 4187 4188 /* Operands that match previous ones have already been handled. */ 4189 if (goal_alt_matches[i] >= 0) 4190 continue; 4191 4192 /* We should not have an operand with a non-offsettable address 4193 appearing where an offsettable address will do. It also may 4194 be a case when the address should be special in other words 4195 not a general one (e.g. it needs no index reg). */ 4196 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) 4197 { 4198 enum reg_class rclass; 4199 rtx *loc = &XEXP (op, 0); 4200 enum rtx_code code = GET_CODE (*loc); 4201 4202 push_to_sequence (before); 4203 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), 4204 MEM, SCRATCH); 4205 if (GET_RTX_CLASS (code) == RTX_AUTOINC) 4206 new_reg = emit_inc (rclass, *loc, *loc, 4207 /* This value does not matter for MODIFY. */ 4208 GET_MODE_SIZE (GET_MODE (op))); 4209 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE, 4210 "offsetable address", &new_reg)) 4211 lra_emit_move (new_reg, *loc); 4212 before = get_insns (); 4213 end_sequence (); 4214 *loc = new_reg; 4215 lra_update_dup (curr_id, i); 4216 } 4217 else if (goal_alt_matched[i][0] == -1) 4218 { 4219 machine_mode mode; 4220 rtx reg, *loc; 4221 int hard_regno, byte; 4222 enum op_type type = curr_static_id->operand[i].type; 4223 4224 loc = curr_id->operand_loc[i]; 4225 mode = curr_operand_mode[i]; 4226 if (GET_CODE (*loc) == SUBREG) 4227 { 4228 reg = SUBREG_REG (*loc); 4229 byte = SUBREG_BYTE (*loc); 4230 if (REG_P (reg) 4231 /* Strict_low_part requires reloading the register and not 4232 just the subreg. Likewise for a strict subreg no wider 4233 than a word for WORD_REGISTER_OPERATIONS targets. */ 4234 && (curr_static_id->operand[i].strict_low 4235 || (GET_MODE_SIZE (mode) 4236 <= GET_MODE_SIZE (GET_MODE (reg)) 4237 && (hard_regno 4238 = get_try_hard_regno (REGNO (reg))) >= 0 4239 && (simplify_subreg_regno 4240 (hard_regno, 4241 GET_MODE (reg), byte, mode) < 0) 4242 && (goal_alt[i] == NO_REGS 4243 || (simplify_subreg_regno 4244 (ira_class_hard_regs[goal_alt[i]][0], 4245 GET_MODE (reg), byte, mode) >= 0))) 4246 || (GET_MODE_PRECISION (mode) 4247 < GET_MODE_PRECISION (GET_MODE (reg)) 4248 && GET_MODE_SIZE (GET_MODE (reg)) <= UNITS_PER_WORD 4249 && WORD_REGISTER_OPERATIONS))) 4250 { 4251 /* An OP_INOUT is required when reloading a subreg of a 4252 mode wider than a word to ensure that data beyond the 4253 word being reloaded is preserved. Also automatically 4254 ensure that strict_low_part reloads are made into 4255 OP_INOUT which should already be true from the backend 4256 constraints. */ 4257 if (type == OP_OUT 4258 && (curr_static_id->operand[i].strict_low 4259 || (GET_MODE_SIZE (GET_MODE (reg)) > UNITS_PER_WORD 4260 && (GET_MODE_SIZE (mode) 4261 < GET_MODE_SIZE (GET_MODE (reg)))))) 4262 type = OP_INOUT; 4263 loc = &SUBREG_REG (*loc); 4264 mode = GET_MODE (*loc); 4265 } 4266 } 4267 old = *loc; 4268 if (get_reload_reg (type, mode, old, goal_alt[i], 4269 loc != curr_id->operand_loc[i], "", &new_reg) 4270 && type != OP_OUT) 4271 { 4272 push_to_sequence (before); 4273 lra_emit_move (new_reg, old); 4274 before = get_insns (); 4275 end_sequence (); 4276 } 4277 *loc = new_reg; 4278 if (type != OP_IN 4279 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) 4280 { 4281 start_sequence (); 4282 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); 4283 emit_insn (after); 4284 after = get_insns (); 4285 end_sequence (); 4286 *loc = new_reg; 4287 } 4288 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) 4289 if (goal_alt_dont_inherit_ops[j] == i) 4290 { 4291 lra_set_regno_unique_value (REGNO (new_reg)); 4292 break; 4293 } 4294 lra_update_dup (curr_id, i); 4295 } 4296 else if (curr_static_id->operand[i].type == OP_IN 4297 && (curr_static_id->operand[goal_alt_matched[i][0]].type 4298 == OP_OUT 4299 || (curr_static_id->operand[goal_alt_matched[i][0]].type 4300 == OP_INOUT 4301 && (operands_match_p 4302 (*curr_id->operand_loc[i], 4303 *curr_id->operand_loc[goal_alt_matched[i][0]], 4304 -1))))) 4305 { 4306 /* generate reloads for input and matched outputs. */ 4307 match_inputs[0] = i; 4308 match_inputs[1] = -1; 4309 match_reload (goal_alt_matched[i][0], match_inputs, outputs, 4310 goal_alt[i], &before, &after, 4311 curr_static_id->operand_alternative 4312 [goal_alt_number * n_operands + goal_alt_matched[i][0]] 4313 .earlyclobber); 4314 } 4315 else if ((curr_static_id->operand[i].type == OP_OUT 4316 || (curr_static_id->operand[i].type == OP_INOUT 4317 && (operands_match_p 4318 (*curr_id->operand_loc[i], 4319 *curr_id->operand_loc[goal_alt_matched[i][0]], 4320 -1)))) 4321 && (curr_static_id->operand[goal_alt_matched[i][0]].type 4322 == OP_IN)) 4323 /* Generate reloads for output and matched inputs. */ 4324 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, 4325 &after, curr_static_id->operand_alternative 4326 [goal_alt_number * n_operands + i].earlyclobber); 4327 else if (curr_static_id->operand[i].type == OP_IN 4328 && (curr_static_id->operand[goal_alt_matched[i][0]].type 4329 == OP_IN)) 4330 { 4331 /* Generate reloads for matched inputs. */ 4332 match_inputs[0] = i; 4333 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) 4334 match_inputs[j + 1] = k; 4335 match_inputs[j + 1] = -1; 4336 match_reload (-1, match_inputs, outputs, goal_alt[i], &before, 4337 &after, false); 4338 } 4339 else 4340 /* We must generate code in any case when function 4341 process_alt_operands decides that it is possible. */ 4342 gcc_unreachable (); 4343 4344 /* Memorise processed outputs so that output remaining to be processed 4345 can avoid using the same register value (see match_reload). */ 4346 if (curr_static_id->operand[i].type == OP_OUT) 4347 { 4348 outputs[n_outputs++] = i; 4349 outputs[n_outputs] = -1; 4350 } 4351 4352 if (optional_p) 4353 { 4354 rtx reg = op; 4355 4356 lra_assert (REG_P (reg)); 4357 regno = REGNO (reg); 4358 op = *curr_id->operand_loc[i]; /* Substitution. */ 4359 if (GET_CODE (op) == SUBREG) 4360 op = SUBREG_REG (op); 4361 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); 4362 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); 4363 lra_reg_info[REGNO (op)].restore_rtx = reg; 4364 if (lra_dump_file != NULL) 4365 fprintf (lra_dump_file, 4366 " Making reload reg %d for reg %d optional\n", 4367 REGNO (op), regno); 4368 } 4369 } 4370 if (before != NULL_RTX || after != NULL_RTX 4371 || max_regno_before != max_reg_num ()) 4372 change_p = true; 4373 if (change_p) 4374 { 4375 lra_update_operator_dups (curr_id); 4376 /* Something changes -- process the insn. */ 4377 lra_update_insn_regno_info (curr_insn); 4378 } 4379 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); 4380 return change_p; 4381 } 4382 4383 /* Return true if INSN satisfies all constraints. In other words, no 4384 reload insns are needed. */ 4385 bool 4386 lra_constrain_insn (rtx_insn *insn) 4387 { 4388 int saved_new_regno_start = new_regno_start; 4389 int saved_new_insn_uid_start = new_insn_uid_start; 4390 bool change_p; 4391 4392 curr_insn = insn; 4393 curr_id = lra_get_insn_recog_data (curr_insn); 4394 curr_static_id = curr_id->insn_static_data; 4395 new_insn_uid_start = get_max_uid (); 4396 new_regno_start = max_reg_num (); 4397 change_p = curr_insn_transform (true); 4398 new_regno_start = saved_new_regno_start; 4399 new_insn_uid_start = saved_new_insn_uid_start; 4400 return ! change_p; 4401 } 4402 4403 /* Return true if X is in LIST. */ 4404 static bool 4405 in_list_p (rtx x, rtx list) 4406 { 4407 for (; list != NULL_RTX; list = XEXP (list, 1)) 4408 if (XEXP (list, 0) == x) 4409 return true; 4410 return false; 4411 } 4412 4413 /* Return true if X contains an allocatable hard register (if 4414 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ 4415 static bool 4416 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) 4417 { 4418 int i, j; 4419 const char *fmt; 4420 enum rtx_code code; 4421 4422 code = GET_CODE (x); 4423 if (REG_P (x)) 4424 { 4425 int regno = REGNO (x); 4426 HARD_REG_SET alloc_regs; 4427 4428 if (hard_reg_p) 4429 { 4430 if (regno >= FIRST_PSEUDO_REGISTER) 4431 regno = lra_get_regno_hard_regno (regno); 4432 if (regno < 0) 4433 return false; 4434 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); 4435 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); 4436 } 4437 else 4438 { 4439 if (regno < FIRST_PSEUDO_REGISTER) 4440 return false; 4441 if (! spilled_p) 4442 return true; 4443 return lra_get_regno_hard_regno (regno) < 0; 4444 } 4445 } 4446 fmt = GET_RTX_FORMAT (code); 4447 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4448 { 4449 if (fmt[i] == 'e') 4450 { 4451 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) 4452 return true; 4453 } 4454 else if (fmt[i] == 'E') 4455 { 4456 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 4457 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) 4458 return true; 4459 } 4460 } 4461 return false; 4462 } 4463 4464 /* Process all regs in location *LOC and change them on equivalent 4465 substitution. Return true if any change was done. */ 4466 static bool 4467 loc_equivalence_change_p (rtx *loc) 4468 { 4469 rtx subst, reg, x = *loc; 4470 bool result = false; 4471 enum rtx_code code = GET_CODE (x); 4472 const char *fmt; 4473 int i, j; 4474 4475 if (code == SUBREG) 4476 { 4477 reg = SUBREG_REG (x); 4478 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg 4479 && GET_MODE (subst) == VOIDmode) 4480 { 4481 /* We cannot reload debug location. Simplify subreg here 4482 while we know the inner mode. */ 4483 *loc = simplify_gen_subreg (GET_MODE (x), subst, 4484 GET_MODE (reg), SUBREG_BYTE (x)); 4485 return true; 4486 } 4487 } 4488 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) 4489 { 4490 *loc = subst; 4491 return true; 4492 } 4493 4494 /* Scan all the operand sub-expressions. */ 4495 fmt = GET_RTX_FORMAT (code); 4496 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4497 { 4498 if (fmt[i] == 'e') 4499 result = loc_equivalence_change_p (&XEXP (x, i)) || result; 4500 else if (fmt[i] == 'E') 4501 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 4502 result 4503 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; 4504 } 4505 return result; 4506 } 4507 4508 /* Similar to loc_equivalence_change_p, but for use as 4509 simplify_replace_fn_rtx callback. DATA is insn for which the 4510 elimination is done. If it null we don't do the elimination. */ 4511 static rtx 4512 loc_equivalence_callback (rtx loc, const_rtx, void *data) 4513 { 4514 if (!REG_P (loc)) 4515 return NULL_RTX; 4516 4517 rtx subst = (data == NULL 4518 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); 4519 if (subst != loc) 4520 return subst; 4521 4522 return NULL_RTX; 4523 } 4524 4525 /* Maximum number of generated reload insns per an insn. It is for 4526 preventing this pass cycling in a bug case. */ 4527 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS 4528 4529 /* The current iteration number of this LRA pass. */ 4530 int lra_constraint_iter; 4531 4532 /* True if we substituted equiv which needs checking register 4533 allocation correctness because the equivalent value contains 4534 allocatable hard registers or when we restore multi-register 4535 pseudo. */ 4536 bool lra_risky_transformations_p; 4537 4538 /* Return true if REGNO is referenced in more than one block. */ 4539 static bool 4540 multi_block_pseudo_p (int regno) 4541 { 4542 basic_block bb = NULL; 4543 unsigned int uid; 4544 bitmap_iterator bi; 4545 4546 if (regno < FIRST_PSEUDO_REGISTER) 4547 return false; 4548 4549 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) 4550 if (bb == NULL) 4551 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); 4552 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) 4553 return true; 4554 return false; 4555 } 4556 4557 /* Return true if LIST contains a deleted insn. */ 4558 static bool 4559 contains_deleted_insn_p (rtx_insn_list *list) 4560 { 4561 for (; list != NULL_RTX; list = list->next ()) 4562 if (NOTE_P (list->insn ()) 4563 && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) 4564 return true; 4565 return false; 4566 } 4567 4568 /* Return true if X contains a pseudo dying in INSN. */ 4569 static bool 4570 dead_pseudo_p (rtx x, rtx_insn *insn) 4571 { 4572 int i, j; 4573 const char *fmt; 4574 enum rtx_code code; 4575 4576 if (REG_P (x)) 4577 return (insn != NULL_RTX 4578 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); 4579 code = GET_CODE (x); 4580 fmt = GET_RTX_FORMAT (code); 4581 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4582 { 4583 if (fmt[i] == 'e') 4584 { 4585 if (dead_pseudo_p (XEXP (x, i), insn)) 4586 return true; 4587 } 4588 else if (fmt[i] == 'E') 4589 { 4590 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 4591 if (dead_pseudo_p (XVECEXP (x, i, j), insn)) 4592 return true; 4593 } 4594 } 4595 return false; 4596 } 4597 4598 /* Return true if INSN contains a dying pseudo in INSN right hand 4599 side. */ 4600 static bool 4601 insn_rhs_dead_pseudo_p (rtx_insn *insn) 4602 { 4603 rtx set = single_set (insn); 4604 4605 gcc_assert (set != NULL); 4606 return dead_pseudo_p (SET_SRC (set), insn); 4607 } 4608 4609 /* Return true if any init insn of REGNO contains a dying pseudo in 4610 insn right hand side. */ 4611 static bool 4612 init_insn_rhs_dead_pseudo_p (int regno) 4613 { 4614 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; 4615 4616 if (insns == NULL) 4617 return false; 4618 for (; insns != NULL_RTX; insns = insns->next ()) 4619 if (insn_rhs_dead_pseudo_p (insns->insn ())) 4620 return true; 4621 return false; 4622 } 4623 4624 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is 4625 reverse only if we have one init insn with given REGNO as a 4626 source. */ 4627 static bool 4628 reverse_equiv_p (int regno) 4629 { 4630 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; 4631 rtx set; 4632 4633 if (insns == NULL) 4634 return false; 4635 if (! INSN_P (insns->insn ()) 4636 || insns->next () != NULL) 4637 return false; 4638 if ((set = single_set (insns->insn ())) == NULL_RTX) 4639 return false; 4640 return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; 4641 } 4642 4643 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We 4644 call this function only for non-reverse equivalence. */ 4645 static bool 4646 contains_reloaded_insn_p (int regno) 4647 { 4648 rtx set; 4649 rtx_insn_list *list = ira_reg_equiv[regno].init_insns; 4650 4651 for (; list != NULL; list = list->next ()) 4652 if ((set = single_set (list->insn ())) == NULL_RTX 4653 || ! REG_P (SET_DEST (set)) 4654 || (int) REGNO (SET_DEST (set)) != regno) 4655 return true; 4656 return false; 4657 } 4658 4659 /* Entry function of LRA constraint pass. Return true if the 4660 constraint pass did change the code. */ 4661 bool 4662 lra_constraints (bool first_p) 4663 { 4664 bool changed_p; 4665 int i, hard_regno, new_insns_num; 4666 unsigned int min_len, new_min_len, uid; 4667 rtx set, x, reg, dest_reg; 4668 basic_block last_bb; 4669 bitmap_head equiv_insn_bitmap; 4670 bitmap_iterator bi; 4671 4672 lra_constraint_iter++; 4673 if (lra_dump_file != NULL) 4674 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", 4675 lra_constraint_iter); 4676 changed_p = false; 4677 if (pic_offset_table_rtx 4678 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) 4679 lra_risky_transformations_p = true; 4680 else 4681 /* On the first iteration we should check IRA assignment 4682 correctness. In rare cases, the assignments can be wrong as 4683 early clobbers operands are ignored in IRA. */ 4684 lra_risky_transformations_p = first_p; 4685 new_insn_uid_start = get_max_uid (); 4686 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); 4687 /* Mark used hard regs for target stack size calulations. */ 4688 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 4689 if (lra_reg_info[i].nrefs != 0 4690 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) 4691 { 4692 int j, nregs; 4693 4694 nregs = hard_regno_nregs[hard_regno][lra_reg_info[i].biggest_mode]; 4695 for (j = 0; j < nregs; j++) 4696 df_set_regs_ever_live (hard_regno + j, true); 4697 } 4698 /* Do elimination before the equivalence processing as we can spill 4699 some pseudos during elimination. */ 4700 lra_eliminate (false, first_p); 4701 bitmap_initialize (&equiv_insn_bitmap, ®_obstack); 4702 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 4703 if (lra_reg_info[i].nrefs != 0) 4704 { 4705 ira_reg_equiv[i].profitable_p = true; 4706 reg = regno_reg_rtx[i]; 4707 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) 4708 { 4709 bool pseudo_p = contains_reg_p (x, false, false); 4710 4711 /* After RTL transformation, we can not guarantee that 4712 pseudo in the substitution was not reloaded which might 4713 make equivalence invalid. For example, in reverse 4714 equiv of p0 4715 4716 p0 <- ... 4717 ... 4718 equiv_mem <- p0 4719 4720 the memory address register was reloaded before the 2nd 4721 insn. */ 4722 if ((! first_p && pseudo_p) 4723 /* We don't use DF for compilation speed sake. So it 4724 is problematic to update live info when we use an 4725 equivalence containing pseudos in more than one 4726 BB. */ 4727 || (pseudo_p && multi_block_pseudo_p (i)) 4728 /* If an init insn was deleted for some reason, cancel 4729 the equiv. We could update the equiv insns after 4730 transformations including an equiv insn deletion 4731 but it is not worthy as such cases are extremely 4732 rare. */ 4733 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) 4734 /* If it is not a reverse equivalence, we check that a 4735 pseudo in rhs of the init insn is not dying in the 4736 insn. Otherwise, the live info at the beginning of 4737 the corresponding BB might be wrong after we 4738 removed the insn. When the equiv can be a 4739 constant, the right hand side of the init insn can 4740 be a pseudo. */ 4741 || (! reverse_equiv_p (i) 4742 && (init_insn_rhs_dead_pseudo_p (i) 4743 /* If we reloaded the pseudo in an equivalence 4744 init insn, we can not remove the equiv init 4745 insns and the init insns might write into 4746 const memory in this case. */ 4747 || contains_reloaded_insn_p (i))) 4748 /* Prevent access beyond equivalent memory for 4749 paradoxical subregs. */ 4750 || (MEM_P (x) 4751 && (GET_MODE_SIZE (lra_reg_info[i].biggest_mode) 4752 > GET_MODE_SIZE (GET_MODE (x)))) 4753 || (pic_offset_table_rtx 4754 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) 4755 && (targetm.preferred_reload_class 4756 (x, lra_get_allocno_class (i)) == NO_REGS)) 4757 || contains_symbol_ref_p (x)))) 4758 ira_reg_equiv[i].defined_p = false; 4759 if (contains_reg_p (x, false, true)) 4760 ira_reg_equiv[i].profitable_p = false; 4761 if (get_equiv (reg) != reg) 4762 bitmap_ior_into (&equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); 4763 } 4764 } 4765 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 4766 update_equiv (i); 4767 /* We should add all insns containing pseudos which should be 4768 substituted by their equivalences. */ 4769 EXECUTE_IF_SET_IN_BITMAP (&equiv_insn_bitmap, 0, uid, bi) 4770 lra_push_insn_by_uid (uid); 4771 min_len = lra_insn_stack_length (); 4772 new_insns_num = 0; 4773 last_bb = NULL; 4774 changed_p = false; 4775 while ((new_min_len = lra_insn_stack_length ()) != 0) 4776 { 4777 curr_insn = lra_pop_insn (); 4778 --new_min_len; 4779 curr_bb = BLOCK_FOR_INSN (curr_insn); 4780 if (curr_bb != last_bb) 4781 { 4782 last_bb = curr_bb; 4783 bb_reload_num = lra_curr_reload_num; 4784 } 4785 if (min_len > new_min_len) 4786 { 4787 min_len = new_min_len; 4788 new_insns_num = 0; 4789 } 4790 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) 4791 internal_error 4792 ("Max. number of generated reload insns per insn is achieved (%d)\n", 4793 MAX_RELOAD_INSNS_NUMBER); 4794 new_insns_num++; 4795 if (DEBUG_INSN_P (curr_insn)) 4796 { 4797 /* We need to check equivalence in debug insn and change 4798 pseudo to the equivalent value if necessary. */ 4799 curr_id = lra_get_insn_recog_data (curr_insn); 4800 if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn))) 4801 { 4802 rtx old = *curr_id->operand_loc[0]; 4803 *curr_id->operand_loc[0] 4804 = simplify_replace_fn_rtx (old, NULL_RTX, 4805 loc_equivalence_callback, curr_insn); 4806 if (old != *curr_id->operand_loc[0]) 4807 { 4808 lra_update_insn_regno_info (curr_insn); 4809 changed_p = true; 4810 } 4811 } 4812 } 4813 else if (INSN_P (curr_insn)) 4814 { 4815 if ((set = single_set (curr_insn)) != NULL_RTX) 4816 { 4817 dest_reg = SET_DEST (set); 4818 /* The equivalence pseudo could be set up as SUBREG in a 4819 case when it is a call restore insn in a mode 4820 different from the pseudo mode. */ 4821 if (GET_CODE (dest_reg) == SUBREG) 4822 dest_reg = SUBREG_REG (dest_reg); 4823 if ((REG_P (dest_reg) 4824 && (x = get_equiv (dest_reg)) != dest_reg 4825 /* Remove insns which set up a pseudo whose value 4826 can not be changed. Such insns might be not in 4827 init_insns because we don't update equiv data 4828 during insn transformations. 4829 4830 As an example, let suppose that a pseudo got 4831 hard register and on the 1st pass was not 4832 changed to equivalent constant. We generate an 4833 additional insn setting up the pseudo because of 4834 secondary memory movement. Then the pseudo is 4835 spilled and we use the equiv constant. In this 4836 case we should remove the additional insn and 4837 this insn is not init_insns list. */ 4838 && (! MEM_P (x) || MEM_READONLY_P (x) 4839 /* Check that this is actually an insn setting 4840 up the equivalence. */ 4841 || in_list_p (curr_insn, 4842 ira_reg_equiv 4843 [REGNO (dest_reg)].init_insns))) 4844 || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) 4845 && in_list_p (curr_insn, 4846 ira_reg_equiv 4847 [REGNO (SET_SRC (set))].init_insns))) 4848 { 4849 /* This is equiv init insn of pseudo which did not get a 4850 hard register -- remove the insn. */ 4851 if (lra_dump_file != NULL) 4852 { 4853 fprintf (lra_dump_file, 4854 " Removing equiv init insn %i (freq=%d)\n", 4855 INSN_UID (curr_insn), 4856 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); 4857 dump_insn_slim (lra_dump_file, curr_insn); 4858 } 4859 if (contains_reg_p (x, true, false)) 4860 lra_risky_transformations_p = true; 4861 lra_set_insn_deleted (curr_insn); 4862 continue; 4863 } 4864 } 4865 curr_id = lra_get_insn_recog_data (curr_insn); 4866 curr_static_id = curr_id->insn_static_data; 4867 init_curr_insn_input_reloads (); 4868 init_curr_operand_mode (); 4869 if (curr_insn_transform (false)) 4870 changed_p = true; 4871 /* Check non-transformed insns too for equiv change as USE 4872 or CLOBBER don't need reloads but can contain pseudos 4873 being changed on their equivalences. */ 4874 else if (bitmap_bit_p (&equiv_insn_bitmap, INSN_UID (curr_insn)) 4875 && loc_equivalence_change_p (&PATTERN (curr_insn))) 4876 { 4877 lra_update_insn_regno_info (curr_insn); 4878 changed_p = true; 4879 } 4880 } 4881 } 4882 bitmap_clear (&equiv_insn_bitmap); 4883 /* If we used a new hard regno, changed_p should be true because the 4884 hard reg is assigned to a new pseudo. */ 4885 if (flag_checking && !changed_p) 4886 { 4887 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 4888 if (lra_reg_info[i].nrefs != 0 4889 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) 4890 { 4891 int j, nregs = hard_regno_nregs[hard_regno][PSEUDO_REGNO_MODE (i)]; 4892 4893 for (j = 0; j < nregs; j++) 4894 lra_assert (df_regs_ever_live_p (hard_regno + j)); 4895 } 4896 } 4897 return changed_p; 4898 } 4899 4900 static void initiate_invariants (void); 4901 static void finish_invariants (void); 4902 4903 /* Initiate the LRA constraint pass. It is done once per 4904 function. */ 4905 void 4906 lra_constraints_init (void) 4907 { 4908 initiate_invariants (); 4909 } 4910 4911 /* Finalize the LRA constraint pass. It is done once per 4912 function. */ 4913 void 4914 lra_constraints_finish (void) 4915 { 4916 finish_invariants (); 4917 } 4918 4919 4920 4921 /* Structure describes invariants for ineheritance. */ 4922 struct lra_invariant 4923 { 4924 /* The order number of the invariant. */ 4925 int num; 4926 /* The invariant RTX. */ 4927 rtx invariant_rtx; 4928 /* The origin insn of the invariant. */ 4929 rtx_insn *insn; 4930 }; 4931 4932 typedef lra_invariant invariant_t; 4933 typedef invariant_t *invariant_ptr_t; 4934 typedef const invariant_t *const_invariant_ptr_t; 4935 4936 /* Pointer to the inheritance invariants. */ 4937 static vec<invariant_ptr_t> invariants; 4938 4939 /* Allocation pool for the invariants. */ 4940 static object_allocator<lra_invariant> *invariants_pool; 4941 4942 /* Hash table for the invariants. */ 4943 static htab_t invariant_table; 4944 4945 /* Hash function for INVARIANT. */ 4946 static hashval_t 4947 invariant_hash (const void *invariant) 4948 { 4949 rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx; 4950 return lra_rtx_hash (inv); 4951 } 4952 4953 /* Equal function for invariants INVARIANT1 and INVARIANT2. */ 4954 static int 4955 invariant_eq_p (const void *invariant1, const void *invariant2) 4956 { 4957 rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx; 4958 rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx; 4959 4960 return rtx_equal_p (inv1, inv2); 4961 } 4962 4963 /* Insert INVARIANT_RTX into the table if it is not there yet. Return 4964 invariant which is in the table. */ 4965 static invariant_ptr_t 4966 insert_invariant (rtx invariant_rtx) 4967 { 4968 void **entry_ptr; 4969 invariant_t invariant; 4970 invariant_ptr_t invariant_ptr; 4971 4972 invariant.invariant_rtx = invariant_rtx; 4973 entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT); 4974 if (*entry_ptr == NULL) 4975 { 4976 invariant_ptr = invariants_pool->allocate (); 4977 invariant_ptr->invariant_rtx = invariant_rtx; 4978 invariant_ptr->insn = NULL; 4979 invariants.safe_push (invariant_ptr); 4980 *entry_ptr = (void *) invariant_ptr; 4981 } 4982 return (invariant_ptr_t) *entry_ptr; 4983 } 4984 4985 /* Initiate the invariant table. */ 4986 static void 4987 initiate_invariants (void) 4988 { 4989 invariants.create (100); 4990 invariants_pool 4991 = new object_allocator<lra_invariant> ("Inheritance invariants"); 4992 invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL); 4993 } 4994 4995 /* Finish the invariant table. */ 4996 static void 4997 finish_invariants (void) 4998 { 4999 htab_delete (invariant_table); 5000 delete invariants_pool; 5001 invariants.release (); 5002 } 5003 5004 /* Make the invariant table empty. */ 5005 static void 5006 clear_invariants (void) 5007 { 5008 htab_empty (invariant_table); 5009 invariants_pool->release (); 5010 invariants.truncate (0); 5011 } 5012 5013 5014 5015 /* This page contains code to do inheritance/split 5016 transformations. */ 5017 5018 /* Number of reloads passed so far in current EBB. */ 5019 static int reloads_num; 5020 5021 /* Number of calls passed so far in current EBB. */ 5022 static int calls_num; 5023 5024 /* Current reload pseudo check for validity of elements in 5025 USAGE_INSNS. */ 5026 static int curr_usage_insns_check; 5027 5028 /* Info about last usage of registers in EBB to do inheritance/split 5029 transformation. Inheritance transformation is done from a spilled 5030 pseudo and split transformations from a hard register or a pseudo 5031 assigned to a hard register. */ 5032 struct usage_insns 5033 { 5034 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member 5035 value INSNS is valid. The insns is chain of optional debug insns 5036 and a finishing non-debug insn using the corresponding reg. The 5037 value is also used to mark the registers which are set up in the 5038 current insn. The negated insn uid is used for this. */ 5039 int check; 5040 /* Value of global reloads_num at the last insn in INSNS. */ 5041 int reloads_num; 5042 /* Value of global reloads_nums at the last insn in INSNS. */ 5043 int calls_num; 5044 /* It can be true only for splitting. And it means that the restore 5045 insn should be put after insn given by the following member. */ 5046 bool after_p; 5047 /* Next insns in the current EBB which use the original reg and the 5048 original reg value is not changed between the current insn and 5049 the next insns. In order words, e.g. for inheritance, if we need 5050 to use the original reg value again in the next insns we can try 5051 to use the value in a hard register from a reload insn of the 5052 current insn. */ 5053 rtx insns; 5054 }; 5055 5056 /* Map: regno -> corresponding pseudo usage insns. */ 5057 static struct usage_insns *usage_insns; 5058 5059 static void 5060 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) 5061 { 5062 usage_insns[regno].check = curr_usage_insns_check; 5063 usage_insns[regno].insns = insn; 5064 usage_insns[regno].reloads_num = reloads_num; 5065 usage_insns[regno].calls_num = calls_num; 5066 usage_insns[regno].after_p = after_p; 5067 } 5068 5069 /* The function is used to form list REGNO usages which consists of 5070 optional debug insns finished by a non-debug insn using REGNO. 5071 RELOADS_NUM is current number of reload insns processed so far. */ 5072 static void 5073 add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) 5074 { 5075 rtx next_usage_insns; 5076 5077 if (usage_insns[regno].check == curr_usage_insns_check 5078 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX 5079 && DEBUG_INSN_P (insn)) 5080 { 5081 /* Check that we did not add the debug insn yet. */ 5082 if (next_usage_insns != insn 5083 && (GET_CODE (next_usage_insns) != INSN_LIST 5084 || XEXP (next_usage_insns, 0) != insn)) 5085 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, 5086 next_usage_insns); 5087 } 5088 else if (NONDEBUG_INSN_P (insn)) 5089 setup_next_usage_insn (regno, insn, reloads_num, false); 5090 else 5091 usage_insns[regno].check = 0; 5092 } 5093 5094 /* Return first non-debug insn in list USAGE_INSNS. */ 5095 static rtx_insn * 5096 skip_usage_debug_insns (rtx usage_insns) 5097 { 5098 rtx insn; 5099 5100 /* Skip debug insns. */ 5101 for (insn = usage_insns; 5102 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; 5103 insn = XEXP (insn, 1)) 5104 ; 5105 return safe_as_a <rtx_insn *> (insn); 5106 } 5107 5108 /* Return true if we need secondary memory moves for insn in 5109 USAGE_INSNS after inserting inherited pseudo of class INHER_CL 5110 into the insn. */ 5111 static bool 5112 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, 5113 rtx usage_insns ATTRIBUTE_UNUSED) 5114 { 5115 #ifndef SECONDARY_MEMORY_NEEDED 5116 return false; 5117 #else 5118 rtx_insn *insn; 5119 rtx set, dest; 5120 enum reg_class cl; 5121 5122 if (inher_cl == ALL_REGS 5123 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) 5124 return false; 5125 lra_assert (INSN_P (insn)); 5126 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) 5127 return false; 5128 dest = SET_DEST (set); 5129 if (! REG_P (dest)) 5130 return false; 5131 lra_assert (inher_cl != NO_REGS); 5132 cl = get_reg_class (REGNO (dest)); 5133 return (cl != NO_REGS && cl != ALL_REGS 5134 && SECONDARY_MEMORY_NEEDED (inher_cl, cl, GET_MODE (dest))); 5135 #endif 5136 } 5137 5138 /* Registers involved in inheritance/split in the current EBB 5139 (inheritance/split pseudos and original registers). */ 5140 static bitmap_head check_only_regs; 5141 5142 /* Reload pseudos can not be involded in invariant inheritance in the 5143 current EBB. */ 5144 static bitmap_head invalid_invariant_regs; 5145 5146 /* Do inheritance transformations for insn INSN, which defines (if 5147 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which 5148 instruction in the EBB next uses ORIGINAL_REGNO; it has the same 5149 form as the "insns" field of usage_insns. Return true if we 5150 succeed in such transformation. 5151 5152 The transformations look like: 5153 5154 p <- ... i <- ... 5155 ... p <- i (new insn) 5156 ... => 5157 <- ... p ... <- ... i ... 5158 or 5159 ... i <- p (new insn) 5160 <- ... p ... <- ... i ... 5161 ... => 5162 <- ... p ... <- ... i ... 5163 where p is a spilled original pseudo and i is a new inheritance pseudo. 5164 5165 5166 The inheritance pseudo has the smallest class of two classes CL and 5167 class of ORIGINAL REGNO. */ 5168 static bool 5169 inherit_reload_reg (bool def_p, int original_regno, 5170 enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) 5171 { 5172 if (optimize_function_for_size_p (cfun)) 5173 return false; 5174 5175 enum reg_class rclass = lra_get_allocno_class (original_regno); 5176 rtx original_reg = regno_reg_rtx[original_regno]; 5177 rtx new_reg, usage_insn; 5178 rtx_insn *new_insns; 5179 5180 lra_assert (! usage_insns[original_regno].after_p); 5181 if (lra_dump_file != NULL) 5182 fprintf (lra_dump_file, 5183 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); 5184 if (! ira_reg_classes_intersect_p[cl][rclass]) 5185 { 5186 if (lra_dump_file != NULL) 5187 { 5188 fprintf (lra_dump_file, 5189 " Rejecting inheritance for %d " 5190 "because of disjoint classes %s and %s\n", 5191 original_regno, reg_class_names[cl], 5192 reg_class_names[rclass]); 5193 fprintf (lra_dump_file, 5194 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 5195 } 5196 return false; 5197 } 5198 if ((ira_class_subset_p[cl][rclass] && cl != rclass) 5199 /* We don't use a subset of two classes because it can be 5200 NO_REGS. This transformation is still profitable in most 5201 cases even if the classes are not intersected as register 5202 move is probably cheaper than a memory load. */ 5203 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) 5204 { 5205 if (lra_dump_file != NULL) 5206 fprintf (lra_dump_file, " Use smallest class of %s and %s\n", 5207 reg_class_names[cl], reg_class_names[rclass]); 5208 5209 rclass = cl; 5210 } 5211 if (check_secondary_memory_needed_p (rclass, next_usage_insns)) 5212 { 5213 /* Reject inheritance resulting in secondary memory moves. 5214 Otherwise, there is a danger in LRA cycling. Also such 5215 transformation will be unprofitable. */ 5216 if (lra_dump_file != NULL) 5217 { 5218 rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); 5219 rtx set = single_set (insn); 5220 5221 lra_assert (set != NULL_RTX); 5222 5223 rtx dest = SET_DEST (set); 5224 5225 lra_assert (REG_P (dest)); 5226 fprintf (lra_dump_file, 5227 " Rejecting inheritance for insn %d(%s)<-%d(%s) " 5228 "as secondary mem is needed\n", 5229 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], 5230 original_regno, reg_class_names[rclass]); 5231 fprintf (lra_dump_file, 5232 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 5233 } 5234 return false; 5235 } 5236 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, 5237 rclass, "inheritance"); 5238 start_sequence (); 5239 if (def_p) 5240 lra_emit_move (original_reg, new_reg); 5241 else 5242 lra_emit_move (new_reg, original_reg); 5243 new_insns = get_insns (); 5244 end_sequence (); 5245 if (NEXT_INSN (new_insns) != NULL_RTX) 5246 { 5247 if (lra_dump_file != NULL) 5248 { 5249 fprintf (lra_dump_file, 5250 " Rejecting inheritance %d->%d " 5251 "as it results in 2 or more insns:\n", 5252 original_regno, REGNO (new_reg)); 5253 dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); 5254 fprintf (lra_dump_file, 5255 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 5256 } 5257 return false; 5258 } 5259 lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); 5260 lra_update_insn_regno_info (insn); 5261 if (! def_p) 5262 /* We now have a new usage insn for original regno. */ 5263 setup_next_usage_insn (original_regno, new_insns, reloads_num, false); 5264 if (lra_dump_file != NULL) 5265 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", 5266 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); 5267 lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; 5268 bitmap_set_bit (&check_only_regs, REGNO (new_reg)); 5269 bitmap_set_bit (&check_only_regs, original_regno); 5270 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); 5271 if (def_p) 5272 lra_process_new_insns (insn, NULL, new_insns, 5273 "Add original<-inheritance"); 5274 else 5275 lra_process_new_insns (insn, new_insns, NULL, 5276 "Add inheritance<-original"); 5277 while (next_usage_insns != NULL_RTX) 5278 { 5279 if (GET_CODE (next_usage_insns) != INSN_LIST) 5280 { 5281 usage_insn = next_usage_insns; 5282 lra_assert (NONDEBUG_INSN_P (usage_insn)); 5283 next_usage_insns = NULL; 5284 } 5285 else 5286 { 5287 usage_insn = XEXP (next_usage_insns, 0); 5288 lra_assert (DEBUG_INSN_P (usage_insn)); 5289 next_usage_insns = XEXP (next_usage_insns, 1); 5290 } 5291 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false); 5292 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); 5293 if (lra_dump_file != NULL) 5294 { 5295 fprintf (lra_dump_file, 5296 " Inheritance reuse change %d->%d (bb%d):\n", 5297 original_regno, REGNO (new_reg), 5298 BLOCK_FOR_INSN (usage_insn)->index); 5299 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); 5300 } 5301 } 5302 if (lra_dump_file != NULL) 5303 fprintf (lra_dump_file, 5304 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 5305 return true; 5306 } 5307 5308 /* Return true if we need a caller save/restore for pseudo REGNO which 5309 was assigned to a hard register. */ 5310 static inline bool 5311 need_for_call_save_p (int regno) 5312 { 5313 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); 5314 return (usage_insns[regno].calls_num < calls_num 5315 && (overlaps_hard_reg_set_p 5316 ((flag_ipa_ra && 5317 ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set)) 5318 ? lra_reg_info[regno].actual_call_used_reg_set 5319 : call_used_reg_set, 5320 PSEUDO_REGNO_MODE (regno), reg_renumber[regno]) 5321 || HARD_REGNO_CALL_PART_CLOBBERED (reg_renumber[regno], 5322 PSEUDO_REGNO_MODE (regno)))); 5323 } 5324 5325 /* Global registers occurring in the current EBB. */ 5326 static bitmap_head ebb_global_regs; 5327 5328 /* Return true if we need a split for hard register REGNO or pseudo 5329 REGNO which was assigned to a hard register. 5330 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be 5331 used for reloads since the EBB end. It is an approximation of the 5332 used hard registers in the split range. The exact value would 5333 require expensive calculations. If we were aggressive with 5334 splitting because of the approximation, the split pseudo will save 5335 the same hard register assignment and will be removed in the undo 5336 pass. We still need the approximation because too aggressive 5337 splitting would result in too inaccurate cost calculation in the 5338 assignment pass because of too many generated moves which will be 5339 probably removed in the undo pass. */ 5340 static inline bool 5341 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) 5342 { 5343 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; 5344 5345 lra_assert (hard_regno >= 0); 5346 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) 5347 /* Don't split eliminable hard registers, otherwise we can 5348 split hard registers like hard frame pointer, which 5349 lives on BB start/end according to DF-infrastructure, 5350 when there is a pseudo assigned to the register and 5351 living in the same BB. */ 5352 && (regno >= FIRST_PSEUDO_REGISTER 5353 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) 5354 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) 5355 /* Don't split call clobbered hard regs living through 5356 calls, otherwise we might have a check problem in the 5357 assign sub-pass as in the most cases (exception is a 5358 situation when lra_risky_transformations_p value is 5359 true) the assign pass assumes that all pseudos living 5360 through calls are assigned to call saved hard regs. */ 5361 && (regno >= FIRST_PSEUDO_REGISTER 5362 || ! TEST_HARD_REG_BIT (call_used_reg_set, regno) 5363 || usage_insns[regno].calls_num == calls_num) 5364 /* We need at least 2 reloads to make pseudo splitting 5365 profitable. We should provide hard regno splitting in 5366 any case to solve 1st insn scheduling problem when 5367 moving hard register definition up might result in 5368 impossibility to find hard register for reload pseudo of 5369 small register class. */ 5370 && (usage_insns[regno].reloads_num 5371 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) 5372 && (regno < FIRST_PSEUDO_REGISTER 5373 /* For short living pseudos, spilling + inheritance can 5374 be considered a substitution for splitting. 5375 Therefore we do not splitting for local pseudos. It 5376 decreases also aggressiveness of splitting. The 5377 minimal number of references is chosen taking into 5378 account that for 2 references splitting has no sense 5379 as we can just spill the pseudo. */ 5380 || (regno >= FIRST_PSEUDO_REGISTER 5381 && lra_reg_info[regno].nrefs > 3 5382 && bitmap_bit_p (&ebb_global_regs, regno)))) 5383 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); 5384 } 5385 5386 /* Return class for the split pseudo created from original pseudo with 5387 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We 5388 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and 5389 results in no secondary memory movements. */ 5390 static enum reg_class 5391 choose_split_class (enum reg_class allocno_class, 5392 int hard_regno ATTRIBUTE_UNUSED, 5393 machine_mode mode ATTRIBUTE_UNUSED) 5394 { 5395 #ifndef SECONDARY_MEMORY_NEEDED 5396 return allocno_class; 5397 #else 5398 int i; 5399 enum reg_class cl, best_cl = NO_REGS; 5400 enum reg_class hard_reg_class ATTRIBUTE_UNUSED 5401 = REGNO_REG_CLASS (hard_regno); 5402 5403 if (! SECONDARY_MEMORY_NEEDED (allocno_class, allocno_class, mode) 5404 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) 5405 return allocno_class; 5406 for (i = 0; 5407 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; 5408 i++) 5409 if (! SECONDARY_MEMORY_NEEDED (cl, hard_reg_class, mode) 5410 && ! SECONDARY_MEMORY_NEEDED (hard_reg_class, cl, mode) 5411 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) 5412 && (best_cl == NO_REGS 5413 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) 5414 best_cl = cl; 5415 return best_cl; 5416 #endif 5417 } 5418 5419 /* Do split transformations for insn INSN, which defines or uses 5420 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in 5421 the EBB next uses ORIGINAL_REGNO; it has the same form as the 5422 "insns" field of usage_insns. 5423 5424 The transformations look like: 5425 5426 p <- ... p <- ... 5427 ... s <- p (new insn -- save) 5428 ... => 5429 ... p <- s (new insn -- restore) 5430 <- ... p ... <- ... p ... 5431 or 5432 <- ... p ... <- ... p ... 5433 ... s <- p (new insn -- save) 5434 ... => 5435 ... p <- s (new insn -- restore) 5436 <- ... p ... <- ... p ... 5437 5438 where p is an original pseudo got a hard register or a hard 5439 register and s is a new split pseudo. The save is put before INSN 5440 if BEFORE_P is true. Return true if we succeed in such 5441 transformation. */ 5442 static bool 5443 split_reg (bool before_p, int original_regno, rtx_insn *insn, 5444 rtx next_usage_insns) 5445 { 5446 enum reg_class rclass; 5447 rtx original_reg; 5448 int hard_regno, nregs; 5449 rtx new_reg, usage_insn; 5450 rtx_insn *restore, *save; 5451 bool after_p; 5452 bool call_save_p; 5453 machine_mode mode; 5454 5455 if (original_regno < FIRST_PSEUDO_REGISTER) 5456 { 5457 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; 5458 hard_regno = original_regno; 5459 call_save_p = false; 5460 nregs = 1; 5461 mode = lra_reg_info[hard_regno].biggest_mode; 5462 machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]); 5463 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen 5464 as part of a multi-word register. In that case, or if the biggest 5465 mode was larger than a register, just use the reg_rtx. Otherwise, 5466 limit the size to that of the biggest access in the function. */ 5467 if (mode == VOIDmode 5468 || GET_MODE_SIZE (mode) > GET_MODE_SIZE (reg_rtx_mode)) 5469 { 5470 original_reg = regno_reg_rtx[hard_regno]; 5471 mode = reg_rtx_mode; 5472 } 5473 else 5474 original_reg = gen_rtx_REG (mode, hard_regno); 5475 } 5476 else 5477 { 5478 mode = PSEUDO_REGNO_MODE (original_regno); 5479 hard_regno = reg_renumber[original_regno]; 5480 nregs = hard_regno_nregs[hard_regno][mode]; 5481 rclass = lra_get_allocno_class (original_regno); 5482 original_reg = regno_reg_rtx[original_regno]; 5483 call_save_p = need_for_call_save_p (original_regno); 5484 } 5485 lra_assert (hard_regno >= 0); 5486 if (lra_dump_file != NULL) 5487 fprintf (lra_dump_file, 5488 " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); 5489 5490 if (call_save_p) 5491 { 5492 mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, 5493 hard_regno_nregs[hard_regno][mode], 5494 mode); 5495 new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); 5496 } 5497 else 5498 { 5499 rclass = choose_split_class (rclass, hard_regno, mode); 5500 if (rclass == NO_REGS) 5501 { 5502 if (lra_dump_file != NULL) 5503 { 5504 fprintf (lra_dump_file, 5505 " Rejecting split of %d(%s): " 5506 "no good reg class for %d(%s)\n", 5507 original_regno, 5508 reg_class_names[lra_get_allocno_class (original_regno)], 5509 hard_regno, 5510 reg_class_names[REGNO_REG_CLASS (hard_regno)]); 5511 fprintf 5512 (lra_dump_file, 5513 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5514 } 5515 return false; 5516 } 5517 /* Split_if_necessary can split hard registers used as part of a 5518 multi-register mode but splits each register individually. The 5519 mode used for each independent register may not be supported 5520 so reject the split. Splitting the wider mode should theoretically 5521 be possible but is not implemented. */ 5522 if (! HARD_REGNO_MODE_OK (hard_regno, mode)) 5523 { 5524 if (lra_dump_file != NULL) 5525 { 5526 fprintf (lra_dump_file, 5527 " Rejecting split of %d(%s): unsuitable mode %s\n", 5528 original_regno, 5529 reg_class_names[lra_get_allocno_class (original_regno)], 5530 GET_MODE_NAME (mode)); 5531 fprintf 5532 (lra_dump_file, 5533 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5534 } 5535 return false; 5536 } 5537 new_reg = lra_create_new_reg (mode, original_reg, rclass, "split"); 5538 reg_renumber[REGNO (new_reg)] = hard_regno; 5539 } 5540 save = emit_spill_move (true, new_reg, original_reg); 5541 if (NEXT_INSN (save) != NULL_RTX && !call_save_p) 5542 { 5543 if (lra_dump_file != NULL) 5544 { 5545 fprintf 5546 (lra_dump_file, 5547 " Rejecting split %d->%d resulting in > 2 save insns:\n", 5548 original_regno, REGNO (new_reg)); 5549 dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); 5550 fprintf (lra_dump_file, 5551 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5552 } 5553 return false; 5554 } 5555 restore = emit_spill_move (false, new_reg, original_reg); 5556 if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) 5557 { 5558 if (lra_dump_file != NULL) 5559 { 5560 fprintf (lra_dump_file, 5561 " Rejecting split %d->%d " 5562 "resulting in > 2 restore insns:\n", 5563 original_regno, REGNO (new_reg)); 5564 dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); 5565 fprintf (lra_dump_file, 5566 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5567 } 5568 return false; 5569 } 5570 after_p = usage_insns[original_regno].after_p; 5571 lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; 5572 bitmap_set_bit (&check_only_regs, REGNO (new_reg)); 5573 bitmap_set_bit (&check_only_regs, original_regno); 5574 bitmap_set_bit (&lra_split_regs, REGNO (new_reg)); 5575 for (;;) 5576 { 5577 if (GET_CODE (next_usage_insns) != INSN_LIST) 5578 { 5579 usage_insn = next_usage_insns; 5580 break; 5581 } 5582 usage_insn = XEXP (next_usage_insns, 0); 5583 lra_assert (DEBUG_INSN_P (usage_insn)); 5584 next_usage_insns = XEXP (next_usage_insns, 1); 5585 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false); 5586 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); 5587 if (lra_dump_file != NULL) 5588 { 5589 fprintf (lra_dump_file, " Split reuse change %d->%d:\n", 5590 original_regno, REGNO (new_reg)); 5591 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); 5592 } 5593 } 5594 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); 5595 lra_assert (usage_insn != insn || (after_p && before_p)); 5596 lra_process_new_insns (as_a <rtx_insn *> (usage_insn), 5597 after_p ? NULL : restore, 5598 after_p ? restore : NULL, 5599 call_save_p 5600 ? "Add reg<-save" : "Add reg<-split"); 5601 lra_process_new_insns (insn, before_p ? save : NULL, 5602 before_p ? NULL : save, 5603 call_save_p 5604 ? "Add save<-reg" : "Add split<-reg"); 5605 if (nregs > 1) 5606 /* If we are trying to split multi-register. We should check 5607 conflicts on the next assignment sub-pass. IRA can allocate on 5608 sub-register levels, LRA do this on pseudos level right now and 5609 this discrepancy may create allocation conflicts after 5610 splitting. */ 5611 lra_risky_transformations_p = true; 5612 if (lra_dump_file != NULL) 5613 fprintf (lra_dump_file, 5614 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5615 return true; 5616 } 5617 5618 /* Recognize that we need a split transformation for insn INSN, which 5619 defines or uses REGNO in its insn biggest MODE (we use it only if 5620 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains 5621 hard registers which might be used for reloads since the EBB end. 5622 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla 5623 uid before starting INSN processing. Return true if we succeed in 5624 such transformation. */ 5625 static bool 5626 split_if_necessary (int regno, machine_mode mode, 5627 HARD_REG_SET potential_reload_hard_regs, 5628 bool before_p, rtx_insn *insn, int max_uid) 5629 { 5630 bool res = false; 5631 int i, nregs = 1; 5632 rtx next_usage_insns; 5633 5634 if (regno < FIRST_PSEUDO_REGISTER) 5635 nregs = hard_regno_nregs[regno][mode]; 5636 for (i = 0; i < nregs; i++) 5637 if (usage_insns[regno + i].check == curr_usage_insns_check 5638 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX 5639 /* To avoid processing the register twice or more. */ 5640 && ((GET_CODE (next_usage_insns) != INSN_LIST 5641 && INSN_UID (next_usage_insns) < max_uid) 5642 || (GET_CODE (next_usage_insns) == INSN_LIST 5643 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) 5644 && need_for_split_p (potential_reload_hard_regs, regno + i) 5645 && split_reg (before_p, regno + i, insn, next_usage_insns)) 5646 res = true; 5647 return res; 5648 } 5649 5650 /* Return TRUE if rtx X is considered as an invariant for 5651 inheritance. */ 5652 static bool 5653 invariant_p (const_rtx x) 5654 { 5655 machine_mode mode; 5656 const char *fmt; 5657 enum rtx_code code; 5658 int i, j; 5659 5660 code = GET_CODE (x); 5661 mode = GET_MODE (x); 5662 if (code == SUBREG) 5663 { 5664 x = SUBREG_REG (x); 5665 code = GET_CODE (x); 5666 if (GET_MODE_SIZE (GET_MODE (x)) > GET_MODE_SIZE (mode)) 5667 mode = GET_MODE (x); 5668 } 5669 5670 if (MEM_P (x)) 5671 return false; 5672 5673 if (REG_P (x)) 5674 { 5675 int i, nregs, regno = REGNO (x); 5676 5677 if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM 5678 || TEST_HARD_REG_BIT (eliminable_regset, regno) 5679 || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) 5680 return false; 5681 nregs = hard_regno_nregs[regno][mode]; 5682 for (i = 0; i < nregs; i++) 5683 if (! fixed_regs[regno + i] 5684 /* A hard register may be clobbered in the current insn 5685 but we can ignore this case because if the hard 5686 register is used it should be set somewhere after the 5687 clobber. */ 5688 || bitmap_bit_p (&invalid_invariant_regs, regno + i)) 5689 return false; 5690 } 5691 fmt = GET_RTX_FORMAT (code); 5692 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 5693 { 5694 if (fmt[i] == 'e') 5695 { 5696 if (! invariant_p (XEXP (x, i))) 5697 return false; 5698 } 5699 else if (fmt[i] == 'E') 5700 { 5701 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 5702 if (! invariant_p (XVECEXP (x, i, j))) 5703 return false; 5704 } 5705 } 5706 return true; 5707 } 5708 5709 /* We have 'dest_reg <- invariant'. Let us try to make an invariant 5710 inheritance transformation (using dest_reg instead invariant in a 5711 subsequent insn). */ 5712 static bool 5713 process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx) 5714 { 5715 invariant_ptr_t invariant_ptr; 5716 rtx_insn *insn, *new_insns; 5717 rtx insn_set, insn_reg, new_reg; 5718 int insn_regno; 5719 bool succ_p = false; 5720 int dst_regno = REGNO (dst_reg); 5721 enum machine_mode dst_mode = GET_MODE (dst_reg); 5722 enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl; 5723 5724 invariant_ptr = insert_invariant (invariant_rtx); 5725 if ((insn = invariant_ptr->insn) != NULL_RTX) 5726 { 5727 /* We have a subsequent insn using the invariant. */ 5728 insn_set = single_set (insn); 5729 lra_assert (insn_set != NULL); 5730 insn_reg = SET_DEST (insn_set); 5731 lra_assert (REG_P (insn_reg)); 5732 insn_regno = REGNO (insn_reg); 5733 insn_reg_cl = lra_get_allocno_class (insn_regno); 5734 5735 if (dst_mode == GET_MODE (insn_reg) 5736 /* We should consider only result move reg insns which are 5737 cheap. */ 5738 && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2 5739 && targetm.register_move_cost (dst_mode, cl, cl) == 2) 5740 { 5741 if (lra_dump_file != NULL) 5742 fprintf (lra_dump_file, 5743 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); 5744 new_reg = lra_create_new_reg (dst_mode, dst_reg, 5745 cl, "invariant inheritance"); 5746 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); 5747 bitmap_set_bit (&check_only_regs, REGNO (new_reg)); 5748 lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn); 5749 start_sequence (); 5750 lra_emit_move (new_reg, dst_reg); 5751 new_insns = get_insns (); 5752 end_sequence (); 5753 lra_process_new_insns (curr_insn, NULL, new_insns, 5754 "Add invariant inheritance<-original"); 5755 start_sequence (); 5756 lra_emit_move (SET_DEST (insn_set), new_reg); 5757 new_insns = get_insns (); 5758 end_sequence (); 5759 lra_process_new_insns (insn, NULL, new_insns, 5760 "Changing reload<-inheritance"); 5761 lra_set_insn_deleted (insn); 5762 succ_p = true; 5763 if (lra_dump_file != NULL) 5764 { 5765 fprintf (lra_dump_file, 5766 " Invariant inheritance reuse change %d (bb%d):\n", 5767 REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); 5768 dump_insn_slim (lra_dump_file, insn); 5769 fprintf (lra_dump_file, 5770 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n"); 5771 } 5772 } 5773 } 5774 invariant_ptr->insn = curr_insn; 5775 return succ_p; 5776 } 5777 5778 /* Check only registers living at the current program point in the 5779 current EBB. */ 5780 static bitmap_head live_regs; 5781 5782 /* Update live info in EBB given by its HEAD and TAIL insns after 5783 inheritance/split transformation. The function removes dead moves 5784 too. */ 5785 static void 5786 update_ebb_live_info (rtx_insn *head, rtx_insn *tail) 5787 { 5788 unsigned int j; 5789 int i, regno; 5790 bool live_p; 5791 rtx_insn *prev_insn; 5792 rtx set; 5793 bool remove_p; 5794 basic_block last_bb, prev_bb, curr_bb; 5795 bitmap_iterator bi; 5796 struct lra_insn_reg *reg; 5797 edge e; 5798 edge_iterator ei; 5799 5800 last_bb = BLOCK_FOR_INSN (tail); 5801 prev_bb = NULL; 5802 for (curr_insn = tail; 5803 curr_insn != PREV_INSN (head); 5804 curr_insn = prev_insn) 5805 { 5806 prev_insn = PREV_INSN (curr_insn); 5807 /* We need to process empty blocks too. They contain 5808 NOTE_INSN_BASIC_BLOCK referring for the basic block. */ 5809 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) 5810 continue; 5811 curr_bb = BLOCK_FOR_INSN (curr_insn); 5812 if (curr_bb != prev_bb) 5813 { 5814 if (prev_bb != NULL) 5815 { 5816 /* Update df_get_live_in (prev_bb): */ 5817 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) 5818 if (bitmap_bit_p (&live_regs, j)) 5819 bitmap_set_bit (df_get_live_in (prev_bb), j); 5820 else 5821 bitmap_clear_bit (df_get_live_in (prev_bb), j); 5822 } 5823 if (curr_bb != last_bb) 5824 { 5825 /* Update df_get_live_out (curr_bb): */ 5826 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) 5827 { 5828 live_p = bitmap_bit_p (&live_regs, j); 5829 if (! live_p) 5830 FOR_EACH_EDGE (e, ei, curr_bb->succs) 5831 if (bitmap_bit_p (df_get_live_in (e->dest), j)) 5832 { 5833 live_p = true; 5834 break; 5835 } 5836 if (live_p) 5837 bitmap_set_bit (df_get_live_out (curr_bb), j); 5838 else 5839 bitmap_clear_bit (df_get_live_out (curr_bb), j); 5840 } 5841 } 5842 prev_bb = curr_bb; 5843 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); 5844 } 5845 if (! NONDEBUG_INSN_P (curr_insn)) 5846 continue; 5847 curr_id = lra_get_insn_recog_data (curr_insn); 5848 curr_static_id = curr_id->insn_static_data; 5849 remove_p = false; 5850 if ((set = single_set (curr_insn)) != NULL_RTX 5851 && REG_P (SET_DEST (set)) 5852 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER 5853 && SET_DEST (set) != pic_offset_table_rtx 5854 && bitmap_bit_p (&check_only_regs, regno) 5855 && ! bitmap_bit_p (&live_regs, regno)) 5856 remove_p = true; 5857 /* See which defined values die here. */ 5858 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 5859 if (reg->type == OP_OUT && ! reg->subreg_p) 5860 bitmap_clear_bit (&live_regs, reg->regno); 5861 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) 5862 if (reg->type == OP_OUT && ! reg->subreg_p) 5863 bitmap_clear_bit (&live_regs, reg->regno); 5864 if (curr_id->arg_hard_regs != NULL) 5865 /* Make clobbered argument hard registers die. */ 5866 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) 5867 if (regno >= FIRST_PSEUDO_REGISTER) 5868 bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); 5869 /* Mark each used value as live. */ 5870 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 5871 if (reg->type != OP_OUT 5872 && bitmap_bit_p (&check_only_regs, reg->regno)) 5873 bitmap_set_bit (&live_regs, reg->regno); 5874 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) 5875 if (reg->type != OP_OUT 5876 && bitmap_bit_p (&check_only_regs, reg->regno)) 5877 bitmap_set_bit (&live_regs, reg->regno); 5878 if (curr_id->arg_hard_regs != NULL) 5879 /* Make used argument hard registers live. */ 5880 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) 5881 if (regno < FIRST_PSEUDO_REGISTER 5882 && bitmap_bit_p (&check_only_regs, regno)) 5883 bitmap_set_bit (&live_regs, regno); 5884 /* It is quite important to remove dead move insns because it 5885 means removing dead store. We don't need to process them for 5886 constraints. */ 5887 if (remove_p) 5888 { 5889 if (lra_dump_file != NULL) 5890 { 5891 fprintf (lra_dump_file, " Removing dead insn:\n "); 5892 dump_insn_slim (lra_dump_file, curr_insn); 5893 } 5894 lra_set_insn_deleted (curr_insn); 5895 } 5896 } 5897 } 5898 5899 /* The structure describes info to do an inheritance for the current 5900 insn. We need to collect such info first before doing the 5901 transformations because the transformations change the insn 5902 internal representation. */ 5903 struct to_inherit 5904 { 5905 /* Original regno. */ 5906 int regno; 5907 /* Subsequent insns which can inherit original reg value. */ 5908 rtx insns; 5909 }; 5910 5911 /* Array containing all info for doing inheritance from the current 5912 insn. */ 5913 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; 5914 5915 /* Number elements in the previous array. */ 5916 static int to_inherit_num; 5917 5918 /* Add inheritance info REGNO and INSNS. Their meaning is described in 5919 structure to_inherit. */ 5920 static void 5921 add_to_inherit (int regno, rtx insns) 5922 { 5923 int i; 5924 5925 for (i = 0; i < to_inherit_num; i++) 5926 if (to_inherit[i].regno == regno) 5927 return; 5928 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); 5929 to_inherit[to_inherit_num].regno = regno; 5930 to_inherit[to_inherit_num++].insns = insns; 5931 } 5932 5933 /* Return the last non-debug insn in basic block BB, or the block begin 5934 note if none. */ 5935 static rtx_insn * 5936 get_last_insertion_point (basic_block bb) 5937 { 5938 rtx_insn *insn; 5939 5940 FOR_BB_INSNS_REVERSE (bb, insn) 5941 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) 5942 return insn; 5943 gcc_unreachable (); 5944 } 5945 5946 /* Set up RES by registers living on edges FROM except the edge (FROM, 5947 TO) or by registers set up in a jump insn in BB FROM. */ 5948 static void 5949 get_live_on_other_edges (basic_block from, basic_block to, bitmap res) 5950 { 5951 rtx_insn *last; 5952 struct lra_insn_reg *reg; 5953 edge e; 5954 edge_iterator ei; 5955 5956 lra_assert (to != NULL); 5957 bitmap_clear (res); 5958 FOR_EACH_EDGE (e, ei, from->succs) 5959 if (e->dest != to) 5960 bitmap_ior_into (res, df_get_live_in (e->dest)); 5961 last = get_last_insertion_point (from); 5962 if (! JUMP_P (last)) 5963 return; 5964 curr_id = lra_get_insn_recog_data (last); 5965 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 5966 if (reg->type != OP_IN) 5967 bitmap_set_bit (res, reg->regno); 5968 } 5969 5970 /* Used as a temporary results of some bitmap calculations. */ 5971 static bitmap_head temp_bitmap; 5972 5973 /* We split for reloads of small class of hard regs. The following 5974 defines how many hard regs the class should have to be qualified as 5975 small. The code is mostly oriented to x86/x86-64 architecture 5976 where some insns need to use only specific register or pair of 5977 registers and these register can live in RTL explicitly, e.g. for 5978 parameter passing. */ 5979 static const int max_small_class_regs_num = 2; 5980 5981 /* Do inheritance/split transformations in EBB starting with HEAD and 5982 finishing on TAIL. We process EBB insns in the reverse order. 5983 Return true if we did any inheritance/split transformation in the 5984 EBB. 5985 5986 We should avoid excessive splitting which results in worse code 5987 because of inaccurate cost calculations for spilling new split 5988 pseudos in such case. To achieve this we do splitting only if 5989 register pressure is high in given basic block and there are reload 5990 pseudos requiring hard registers. We could do more register 5991 pressure calculations at any given program point to avoid necessary 5992 splitting even more but it is to expensive and the current approach 5993 works well enough. */ 5994 static bool 5995 inherit_in_ebb (rtx_insn *head, rtx_insn *tail) 5996 { 5997 int i, src_regno, dst_regno, nregs; 5998 bool change_p, succ_p, update_reloads_num_p; 5999 rtx_insn *prev_insn, *last_insn; 6000 rtx next_usage_insns, curr_set; 6001 enum reg_class cl; 6002 struct lra_insn_reg *reg; 6003 basic_block last_processed_bb, curr_bb = NULL; 6004 HARD_REG_SET potential_reload_hard_regs, live_hard_regs; 6005 bitmap to_process; 6006 unsigned int j; 6007 bitmap_iterator bi; 6008 bool head_p, after_p; 6009 6010 change_p = false; 6011 curr_usage_insns_check++; 6012 clear_invariants (); 6013 reloads_num = calls_num = 0; 6014 bitmap_clear (&check_only_regs); 6015 bitmap_clear (&invalid_invariant_regs); 6016 last_processed_bb = NULL; 6017 CLEAR_HARD_REG_SET (potential_reload_hard_regs); 6018 COPY_HARD_REG_SET (live_hard_regs, eliminable_regset); 6019 IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); 6020 /* We don't process new insns generated in the loop. */ 6021 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) 6022 { 6023 prev_insn = PREV_INSN (curr_insn); 6024 if (BLOCK_FOR_INSN (curr_insn) != NULL) 6025 curr_bb = BLOCK_FOR_INSN (curr_insn); 6026 if (last_processed_bb != curr_bb) 6027 { 6028 /* We are at the end of BB. Add qualified living 6029 pseudos for potential splitting. */ 6030 to_process = df_get_live_out (curr_bb); 6031 if (last_processed_bb != NULL) 6032 { 6033 /* We are somewhere in the middle of EBB. */ 6034 get_live_on_other_edges (curr_bb, last_processed_bb, 6035 &temp_bitmap); 6036 to_process = &temp_bitmap; 6037 } 6038 last_processed_bb = curr_bb; 6039 last_insn = get_last_insertion_point (curr_bb); 6040 after_p = (! JUMP_P (last_insn) 6041 && (! CALL_P (last_insn) 6042 || (find_reg_note (last_insn, 6043 REG_NORETURN, NULL_RTX) == NULL_RTX 6044 && ! SIBLING_CALL_P (last_insn)))); 6045 CLEAR_HARD_REG_SET (potential_reload_hard_regs); 6046 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) 6047 { 6048 if ((int) j >= lra_constraint_new_regno_start) 6049 break; 6050 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) 6051 { 6052 if (j < FIRST_PSEUDO_REGISTER) 6053 SET_HARD_REG_BIT (live_hard_regs, j); 6054 else 6055 add_to_hard_reg_set (&live_hard_regs, 6056 PSEUDO_REGNO_MODE (j), 6057 reg_renumber[j]); 6058 setup_next_usage_insn (j, last_insn, reloads_num, after_p); 6059 } 6060 } 6061 } 6062 src_regno = dst_regno = -1; 6063 curr_set = single_set (curr_insn); 6064 if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set))) 6065 dst_regno = REGNO (SET_DEST (curr_set)); 6066 if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set))) 6067 src_regno = REGNO (SET_SRC (curr_set)); 6068 update_reloads_num_p = true; 6069 if (src_regno < lra_constraint_new_regno_start 6070 && src_regno >= FIRST_PSEUDO_REGISTER 6071 && reg_renumber[src_regno] < 0 6072 && dst_regno >= lra_constraint_new_regno_start 6073 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) 6074 { 6075 /* 'reload_pseudo <- original_pseudo'. */ 6076 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) 6077 reloads_num++; 6078 update_reloads_num_p = false; 6079 succ_p = false; 6080 if (usage_insns[src_regno].check == curr_usage_insns_check 6081 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) 6082 succ_p = inherit_reload_reg (false, src_regno, cl, 6083 curr_insn, next_usage_insns); 6084 if (succ_p) 6085 change_p = true; 6086 else 6087 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); 6088 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 6089 IOR_HARD_REG_SET (potential_reload_hard_regs, 6090 reg_class_contents[cl]); 6091 } 6092 else if (src_regno < 0 6093 && dst_regno >= lra_constraint_new_regno_start 6094 && invariant_p (SET_SRC (curr_set)) 6095 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS 6096 && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno) 6097 && ! bitmap_bit_p (&invalid_invariant_regs, 6098 ORIGINAL_REGNO(regno_reg_rtx[dst_regno]))) 6099 { 6100 /* 'reload_pseudo <- invariant'. */ 6101 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) 6102 reloads_num++; 6103 update_reloads_num_p = false; 6104 if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) 6105 change_p = true; 6106 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 6107 IOR_HARD_REG_SET (potential_reload_hard_regs, 6108 reg_class_contents[cl]); 6109 } 6110 else if (src_regno >= lra_constraint_new_regno_start 6111 && dst_regno < lra_constraint_new_regno_start 6112 && dst_regno >= FIRST_PSEUDO_REGISTER 6113 && reg_renumber[dst_regno] < 0 6114 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS 6115 && usage_insns[dst_regno].check == curr_usage_insns_check 6116 && (next_usage_insns 6117 = usage_insns[dst_regno].insns) != NULL_RTX) 6118 { 6119 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) 6120 reloads_num++; 6121 update_reloads_num_p = false; 6122 /* 'original_pseudo <- reload_pseudo'. */ 6123 if (! JUMP_P (curr_insn) 6124 && inherit_reload_reg (true, dst_regno, cl, 6125 curr_insn, next_usage_insns)) 6126 change_p = true; 6127 /* Invalidate. */ 6128 usage_insns[dst_regno].check = 0; 6129 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 6130 IOR_HARD_REG_SET (potential_reload_hard_regs, 6131 reg_class_contents[cl]); 6132 } 6133 else if (INSN_P (curr_insn)) 6134 { 6135 int iter; 6136 int max_uid = get_max_uid (); 6137 6138 curr_id = lra_get_insn_recog_data (curr_insn); 6139 curr_static_id = curr_id->insn_static_data; 6140 to_inherit_num = 0; 6141 /* Process insn definitions. */ 6142 for (iter = 0; iter < 2; iter++) 6143 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; 6144 reg != NULL; 6145 reg = reg->next) 6146 if (reg->type != OP_IN 6147 && (dst_regno = reg->regno) < lra_constraint_new_regno_start) 6148 { 6149 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT 6150 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p 6151 && usage_insns[dst_regno].check == curr_usage_insns_check 6152 && (next_usage_insns 6153 = usage_insns[dst_regno].insns) != NULL_RTX) 6154 { 6155 struct lra_insn_reg *r; 6156 6157 for (r = curr_id->regs; r != NULL; r = r->next) 6158 if (r->type != OP_OUT && r->regno == dst_regno) 6159 break; 6160 /* Don't do inheritance if the pseudo is also 6161 used in the insn. */ 6162 if (r == NULL) 6163 /* We can not do inheritance right now 6164 because the current insn reg info (chain 6165 regs) can change after that. */ 6166 add_to_inherit (dst_regno, next_usage_insns); 6167 } 6168 /* We can not process one reg twice here because of 6169 usage_insns invalidation. */ 6170 if ((dst_regno < FIRST_PSEUDO_REGISTER 6171 || reg_renumber[dst_regno] >= 0) 6172 && ! reg->subreg_p && reg->type != OP_IN) 6173 { 6174 HARD_REG_SET s; 6175 6176 if (split_if_necessary (dst_regno, reg->biggest_mode, 6177 potential_reload_hard_regs, 6178 false, curr_insn, max_uid)) 6179 change_p = true; 6180 CLEAR_HARD_REG_SET (s); 6181 if (dst_regno < FIRST_PSEUDO_REGISTER) 6182 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); 6183 else 6184 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), 6185 reg_renumber[dst_regno]); 6186 AND_COMPL_HARD_REG_SET (live_hard_regs, s); 6187 } 6188 /* We should invalidate potential inheritance or 6189 splitting for the current insn usages to the next 6190 usage insns (see code below) as the output pseudo 6191 prevents this. */ 6192 if ((dst_regno >= FIRST_PSEUDO_REGISTER 6193 && reg_renumber[dst_regno] < 0) 6194 || (reg->type == OP_OUT && ! reg->subreg_p 6195 && (dst_regno < FIRST_PSEUDO_REGISTER 6196 || reg_renumber[dst_regno] >= 0))) 6197 { 6198 /* Invalidate and mark definitions. */ 6199 if (dst_regno >= FIRST_PSEUDO_REGISTER) 6200 usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); 6201 else 6202 { 6203 nregs = hard_regno_nregs[dst_regno][reg->biggest_mode]; 6204 for (i = 0; i < nregs; i++) 6205 usage_insns[dst_regno + i].check 6206 = -(int) INSN_UID (curr_insn); 6207 } 6208 } 6209 } 6210 /* Process clobbered call regs. */ 6211 if (curr_id->arg_hard_regs != NULL) 6212 for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) 6213 if (dst_regno >= FIRST_PSEUDO_REGISTER) 6214 usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check 6215 = -(int) INSN_UID (curr_insn); 6216 if (! JUMP_P (curr_insn)) 6217 for (i = 0; i < to_inherit_num; i++) 6218 if (inherit_reload_reg (true, to_inherit[i].regno, 6219 ALL_REGS, curr_insn, 6220 to_inherit[i].insns)) 6221 change_p = true; 6222 if (CALL_P (curr_insn)) 6223 { 6224 rtx cheap, pat, dest; 6225 rtx_insn *restore; 6226 int regno, hard_regno; 6227 6228 calls_num++; 6229 if ((cheap = find_reg_note (curr_insn, 6230 REG_RETURNED, NULL_RTX)) != NULL_RTX 6231 && ((cheap = XEXP (cheap, 0)), true) 6232 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER 6233 && (hard_regno = reg_renumber[regno]) >= 0 6234 /* If there are pending saves/restores, the 6235 optimization is not worth. */ 6236 && usage_insns[regno].calls_num == calls_num - 1 6237 && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) 6238 { 6239 /* Restore the pseudo from the call result as 6240 REG_RETURNED note says that the pseudo value is 6241 in the call result and the pseudo is an argument 6242 of the call. */ 6243 pat = PATTERN (curr_insn); 6244 if (GET_CODE (pat) == PARALLEL) 6245 pat = XVECEXP (pat, 0, 0); 6246 dest = SET_DEST (pat); 6247 /* For multiple return values dest is PARALLEL. 6248 Currently we handle only single return value case. */ 6249 if (REG_P (dest)) 6250 { 6251 start_sequence (); 6252 emit_move_insn (cheap, copy_rtx (dest)); 6253 restore = get_insns (); 6254 end_sequence (); 6255 lra_process_new_insns (curr_insn, NULL, restore, 6256 "Inserting call parameter restore"); 6257 /* We don't need to save/restore of the pseudo from 6258 this call. */ 6259 usage_insns[regno].calls_num = calls_num; 6260 bitmap_set_bit (&check_only_regs, regno); 6261 } 6262 } 6263 } 6264 to_inherit_num = 0; 6265 /* Process insn usages. */ 6266 for (iter = 0; iter < 2; iter++) 6267 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; 6268 reg != NULL; 6269 reg = reg->next) 6270 if ((reg->type != OP_OUT 6271 || (reg->type == OP_OUT && reg->subreg_p)) 6272 && (src_regno = reg->regno) < lra_constraint_new_regno_start) 6273 { 6274 if (src_regno >= FIRST_PSEUDO_REGISTER 6275 && reg_renumber[src_regno] < 0 && reg->type == OP_IN) 6276 { 6277 if (usage_insns[src_regno].check == curr_usage_insns_check 6278 && (next_usage_insns 6279 = usage_insns[src_regno].insns) != NULL_RTX 6280 && NONDEBUG_INSN_P (curr_insn)) 6281 add_to_inherit (src_regno, next_usage_insns); 6282 else if (usage_insns[src_regno].check 6283 != -(int) INSN_UID (curr_insn)) 6284 /* Add usages but only if the reg is not set up 6285 in the same insn. */ 6286 add_next_usage_insn (src_regno, curr_insn, reloads_num); 6287 } 6288 else if (src_regno < FIRST_PSEUDO_REGISTER 6289 || reg_renumber[src_regno] >= 0) 6290 { 6291 bool before_p; 6292 rtx_insn *use_insn = curr_insn; 6293 6294 before_p = (JUMP_P (curr_insn) 6295 || (CALL_P (curr_insn) && reg->type == OP_IN)); 6296 if (NONDEBUG_INSN_P (curr_insn) 6297 && (! JUMP_P (curr_insn) || reg->type == OP_IN) 6298 && split_if_necessary (src_regno, reg->biggest_mode, 6299 potential_reload_hard_regs, 6300 before_p, curr_insn, max_uid)) 6301 { 6302 if (reg->subreg_p) 6303 lra_risky_transformations_p = true; 6304 change_p = true; 6305 /* Invalidate. */ 6306 usage_insns[src_regno].check = 0; 6307 if (before_p) 6308 use_insn = PREV_INSN (curr_insn); 6309 } 6310 if (NONDEBUG_INSN_P (curr_insn)) 6311 { 6312 if (src_regno < FIRST_PSEUDO_REGISTER) 6313 add_to_hard_reg_set (&live_hard_regs, 6314 reg->biggest_mode, src_regno); 6315 else 6316 add_to_hard_reg_set (&live_hard_regs, 6317 PSEUDO_REGNO_MODE (src_regno), 6318 reg_renumber[src_regno]); 6319 } 6320 add_next_usage_insn (src_regno, use_insn, reloads_num); 6321 } 6322 } 6323 /* Process used call regs. */ 6324 if (curr_id->arg_hard_regs != NULL) 6325 for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) 6326 if (src_regno < FIRST_PSEUDO_REGISTER) 6327 { 6328 SET_HARD_REG_BIT (live_hard_regs, src_regno); 6329 add_next_usage_insn (src_regno, curr_insn, reloads_num); 6330 } 6331 for (i = 0; i < to_inherit_num; i++) 6332 { 6333 src_regno = to_inherit[i].regno; 6334 if (inherit_reload_reg (false, src_regno, ALL_REGS, 6335 curr_insn, to_inherit[i].insns)) 6336 change_p = true; 6337 else 6338 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); 6339 } 6340 } 6341 if (update_reloads_num_p 6342 && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX) 6343 { 6344 int regno = -1; 6345 if ((REG_P (SET_DEST (curr_set)) 6346 && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start 6347 && reg_renumber[regno] < 0 6348 && (cl = lra_get_allocno_class (regno)) != NO_REGS) 6349 || (REG_P (SET_SRC (curr_set)) 6350 && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start 6351 && reg_renumber[regno] < 0 6352 && (cl = lra_get_allocno_class (regno)) != NO_REGS)) 6353 { 6354 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) 6355 reloads_num++; 6356 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 6357 IOR_HARD_REG_SET (potential_reload_hard_regs, 6358 reg_class_contents[cl]); 6359 } 6360 } 6361 if (NONDEBUG_INSN_P (curr_insn)) 6362 { 6363 int regno; 6364 6365 /* Invalidate invariants with changed regs. */ 6366 curr_id = lra_get_insn_recog_data (curr_insn); 6367 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 6368 if (reg->type != OP_IN) 6369 { 6370 bitmap_set_bit (&invalid_invariant_regs, reg->regno); 6371 bitmap_set_bit (&invalid_invariant_regs, 6372 ORIGINAL_REGNO (regno_reg_rtx[reg->regno])); 6373 } 6374 curr_static_id = curr_id->insn_static_data; 6375 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) 6376 if (reg->type != OP_IN) 6377 bitmap_set_bit (&invalid_invariant_regs, reg->regno); 6378 if (curr_id->arg_hard_regs != NULL) 6379 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) 6380 if (regno >= FIRST_PSEUDO_REGISTER) 6381 bitmap_set_bit (&invalid_invariant_regs, 6382 regno - FIRST_PSEUDO_REGISTER); 6383 } 6384 /* We reached the start of the current basic block. */ 6385 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) 6386 || BLOCK_FOR_INSN (prev_insn) != curr_bb) 6387 { 6388 /* We reached the beginning of the current block -- do 6389 rest of spliting in the current BB. */ 6390 to_process = df_get_live_in (curr_bb); 6391 if (BLOCK_FOR_INSN (head) != curr_bb) 6392 { 6393 /* We are somewhere in the middle of EBB. */ 6394 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, 6395 curr_bb, &temp_bitmap); 6396 to_process = &temp_bitmap; 6397 } 6398 head_p = true; 6399 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) 6400 { 6401 if ((int) j >= lra_constraint_new_regno_start) 6402 break; 6403 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) 6404 && usage_insns[j].check == curr_usage_insns_check 6405 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) 6406 { 6407 if (need_for_split_p (potential_reload_hard_regs, j)) 6408 { 6409 if (lra_dump_file != NULL && head_p) 6410 { 6411 fprintf (lra_dump_file, 6412 " ----------------------------------\n"); 6413 head_p = false; 6414 } 6415 if (split_reg (false, j, bb_note (curr_bb), 6416 next_usage_insns)) 6417 change_p = true; 6418 } 6419 usage_insns[j].check = 0; 6420 } 6421 } 6422 } 6423 } 6424 return change_p; 6425 } 6426 6427 /* This value affects EBB forming. If probability of edge from EBB to 6428 a BB is not greater than the following value, we don't add the BB 6429 to EBB. */ 6430 #define EBB_PROBABILITY_CUTOFF \ 6431 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100) 6432 6433 /* Current number of inheritance/split iteration. */ 6434 int lra_inheritance_iter; 6435 6436 /* Entry function for inheritance/split pass. */ 6437 void 6438 lra_inheritance (void) 6439 { 6440 int i; 6441 basic_block bb, start_bb; 6442 edge e; 6443 6444 lra_inheritance_iter++; 6445 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) 6446 return; 6447 timevar_push (TV_LRA_INHERITANCE); 6448 if (lra_dump_file != NULL) 6449 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", 6450 lra_inheritance_iter); 6451 curr_usage_insns_check = 0; 6452 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); 6453 for (i = 0; i < lra_constraint_new_regno_start; i++) 6454 usage_insns[i].check = 0; 6455 bitmap_initialize (&check_only_regs, ®_obstack); 6456 bitmap_initialize (&invalid_invariant_regs, ®_obstack); 6457 bitmap_initialize (&live_regs, ®_obstack); 6458 bitmap_initialize (&temp_bitmap, ®_obstack); 6459 bitmap_initialize (&ebb_global_regs, ®_obstack); 6460 FOR_EACH_BB_FN (bb, cfun) 6461 { 6462 start_bb = bb; 6463 if (lra_dump_file != NULL) 6464 fprintf (lra_dump_file, "EBB"); 6465 /* Form a EBB starting with BB. */ 6466 bitmap_clear (&ebb_global_regs); 6467 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); 6468 for (;;) 6469 { 6470 if (lra_dump_file != NULL) 6471 fprintf (lra_dump_file, " %d", bb->index); 6472 if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 6473 || LABEL_P (BB_HEAD (bb->next_bb))) 6474 break; 6475 e = find_fallthru_edge (bb->succs); 6476 if (! e) 6477 break; 6478 if (e->probability < EBB_PROBABILITY_CUTOFF) 6479 break; 6480 bb = bb->next_bb; 6481 } 6482 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); 6483 if (lra_dump_file != NULL) 6484 fprintf (lra_dump_file, "\n"); 6485 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) 6486 /* Remember that the EBB head and tail can change in 6487 inherit_in_ebb. */ 6488 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); 6489 } 6490 bitmap_clear (&ebb_global_regs); 6491 bitmap_clear (&temp_bitmap); 6492 bitmap_clear (&live_regs); 6493 bitmap_clear (&invalid_invariant_regs); 6494 bitmap_clear (&check_only_regs); 6495 free (usage_insns); 6496 6497 timevar_pop (TV_LRA_INHERITANCE); 6498 } 6499 6500 6501 6502 /* This page contains code to undo failed inheritance/split 6503 transformations. */ 6504 6505 /* Current number of iteration undoing inheritance/split. */ 6506 int lra_undo_inheritance_iter; 6507 6508 /* Fix BB live info LIVE after removing pseudos created on pass doing 6509 inheritance/split which are REMOVED_PSEUDOS. */ 6510 static void 6511 fix_bb_live_info (bitmap live, bitmap removed_pseudos) 6512 { 6513 unsigned int regno; 6514 bitmap_iterator bi; 6515 6516 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) 6517 if (bitmap_clear_bit (live, regno) 6518 && REG_P (lra_reg_info[regno].restore_rtx)) 6519 bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx)); 6520 } 6521 6522 /* Return regno of the (subreg of) REG. Otherwise, return a negative 6523 number. */ 6524 static int 6525 get_regno (rtx reg) 6526 { 6527 if (GET_CODE (reg) == SUBREG) 6528 reg = SUBREG_REG (reg); 6529 if (REG_P (reg)) 6530 return REGNO (reg); 6531 return -1; 6532 } 6533 6534 /* Delete a move INSN with destination reg DREGNO and a previous 6535 clobber insn with the same regno. The inheritance/split code can 6536 generate moves with preceding clobber and when we delete such moves 6537 we should delete the clobber insn too to keep the correct life 6538 info. */ 6539 static void 6540 delete_move_and_clobber (rtx_insn *insn, int dregno) 6541 { 6542 rtx_insn *prev_insn = PREV_INSN (insn); 6543 6544 lra_set_insn_deleted (insn); 6545 lra_assert (dregno >= 0); 6546 if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn) 6547 && GET_CODE (PATTERN (prev_insn)) == CLOBBER 6548 && dregno == get_regno (XEXP (PATTERN (prev_insn), 0))) 6549 lra_set_insn_deleted (prev_insn); 6550 } 6551 6552 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and 6553 return true if we did any change. The undo transformations for 6554 inheritance looks like 6555 i <- i2 6556 p <- i => p <- i2 6557 or removing 6558 p <- i, i <- p, and i <- i3 6559 where p is original pseudo from which inheritance pseudo i was 6560 created, i and i3 are removed inheritance pseudos, i2 is another 6561 not removed inheritance pseudo. All split pseudos or other 6562 occurrences of removed inheritance pseudos are changed on the 6563 corresponding original pseudos. 6564 6565 The function also schedules insns changed and created during 6566 inheritance/split pass for processing by the subsequent constraint 6567 pass. */ 6568 static bool 6569 remove_inheritance_pseudos (bitmap remove_pseudos) 6570 { 6571 basic_block bb; 6572 int regno, sregno, prev_sregno, dregno; 6573 rtx restore_rtx; 6574 rtx set, prev_set; 6575 rtx_insn *prev_insn; 6576 bool change_p, done_p; 6577 6578 change_p = ! bitmap_empty_p (remove_pseudos); 6579 /* We can not finish the function right away if CHANGE_P is true 6580 because we need to marks insns affected by previous 6581 inheritance/split pass for processing by the subsequent 6582 constraint pass. */ 6583 FOR_EACH_BB_FN (bb, cfun) 6584 { 6585 fix_bb_live_info (df_get_live_in (bb), remove_pseudos); 6586 fix_bb_live_info (df_get_live_out (bb), remove_pseudos); 6587 FOR_BB_INSNS_REVERSE (bb, curr_insn) 6588 { 6589 if (! INSN_P (curr_insn)) 6590 continue; 6591 done_p = false; 6592 sregno = dregno = -1; 6593 if (change_p && NONDEBUG_INSN_P (curr_insn) 6594 && (set = single_set (curr_insn)) != NULL_RTX) 6595 { 6596 dregno = get_regno (SET_DEST (set)); 6597 sregno = get_regno (SET_SRC (set)); 6598 } 6599 6600 if (sregno >= 0 && dregno >= 0) 6601 { 6602 if (bitmap_bit_p (remove_pseudos, dregno) 6603 && ! REG_P (lra_reg_info[dregno].restore_rtx)) 6604 { 6605 /* invariant inheritance pseudo <- original pseudo */ 6606 if (lra_dump_file != NULL) 6607 { 6608 fprintf (lra_dump_file, " Removing invariant inheritance:\n"); 6609 dump_insn_slim (lra_dump_file, curr_insn); 6610 fprintf (lra_dump_file, "\n"); 6611 } 6612 delete_move_and_clobber (curr_insn, dregno); 6613 done_p = true; 6614 } 6615 else if (bitmap_bit_p (remove_pseudos, sregno) 6616 && ! REG_P (lra_reg_info[sregno].restore_rtx)) 6617 { 6618 /* reload pseudo <- invariant inheritance pseudo */ 6619 start_sequence (); 6620 /* We can not just change the source. It might be 6621 an insn different from the move. */ 6622 emit_insn (lra_reg_info[sregno].restore_rtx); 6623 rtx_insn *new_insns = get_insns (); 6624 end_sequence (); 6625 lra_assert (single_set (new_insns) != NULL 6626 && SET_DEST (set) == SET_DEST (single_set (new_insns))); 6627 lra_process_new_insns (curr_insn, NULL, new_insns, 6628 "Changing reload<-invariant inheritance"); 6629 delete_move_and_clobber (curr_insn, dregno); 6630 done_p = true; 6631 } 6632 else if ((bitmap_bit_p (remove_pseudos, sregno) 6633 && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno 6634 || (bitmap_bit_p (remove_pseudos, dregno) 6635 && get_regno (lra_reg_info[sregno].restore_rtx) >= 0 6636 && (get_regno (lra_reg_info[sregno].restore_rtx) 6637 == get_regno (lra_reg_info[dregno].restore_rtx))))) 6638 || (bitmap_bit_p (remove_pseudos, dregno) 6639 && get_regno (lra_reg_info[dregno].restore_rtx) == sregno)) 6640 /* One of the following cases: 6641 original <- removed inheritance pseudo 6642 removed inherit pseudo <- another removed inherit pseudo 6643 removed inherit pseudo <- original pseudo 6644 Or 6645 removed_split_pseudo <- original_reg 6646 original_reg <- removed_split_pseudo */ 6647 { 6648 if (lra_dump_file != NULL) 6649 { 6650 fprintf (lra_dump_file, " Removing %s:\n", 6651 bitmap_bit_p (&lra_split_regs, sregno) 6652 || bitmap_bit_p (&lra_split_regs, dregno) 6653 ? "split" : "inheritance"); 6654 dump_insn_slim (lra_dump_file, curr_insn); 6655 } 6656 delete_move_and_clobber (curr_insn, dregno); 6657 done_p = true; 6658 } 6659 else if (bitmap_bit_p (remove_pseudos, sregno) 6660 && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) 6661 { 6662 /* Search the following pattern: 6663 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 6664 original_pseudo <- inherit_or_split_pseudo1 6665 where the 2nd insn is the current insn and 6666 inherit_or_split_pseudo2 is not removed. If it is found, 6667 change the current insn onto: 6668 original_pseudo <- inherit_or_split_pseudo2. */ 6669 for (prev_insn = PREV_INSN (curr_insn); 6670 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); 6671 prev_insn = PREV_INSN (prev_insn)) 6672 ; 6673 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb 6674 && (prev_set = single_set (prev_insn)) != NULL_RTX 6675 /* There should be no subregs in insn we are 6676 searching because only the original reg might 6677 be in subreg when we changed the mode of 6678 load/store for splitting. */ 6679 && REG_P (SET_DEST (prev_set)) 6680 && REG_P (SET_SRC (prev_set)) 6681 && (int) REGNO (SET_DEST (prev_set)) == sregno 6682 && ((prev_sregno = REGNO (SET_SRC (prev_set))) 6683 >= FIRST_PSEUDO_REGISTER) 6684 && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX 6685 || 6686 /* As we consider chain of inheritance or 6687 splitting described in above comment we should 6688 check that sregno and prev_sregno were 6689 inheritance/split pseudos created from the 6690 same original regno. */ 6691 (get_regno (lra_reg_info[sregno].restore_rtx) >= 0 6692 && (get_regno (lra_reg_info[sregno].restore_rtx) 6693 == get_regno (lra_reg_info[prev_sregno].restore_rtx)))) 6694 && ! bitmap_bit_p (remove_pseudos, prev_sregno)) 6695 { 6696 lra_assert (GET_MODE (SET_SRC (prev_set)) 6697 == GET_MODE (regno_reg_rtx[sregno])); 6698 if (GET_CODE (SET_SRC (set)) == SUBREG) 6699 SUBREG_REG (SET_SRC (set)) = SET_SRC (prev_set); 6700 else 6701 SET_SRC (set) = SET_SRC (prev_set); 6702 /* As we are finishing with processing the insn 6703 here, check the destination too as it might 6704 inheritance pseudo for another pseudo. */ 6705 if (bitmap_bit_p (remove_pseudos, dregno) 6706 && bitmap_bit_p (&lra_inheritance_pseudos, dregno) 6707 && (restore_rtx 6708 = lra_reg_info[dregno].restore_rtx) != NULL_RTX) 6709 { 6710 if (GET_CODE (SET_DEST (set)) == SUBREG) 6711 SUBREG_REG (SET_DEST (set)) = restore_rtx; 6712 else 6713 SET_DEST (set) = restore_rtx; 6714 } 6715 lra_push_insn_and_update_insn_regno_info (curr_insn); 6716 lra_set_used_insn_alternative_by_uid 6717 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); 6718 done_p = true; 6719 if (lra_dump_file != NULL) 6720 { 6721 fprintf (lra_dump_file, " Change reload insn:\n"); 6722 dump_insn_slim (lra_dump_file, curr_insn); 6723 } 6724 } 6725 } 6726 } 6727 if (! done_p) 6728 { 6729 struct lra_insn_reg *reg; 6730 bool restored_regs_p = false; 6731 bool kept_regs_p = false; 6732 6733 curr_id = lra_get_insn_recog_data (curr_insn); 6734 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 6735 { 6736 regno = reg->regno; 6737 restore_rtx = lra_reg_info[regno].restore_rtx; 6738 if (restore_rtx != NULL_RTX) 6739 { 6740 if (change_p && bitmap_bit_p (remove_pseudos, regno)) 6741 { 6742 lra_substitute_pseudo_within_insn 6743 (curr_insn, regno, restore_rtx, false); 6744 restored_regs_p = true; 6745 } 6746 else 6747 kept_regs_p = true; 6748 } 6749 } 6750 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) 6751 { 6752 /* The instruction has changed since the previous 6753 constraints pass. */ 6754 lra_push_insn_and_update_insn_regno_info (curr_insn); 6755 lra_set_used_insn_alternative_by_uid 6756 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); 6757 } 6758 else if (restored_regs_p) 6759 /* The instruction has been restored to the form that 6760 it had during the previous constraints pass. */ 6761 lra_update_insn_regno_info (curr_insn); 6762 if (restored_regs_p && lra_dump_file != NULL) 6763 { 6764 fprintf (lra_dump_file, " Insn after restoring regs:\n"); 6765 dump_insn_slim (lra_dump_file, curr_insn); 6766 } 6767 } 6768 } 6769 } 6770 return change_p; 6771 } 6772 6773 /* If optional reload pseudos failed to get a hard register or was not 6774 inherited, it is better to remove optional reloads. We do this 6775 transformation after undoing inheritance to figure out necessity to 6776 remove optional reloads easier. Return true if we do any 6777 change. */ 6778 static bool 6779 undo_optional_reloads (void) 6780 { 6781 bool change_p, keep_p; 6782 unsigned int regno, uid; 6783 bitmap_iterator bi, bi2; 6784 rtx_insn *insn; 6785 rtx set, src, dest; 6786 bitmap_head removed_optional_reload_pseudos, insn_bitmap; 6787 6788 bitmap_initialize (&removed_optional_reload_pseudos, ®_obstack); 6789 bitmap_copy (&removed_optional_reload_pseudos, &lra_optional_reload_pseudos); 6790 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) 6791 { 6792 keep_p = false; 6793 /* Keep optional reloads from previous subpasses. */ 6794 if (lra_reg_info[regno].restore_rtx == NULL_RTX 6795 /* If the original pseudo changed its allocation, just 6796 removing the optional pseudo is dangerous as the original 6797 pseudo will have longer live range. */ 6798 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0) 6799 keep_p = true; 6800 else if (reg_renumber[regno] >= 0) 6801 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) 6802 { 6803 insn = lra_insn_recog_data[uid]->insn; 6804 if ((set = single_set (insn)) == NULL_RTX) 6805 continue; 6806 src = SET_SRC (set); 6807 dest = SET_DEST (set); 6808 if (! REG_P (src) || ! REG_P (dest)) 6809 continue; 6810 if (REGNO (dest) == regno 6811 /* Ignore insn for optional reloads itself. */ 6812 && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src) 6813 /* Check only inheritance on last inheritance pass. */ 6814 && (int) REGNO (src) >= new_regno_start 6815 /* Check that the optional reload was inherited. */ 6816 && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) 6817 { 6818 keep_p = true; 6819 break; 6820 } 6821 } 6822 if (keep_p) 6823 { 6824 bitmap_clear_bit (&removed_optional_reload_pseudos, regno); 6825 if (lra_dump_file != NULL) 6826 fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); 6827 } 6828 } 6829 change_p = ! bitmap_empty_p (&removed_optional_reload_pseudos); 6830 bitmap_initialize (&insn_bitmap, ®_obstack); 6831 EXECUTE_IF_SET_IN_BITMAP (&removed_optional_reload_pseudos, 0, regno, bi) 6832 { 6833 if (lra_dump_file != NULL) 6834 fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); 6835 bitmap_copy (&insn_bitmap, &lra_reg_info[regno].insn_bitmap); 6836 EXECUTE_IF_SET_IN_BITMAP (&insn_bitmap, 0, uid, bi2) 6837 { 6838 insn = lra_insn_recog_data[uid]->insn; 6839 if ((set = single_set (insn)) != NULL_RTX) 6840 { 6841 src = SET_SRC (set); 6842 dest = SET_DEST (set); 6843 if (REG_P (src) && REG_P (dest) 6844 && ((REGNO (src) == regno 6845 && (REGNO (lra_reg_info[regno].restore_rtx) 6846 == REGNO (dest))) 6847 || (REGNO (dest) == regno 6848 && (REGNO (lra_reg_info[regno].restore_rtx) 6849 == REGNO (src))))) 6850 { 6851 if (lra_dump_file != NULL) 6852 { 6853 fprintf (lra_dump_file, " Deleting move %u\n", 6854 INSN_UID (insn)); 6855 dump_insn_slim (lra_dump_file, insn); 6856 } 6857 delete_move_and_clobber (insn, REGNO (dest)); 6858 continue; 6859 } 6860 /* We should not worry about generation memory-memory 6861 moves here as if the corresponding inheritance did 6862 not work (inheritance pseudo did not get a hard reg), 6863 we remove the inheritance pseudo and the optional 6864 reload. */ 6865 } 6866 lra_substitute_pseudo_within_insn 6867 (insn, regno, lra_reg_info[regno].restore_rtx, false); 6868 lra_update_insn_regno_info (insn); 6869 if (lra_dump_file != NULL) 6870 { 6871 fprintf (lra_dump_file, 6872 " Restoring original insn:\n"); 6873 dump_insn_slim (lra_dump_file, insn); 6874 } 6875 } 6876 } 6877 /* Clear restore_regnos. */ 6878 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) 6879 lra_reg_info[regno].restore_rtx = NULL_RTX; 6880 bitmap_clear (&insn_bitmap); 6881 bitmap_clear (&removed_optional_reload_pseudos); 6882 return change_p; 6883 } 6884 6885 /* Entry function for undoing inheritance/split transformation. Return true 6886 if we did any RTL change in this pass. */ 6887 bool 6888 lra_undo_inheritance (void) 6889 { 6890 unsigned int regno; 6891 int hard_regno; 6892 int n_all_inherit, n_inherit, n_all_split, n_split; 6893 rtx restore_rtx; 6894 bitmap_head remove_pseudos; 6895 bitmap_iterator bi; 6896 bool change_p; 6897 6898 lra_undo_inheritance_iter++; 6899 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) 6900 return false; 6901 if (lra_dump_file != NULL) 6902 fprintf (lra_dump_file, 6903 "\n********** Undoing inheritance #%d: **********\n\n", 6904 lra_undo_inheritance_iter); 6905 bitmap_initialize (&remove_pseudos, ®_obstack); 6906 n_inherit = n_all_inherit = 0; 6907 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) 6908 if (lra_reg_info[regno].restore_rtx != NULL_RTX) 6909 { 6910 n_all_inherit++; 6911 if (reg_renumber[regno] < 0 6912 /* If the original pseudo changed its allocation, just 6913 removing inheritance is dangerous as for changing 6914 allocation we used shorter live-ranges. */ 6915 && (! REG_P (lra_reg_info[regno].restore_rtx) 6916 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0)) 6917 bitmap_set_bit (&remove_pseudos, regno); 6918 else 6919 n_inherit++; 6920 } 6921 if (lra_dump_file != NULL && n_all_inherit != 0) 6922 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", 6923 n_inherit, n_all_inherit, 6924 (double) n_inherit / n_all_inherit * 100); 6925 n_split = n_all_split = 0; 6926 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) 6927 if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX) 6928 { 6929 int restore_regno = REGNO (restore_rtx); 6930 6931 n_all_split++; 6932 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER 6933 ? reg_renumber[restore_regno] : restore_regno); 6934 if (hard_regno < 0 || reg_renumber[regno] == hard_regno) 6935 bitmap_set_bit (&remove_pseudos, regno); 6936 else 6937 { 6938 n_split++; 6939 if (lra_dump_file != NULL) 6940 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", 6941 regno, restore_regno); 6942 } 6943 } 6944 if (lra_dump_file != NULL && n_all_split != 0) 6945 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", 6946 n_split, n_all_split, 6947 (double) n_split / n_all_split * 100); 6948 change_p = remove_inheritance_pseudos (&remove_pseudos); 6949 bitmap_clear (&remove_pseudos); 6950 /* Clear restore_regnos. */ 6951 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) 6952 lra_reg_info[regno].restore_rtx = NULL_RTX; 6953 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) 6954 lra_reg_info[regno].restore_rtx = NULL_RTX; 6955 change_p = undo_optional_reloads () || change_p; 6956 return change_p; 6957 } 6958