1 /* Code for RTL transformations to satisfy insn constraints. 2 Copyright (C) 2010-2019 Free Software Foundation, Inc. 3 Contributed by Vladimir Makarov <vmakarov@redhat.com>. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it under 8 the terms of the GNU General Public License as published by the Free 9 Software Foundation; either version 3, or (at your option) any later 10 version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 /* This file contains code for 3 passes: constraint pass, 23 inheritance/split pass, and pass for undoing failed inheritance and 24 split. 25 26 The major goal of constraint pass is to transform RTL to satisfy 27 insn and address constraints by: 28 o choosing insn alternatives; 29 o generating *reload insns* (or reloads in brief) and *reload 30 pseudos* which will get necessary hard registers later; 31 o substituting pseudos with equivalent values and removing the 32 instructions that initialized those pseudos. 33 34 The constraint pass has biggest and most complicated code in LRA. 35 There are a lot of important details like: 36 o reuse of input reload pseudos to simplify reload pseudo 37 allocations; 38 o some heuristics to choose insn alternative to improve the 39 inheritance; 40 o early clobbers etc. 41 42 The pass is mimicking former reload pass in alternative choosing 43 because the reload pass is oriented to current machine description 44 model. It might be changed if the machine description model is 45 changed. 46 47 There is special code for preventing all LRA and this pass cycling 48 in case of bugs. 49 50 On the first iteration of the pass we process every instruction and 51 choose an alternative for each one. On subsequent iterations we try 52 to avoid reprocessing instructions if we can be sure that the old 53 choice is still valid. 54 55 The inheritance/spilt pass is to transform code to achieve 56 ineheritance and live range splitting. It is done on backward 57 traversal of EBBs. 58 59 The inheritance optimization goal is to reuse values in hard 60 registers. There is analogous optimization in old reload pass. The 61 inheritance is achieved by following transformation: 62 63 reload_p1 <- p reload_p1 <- p 64 ... new_p <- reload_p1 65 ... => ... 66 reload_p2 <- p reload_p2 <- new_p 67 68 where p is spilled and not changed between the insns. Reload_p1 is 69 also called *original pseudo* and new_p is called *inheritance 70 pseudo*. 71 72 The subsequent assignment pass will try to assign the same (or 73 another if it is not possible) hard register to new_p as to 74 reload_p1 or reload_p2. 75 76 If the assignment pass fails to assign a hard register to new_p, 77 this file will undo the inheritance and restore the original code. 78 This is because implementing the above sequence with a spilled 79 new_p would make the code much worse. The inheritance is done in 80 EBB scope. The above is just a simplified example to get an idea 81 of the inheritance as the inheritance is also done for non-reload 82 insns. 83 84 Splitting (transformation) is also done in EBB scope on the same 85 pass as the inheritance: 86 87 r <- ... or ... <- r r <- ... or ... <- r 88 ... s <- r (new insn -- save) 89 ... => 90 ... r <- s (new insn -- restore) 91 ... <- r ... <- r 92 93 The *split pseudo* s is assigned to the hard register of the 94 original pseudo or hard register r. 95 96 Splitting is done: 97 o In EBBs with high register pressure for global pseudos (living 98 in at least 2 BBs) and assigned to hard registers when there 99 are more one reloads needing the hard registers; 100 o for pseudos needing save/restore code around calls. 101 102 If the split pseudo still has the same hard register as the 103 original pseudo after the subsequent assignment pass or the 104 original pseudo was split, the opposite transformation is done on 105 the same pass for undoing inheritance. */ 106 107 #undef REG_OK_STRICT 108 109 #include "config.h" 110 #include "system.h" 111 #include "coretypes.h" 112 #include "backend.h" 113 #include "target.h" 114 #include "rtl.h" 115 #include "tree.h" 116 #include "predict.h" 117 #include "df.h" 118 #include "memmodel.h" 119 #include "tm_p.h" 120 #include "expmed.h" 121 #include "optabs.h" 122 #include "regs.h" 123 #include "ira.h" 124 #include "recog.h" 125 #include "output.h" 126 #include "addresses.h" 127 #include "expr.h" 128 #include "cfgrtl.h" 129 #include "rtl-error.h" 130 #include "params.h" 131 #include "lra.h" 132 #include "lra-int.h" 133 #include "print-rtl.h" 134 135 /* Value of LRA_CURR_RELOAD_NUM at the beginning of BB of the current 136 insn. Remember that LRA_CURR_RELOAD_NUM is the number of emitted 137 reload insns. */ 138 static int bb_reload_num; 139 140 /* The current insn being processed and corresponding its single set 141 (NULL otherwise), its data (basic block, the insn data, the insn 142 static data, and the mode of each operand). */ 143 static rtx_insn *curr_insn; 144 static rtx curr_insn_set; 145 static basic_block curr_bb; 146 static lra_insn_recog_data_t curr_id; 147 static struct lra_static_insn_data *curr_static_id; 148 static machine_mode curr_operand_mode[MAX_RECOG_OPERANDS]; 149 /* Mode of the register substituted by its equivalence with VOIDmode 150 (e.g. constant) and whose subreg is given operand of the current 151 insn. VOIDmode in all other cases. */ 152 static machine_mode original_subreg_reg_mode[MAX_RECOG_OPERANDS]; 153 154 155 156 /* Start numbers for new registers and insns at the current constraints 157 pass start. */ 158 static int new_regno_start; 159 static int new_insn_uid_start; 160 161 /* If LOC is nonnull, strip any outer subreg from it. */ 162 static inline rtx * 163 strip_subreg (rtx *loc) 164 { 165 return loc && GET_CODE (*loc) == SUBREG ? &SUBREG_REG (*loc) : loc; 166 } 167 168 /* Return hard regno of REGNO or if it is was not assigned to a hard 169 register, use a hard register from its allocno class. */ 170 static int 171 get_try_hard_regno (int regno) 172 { 173 int hard_regno; 174 enum reg_class rclass; 175 176 if ((hard_regno = regno) >= FIRST_PSEUDO_REGISTER) 177 hard_regno = lra_get_regno_hard_regno (regno); 178 if (hard_regno >= 0) 179 return hard_regno; 180 rclass = lra_get_allocno_class (regno); 181 if (rclass == NO_REGS) 182 return -1; 183 return ira_class_hard_regs[rclass][0]; 184 } 185 186 /* Return the hard regno of X after removing its subreg. If X is not 187 a register or a subreg of a register, return -1. If X is a pseudo, 188 use its assignment. If FINAL_P return the final hard regno which will 189 be after elimination. */ 190 static int 191 get_hard_regno (rtx x, bool final_p) 192 { 193 rtx reg; 194 int hard_regno; 195 196 reg = x; 197 if (SUBREG_P (x)) 198 reg = SUBREG_REG (x); 199 if (! REG_P (reg)) 200 return -1; 201 if (! HARD_REGISTER_NUM_P (hard_regno = REGNO (reg))) 202 hard_regno = lra_get_regno_hard_regno (hard_regno); 203 if (hard_regno < 0) 204 return -1; 205 if (final_p) 206 hard_regno = lra_get_elimination_hard_regno (hard_regno); 207 if (SUBREG_P (x)) 208 hard_regno += subreg_regno_offset (hard_regno, GET_MODE (reg), 209 SUBREG_BYTE (x), GET_MODE (x)); 210 return hard_regno; 211 } 212 213 /* If REGNO is a hard register or has been allocated a hard register, 214 return the class of that register. If REGNO is a reload pseudo 215 created by the current constraints pass, return its allocno class. 216 Return NO_REGS otherwise. */ 217 static enum reg_class 218 get_reg_class (int regno) 219 { 220 int hard_regno; 221 222 if (! HARD_REGISTER_NUM_P (hard_regno = regno)) 223 hard_regno = lra_get_regno_hard_regno (regno); 224 if (hard_regno >= 0) 225 { 226 hard_regno = lra_get_elimination_hard_regno (hard_regno); 227 return REGNO_REG_CLASS (hard_regno); 228 } 229 if (regno >= new_regno_start) 230 return lra_get_allocno_class (regno); 231 return NO_REGS; 232 } 233 234 /* Return true if REG satisfies (or will satisfy) reg class constraint 235 CL. Use elimination first if REG is a hard register. If REG is a 236 reload pseudo created by this constraints pass, assume that it will 237 be allocated a hard register from its allocno class, but allow that 238 class to be narrowed to CL if it is currently a superset of CL. 239 240 If NEW_CLASS is nonnull, set *NEW_CLASS to the new allocno class of 241 REGNO (reg), or NO_REGS if no change in its class was needed. */ 242 static bool 243 in_class_p (rtx reg, enum reg_class cl, enum reg_class *new_class) 244 { 245 enum reg_class rclass, common_class; 246 machine_mode reg_mode; 247 int class_size, hard_regno, nregs, i, j; 248 int regno = REGNO (reg); 249 250 if (new_class != NULL) 251 *new_class = NO_REGS; 252 if (regno < FIRST_PSEUDO_REGISTER) 253 { 254 rtx final_reg = reg; 255 rtx *final_loc = &final_reg; 256 257 lra_eliminate_reg_if_possible (final_loc); 258 return TEST_HARD_REG_BIT (reg_class_contents[cl], REGNO (*final_loc)); 259 } 260 reg_mode = GET_MODE (reg); 261 rclass = get_reg_class (regno); 262 if (regno < new_regno_start 263 /* Do not allow the constraints for reload instructions to 264 influence the classes of new pseudos. These reloads are 265 typically moves that have many alternatives, and restricting 266 reload pseudos for one alternative may lead to situations 267 where other reload pseudos are no longer allocatable. */ 268 || (INSN_UID (curr_insn) >= new_insn_uid_start 269 && curr_insn_set != NULL 270 && ((OBJECT_P (SET_SRC (curr_insn_set)) 271 && ! CONSTANT_P (SET_SRC (curr_insn_set))) 272 || (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG 273 && OBJECT_P (SUBREG_REG (SET_SRC (curr_insn_set))) 274 && ! CONSTANT_P (SUBREG_REG (SET_SRC (curr_insn_set))))))) 275 /* When we don't know what class will be used finally for reload 276 pseudos, we use ALL_REGS. */ 277 return ((regno >= new_regno_start && rclass == ALL_REGS) 278 || (rclass != NO_REGS && ira_class_subset_p[rclass][cl] 279 && ! hard_reg_set_subset_p (reg_class_contents[cl], 280 lra_no_alloc_regs))); 281 else 282 { 283 common_class = ira_reg_class_subset[rclass][cl]; 284 if (new_class != NULL) 285 *new_class = common_class; 286 if (hard_reg_set_subset_p (reg_class_contents[common_class], 287 lra_no_alloc_regs)) 288 return false; 289 /* Check that there are enough allocatable regs. */ 290 class_size = ira_class_hard_regs_num[common_class]; 291 for (i = 0; i < class_size; i++) 292 { 293 hard_regno = ira_class_hard_regs[common_class][i]; 294 nregs = hard_regno_nregs (hard_regno, reg_mode); 295 if (nregs == 1) 296 return true; 297 for (j = 0; j < nregs; j++) 298 if (TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno + j) 299 || ! TEST_HARD_REG_BIT (reg_class_contents[common_class], 300 hard_regno + j)) 301 break; 302 if (j >= nregs) 303 return true; 304 } 305 return false; 306 } 307 } 308 309 /* Return true if REGNO satisfies a memory constraint. */ 310 static bool 311 in_mem_p (int regno) 312 { 313 return get_reg_class (regno) == NO_REGS; 314 } 315 316 /* Return 1 if ADDR is a valid memory address for mode MODE in address 317 space AS, and check that each pseudo has the proper kind of hard 318 reg. */ 319 static int 320 valid_address_p (machine_mode mode ATTRIBUTE_UNUSED, 321 rtx addr, addr_space_t as) 322 { 323 #ifdef GO_IF_LEGITIMATE_ADDRESS 324 lra_assert (ADDR_SPACE_GENERIC_P (as)); 325 GO_IF_LEGITIMATE_ADDRESS (mode, addr, win); 326 return 0; 327 328 win: 329 return 1; 330 #else 331 return targetm.addr_space.legitimate_address_p (mode, addr, 0, as); 332 #endif 333 } 334 335 namespace { 336 /* Temporarily eliminates registers in an address (for the lifetime of 337 the object). */ 338 class address_eliminator { 339 public: 340 address_eliminator (struct address_info *ad); 341 ~address_eliminator (); 342 343 private: 344 struct address_info *m_ad; 345 rtx *m_base_loc; 346 rtx m_base_reg; 347 rtx *m_index_loc; 348 rtx m_index_reg; 349 }; 350 } 351 352 address_eliminator::address_eliminator (struct address_info *ad) 353 : m_ad (ad), 354 m_base_loc (strip_subreg (ad->base_term)), 355 m_base_reg (NULL_RTX), 356 m_index_loc (strip_subreg (ad->index_term)), 357 m_index_reg (NULL_RTX) 358 { 359 if (m_base_loc != NULL) 360 { 361 m_base_reg = *m_base_loc; 362 /* If we have non-legitimate address which is decomposed not in 363 the way we expected, don't do elimination here. In such case 364 the address will be reloaded and elimination will be done in 365 reload insn finally. */ 366 if (REG_P (m_base_reg)) 367 lra_eliminate_reg_if_possible (m_base_loc); 368 if (m_ad->base_term2 != NULL) 369 *m_ad->base_term2 = *m_ad->base_term; 370 } 371 if (m_index_loc != NULL) 372 { 373 m_index_reg = *m_index_loc; 374 if (REG_P (m_index_reg)) 375 lra_eliminate_reg_if_possible (m_index_loc); 376 } 377 } 378 379 address_eliminator::~address_eliminator () 380 { 381 if (m_base_loc && *m_base_loc != m_base_reg) 382 { 383 *m_base_loc = m_base_reg; 384 if (m_ad->base_term2 != NULL) 385 *m_ad->base_term2 = *m_ad->base_term; 386 } 387 if (m_index_loc && *m_index_loc != m_index_reg) 388 *m_index_loc = m_index_reg; 389 } 390 391 /* Return true if the eliminated form of AD is a legitimate target address. */ 392 static bool 393 valid_address_p (struct address_info *ad) 394 { 395 address_eliminator eliminator (ad); 396 return valid_address_p (ad->mode, *ad->outer, ad->as); 397 } 398 399 /* Return true if the eliminated form of memory reference OP satisfies 400 extra (special) memory constraint CONSTRAINT. */ 401 static bool 402 satisfies_memory_constraint_p (rtx op, enum constraint_num constraint) 403 { 404 struct address_info ad; 405 406 decompose_mem_address (&ad, op); 407 address_eliminator eliminator (&ad); 408 return constraint_satisfied_p (op, constraint); 409 } 410 411 /* Return true if the eliminated form of address AD satisfies extra 412 address constraint CONSTRAINT. */ 413 static bool 414 satisfies_address_constraint_p (struct address_info *ad, 415 enum constraint_num constraint) 416 { 417 address_eliminator eliminator (ad); 418 return constraint_satisfied_p (*ad->outer, constraint); 419 } 420 421 /* Return true if the eliminated form of address OP satisfies extra 422 address constraint CONSTRAINT. */ 423 static bool 424 satisfies_address_constraint_p (rtx op, enum constraint_num constraint) 425 { 426 struct address_info ad; 427 428 decompose_lea_address (&ad, &op); 429 return satisfies_address_constraint_p (&ad, constraint); 430 } 431 432 /* Initiate equivalences for LRA. As we keep original equivalences 433 before any elimination, we need to make copies otherwise any change 434 in insns might change the equivalences. */ 435 void 436 lra_init_equiv (void) 437 { 438 ira_expand_reg_equiv (); 439 for (int i = FIRST_PSEUDO_REGISTER; i < max_reg_num (); i++) 440 { 441 rtx res; 442 443 if ((res = ira_reg_equiv[i].memory) != NULL_RTX) 444 ira_reg_equiv[i].memory = copy_rtx (res); 445 if ((res = ira_reg_equiv[i].invariant) != NULL_RTX) 446 ira_reg_equiv[i].invariant = copy_rtx (res); 447 } 448 } 449 450 static rtx loc_equivalence_callback (rtx, const_rtx, void *); 451 452 /* Update equivalence for REGNO. We need to this as the equivalence 453 might contain other pseudos which are changed by their 454 equivalences. */ 455 static void 456 update_equiv (int regno) 457 { 458 rtx x; 459 460 if ((x = ira_reg_equiv[regno].memory) != NULL_RTX) 461 ira_reg_equiv[regno].memory 462 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, 463 NULL_RTX); 464 if ((x = ira_reg_equiv[regno].invariant) != NULL_RTX) 465 ira_reg_equiv[regno].invariant 466 = simplify_replace_fn_rtx (x, NULL_RTX, loc_equivalence_callback, 467 NULL_RTX); 468 } 469 470 /* If we have decided to substitute X with another value, return that 471 value, otherwise return X. */ 472 static rtx 473 get_equiv (rtx x) 474 { 475 int regno; 476 rtx res; 477 478 if (! REG_P (x) || (regno = REGNO (x)) < FIRST_PSEUDO_REGISTER 479 || ! ira_reg_equiv[regno].defined_p 480 || ! ira_reg_equiv[regno].profitable_p 481 || lra_get_regno_hard_regno (regno) >= 0) 482 return x; 483 if ((res = ira_reg_equiv[regno].memory) != NULL_RTX) 484 { 485 if (targetm.cannot_substitute_mem_equiv_p (res)) 486 return x; 487 return res; 488 } 489 if ((res = ira_reg_equiv[regno].constant) != NULL_RTX) 490 return res; 491 if ((res = ira_reg_equiv[regno].invariant) != NULL_RTX) 492 return res; 493 gcc_unreachable (); 494 } 495 496 /* If we have decided to substitute X with the equivalent value, 497 return that value after elimination for INSN, otherwise return 498 X. */ 499 static rtx 500 get_equiv_with_elimination (rtx x, rtx_insn *insn) 501 { 502 rtx res = get_equiv (x); 503 504 if (x == res || CONSTANT_P (res)) 505 return res; 506 return lra_eliminate_regs_1 (insn, res, GET_MODE (res), 507 false, false, 0, true); 508 } 509 510 /* Set up curr_operand_mode. */ 511 static void 512 init_curr_operand_mode (void) 513 { 514 int nop = curr_static_id->n_operands; 515 for (int i = 0; i < nop; i++) 516 { 517 machine_mode mode = GET_MODE (*curr_id->operand_loc[i]); 518 if (mode == VOIDmode) 519 { 520 /* The .md mode for address operands is the mode of the 521 addressed value rather than the mode of the address itself. */ 522 if (curr_id->icode >= 0 && curr_static_id->operand[i].is_address) 523 mode = Pmode; 524 else 525 mode = curr_static_id->operand[i].mode; 526 } 527 curr_operand_mode[i] = mode; 528 } 529 } 530 531 532 533 /* The page contains code to reuse input reloads. */ 534 535 /* Structure describes input reload of the current insns. */ 536 struct input_reload 537 { 538 /* True for input reload of matched operands. */ 539 bool match_p; 540 /* Reloaded value. */ 541 rtx input; 542 /* Reload pseudo used. */ 543 rtx reg; 544 }; 545 546 /* The number of elements in the following array. */ 547 static int curr_insn_input_reloads_num; 548 /* Array containing info about input reloads. It is used to find the 549 same input reload and reuse the reload pseudo in this case. */ 550 static struct input_reload curr_insn_input_reloads[LRA_MAX_INSN_RELOADS]; 551 552 /* Initiate data concerning reuse of input reloads for the current 553 insn. */ 554 static void 555 init_curr_insn_input_reloads (void) 556 { 557 curr_insn_input_reloads_num = 0; 558 } 559 560 /* Create a new pseudo using MODE, RCLASS, ORIGINAL or reuse already 561 created input reload pseudo (only if TYPE is not OP_OUT). Don't 562 reuse pseudo if IN_SUBREG_P is true and the reused pseudo should be 563 wrapped up in SUBREG. The result pseudo is returned through 564 RESULT_REG. Return TRUE if we created a new pseudo, FALSE if we 565 reused the already created input reload pseudo. Use TITLE to 566 describe new registers for debug purposes. */ 567 static bool 568 get_reload_reg (enum op_type type, machine_mode mode, rtx original, 569 enum reg_class rclass, bool in_subreg_p, 570 const char *title, rtx *result_reg) 571 { 572 int i, regno; 573 enum reg_class new_class; 574 bool unique_p = false; 575 576 if (type == OP_OUT) 577 { 578 *result_reg 579 = lra_create_new_reg_with_unique_value (mode, original, rclass, title); 580 return true; 581 } 582 /* Prevent reuse value of expression with side effects, 583 e.g. volatile memory. */ 584 if (! side_effects_p (original)) 585 for (i = 0; i < curr_insn_input_reloads_num; i++) 586 { 587 if (! curr_insn_input_reloads[i].match_p 588 && rtx_equal_p (curr_insn_input_reloads[i].input, original) 589 && in_class_p (curr_insn_input_reloads[i].reg, rclass, &new_class)) 590 { 591 rtx reg = curr_insn_input_reloads[i].reg; 592 regno = REGNO (reg); 593 /* If input is equal to original and both are VOIDmode, 594 GET_MODE (reg) might be still different from mode. 595 Ensure we don't return *result_reg with wrong mode. */ 596 if (GET_MODE (reg) != mode) 597 { 598 if (in_subreg_p) 599 continue; 600 if (maybe_lt (GET_MODE_SIZE (GET_MODE (reg)), 601 GET_MODE_SIZE (mode))) 602 continue; 603 reg = lowpart_subreg (mode, reg, GET_MODE (reg)); 604 if (reg == NULL_RTX || GET_CODE (reg) != SUBREG) 605 continue; 606 } 607 *result_reg = reg; 608 if (lra_dump_file != NULL) 609 { 610 fprintf (lra_dump_file, " Reuse r%d for reload ", regno); 611 dump_value_slim (lra_dump_file, original, 1); 612 } 613 if (new_class != lra_get_allocno_class (regno)) 614 lra_change_class (regno, new_class, ", change to", false); 615 if (lra_dump_file != NULL) 616 fprintf (lra_dump_file, "\n"); 617 return false; 618 } 619 /* If we have an input reload with a different mode, make sure it 620 will get a different hard reg. */ 621 else if (REG_P (original) 622 && REG_P (curr_insn_input_reloads[i].input) 623 && REGNO (original) == REGNO (curr_insn_input_reloads[i].input) 624 && (GET_MODE (original) 625 != GET_MODE (curr_insn_input_reloads[i].input))) 626 unique_p = true; 627 } 628 *result_reg = (unique_p 629 ? lra_create_new_reg_with_unique_value 630 : lra_create_new_reg) (mode, original, rclass, title); 631 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); 632 curr_insn_input_reloads[curr_insn_input_reloads_num].input = original; 633 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = false; 634 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = *result_reg; 635 return true; 636 } 637 638 639 /* The page contains major code to choose the current insn alternative 640 and generate reloads for it. */ 641 642 /* Return the offset from REGNO of the least significant register 643 in (reg:MODE REGNO). 644 645 This function is used to tell whether two registers satisfy 646 a matching constraint. (reg:MODE1 REGNO1) matches (reg:MODE2 REGNO2) if: 647 648 REGNO1 + lra_constraint_offset (REGNO1, MODE1) 649 == REGNO2 + lra_constraint_offset (REGNO2, MODE2) */ 650 int 651 lra_constraint_offset (int regno, machine_mode mode) 652 { 653 lra_assert (regno < FIRST_PSEUDO_REGISTER); 654 655 scalar_int_mode int_mode; 656 if (WORDS_BIG_ENDIAN 657 && is_a <scalar_int_mode> (mode, &int_mode) 658 && GET_MODE_SIZE (int_mode) > UNITS_PER_WORD) 659 return hard_regno_nregs (regno, mode) - 1; 660 return 0; 661 } 662 663 /* Like rtx_equal_p except that it allows a REG and a SUBREG to match 664 if they are the same hard reg, and has special hacks for 665 auto-increment and auto-decrement. This is specifically intended for 666 process_alt_operands to use in determining whether two operands 667 match. X is the operand whose number is the lower of the two. 668 669 It is supposed that X is the output operand and Y is the input 670 operand. Y_HARD_REGNO is the final hard regno of register Y or 671 register in subreg Y as we know it now. Otherwise, it is a 672 negative value. */ 673 static bool 674 operands_match_p (rtx x, rtx y, int y_hard_regno) 675 { 676 int i; 677 RTX_CODE code = GET_CODE (x); 678 const char *fmt; 679 680 if (x == y) 681 return true; 682 if ((code == REG || (code == SUBREG && REG_P (SUBREG_REG (x)))) 683 && (REG_P (y) || (GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y))))) 684 { 685 int j; 686 687 i = get_hard_regno (x, false); 688 if (i < 0) 689 goto slow; 690 691 if ((j = y_hard_regno) < 0) 692 goto slow; 693 694 i += lra_constraint_offset (i, GET_MODE (x)); 695 j += lra_constraint_offset (j, GET_MODE (y)); 696 697 return i == j; 698 } 699 700 /* If two operands must match, because they are really a single 701 operand of an assembler insn, then two post-increments are invalid 702 because the assembler insn would increment only once. On the 703 other hand, a post-increment matches ordinary indexing if the 704 post-increment is the output operand. */ 705 if (code == POST_DEC || code == POST_INC || code == POST_MODIFY) 706 return operands_match_p (XEXP (x, 0), y, y_hard_regno); 707 708 /* Two pre-increments are invalid because the assembler insn would 709 increment only once. On the other hand, a pre-increment matches 710 ordinary indexing if the pre-increment is the input operand. */ 711 if (GET_CODE (y) == PRE_DEC || GET_CODE (y) == PRE_INC 712 || GET_CODE (y) == PRE_MODIFY) 713 return operands_match_p (x, XEXP (y, 0), -1); 714 715 slow: 716 717 if (code == REG && REG_P (y)) 718 return REGNO (x) == REGNO (y); 719 720 if (code == REG && GET_CODE (y) == SUBREG && REG_P (SUBREG_REG (y)) 721 && x == SUBREG_REG (y)) 722 return true; 723 if (GET_CODE (y) == REG && code == SUBREG && REG_P (SUBREG_REG (x)) 724 && SUBREG_REG (x) == y) 725 return true; 726 727 /* Now we have disposed of all the cases in which different rtx 728 codes can match. */ 729 if (code != GET_CODE (y)) 730 return false; 731 732 /* (MULT:SI x y) and (MULT:HI x y) are NOT equivalent. */ 733 if (GET_MODE (x) != GET_MODE (y)) 734 return false; 735 736 switch (code) 737 { 738 CASE_CONST_UNIQUE: 739 return false; 740 741 case LABEL_REF: 742 return label_ref_label (x) == label_ref_label (y); 743 case SYMBOL_REF: 744 return XSTR (x, 0) == XSTR (y, 0); 745 746 default: 747 break; 748 } 749 750 /* Compare the elements. If any pair of corresponding elements fail 751 to match, return false for the whole things. */ 752 753 fmt = GET_RTX_FORMAT (code); 754 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 755 { 756 int val, j; 757 switch (fmt[i]) 758 { 759 case 'w': 760 if (XWINT (x, i) != XWINT (y, i)) 761 return false; 762 break; 763 764 case 'i': 765 if (XINT (x, i) != XINT (y, i)) 766 return false; 767 break; 768 769 case 'p': 770 if (maybe_ne (SUBREG_BYTE (x), SUBREG_BYTE (y))) 771 return false; 772 break; 773 774 case 'e': 775 val = operands_match_p (XEXP (x, i), XEXP (y, i), -1); 776 if (val == 0) 777 return false; 778 break; 779 780 case '0': 781 break; 782 783 case 'E': 784 if (XVECLEN (x, i) != XVECLEN (y, i)) 785 return false; 786 for (j = XVECLEN (x, i) - 1; j >= 0; --j) 787 { 788 val = operands_match_p (XVECEXP (x, i, j), XVECEXP (y, i, j), -1); 789 if (val == 0) 790 return false; 791 } 792 break; 793 794 /* It is believed that rtx's at this level will never 795 contain anything but integers and other rtx's, except for 796 within LABEL_REFs and SYMBOL_REFs. */ 797 default: 798 gcc_unreachable (); 799 } 800 } 801 return true; 802 } 803 804 /* True if X is a constant that can be forced into the constant pool. 805 MODE is the mode of the operand, or VOIDmode if not known. */ 806 #define CONST_POOL_OK_P(MODE, X) \ 807 ((MODE) != VOIDmode \ 808 && CONSTANT_P (X) \ 809 && GET_CODE (X) != HIGH \ 810 && GET_MODE_SIZE (MODE).is_constant () \ 811 && !targetm.cannot_force_const_mem (MODE, X)) 812 813 /* True if C is a non-empty register class that has too few registers 814 to be safely used as a reload target class. */ 815 #define SMALL_REGISTER_CLASS_P(C) \ 816 (ira_class_hard_regs_num [(C)] == 1 \ 817 || (ira_class_hard_regs_num [(C)] >= 1 \ 818 && targetm.class_likely_spilled_p (C))) 819 820 /* If REG is a reload pseudo, try to make its class satisfying CL. */ 821 static void 822 narrow_reload_pseudo_class (rtx reg, enum reg_class cl) 823 { 824 enum reg_class rclass; 825 826 /* Do not make more accurate class from reloads generated. They are 827 mostly moves with a lot of constraints. Making more accurate 828 class may results in very narrow class and impossibility of find 829 registers for several reloads of one insn. */ 830 if (INSN_UID (curr_insn) >= new_insn_uid_start) 831 return; 832 if (GET_CODE (reg) == SUBREG) 833 reg = SUBREG_REG (reg); 834 if (! REG_P (reg) || (int) REGNO (reg) < new_regno_start) 835 return; 836 if (in_class_p (reg, cl, &rclass) && rclass != cl) 837 lra_change_class (REGNO (reg), rclass, " Change to", true); 838 } 839 840 /* Searches X for any reference to a reg with the same value as REGNO, 841 returning the rtx of the reference found if any. Otherwise, 842 returns NULL_RTX. */ 843 static rtx 844 regno_val_use_in (unsigned int regno, rtx x) 845 { 846 const char *fmt; 847 int i, j; 848 rtx tem; 849 850 if (REG_P (x) && lra_reg_info[REGNO (x)].val == lra_reg_info[regno].val) 851 return x; 852 853 fmt = GET_RTX_FORMAT (GET_CODE (x)); 854 for (i = GET_RTX_LENGTH (GET_CODE (x)) - 1; i >= 0; i--) 855 { 856 if (fmt[i] == 'e') 857 { 858 if ((tem = regno_val_use_in (regno, XEXP (x, i)))) 859 return tem; 860 } 861 else if (fmt[i] == 'E') 862 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 863 if ((tem = regno_val_use_in (regno , XVECEXP (x, i, j)))) 864 return tem; 865 } 866 867 return NULL_RTX; 868 } 869 870 /* Return true if all current insn non-output operands except INS (it 871 has a negaitve end marker) do not use pseudos with the same value 872 as REGNO. */ 873 static bool 874 check_conflict_input_operands (int regno, signed char *ins) 875 { 876 int in; 877 int n_operands = curr_static_id->n_operands; 878 879 for (int nop = 0; nop < n_operands; nop++) 880 if (! curr_static_id->operand[nop].is_operator 881 && curr_static_id->operand[nop].type != OP_OUT) 882 { 883 for (int i = 0; (in = ins[i]) >= 0; i++) 884 if (in == nop) 885 break; 886 if (in < 0 887 && regno_val_use_in (regno, *curr_id->operand_loc[nop]) != NULL_RTX) 888 return false; 889 } 890 return true; 891 } 892 893 /* Generate reloads for matching OUT and INS (array of input operand 894 numbers with end marker -1) with reg class GOAL_CLASS, considering 895 output operands OUTS (similar array to INS) needing to be in different 896 registers. Add input and output reloads correspondingly to the lists 897 *BEFORE and *AFTER. OUT might be negative. In this case we generate 898 input reloads for matched input operands INS. EARLY_CLOBBER_P is a flag 899 that the output operand is early clobbered for chosen alternative. */ 900 static void 901 match_reload (signed char out, signed char *ins, signed char *outs, 902 enum reg_class goal_class, rtx_insn **before, 903 rtx_insn **after, bool early_clobber_p) 904 { 905 bool out_conflict; 906 int i, in; 907 rtx new_in_reg, new_out_reg, reg; 908 machine_mode inmode, outmode; 909 rtx in_rtx = *curr_id->operand_loc[ins[0]]; 910 rtx out_rtx = out < 0 ? in_rtx : *curr_id->operand_loc[out]; 911 912 inmode = curr_operand_mode[ins[0]]; 913 outmode = out < 0 ? inmode : curr_operand_mode[out]; 914 push_to_sequence (*before); 915 if (inmode != outmode) 916 { 917 /* process_alt_operands has already checked that the mode sizes 918 are ordered. */ 919 if (partial_subreg_p (outmode, inmode)) 920 { 921 reg = new_in_reg 922 = lra_create_new_reg_with_unique_value (inmode, in_rtx, 923 goal_class, ""); 924 new_out_reg = gen_lowpart_SUBREG (outmode, reg); 925 LRA_SUBREG_P (new_out_reg) = 1; 926 /* If the input reg is dying here, we can use the same hard 927 register for REG and IN_RTX. We do it only for original 928 pseudos as reload pseudos can die although original 929 pseudos still live where reload pseudos dies. */ 930 if (REG_P (in_rtx) && (int) REGNO (in_rtx) < lra_new_regno_start 931 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) 932 && (!early_clobber_p 933 || check_conflict_input_operands(REGNO (in_rtx), ins))) 934 lra_assign_reg_val (REGNO (in_rtx), REGNO (reg)); 935 } 936 else 937 { 938 reg = new_out_reg 939 = lra_create_new_reg_with_unique_value (outmode, out_rtx, 940 goal_class, ""); 941 new_in_reg = gen_lowpart_SUBREG (inmode, reg); 942 /* NEW_IN_REG is non-paradoxical subreg. We don't want 943 NEW_OUT_REG living above. We add clobber clause for 944 this. This is just a temporary clobber. We can remove 945 it at the end of LRA work. */ 946 rtx_insn *clobber = emit_clobber (new_out_reg); 947 LRA_TEMP_CLOBBER_P (PATTERN (clobber)) = 1; 948 LRA_SUBREG_P (new_in_reg) = 1; 949 if (GET_CODE (in_rtx) == SUBREG) 950 { 951 rtx subreg_reg = SUBREG_REG (in_rtx); 952 953 /* If SUBREG_REG is dying here and sub-registers IN_RTX 954 and NEW_IN_REG are similar, we can use the same hard 955 register for REG and SUBREG_REG. */ 956 if (REG_P (subreg_reg) 957 && (int) REGNO (subreg_reg) < lra_new_regno_start 958 && GET_MODE (subreg_reg) == outmode 959 && known_eq (SUBREG_BYTE (in_rtx), SUBREG_BYTE (new_in_reg)) 960 && find_regno_note (curr_insn, REG_DEAD, REGNO (subreg_reg)) 961 && (! early_clobber_p 962 || check_conflict_input_operands (REGNO (subreg_reg), 963 ins))) 964 lra_assign_reg_val (REGNO (subreg_reg), REGNO (reg)); 965 } 966 } 967 } 968 else 969 { 970 /* Pseudos have values -- see comments for lra_reg_info. 971 Different pseudos with the same value do not conflict even if 972 they live in the same place. When we create a pseudo we 973 assign value of original pseudo (if any) from which we 974 created the new pseudo. If we create the pseudo from the 975 input pseudo, the new pseudo will have no conflict with the 976 input pseudo which is wrong when the input pseudo lives after 977 the insn and as the new pseudo value is changed by the insn 978 output. Therefore we create the new pseudo from the output 979 except the case when we have single matched dying input 980 pseudo. 981 982 We cannot reuse the current output register because we might 983 have a situation like "a <- a op b", where the constraints 984 force the second input operand ("b") to match the output 985 operand ("a"). "b" must then be copied into a new register 986 so that it doesn't clobber the current value of "a". 987 988 We cannot use the same value if the output pseudo is 989 early clobbered or the input pseudo is mentioned in the 990 output, e.g. as an address part in memory, because 991 output reload will actually extend the pseudo liveness. 992 We don't care about eliminable hard regs here as we are 993 interesting only in pseudos. */ 994 995 /* Matching input's register value is the same as one of the other 996 output operand. Output operands in a parallel insn must be in 997 different registers. */ 998 out_conflict = false; 999 if (REG_P (in_rtx)) 1000 { 1001 for (i = 0; outs[i] >= 0; i++) 1002 { 1003 rtx other_out_rtx = *curr_id->operand_loc[outs[i]]; 1004 if (REG_P (other_out_rtx) 1005 && (regno_val_use_in (REGNO (in_rtx), other_out_rtx) 1006 != NULL_RTX)) 1007 { 1008 out_conflict = true; 1009 break; 1010 } 1011 } 1012 } 1013 1014 new_in_reg = new_out_reg 1015 = (! early_clobber_p && ins[1] < 0 && REG_P (in_rtx) 1016 && (int) REGNO (in_rtx) < lra_new_regno_start 1017 && find_regno_note (curr_insn, REG_DEAD, REGNO (in_rtx)) 1018 && (! early_clobber_p 1019 || check_conflict_input_operands (REGNO (in_rtx), ins)) 1020 && (out < 0 1021 || regno_val_use_in (REGNO (in_rtx), out_rtx) == NULL_RTX) 1022 && !out_conflict 1023 ? lra_create_new_reg (inmode, in_rtx, goal_class, "") 1024 : lra_create_new_reg_with_unique_value (outmode, out_rtx, 1025 goal_class, "")); 1026 } 1027 /* In operand can be got from transformations before processing insn 1028 constraints. One example of such transformations is subreg 1029 reloading (see function simplify_operand_subreg). The new 1030 pseudos created by the transformations might have inaccurate 1031 class (ALL_REGS) and we should make their classes more 1032 accurate. */ 1033 narrow_reload_pseudo_class (in_rtx, goal_class); 1034 lra_emit_move (copy_rtx (new_in_reg), in_rtx); 1035 *before = get_insns (); 1036 end_sequence (); 1037 /* Add the new pseudo to consider values of subsequent input reload 1038 pseudos. */ 1039 lra_assert (curr_insn_input_reloads_num < LRA_MAX_INSN_RELOADS); 1040 curr_insn_input_reloads[curr_insn_input_reloads_num].input = in_rtx; 1041 curr_insn_input_reloads[curr_insn_input_reloads_num].match_p = true; 1042 curr_insn_input_reloads[curr_insn_input_reloads_num++].reg = new_in_reg; 1043 for (i = 0; (in = ins[i]) >= 0; i++) 1044 { 1045 lra_assert 1046 (GET_MODE (*curr_id->operand_loc[in]) == VOIDmode 1047 || GET_MODE (new_in_reg) == GET_MODE (*curr_id->operand_loc[in])); 1048 *curr_id->operand_loc[in] = new_in_reg; 1049 } 1050 lra_update_dups (curr_id, ins); 1051 if (out < 0) 1052 return; 1053 /* See a comment for the input operand above. */ 1054 narrow_reload_pseudo_class (out_rtx, goal_class); 1055 if (find_reg_note (curr_insn, REG_UNUSED, out_rtx) == NULL_RTX) 1056 { 1057 start_sequence (); 1058 lra_emit_move (out_rtx, copy_rtx (new_out_reg)); 1059 emit_insn (*after); 1060 *after = get_insns (); 1061 end_sequence (); 1062 } 1063 *curr_id->operand_loc[out] = new_out_reg; 1064 lra_update_dup (curr_id, out); 1065 } 1066 1067 /* Return register class which is union of all reg classes in insn 1068 constraint alternative string starting with P. */ 1069 static enum reg_class 1070 reg_class_from_constraints (const char *p) 1071 { 1072 int c, len; 1073 enum reg_class op_class = NO_REGS; 1074 1075 do 1076 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) 1077 { 1078 case '#': 1079 case ',': 1080 return op_class; 1081 1082 case 'g': 1083 op_class = reg_class_subunion[op_class][GENERAL_REGS]; 1084 break; 1085 1086 default: 1087 enum constraint_num cn = lookup_constraint (p); 1088 enum reg_class cl = reg_class_for_constraint (cn); 1089 if (cl == NO_REGS) 1090 { 1091 if (insn_extra_address_constraint (cn)) 1092 op_class 1093 = (reg_class_subunion 1094 [op_class][base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 1095 ADDRESS, SCRATCH)]); 1096 break; 1097 } 1098 1099 op_class = reg_class_subunion[op_class][cl]; 1100 break; 1101 } 1102 while ((p += len), c); 1103 return op_class; 1104 } 1105 1106 /* If OP is a register, return the class of the register as per 1107 get_reg_class, otherwise return NO_REGS. */ 1108 static inline enum reg_class 1109 get_op_class (rtx op) 1110 { 1111 return REG_P (op) ? get_reg_class (REGNO (op)) : NO_REGS; 1112 } 1113 1114 /* Return generated insn mem_pseudo:=val if TO_P or val:=mem_pseudo 1115 otherwise. If modes of MEM_PSEUDO and VAL are different, use 1116 SUBREG for VAL to make them equal. */ 1117 static rtx_insn * 1118 emit_spill_move (bool to_p, rtx mem_pseudo, rtx val) 1119 { 1120 if (GET_MODE (mem_pseudo) != GET_MODE (val)) 1121 { 1122 /* Usually size of mem_pseudo is greater than val size but in 1123 rare cases it can be less as it can be defined by target 1124 dependent macro HARD_REGNO_CALLER_SAVE_MODE. */ 1125 if (! MEM_P (val)) 1126 { 1127 val = gen_lowpart_SUBREG (GET_MODE (mem_pseudo), 1128 GET_CODE (val) == SUBREG 1129 ? SUBREG_REG (val) : val); 1130 LRA_SUBREG_P (val) = 1; 1131 } 1132 else 1133 { 1134 mem_pseudo = gen_lowpart_SUBREG (GET_MODE (val), mem_pseudo); 1135 LRA_SUBREG_P (mem_pseudo) = 1; 1136 } 1137 } 1138 return to_p ? gen_move_insn (mem_pseudo, val) 1139 : gen_move_insn (val, mem_pseudo); 1140 } 1141 1142 /* Process a special case insn (register move), return true if we 1143 don't need to process it anymore. INSN should be a single set 1144 insn. Set up that RTL was changed through CHANGE_P and that hook 1145 TARGET_SECONDARY_MEMORY_NEEDED says to use secondary memory through 1146 SEC_MEM_P. */ 1147 static bool 1148 check_and_process_move (bool *change_p, bool *sec_mem_p ATTRIBUTE_UNUSED) 1149 { 1150 int sregno, dregno; 1151 rtx dest, src, dreg, sreg, new_reg, scratch_reg; 1152 rtx_insn *before; 1153 enum reg_class dclass, sclass, secondary_class; 1154 secondary_reload_info sri; 1155 1156 lra_assert (curr_insn_set != NULL_RTX); 1157 dreg = dest = SET_DEST (curr_insn_set); 1158 sreg = src = SET_SRC (curr_insn_set); 1159 if (GET_CODE (dest) == SUBREG) 1160 dreg = SUBREG_REG (dest); 1161 if (GET_CODE (src) == SUBREG) 1162 sreg = SUBREG_REG (src); 1163 if (! (REG_P (dreg) || MEM_P (dreg)) || ! (REG_P (sreg) || MEM_P (sreg))) 1164 return false; 1165 sclass = dclass = NO_REGS; 1166 if (REG_P (dreg)) 1167 dclass = get_reg_class (REGNO (dreg)); 1168 gcc_assert (dclass < LIM_REG_CLASSES); 1169 if (dclass == ALL_REGS) 1170 /* ALL_REGS is used for new pseudos created by transformations 1171 like reload of SUBREG_REG (see function 1172 simplify_operand_subreg). We don't know their class yet. We 1173 should figure out the class from processing the insn 1174 constraints not in this fast path function. Even if ALL_REGS 1175 were a right class for the pseudo, secondary_... hooks usually 1176 are not define for ALL_REGS. */ 1177 return false; 1178 if (REG_P (sreg)) 1179 sclass = get_reg_class (REGNO (sreg)); 1180 gcc_assert (sclass < LIM_REG_CLASSES); 1181 if (sclass == ALL_REGS) 1182 /* See comments above. */ 1183 return false; 1184 if (sclass == NO_REGS && dclass == NO_REGS) 1185 return false; 1186 if (targetm.secondary_memory_needed (GET_MODE (src), sclass, dclass) 1187 && ((sclass != NO_REGS && dclass != NO_REGS) 1188 || (GET_MODE (src) 1189 != targetm.secondary_memory_needed_mode (GET_MODE (src))))) 1190 { 1191 *sec_mem_p = true; 1192 return false; 1193 } 1194 if (! REG_P (dreg) || ! REG_P (sreg)) 1195 return false; 1196 sri.prev_sri = NULL; 1197 sri.icode = CODE_FOR_nothing; 1198 sri.extra_cost = 0; 1199 secondary_class = NO_REGS; 1200 /* Set up hard register for a reload pseudo for hook 1201 secondary_reload because some targets just ignore unassigned 1202 pseudos in the hook. */ 1203 if (dclass != NO_REGS && lra_get_regno_hard_regno (REGNO (dreg)) < 0) 1204 { 1205 dregno = REGNO (dreg); 1206 reg_renumber[dregno] = ira_class_hard_regs[dclass][0]; 1207 } 1208 else 1209 dregno = -1; 1210 if (sclass != NO_REGS && lra_get_regno_hard_regno (REGNO (sreg)) < 0) 1211 { 1212 sregno = REGNO (sreg); 1213 reg_renumber[sregno] = ira_class_hard_regs[sclass][0]; 1214 } 1215 else 1216 sregno = -1; 1217 if (sclass != NO_REGS) 1218 secondary_class 1219 = (enum reg_class) targetm.secondary_reload (false, dest, 1220 (reg_class_t) sclass, 1221 GET_MODE (src), &sri); 1222 if (sclass == NO_REGS 1223 || ((secondary_class != NO_REGS || sri.icode != CODE_FOR_nothing) 1224 && dclass != NO_REGS)) 1225 { 1226 enum reg_class old_sclass = secondary_class; 1227 secondary_reload_info old_sri = sri; 1228 1229 sri.prev_sri = NULL; 1230 sri.icode = CODE_FOR_nothing; 1231 sri.extra_cost = 0; 1232 secondary_class 1233 = (enum reg_class) targetm.secondary_reload (true, src, 1234 (reg_class_t) dclass, 1235 GET_MODE (src), &sri); 1236 /* Check the target hook consistency. */ 1237 lra_assert 1238 ((secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) 1239 || (old_sclass == NO_REGS && old_sri.icode == CODE_FOR_nothing) 1240 || (secondary_class == old_sclass && sri.icode == old_sri.icode)); 1241 } 1242 if (sregno >= 0) 1243 reg_renumber [sregno] = -1; 1244 if (dregno >= 0) 1245 reg_renumber [dregno] = -1; 1246 if (secondary_class == NO_REGS && sri.icode == CODE_FOR_nothing) 1247 return false; 1248 *change_p = true; 1249 new_reg = NULL_RTX; 1250 if (secondary_class != NO_REGS) 1251 new_reg = lra_create_new_reg_with_unique_value (GET_MODE (src), NULL_RTX, 1252 secondary_class, 1253 "secondary"); 1254 start_sequence (); 1255 if (sri.icode == CODE_FOR_nothing) 1256 lra_emit_move (new_reg, src); 1257 else 1258 { 1259 enum reg_class scratch_class; 1260 1261 scratch_class = (reg_class_from_constraints 1262 (insn_data[sri.icode].operand[2].constraint)); 1263 scratch_reg = (lra_create_new_reg_with_unique_value 1264 (insn_data[sri.icode].operand[2].mode, NULL_RTX, 1265 scratch_class, "scratch")); 1266 emit_insn (GEN_FCN (sri.icode) (new_reg != NULL_RTX ? new_reg : dest, 1267 src, scratch_reg)); 1268 } 1269 before = get_insns (); 1270 end_sequence (); 1271 lra_process_new_insns (curr_insn, before, NULL, "Inserting the move"); 1272 if (new_reg != NULL_RTX) 1273 SET_SRC (curr_insn_set) = new_reg; 1274 else 1275 { 1276 if (lra_dump_file != NULL) 1277 { 1278 fprintf (lra_dump_file, "Deleting move %u\n", INSN_UID (curr_insn)); 1279 dump_insn_slim (lra_dump_file, curr_insn); 1280 } 1281 lra_set_insn_deleted (curr_insn); 1282 return true; 1283 } 1284 return false; 1285 } 1286 1287 /* The following data describe the result of process_alt_operands. 1288 The data are used in curr_insn_transform to generate reloads. */ 1289 1290 /* The chosen reg classes which should be used for the corresponding 1291 operands. */ 1292 static enum reg_class goal_alt[MAX_RECOG_OPERANDS]; 1293 /* True if the operand should be the same as another operand and that 1294 other operand does not need a reload. */ 1295 static bool goal_alt_match_win[MAX_RECOG_OPERANDS]; 1296 /* True if the operand does not need a reload. */ 1297 static bool goal_alt_win[MAX_RECOG_OPERANDS]; 1298 /* True if the operand can be offsetable memory. */ 1299 static bool goal_alt_offmemok[MAX_RECOG_OPERANDS]; 1300 /* The number of an operand to which given operand can be matched to. */ 1301 static int goal_alt_matches[MAX_RECOG_OPERANDS]; 1302 /* The number of elements in the following array. */ 1303 static int goal_alt_dont_inherit_ops_num; 1304 /* Numbers of operands whose reload pseudos should not be inherited. */ 1305 static int goal_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; 1306 /* True if the insn commutative operands should be swapped. */ 1307 static bool goal_alt_swapped; 1308 /* The chosen insn alternative. */ 1309 static int goal_alt_number; 1310 1311 /* True if the corresponding operand is the result of an equivalence 1312 substitution. */ 1313 static bool equiv_substition_p[MAX_RECOG_OPERANDS]; 1314 1315 /* The following five variables are used to choose the best insn 1316 alternative. They reflect final characteristics of the best 1317 alternative. */ 1318 1319 /* Number of necessary reloads and overall cost reflecting the 1320 previous value and other unpleasantness of the best alternative. */ 1321 static int best_losers, best_overall; 1322 /* Overall number hard registers used for reloads. For example, on 1323 some targets we need 2 general registers to reload DFmode and only 1324 one floating point register. */ 1325 static int best_reload_nregs; 1326 /* Overall number reflecting distances of previous reloading the same 1327 value. The distances are counted from the current BB start. It is 1328 used to improve inheritance chances. */ 1329 static int best_reload_sum; 1330 1331 /* True if the current insn should have no correspondingly input or 1332 output reloads. */ 1333 static bool no_input_reloads_p, no_output_reloads_p; 1334 1335 /* True if we swapped the commutative operands in the current 1336 insn. */ 1337 static int curr_swapped; 1338 1339 /* if CHECK_ONLY_P is false, arrange for address element *LOC to be a 1340 register of class CL. Add any input reloads to list BEFORE. AFTER 1341 is nonnull if *LOC is an automodified value; handle that case by 1342 adding the required output reloads to list AFTER. Return true if 1343 the RTL was changed. 1344 1345 if CHECK_ONLY_P is true, check that the *LOC is a correct address 1346 register. Return false if the address register is correct. */ 1347 static bool 1348 process_addr_reg (rtx *loc, bool check_only_p, rtx_insn **before, rtx_insn **after, 1349 enum reg_class cl) 1350 { 1351 int regno; 1352 enum reg_class rclass, new_class; 1353 rtx reg; 1354 rtx new_reg; 1355 machine_mode mode; 1356 bool subreg_p, before_p = false; 1357 1358 subreg_p = GET_CODE (*loc) == SUBREG; 1359 if (subreg_p) 1360 { 1361 reg = SUBREG_REG (*loc); 1362 mode = GET_MODE (reg); 1363 1364 /* For mode with size bigger than ptr_mode, there unlikely to be "mov" 1365 between two registers with different classes, but there normally will 1366 be "mov" which transfers element of vector register into the general 1367 register, and this normally will be a subreg which should be reloaded 1368 as a whole. This is particularly likely to be triggered when 1369 -fno-split-wide-types specified. */ 1370 if (!REG_P (reg) 1371 || in_class_p (reg, cl, &new_class) 1372 || known_le (GET_MODE_SIZE (mode), GET_MODE_SIZE (ptr_mode))) 1373 loc = &SUBREG_REG (*loc); 1374 } 1375 1376 reg = *loc; 1377 mode = GET_MODE (reg); 1378 if (! REG_P (reg)) 1379 { 1380 if (check_only_p) 1381 return true; 1382 /* Always reload memory in an address even if the target supports 1383 such addresses. */ 1384 new_reg = lra_create_new_reg_with_unique_value (mode, reg, cl, "address"); 1385 before_p = true; 1386 } 1387 else 1388 { 1389 regno = REGNO (reg); 1390 rclass = get_reg_class (regno); 1391 if (! check_only_p 1392 && (*loc = get_equiv_with_elimination (reg, curr_insn)) != reg) 1393 { 1394 if (lra_dump_file != NULL) 1395 { 1396 fprintf (lra_dump_file, 1397 "Changing pseudo %d in address of insn %u on equiv ", 1398 REGNO (reg), INSN_UID (curr_insn)); 1399 dump_value_slim (lra_dump_file, *loc, 1); 1400 fprintf (lra_dump_file, "\n"); 1401 } 1402 *loc = copy_rtx (*loc); 1403 } 1404 if (*loc != reg || ! in_class_p (reg, cl, &new_class)) 1405 { 1406 if (check_only_p) 1407 return true; 1408 reg = *loc; 1409 if (get_reload_reg (after == NULL ? OP_IN : OP_INOUT, 1410 mode, reg, cl, subreg_p, "address", &new_reg)) 1411 before_p = true; 1412 } 1413 else if (new_class != NO_REGS && rclass != new_class) 1414 { 1415 if (check_only_p) 1416 return true; 1417 lra_change_class (regno, new_class, " Change to", true); 1418 return false; 1419 } 1420 else 1421 return false; 1422 } 1423 if (before_p) 1424 { 1425 push_to_sequence (*before); 1426 lra_emit_move (new_reg, reg); 1427 *before = get_insns (); 1428 end_sequence (); 1429 } 1430 *loc = new_reg; 1431 if (after != NULL) 1432 { 1433 start_sequence (); 1434 lra_emit_move (before_p ? copy_rtx (reg) : reg, new_reg); 1435 emit_insn (*after); 1436 *after = get_insns (); 1437 end_sequence (); 1438 } 1439 return true; 1440 } 1441 1442 /* Insert move insn in simplify_operand_subreg. BEFORE returns 1443 the insn to be inserted before curr insn. AFTER returns the 1444 the insn to be inserted after curr insn. ORIGREG and NEWREG 1445 are the original reg and new reg for reload. */ 1446 static void 1447 insert_move_for_subreg (rtx_insn **before, rtx_insn **after, rtx origreg, 1448 rtx newreg) 1449 { 1450 if (before) 1451 { 1452 push_to_sequence (*before); 1453 lra_emit_move (newreg, origreg); 1454 *before = get_insns (); 1455 end_sequence (); 1456 } 1457 if (after) 1458 { 1459 start_sequence (); 1460 lra_emit_move (origreg, newreg); 1461 emit_insn (*after); 1462 *after = get_insns (); 1463 end_sequence (); 1464 } 1465 } 1466 1467 static int valid_address_p (machine_mode mode, rtx addr, addr_space_t as); 1468 static bool process_address (int, bool, rtx_insn **, rtx_insn **); 1469 1470 /* Make reloads for subreg in operand NOP with internal subreg mode 1471 REG_MODE, add new reloads for further processing. Return true if 1472 any change was done. */ 1473 static bool 1474 simplify_operand_subreg (int nop, machine_mode reg_mode) 1475 { 1476 int hard_regno; 1477 rtx_insn *before, *after; 1478 machine_mode mode, innermode; 1479 rtx reg, new_reg; 1480 rtx operand = *curr_id->operand_loc[nop]; 1481 enum reg_class regclass; 1482 enum op_type type; 1483 1484 before = after = NULL; 1485 1486 if (GET_CODE (operand) != SUBREG) 1487 return false; 1488 1489 mode = GET_MODE (operand); 1490 reg = SUBREG_REG (operand); 1491 innermode = GET_MODE (reg); 1492 type = curr_static_id->operand[nop].type; 1493 if (MEM_P (reg)) 1494 { 1495 const bool addr_was_valid 1496 = valid_address_p (innermode, XEXP (reg, 0), MEM_ADDR_SPACE (reg)); 1497 alter_subreg (curr_id->operand_loc[nop], false); 1498 rtx subst = *curr_id->operand_loc[nop]; 1499 lra_assert (MEM_P (subst)); 1500 const bool addr_is_valid = valid_address_p (GET_MODE (subst), 1501 XEXP (subst, 0), 1502 MEM_ADDR_SPACE (subst)); 1503 if (!addr_was_valid 1504 || addr_is_valid 1505 || ((get_constraint_type (lookup_constraint 1506 (curr_static_id->operand[nop].constraint)) 1507 != CT_SPECIAL_MEMORY) 1508 /* We still can reload address and if the address is 1509 valid, we can remove subreg without reloading its 1510 inner memory. */ 1511 && valid_address_p (GET_MODE (subst), 1512 regno_reg_rtx 1513 [ira_class_hard_regs 1514 [base_reg_class (GET_MODE (subst), 1515 MEM_ADDR_SPACE (subst), 1516 ADDRESS, SCRATCH)][0]], 1517 MEM_ADDR_SPACE (subst)))) 1518 { 1519 /* If we change the address for a paradoxical subreg of memory, the 1520 new address might violate the necessary alignment or the access 1521 might be slow; take this into consideration. We need not worry 1522 about accesses beyond allocated memory for paradoxical memory 1523 subregs as we don't substitute such equiv memory (see processing 1524 equivalences in function lra_constraints) and because for spilled 1525 pseudos we allocate stack memory enough for the biggest 1526 corresponding paradoxical subreg. 1527 1528 However, do not blindly simplify a (subreg (mem ...)) for 1529 WORD_REGISTER_OPERATIONS targets as this may lead to loading junk 1530 data into a register when the inner is narrower than outer or 1531 missing important data from memory when the inner is wider than 1532 outer. This rule only applies to modes that are no wider than 1533 a word. 1534 1535 If valid memory becomes invalid after subreg elimination 1536 and address might be different we still have to reload 1537 memory. 1538 */ 1539 if ((! addr_was_valid 1540 || addr_is_valid 1541 || known_eq (GET_MODE_SIZE (mode), GET_MODE_SIZE (innermode))) 1542 && !(maybe_ne (GET_MODE_PRECISION (mode), 1543 GET_MODE_PRECISION (innermode)) 1544 && known_le (GET_MODE_SIZE (mode), UNITS_PER_WORD) 1545 && known_le (GET_MODE_SIZE (innermode), UNITS_PER_WORD) 1546 && WORD_REGISTER_OPERATIONS) 1547 && (!(MEM_ALIGN (subst) < GET_MODE_ALIGNMENT (mode) 1548 && targetm.slow_unaligned_access (mode, MEM_ALIGN (subst))) 1549 || (MEM_ALIGN (reg) < GET_MODE_ALIGNMENT (innermode) 1550 && targetm.slow_unaligned_access (innermode, 1551 MEM_ALIGN (reg))))) 1552 return true; 1553 1554 *curr_id->operand_loc[nop] = operand; 1555 1556 /* But if the address was not valid, we cannot reload the MEM without 1557 reloading the address first. */ 1558 if (!addr_was_valid) 1559 process_address (nop, false, &before, &after); 1560 1561 /* INNERMODE is fast, MODE slow. Reload the mem in INNERMODE. */ 1562 enum reg_class rclass 1563 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1564 if (get_reload_reg (curr_static_id->operand[nop].type, innermode, 1565 reg, rclass, TRUE, "slow/invalid mem", &new_reg)) 1566 { 1567 bool insert_before, insert_after; 1568 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); 1569 1570 insert_before = (type != OP_OUT 1571 || partial_subreg_p (mode, innermode)); 1572 insert_after = type != OP_IN; 1573 insert_move_for_subreg (insert_before ? &before : NULL, 1574 insert_after ? &after : NULL, 1575 reg, new_reg); 1576 } 1577 SUBREG_REG (operand) = new_reg; 1578 1579 /* Convert to MODE. */ 1580 reg = operand; 1581 rclass 1582 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1583 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, 1584 rclass, TRUE, "slow/invalid mem", &new_reg)) 1585 { 1586 bool insert_before, insert_after; 1587 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); 1588 1589 insert_before = type != OP_OUT; 1590 insert_after = type != OP_IN; 1591 insert_move_for_subreg (insert_before ? &before : NULL, 1592 insert_after ? &after : NULL, 1593 reg, new_reg); 1594 } 1595 *curr_id->operand_loc[nop] = new_reg; 1596 lra_process_new_insns (curr_insn, before, after, 1597 "Inserting slow/invalid mem reload"); 1598 return true; 1599 } 1600 1601 /* If the address was valid and became invalid, prefer to reload 1602 the memory. Typical case is when the index scale should 1603 correspond the memory. */ 1604 *curr_id->operand_loc[nop] = operand; 1605 /* Do not return false here as the MEM_P (reg) will be processed 1606 later in this function. */ 1607 } 1608 else if (REG_P (reg) && REGNO (reg) < FIRST_PSEUDO_REGISTER) 1609 { 1610 alter_subreg (curr_id->operand_loc[nop], false); 1611 return true; 1612 } 1613 else if (CONSTANT_P (reg)) 1614 { 1615 /* Try to simplify subreg of constant. It is usually result of 1616 equivalence substitution. */ 1617 if (innermode == VOIDmode 1618 && (innermode = original_subreg_reg_mode[nop]) == VOIDmode) 1619 innermode = curr_static_id->operand[nop].mode; 1620 if ((new_reg = simplify_subreg (mode, reg, innermode, 1621 SUBREG_BYTE (operand))) != NULL_RTX) 1622 { 1623 *curr_id->operand_loc[nop] = new_reg; 1624 return true; 1625 } 1626 } 1627 /* Put constant into memory when we have mixed modes. It generates 1628 a better code in most cases as it does not need a secondary 1629 reload memory. It also prevents LRA looping when LRA is using 1630 secondary reload memory again and again. */ 1631 if (CONSTANT_P (reg) && CONST_POOL_OK_P (reg_mode, reg) 1632 && SCALAR_INT_MODE_P (reg_mode) != SCALAR_INT_MODE_P (mode)) 1633 { 1634 SUBREG_REG (operand) = force_const_mem (reg_mode, reg); 1635 alter_subreg (curr_id->operand_loc[nop], false); 1636 return true; 1637 } 1638 /* Force a reload of the SUBREG_REG if this is a constant or PLUS or 1639 if there may be a problem accessing OPERAND in the outer 1640 mode. */ 1641 if ((REG_P (reg) 1642 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 1643 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 1644 /* Don't reload paradoxical subregs because we could be looping 1645 having repeatedly final regno out of hard regs range. */ 1646 && (hard_regno_nregs (hard_regno, innermode) 1647 >= hard_regno_nregs (hard_regno, mode)) 1648 && simplify_subreg_regno (hard_regno, innermode, 1649 SUBREG_BYTE (operand), mode) < 0 1650 /* Don't reload subreg for matching reload. It is actually 1651 valid subreg in LRA. */ 1652 && ! LRA_SUBREG_P (operand)) 1653 || CONSTANT_P (reg) || GET_CODE (reg) == PLUS || MEM_P (reg)) 1654 { 1655 enum reg_class rclass; 1656 1657 if (REG_P (reg)) 1658 /* There is a big probability that we will get the same class 1659 for the new pseudo and we will get the same insn which 1660 means infinite looping. So spill the new pseudo. */ 1661 rclass = NO_REGS; 1662 else 1663 /* The class will be defined later in curr_insn_transform. */ 1664 rclass 1665 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1666 1667 if (get_reload_reg (curr_static_id->operand[nop].type, reg_mode, reg, 1668 rclass, TRUE, "subreg reg", &new_reg)) 1669 { 1670 bool insert_before, insert_after; 1671 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); 1672 1673 insert_before = (type != OP_OUT 1674 || read_modify_subreg_p (operand)); 1675 insert_after = (type != OP_IN); 1676 insert_move_for_subreg (insert_before ? &before : NULL, 1677 insert_after ? &after : NULL, 1678 reg, new_reg); 1679 } 1680 SUBREG_REG (operand) = new_reg; 1681 lra_process_new_insns (curr_insn, before, after, 1682 "Inserting subreg reload"); 1683 return true; 1684 } 1685 /* Force a reload for a paradoxical subreg. For paradoxical subreg, 1686 IRA allocates hardreg to the inner pseudo reg according to its mode 1687 instead of the outermode, so the size of the hardreg may not be enough 1688 to contain the outermode operand, in that case we may need to insert 1689 reload for the reg. For the following two types of paradoxical subreg, 1690 we need to insert reload: 1691 1. If the op_type is OP_IN, and the hardreg could not be paired with 1692 other hardreg to contain the outermode operand 1693 (checked by in_hard_reg_set_p), we need to insert the reload. 1694 2. If the op_type is OP_OUT or OP_INOUT. 1695 1696 Here is a paradoxical subreg example showing how the reload is generated: 1697 1698 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) 1699 (subreg:TI (reg:DI 107 [ __comp ]) 0)) {*movti_internal_rex64} 1700 1701 In IRA, reg107 is allocated to a DImode hardreg. We use x86-64 as example 1702 here, if reg107 is assigned to hardreg R15, because R15 is the last 1703 hardreg, compiler cannot find another hardreg to pair with R15 to 1704 contain TImode data. So we insert a TImode reload reg180 for it. 1705 After reload is inserted: 1706 1707 (insn 283 0 0 (set (subreg:DI (reg:TI 180 [orig:107 __comp ] [107]) 0) 1708 (reg:DI 107 [ __comp ])) -1 1709 (insn 5 4 7 2 (set (reg:TI 106 [ __comp ]) 1710 (subreg:TI (reg:TI 180 [orig:107 __comp ] [107]) 0)) {*movti_internal_rex64} 1711 1712 Two reload hard registers will be allocated to reg180 to save TImode data 1713 in LRA_assign. 1714 1715 For LRA pseudos this should normally be handled by the biggest_mode 1716 mechanism. However, it's possible for new uses of an LRA pseudo 1717 to be introduced after we've allocated it, such as when undoing 1718 inheritance, and the allocated register might not then be appropriate 1719 for the new uses. */ 1720 else if (REG_P (reg) 1721 && REGNO (reg) >= FIRST_PSEUDO_REGISTER 1722 && (hard_regno = lra_get_regno_hard_regno (REGNO (reg))) >= 0 1723 && (hard_regno_nregs (hard_regno, innermode) 1724 < hard_regno_nregs (hard_regno, mode)) 1725 && (regclass = lra_get_allocno_class (REGNO (reg))) 1726 && (type != OP_IN 1727 || !in_hard_reg_set_p (reg_class_contents[regclass], 1728 mode, hard_regno) 1729 || overlaps_hard_reg_set_p (lra_no_alloc_regs, 1730 mode, hard_regno))) 1731 { 1732 /* The class will be defined later in curr_insn_transform. */ 1733 enum reg_class rclass 1734 = (enum reg_class) targetm.preferred_reload_class (reg, ALL_REGS); 1735 1736 if (get_reload_reg (curr_static_id->operand[nop].type, mode, reg, 1737 rclass, TRUE, "paradoxical subreg", &new_reg)) 1738 { 1739 rtx subreg; 1740 bool insert_before, insert_after; 1741 1742 PUT_MODE (new_reg, mode); 1743 subreg = gen_lowpart_SUBREG (innermode, new_reg); 1744 bitmap_set_bit (&lra_subreg_reload_pseudos, REGNO (new_reg)); 1745 1746 insert_before = (type != OP_OUT); 1747 insert_after = (type != OP_IN); 1748 insert_move_for_subreg (insert_before ? &before : NULL, 1749 insert_after ? &after : NULL, 1750 reg, subreg); 1751 } 1752 SUBREG_REG (operand) = new_reg; 1753 lra_process_new_insns (curr_insn, before, after, 1754 "Inserting paradoxical subreg reload"); 1755 return true; 1756 } 1757 return false; 1758 } 1759 1760 /* Return TRUE if X refers for a hard register from SET. */ 1761 static bool 1762 uses_hard_regs_p (rtx x, HARD_REG_SET set) 1763 { 1764 int i, j, x_hard_regno; 1765 machine_mode mode; 1766 const char *fmt; 1767 enum rtx_code code; 1768 1769 if (x == NULL_RTX) 1770 return false; 1771 code = GET_CODE (x); 1772 mode = GET_MODE (x); 1773 1774 if (code == SUBREG) 1775 { 1776 /* For all SUBREGs we want to check whether the full multi-register 1777 overlaps the set. For normal SUBREGs this means 'get_hard_regno' of 1778 the inner register, for paradoxical SUBREGs this means the 1779 'get_hard_regno' of the full SUBREG and for complete SUBREGs either is 1780 fine. Use the wider mode for all cases. */ 1781 rtx subreg = SUBREG_REG (x); 1782 mode = wider_subreg_mode (x); 1783 if (mode == GET_MODE (subreg)) 1784 { 1785 x = subreg; 1786 code = GET_CODE (x); 1787 } 1788 } 1789 1790 if (REG_P (x) || SUBREG_P (x)) 1791 { 1792 x_hard_regno = get_hard_regno (x, true); 1793 return (x_hard_regno >= 0 1794 && overlaps_hard_reg_set_p (set, mode, x_hard_regno)); 1795 } 1796 if (MEM_P (x)) 1797 { 1798 struct address_info ad; 1799 1800 decompose_mem_address (&ad, x); 1801 if (ad.base_term != NULL && uses_hard_regs_p (*ad.base_term, set)) 1802 return true; 1803 if (ad.index_term != NULL && uses_hard_regs_p (*ad.index_term, set)) 1804 return true; 1805 } 1806 fmt = GET_RTX_FORMAT (code); 1807 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 1808 { 1809 if (fmt[i] == 'e') 1810 { 1811 if (uses_hard_regs_p (XEXP (x, i), set)) 1812 return true; 1813 } 1814 else if (fmt[i] == 'E') 1815 { 1816 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 1817 if (uses_hard_regs_p (XVECEXP (x, i, j), set)) 1818 return true; 1819 } 1820 } 1821 return false; 1822 } 1823 1824 /* Return true if OP is a spilled pseudo. */ 1825 static inline bool 1826 spilled_pseudo_p (rtx op) 1827 { 1828 return (REG_P (op) 1829 && REGNO (op) >= FIRST_PSEUDO_REGISTER && in_mem_p (REGNO (op))); 1830 } 1831 1832 /* Return true if X is a general constant. */ 1833 static inline bool 1834 general_constant_p (rtx x) 1835 { 1836 return CONSTANT_P (x) && (! flag_pic || LEGITIMATE_PIC_OPERAND_P (x)); 1837 } 1838 1839 static bool 1840 reg_in_class_p (rtx reg, enum reg_class cl) 1841 { 1842 if (cl == NO_REGS) 1843 return get_reg_class (REGNO (reg)) == NO_REGS; 1844 return in_class_p (reg, cl, NULL); 1845 } 1846 1847 /* Return true if SET of RCLASS contains no hard regs which can be 1848 used in MODE. */ 1849 static bool 1850 prohibited_class_reg_set_mode_p (enum reg_class rclass, 1851 HARD_REG_SET &set, 1852 machine_mode mode) 1853 { 1854 HARD_REG_SET temp; 1855 1856 lra_assert (hard_reg_set_subset_p (reg_class_contents[rclass], set)); 1857 COPY_HARD_REG_SET (temp, set); 1858 AND_COMPL_HARD_REG_SET (temp, lra_no_alloc_regs); 1859 return (hard_reg_set_subset_p 1860 (temp, ira_prohibited_class_mode_regs[rclass][mode])); 1861 } 1862 1863 1864 /* Used to check validity info about small class input operands. It 1865 should be incremented at start of processing an insn 1866 alternative. */ 1867 static unsigned int curr_small_class_check = 0; 1868 1869 /* Update number of used inputs of class OP_CLASS for operand NOP. 1870 Return true if we have more such class operands than the number of 1871 available regs. */ 1872 static bool 1873 update_and_check_small_class_inputs (int nop, enum reg_class op_class) 1874 { 1875 static unsigned int small_class_check[LIM_REG_CLASSES]; 1876 static int small_class_input_nums[LIM_REG_CLASSES]; 1877 1878 if (SMALL_REGISTER_CLASS_P (op_class) 1879 /* We are interesting in classes became small because of fixing 1880 some hard regs, e.g. by an user through GCC options. */ 1881 && hard_reg_set_intersect_p (reg_class_contents[op_class], 1882 ira_no_alloc_regs) 1883 && (curr_static_id->operand[nop].type != OP_OUT 1884 || curr_static_id->operand[nop].early_clobber)) 1885 { 1886 if (small_class_check[op_class] == curr_small_class_check) 1887 small_class_input_nums[op_class]++; 1888 else 1889 { 1890 small_class_check[op_class] = curr_small_class_check; 1891 small_class_input_nums[op_class] = 1; 1892 } 1893 if (small_class_input_nums[op_class] > ira_class_hard_regs_num[op_class]) 1894 return true; 1895 } 1896 return false; 1897 } 1898 1899 /* Major function to choose the current insn alternative and what 1900 operands should be reloaded and how. If ONLY_ALTERNATIVE is not 1901 negative we should consider only this alternative. Return false if 1902 we cannot choose the alternative or find how to reload the 1903 operands. */ 1904 static bool 1905 process_alt_operands (int only_alternative) 1906 { 1907 bool ok_p = false; 1908 int nop, overall, nalt; 1909 int n_alternatives = curr_static_id->n_alternatives; 1910 int n_operands = curr_static_id->n_operands; 1911 /* LOSERS counts the operands that don't fit this alternative and 1912 would require loading. */ 1913 int losers; 1914 int addr_losers; 1915 /* REJECT is a count of how undesirable this alternative says it is 1916 if any reloading is required. If the alternative matches exactly 1917 then REJECT is ignored, but otherwise it gets this much counted 1918 against it in addition to the reloading needed. */ 1919 int reject; 1920 /* This is defined by '!' or '?' alternative constraint and added to 1921 reject. But in some cases it can be ignored. */ 1922 int static_reject; 1923 int op_reject; 1924 /* The number of elements in the following array. */ 1925 int early_clobbered_regs_num; 1926 /* Numbers of operands which are early clobber registers. */ 1927 int early_clobbered_nops[MAX_RECOG_OPERANDS]; 1928 enum reg_class curr_alt[MAX_RECOG_OPERANDS]; 1929 HARD_REG_SET curr_alt_set[MAX_RECOG_OPERANDS]; 1930 bool curr_alt_match_win[MAX_RECOG_OPERANDS]; 1931 bool curr_alt_win[MAX_RECOG_OPERANDS]; 1932 bool curr_alt_offmemok[MAX_RECOG_OPERANDS]; 1933 int curr_alt_matches[MAX_RECOG_OPERANDS]; 1934 /* The number of elements in the following array. */ 1935 int curr_alt_dont_inherit_ops_num; 1936 /* Numbers of operands whose reload pseudos should not be inherited. */ 1937 int curr_alt_dont_inherit_ops[MAX_RECOG_OPERANDS]; 1938 rtx op; 1939 /* The register when the operand is a subreg of register, otherwise the 1940 operand itself. */ 1941 rtx no_subreg_reg_operand[MAX_RECOG_OPERANDS]; 1942 /* The register if the operand is a register or subreg of register, 1943 otherwise NULL. */ 1944 rtx operand_reg[MAX_RECOG_OPERANDS]; 1945 int hard_regno[MAX_RECOG_OPERANDS]; 1946 machine_mode biggest_mode[MAX_RECOG_OPERANDS]; 1947 int reload_nregs, reload_sum; 1948 bool costly_p; 1949 enum reg_class cl; 1950 1951 /* Calculate some data common for all alternatives to speed up the 1952 function. */ 1953 for (nop = 0; nop < n_operands; nop++) 1954 { 1955 rtx reg; 1956 1957 op = no_subreg_reg_operand[nop] = *curr_id->operand_loc[nop]; 1958 /* The real hard regno of the operand after the allocation. */ 1959 hard_regno[nop] = get_hard_regno (op, true); 1960 1961 operand_reg[nop] = reg = op; 1962 biggest_mode[nop] = GET_MODE (op); 1963 if (GET_CODE (op) == SUBREG) 1964 { 1965 biggest_mode[nop] = wider_subreg_mode (op); 1966 operand_reg[nop] = reg = SUBREG_REG (op); 1967 } 1968 if (! REG_P (reg)) 1969 operand_reg[nop] = NULL_RTX; 1970 else if (REGNO (reg) >= FIRST_PSEUDO_REGISTER 1971 || ((int) REGNO (reg) 1972 == lra_get_elimination_hard_regno (REGNO (reg)))) 1973 no_subreg_reg_operand[nop] = reg; 1974 else 1975 operand_reg[nop] = no_subreg_reg_operand[nop] 1976 /* Just use natural mode for elimination result. It should 1977 be enough for extra constraints hooks. */ 1978 = regno_reg_rtx[hard_regno[nop]]; 1979 } 1980 1981 /* The constraints are made of several alternatives. Each operand's 1982 constraint looks like foo,bar,... with commas separating the 1983 alternatives. The first alternatives for all operands go 1984 together, the second alternatives go together, etc. 1985 1986 First loop over alternatives. */ 1987 alternative_mask preferred = curr_id->preferred_alternatives; 1988 if (only_alternative >= 0) 1989 preferred &= ALTERNATIVE_BIT (only_alternative); 1990 1991 for (nalt = 0; nalt < n_alternatives; nalt++) 1992 { 1993 /* Loop over operands for one constraint alternative. */ 1994 if (!TEST_BIT (preferred, nalt)) 1995 continue; 1996 1997 bool matching_early_clobber[MAX_RECOG_OPERANDS]; 1998 curr_small_class_check++; 1999 overall = losers = addr_losers = 0; 2000 static_reject = reject = reload_nregs = reload_sum = 0; 2001 for (nop = 0; nop < n_operands; nop++) 2002 { 2003 int inc = (curr_static_id 2004 ->operand_alternative[nalt * n_operands + nop].reject); 2005 if (lra_dump_file != NULL && inc != 0) 2006 fprintf (lra_dump_file, 2007 " Staticly defined alt reject+=%d\n", inc); 2008 static_reject += inc; 2009 matching_early_clobber[nop] = 0; 2010 } 2011 reject += static_reject; 2012 early_clobbered_regs_num = 0; 2013 2014 for (nop = 0; nop < n_operands; nop++) 2015 { 2016 const char *p; 2017 char *end; 2018 int len, c, m, i, opalt_num, this_alternative_matches; 2019 bool win, did_match, offmemok, early_clobber_p; 2020 /* false => this operand can be reloaded somehow for this 2021 alternative. */ 2022 bool badop; 2023 /* true => this operand can be reloaded if the alternative 2024 allows regs. */ 2025 bool winreg; 2026 /* True if a constant forced into memory would be OK for 2027 this operand. */ 2028 bool constmemok; 2029 enum reg_class this_alternative, this_costly_alternative; 2030 HARD_REG_SET this_alternative_set, this_costly_alternative_set; 2031 bool this_alternative_match_win, this_alternative_win; 2032 bool this_alternative_offmemok; 2033 bool scratch_p; 2034 machine_mode mode; 2035 enum constraint_num cn; 2036 2037 opalt_num = nalt * n_operands + nop; 2038 if (curr_static_id->operand_alternative[opalt_num].anything_ok) 2039 { 2040 /* Fast track for no constraints at all. */ 2041 curr_alt[nop] = NO_REGS; 2042 CLEAR_HARD_REG_SET (curr_alt_set[nop]); 2043 curr_alt_win[nop] = true; 2044 curr_alt_match_win[nop] = false; 2045 curr_alt_offmemok[nop] = false; 2046 curr_alt_matches[nop] = -1; 2047 continue; 2048 } 2049 2050 op = no_subreg_reg_operand[nop]; 2051 mode = curr_operand_mode[nop]; 2052 2053 win = did_match = winreg = offmemok = constmemok = false; 2054 badop = true; 2055 2056 early_clobber_p = false; 2057 p = curr_static_id->operand_alternative[opalt_num].constraint; 2058 2059 this_costly_alternative = this_alternative = NO_REGS; 2060 /* We update set of possible hard regs besides its class 2061 because reg class might be inaccurate. For example, 2062 union of LO_REGS (l), HI_REGS(h), and STACK_REG(k) in ARM 2063 is translated in HI_REGS because classes are merged by 2064 pairs and there is no accurate intermediate class. */ 2065 CLEAR_HARD_REG_SET (this_alternative_set); 2066 CLEAR_HARD_REG_SET (this_costly_alternative_set); 2067 this_alternative_win = false; 2068 this_alternative_match_win = false; 2069 this_alternative_offmemok = false; 2070 this_alternative_matches = -1; 2071 2072 /* An empty constraint should be excluded by the fast 2073 track. */ 2074 lra_assert (*p != 0 && *p != ','); 2075 2076 op_reject = 0; 2077 /* Scan this alternative's specs for this operand; set WIN 2078 if the operand fits any letter in this alternative. 2079 Otherwise, clear BADOP if this operand could fit some 2080 letter after reloads, or set WINREG if this operand could 2081 fit after reloads provided the constraint allows some 2082 registers. */ 2083 costly_p = false; 2084 do 2085 { 2086 switch ((c = *p, len = CONSTRAINT_LEN (c, p)), c) 2087 { 2088 case '\0': 2089 len = 0; 2090 break; 2091 case ',': 2092 c = '\0'; 2093 break; 2094 2095 case '&': 2096 early_clobber_p = true; 2097 break; 2098 2099 case '$': 2100 op_reject += LRA_MAX_REJECT; 2101 break; 2102 case '^': 2103 op_reject += LRA_LOSER_COST_FACTOR; 2104 break; 2105 2106 case '#': 2107 /* Ignore rest of this alternative. */ 2108 c = '\0'; 2109 break; 2110 2111 case '0': case '1': case '2': case '3': case '4': 2112 case '5': case '6': case '7': case '8': case '9': 2113 { 2114 int m_hregno; 2115 bool match_p; 2116 2117 m = strtoul (p, &end, 10); 2118 p = end; 2119 len = 0; 2120 lra_assert (nop > m); 2121 2122 /* Reject matches if we don't know which operand is 2123 bigger. This situation would arguably be a bug in 2124 an .md pattern, but could also occur in a user asm. */ 2125 if (!ordered_p (GET_MODE_SIZE (biggest_mode[m]), 2126 GET_MODE_SIZE (biggest_mode[nop]))) 2127 break; 2128 2129 /* Don't match wrong asm insn operands for proper 2130 diagnostic later. */ 2131 if (INSN_CODE (curr_insn) < 0 2132 && (curr_operand_mode[m] == BLKmode 2133 || curr_operand_mode[nop] == BLKmode) 2134 && curr_operand_mode[m] != curr_operand_mode[nop]) 2135 break; 2136 2137 m_hregno = get_hard_regno (*curr_id->operand_loc[m], false); 2138 /* We are supposed to match a previous operand. 2139 If we do, we win if that one did. If we do 2140 not, count both of the operands as losers. 2141 (This is too conservative, since most of the 2142 time only a single reload insn will be needed 2143 to make the two operands win. As a result, 2144 this alternative may be rejected when it is 2145 actually desirable.) */ 2146 match_p = false; 2147 if (operands_match_p (*curr_id->operand_loc[nop], 2148 *curr_id->operand_loc[m], m_hregno)) 2149 { 2150 /* We should reject matching of an early 2151 clobber operand if the matching operand is 2152 not dying in the insn. */ 2153 if (! curr_static_id->operand[m].early_clobber 2154 || operand_reg[nop] == NULL_RTX 2155 || (find_regno_note (curr_insn, REG_DEAD, 2156 REGNO (op)) 2157 || REGNO (op) == REGNO (operand_reg[m]))) 2158 match_p = true; 2159 } 2160 if (match_p) 2161 { 2162 /* If we are matching a non-offsettable 2163 address where an offsettable address was 2164 expected, then we must reject this 2165 combination, because we can't reload 2166 it. */ 2167 if (curr_alt_offmemok[m] 2168 && MEM_P (*curr_id->operand_loc[m]) 2169 && curr_alt[m] == NO_REGS && ! curr_alt_win[m]) 2170 continue; 2171 } 2172 else 2173 { 2174 /* Operands don't match. If the operands are 2175 different user defined explicit hard registers, 2176 then we cannot make them match. */ 2177 if ((REG_P (*curr_id->operand_loc[nop]) 2178 || SUBREG_P (*curr_id->operand_loc[nop])) 2179 && (REG_P (*curr_id->operand_loc[m]) 2180 || SUBREG_P (*curr_id->operand_loc[m]))) 2181 { 2182 rtx nop_reg = *curr_id->operand_loc[nop]; 2183 if (SUBREG_P (nop_reg)) 2184 nop_reg = SUBREG_REG (nop_reg); 2185 rtx m_reg = *curr_id->operand_loc[m]; 2186 if (SUBREG_P (m_reg)) 2187 m_reg = SUBREG_REG (m_reg); 2188 2189 if (REG_P (nop_reg) 2190 && HARD_REGISTER_P (nop_reg) 2191 && REG_USERVAR_P (nop_reg) 2192 && REG_P (m_reg) 2193 && HARD_REGISTER_P (m_reg) 2194 && REG_USERVAR_P (m_reg)) 2195 break; 2196 } 2197 2198 /* Both operands must allow a reload register, 2199 otherwise we cannot make them match. */ 2200 if (curr_alt[m] == NO_REGS) 2201 break; 2202 /* Retroactively mark the operand we had to 2203 match as a loser, if it wasn't already and 2204 it wasn't matched to a register constraint 2205 (e.g it might be matched by memory). */ 2206 if (curr_alt_win[m] 2207 && (operand_reg[m] == NULL_RTX 2208 || hard_regno[m] < 0)) 2209 { 2210 losers++; 2211 reload_nregs 2212 += (ira_reg_class_max_nregs[curr_alt[m]] 2213 [GET_MODE (*curr_id->operand_loc[m])]); 2214 } 2215 2216 /* Prefer matching earlyclobber alternative as 2217 it results in less hard regs required for 2218 the insn than a non-matching earlyclobber 2219 alternative. */ 2220 if (curr_static_id->operand[m].early_clobber) 2221 { 2222 if (lra_dump_file != NULL) 2223 fprintf 2224 (lra_dump_file, 2225 " %d Matching earlyclobber alt:" 2226 " reject--\n", 2227 nop); 2228 if (!matching_early_clobber[m]) 2229 { 2230 reject--; 2231 matching_early_clobber[m] = 1; 2232 } 2233 } 2234 /* Otherwise we prefer no matching 2235 alternatives because it gives more freedom 2236 in RA. */ 2237 else if (operand_reg[nop] == NULL_RTX 2238 || (find_regno_note (curr_insn, REG_DEAD, 2239 REGNO (operand_reg[nop])) 2240 == NULL_RTX)) 2241 { 2242 if (lra_dump_file != NULL) 2243 fprintf 2244 (lra_dump_file, 2245 " %d Matching alt: reject+=2\n", 2246 nop); 2247 reject += 2; 2248 } 2249 } 2250 /* If we have to reload this operand and some 2251 previous operand also had to match the same 2252 thing as this operand, we don't know how to do 2253 that. */ 2254 if (!match_p || !curr_alt_win[m]) 2255 { 2256 for (i = 0; i < nop; i++) 2257 if (curr_alt_matches[i] == m) 2258 break; 2259 if (i < nop) 2260 break; 2261 } 2262 else 2263 did_match = true; 2264 2265 this_alternative_matches = m; 2266 /* This can be fixed with reloads if the operand 2267 we are supposed to match can be fixed with 2268 reloads. */ 2269 badop = false; 2270 this_alternative = curr_alt[m]; 2271 COPY_HARD_REG_SET (this_alternative_set, curr_alt_set[m]); 2272 winreg = this_alternative != NO_REGS; 2273 break; 2274 } 2275 2276 case 'g': 2277 if (MEM_P (op) 2278 || general_constant_p (op) 2279 || spilled_pseudo_p (op)) 2280 win = true; 2281 cl = GENERAL_REGS; 2282 goto reg; 2283 2284 default: 2285 cn = lookup_constraint (p); 2286 switch (get_constraint_type (cn)) 2287 { 2288 case CT_REGISTER: 2289 cl = reg_class_for_constraint (cn); 2290 if (cl != NO_REGS) 2291 goto reg; 2292 break; 2293 2294 case CT_CONST_INT: 2295 if (CONST_INT_P (op) 2296 && insn_const_int_ok_for_constraint (INTVAL (op), cn)) 2297 win = true; 2298 break; 2299 2300 case CT_MEMORY: 2301 if (MEM_P (op) 2302 && satisfies_memory_constraint_p (op, cn)) 2303 win = true; 2304 else if (spilled_pseudo_p (op)) 2305 win = true; 2306 2307 /* If we didn't already win, we can reload constants 2308 via force_const_mem or put the pseudo value into 2309 memory, or make other memory by reloading the 2310 address like for 'o'. */ 2311 if (CONST_POOL_OK_P (mode, op) 2312 || MEM_P (op) || REG_P (op) 2313 /* We can restore the equiv insn by a 2314 reload. */ 2315 || equiv_substition_p[nop]) 2316 badop = false; 2317 constmemok = true; 2318 offmemok = true; 2319 break; 2320 2321 case CT_ADDRESS: 2322 /* An asm operand with an address constraint 2323 that doesn't satisfy address_operand has 2324 is_address cleared, so that we don't try to 2325 make a non-address fit. */ 2326 if (!curr_static_id->operand[nop].is_address) 2327 break; 2328 /* If we didn't already win, we can reload the address 2329 into a base register. */ 2330 if (satisfies_address_constraint_p (op, cn)) 2331 win = true; 2332 cl = base_reg_class (VOIDmode, ADDR_SPACE_GENERIC, 2333 ADDRESS, SCRATCH); 2334 badop = false; 2335 goto reg; 2336 2337 case CT_FIXED_FORM: 2338 if (constraint_satisfied_p (op, cn)) 2339 win = true; 2340 break; 2341 2342 case CT_SPECIAL_MEMORY: 2343 if (MEM_P (op) 2344 && satisfies_memory_constraint_p (op, cn)) 2345 win = true; 2346 else if (spilled_pseudo_p (op)) 2347 win = true; 2348 break; 2349 } 2350 break; 2351 2352 reg: 2353 if (mode == BLKmode) 2354 break; 2355 this_alternative = reg_class_subunion[this_alternative][cl]; 2356 IOR_HARD_REG_SET (this_alternative_set, 2357 reg_class_contents[cl]); 2358 if (costly_p) 2359 { 2360 this_costly_alternative 2361 = reg_class_subunion[this_costly_alternative][cl]; 2362 IOR_HARD_REG_SET (this_costly_alternative_set, 2363 reg_class_contents[cl]); 2364 } 2365 winreg = true; 2366 if (REG_P (op)) 2367 { 2368 if (hard_regno[nop] >= 0 2369 && in_hard_reg_set_p (this_alternative_set, 2370 mode, hard_regno[nop])) 2371 win = true; 2372 else if (hard_regno[nop] < 0 2373 && in_class_p (op, this_alternative, NULL)) 2374 win = true; 2375 } 2376 break; 2377 } 2378 if (c != ' ' && c != '\t') 2379 costly_p = c == '*'; 2380 } 2381 while ((p += len), c); 2382 2383 scratch_p = (operand_reg[nop] != NULL_RTX 2384 && lra_former_scratch_p (REGNO (operand_reg[nop]))); 2385 /* Record which operands fit this alternative. */ 2386 if (win) 2387 { 2388 this_alternative_win = true; 2389 if (operand_reg[nop] != NULL_RTX) 2390 { 2391 if (hard_regno[nop] >= 0) 2392 { 2393 if (in_hard_reg_set_p (this_costly_alternative_set, 2394 mode, hard_regno[nop])) 2395 { 2396 if (lra_dump_file != NULL) 2397 fprintf (lra_dump_file, 2398 " %d Costly set: reject++\n", 2399 nop); 2400 reject++; 2401 } 2402 } 2403 else 2404 { 2405 /* Prefer won reg to spilled pseudo under other 2406 equal conditions for possibe inheritance. */ 2407 if (! scratch_p) 2408 { 2409 if (lra_dump_file != NULL) 2410 fprintf 2411 (lra_dump_file, 2412 " %d Non pseudo reload: reject++\n", 2413 nop); 2414 reject++; 2415 } 2416 if (in_class_p (operand_reg[nop], 2417 this_costly_alternative, NULL)) 2418 { 2419 if (lra_dump_file != NULL) 2420 fprintf 2421 (lra_dump_file, 2422 " %d Non pseudo costly reload:" 2423 " reject++\n", 2424 nop); 2425 reject++; 2426 } 2427 } 2428 /* We simulate the behavior of old reload here. 2429 Although scratches need hard registers and it 2430 might result in spilling other pseudos, no reload 2431 insns are generated for the scratches. So it 2432 might cost something but probably less than old 2433 reload pass believes. */ 2434 if (scratch_p) 2435 { 2436 if (lra_dump_file != NULL) 2437 fprintf (lra_dump_file, 2438 " %d Scratch win: reject+=2\n", 2439 nop); 2440 reject += 2; 2441 } 2442 } 2443 } 2444 else if (did_match) 2445 this_alternative_match_win = true; 2446 else 2447 { 2448 int const_to_mem = 0; 2449 bool no_regs_p; 2450 2451 reject += op_reject; 2452 /* Never do output reload of stack pointer. It makes 2453 impossible to do elimination when SP is changed in 2454 RTL. */ 2455 if (op == stack_pointer_rtx && ! frame_pointer_needed 2456 && curr_static_id->operand[nop].type != OP_IN) 2457 goto fail; 2458 2459 /* If this alternative asks for a specific reg class, see if there 2460 is at least one allocatable register in that class. */ 2461 no_regs_p 2462 = (this_alternative == NO_REGS 2463 || (hard_reg_set_subset_p 2464 (reg_class_contents[this_alternative], 2465 lra_no_alloc_regs))); 2466 2467 /* For asms, verify that the class for this alternative is possible 2468 for the mode that is specified. */ 2469 if (!no_regs_p && INSN_CODE (curr_insn) < 0) 2470 { 2471 int i; 2472 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 2473 if (targetm.hard_regno_mode_ok (i, mode) 2474 && in_hard_reg_set_p (reg_class_contents[this_alternative], 2475 mode, i)) 2476 break; 2477 if (i == FIRST_PSEUDO_REGISTER) 2478 winreg = false; 2479 } 2480 2481 /* If this operand accepts a register, and if the 2482 register class has at least one allocatable register, 2483 then this operand can be reloaded. */ 2484 if (winreg && !no_regs_p) 2485 badop = false; 2486 2487 if (badop) 2488 { 2489 if (lra_dump_file != NULL) 2490 fprintf (lra_dump_file, 2491 " alt=%d: Bad operand -- refuse\n", 2492 nalt); 2493 goto fail; 2494 } 2495 2496 if (this_alternative != NO_REGS) 2497 { 2498 HARD_REG_SET available_regs; 2499 2500 COPY_HARD_REG_SET (available_regs, 2501 reg_class_contents[this_alternative]); 2502 AND_COMPL_HARD_REG_SET 2503 (available_regs, 2504 ira_prohibited_class_mode_regs[this_alternative][mode]); 2505 AND_COMPL_HARD_REG_SET (available_regs, lra_no_alloc_regs); 2506 if (hard_reg_set_empty_p (available_regs)) 2507 { 2508 /* There are no hard regs holding a value of given 2509 mode. */ 2510 if (offmemok) 2511 { 2512 this_alternative = NO_REGS; 2513 if (lra_dump_file != NULL) 2514 fprintf (lra_dump_file, 2515 " %d Using memory because of" 2516 " a bad mode: reject+=2\n", 2517 nop); 2518 reject += 2; 2519 } 2520 else 2521 { 2522 if (lra_dump_file != NULL) 2523 fprintf (lra_dump_file, 2524 " alt=%d: Wrong mode -- refuse\n", 2525 nalt); 2526 goto fail; 2527 } 2528 } 2529 } 2530 2531 /* If not assigned pseudo has a class which a subset of 2532 required reg class, it is a less costly alternative 2533 as the pseudo still can get a hard reg of necessary 2534 class. */ 2535 if (! no_regs_p && REG_P (op) && hard_regno[nop] < 0 2536 && (cl = get_reg_class (REGNO (op))) != NO_REGS 2537 && ira_class_subset_p[this_alternative][cl]) 2538 { 2539 if (lra_dump_file != NULL) 2540 fprintf 2541 (lra_dump_file, 2542 " %d Super set class reg: reject-=3\n", nop); 2543 reject -= 3; 2544 } 2545 2546 this_alternative_offmemok = offmemok; 2547 if (this_costly_alternative != NO_REGS) 2548 { 2549 if (lra_dump_file != NULL) 2550 fprintf (lra_dump_file, 2551 " %d Costly loser: reject++\n", nop); 2552 reject++; 2553 } 2554 /* If the operand is dying, has a matching constraint, 2555 and satisfies constraints of the matched operand 2556 which failed to satisfy the own constraints, most probably 2557 the reload for this operand will be gone. */ 2558 if (this_alternative_matches >= 0 2559 && !curr_alt_win[this_alternative_matches] 2560 && REG_P (op) 2561 && find_regno_note (curr_insn, REG_DEAD, REGNO (op)) 2562 && (hard_regno[nop] >= 0 2563 ? in_hard_reg_set_p (this_alternative_set, 2564 mode, hard_regno[nop]) 2565 : in_class_p (op, this_alternative, NULL))) 2566 { 2567 if (lra_dump_file != NULL) 2568 fprintf 2569 (lra_dump_file, 2570 " %d Dying matched operand reload: reject++\n", 2571 nop); 2572 reject++; 2573 } 2574 else 2575 { 2576 /* Strict_low_part requires to reload the register 2577 not the sub-register. In this case we should 2578 check that a final reload hard reg can hold the 2579 value mode. */ 2580 if (curr_static_id->operand[nop].strict_low 2581 && REG_P (op) 2582 && hard_regno[nop] < 0 2583 && GET_CODE (*curr_id->operand_loc[nop]) == SUBREG 2584 && ira_class_hard_regs_num[this_alternative] > 0 2585 && (!targetm.hard_regno_mode_ok 2586 (ira_class_hard_regs[this_alternative][0], 2587 GET_MODE (*curr_id->operand_loc[nop])))) 2588 { 2589 if (lra_dump_file != NULL) 2590 fprintf 2591 (lra_dump_file, 2592 " alt=%d: Strict low subreg reload -- refuse\n", 2593 nalt); 2594 goto fail; 2595 } 2596 losers++; 2597 } 2598 if (operand_reg[nop] != NULL_RTX 2599 /* Output operands and matched input operands are 2600 not inherited. The following conditions do not 2601 exactly describe the previous statement but they 2602 are pretty close. */ 2603 && curr_static_id->operand[nop].type != OP_OUT 2604 && (this_alternative_matches < 0 2605 || curr_static_id->operand[nop].type != OP_IN)) 2606 { 2607 int last_reload = (lra_reg_info[ORIGINAL_REGNO 2608 (operand_reg[nop])] 2609 .last_reload); 2610 2611 /* The value of reload_sum has sense only if we 2612 process insns in their order. It happens only on 2613 the first constraints sub-pass when we do most of 2614 reload work. */ 2615 if (lra_constraint_iter == 1 && last_reload > bb_reload_num) 2616 reload_sum += last_reload - bb_reload_num; 2617 } 2618 /* If this is a constant that is reloaded into the 2619 desired class by copying it to memory first, count 2620 that as another reload. This is consistent with 2621 other code and is required to avoid choosing another 2622 alternative when the constant is moved into memory. 2623 Note that the test here is precisely the same as in 2624 the code below that calls force_const_mem. */ 2625 if (CONST_POOL_OK_P (mode, op) 2626 && ((targetm.preferred_reload_class 2627 (op, this_alternative) == NO_REGS) 2628 || no_input_reloads_p)) 2629 { 2630 const_to_mem = 1; 2631 if (! no_regs_p) 2632 losers++; 2633 } 2634 2635 /* Alternative loses if it requires a type of reload not 2636 permitted for this insn. We can always reload 2637 objects with a REG_UNUSED note. */ 2638 if ((curr_static_id->operand[nop].type != OP_IN 2639 && no_output_reloads_p 2640 && ! find_reg_note (curr_insn, REG_UNUSED, op)) 2641 || (curr_static_id->operand[nop].type != OP_OUT 2642 && no_input_reloads_p && ! const_to_mem) 2643 || (this_alternative_matches >= 0 2644 && (no_input_reloads_p 2645 || (no_output_reloads_p 2646 && (curr_static_id->operand 2647 [this_alternative_matches].type != OP_IN) 2648 && ! find_reg_note (curr_insn, REG_UNUSED, 2649 no_subreg_reg_operand 2650 [this_alternative_matches]))))) 2651 { 2652 if (lra_dump_file != NULL) 2653 fprintf 2654 (lra_dump_file, 2655 " alt=%d: No input/otput reload -- refuse\n", 2656 nalt); 2657 goto fail; 2658 } 2659 2660 /* Alternative loses if it required class pseudo cannot 2661 hold value of required mode. Such insns can be 2662 described by insn definitions with mode iterators. */ 2663 if (GET_MODE (*curr_id->operand_loc[nop]) != VOIDmode 2664 && ! hard_reg_set_empty_p (this_alternative_set) 2665 /* It is common practice for constraints to use a 2666 class which does not have actually enough regs to 2667 hold the value (e.g. x86 AREG for mode requiring 2668 more one general reg). Therefore we have 2 2669 conditions to check that the reload pseudo cannot 2670 hold the mode value. */ 2671 && (!targetm.hard_regno_mode_ok 2672 (ira_class_hard_regs[this_alternative][0], 2673 GET_MODE (*curr_id->operand_loc[nop]))) 2674 /* The above condition is not enough as the first 2675 reg in ira_class_hard_regs can be not aligned for 2676 multi-words mode values. */ 2677 && (prohibited_class_reg_set_mode_p 2678 (this_alternative, this_alternative_set, 2679 GET_MODE (*curr_id->operand_loc[nop])))) 2680 { 2681 if (lra_dump_file != NULL) 2682 fprintf (lra_dump_file, 2683 " alt=%d: reload pseudo for op %d " 2684 "cannot hold the mode value -- refuse\n", 2685 nalt, nop); 2686 goto fail; 2687 } 2688 2689 /* Check strong discouragement of reload of non-constant 2690 into class THIS_ALTERNATIVE. */ 2691 if (! CONSTANT_P (op) && ! no_regs_p 2692 && (targetm.preferred_reload_class 2693 (op, this_alternative) == NO_REGS 2694 || (curr_static_id->operand[nop].type == OP_OUT 2695 && (targetm.preferred_output_reload_class 2696 (op, this_alternative) == NO_REGS)))) 2697 { 2698 if (lra_dump_file != NULL) 2699 fprintf (lra_dump_file, 2700 " %d Non-prefered reload: reject+=%d\n", 2701 nop, LRA_MAX_REJECT); 2702 reject += LRA_MAX_REJECT; 2703 } 2704 2705 if (! (MEM_P (op) && offmemok) 2706 && ! (const_to_mem && constmemok)) 2707 { 2708 /* We prefer to reload pseudos over reloading other 2709 things, since such reloads may be able to be 2710 eliminated later. So bump REJECT in other cases. 2711 Don't do this in the case where we are forcing a 2712 constant into memory and it will then win since 2713 we don't want to have a different alternative 2714 match then. */ 2715 if (! (REG_P (op) && REGNO (op) >= FIRST_PSEUDO_REGISTER)) 2716 { 2717 if (lra_dump_file != NULL) 2718 fprintf 2719 (lra_dump_file, 2720 " %d Non-pseudo reload: reject+=2\n", 2721 nop); 2722 reject += 2; 2723 } 2724 2725 if (! no_regs_p) 2726 reload_nregs 2727 += ira_reg_class_max_nregs[this_alternative][mode]; 2728 2729 if (SMALL_REGISTER_CLASS_P (this_alternative)) 2730 { 2731 if (lra_dump_file != NULL) 2732 fprintf 2733 (lra_dump_file, 2734 " %d Small class reload: reject+=%d\n", 2735 nop, LRA_LOSER_COST_FACTOR / 2); 2736 reject += LRA_LOSER_COST_FACTOR / 2; 2737 } 2738 } 2739 2740 /* We are trying to spill pseudo into memory. It is 2741 usually more costly than moving to a hard register 2742 although it might takes the same number of 2743 reloads. 2744 2745 Non-pseudo spill may happen also. Suppose a target allows both 2746 register and memory in the operand constraint alternatives, 2747 then it's typical that an eliminable register has a substition 2748 of "base + offset" which can either be reloaded by a simple 2749 "new_reg <= base + offset" which will match the register 2750 constraint, or a similar reg addition followed by further spill 2751 to and reload from memory which will match the memory 2752 constraint, but this memory spill will be much more costly 2753 usually. 2754 2755 Code below increases the reject for both pseudo and non-pseudo 2756 spill. */ 2757 if (no_regs_p 2758 && !(MEM_P (op) && offmemok) 2759 && !(REG_P (op) && hard_regno[nop] < 0)) 2760 { 2761 if (lra_dump_file != NULL) 2762 fprintf 2763 (lra_dump_file, 2764 " %d Spill %spseudo into memory: reject+=3\n", 2765 nop, REG_P (op) ? "" : "Non-"); 2766 reject += 3; 2767 if (VECTOR_MODE_P (mode)) 2768 { 2769 /* Spilling vectors into memory is usually more 2770 costly as they contain big values. */ 2771 if (lra_dump_file != NULL) 2772 fprintf 2773 (lra_dump_file, 2774 " %d Spill vector pseudo: reject+=2\n", 2775 nop); 2776 reject += 2; 2777 } 2778 } 2779 2780 /* When we use an operand requiring memory in given 2781 alternative, the insn should write *and* read the 2782 value to/from memory it is costly in comparison with 2783 an insn alternative which does not use memory 2784 (e.g. register or immediate operand). We exclude 2785 memory operand for such case as we can satisfy the 2786 memory constraints by reloading address. */ 2787 if (no_regs_p && offmemok && !MEM_P (op)) 2788 { 2789 if (lra_dump_file != NULL) 2790 fprintf 2791 (lra_dump_file, 2792 " Using memory insn operand %d: reject+=3\n", 2793 nop); 2794 reject += 3; 2795 } 2796 2797 /* If reload requires moving value through secondary 2798 memory, it will need one more insn at least. */ 2799 if (this_alternative != NO_REGS 2800 && REG_P (op) && (cl = get_reg_class (REGNO (op))) != NO_REGS 2801 && ((curr_static_id->operand[nop].type != OP_OUT 2802 && targetm.secondary_memory_needed (GET_MODE (op), cl, 2803 this_alternative)) 2804 || (curr_static_id->operand[nop].type != OP_IN 2805 && (targetm.secondary_memory_needed 2806 (GET_MODE (op), this_alternative, cl))))) 2807 losers++; 2808 2809 if (MEM_P (op) && offmemok) 2810 addr_losers++; 2811 else 2812 { 2813 /* Input reloads can be inherited more often than 2814 output reloads can be removed, so penalize output 2815 reloads. */ 2816 if (!REG_P (op) || curr_static_id->operand[nop].type != OP_IN) 2817 { 2818 if (lra_dump_file != NULL) 2819 fprintf 2820 (lra_dump_file, 2821 " %d Non input pseudo reload: reject++\n", 2822 nop); 2823 reject++; 2824 } 2825 2826 if (curr_static_id->operand[nop].type == OP_INOUT) 2827 { 2828 if (lra_dump_file != NULL) 2829 fprintf 2830 (lra_dump_file, 2831 " %d Input/Output reload: reject+=%d\n", 2832 nop, LRA_LOSER_COST_FACTOR); 2833 reject += LRA_LOSER_COST_FACTOR; 2834 } 2835 } 2836 } 2837 2838 if (early_clobber_p && ! scratch_p) 2839 { 2840 if (lra_dump_file != NULL) 2841 fprintf (lra_dump_file, 2842 " %d Early clobber: reject++\n", nop); 2843 reject++; 2844 } 2845 /* ??? We check early clobbers after processing all operands 2846 (see loop below) and there we update the costs more. 2847 Should we update the cost (may be approximately) here 2848 because of early clobber register reloads or it is a rare 2849 or non-important thing to be worth to do it. */ 2850 overall = (losers * LRA_LOSER_COST_FACTOR + reject 2851 - (addr_losers == losers ? static_reject : 0)); 2852 if ((best_losers == 0 || losers != 0) && best_overall < overall) 2853 { 2854 if (lra_dump_file != NULL) 2855 fprintf (lra_dump_file, 2856 " alt=%d,overall=%d,losers=%d -- refuse\n", 2857 nalt, overall, losers); 2858 goto fail; 2859 } 2860 2861 if (update_and_check_small_class_inputs (nop, this_alternative)) 2862 { 2863 if (lra_dump_file != NULL) 2864 fprintf (lra_dump_file, 2865 " alt=%d, not enough small class regs -- refuse\n", 2866 nalt); 2867 goto fail; 2868 } 2869 curr_alt[nop] = this_alternative; 2870 COPY_HARD_REG_SET (curr_alt_set[nop], this_alternative_set); 2871 curr_alt_win[nop] = this_alternative_win; 2872 curr_alt_match_win[nop] = this_alternative_match_win; 2873 curr_alt_offmemok[nop] = this_alternative_offmemok; 2874 curr_alt_matches[nop] = this_alternative_matches; 2875 2876 if (this_alternative_matches >= 0 2877 && !did_match && !this_alternative_win) 2878 curr_alt_win[this_alternative_matches] = false; 2879 2880 if (early_clobber_p && operand_reg[nop] != NULL_RTX) 2881 early_clobbered_nops[early_clobbered_regs_num++] = nop; 2882 } 2883 2884 if (curr_insn_set != NULL_RTX && n_operands == 2 2885 /* Prevent processing non-move insns. */ 2886 && (GET_CODE (SET_SRC (curr_insn_set)) == SUBREG 2887 || SET_SRC (curr_insn_set) == no_subreg_reg_operand[1]) 2888 && ((! curr_alt_win[0] && ! curr_alt_win[1] 2889 && REG_P (no_subreg_reg_operand[0]) 2890 && REG_P (no_subreg_reg_operand[1]) 2891 && (reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) 2892 || reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0]))) 2893 || (! curr_alt_win[0] && curr_alt_win[1] 2894 && REG_P (no_subreg_reg_operand[1]) 2895 /* Check that we reload memory not the memory 2896 address. */ 2897 && ! (curr_alt_offmemok[0] 2898 && MEM_P (no_subreg_reg_operand[0])) 2899 && reg_in_class_p (no_subreg_reg_operand[1], curr_alt[0])) 2900 || (curr_alt_win[0] && ! curr_alt_win[1] 2901 && REG_P (no_subreg_reg_operand[0]) 2902 /* Check that we reload memory not the memory 2903 address. */ 2904 && ! (curr_alt_offmemok[1] 2905 && MEM_P (no_subreg_reg_operand[1])) 2906 && reg_in_class_p (no_subreg_reg_operand[0], curr_alt[1]) 2907 && (! CONST_POOL_OK_P (curr_operand_mode[1], 2908 no_subreg_reg_operand[1]) 2909 || (targetm.preferred_reload_class 2910 (no_subreg_reg_operand[1], 2911 (enum reg_class) curr_alt[1]) != NO_REGS)) 2912 /* If it is a result of recent elimination in move 2913 insn we can transform it into an add still by 2914 using this alternative. */ 2915 && GET_CODE (no_subreg_reg_operand[1]) != PLUS 2916 /* Likewise if the source has been replaced with an 2917 equivalent value. This only happens once -- the reload 2918 will use the equivalent value instead of the register it 2919 replaces -- so there should be no danger of cycling. */ 2920 && !equiv_substition_p[1]))) 2921 { 2922 /* We have a move insn and a new reload insn will be similar 2923 to the current insn. We should avoid such situation as 2924 it results in LRA cycling. */ 2925 if (lra_dump_file != NULL) 2926 fprintf (lra_dump_file, 2927 " Cycle danger: overall += LRA_MAX_REJECT\n"); 2928 overall += LRA_MAX_REJECT; 2929 } 2930 ok_p = true; 2931 curr_alt_dont_inherit_ops_num = 0; 2932 for (nop = 0; nop < early_clobbered_regs_num; nop++) 2933 { 2934 int i, j, clobbered_hard_regno, first_conflict_j, last_conflict_j; 2935 HARD_REG_SET temp_set; 2936 2937 i = early_clobbered_nops[nop]; 2938 if ((! curr_alt_win[i] && ! curr_alt_match_win[i]) 2939 || hard_regno[i] < 0) 2940 continue; 2941 lra_assert (operand_reg[i] != NULL_RTX); 2942 clobbered_hard_regno = hard_regno[i]; 2943 CLEAR_HARD_REG_SET (temp_set); 2944 add_to_hard_reg_set (&temp_set, biggest_mode[i], clobbered_hard_regno); 2945 first_conflict_j = last_conflict_j = -1; 2946 for (j = 0; j < n_operands; j++) 2947 if (j == i 2948 /* We don't want process insides of match_operator and 2949 match_parallel because otherwise we would process 2950 their operands once again generating a wrong 2951 code. */ 2952 || curr_static_id->operand[j].is_operator) 2953 continue; 2954 else if ((curr_alt_matches[j] == i && curr_alt_match_win[j]) 2955 || (curr_alt_matches[i] == j && curr_alt_match_win[i])) 2956 continue; 2957 /* If we don't reload j-th operand, check conflicts. */ 2958 else if ((curr_alt_win[j] || curr_alt_match_win[j]) 2959 && uses_hard_regs_p (*curr_id->operand_loc[j], temp_set)) 2960 { 2961 if (first_conflict_j < 0) 2962 first_conflict_j = j; 2963 last_conflict_j = j; 2964 /* Both the earlyclobber operand and conflicting operand 2965 cannot both be user defined hard registers. */ 2966 if (HARD_REGISTER_P (operand_reg[i]) 2967 && REG_USERVAR_P (operand_reg[i]) 2968 && operand_reg[j] != NULL_RTX 2969 && HARD_REGISTER_P (operand_reg[j]) 2970 && REG_USERVAR_P (operand_reg[j])) 2971 fatal_insn ("unable to generate reloads for " 2972 "impossible constraints:", curr_insn); 2973 } 2974 if (last_conflict_j < 0) 2975 continue; 2976 2977 /* If an earlyclobber operand conflicts with another non-matching 2978 operand (ie, they have been assigned the same hard register), 2979 then it is better to reload the other operand, as there may 2980 exist yet another operand with a matching constraint associated 2981 with the earlyclobber operand. However, if one of the operands 2982 is an explicit use of a hard register, then we must reload the 2983 other non-hard register operand. */ 2984 if (HARD_REGISTER_P (operand_reg[i]) 2985 || (first_conflict_j == last_conflict_j 2986 && operand_reg[last_conflict_j] != NULL_RTX 2987 && !curr_alt_match_win[last_conflict_j] 2988 && !HARD_REGISTER_P (operand_reg[last_conflict_j]))) 2989 { 2990 curr_alt_win[last_conflict_j] = false; 2991 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] 2992 = last_conflict_j; 2993 losers++; 2994 if (lra_dump_file != NULL) 2995 fprintf 2996 (lra_dump_file, 2997 " %d Conflict early clobber reload: reject--\n", 2998 i); 2999 } 3000 else 3001 { 3002 /* We need to reload early clobbered register and the 3003 matched registers. */ 3004 for (j = 0; j < n_operands; j++) 3005 if (curr_alt_matches[j] == i) 3006 { 3007 curr_alt_match_win[j] = false; 3008 losers++; 3009 overall += LRA_LOSER_COST_FACTOR; 3010 } 3011 if (! curr_alt_match_win[i]) 3012 curr_alt_dont_inherit_ops[curr_alt_dont_inherit_ops_num++] = i; 3013 else 3014 { 3015 /* Remember pseudos used for match reloads are never 3016 inherited. */ 3017 lra_assert (curr_alt_matches[i] >= 0); 3018 curr_alt_win[curr_alt_matches[i]] = false; 3019 } 3020 curr_alt_win[i] = curr_alt_match_win[i] = false; 3021 losers++; 3022 if (lra_dump_file != NULL) 3023 fprintf 3024 (lra_dump_file, 3025 " %d Matched conflict early clobber reloads: " 3026 "reject--\n", 3027 i); 3028 } 3029 /* Early clobber was already reflected in REJECT. */ 3030 if (!matching_early_clobber[i]) 3031 { 3032 lra_assert (reject > 0); 3033 reject--; 3034 matching_early_clobber[i] = 1; 3035 } 3036 overall += LRA_LOSER_COST_FACTOR - 1; 3037 } 3038 if (lra_dump_file != NULL) 3039 fprintf (lra_dump_file, " alt=%d,overall=%d,losers=%d,rld_nregs=%d\n", 3040 nalt, overall, losers, reload_nregs); 3041 3042 /* If this alternative can be made to work by reloading, and it 3043 needs less reloading than the others checked so far, record 3044 it as the chosen goal for reloading. */ 3045 if ((best_losers != 0 && losers == 0) 3046 || (((best_losers == 0 && losers == 0) 3047 || (best_losers != 0 && losers != 0)) 3048 && (best_overall > overall 3049 || (best_overall == overall 3050 /* If the cost of the reloads is the same, 3051 prefer alternative which requires minimal 3052 number of reload regs. */ 3053 && (reload_nregs < best_reload_nregs 3054 || (reload_nregs == best_reload_nregs 3055 && (best_reload_sum < reload_sum 3056 || (best_reload_sum == reload_sum 3057 && nalt < goal_alt_number)))))))) 3058 { 3059 for (nop = 0; nop < n_operands; nop++) 3060 { 3061 goal_alt_win[nop] = curr_alt_win[nop]; 3062 goal_alt_match_win[nop] = curr_alt_match_win[nop]; 3063 goal_alt_matches[nop] = curr_alt_matches[nop]; 3064 goal_alt[nop] = curr_alt[nop]; 3065 goal_alt_offmemok[nop] = curr_alt_offmemok[nop]; 3066 } 3067 goal_alt_dont_inherit_ops_num = curr_alt_dont_inherit_ops_num; 3068 for (nop = 0; nop < curr_alt_dont_inherit_ops_num; nop++) 3069 goal_alt_dont_inherit_ops[nop] = curr_alt_dont_inherit_ops[nop]; 3070 goal_alt_swapped = curr_swapped; 3071 best_overall = overall; 3072 best_losers = losers; 3073 best_reload_nregs = reload_nregs; 3074 best_reload_sum = reload_sum; 3075 goal_alt_number = nalt; 3076 } 3077 if (losers == 0) 3078 /* Everything is satisfied. Do not process alternatives 3079 anymore. */ 3080 break; 3081 fail: 3082 ; 3083 } 3084 return ok_p; 3085 } 3086 3087 /* Make reload base reg from address AD. */ 3088 static rtx 3089 base_to_reg (struct address_info *ad) 3090 { 3091 enum reg_class cl; 3092 int code = -1; 3093 rtx new_inner = NULL_RTX; 3094 rtx new_reg = NULL_RTX; 3095 rtx_insn *insn; 3096 rtx_insn *last_insn = get_last_insn(); 3097 3098 lra_assert (ad->disp == ad->disp_term); 3099 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, 3100 get_index_code (ad)); 3101 new_reg = lra_create_new_reg (GET_MODE (*ad->base), NULL_RTX, 3102 cl, "base"); 3103 new_inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), new_reg, 3104 ad->disp_term == NULL 3105 ? const0_rtx 3106 : *ad->disp_term); 3107 if (!valid_address_p (ad->mode, new_inner, ad->as)) 3108 return NULL_RTX; 3109 insn = emit_insn (gen_rtx_SET (new_reg, *ad->base)); 3110 code = recog_memoized (insn); 3111 if (code < 0) 3112 { 3113 delete_insns_since (last_insn); 3114 return NULL_RTX; 3115 } 3116 3117 return new_inner; 3118 } 3119 3120 /* Make reload base reg + DISP from address AD. Return the new pseudo. */ 3121 static rtx 3122 base_plus_disp_to_reg (struct address_info *ad, rtx disp) 3123 { 3124 enum reg_class cl; 3125 rtx new_reg; 3126 3127 lra_assert (ad->base == ad->base_term); 3128 cl = base_reg_class (ad->mode, ad->as, ad->base_outer_code, 3129 get_index_code (ad)); 3130 new_reg = lra_create_new_reg (GET_MODE (*ad->base_term), NULL_RTX, 3131 cl, "base + disp"); 3132 lra_emit_add (new_reg, *ad->base_term, disp); 3133 return new_reg; 3134 } 3135 3136 /* Make reload of index part of address AD. Return the new 3137 pseudo. */ 3138 static rtx 3139 index_part_to_reg (struct address_info *ad) 3140 { 3141 rtx new_reg; 3142 3143 new_reg = lra_create_new_reg (GET_MODE (*ad->index), NULL_RTX, 3144 INDEX_REG_CLASS, "index term"); 3145 expand_mult (GET_MODE (*ad->index), *ad->index_term, 3146 GEN_INT (get_index_scale (ad)), new_reg, 1); 3147 return new_reg; 3148 } 3149 3150 /* Return true if we can add a displacement to address AD, even if that 3151 makes the address invalid. The fix-up code requires any new address 3152 to be the sum of the BASE_TERM, INDEX and DISP_TERM fields. */ 3153 static bool 3154 can_add_disp_p (struct address_info *ad) 3155 { 3156 return (!ad->autoinc_p 3157 && ad->segment == NULL 3158 && ad->base == ad->base_term 3159 && ad->disp == ad->disp_term); 3160 } 3161 3162 /* Make equiv substitution in address AD. Return true if a substitution 3163 was made. */ 3164 static bool 3165 equiv_address_substitution (struct address_info *ad) 3166 { 3167 rtx base_reg, new_base_reg, index_reg, new_index_reg, *base_term, *index_term; 3168 poly_int64 disp; 3169 HOST_WIDE_INT scale; 3170 bool change_p; 3171 3172 base_term = strip_subreg (ad->base_term); 3173 if (base_term == NULL) 3174 base_reg = new_base_reg = NULL_RTX; 3175 else 3176 { 3177 base_reg = *base_term; 3178 new_base_reg = get_equiv_with_elimination (base_reg, curr_insn); 3179 } 3180 index_term = strip_subreg (ad->index_term); 3181 if (index_term == NULL) 3182 index_reg = new_index_reg = NULL_RTX; 3183 else 3184 { 3185 index_reg = *index_term; 3186 new_index_reg = get_equiv_with_elimination (index_reg, curr_insn); 3187 } 3188 if (base_reg == new_base_reg && index_reg == new_index_reg) 3189 return false; 3190 disp = 0; 3191 change_p = false; 3192 if (lra_dump_file != NULL) 3193 { 3194 fprintf (lra_dump_file, "Changing address in insn %d ", 3195 INSN_UID (curr_insn)); 3196 dump_value_slim (lra_dump_file, *ad->outer, 1); 3197 } 3198 if (base_reg != new_base_reg) 3199 { 3200 poly_int64 offset; 3201 if (REG_P (new_base_reg)) 3202 { 3203 *base_term = new_base_reg; 3204 change_p = true; 3205 } 3206 else if (GET_CODE (new_base_reg) == PLUS 3207 && REG_P (XEXP (new_base_reg, 0)) 3208 && poly_int_rtx_p (XEXP (new_base_reg, 1), &offset) 3209 && can_add_disp_p (ad)) 3210 { 3211 disp += offset; 3212 *base_term = XEXP (new_base_reg, 0); 3213 change_p = true; 3214 } 3215 if (ad->base_term2 != NULL) 3216 *ad->base_term2 = *ad->base_term; 3217 } 3218 if (index_reg != new_index_reg) 3219 { 3220 poly_int64 offset; 3221 if (REG_P (new_index_reg)) 3222 { 3223 *index_term = new_index_reg; 3224 change_p = true; 3225 } 3226 else if (GET_CODE (new_index_reg) == PLUS 3227 && REG_P (XEXP (new_index_reg, 0)) 3228 && poly_int_rtx_p (XEXP (new_index_reg, 1), &offset) 3229 && can_add_disp_p (ad) 3230 && (scale = get_index_scale (ad))) 3231 { 3232 disp += offset * scale; 3233 *index_term = XEXP (new_index_reg, 0); 3234 change_p = true; 3235 } 3236 } 3237 if (maybe_ne (disp, 0)) 3238 { 3239 if (ad->disp != NULL) 3240 *ad->disp = plus_constant (GET_MODE (*ad->inner), *ad->disp, disp); 3241 else 3242 { 3243 *ad->inner = plus_constant (GET_MODE (*ad->inner), *ad->inner, disp); 3244 update_address (ad); 3245 } 3246 change_p = true; 3247 } 3248 if (lra_dump_file != NULL) 3249 { 3250 if (! change_p) 3251 fprintf (lra_dump_file, " -- no change\n"); 3252 else 3253 { 3254 fprintf (lra_dump_file, " on equiv "); 3255 dump_value_slim (lra_dump_file, *ad->outer, 1); 3256 fprintf (lra_dump_file, "\n"); 3257 } 3258 } 3259 return change_p; 3260 } 3261 3262 /* Major function to make reloads for an address in operand NOP or 3263 check its correctness (If CHECK_ONLY_P is true). The supported 3264 cases are: 3265 3266 1) an address that existed before LRA started, at which point it 3267 must have been valid. These addresses are subject to elimination 3268 and may have become invalid due to the elimination offset being out 3269 of range. 3270 3271 2) an address created by forcing a constant to memory 3272 (force_const_to_mem). The initial form of these addresses might 3273 not be valid, and it is this function's job to make them valid. 3274 3275 3) a frame address formed from a register and a (possibly zero) 3276 constant offset. As above, these addresses might not be valid and 3277 this function must make them so. 3278 3279 Add reloads to the lists *BEFORE and *AFTER. We might need to add 3280 reloads to *AFTER because of inc/dec, {pre, post} modify in the 3281 address. Return true for any RTL change. 3282 3283 The function is a helper function which does not produce all 3284 transformations (when CHECK_ONLY_P is false) which can be 3285 necessary. It does just basic steps. To do all necessary 3286 transformations use function process_address. */ 3287 static bool 3288 process_address_1 (int nop, bool check_only_p, 3289 rtx_insn **before, rtx_insn **after) 3290 { 3291 struct address_info ad; 3292 rtx new_reg; 3293 HOST_WIDE_INT scale; 3294 rtx op = *curr_id->operand_loc[nop]; 3295 const char *constraint = curr_static_id->operand[nop].constraint; 3296 enum constraint_num cn = lookup_constraint (constraint); 3297 bool change_p = false; 3298 3299 if (MEM_P (op) 3300 && GET_MODE (op) == BLKmode 3301 && GET_CODE (XEXP (op, 0)) == SCRATCH) 3302 return false; 3303 3304 if (insn_extra_address_constraint (cn) 3305 /* When we find an asm operand with an address constraint that 3306 doesn't satisfy address_operand to begin with, we clear 3307 is_address, so that we don't try to make a non-address fit. 3308 If the asm statement got this far, it's because other 3309 constraints are available, and we'll use them, disregarding 3310 the unsatisfiable address ones. */ 3311 && curr_static_id->operand[nop].is_address) 3312 decompose_lea_address (&ad, curr_id->operand_loc[nop]); 3313 /* Do not attempt to decompose arbitrary addresses generated by combine 3314 for asm operands with loose constraints, e.g 'X'. */ 3315 else if (MEM_P (op) 3316 && !(INSN_CODE (curr_insn) < 0 3317 && get_constraint_type (cn) == CT_FIXED_FORM 3318 && constraint_satisfied_p (op, cn))) 3319 decompose_mem_address (&ad, op); 3320 else if (GET_CODE (op) == SUBREG 3321 && MEM_P (SUBREG_REG (op))) 3322 decompose_mem_address (&ad, SUBREG_REG (op)); 3323 else 3324 return false; 3325 /* If INDEX_REG_CLASS is assigned to base_term already and isn't to 3326 index_term, swap them so to avoid assigning INDEX_REG_CLASS to both 3327 when INDEX_REG_CLASS is a single register class. */ 3328 if (ad.base_term != NULL 3329 && ad.index_term != NULL 3330 && ira_class_hard_regs_num[INDEX_REG_CLASS] == 1 3331 && REG_P (*ad.base_term) 3332 && REG_P (*ad.index_term) 3333 && in_class_p (*ad.base_term, INDEX_REG_CLASS, NULL) 3334 && ! in_class_p (*ad.index_term, INDEX_REG_CLASS, NULL)) 3335 { 3336 std::swap (ad.base, ad.index); 3337 std::swap (ad.base_term, ad.index_term); 3338 } 3339 if (! check_only_p) 3340 change_p = equiv_address_substitution (&ad); 3341 if (ad.base_term != NULL 3342 && (process_addr_reg 3343 (ad.base_term, check_only_p, before, 3344 (ad.autoinc_p 3345 && !(REG_P (*ad.base_term) 3346 && find_regno_note (curr_insn, REG_DEAD, 3347 REGNO (*ad.base_term)) != NULL_RTX) 3348 ? after : NULL), 3349 base_reg_class (ad.mode, ad.as, ad.base_outer_code, 3350 get_index_code (&ad))))) 3351 { 3352 change_p = true; 3353 if (ad.base_term2 != NULL) 3354 *ad.base_term2 = *ad.base_term; 3355 } 3356 if (ad.index_term != NULL 3357 && process_addr_reg (ad.index_term, check_only_p, 3358 before, NULL, INDEX_REG_CLASS)) 3359 change_p = true; 3360 3361 /* Target hooks sometimes don't treat extra-constraint addresses as 3362 legitimate address_operands, so handle them specially. */ 3363 if (insn_extra_address_constraint (cn) 3364 && satisfies_address_constraint_p (&ad, cn)) 3365 return change_p; 3366 3367 if (check_only_p) 3368 return change_p; 3369 3370 /* There are three cases where the shape of *AD.INNER may now be invalid: 3371 3372 1) the original address was valid, but either elimination or 3373 equiv_address_substitution was applied and that made 3374 the address invalid. 3375 3376 2) the address is an invalid symbolic address created by 3377 force_const_to_mem. 3378 3379 3) the address is a frame address with an invalid offset. 3380 3381 4) the address is a frame address with an invalid base. 3382 3383 All these cases involve a non-autoinc address, so there is no 3384 point revalidating other types. */ 3385 if (ad.autoinc_p || valid_address_p (&ad)) 3386 return change_p; 3387 3388 /* Any index existed before LRA started, so we can assume that the 3389 presence and shape of the index is valid. */ 3390 push_to_sequence (*before); 3391 lra_assert (ad.disp == ad.disp_term); 3392 if (ad.base == NULL) 3393 { 3394 if (ad.index == NULL) 3395 { 3396 rtx_insn *insn; 3397 rtx_insn *last = get_last_insn (); 3398 int code = -1; 3399 enum reg_class cl = base_reg_class (ad.mode, ad.as, 3400 SCRATCH, SCRATCH); 3401 rtx addr = *ad.inner; 3402 3403 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); 3404 if (HAVE_lo_sum) 3405 { 3406 /* addr => lo_sum (new_base, addr), case (2) above. */ 3407 insn = emit_insn (gen_rtx_SET 3408 (new_reg, 3409 gen_rtx_HIGH (Pmode, copy_rtx (addr)))); 3410 code = recog_memoized (insn); 3411 if (code >= 0) 3412 { 3413 *ad.inner = gen_rtx_LO_SUM (Pmode, new_reg, addr); 3414 if (! valid_address_p (ad.mode, *ad.outer, ad.as)) 3415 { 3416 /* Try to put lo_sum into register. */ 3417 insn = emit_insn (gen_rtx_SET 3418 (new_reg, 3419 gen_rtx_LO_SUM (Pmode, new_reg, addr))); 3420 code = recog_memoized (insn); 3421 if (code >= 0) 3422 { 3423 *ad.inner = new_reg; 3424 if (! valid_address_p (ad.mode, *ad.outer, ad.as)) 3425 { 3426 *ad.inner = addr; 3427 code = -1; 3428 } 3429 } 3430 3431 } 3432 } 3433 if (code < 0) 3434 delete_insns_since (last); 3435 } 3436 3437 if (code < 0) 3438 { 3439 /* addr => new_base, case (2) above. */ 3440 lra_emit_move (new_reg, addr); 3441 3442 for (insn = last == NULL_RTX ? get_insns () : NEXT_INSN (last); 3443 insn != NULL_RTX; 3444 insn = NEXT_INSN (insn)) 3445 if (recog_memoized (insn) < 0) 3446 break; 3447 if (insn != NULL_RTX) 3448 { 3449 /* Do nothing if we cannot generate right insns. 3450 This is analogous to reload pass behavior. */ 3451 delete_insns_since (last); 3452 end_sequence (); 3453 return false; 3454 } 3455 *ad.inner = new_reg; 3456 } 3457 } 3458 else 3459 { 3460 /* index * scale + disp => new base + index * scale, 3461 case (1) above. */ 3462 enum reg_class cl = base_reg_class (ad.mode, ad.as, PLUS, 3463 GET_CODE (*ad.index)); 3464 3465 lra_assert (INDEX_REG_CLASS != NO_REGS); 3466 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "disp"); 3467 lra_emit_move (new_reg, *ad.disp); 3468 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), 3469 new_reg, *ad.index); 3470 } 3471 } 3472 else if (ad.index == NULL) 3473 { 3474 int regno; 3475 enum reg_class cl; 3476 rtx set; 3477 rtx_insn *insns, *last_insn; 3478 /* Try to reload base into register only if the base is invalid 3479 for the address but with valid offset, case (4) above. */ 3480 start_sequence (); 3481 new_reg = base_to_reg (&ad); 3482 3483 /* base + disp => new base, cases (1) and (3) above. */ 3484 /* Another option would be to reload the displacement into an 3485 index register. However, postreload has code to optimize 3486 address reloads that have the same base and different 3487 displacements, so reloading into an index register would 3488 not necessarily be a win. */ 3489 if (new_reg == NULL_RTX) 3490 { 3491 /* See if the target can split the displacement into a 3492 legitimate new displacement from a local anchor. */ 3493 gcc_assert (ad.disp == ad.disp_term); 3494 poly_int64 orig_offset; 3495 rtx offset1, offset2; 3496 if (poly_int_rtx_p (*ad.disp, &orig_offset) 3497 && targetm.legitimize_address_displacement (&offset1, &offset2, 3498 orig_offset, 3499 ad.mode)) 3500 { 3501 new_reg = base_plus_disp_to_reg (&ad, offset1); 3502 new_reg = gen_rtx_PLUS (GET_MODE (new_reg), new_reg, offset2); 3503 } 3504 else 3505 new_reg = base_plus_disp_to_reg (&ad, *ad.disp); 3506 } 3507 insns = get_insns (); 3508 last_insn = get_last_insn (); 3509 /* If we generated at least two insns, try last insn source as 3510 an address. If we succeed, we generate one less insn. */ 3511 if (REG_P (new_reg) 3512 && last_insn != insns 3513 && (set = single_set (last_insn)) != NULL_RTX 3514 && GET_CODE (SET_SRC (set)) == PLUS 3515 && REG_P (XEXP (SET_SRC (set), 0)) 3516 && CONSTANT_P (XEXP (SET_SRC (set), 1))) 3517 { 3518 *ad.inner = SET_SRC (set); 3519 if (valid_address_p (ad.mode, *ad.outer, ad.as)) 3520 { 3521 *ad.base_term = XEXP (SET_SRC (set), 0); 3522 *ad.disp_term = XEXP (SET_SRC (set), 1); 3523 cl = base_reg_class (ad.mode, ad.as, ad.base_outer_code, 3524 get_index_code (&ad)); 3525 regno = REGNO (*ad.base_term); 3526 if (regno >= FIRST_PSEUDO_REGISTER 3527 && cl != lra_get_allocno_class (regno)) 3528 lra_change_class (regno, cl, " Change to", true); 3529 new_reg = SET_SRC (set); 3530 delete_insns_since (PREV_INSN (last_insn)); 3531 } 3532 } 3533 end_sequence (); 3534 emit_insn (insns); 3535 *ad.inner = new_reg; 3536 } 3537 else if (ad.disp_term != NULL) 3538 { 3539 /* base + scale * index + disp => new base + scale * index, 3540 case (1) above. */ 3541 gcc_assert (ad.disp == ad.disp_term); 3542 new_reg = base_plus_disp_to_reg (&ad, *ad.disp); 3543 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), 3544 new_reg, *ad.index); 3545 } 3546 else if ((scale = get_index_scale (&ad)) == 1) 3547 { 3548 /* The last transformation to one reg will be made in 3549 curr_insn_transform function. */ 3550 end_sequence (); 3551 return false; 3552 } 3553 else if (scale != 0) 3554 { 3555 /* base + scale * index => base + new_reg, 3556 case (1) above. 3557 Index part of address may become invalid. For example, we 3558 changed pseudo on the equivalent memory and a subreg of the 3559 pseudo onto the memory of different mode for which the scale is 3560 prohibitted. */ 3561 new_reg = index_part_to_reg (&ad); 3562 *ad.inner = simplify_gen_binary (PLUS, GET_MODE (new_reg), 3563 *ad.base_term, new_reg); 3564 } 3565 else 3566 { 3567 enum reg_class cl = base_reg_class (ad.mode, ad.as, 3568 SCRATCH, SCRATCH); 3569 rtx addr = *ad.inner; 3570 3571 new_reg = lra_create_new_reg (Pmode, NULL_RTX, cl, "addr"); 3572 /* addr => new_base. */ 3573 lra_emit_move (new_reg, addr); 3574 *ad.inner = new_reg; 3575 } 3576 *before = get_insns (); 3577 end_sequence (); 3578 return true; 3579 } 3580 3581 /* If CHECK_ONLY_P is false, do address reloads until it is necessary. 3582 Use process_address_1 as a helper function. Return true for any 3583 RTL changes. 3584 3585 If CHECK_ONLY_P is true, just check address correctness. Return 3586 false if the address correct. */ 3587 static bool 3588 process_address (int nop, bool check_only_p, 3589 rtx_insn **before, rtx_insn **after) 3590 { 3591 bool res = false; 3592 3593 while (process_address_1 (nop, check_only_p, before, after)) 3594 { 3595 if (check_only_p) 3596 return true; 3597 res = true; 3598 } 3599 return res; 3600 } 3601 3602 /* Emit insns to reload VALUE into a new register. VALUE is an 3603 auto-increment or auto-decrement RTX whose operand is a register or 3604 memory location; so reloading involves incrementing that location. 3605 IN is either identical to VALUE, or some cheaper place to reload 3606 value being incremented/decremented from. 3607 3608 INC_AMOUNT is the number to increment or decrement by (always 3609 positive and ignored for POST_MODIFY/PRE_MODIFY). 3610 3611 Return pseudo containing the result. */ 3612 static rtx 3613 emit_inc (enum reg_class new_rclass, rtx in, rtx value, poly_int64 inc_amount) 3614 { 3615 /* REG or MEM to be copied and incremented. */ 3616 rtx incloc = XEXP (value, 0); 3617 /* Nonzero if increment after copying. */ 3618 int post = (GET_CODE (value) == POST_DEC || GET_CODE (value) == POST_INC 3619 || GET_CODE (value) == POST_MODIFY); 3620 rtx_insn *last; 3621 rtx inc; 3622 rtx_insn *add_insn; 3623 int code; 3624 rtx real_in = in == value ? incloc : in; 3625 rtx result; 3626 bool plus_p = true; 3627 3628 if (GET_CODE (value) == PRE_MODIFY || GET_CODE (value) == POST_MODIFY) 3629 { 3630 lra_assert (GET_CODE (XEXP (value, 1)) == PLUS 3631 || GET_CODE (XEXP (value, 1)) == MINUS); 3632 lra_assert (rtx_equal_p (XEXP (XEXP (value, 1), 0), XEXP (value, 0))); 3633 plus_p = GET_CODE (XEXP (value, 1)) == PLUS; 3634 inc = XEXP (XEXP (value, 1), 1); 3635 } 3636 else 3637 { 3638 if (GET_CODE (value) == PRE_DEC || GET_CODE (value) == POST_DEC) 3639 inc_amount = -inc_amount; 3640 3641 inc = gen_int_mode (inc_amount, GET_MODE (value)); 3642 } 3643 3644 if (! post && REG_P (incloc)) 3645 result = incloc; 3646 else 3647 result = lra_create_new_reg (GET_MODE (value), value, new_rclass, 3648 "INC/DEC result"); 3649 3650 if (real_in != result) 3651 { 3652 /* First copy the location to the result register. */ 3653 lra_assert (REG_P (result)); 3654 emit_insn (gen_move_insn (result, real_in)); 3655 } 3656 3657 /* We suppose that there are insns to add/sub with the constant 3658 increment permitted in {PRE/POST)_{DEC/INC/MODIFY}. At least the 3659 old reload worked with this assumption. If the assumption 3660 becomes wrong, we should use approach in function 3661 base_plus_disp_to_reg. */ 3662 if (in == value) 3663 { 3664 /* See if we can directly increment INCLOC. */ 3665 last = get_last_insn (); 3666 add_insn = emit_insn (plus_p 3667 ? gen_add2_insn (incloc, inc) 3668 : gen_sub2_insn (incloc, inc)); 3669 3670 code = recog_memoized (add_insn); 3671 if (code >= 0) 3672 { 3673 if (! post && result != incloc) 3674 emit_insn (gen_move_insn (result, incloc)); 3675 return result; 3676 } 3677 delete_insns_since (last); 3678 } 3679 3680 /* If couldn't do the increment directly, must increment in RESULT. 3681 The way we do this depends on whether this is pre- or 3682 post-increment. For pre-increment, copy INCLOC to the reload 3683 register, increment it there, then save back. */ 3684 if (! post) 3685 { 3686 if (real_in != result) 3687 emit_insn (gen_move_insn (result, real_in)); 3688 if (plus_p) 3689 emit_insn (gen_add2_insn (result, inc)); 3690 else 3691 emit_insn (gen_sub2_insn (result, inc)); 3692 if (result != incloc) 3693 emit_insn (gen_move_insn (incloc, result)); 3694 } 3695 else 3696 { 3697 /* Post-increment. 3698 3699 Because this might be a jump insn or a compare, and because 3700 RESULT may not be available after the insn in an input 3701 reload, we must do the incrementing before the insn being 3702 reloaded for. 3703 3704 We have already copied IN to RESULT. Increment the copy in 3705 RESULT, save that back, then decrement RESULT so it has 3706 the original value. */ 3707 if (plus_p) 3708 emit_insn (gen_add2_insn (result, inc)); 3709 else 3710 emit_insn (gen_sub2_insn (result, inc)); 3711 emit_insn (gen_move_insn (incloc, result)); 3712 /* Restore non-modified value for the result. We prefer this 3713 way because it does not require an additional hard 3714 register. */ 3715 if (plus_p) 3716 { 3717 poly_int64 offset; 3718 if (poly_int_rtx_p (inc, &offset)) 3719 emit_insn (gen_add2_insn (result, 3720 gen_int_mode (-offset, 3721 GET_MODE (result)))); 3722 else 3723 emit_insn (gen_sub2_insn (result, inc)); 3724 } 3725 else 3726 emit_insn (gen_add2_insn (result, inc)); 3727 } 3728 return result; 3729 } 3730 3731 /* Return true if the current move insn does not need processing as we 3732 already know that it satisfies its constraints. */ 3733 static bool 3734 simple_move_p (void) 3735 { 3736 rtx dest, src; 3737 enum reg_class dclass, sclass; 3738 3739 lra_assert (curr_insn_set != NULL_RTX); 3740 dest = SET_DEST (curr_insn_set); 3741 src = SET_SRC (curr_insn_set); 3742 3743 /* If the instruction has multiple sets we need to process it even if it 3744 is single_set. This can happen if one or more of the SETs are dead. 3745 See PR73650. */ 3746 if (multiple_sets (curr_insn)) 3747 return false; 3748 3749 return ((dclass = get_op_class (dest)) != NO_REGS 3750 && (sclass = get_op_class (src)) != NO_REGS 3751 /* The backend guarantees that register moves of cost 2 3752 never need reloads. */ 3753 && targetm.register_move_cost (GET_MODE (src), sclass, dclass) == 2); 3754 } 3755 3756 /* Swap operands NOP and NOP + 1. */ 3757 static inline void 3758 swap_operands (int nop) 3759 { 3760 std::swap (curr_operand_mode[nop], curr_operand_mode[nop + 1]); 3761 std::swap (original_subreg_reg_mode[nop], original_subreg_reg_mode[nop + 1]); 3762 std::swap (*curr_id->operand_loc[nop], *curr_id->operand_loc[nop + 1]); 3763 std::swap (equiv_substition_p[nop], equiv_substition_p[nop + 1]); 3764 /* Swap the duplicates too. */ 3765 lra_update_dup (curr_id, nop); 3766 lra_update_dup (curr_id, nop + 1); 3767 } 3768 3769 /* Main entry point of the constraint code: search the body of the 3770 current insn to choose the best alternative. It is mimicking insn 3771 alternative cost calculation model of former reload pass. That is 3772 because machine descriptions were written to use this model. This 3773 model can be changed in future. Make commutative operand exchange 3774 if it is chosen. 3775 3776 if CHECK_ONLY_P is false, do RTL changes to satisfy the 3777 constraints. Return true if any change happened during function 3778 call. 3779 3780 If CHECK_ONLY_P is true then don't do any transformation. Just 3781 check that the insn satisfies all constraints. If the insn does 3782 not satisfy any constraint, return true. */ 3783 static bool 3784 curr_insn_transform (bool check_only_p) 3785 { 3786 int i, j, k; 3787 int n_operands; 3788 int n_alternatives; 3789 int n_outputs; 3790 int commutative; 3791 signed char goal_alt_matched[MAX_RECOG_OPERANDS][MAX_RECOG_OPERANDS]; 3792 signed char match_inputs[MAX_RECOG_OPERANDS + 1]; 3793 signed char outputs[MAX_RECOG_OPERANDS + 1]; 3794 rtx_insn *before, *after; 3795 bool alt_p = false; 3796 /* Flag that the insn has been changed through a transformation. */ 3797 bool change_p; 3798 bool sec_mem_p; 3799 bool use_sec_mem_p; 3800 int max_regno_before; 3801 int reused_alternative_num; 3802 3803 curr_insn_set = single_set (curr_insn); 3804 if (curr_insn_set != NULL_RTX && simple_move_p ()) 3805 { 3806 /* We assume that the corresponding insn alternative has no 3807 earlier clobbers. If it is not the case, don't define move 3808 cost equal to 2 for the corresponding register classes. */ 3809 lra_set_used_insn_alternative (curr_insn, LRA_NON_CLOBBERED_ALT); 3810 return false; 3811 } 3812 3813 no_input_reloads_p = no_output_reloads_p = false; 3814 goal_alt_number = -1; 3815 change_p = sec_mem_p = false; 3816 /* JUMP_INSNs and CALL_INSNs are not allowed to have any output 3817 reloads; neither are insns that SET cc0. Insns that use CC0 are 3818 not allowed to have any input reloads. */ 3819 if (JUMP_P (curr_insn) || CALL_P (curr_insn)) 3820 no_output_reloads_p = true; 3821 3822 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (curr_insn))) 3823 no_input_reloads_p = true; 3824 if (HAVE_cc0 && reg_set_p (cc0_rtx, PATTERN (curr_insn))) 3825 no_output_reloads_p = true; 3826 3827 n_operands = curr_static_id->n_operands; 3828 n_alternatives = curr_static_id->n_alternatives; 3829 3830 /* Just return "no reloads" if insn has no operands with 3831 constraints. */ 3832 if (n_operands == 0 || n_alternatives == 0) 3833 return false; 3834 3835 max_regno_before = max_reg_num (); 3836 3837 for (i = 0; i < n_operands; i++) 3838 { 3839 goal_alt_matched[i][0] = -1; 3840 goal_alt_matches[i] = -1; 3841 } 3842 3843 commutative = curr_static_id->commutative; 3844 3845 /* Now see what we need for pseudos that didn't get hard regs or got 3846 the wrong kind of hard reg. For this, we must consider all the 3847 operands together against the register constraints. */ 3848 3849 best_losers = best_overall = INT_MAX; 3850 best_reload_sum = 0; 3851 3852 curr_swapped = false; 3853 goal_alt_swapped = false; 3854 3855 if (! check_only_p) 3856 /* Make equivalence substitution and memory subreg elimination 3857 before address processing because an address legitimacy can 3858 depend on memory mode. */ 3859 for (i = 0; i < n_operands; i++) 3860 { 3861 rtx op, subst, old; 3862 bool op_change_p = false; 3863 3864 if (curr_static_id->operand[i].is_operator) 3865 continue; 3866 3867 old = op = *curr_id->operand_loc[i]; 3868 if (GET_CODE (old) == SUBREG) 3869 old = SUBREG_REG (old); 3870 subst = get_equiv_with_elimination (old, curr_insn); 3871 original_subreg_reg_mode[i] = VOIDmode; 3872 equiv_substition_p[i] = false; 3873 if (subst != old) 3874 { 3875 equiv_substition_p[i] = true; 3876 subst = copy_rtx (subst); 3877 lra_assert (REG_P (old)); 3878 if (GET_CODE (op) != SUBREG) 3879 *curr_id->operand_loc[i] = subst; 3880 else 3881 { 3882 SUBREG_REG (op) = subst; 3883 if (GET_MODE (subst) == VOIDmode) 3884 original_subreg_reg_mode[i] = GET_MODE (old); 3885 } 3886 if (lra_dump_file != NULL) 3887 { 3888 fprintf (lra_dump_file, 3889 "Changing pseudo %d in operand %i of insn %u on equiv ", 3890 REGNO (old), i, INSN_UID (curr_insn)); 3891 dump_value_slim (lra_dump_file, subst, 1); 3892 fprintf (lra_dump_file, "\n"); 3893 } 3894 op_change_p = change_p = true; 3895 } 3896 if (simplify_operand_subreg (i, GET_MODE (old)) || op_change_p) 3897 { 3898 change_p = true; 3899 lra_update_dup (curr_id, i); 3900 } 3901 } 3902 3903 /* Reload address registers and displacements. We do it before 3904 finding an alternative because of memory constraints. */ 3905 before = after = NULL; 3906 for (i = 0; i < n_operands; i++) 3907 if (! curr_static_id->operand[i].is_operator 3908 && process_address (i, check_only_p, &before, &after)) 3909 { 3910 if (check_only_p) 3911 return true; 3912 change_p = true; 3913 lra_update_dup (curr_id, i); 3914 } 3915 3916 if (change_p) 3917 /* If we've changed the instruction then any alternative that 3918 we chose previously may no longer be valid. */ 3919 lra_set_used_insn_alternative (curr_insn, LRA_UNKNOWN_ALT); 3920 3921 if (! check_only_p && curr_insn_set != NULL_RTX 3922 && check_and_process_move (&change_p, &sec_mem_p)) 3923 return change_p; 3924 3925 try_swapped: 3926 3927 reused_alternative_num = check_only_p ? LRA_UNKNOWN_ALT : curr_id->used_insn_alternative; 3928 if (lra_dump_file != NULL && reused_alternative_num >= 0) 3929 fprintf (lra_dump_file, "Reusing alternative %d for insn #%u\n", 3930 reused_alternative_num, INSN_UID (curr_insn)); 3931 3932 if (process_alt_operands (reused_alternative_num)) 3933 alt_p = true; 3934 3935 if (check_only_p) 3936 return ! alt_p || best_losers != 0; 3937 3938 /* If insn is commutative (it's safe to exchange a certain pair of 3939 operands) then we need to try each alternative twice, the second 3940 time matching those two operands as if we had exchanged them. To 3941 do this, really exchange them in operands. 3942 3943 If we have just tried the alternatives the second time, return 3944 operands to normal and drop through. */ 3945 3946 if (reused_alternative_num < 0 && commutative >= 0) 3947 { 3948 curr_swapped = !curr_swapped; 3949 if (curr_swapped) 3950 { 3951 swap_operands (commutative); 3952 goto try_swapped; 3953 } 3954 else 3955 swap_operands (commutative); 3956 } 3957 3958 if (! alt_p && ! sec_mem_p) 3959 { 3960 /* No alternative works with reloads?? */ 3961 if (INSN_CODE (curr_insn) >= 0) 3962 fatal_insn ("unable to generate reloads for:", curr_insn); 3963 error_for_asm (curr_insn, 3964 "inconsistent operand constraints in an %<asm%>"); 3965 lra_asm_error_p = true; 3966 /* Avoid further trouble with this insn. Don't generate use 3967 pattern here as we could use the insn SP offset. */ 3968 lra_set_insn_deleted (curr_insn); 3969 return true; 3970 } 3971 3972 /* If the best alternative is with operands 1 and 2 swapped, swap 3973 them. Update the operand numbers of any reloads already 3974 pushed. */ 3975 3976 if (goal_alt_swapped) 3977 { 3978 if (lra_dump_file != NULL) 3979 fprintf (lra_dump_file, " Commutative operand exchange in insn %u\n", 3980 INSN_UID (curr_insn)); 3981 3982 /* Swap the duplicates too. */ 3983 swap_operands (commutative); 3984 change_p = true; 3985 } 3986 3987 /* Some targets' TARGET_SECONDARY_MEMORY_NEEDED (e.g. x86) are defined 3988 too conservatively. So we use the secondary memory only if there 3989 is no any alternative without reloads. */ 3990 use_sec_mem_p = false; 3991 if (! alt_p) 3992 use_sec_mem_p = true; 3993 else if (sec_mem_p) 3994 { 3995 for (i = 0; i < n_operands; i++) 3996 if (! goal_alt_win[i] && ! goal_alt_match_win[i]) 3997 break; 3998 use_sec_mem_p = i < n_operands; 3999 } 4000 4001 if (use_sec_mem_p) 4002 { 4003 int in = -1, out = -1; 4004 rtx new_reg, src, dest, rld; 4005 machine_mode sec_mode, rld_mode; 4006 4007 lra_assert (curr_insn_set != NULL_RTX && sec_mem_p); 4008 dest = SET_DEST (curr_insn_set); 4009 src = SET_SRC (curr_insn_set); 4010 for (i = 0; i < n_operands; i++) 4011 if (*curr_id->operand_loc[i] == dest) 4012 out = i; 4013 else if (*curr_id->operand_loc[i] == src) 4014 in = i; 4015 for (i = 0; i < curr_static_id->n_dups; i++) 4016 if (out < 0 && *curr_id->dup_loc[i] == dest) 4017 out = curr_static_id->dup_num[i]; 4018 else if (in < 0 && *curr_id->dup_loc[i] == src) 4019 in = curr_static_id->dup_num[i]; 4020 lra_assert (out >= 0 && in >= 0 4021 && curr_static_id->operand[out].type == OP_OUT 4022 && curr_static_id->operand[in].type == OP_IN); 4023 rld = partial_subreg_p (GET_MODE (src), GET_MODE (dest)) ? src : dest; 4024 rld_mode = GET_MODE (rld); 4025 sec_mode = targetm.secondary_memory_needed_mode (rld_mode); 4026 new_reg = lra_create_new_reg (sec_mode, NULL_RTX, 4027 NO_REGS, "secondary"); 4028 /* If the mode is changed, it should be wider. */ 4029 lra_assert (!partial_subreg_p (sec_mode, rld_mode)); 4030 if (sec_mode != rld_mode) 4031 { 4032 /* If the target says specifically to use another mode for 4033 secondary memory moves we cannot reuse the original 4034 insn. */ 4035 after = emit_spill_move (false, new_reg, dest); 4036 lra_process_new_insns (curr_insn, NULL, after, 4037 "Inserting the sec. move"); 4038 /* We may have non null BEFORE here (e.g. after address 4039 processing. */ 4040 push_to_sequence (before); 4041 before = emit_spill_move (true, new_reg, src); 4042 emit_insn (before); 4043 before = get_insns (); 4044 end_sequence (); 4045 lra_process_new_insns (curr_insn, before, NULL, "Changing on"); 4046 lra_set_insn_deleted (curr_insn); 4047 } 4048 else if (dest == rld) 4049 { 4050 *curr_id->operand_loc[out] = new_reg; 4051 lra_update_dup (curr_id, out); 4052 after = emit_spill_move (false, new_reg, dest); 4053 lra_process_new_insns (curr_insn, NULL, after, 4054 "Inserting the sec. move"); 4055 } 4056 else 4057 { 4058 *curr_id->operand_loc[in] = new_reg; 4059 lra_update_dup (curr_id, in); 4060 /* See comments above. */ 4061 push_to_sequence (before); 4062 before = emit_spill_move (true, new_reg, src); 4063 emit_insn (before); 4064 before = get_insns (); 4065 end_sequence (); 4066 lra_process_new_insns (curr_insn, before, NULL, 4067 "Inserting the sec. move"); 4068 } 4069 lra_update_insn_regno_info (curr_insn); 4070 return true; 4071 } 4072 4073 lra_assert (goal_alt_number >= 0); 4074 lra_set_used_insn_alternative (curr_insn, goal_alt_number); 4075 4076 if (lra_dump_file != NULL) 4077 { 4078 const char *p; 4079 4080 fprintf (lra_dump_file, " Choosing alt %d in insn %u:", 4081 goal_alt_number, INSN_UID (curr_insn)); 4082 for (i = 0; i < n_operands; i++) 4083 { 4084 p = (curr_static_id->operand_alternative 4085 [goal_alt_number * n_operands + i].constraint); 4086 if (*p == '\0') 4087 continue; 4088 fprintf (lra_dump_file, " (%d) ", i); 4089 for (; *p != '\0' && *p != ',' && *p != '#'; p++) 4090 fputc (*p, lra_dump_file); 4091 } 4092 if (INSN_CODE (curr_insn) >= 0 4093 && (p = get_insn_name (INSN_CODE (curr_insn))) != NULL) 4094 fprintf (lra_dump_file, " {%s}", p); 4095 if (maybe_ne (curr_id->sp_offset, 0)) 4096 { 4097 fprintf (lra_dump_file, " (sp_off="); 4098 print_dec (curr_id->sp_offset, lra_dump_file); 4099 fprintf (lra_dump_file, ")"); 4100 } 4101 fprintf (lra_dump_file, "\n"); 4102 } 4103 4104 /* Right now, for any pair of operands I and J that are required to 4105 match, with J < I, goal_alt_matches[I] is J. Add I to 4106 goal_alt_matched[J]. */ 4107 4108 for (i = 0; i < n_operands; i++) 4109 if ((j = goal_alt_matches[i]) >= 0) 4110 { 4111 for (k = 0; goal_alt_matched[j][k] >= 0; k++) 4112 ; 4113 /* We allow matching one output operand and several input 4114 operands. */ 4115 lra_assert (k == 0 4116 || (curr_static_id->operand[j].type == OP_OUT 4117 && curr_static_id->operand[i].type == OP_IN 4118 && (curr_static_id->operand 4119 [goal_alt_matched[j][0]].type == OP_IN))); 4120 goal_alt_matched[j][k] = i; 4121 goal_alt_matched[j][k + 1] = -1; 4122 } 4123 4124 for (i = 0; i < n_operands; i++) 4125 goal_alt_win[i] |= goal_alt_match_win[i]; 4126 4127 /* Any constants that aren't allowed and can't be reloaded into 4128 registers are here changed into memory references. */ 4129 for (i = 0; i < n_operands; i++) 4130 if (goal_alt_win[i]) 4131 { 4132 int regno; 4133 enum reg_class new_class; 4134 rtx reg = *curr_id->operand_loc[i]; 4135 4136 if (GET_CODE (reg) == SUBREG) 4137 reg = SUBREG_REG (reg); 4138 4139 if (REG_P (reg) && (regno = REGNO (reg)) >= FIRST_PSEUDO_REGISTER) 4140 { 4141 bool ok_p = in_class_p (reg, goal_alt[i], &new_class); 4142 4143 if (new_class != NO_REGS && get_reg_class (regno) != new_class) 4144 { 4145 lra_assert (ok_p); 4146 lra_change_class (regno, new_class, " Change to", true); 4147 } 4148 } 4149 } 4150 else 4151 { 4152 const char *constraint; 4153 char c; 4154 rtx op = *curr_id->operand_loc[i]; 4155 rtx subreg = NULL_RTX; 4156 machine_mode mode = curr_operand_mode[i]; 4157 4158 if (GET_CODE (op) == SUBREG) 4159 { 4160 subreg = op; 4161 op = SUBREG_REG (op); 4162 mode = GET_MODE (op); 4163 } 4164 4165 if (CONST_POOL_OK_P (mode, op) 4166 && ((targetm.preferred_reload_class 4167 (op, (enum reg_class) goal_alt[i]) == NO_REGS) 4168 || no_input_reloads_p)) 4169 { 4170 rtx tem = force_const_mem (mode, op); 4171 4172 change_p = true; 4173 if (subreg != NULL_RTX) 4174 tem = gen_rtx_SUBREG (mode, tem, SUBREG_BYTE (subreg)); 4175 4176 *curr_id->operand_loc[i] = tem; 4177 lra_update_dup (curr_id, i); 4178 process_address (i, false, &before, &after); 4179 4180 /* If the alternative accepts constant pool refs directly 4181 there will be no reload needed at all. */ 4182 if (subreg != NULL_RTX) 4183 continue; 4184 /* Skip alternatives before the one requested. */ 4185 constraint = (curr_static_id->operand_alternative 4186 [goal_alt_number * n_operands + i].constraint); 4187 for (; 4188 (c = *constraint) && c != ',' && c != '#'; 4189 constraint += CONSTRAINT_LEN (c, constraint)) 4190 { 4191 enum constraint_num cn = lookup_constraint (constraint); 4192 if ((insn_extra_memory_constraint (cn) 4193 || insn_extra_special_memory_constraint (cn)) 4194 && satisfies_memory_constraint_p (tem, cn)) 4195 break; 4196 } 4197 if (c == '\0' || c == ',' || c == '#') 4198 continue; 4199 4200 goal_alt_win[i] = true; 4201 } 4202 } 4203 4204 n_outputs = 0; 4205 outputs[0] = -1; 4206 for (i = 0; i < n_operands; i++) 4207 { 4208 int regno; 4209 bool optional_p = false; 4210 rtx old, new_reg; 4211 rtx op = *curr_id->operand_loc[i]; 4212 4213 if (goal_alt_win[i]) 4214 { 4215 if (goal_alt[i] == NO_REGS 4216 && REG_P (op) 4217 /* When we assign NO_REGS it means that we will not 4218 assign a hard register to the scratch pseudo by 4219 assigment pass and the scratch pseudo will be 4220 spilled. Spilled scratch pseudos are transformed 4221 back to scratches at the LRA end. */ 4222 && lra_former_scratch_operand_p (curr_insn, i) 4223 && lra_former_scratch_p (REGNO (op))) 4224 { 4225 int regno = REGNO (op); 4226 lra_change_class (regno, NO_REGS, " Change to", true); 4227 if (lra_get_regno_hard_regno (regno) >= 0) 4228 /* We don't have to mark all insn affected by the 4229 spilled pseudo as there is only one such insn, the 4230 current one. */ 4231 reg_renumber[regno] = -1; 4232 lra_assert (bitmap_single_bit_set_p 4233 (&lra_reg_info[REGNO (op)].insn_bitmap)); 4234 } 4235 /* We can do an optional reload. If the pseudo got a hard 4236 reg, we might improve the code through inheritance. If 4237 it does not get a hard register we coalesce memory/memory 4238 moves later. Ignore move insns to avoid cycling. */ 4239 if (! lra_simple_p 4240 && lra_undo_inheritance_iter < LRA_MAX_INHERITANCE_PASSES 4241 && goal_alt[i] != NO_REGS && REG_P (op) 4242 && (regno = REGNO (op)) >= FIRST_PSEUDO_REGISTER 4243 && regno < new_regno_start 4244 && ! lra_former_scratch_p (regno) 4245 && reg_renumber[regno] < 0 4246 /* Check that the optional reload pseudo will be able to 4247 hold given mode value. */ 4248 && ! (prohibited_class_reg_set_mode_p 4249 (goal_alt[i], reg_class_contents[goal_alt[i]], 4250 PSEUDO_REGNO_MODE (regno))) 4251 && (curr_insn_set == NULL_RTX 4252 || !((REG_P (SET_SRC (curr_insn_set)) 4253 || MEM_P (SET_SRC (curr_insn_set)) 4254 || GET_CODE (SET_SRC (curr_insn_set)) == SUBREG) 4255 && (REG_P (SET_DEST (curr_insn_set)) 4256 || MEM_P (SET_DEST (curr_insn_set)) 4257 || GET_CODE (SET_DEST (curr_insn_set)) == SUBREG)))) 4258 optional_p = true; 4259 else if (goal_alt_matched[i][0] != -1 4260 && curr_static_id->operand[i].type == OP_OUT 4261 && (curr_static_id->operand_alternative 4262 [goal_alt_number * n_operands + i].earlyclobber) 4263 && REG_P (op)) 4264 { 4265 for (j = 0; goal_alt_matched[i][j] != -1; j++) 4266 { 4267 rtx op2 = *curr_id->operand_loc[goal_alt_matched[i][j]]; 4268 4269 if (REG_P (op2) && REGNO (op) != REGNO (op2)) 4270 break; 4271 } 4272 if (goal_alt_matched[i][j] != -1) 4273 { 4274 /* Generate reloads for different output and matched 4275 input registers. This is the easiest way to avoid 4276 creation of non-existing register conflicts in 4277 lra-lives.c. */ 4278 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, 4279 &after, TRUE); 4280 outputs[n_outputs++] = i; 4281 outputs[n_outputs] = -1; 4282 } 4283 continue; 4284 } 4285 else 4286 continue; 4287 } 4288 4289 /* Operands that match previous ones have already been handled. */ 4290 if (goal_alt_matches[i] >= 0) 4291 continue; 4292 4293 /* We should not have an operand with a non-offsettable address 4294 appearing where an offsettable address will do. It also may 4295 be a case when the address should be special in other words 4296 not a general one (e.g. it needs no index reg). */ 4297 if (goal_alt_matched[i][0] == -1 && goal_alt_offmemok[i] && MEM_P (op)) 4298 { 4299 enum reg_class rclass; 4300 rtx *loc = &XEXP (op, 0); 4301 enum rtx_code code = GET_CODE (*loc); 4302 4303 push_to_sequence (before); 4304 rclass = base_reg_class (GET_MODE (op), MEM_ADDR_SPACE (op), 4305 MEM, SCRATCH); 4306 if (GET_RTX_CLASS (code) == RTX_AUTOINC) 4307 new_reg = emit_inc (rclass, *loc, *loc, 4308 /* This value does not matter for MODIFY. */ 4309 GET_MODE_SIZE (GET_MODE (op))); 4310 else if (get_reload_reg (OP_IN, Pmode, *loc, rclass, FALSE, 4311 "offsetable address", &new_reg)) 4312 { 4313 rtx addr = *loc; 4314 enum rtx_code code = GET_CODE (addr); 4315 4316 if (code == AND && CONST_INT_P (XEXP (addr, 1))) 4317 /* (and ... (const_int -X)) is used to align to X bytes. */ 4318 addr = XEXP (*loc, 0); 4319 lra_emit_move (new_reg, addr); 4320 if (addr != *loc) 4321 emit_move_insn (new_reg, gen_rtx_AND (GET_MODE (new_reg), new_reg, XEXP (*loc, 1))); 4322 } 4323 before = get_insns (); 4324 end_sequence (); 4325 *loc = new_reg; 4326 lra_update_dup (curr_id, i); 4327 } 4328 else if (goal_alt_matched[i][0] == -1) 4329 { 4330 machine_mode mode; 4331 rtx reg, *loc; 4332 int hard_regno; 4333 enum op_type type = curr_static_id->operand[i].type; 4334 4335 loc = curr_id->operand_loc[i]; 4336 mode = curr_operand_mode[i]; 4337 if (GET_CODE (*loc) == SUBREG) 4338 { 4339 reg = SUBREG_REG (*loc); 4340 poly_int64 byte = SUBREG_BYTE (*loc); 4341 if (REG_P (reg) 4342 /* Strict_low_part requires reloading the register and not 4343 just the subreg. Likewise for a strict subreg no wider 4344 than a word for WORD_REGISTER_OPERATIONS targets. */ 4345 && (curr_static_id->operand[i].strict_low 4346 || (!paradoxical_subreg_p (mode, GET_MODE (reg)) 4347 && (hard_regno 4348 = get_try_hard_regno (REGNO (reg))) >= 0 4349 && (simplify_subreg_regno 4350 (hard_regno, 4351 GET_MODE (reg), byte, mode) < 0) 4352 && (goal_alt[i] == NO_REGS 4353 || (simplify_subreg_regno 4354 (ira_class_hard_regs[goal_alt[i]][0], 4355 GET_MODE (reg), byte, mode) >= 0))) 4356 || (partial_subreg_p (mode, GET_MODE (reg)) 4357 && known_le (GET_MODE_SIZE (GET_MODE (reg)), 4358 UNITS_PER_WORD) 4359 && WORD_REGISTER_OPERATIONS))) 4360 { 4361 /* An OP_INOUT is required when reloading a subreg of a 4362 mode wider than a word to ensure that data beyond the 4363 word being reloaded is preserved. Also automatically 4364 ensure that strict_low_part reloads are made into 4365 OP_INOUT which should already be true from the backend 4366 constraints. */ 4367 if (type == OP_OUT 4368 && (curr_static_id->operand[i].strict_low 4369 || read_modify_subreg_p (*loc))) 4370 type = OP_INOUT; 4371 loc = &SUBREG_REG (*loc); 4372 mode = GET_MODE (*loc); 4373 } 4374 } 4375 old = *loc; 4376 if (get_reload_reg (type, mode, old, goal_alt[i], 4377 loc != curr_id->operand_loc[i], "", &new_reg) 4378 && type != OP_OUT) 4379 { 4380 push_to_sequence (before); 4381 lra_emit_move (new_reg, old); 4382 before = get_insns (); 4383 end_sequence (); 4384 } 4385 *loc = new_reg; 4386 if (type != OP_IN 4387 && find_reg_note (curr_insn, REG_UNUSED, old) == NULL_RTX) 4388 { 4389 start_sequence (); 4390 lra_emit_move (type == OP_INOUT ? copy_rtx (old) : old, new_reg); 4391 emit_insn (after); 4392 after = get_insns (); 4393 end_sequence (); 4394 *loc = new_reg; 4395 } 4396 for (j = 0; j < goal_alt_dont_inherit_ops_num; j++) 4397 if (goal_alt_dont_inherit_ops[j] == i) 4398 { 4399 lra_set_regno_unique_value (REGNO (new_reg)); 4400 break; 4401 } 4402 lra_update_dup (curr_id, i); 4403 } 4404 else if (curr_static_id->operand[i].type == OP_IN 4405 && (curr_static_id->operand[goal_alt_matched[i][0]].type 4406 == OP_OUT 4407 || (curr_static_id->operand[goal_alt_matched[i][0]].type 4408 == OP_INOUT 4409 && (operands_match_p 4410 (*curr_id->operand_loc[i], 4411 *curr_id->operand_loc[goal_alt_matched[i][0]], 4412 -1))))) 4413 { 4414 /* generate reloads for input and matched outputs. */ 4415 match_inputs[0] = i; 4416 match_inputs[1] = -1; 4417 match_reload (goal_alt_matched[i][0], match_inputs, outputs, 4418 goal_alt[i], &before, &after, 4419 curr_static_id->operand_alternative 4420 [goal_alt_number * n_operands + goal_alt_matched[i][0]] 4421 .earlyclobber); 4422 } 4423 else if ((curr_static_id->operand[i].type == OP_OUT 4424 || (curr_static_id->operand[i].type == OP_INOUT 4425 && (operands_match_p 4426 (*curr_id->operand_loc[i], 4427 *curr_id->operand_loc[goal_alt_matched[i][0]], 4428 -1)))) 4429 && (curr_static_id->operand[goal_alt_matched[i][0]].type 4430 == OP_IN)) 4431 /* Generate reloads for output and matched inputs. */ 4432 match_reload (i, goal_alt_matched[i], outputs, goal_alt[i], &before, 4433 &after, curr_static_id->operand_alternative 4434 [goal_alt_number * n_operands + i].earlyclobber); 4435 else if (curr_static_id->operand[i].type == OP_IN 4436 && (curr_static_id->operand[goal_alt_matched[i][0]].type 4437 == OP_IN)) 4438 { 4439 /* Generate reloads for matched inputs. */ 4440 match_inputs[0] = i; 4441 for (j = 0; (k = goal_alt_matched[i][j]) >= 0; j++) 4442 match_inputs[j + 1] = k; 4443 match_inputs[j + 1] = -1; 4444 match_reload (-1, match_inputs, outputs, goal_alt[i], &before, 4445 &after, false); 4446 } 4447 else 4448 /* We must generate code in any case when function 4449 process_alt_operands decides that it is possible. */ 4450 gcc_unreachable (); 4451 4452 /* Memorise processed outputs so that output remaining to be processed 4453 can avoid using the same register value (see match_reload). */ 4454 if (curr_static_id->operand[i].type == OP_OUT) 4455 { 4456 outputs[n_outputs++] = i; 4457 outputs[n_outputs] = -1; 4458 } 4459 4460 if (optional_p) 4461 { 4462 rtx reg = op; 4463 4464 lra_assert (REG_P (reg)); 4465 regno = REGNO (reg); 4466 op = *curr_id->operand_loc[i]; /* Substitution. */ 4467 if (GET_CODE (op) == SUBREG) 4468 op = SUBREG_REG (op); 4469 gcc_assert (REG_P (op) && (int) REGNO (op) >= new_regno_start); 4470 bitmap_set_bit (&lra_optional_reload_pseudos, REGNO (op)); 4471 lra_reg_info[REGNO (op)].restore_rtx = reg; 4472 if (lra_dump_file != NULL) 4473 fprintf (lra_dump_file, 4474 " Making reload reg %d for reg %d optional\n", 4475 REGNO (op), regno); 4476 } 4477 } 4478 if (before != NULL_RTX || after != NULL_RTX 4479 || max_regno_before != max_reg_num ()) 4480 change_p = true; 4481 if (change_p) 4482 { 4483 lra_update_operator_dups (curr_id); 4484 /* Something changes -- process the insn. */ 4485 lra_update_insn_regno_info (curr_insn); 4486 } 4487 lra_process_new_insns (curr_insn, before, after, "Inserting insn reload"); 4488 return change_p; 4489 } 4490 4491 /* Return true if INSN satisfies all constraints. In other words, no 4492 reload insns are needed. */ 4493 bool 4494 lra_constrain_insn (rtx_insn *insn) 4495 { 4496 int saved_new_regno_start = new_regno_start; 4497 int saved_new_insn_uid_start = new_insn_uid_start; 4498 bool change_p; 4499 4500 curr_insn = insn; 4501 curr_id = lra_get_insn_recog_data (curr_insn); 4502 curr_static_id = curr_id->insn_static_data; 4503 new_insn_uid_start = get_max_uid (); 4504 new_regno_start = max_reg_num (); 4505 change_p = curr_insn_transform (true); 4506 new_regno_start = saved_new_regno_start; 4507 new_insn_uid_start = saved_new_insn_uid_start; 4508 return ! change_p; 4509 } 4510 4511 /* Return true if X is in LIST. */ 4512 static bool 4513 in_list_p (rtx x, rtx list) 4514 { 4515 for (; list != NULL_RTX; list = XEXP (list, 1)) 4516 if (XEXP (list, 0) == x) 4517 return true; 4518 return false; 4519 } 4520 4521 /* Return true if X contains an allocatable hard register (if 4522 HARD_REG_P) or a (spilled if SPILLED_P) pseudo. */ 4523 static bool 4524 contains_reg_p (rtx x, bool hard_reg_p, bool spilled_p) 4525 { 4526 int i, j; 4527 const char *fmt; 4528 enum rtx_code code; 4529 4530 code = GET_CODE (x); 4531 if (REG_P (x)) 4532 { 4533 int regno = REGNO (x); 4534 HARD_REG_SET alloc_regs; 4535 4536 if (hard_reg_p) 4537 { 4538 if (regno >= FIRST_PSEUDO_REGISTER) 4539 regno = lra_get_regno_hard_regno (regno); 4540 if (regno < 0) 4541 return false; 4542 COMPL_HARD_REG_SET (alloc_regs, lra_no_alloc_regs); 4543 return overlaps_hard_reg_set_p (alloc_regs, GET_MODE (x), regno); 4544 } 4545 else 4546 { 4547 if (regno < FIRST_PSEUDO_REGISTER) 4548 return false; 4549 if (! spilled_p) 4550 return true; 4551 return lra_get_regno_hard_regno (regno) < 0; 4552 } 4553 } 4554 fmt = GET_RTX_FORMAT (code); 4555 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4556 { 4557 if (fmt[i] == 'e') 4558 { 4559 if (contains_reg_p (XEXP (x, i), hard_reg_p, spilled_p)) 4560 return true; 4561 } 4562 else if (fmt[i] == 'E') 4563 { 4564 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 4565 if (contains_reg_p (XVECEXP (x, i, j), hard_reg_p, spilled_p)) 4566 return true; 4567 } 4568 } 4569 return false; 4570 } 4571 4572 /* Process all regs in location *LOC and change them on equivalent 4573 substitution. Return true if any change was done. */ 4574 static bool 4575 loc_equivalence_change_p (rtx *loc) 4576 { 4577 rtx subst, reg, x = *loc; 4578 bool result = false; 4579 enum rtx_code code = GET_CODE (x); 4580 const char *fmt; 4581 int i, j; 4582 4583 if (code == SUBREG) 4584 { 4585 reg = SUBREG_REG (x); 4586 if ((subst = get_equiv_with_elimination (reg, curr_insn)) != reg 4587 && GET_MODE (subst) == VOIDmode) 4588 { 4589 /* We cannot reload debug location. Simplify subreg here 4590 while we know the inner mode. */ 4591 *loc = simplify_gen_subreg (GET_MODE (x), subst, 4592 GET_MODE (reg), SUBREG_BYTE (x)); 4593 return true; 4594 } 4595 } 4596 if (code == REG && (subst = get_equiv_with_elimination (x, curr_insn)) != x) 4597 { 4598 *loc = subst; 4599 return true; 4600 } 4601 4602 /* Scan all the operand sub-expressions. */ 4603 fmt = GET_RTX_FORMAT (code); 4604 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4605 { 4606 if (fmt[i] == 'e') 4607 result = loc_equivalence_change_p (&XEXP (x, i)) || result; 4608 else if (fmt[i] == 'E') 4609 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 4610 result 4611 = loc_equivalence_change_p (&XVECEXP (x, i, j)) || result; 4612 } 4613 return result; 4614 } 4615 4616 /* Similar to loc_equivalence_change_p, but for use as 4617 simplify_replace_fn_rtx callback. DATA is insn for which the 4618 elimination is done. If it null we don't do the elimination. */ 4619 static rtx 4620 loc_equivalence_callback (rtx loc, const_rtx, void *data) 4621 { 4622 if (!REG_P (loc)) 4623 return NULL_RTX; 4624 4625 rtx subst = (data == NULL 4626 ? get_equiv (loc) : get_equiv_with_elimination (loc, (rtx_insn *) data)); 4627 if (subst != loc) 4628 return subst; 4629 4630 return NULL_RTX; 4631 } 4632 4633 /* Maximum number of generated reload insns per an insn. It is for 4634 preventing this pass cycling in a bug case. */ 4635 #define MAX_RELOAD_INSNS_NUMBER LRA_MAX_INSN_RELOADS 4636 4637 /* The current iteration number of this LRA pass. */ 4638 int lra_constraint_iter; 4639 4640 /* True if we substituted equiv which needs checking register 4641 allocation correctness because the equivalent value contains 4642 allocatable hard registers or when we restore multi-register 4643 pseudo. */ 4644 bool lra_risky_transformations_p; 4645 4646 /* Return true if REGNO is referenced in more than one block. */ 4647 static bool 4648 multi_block_pseudo_p (int regno) 4649 { 4650 basic_block bb = NULL; 4651 unsigned int uid; 4652 bitmap_iterator bi; 4653 4654 if (regno < FIRST_PSEUDO_REGISTER) 4655 return false; 4656 4657 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) 4658 if (bb == NULL) 4659 bb = BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn); 4660 else if (BLOCK_FOR_INSN (lra_insn_recog_data[uid]->insn) != bb) 4661 return true; 4662 return false; 4663 } 4664 4665 /* Return true if LIST contains a deleted insn. */ 4666 static bool 4667 contains_deleted_insn_p (rtx_insn_list *list) 4668 { 4669 for (; list != NULL_RTX; list = list->next ()) 4670 if (NOTE_P (list->insn ()) 4671 && NOTE_KIND (list->insn ()) == NOTE_INSN_DELETED) 4672 return true; 4673 return false; 4674 } 4675 4676 /* Return true if X contains a pseudo dying in INSN. */ 4677 static bool 4678 dead_pseudo_p (rtx x, rtx_insn *insn) 4679 { 4680 int i, j; 4681 const char *fmt; 4682 enum rtx_code code; 4683 4684 if (REG_P (x)) 4685 return (insn != NULL_RTX 4686 && find_regno_note (insn, REG_DEAD, REGNO (x)) != NULL_RTX); 4687 code = GET_CODE (x); 4688 fmt = GET_RTX_FORMAT (code); 4689 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4690 { 4691 if (fmt[i] == 'e') 4692 { 4693 if (dead_pseudo_p (XEXP (x, i), insn)) 4694 return true; 4695 } 4696 else if (fmt[i] == 'E') 4697 { 4698 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 4699 if (dead_pseudo_p (XVECEXP (x, i, j), insn)) 4700 return true; 4701 } 4702 } 4703 return false; 4704 } 4705 4706 /* Return true if INSN contains a dying pseudo in INSN right hand 4707 side. */ 4708 static bool 4709 insn_rhs_dead_pseudo_p (rtx_insn *insn) 4710 { 4711 rtx set = single_set (insn); 4712 4713 gcc_assert (set != NULL); 4714 return dead_pseudo_p (SET_SRC (set), insn); 4715 } 4716 4717 /* Return true if any init insn of REGNO contains a dying pseudo in 4718 insn right hand side. */ 4719 static bool 4720 init_insn_rhs_dead_pseudo_p (int regno) 4721 { 4722 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; 4723 4724 if (insns == NULL) 4725 return false; 4726 for (; insns != NULL_RTX; insns = insns->next ()) 4727 if (insn_rhs_dead_pseudo_p (insns->insn ())) 4728 return true; 4729 return false; 4730 } 4731 4732 /* Return TRUE if REGNO has a reverse equivalence. The equivalence is 4733 reverse only if we have one init insn with given REGNO as a 4734 source. */ 4735 static bool 4736 reverse_equiv_p (int regno) 4737 { 4738 rtx_insn_list *insns = ira_reg_equiv[regno].init_insns; 4739 rtx set; 4740 4741 if (insns == NULL) 4742 return false; 4743 if (! INSN_P (insns->insn ()) 4744 || insns->next () != NULL) 4745 return false; 4746 if ((set = single_set (insns->insn ())) == NULL_RTX) 4747 return false; 4748 return REG_P (SET_SRC (set)) && (int) REGNO (SET_SRC (set)) == regno; 4749 } 4750 4751 /* Return TRUE if REGNO was reloaded in an equivalence init insn. We 4752 call this function only for non-reverse equivalence. */ 4753 static bool 4754 contains_reloaded_insn_p (int regno) 4755 { 4756 rtx set; 4757 rtx_insn_list *list = ira_reg_equiv[regno].init_insns; 4758 4759 for (; list != NULL; list = list->next ()) 4760 if ((set = single_set (list->insn ())) == NULL_RTX 4761 || ! REG_P (SET_DEST (set)) 4762 || (int) REGNO (SET_DEST (set)) != regno) 4763 return true; 4764 return false; 4765 } 4766 4767 /* Entry function of LRA constraint pass. Return true if the 4768 constraint pass did change the code. */ 4769 bool 4770 lra_constraints (bool first_p) 4771 { 4772 bool changed_p; 4773 int i, hard_regno, new_insns_num; 4774 unsigned int min_len, new_min_len, uid; 4775 rtx set, x, reg, dest_reg; 4776 basic_block last_bb; 4777 bitmap_iterator bi; 4778 4779 lra_constraint_iter++; 4780 if (lra_dump_file != NULL) 4781 fprintf (lra_dump_file, "\n********** Local #%d: **********\n\n", 4782 lra_constraint_iter); 4783 changed_p = false; 4784 if (pic_offset_table_rtx 4785 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) 4786 lra_risky_transformations_p = true; 4787 else 4788 /* On the first iteration we should check IRA assignment 4789 correctness. In rare cases, the assignments can be wrong as 4790 early clobbers operands are ignored in IRA or usages of 4791 paradoxical sub-registers are not taken into account by 4792 IRA. */ 4793 lra_risky_transformations_p = first_p; 4794 new_insn_uid_start = get_max_uid (); 4795 new_regno_start = first_p ? lra_constraint_new_regno_start : max_reg_num (); 4796 /* Mark used hard regs for target stack size calulations. */ 4797 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 4798 if (lra_reg_info[i].nrefs != 0 4799 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) 4800 { 4801 int j, nregs; 4802 4803 nregs = hard_regno_nregs (hard_regno, lra_reg_info[i].biggest_mode); 4804 for (j = 0; j < nregs; j++) 4805 df_set_regs_ever_live (hard_regno + j, true); 4806 } 4807 /* Do elimination before the equivalence processing as we can spill 4808 some pseudos during elimination. */ 4809 lra_eliminate (false, first_p); 4810 auto_bitmap equiv_insn_bitmap (®_obstack); 4811 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 4812 if (lra_reg_info[i].nrefs != 0) 4813 { 4814 ira_reg_equiv[i].profitable_p = true; 4815 reg = regno_reg_rtx[i]; 4816 if (lra_get_regno_hard_regno (i) < 0 && (x = get_equiv (reg)) != reg) 4817 { 4818 bool pseudo_p = contains_reg_p (x, false, false); 4819 4820 /* After RTL transformation, we cannot guarantee that 4821 pseudo in the substitution was not reloaded which might 4822 make equivalence invalid. For example, in reverse 4823 equiv of p0 4824 4825 p0 <- ... 4826 ... 4827 equiv_mem <- p0 4828 4829 the memory address register was reloaded before the 2nd 4830 insn. */ 4831 if ((! first_p && pseudo_p) 4832 /* We don't use DF for compilation speed sake. So it 4833 is problematic to update live info when we use an 4834 equivalence containing pseudos in more than one 4835 BB. */ 4836 || (pseudo_p && multi_block_pseudo_p (i)) 4837 /* If an init insn was deleted for some reason, cancel 4838 the equiv. We could update the equiv insns after 4839 transformations including an equiv insn deletion 4840 but it is not worthy as such cases are extremely 4841 rare. */ 4842 || contains_deleted_insn_p (ira_reg_equiv[i].init_insns) 4843 /* If it is not a reverse equivalence, we check that a 4844 pseudo in rhs of the init insn is not dying in the 4845 insn. Otherwise, the live info at the beginning of 4846 the corresponding BB might be wrong after we 4847 removed the insn. When the equiv can be a 4848 constant, the right hand side of the init insn can 4849 be a pseudo. */ 4850 || (! reverse_equiv_p (i) 4851 && (init_insn_rhs_dead_pseudo_p (i) 4852 /* If we reloaded the pseudo in an equivalence 4853 init insn, we cannot remove the equiv init 4854 insns and the init insns might write into 4855 const memory in this case. */ 4856 || contains_reloaded_insn_p (i))) 4857 /* Prevent access beyond equivalent memory for 4858 paradoxical subregs. */ 4859 || (MEM_P (x) 4860 && maybe_gt (GET_MODE_SIZE (lra_reg_info[i].biggest_mode), 4861 GET_MODE_SIZE (GET_MODE (x)))) 4862 || (pic_offset_table_rtx 4863 && ((CONST_POOL_OK_P (PSEUDO_REGNO_MODE (i), x) 4864 && (targetm.preferred_reload_class 4865 (x, lra_get_allocno_class (i)) == NO_REGS)) 4866 || contains_symbol_ref_p (x)))) 4867 ira_reg_equiv[i].defined_p = false; 4868 if (contains_reg_p (x, false, true)) 4869 ira_reg_equiv[i].profitable_p = false; 4870 if (get_equiv (reg) != reg) 4871 bitmap_ior_into (equiv_insn_bitmap, &lra_reg_info[i].insn_bitmap); 4872 } 4873 } 4874 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 4875 update_equiv (i); 4876 /* We should add all insns containing pseudos which should be 4877 substituted by their equivalences. */ 4878 EXECUTE_IF_SET_IN_BITMAP (equiv_insn_bitmap, 0, uid, bi) 4879 lra_push_insn_by_uid (uid); 4880 min_len = lra_insn_stack_length (); 4881 new_insns_num = 0; 4882 last_bb = NULL; 4883 changed_p = false; 4884 while ((new_min_len = lra_insn_stack_length ()) != 0) 4885 { 4886 curr_insn = lra_pop_insn (); 4887 --new_min_len; 4888 curr_bb = BLOCK_FOR_INSN (curr_insn); 4889 if (curr_bb != last_bb) 4890 { 4891 last_bb = curr_bb; 4892 bb_reload_num = lra_curr_reload_num; 4893 } 4894 if (min_len > new_min_len) 4895 { 4896 min_len = new_min_len; 4897 new_insns_num = 0; 4898 } 4899 if (new_insns_num > MAX_RELOAD_INSNS_NUMBER) 4900 internal_error 4901 ("Max. number of generated reload insns per insn is achieved (%d)\n", 4902 MAX_RELOAD_INSNS_NUMBER); 4903 new_insns_num++; 4904 if (DEBUG_INSN_P (curr_insn)) 4905 { 4906 /* We need to check equivalence in debug insn and change 4907 pseudo to the equivalent value if necessary. */ 4908 curr_id = lra_get_insn_recog_data (curr_insn); 4909 if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn))) 4910 { 4911 rtx old = *curr_id->operand_loc[0]; 4912 *curr_id->operand_loc[0] 4913 = simplify_replace_fn_rtx (old, NULL_RTX, 4914 loc_equivalence_callback, curr_insn); 4915 if (old != *curr_id->operand_loc[0]) 4916 { 4917 lra_update_insn_regno_info (curr_insn); 4918 changed_p = true; 4919 } 4920 } 4921 } 4922 else if (INSN_P (curr_insn)) 4923 { 4924 if ((set = single_set (curr_insn)) != NULL_RTX) 4925 { 4926 dest_reg = SET_DEST (set); 4927 /* The equivalence pseudo could be set up as SUBREG in a 4928 case when it is a call restore insn in a mode 4929 different from the pseudo mode. */ 4930 if (GET_CODE (dest_reg) == SUBREG) 4931 dest_reg = SUBREG_REG (dest_reg); 4932 if ((REG_P (dest_reg) 4933 && (x = get_equiv (dest_reg)) != dest_reg 4934 /* Remove insns which set up a pseudo whose value 4935 cannot be changed. Such insns might be not in 4936 init_insns because we don't update equiv data 4937 during insn transformations. 4938 4939 As an example, let suppose that a pseudo got 4940 hard register and on the 1st pass was not 4941 changed to equivalent constant. We generate an 4942 additional insn setting up the pseudo because of 4943 secondary memory movement. Then the pseudo is 4944 spilled and we use the equiv constant. In this 4945 case we should remove the additional insn and 4946 this insn is not init_insns list. */ 4947 && (! MEM_P (x) || MEM_READONLY_P (x) 4948 /* Check that this is actually an insn setting 4949 up the equivalence. */ 4950 || in_list_p (curr_insn, 4951 ira_reg_equiv 4952 [REGNO (dest_reg)].init_insns))) 4953 || (((x = get_equiv (SET_SRC (set))) != SET_SRC (set)) 4954 && in_list_p (curr_insn, 4955 ira_reg_equiv 4956 [REGNO (SET_SRC (set))].init_insns))) 4957 { 4958 /* This is equiv init insn of pseudo which did not get a 4959 hard register -- remove the insn. */ 4960 if (lra_dump_file != NULL) 4961 { 4962 fprintf (lra_dump_file, 4963 " Removing equiv init insn %i (freq=%d)\n", 4964 INSN_UID (curr_insn), 4965 REG_FREQ_FROM_BB (BLOCK_FOR_INSN (curr_insn))); 4966 dump_insn_slim (lra_dump_file, curr_insn); 4967 } 4968 if (contains_reg_p (x, true, false)) 4969 lra_risky_transformations_p = true; 4970 lra_set_insn_deleted (curr_insn); 4971 continue; 4972 } 4973 } 4974 curr_id = lra_get_insn_recog_data (curr_insn); 4975 curr_static_id = curr_id->insn_static_data; 4976 init_curr_insn_input_reloads (); 4977 init_curr_operand_mode (); 4978 if (curr_insn_transform (false)) 4979 changed_p = true; 4980 /* Check non-transformed insns too for equiv change as USE 4981 or CLOBBER don't need reloads but can contain pseudos 4982 being changed on their equivalences. */ 4983 else if (bitmap_bit_p (equiv_insn_bitmap, INSN_UID (curr_insn)) 4984 && loc_equivalence_change_p (&PATTERN (curr_insn))) 4985 { 4986 lra_update_insn_regno_info (curr_insn); 4987 changed_p = true; 4988 } 4989 } 4990 } 4991 4992 /* If we used a new hard regno, changed_p should be true because the 4993 hard reg is assigned to a new pseudo. */ 4994 if (flag_checking && !changed_p) 4995 { 4996 for (i = FIRST_PSEUDO_REGISTER; i < new_regno_start; i++) 4997 if (lra_reg_info[i].nrefs != 0 4998 && (hard_regno = lra_get_regno_hard_regno (i)) >= 0) 4999 { 5000 int j, nregs = hard_regno_nregs (hard_regno, 5001 PSEUDO_REGNO_MODE (i)); 5002 5003 for (j = 0; j < nregs; j++) 5004 lra_assert (df_regs_ever_live_p (hard_regno + j)); 5005 } 5006 } 5007 return changed_p; 5008 } 5009 5010 static void initiate_invariants (void); 5011 static void finish_invariants (void); 5012 5013 /* Initiate the LRA constraint pass. It is done once per 5014 function. */ 5015 void 5016 lra_constraints_init (void) 5017 { 5018 initiate_invariants (); 5019 } 5020 5021 /* Finalize the LRA constraint pass. It is done once per 5022 function. */ 5023 void 5024 lra_constraints_finish (void) 5025 { 5026 finish_invariants (); 5027 } 5028 5029 5030 5031 /* Structure describes invariants for ineheritance. */ 5032 struct lra_invariant 5033 { 5034 /* The order number of the invariant. */ 5035 int num; 5036 /* The invariant RTX. */ 5037 rtx invariant_rtx; 5038 /* The origin insn of the invariant. */ 5039 rtx_insn *insn; 5040 }; 5041 5042 typedef lra_invariant invariant_t; 5043 typedef invariant_t *invariant_ptr_t; 5044 typedef const invariant_t *const_invariant_ptr_t; 5045 5046 /* Pointer to the inheritance invariants. */ 5047 static vec<invariant_ptr_t> invariants; 5048 5049 /* Allocation pool for the invariants. */ 5050 static object_allocator<lra_invariant> *invariants_pool; 5051 5052 /* Hash table for the invariants. */ 5053 static htab_t invariant_table; 5054 5055 /* Hash function for INVARIANT. */ 5056 static hashval_t 5057 invariant_hash (const void *invariant) 5058 { 5059 rtx inv = ((const_invariant_ptr_t) invariant)->invariant_rtx; 5060 return lra_rtx_hash (inv); 5061 } 5062 5063 /* Equal function for invariants INVARIANT1 and INVARIANT2. */ 5064 static int 5065 invariant_eq_p (const void *invariant1, const void *invariant2) 5066 { 5067 rtx inv1 = ((const_invariant_ptr_t) invariant1)->invariant_rtx; 5068 rtx inv2 = ((const_invariant_ptr_t) invariant2)->invariant_rtx; 5069 5070 return rtx_equal_p (inv1, inv2); 5071 } 5072 5073 /* Insert INVARIANT_RTX into the table if it is not there yet. Return 5074 invariant which is in the table. */ 5075 static invariant_ptr_t 5076 insert_invariant (rtx invariant_rtx) 5077 { 5078 void **entry_ptr; 5079 invariant_t invariant; 5080 invariant_ptr_t invariant_ptr; 5081 5082 invariant.invariant_rtx = invariant_rtx; 5083 entry_ptr = htab_find_slot (invariant_table, &invariant, INSERT); 5084 if (*entry_ptr == NULL) 5085 { 5086 invariant_ptr = invariants_pool->allocate (); 5087 invariant_ptr->invariant_rtx = invariant_rtx; 5088 invariant_ptr->insn = NULL; 5089 invariants.safe_push (invariant_ptr); 5090 *entry_ptr = (void *) invariant_ptr; 5091 } 5092 return (invariant_ptr_t) *entry_ptr; 5093 } 5094 5095 /* Initiate the invariant table. */ 5096 static void 5097 initiate_invariants (void) 5098 { 5099 invariants.create (100); 5100 invariants_pool 5101 = new object_allocator<lra_invariant> ("Inheritance invariants"); 5102 invariant_table = htab_create (100, invariant_hash, invariant_eq_p, NULL); 5103 } 5104 5105 /* Finish the invariant table. */ 5106 static void 5107 finish_invariants (void) 5108 { 5109 htab_delete (invariant_table); 5110 delete invariants_pool; 5111 invariants.release (); 5112 } 5113 5114 /* Make the invariant table empty. */ 5115 static void 5116 clear_invariants (void) 5117 { 5118 htab_empty (invariant_table); 5119 invariants_pool->release (); 5120 invariants.truncate (0); 5121 } 5122 5123 5124 5125 /* This page contains code to do inheritance/split 5126 transformations. */ 5127 5128 /* Number of reloads passed so far in current EBB. */ 5129 static int reloads_num; 5130 5131 /* Number of calls passed so far in current EBB. */ 5132 static int calls_num; 5133 5134 /* Current reload pseudo check for validity of elements in 5135 USAGE_INSNS. */ 5136 static int curr_usage_insns_check; 5137 5138 /* Info about last usage of registers in EBB to do inheritance/split 5139 transformation. Inheritance transformation is done from a spilled 5140 pseudo and split transformations from a hard register or a pseudo 5141 assigned to a hard register. */ 5142 struct usage_insns 5143 { 5144 /* If the value is equal to CURR_USAGE_INSNS_CHECK, then the member 5145 value INSNS is valid. The insns is chain of optional debug insns 5146 and a finishing non-debug insn using the corresponding reg. The 5147 value is also used to mark the registers which are set up in the 5148 current insn. The negated insn uid is used for this. */ 5149 int check; 5150 /* Value of global reloads_num at the last insn in INSNS. */ 5151 int reloads_num; 5152 /* Value of global reloads_nums at the last insn in INSNS. */ 5153 int calls_num; 5154 /* It can be true only for splitting. And it means that the restore 5155 insn should be put after insn given by the following member. */ 5156 bool after_p; 5157 /* Next insns in the current EBB which use the original reg and the 5158 original reg value is not changed between the current insn and 5159 the next insns. In order words, e.g. for inheritance, if we need 5160 to use the original reg value again in the next insns we can try 5161 to use the value in a hard register from a reload insn of the 5162 current insn. */ 5163 rtx insns; 5164 }; 5165 5166 /* Map: regno -> corresponding pseudo usage insns. */ 5167 static struct usage_insns *usage_insns; 5168 5169 static void 5170 setup_next_usage_insn (int regno, rtx insn, int reloads_num, bool after_p) 5171 { 5172 usage_insns[regno].check = curr_usage_insns_check; 5173 usage_insns[regno].insns = insn; 5174 usage_insns[regno].reloads_num = reloads_num; 5175 usage_insns[regno].calls_num = calls_num; 5176 usage_insns[regno].after_p = after_p; 5177 } 5178 5179 /* The function is used to form list REGNO usages which consists of 5180 optional debug insns finished by a non-debug insn using REGNO. 5181 RELOADS_NUM is current number of reload insns processed so far. */ 5182 static void 5183 add_next_usage_insn (int regno, rtx_insn *insn, int reloads_num) 5184 { 5185 rtx next_usage_insns; 5186 5187 if (usage_insns[regno].check == curr_usage_insns_check 5188 && (next_usage_insns = usage_insns[regno].insns) != NULL_RTX 5189 && DEBUG_INSN_P (insn)) 5190 { 5191 /* Check that we did not add the debug insn yet. */ 5192 if (next_usage_insns != insn 5193 && (GET_CODE (next_usage_insns) != INSN_LIST 5194 || XEXP (next_usage_insns, 0) != insn)) 5195 usage_insns[regno].insns = gen_rtx_INSN_LIST (VOIDmode, insn, 5196 next_usage_insns); 5197 } 5198 else if (NONDEBUG_INSN_P (insn)) 5199 setup_next_usage_insn (regno, insn, reloads_num, false); 5200 else 5201 usage_insns[regno].check = 0; 5202 } 5203 5204 /* Return first non-debug insn in list USAGE_INSNS. */ 5205 static rtx_insn * 5206 skip_usage_debug_insns (rtx usage_insns) 5207 { 5208 rtx insn; 5209 5210 /* Skip debug insns. */ 5211 for (insn = usage_insns; 5212 insn != NULL_RTX && GET_CODE (insn) == INSN_LIST; 5213 insn = XEXP (insn, 1)) 5214 ; 5215 return safe_as_a <rtx_insn *> (insn); 5216 } 5217 5218 /* Return true if we need secondary memory moves for insn in 5219 USAGE_INSNS after inserting inherited pseudo of class INHER_CL 5220 into the insn. */ 5221 static bool 5222 check_secondary_memory_needed_p (enum reg_class inher_cl ATTRIBUTE_UNUSED, 5223 rtx usage_insns ATTRIBUTE_UNUSED) 5224 { 5225 rtx_insn *insn; 5226 rtx set, dest; 5227 enum reg_class cl; 5228 5229 if (inher_cl == ALL_REGS 5230 || (insn = skip_usage_debug_insns (usage_insns)) == NULL_RTX) 5231 return false; 5232 lra_assert (INSN_P (insn)); 5233 if ((set = single_set (insn)) == NULL_RTX || ! REG_P (SET_DEST (set))) 5234 return false; 5235 dest = SET_DEST (set); 5236 if (! REG_P (dest)) 5237 return false; 5238 lra_assert (inher_cl != NO_REGS); 5239 cl = get_reg_class (REGNO (dest)); 5240 return (cl != NO_REGS && cl != ALL_REGS 5241 && targetm.secondary_memory_needed (GET_MODE (dest), inher_cl, cl)); 5242 } 5243 5244 /* Registers involved in inheritance/split in the current EBB 5245 (inheritance/split pseudos and original registers). */ 5246 static bitmap_head check_only_regs; 5247 5248 /* Reload pseudos cannot be involded in invariant inheritance in the 5249 current EBB. */ 5250 static bitmap_head invalid_invariant_regs; 5251 5252 /* Do inheritance transformations for insn INSN, which defines (if 5253 DEF_P) or uses ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which 5254 instruction in the EBB next uses ORIGINAL_REGNO; it has the same 5255 form as the "insns" field of usage_insns. Return true if we 5256 succeed in such transformation. 5257 5258 The transformations look like: 5259 5260 p <- ... i <- ... 5261 ... p <- i (new insn) 5262 ... => 5263 <- ... p ... <- ... i ... 5264 or 5265 ... i <- p (new insn) 5266 <- ... p ... <- ... i ... 5267 ... => 5268 <- ... p ... <- ... i ... 5269 where p is a spilled original pseudo and i is a new inheritance pseudo. 5270 5271 5272 The inheritance pseudo has the smallest class of two classes CL and 5273 class of ORIGINAL REGNO. */ 5274 static bool 5275 inherit_reload_reg (bool def_p, int original_regno, 5276 enum reg_class cl, rtx_insn *insn, rtx next_usage_insns) 5277 { 5278 if (optimize_function_for_size_p (cfun)) 5279 return false; 5280 5281 enum reg_class rclass = lra_get_allocno_class (original_regno); 5282 rtx original_reg = regno_reg_rtx[original_regno]; 5283 rtx new_reg, usage_insn; 5284 rtx_insn *new_insns; 5285 5286 lra_assert (! usage_insns[original_regno].after_p); 5287 if (lra_dump_file != NULL) 5288 fprintf (lra_dump_file, 5289 " <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<\n"); 5290 if (! ira_reg_classes_intersect_p[cl][rclass]) 5291 { 5292 if (lra_dump_file != NULL) 5293 { 5294 fprintf (lra_dump_file, 5295 " Rejecting inheritance for %d " 5296 "because of disjoint classes %s and %s\n", 5297 original_regno, reg_class_names[cl], 5298 reg_class_names[rclass]); 5299 fprintf (lra_dump_file, 5300 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 5301 } 5302 return false; 5303 } 5304 if ((ira_class_subset_p[cl][rclass] && cl != rclass) 5305 /* We don't use a subset of two classes because it can be 5306 NO_REGS. This transformation is still profitable in most 5307 cases even if the classes are not intersected as register 5308 move is probably cheaper than a memory load. */ 5309 || ira_class_hard_regs_num[cl] < ira_class_hard_regs_num[rclass]) 5310 { 5311 if (lra_dump_file != NULL) 5312 fprintf (lra_dump_file, " Use smallest class of %s and %s\n", 5313 reg_class_names[cl], reg_class_names[rclass]); 5314 5315 rclass = cl; 5316 } 5317 if (check_secondary_memory_needed_p (rclass, next_usage_insns)) 5318 { 5319 /* Reject inheritance resulting in secondary memory moves. 5320 Otherwise, there is a danger in LRA cycling. Also such 5321 transformation will be unprofitable. */ 5322 if (lra_dump_file != NULL) 5323 { 5324 rtx_insn *insn = skip_usage_debug_insns (next_usage_insns); 5325 rtx set = single_set (insn); 5326 5327 lra_assert (set != NULL_RTX); 5328 5329 rtx dest = SET_DEST (set); 5330 5331 lra_assert (REG_P (dest)); 5332 fprintf (lra_dump_file, 5333 " Rejecting inheritance for insn %d(%s)<-%d(%s) " 5334 "as secondary mem is needed\n", 5335 REGNO (dest), reg_class_names[get_reg_class (REGNO (dest))], 5336 original_regno, reg_class_names[rclass]); 5337 fprintf (lra_dump_file, 5338 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 5339 } 5340 return false; 5341 } 5342 new_reg = lra_create_new_reg (GET_MODE (original_reg), original_reg, 5343 rclass, "inheritance"); 5344 start_sequence (); 5345 if (def_p) 5346 lra_emit_move (original_reg, new_reg); 5347 else 5348 lra_emit_move (new_reg, original_reg); 5349 new_insns = get_insns (); 5350 end_sequence (); 5351 if (NEXT_INSN (new_insns) != NULL_RTX) 5352 { 5353 if (lra_dump_file != NULL) 5354 { 5355 fprintf (lra_dump_file, 5356 " Rejecting inheritance %d->%d " 5357 "as it results in 2 or more insns:\n", 5358 original_regno, REGNO (new_reg)); 5359 dump_rtl_slim (lra_dump_file, new_insns, NULL, -1, 0); 5360 fprintf (lra_dump_file, 5361 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 5362 } 5363 return false; 5364 } 5365 lra_substitute_pseudo_within_insn (insn, original_regno, new_reg, false); 5366 lra_update_insn_regno_info (insn); 5367 if (! def_p) 5368 /* We now have a new usage insn for original regno. */ 5369 setup_next_usage_insn (original_regno, new_insns, reloads_num, false); 5370 if (lra_dump_file != NULL) 5371 fprintf (lra_dump_file, " Original reg change %d->%d (bb%d):\n", 5372 original_regno, REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); 5373 lra_reg_info[REGNO (new_reg)].restore_rtx = regno_reg_rtx[original_regno]; 5374 bitmap_set_bit (&check_only_regs, REGNO (new_reg)); 5375 bitmap_set_bit (&check_only_regs, original_regno); 5376 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); 5377 if (def_p) 5378 lra_process_new_insns (insn, NULL, new_insns, 5379 "Add original<-inheritance"); 5380 else 5381 lra_process_new_insns (insn, new_insns, NULL, 5382 "Add inheritance<-original"); 5383 while (next_usage_insns != NULL_RTX) 5384 { 5385 if (GET_CODE (next_usage_insns) != INSN_LIST) 5386 { 5387 usage_insn = next_usage_insns; 5388 lra_assert (NONDEBUG_INSN_P (usage_insn)); 5389 next_usage_insns = NULL; 5390 } 5391 else 5392 { 5393 usage_insn = XEXP (next_usage_insns, 0); 5394 lra_assert (DEBUG_INSN_P (usage_insn)); 5395 next_usage_insns = XEXP (next_usage_insns, 1); 5396 } 5397 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, 5398 DEBUG_INSN_P (usage_insn)); 5399 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); 5400 if (lra_dump_file != NULL) 5401 { 5402 basic_block bb = BLOCK_FOR_INSN (usage_insn); 5403 fprintf (lra_dump_file, 5404 " Inheritance reuse change %d->%d (bb%d):\n", 5405 original_regno, REGNO (new_reg), 5406 bb ? bb->index : -1); 5407 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); 5408 } 5409 } 5410 if (lra_dump_file != NULL) 5411 fprintf (lra_dump_file, 5412 " >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"); 5413 return true; 5414 } 5415 5416 /* Return true if we need a caller save/restore for pseudo REGNO which 5417 was assigned to a hard register. */ 5418 static inline bool 5419 need_for_call_save_p (int regno) 5420 { 5421 lra_assert (regno >= FIRST_PSEUDO_REGISTER && reg_renumber[regno] >= 0); 5422 return (usage_insns[regno].calls_num < calls_num 5423 && (overlaps_hard_reg_set_p 5424 ((flag_ipa_ra && 5425 ! hard_reg_set_empty_p (lra_reg_info[regno].actual_call_used_reg_set)) 5426 ? lra_reg_info[regno].actual_call_used_reg_set 5427 : call_used_reg_set, 5428 PSEUDO_REGNO_MODE (regno), reg_renumber[regno]) 5429 || (targetm.hard_regno_call_part_clobbered 5430 (lra_reg_info[regno].call_insn, 5431 reg_renumber[regno], PSEUDO_REGNO_MODE (regno))))); 5432 } 5433 5434 /* Global registers occurring in the current EBB. */ 5435 static bitmap_head ebb_global_regs; 5436 5437 /* Return true if we need a split for hard register REGNO or pseudo 5438 REGNO which was assigned to a hard register. 5439 POTENTIAL_RELOAD_HARD_REGS contains hard registers which might be 5440 used for reloads since the EBB end. It is an approximation of the 5441 used hard registers in the split range. The exact value would 5442 require expensive calculations. If we were aggressive with 5443 splitting because of the approximation, the split pseudo will save 5444 the same hard register assignment and will be removed in the undo 5445 pass. We still need the approximation because too aggressive 5446 splitting would result in too inaccurate cost calculation in the 5447 assignment pass because of too many generated moves which will be 5448 probably removed in the undo pass. */ 5449 static inline bool 5450 need_for_split_p (HARD_REG_SET potential_reload_hard_regs, int regno) 5451 { 5452 int hard_regno = regno < FIRST_PSEUDO_REGISTER ? regno : reg_renumber[regno]; 5453 5454 lra_assert (hard_regno >= 0); 5455 return ((TEST_HARD_REG_BIT (potential_reload_hard_regs, hard_regno) 5456 /* Don't split eliminable hard registers, otherwise we can 5457 split hard registers like hard frame pointer, which 5458 lives on BB start/end according to DF-infrastructure, 5459 when there is a pseudo assigned to the register and 5460 living in the same BB. */ 5461 && (regno >= FIRST_PSEUDO_REGISTER 5462 || ! TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) 5463 && ! TEST_HARD_REG_BIT (lra_no_alloc_regs, hard_regno) 5464 /* Don't split call clobbered hard regs living through 5465 calls, otherwise we might have a check problem in the 5466 assign sub-pass as in the most cases (exception is a 5467 situation when lra_risky_transformations_p value is 5468 true) the assign pass assumes that all pseudos living 5469 through calls are assigned to call saved hard regs. */ 5470 && (regno >= FIRST_PSEUDO_REGISTER 5471 || ! TEST_HARD_REG_BIT (call_used_reg_set, regno) 5472 || usage_insns[regno].calls_num == calls_num) 5473 /* We need at least 2 reloads to make pseudo splitting 5474 profitable. We should provide hard regno splitting in 5475 any case to solve 1st insn scheduling problem when 5476 moving hard register definition up might result in 5477 impossibility to find hard register for reload pseudo of 5478 small register class. */ 5479 && (usage_insns[regno].reloads_num 5480 + (regno < FIRST_PSEUDO_REGISTER ? 0 : 3) < reloads_num) 5481 && (regno < FIRST_PSEUDO_REGISTER 5482 /* For short living pseudos, spilling + inheritance can 5483 be considered a substitution for splitting. 5484 Therefore we do not splitting for local pseudos. It 5485 decreases also aggressiveness of splitting. The 5486 minimal number of references is chosen taking into 5487 account that for 2 references splitting has no sense 5488 as we can just spill the pseudo. */ 5489 || (regno >= FIRST_PSEUDO_REGISTER 5490 && lra_reg_info[regno].nrefs > 3 5491 && bitmap_bit_p (&ebb_global_regs, regno)))) 5492 || (regno >= FIRST_PSEUDO_REGISTER && need_for_call_save_p (regno))); 5493 } 5494 5495 /* Return class for the split pseudo created from original pseudo with 5496 ALLOCNO_CLASS and MODE which got a hard register HARD_REGNO. We 5497 choose subclass of ALLOCNO_CLASS which contains HARD_REGNO and 5498 results in no secondary memory movements. */ 5499 static enum reg_class 5500 choose_split_class (enum reg_class allocno_class, 5501 int hard_regno ATTRIBUTE_UNUSED, 5502 machine_mode mode ATTRIBUTE_UNUSED) 5503 { 5504 int i; 5505 enum reg_class cl, best_cl = NO_REGS; 5506 enum reg_class hard_reg_class ATTRIBUTE_UNUSED 5507 = REGNO_REG_CLASS (hard_regno); 5508 5509 if (! targetm.secondary_memory_needed (mode, allocno_class, allocno_class) 5510 && TEST_HARD_REG_BIT (reg_class_contents[allocno_class], hard_regno)) 5511 return allocno_class; 5512 for (i = 0; 5513 (cl = reg_class_subclasses[allocno_class][i]) != LIM_REG_CLASSES; 5514 i++) 5515 if (! targetm.secondary_memory_needed (mode, cl, hard_reg_class) 5516 && ! targetm.secondary_memory_needed (mode, hard_reg_class, cl) 5517 && TEST_HARD_REG_BIT (reg_class_contents[cl], hard_regno) 5518 && (best_cl == NO_REGS 5519 || ira_class_hard_regs_num[best_cl] < ira_class_hard_regs_num[cl])) 5520 best_cl = cl; 5521 return best_cl; 5522 } 5523 5524 /* Copy any equivalence information from ORIGINAL_REGNO to NEW_REGNO. 5525 It only makes sense to call this function if NEW_REGNO is always 5526 equal to ORIGINAL_REGNO. */ 5527 5528 static void 5529 lra_copy_reg_equiv (unsigned int new_regno, unsigned int original_regno) 5530 { 5531 if (!ira_reg_equiv[original_regno].defined_p) 5532 return; 5533 5534 ira_expand_reg_equiv (); 5535 ira_reg_equiv[new_regno].defined_p = true; 5536 if (ira_reg_equiv[original_regno].memory) 5537 ira_reg_equiv[new_regno].memory 5538 = copy_rtx (ira_reg_equiv[original_regno].memory); 5539 if (ira_reg_equiv[original_regno].constant) 5540 ira_reg_equiv[new_regno].constant 5541 = copy_rtx (ira_reg_equiv[original_regno].constant); 5542 if (ira_reg_equiv[original_regno].invariant) 5543 ira_reg_equiv[new_regno].invariant 5544 = copy_rtx (ira_reg_equiv[original_regno].invariant); 5545 } 5546 5547 /* Do split transformations for insn INSN, which defines or uses 5548 ORIGINAL_REGNO. NEXT_USAGE_INSNS specifies which instruction in 5549 the EBB next uses ORIGINAL_REGNO; it has the same form as the 5550 "insns" field of usage_insns. If TO is not NULL, we don't use 5551 usage_insns, we put restore insns after TO insn. It is a case when 5552 we call it from lra_split_hard_reg_for, outside the inheritance 5553 pass. 5554 5555 The transformations look like: 5556 5557 p <- ... p <- ... 5558 ... s <- p (new insn -- save) 5559 ... => 5560 ... p <- s (new insn -- restore) 5561 <- ... p ... <- ... p ... 5562 or 5563 <- ... p ... <- ... p ... 5564 ... s <- p (new insn -- save) 5565 ... => 5566 ... p <- s (new insn -- restore) 5567 <- ... p ... <- ... p ... 5568 5569 where p is an original pseudo got a hard register or a hard 5570 register and s is a new split pseudo. The save is put before INSN 5571 if BEFORE_P is true. Return true if we succeed in such 5572 transformation. */ 5573 static bool 5574 split_reg (bool before_p, int original_regno, rtx_insn *insn, 5575 rtx next_usage_insns, rtx_insn *to) 5576 { 5577 enum reg_class rclass; 5578 rtx original_reg; 5579 int hard_regno, nregs; 5580 rtx new_reg, usage_insn; 5581 rtx_insn *restore, *save; 5582 bool after_p; 5583 bool call_save_p; 5584 machine_mode mode; 5585 5586 if (original_regno < FIRST_PSEUDO_REGISTER) 5587 { 5588 rclass = ira_allocno_class_translate[REGNO_REG_CLASS (original_regno)]; 5589 hard_regno = original_regno; 5590 call_save_p = false; 5591 nregs = 1; 5592 mode = lra_reg_info[hard_regno].biggest_mode; 5593 machine_mode reg_rtx_mode = GET_MODE (regno_reg_rtx[hard_regno]); 5594 /* A reg can have a biggest_mode of VOIDmode if it was only ever seen 5595 as part of a multi-word register. In that case, or if the biggest 5596 mode was larger than a register, just use the reg_rtx. Otherwise, 5597 limit the size to that of the biggest access in the function. */ 5598 if (mode == VOIDmode 5599 || paradoxical_subreg_p (mode, reg_rtx_mode)) 5600 { 5601 original_reg = regno_reg_rtx[hard_regno]; 5602 mode = reg_rtx_mode; 5603 } 5604 else 5605 original_reg = gen_rtx_REG (mode, hard_regno); 5606 } 5607 else 5608 { 5609 mode = PSEUDO_REGNO_MODE (original_regno); 5610 hard_regno = reg_renumber[original_regno]; 5611 nregs = hard_regno_nregs (hard_regno, mode); 5612 rclass = lra_get_allocno_class (original_regno); 5613 original_reg = regno_reg_rtx[original_regno]; 5614 call_save_p = need_for_call_save_p (original_regno); 5615 } 5616 lra_assert (hard_regno >= 0); 5617 if (lra_dump_file != NULL) 5618 fprintf (lra_dump_file, 5619 " ((((((((((((((((((((((((((((((((((((((((((((((((\n"); 5620 5621 if (call_save_p) 5622 { 5623 mode = HARD_REGNO_CALLER_SAVE_MODE (hard_regno, 5624 hard_regno_nregs (hard_regno, mode), 5625 mode); 5626 new_reg = lra_create_new_reg (mode, NULL_RTX, NO_REGS, "save"); 5627 } 5628 else 5629 { 5630 rclass = choose_split_class (rclass, hard_regno, mode); 5631 if (rclass == NO_REGS) 5632 { 5633 if (lra_dump_file != NULL) 5634 { 5635 fprintf (lra_dump_file, 5636 " Rejecting split of %d(%s): " 5637 "no good reg class for %d(%s)\n", 5638 original_regno, 5639 reg_class_names[lra_get_allocno_class (original_regno)], 5640 hard_regno, 5641 reg_class_names[REGNO_REG_CLASS (hard_regno)]); 5642 fprintf 5643 (lra_dump_file, 5644 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5645 } 5646 return false; 5647 } 5648 /* Split_if_necessary can split hard registers used as part of a 5649 multi-register mode but splits each register individually. The 5650 mode used for each independent register may not be supported 5651 so reject the split. Splitting the wider mode should theoretically 5652 be possible but is not implemented. */ 5653 if (!targetm.hard_regno_mode_ok (hard_regno, mode)) 5654 { 5655 if (lra_dump_file != NULL) 5656 { 5657 fprintf (lra_dump_file, 5658 " Rejecting split of %d(%s): unsuitable mode %s\n", 5659 original_regno, 5660 reg_class_names[lra_get_allocno_class (original_regno)], 5661 GET_MODE_NAME (mode)); 5662 fprintf 5663 (lra_dump_file, 5664 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5665 } 5666 return false; 5667 } 5668 new_reg = lra_create_new_reg (mode, original_reg, rclass, "split"); 5669 reg_renumber[REGNO (new_reg)] = hard_regno; 5670 } 5671 int new_regno = REGNO (new_reg); 5672 save = emit_spill_move (true, new_reg, original_reg); 5673 if (NEXT_INSN (save) != NULL_RTX && !call_save_p) 5674 { 5675 if (lra_dump_file != NULL) 5676 { 5677 fprintf 5678 (lra_dump_file, 5679 " Rejecting split %d->%d resulting in > 2 save insns:\n", 5680 original_regno, new_regno); 5681 dump_rtl_slim (lra_dump_file, save, NULL, -1, 0); 5682 fprintf (lra_dump_file, 5683 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5684 } 5685 return false; 5686 } 5687 restore = emit_spill_move (false, new_reg, original_reg); 5688 if (NEXT_INSN (restore) != NULL_RTX && !call_save_p) 5689 { 5690 if (lra_dump_file != NULL) 5691 { 5692 fprintf (lra_dump_file, 5693 " Rejecting split %d->%d " 5694 "resulting in > 2 restore insns:\n", 5695 original_regno, new_regno); 5696 dump_rtl_slim (lra_dump_file, restore, NULL, -1, 0); 5697 fprintf (lra_dump_file, 5698 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5699 } 5700 return false; 5701 } 5702 /* Transfer equivalence information to the spill register, so that 5703 if we fail to allocate the spill register, we have the option of 5704 rematerializing the original value instead of spilling to the stack. */ 5705 if (!HARD_REGISTER_NUM_P (original_regno) 5706 && mode == PSEUDO_REGNO_MODE (original_regno)) 5707 lra_copy_reg_equiv (new_regno, original_regno); 5708 lra_reg_info[new_regno].restore_rtx = regno_reg_rtx[original_regno]; 5709 bitmap_set_bit (&lra_split_regs, new_regno); 5710 if (to != NULL) 5711 { 5712 lra_assert (next_usage_insns == NULL); 5713 usage_insn = to; 5714 after_p = TRUE; 5715 } 5716 else 5717 { 5718 /* We need check_only_regs only inside the inheritance pass. */ 5719 bitmap_set_bit (&check_only_regs, new_regno); 5720 bitmap_set_bit (&check_only_regs, original_regno); 5721 after_p = usage_insns[original_regno].after_p; 5722 for (;;) 5723 { 5724 if (GET_CODE (next_usage_insns) != INSN_LIST) 5725 { 5726 usage_insn = next_usage_insns; 5727 break; 5728 } 5729 usage_insn = XEXP (next_usage_insns, 0); 5730 lra_assert (DEBUG_INSN_P (usage_insn)); 5731 next_usage_insns = XEXP (next_usage_insns, 1); 5732 lra_substitute_pseudo (&usage_insn, original_regno, new_reg, false, 5733 true); 5734 lra_update_insn_regno_info (as_a <rtx_insn *> (usage_insn)); 5735 if (lra_dump_file != NULL) 5736 { 5737 fprintf (lra_dump_file, " Split reuse change %d->%d:\n", 5738 original_regno, new_regno); 5739 dump_insn_slim (lra_dump_file, as_a <rtx_insn *> (usage_insn)); 5740 } 5741 } 5742 } 5743 lra_assert (NOTE_P (usage_insn) || NONDEBUG_INSN_P (usage_insn)); 5744 lra_assert (usage_insn != insn || (after_p && before_p)); 5745 lra_process_new_insns (as_a <rtx_insn *> (usage_insn), 5746 after_p ? NULL : restore, 5747 after_p ? restore : NULL, 5748 call_save_p 5749 ? "Add reg<-save" : "Add reg<-split"); 5750 lra_process_new_insns (insn, before_p ? save : NULL, 5751 before_p ? NULL : save, 5752 call_save_p 5753 ? "Add save<-reg" : "Add split<-reg"); 5754 if (nregs > 1) 5755 /* If we are trying to split multi-register. We should check 5756 conflicts on the next assignment sub-pass. IRA can allocate on 5757 sub-register levels, LRA do this on pseudos level right now and 5758 this discrepancy may create allocation conflicts after 5759 splitting. */ 5760 lra_risky_transformations_p = true; 5761 if (lra_dump_file != NULL) 5762 fprintf (lra_dump_file, 5763 " ))))))))))))))))))))))))))))))))))))))))))))))))\n"); 5764 return true; 5765 } 5766 5767 /* Split a hard reg for reload pseudo REGNO having RCLASS and living 5768 in the range [FROM, TO]. Return true if did a split. Otherwise, 5769 return false. */ 5770 bool 5771 spill_hard_reg_in_range (int regno, enum reg_class rclass, rtx_insn *from, rtx_insn *to) 5772 { 5773 int i, hard_regno; 5774 int rclass_size; 5775 rtx_insn *insn; 5776 unsigned int uid; 5777 bitmap_iterator bi; 5778 HARD_REG_SET ignore; 5779 5780 lra_assert (from != NULL && to != NULL); 5781 CLEAR_HARD_REG_SET (ignore); 5782 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi) 5783 { 5784 lra_insn_recog_data_t id = lra_insn_recog_data[uid]; 5785 struct lra_static_insn_data *static_id = id->insn_static_data; 5786 struct lra_insn_reg *reg; 5787 5788 for (reg = id->regs; reg != NULL; reg = reg->next) 5789 if (reg->regno < FIRST_PSEUDO_REGISTER) 5790 SET_HARD_REG_BIT (ignore, reg->regno); 5791 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) 5792 SET_HARD_REG_BIT (ignore, reg->regno); 5793 } 5794 rclass_size = ira_class_hard_regs_num[rclass]; 5795 for (i = 0; i < rclass_size; i++) 5796 { 5797 hard_regno = ira_class_hard_regs[rclass][i]; 5798 if (! TEST_HARD_REG_BIT (lra_reg_info[regno].conflict_hard_regs, hard_regno) 5799 || TEST_HARD_REG_BIT (ignore, hard_regno)) 5800 continue; 5801 for (insn = from; insn != NEXT_INSN (to); insn = NEXT_INSN (insn)) 5802 { 5803 struct lra_static_insn_data *static_id; 5804 struct lra_insn_reg *reg; 5805 5806 if (!INSN_P (insn)) 5807 continue; 5808 if (bitmap_bit_p (&lra_reg_info[hard_regno].insn_bitmap, 5809 INSN_UID (insn))) 5810 break; 5811 static_id = lra_get_insn_recog_data (insn)->insn_static_data; 5812 for (reg = static_id->hard_regs; reg != NULL; reg = reg->next) 5813 if (reg->regno == hard_regno) 5814 break; 5815 if (reg != NULL) 5816 break; 5817 } 5818 if (insn != NEXT_INSN (to)) 5819 continue; 5820 if (split_reg (TRUE, hard_regno, from, NULL, to)) 5821 return true; 5822 } 5823 return false; 5824 } 5825 5826 /* Recognize that we need a split transformation for insn INSN, which 5827 defines or uses REGNO in its insn biggest MODE (we use it only if 5828 REGNO is a hard register). POTENTIAL_RELOAD_HARD_REGS contains 5829 hard registers which might be used for reloads since the EBB end. 5830 Put the save before INSN if BEFORE_P is true. MAX_UID is maximla 5831 uid before starting INSN processing. Return true if we succeed in 5832 such transformation. */ 5833 static bool 5834 split_if_necessary (int regno, machine_mode mode, 5835 HARD_REG_SET potential_reload_hard_regs, 5836 bool before_p, rtx_insn *insn, int max_uid) 5837 { 5838 bool res = false; 5839 int i, nregs = 1; 5840 rtx next_usage_insns; 5841 5842 if (regno < FIRST_PSEUDO_REGISTER) 5843 nregs = hard_regno_nregs (regno, mode); 5844 for (i = 0; i < nregs; i++) 5845 if (usage_insns[regno + i].check == curr_usage_insns_check 5846 && (next_usage_insns = usage_insns[regno + i].insns) != NULL_RTX 5847 /* To avoid processing the register twice or more. */ 5848 && ((GET_CODE (next_usage_insns) != INSN_LIST 5849 && INSN_UID (next_usage_insns) < max_uid) 5850 || (GET_CODE (next_usage_insns) == INSN_LIST 5851 && (INSN_UID (XEXP (next_usage_insns, 0)) < max_uid))) 5852 && need_for_split_p (potential_reload_hard_regs, regno + i) 5853 && split_reg (before_p, regno + i, insn, next_usage_insns, NULL)) 5854 res = true; 5855 return res; 5856 } 5857 5858 /* Return TRUE if rtx X is considered as an invariant for 5859 inheritance. */ 5860 static bool 5861 invariant_p (const_rtx x) 5862 { 5863 machine_mode mode; 5864 const char *fmt; 5865 enum rtx_code code; 5866 int i, j; 5867 5868 if (side_effects_p (x)) 5869 return false; 5870 5871 code = GET_CODE (x); 5872 mode = GET_MODE (x); 5873 if (code == SUBREG) 5874 { 5875 x = SUBREG_REG (x); 5876 code = GET_CODE (x); 5877 mode = wider_subreg_mode (mode, GET_MODE (x)); 5878 } 5879 5880 if (MEM_P (x)) 5881 return false; 5882 5883 if (REG_P (x)) 5884 { 5885 int i, nregs, regno = REGNO (x); 5886 5887 if (regno >= FIRST_PSEUDO_REGISTER || regno == STACK_POINTER_REGNUM 5888 || TEST_HARD_REG_BIT (eliminable_regset, regno) 5889 || GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) 5890 return false; 5891 nregs = hard_regno_nregs (regno, mode); 5892 for (i = 0; i < nregs; i++) 5893 if (! fixed_regs[regno + i] 5894 /* A hard register may be clobbered in the current insn 5895 but we can ignore this case because if the hard 5896 register is used it should be set somewhere after the 5897 clobber. */ 5898 || bitmap_bit_p (&invalid_invariant_regs, regno + i)) 5899 return false; 5900 } 5901 fmt = GET_RTX_FORMAT (code); 5902 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 5903 { 5904 if (fmt[i] == 'e') 5905 { 5906 if (! invariant_p (XEXP (x, i))) 5907 return false; 5908 } 5909 else if (fmt[i] == 'E') 5910 { 5911 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 5912 if (! invariant_p (XVECEXP (x, i, j))) 5913 return false; 5914 } 5915 } 5916 return true; 5917 } 5918 5919 /* We have 'dest_reg <- invariant'. Let us try to make an invariant 5920 inheritance transformation (using dest_reg instead invariant in a 5921 subsequent insn). */ 5922 static bool 5923 process_invariant_for_inheritance (rtx dst_reg, rtx invariant_rtx) 5924 { 5925 invariant_ptr_t invariant_ptr; 5926 rtx_insn *insn, *new_insns; 5927 rtx insn_set, insn_reg, new_reg; 5928 int insn_regno; 5929 bool succ_p = false; 5930 int dst_regno = REGNO (dst_reg); 5931 machine_mode dst_mode = GET_MODE (dst_reg); 5932 enum reg_class cl = lra_get_allocno_class (dst_regno), insn_reg_cl; 5933 5934 invariant_ptr = insert_invariant (invariant_rtx); 5935 if ((insn = invariant_ptr->insn) != NULL_RTX) 5936 { 5937 /* We have a subsequent insn using the invariant. */ 5938 insn_set = single_set (insn); 5939 lra_assert (insn_set != NULL); 5940 insn_reg = SET_DEST (insn_set); 5941 lra_assert (REG_P (insn_reg)); 5942 insn_regno = REGNO (insn_reg); 5943 insn_reg_cl = lra_get_allocno_class (insn_regno); 5944 5945 if (dst_mode == GET_MODE (insn_reg) 5946 /* We should consider only result move reg insns which are 5947 cheap. */ 5948 && targetm.register_move_cost (dst_mode, cl, insn_reg_cl) == 2 5949 && targetm.register_move_cost (dst_mode, cl, cl) == 2) 5950 { 5951 if (lra_dump_file != NULL) 5952 fprintf (lra_dump_file, 5953 " [[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[[\n"); 5954 new_reg = lra_create_new_reg (dst_mode, dst_reg, 5955 cl, "invariant inheritance"); 5956 bitmap_set_bit (&lra_inheritance_pseudos, REGNO (new_reg)); 5957 bitmap_set_bit (&check_only_regs, REGNO (new_reg)); 5958 lra_reg_info[REGNO (new_reg)].restore_rtx = PATTERN (insn); 5959 start_sequence (); 5960 lra_emit_move (new_reg, dst_reg); 5961 new_insns = get_insns (); 5962 end_sequence (); 5963 lra_process_new_insns (curr_insn, NULL, new_insns, 5964 "Add invariant inheritance<-original"); 5965 start_sequence (); 5966 lra_emit_move (SET_DEST (insn_set), new_reg); 5967 new_insns = get_insns (); 5968 end_sequence (); 5969 lra_process_new_insns (insn, NULL, new_insns, 5970 "Changing reload<-inheritance"); 5971 lra_set_insn_deleted (insn); 5972 succ_p = true; 5973 if (lra_dump_file != NULL) 5974 { 5975 fprintf (lra_dump_file, 5976 " Invariant inheritance reuse change %d (bb%d):\n", 5977 REGNO (new_reg), BLOCK_FOR_INSN (insn)->index); 5978 dump_insn_slim (lra_dump_file, insn); 5979 fprintf (lra_dump_file, 5980 " ]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]]\n"); 5981 } 5982 } 5983 } 5984 invariant_ptr->insn = curr_insn; 5985 return succ_p; 5986 } 5987 5988 /* Check only registers living at the current program point in the 5989 current EBB. */ 5990 static bitmap_head live_regs; 5991 5992 /* Update live info in EBB given by its HEAD and TAIL insns after 5993 inheritance/split transformation. The function removes dead moves 5994 too. */ 5995 static void 5996 update_ebb_live_info (rtx_insn *head, rtx_insn *tail) 5997 { 5998 unsigned int j; 5999 int i, regno; 6000 bool live_p; 6001 rtx_insn *prev_insn; 6002 rtx set; 6003 bool remove_p; 6004 basic_block last_bb, prev_bb, curr_bb; 6005 bitmap_iterator bi; 6006 struct lra_insn_reg *reg; 6007 edge e; 6008 edge_iterator ei; 6009 6010 last_bb = BLOCK_FOR_INSN (tail); 6011 prev_bb = NULL; 6012 for (curr_insn = tail; 6013 curr_insn != PREV_INSN (head); 6014 curr_insn = prev_insn) 6015 { 6016 prev_insn = PREV_INSN (curr_insn); 6017 /* We need to process empty blocks too. They contain 6018 NOTE_INSN_BASIC_BLOCK referring for the basic block. */ 6019 if (NOTE_P (curr_insn) && NOTE_KIND (curr_insn) != NOTE_INSN_BASIC_BLOCK) 6020 continue; 6021 curr_bb = BLOCK_FOR_INSN (curr_insn); 6022 if (curr_bb != prev_bb) 6023 { 6024 if (prev_bb != NULL) 6025 { 6026 /* Update df_get_live_in (prev_bb): */ 6027 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) 6028 if (bitmap_bit_p (&live_regs, j)) 6029 bitmap_set_bit (df_get_live_in (prev_bb), j); 6030 else 6031 bitmap_clear_bit (df_get_live_in (prev_bb), j); 6032 } 6033 if (curr_bb != last_bb) 6034 { 6035 /* Update df_get_live_out (curr_bb): */ 6036 EXECUTE_IF_SET_IN_BITMAP (&check_only_regs, 0, j, bi) 6037 { 6038 live_p = bitmap_bit_p (&live_regs, j); 6039 if (! live_p) 6040 FOR_EACH_EDGE (e, ei, curr_bb->succs) 6041 if (bitmap_bit_p (df_get_live_in (e->dest), j)) 6042 { 6043 live_p = true; 6044 break; 6045 } 6046 if (live_p) 6047 bitmap_set_bit (df_get_live_out (curr_bb), j); 6048 else 6049 bitmap_clear_bit (df_get_live_out (curr_bb), j); 6050 } 6051 } 6052 prev_bb = curr_bb; 6053 bitmap_and (&live_regs, &check_only_regs, df_get_live_out (curr_bb)); 6054 } 6055 if (! NONDEBUG_INSN_P (curr_insn)) 6056 continue; 6057 curr_id = lra_get_insn_recog_data (curr_insn); 6058 curr_static_id = curr_id->insn_static_data; 6059 remove_p = false; 6060 if ((set = single_set (curr_insn)) != NULL_RTX 6061 && REG_P (SET_DEST (set)) 6062 && (regno = REGNO (SET_DEST (set))) >= FIRST_PSEUDO_REGISTER 6063 && SET_DEST (set) != pic_offset_table_rtx 6064 && bitmap_bit_p (&check_only_regs, regno) 6065 && ! bitmap_bit_p (&live_regs, regno)) 6066 remove_p = true; 6067 /* See which defined values die here. */ 6068 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 6069 if (reg->type == OP_OUT && ! reg->subreg_p) 6070 bitmap_clear_bit (&live_regs, reg->regno); 6071 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) 6072 if (reg->type == OP_OUT && ! reg->subreg_p) 6073 bitmap_clear_bit (&live_regs, reg->regno); 6074 if (curr_id->arg_hard_regs != NULL) 6075 /* Make clobbered argument hard registers die. */ 6076 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) 6077 if (regno >= FIRST_PSEUDO_REGISTER) 6078 bitmap_clear_bit (&live_regs, regno - FIRST_PSEUDO_REGISTER); 6079 /* Mark each used value as live. */ 6080 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 6081 if (reg->type != OP_OUT 6082 && bitmap_bit_p (&check_only_regs, reg->regno)) 6083 bitmap_set_bit (&live_regs, reg->regno); 6084 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) 6085 if (reg->type != OP_OUT 6086 && bitmap_bit_p (&check_only_regs, reg->regno)) 6087 bitmap_set_bit (&live_regs, reg->regno); 6088 if (curr_id->arg_hard_regs != NULL) 6089 /* Make used argument hard registers live. */ 6090 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) 6091 if (regno < FIRST_PSEUDO_REGISTER 6092 && bitmap_bit_p (&check_only_regs, regno)) 6093 bitmap_set_bit (&live_regs, regno); 6094 /* It is quite important to remove dead move insns because it 6095 means removing dead store. We don't need to process them for 6096 constraints. */ 6097 if (remove_p) 6098 { 6099 if (lra_dump_file != NULL) 6100 { 6101 fprintf (lra_dump_file, " Removing dead insn:\n "); 6102 dump_insn_slim (lra_dump_file, curr_insn); 6103 } 6104 lra_set_insn_deleted (curr_insn); 6105 } 6106 } 6107 } 6108 6109 /* The structure describes info to do an inheritance for the current 6110 insn. We need to collect such info first before doing the 6111 transformations because the transformations change the insn 6112 internal representation. */ 6113 struct to_inherit 6114 { 6115 /* Original regno. */ 6116 int regno; 6117 /* Subsequent insns which can inherit original reg value. */ 6118 rtx insns; 6119 }; 6120 6121 /* Array containing all info for doing inheritance from the current 6122 insn. */ 6123 static struct to_inherit to_inherit[LRA_MAX_INSN_RELOADS]; 6124 6125 /* Number elements in the previous array. */ 6126 static int to_inherit_num; 6127 6128 /* Add inheritance info REGNO and INSNS. Their meaning is described in 6129 structure to_inherit. */ 6130 static void 6131 add_to_inherit (int regno, rtx insns) 6132 { 6133 int i; 6134 6135 for (i = 0; i < to_inherit_num; i++) 6136 if (to_inherit[i].regno == regno) 6137 return; 6138 lra_assert (to_inherit_num < LRA_MAX_INSN_RELOADS); 6139 to_inherit[to_inherit_num].regno = regno; 6140 to_inherit[to_inherit_num++].insns = insns; 6141 } 6142 6143 /* Return the last non-debug insn in basic block BB, or the block begin 6144 note if none. */ 6145 static rtx_insn * 6146 get_last_insertion_point (basic_block bb) 6147 { 6148 rtx_insn *insn; 6149 6150 FOR_BB_INSNS_REVERSE (bb, insn) 6151 if (NONDEBUG_INSN_P (insn) || NOTE_INSN_BASIC_BLOCK_P (insn)) 6152 return insn; 6153 gcc_unreachable (); 6154 } 6155 6156 /* Set up RES by registers living on edges FROM except the edge (FROM, 6157 TO) or by registers set up in a jump insn in BB FROM. */ 6158 static void 6159 get_live_on_other_edges (basic_block from, basic_block to, bitmap res) 6160 { 6161 rtx_insn *last; 6162 struct lra_insn_reg *reg; 6163 edge e; 6164 edge_iterator ei; 6165 6166 lra_assert (to != NULL); 6167 bitmap_clear (res); 6168 FOR_EACH_EDGE (e, ei, from->succs) 6169 if (e->dest != to) 6170 bitmap_ior_into (res, df_get_live_in (e->dest)); 6171 last = get_last_insertion_point (from); 6172 if (! JUMP_P (last)) 6173 return; 6174 curr_id = lra_get_insn_recog_data (last); 6175 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 6176 if (reg->type != OP_IN) 6177 bitmap_set_bit (res, reg->regno); 6178 } 6179 6180 /* Used as a temporary results of some bitmap calculations. */ 6181 static bitmap_head temp_bitmap; 6182 6183 /* We split for reloads of small class of hard regs. The following 6184 defines how many hard regs the class should have to be qualified as 6185 small. The code is mostly oriented to x86/x86-64 architecture 6186 where some insns need to use only specific register or pair of 6187 registers and these register can live in RTL explicitly, e.g. for 6188 parameter passing. */ 6189 static const int max_small_class_regs_num = 2; 6190 6191 /* Do inheritance/split transformations in EBB starting with HEAD and 6192 finishing on TAIL. We process EBB insns in the reverse order. 6193 Return true if we did any inheritance/split transformation in the 6194 EBB. 6195 6196 We should avoid excessive splitting which results in worse code 6197 because of inaccurate cost calculations for spilling new split 6198 pseudos in such case. To achieve this we do splitting only if 6199 register pressure is high in given basic block and there are reload 6200 pseudos requiring hard registers. We could do more register 6201 pressure calculations at any given program point to avoid necessary 6202 splitting even more but it is to expensive and the current approach 6203 works well enough. */ 6204 static bool 6205 inherit_in_ebb (rtx_insn *head, rtx_insn *tail) 6206 { 6207 int i, src_regno, dst_regno, nregs; 6208 bool change_p, succ_p, update_reloads_num_p; 6209 rtx_insn *prev_insn, *last_insn; 6210 rtx next_usage_insns, curr_set; 6211 enum reg_class cl; 6212 struct lra_insn_reg *reg; 6213 basic_block last_processed_bb, curr_bb = NULL; 6214 HARD_REG_SET potential_reload_hard_regs, live_hard_regs; 6215 bitmap to_process; 6216 unsigned int j; 6217 bitmap_iterator bi; 6218 bool head_p, after_p; 6219 6220 change_p = false; 6221 curr_usage_insns_check++; 6222 clear_invariants (); 6223 reloads_num = calls_num = 0; 6224 bitmap_clear (&check_only_regs); 6225 bitmap_clear (&invalid_invariant_regs); 6226 last_processed_bb = NULL; 6227 CLEAR_HARD_REG_SET (potential_reload_hard_regs); 6228 COPY_HARD_REG_SET (live_hard_regs, eliminable_regset); 6229 IOR_HARD_REG_SET (live_hard_regs, lra_no_alloc_regs); 6230 /* We don't process new insns generated in the loop. */ 6231 for (curr_insn = tail; curr_insn != PREV_INSN (head); curr_insn = prev_insn) 6232 { 6233 prev_insn = PREV_INSN (curr_insn); 6234 if (BLOCK_FOR_INSN (curr_insn) != NULL) 6235 curr_bb = BLOCK_FOR_INSN (curr_insn); 6236 if (last_processed_bb != curr_bb) 6237 { 6238 /* We are at the end of BB. Add qualified living 6239 pseudos for potential splitting. */ 6240 to_process = df_get_live_out (curr_bb); 6241 if (last_processed_bb != NULL) 6242 { 6243 /* We are somewhere in the middle of EBB. */ 6244 get_live_on_other_edges (curr_bb, last_processed_bb, 6245 &temp_bitmap); 6246 to_process = &temp_bitmap; 6247 } 6248 last_processed_bb = curr_bb; 6249 last_insn = get_last_insertion_point (curr_bb); 6250 after_p = (! JUMP_P (last_insn) 6251 && (! CALL_P (last_insn) 6252 || (find_reg_note (last_insn, 6253 REG_NORETURN, NULL_RTX) == NULL_RTX 6254 && ! SIBLING_CALL_P (last_insn)))); 6255 CLEAR_HARD_REG_SET (potential_reload_hard_regs); 6256 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) 6257 { 6258 if ((int) j >= lra_constraint_new_regno_start) 6259 break; 6260 if (j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) 6261 { 6262 if (j < FIRST_PSEUDO_REGISTER) 6263 SET_HARD_REG_BIT (live_hard_regs, j); 6264 else 6265 add_to_hard_reg_set (&live_hard_regs, 6266 PSEUDO_REGNO_MODE (j), 6267 reg_renumber[j]); 6268 setup_next_usage_insn (j, last_insn, reloads_num, after_p); 6269 } 6270 } 6271 } 6272 src_regno = dst_regno = -1; 6273 curr_set = single_set (curr_insn); 6274 if (curr_set != NULL_RTX && REG_P (SET_DEST (curr_set))) 6275 dst_regno = REGNO (SET_DEST (curr_set)); 6276 if (curr_set != NULL_RTX && REG_P (SET_SRC (curr_set))) 6277 src_regno = REGNO (SET_SRC (curr_set)); 6278 update_reloads_num_p = true; 6279 if (src_regno < lra_constraint_new_regno_start 6280 && src_regno >= FIRST_PSEUDO_REGISTER 6281 && reg_renumber[src_regno] < 0 6282 && dst_regno >= lra_constraint_new_regno_start 6283 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS) 6284 { 6285 /* 'reload_pseudo <- original_pseudo'. */ 6286 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) 6287 reloads_num++; 6288 update_reloads_num_p = false; 6289 succ_p = false; 6290 if (usage_insns[src_regno].check == curr_usage_insns_check 6291 && (next_usage_insns = usage_insns[src_regno].insns) != NULL_RTX) 6292 succ_p = inherit_reload_reg (false, src_regno, cl, 6293 curr_insn, next_usage_insns); 6294 if (succ_p) 6295 change_p = true; 6296 else 6297 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); 6298 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 6299 IOR_HARD_REG_SET (potential_reload_hard_regs, 6300 reg_class_contents[cl]); 6301 } 6302 else if (src_regno < 0 6303 && dst_regno >= lra_constraint_new_regno_start 6304 && invariant_p (SET_SRC (curr_set)) 6305 && (cl = lra_get_allocno_class (dst_regno)) != NO_REGS 6306 && ! bitmap_bit_p (&invalid_invariant_regs, dst_regno) 6307 && ! bitmap_bit_p (&invalid_invariant_regs, 6308 ORIGINAL_REGNO(regno_reg_rtx[dst_regno]))) 6309 { 6310 /* 'reload_pseudo <- invariant'. */ 6311 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) 6312 reloads_num++; 6313 update_reloads_num_p = false; 6314 if (process_invariant_for_inheritance (SET_DEST (curr_set), SET_SRC (curr_set))) 6315 change_p = true; 6316 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 6317 IOR_HARD_REG_SET (potential_reload_hard_regs, 6318 reg_class_contents[cl]); 6319 } 6320 else if (src_regno >= lra_constraint_new_regno_start 6321 && dst_regno < lra_constraint_new_regno_start 6322 && dst_regno >= FIRST_PSEUDO_REGISTER 6323 && reg_renumber[dst_regno] < 0 6324 && (cl = lra_get_allocno_class (src_regno)) != NO_REGS 6325 && usage_insns[dst_regno].check == curr_usage_insns_check 6326 && (next_usage_insns 6327 = usage_insns[dst_regno].insns) != NULL_RTX) 6328 { 6329 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) 6330 reloads_num++; 6331 update_reloads_num_p = false; 6332 /* 'original_pseudo <- reload_pseudo'. */ 6333 if (! JUMP_P (curr_insn) 6334 && inherit_reload_reg (true, dst_regno, cl, 6335 curr_insn, next_usage_insns)) 6336 change_p = true; 6337 /* Invalidate. */ 6338 usage_insns[dst_regno].check = 0; 6339 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 6340 IOR_HARD_REG_SET (potential_reload_hard_regs, 6341 reg_class_contents[cl]); 6342 } 6343 else if (INSN_P (curr_insn)) 6344 { 6345 int iter; 6346 int max_uid = get_max_uid (); 6347 6348 curr_id = lra_get_insn_recog_data (curr_insn); 6349 curr_static_id = curr_id->insn_static_data; 6350 to_inherit_num = 0; 6351 /* Process insn definitions. */ 6352 for (iter = 0; iter < 2; iter++) 6353 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; 6354 reg != NULL; 6355 reg = reg->next) 6356 if (reg->type != OP_IN 6357 && (dst_regno = reg->regno) < lra_constraint_new_regno_start) 6358 { 6359 if (dst_regno >= FIRST_PSEUDO_REGISTER && reg->type == OP_OUT 6360 && reg_renumber[dst_regno] < 0 && ! reg->subreg_p 6361 && usage_insns[dst_regno].check == curr_usage_insns_check 6362 && (next_usage_insns 6363 = usage_insns[dst_regno].insns) != NULL_RTX) 6364 { 6365 struct lra_insn_reg *r; 6366 6367 for (r = curr_id->regs; r != NULL; r = r->next) 6368 if (r->type != OP_OUT && r->regno == dst_regno) 6369 break; 6370 /* Don't do inheritance if the pseudo is also 6371 used in the insn. */ 6372 if (r == NULL) 6373 /* We cannot do inheritance right now 6374 because the current insn reg info (chain 6375 regs) can change after that. */ 6376 add_to_inherit (dst_regno, next_usage_insns); 6377 } 6378 /* We cannot process one reg twice here because of 6379 usage_insns invalidation. */ 6380 if ((dst_regno < FIRST_PSEUDO_REGISTER 6381 || reg_renumber[dst_regno] >= 0) 6382 && ! reg->subreg_p && reg->type != OP_IN) 6383 { 6384 HARD_REG_SET s; 6385 6386 if (split_if_necessary (dst_regno, reg->biggest_mode, 6387 potential_reload_hard_regs, 6388 false, curr_insn, max_uid)) 6389 change_p = true; 6390 CLEAR_HARD_REG_SET (s); 6391 if (dst_regno < FIRST_PSEUDO_REGISTER) 6392 add_to_hard_reg_set (&s, reg->biggest_mode, dst_regno); 6393 else 6394 add_to_hard_reg_set (&s, PSEUDO_REGNO_MODE (dst_regno), 6395 reg_renumber[dst_regno]); 6396 AND_COMPL_HARD_REG_SET (live_hard_regs, s); 6397 AND_COMPL_HARD_REG_SET (potential_reload_hard_regs, s); 6398 } 6399 /* We should invalidate potential inheritance or 6400 splitting for the current insn usages to the next 6401 usage insns (see code below) as the output pseudo 6402 prevents this. */ 6403 if ((dst_regno >= FIRST_PSEUDO_REGISTER 6404 && reg_renumber[dst_regno] < 0) 6405 || (reg->type == OP_OUT && ! reg->subreg_p 6406 && (dst_regno < FIRST_PSEUDO_REGISTER 6407 || reg_renumber[dst_regno] >= 0))) 6408 { 6409 /* Invalidate and mark definitions. */ 6410 if (dst_regno >= FIRST_PSEUDO_REGISTER) 6411 usage_insns[dst_regno].check = -(int) INSN_UID (curr_insn); 6412 else 6413 { 6414 nregs = hard_regno_nregs (dst_regno, 6415 reg->biggest_mode); 6416 for (i = 0; i < nregs; i++) 6417 usage_insns[dst_regno + i].check 6418 = -(int) INSN_UID (curr_insn); 6419 } 6420 } 6421 } 6422 /* Process clobbered call regs. */ 6423 if (curr_id->arg_hard_regs != NULL) 6424 for (i = 0; (dst_regno = curr_id->arg_hard_regs[i]) >= 0; i++) 6425 if (dst_regno >= FIRST_PSEUDO_REGISTER) 6426 usage_insns[dst_regno - FIRST_PSEUDO_REGISTER].check 6427 = -(int) INSN_UID (curr_insn); 6428 if (! JUMP_P (curr_insn)) 6429 for (i = 0; i < to_inherit_num; i++) 6430 if (inherit_reload_reg (true, to_inherit[i].regno, 6431 ALL_REGS, curr_insn, 6432 to_inherit[i].insns)) 6433 change_p = true; 6434 if (CALL_P (curr_insn)) 6435 { 6436 rtx cheap, pat, dest; 6437 rtx_insn *restore; 6438 int regno, hard_regno; 6439 6440 calls_num++; 6441 if ((cheap = find_reg_note (curr_insn, 6442 REG_RETURNED, NULL_RTX)) != NULL_RTX 6443 && ((cheap = XEXP (cheap, 0)), true) 6444 && (regno = REGNO (cheap)) >= FIRST_PSEUDO_REGISTER 6445 && (hard_regno = reg_renumber[regno]) >= 0 6446 && usage_insns[regno].check == curr_usage_insns_check 6447 /* If there are pending saves/restores, the 6448 optimization is not worth. */ 6449 && usage_insns[regno].calls_num == calls_num - 1 6450 && TEST_HARD_REG_BIT (call_used_reg_set, hard_regno)) 6451 { 6452 /* Restore the pseudo from the call result as 6453 REG_RETURNED note says that the pseudo value is 6454 in the call result and the pseudo is an argument 6455 of the call. */ 6456 pat = PATTERN (curr_insn); 6457 if (GET_CODE (pat) == PARALLEL) 6458 pat = XVECEXP (pat, 0, 0); 6459 dest = SET_DEST (pat); 6460 /* For multiple return values dest is PARALLEL. 6461 Currently we handle only single return value case. */ 6462 if (REG_P (dest)) 6463 { 6464 start_sequence (); 6465 emit_move_insn (cheap, copy_rtx (dest)); 6466 restore = get_insns (); 6467 end_sequence (); 6468 lra_process_new_insns (curr_insn, NULL, restore, 6469 "Inserting call parameter restore"); 6470 /* We don't need to save/restore of the pseudo from 6471 this call. */ 6472 usage_insns[regno].calls_num = calls_num; 6473 bitmap_set_bit (&check_only_regs, regno); 6474 } 6475 } 6476 } 6477 to_inherit_num = 0; 6478 /* Process insn usages. */ 6479 for (iter = 0; iter < 2; iter++) 6480 for (reg = iter == 0 ? curr_id->regs : curr_static_id->hard_regs; 6481 reg != NULL; 6482 reg = reg->next) 6483 if ((reg->type != OP_OUT 6484 || (reg->type == OP_OUT && reg->subreg_p)) 6485 && (src_regno = reg->regno) < lra_constraint_new_regno_start) 6486 { 6487 if (src_regno >= FIRST_PSEUDO_REGISTER 6488 && reg_renumber[src_regno] < 0 && reg->type == OP_IN) 6489 { 6490 if (usage_insns[src_regno].check == curr_usage_insns_check 6491 && (next_usage_insns 6492 = usage_insns[src_regno].insns) != NULL_RTX 6493 && NONDEBUG_INSN_P (curr_insn)) 6494 add_to_inherit (src_regno, next_usage_insns); 6495 else if (usage_insns[src_regno].check 6496 != -(int) INSN_UID (curr_insn)) 6497 /* Add usages but only if the reg is not set up 6498 in the same insn. */ 6499 add_next_usage_insn (src_regno, curr_insn, reloads_num); 6500 } 6501 else if (src_regno < FIRST_PSEUDO_REGISTER 6502 || reg_renumber[src_regno] >= 0) 6503 { 6504 bool before_p; 6505 rtx_insn *use_insn = curr_insn; 6506 6507 before_p = (JUMP_P (curr_insn) 6508 || (CALL_P (curr_insn) && reg->type == OP_IN)); 6509 if (NONDEBUG_INSN_P (curr_insn) 6510 && (! JUMP_P (curr_insn) || reg->type == OP_IN) 6511 && split_if_necessary (src_regno, reg->biggest_mode, 6512 potential_reload_hard_regs, 6513 before_p, curr_insn, max_uid)) 6514 { 6515 if (reg->subreg_p) 6516 lra_risky_transformations_p = true; 6517 change_p = true; 6518 /* Invalidate. */ 6519 usage_insns[src_regno].check = 0; 6520 if (before_p) 6521 use_insn = PREV_INSN (curr_insn); 6522 } 6523 if (NONDEBUG_INSN_P (curr_insn)) 6524 { 6525 if (src_regno < FIRST_PSEUDO_REGISTER) 6526 add_to_hard_reg_set (&live_hard_regs, 6527 reg->biggest_mode, src_regno); 6528 else 6529 add_to_hard_reg_set (&live_hard_regs, 6530 PSEUDO_REGNO_MODE (src_regno), 6531 reg_renumber[src_regno]); 6532 } 6533 if (src_regno >= FIRST_PSEUDO_REGISTER) 6534 add_next_usage_insn (src_regno, use_insn, reloads_num); 6535 else 6536 { 6537 for (i = 0; i < hard_regno_nregs (src_regno, reg->biggest_mode); i++) 6538 add_next_usage_insn (src_regno + i, use_insn, reloads_num); 6539 } 6540 } 6541 } 6542 /* Process used call regs. */ 6543 if (curr_id->arg_hard_regs != NULL) 6544 for (i = 0; (src_regno = curr_id->arg_hard_regs[i]) >= 0; i++) 6545 if (src_regno < FIRST_PSEUDO_REGISTER) 6546 { 6547 SET_HARD_REG_BIT (live_hard_regs, src_regno); 6548 add_next_usage_insn (src_regno, curr_insn, reloads_num); 6549 } 6550 for (i = 0; i < to_inherit_num; i++) 6551 { 6552 src_regno = to_inherit[i].regno; 6553 if (inherit_reload_reg (false, src_regno, ALL_REGS, 6554 curr_insn, to_inherit[i].insns)) 6555 change_p = true; 6556 else 6557 setup_next_usage_insn (src_regno, curr_insn, reloads_num, false); 6558 } 6559 } 6560 if (update_reloads_num_p 6561 && NONDEBUG_INSN_P (curr_insn) && curr_set != NULL_RTX) 6562 { 6563 int regno = -1; 6564 if ((REG_P (SET_DEST (curr_set)) 6565 && (regno = REGNO (SET_DEST (curr_set))) >= lra_constraint_new_regno_start 6566 && reg_renumber[regno] < 0 6567 && (cl = lra_get_allocno_class (regno)) != NO_REGS) 6568 || (REG_P (SET_SRC (curr_set)) 6569 && (regno = REGNO (SET_SRC (curr_set))) >= lra_constraint_new_regno_start 6570 && reg_renumber[regno] < 0 6571 && (cl = lra_get_allocno_class (regno)) != NO_REGS)) 6572 { 6573 if (ira_class_hard_regs_num[cl] <= max_small_class_regs_num) 6574 reloads_num++; 6575 if (hard_reg_set_subset_p (reg_class_contents[cl], live_hard_regs)) 6576 IOR_HARD_REG_SET (potential_reload_hard_regs, 6577 reg_class_contents[cl]); 6578 } 6579 } 6580 if (NONDEBUG_INSN_P (curr_insn)) 6581 { 6582 int regno; 6583 6584 /* Invalidate invariants with changed regs. */ 6585 curr_id = lra_get_insn_recog_data (curr_insn); 6586 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 6587 if (reg->type != OP_IN) 6588 { 6589 bitmap_set_bit (&invalid_invariant_regs, reg->regno); 6590 bitmap_set_bit (&invalid_invariant_regs, 6591 ORIGINAL_REGNO (regno_reg_rtx[reg->regno])); 6592 } 6593 curr_static_id = curr_id->insn_static_data; 6594 for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) 6595 if (reg->type != OP_IN) 6596 bitmap_set_bit (&invalid_invariant_regs, reg->regno); 6597 if (curr_id->arg_hard_regs != NULL) 6598 for (i = 0; (regno = curr_id->arg_hard_regs[i]) >= 0; i++) 6599 if (regno >= FIRST_PSEUDO_REGISTER) 6600 bitmap_set_bit (&invalid_invariant_regs, 6601 regno - FIRST_PSEUDO_REGISTER); 6602 } 6603 /* We reached the start of the current basic block. */ 6604 if (prev_insn == NULL_RTX || prev_insn == PREV_INSN (head) 6605 || BLOCK_FOR_INSN (prev_insn) != curr_bb) 6606 { 6607 /* We reached the beginning of the current block -- do 6608 rest of spliting in the current BB. */ 6609 to_process = df_get_live_in (curr_bb); 6610 if (BLOCK_FOR_INSN (head) != curr_bb) 6611 { 6612 /* We are somewhere in the middle of EBB. */ 6613 get_live_on_other_edges (EDGE_PRED (curr_bb, 0)->src, 6614 curr_bb, &temp_bitmap); 6615 to_process = &temp_bitmap; 6616 } 6617 head_p = true; 6618 EXECUTE_IF_SET_IN_BITMAP (to_process, 0, j, bi) 6619 { 6620 if ((int) j >= lra_constraint_new_regno_start) 6621 break; 6622 if (((int) j < FIRST_PSEUDO_REGISTER || reg_renumber[j] >= 0) 6623 && usage_insns[j].check == curr_usage_insns_check 6624 && (next_usage_insns = usage_insns[j].insns) != NULL_RTX) 6625 { 6626 if (need_for_split_p (potential_reload_hard_regs, j)) 6627 { 6628 if (lra_dump_file != NULL && head_p) 6629 { 6630 fprintf (lra_dump_file, 6631 " ----------------------------------\n"); 6632 head_p = false; 6633 } 6634 if (split_reg (false, j, bb_note (curr_bb), 6635 next_usage_insns, NULL)) 6636 change_p = true; 6637 } 6638 usage_insns[j].check = 0; 6639 } 6640 } 6641 } 6642 } 6643 return change_p; 6644 } 6645 6646 /* This value affects EBB forming. If probability of edge from EBB to 6647 a BB is not greater than the following value, we don't add the BB 6648 to EBB. */ 6649 #define EBB_PROBABILITY_CUTOFF \ 6650 ((REG_BR_PROB_BASE * LRA_INHERITANCE_EBB_PROBABILITY_CUTOFF) / 100) 6651 6652 /* Current number of inheritance/split iteration. */ 6653 int lra_inheritance_iter; 6654 6655 /* Entry function for inheritance/split pass. */ 6656 void 6657 lra_inheritance (void) 6658 { 6659 int i; 6660 basic_block bb, start_bb; 6661 edge e; 6662 6663 lra_inheritance_iter++; 6664 if (lra_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) 6665 return; 6666 timevar_push (TV_LRA_INHERITANCE); 6667 if (lra_dump_file != NULL) 6668 fprintf (lra_dump_file, "\n********** Inheritance #%d: **********\n\n", 6669 lra_inheritance_iter); 6670 curr_usage_insns_check = 0; 6671 usage_insns = XNEWVEC (struct usage_insns, lra_constraint_new_regno_start); 6672 for (i = 0; i < lra_constraint_new_regno_start; i++) 6673 usage_insns[i].check = 0; 6674 bitmap_initialize (&check_only_regs, ®_obstack); 6675 bitmap_initialize (&invalid_invariant_regs, ®_obstack); 6676 bitmap_initialize (&live_regs, ®_obstack); 6677 bitmap_initialize (&temp_bitmap, ®_obstack); 6678 bitmap_initialize (&ebb_global_regs, ®_obstack); 6679 FOR_EACH_BB_FN (bb, cfun) 6680 { 6681 start_bb = bb; 6682 if (lra_dump_file != NULL) 6683 fprintf (lra_dump_file, "EBB"); 6684 /* Form a EBB starting with BB. */ 6685 bitmap_clear (&ebb_global_regs); 6686 bitmap_ior_into (&ebb_global_regs, df_get_live_in (bb)); 6687 for (;;) 6688 { 6689 if (lra_dump_file != NULL) 6690 fprintf (lra_dump_file, " %d", bb->index); 6691 if (bb->next_bb == EXIT_BLOCK_PTR_FOR_FN (cfun) 6692 || LABEL_P (BB_HEAD (bb->next_bb))) 6693 break; 6694 e = find_fallthru_edge (bb->succs); 6695 if (! e) 6696 break; 6697 if (e->probability.initialized_p () 6698 && e->probability.to_reg_br_prob_base () < EBB_PROBABILITY_CUTOFF) 6699 break; 6700 bb = bb->next_bb; 6701 } 6702 bitmap_ior_into (&ebb_global_regs, df_get_live_out (bb)); 6703 if (lra_dump_file != NULL) 6704 fprintf (lra_dump_file, "\n"); 6705 if (inherit_in_ebb (BB_HEAD (start_bb), BB_END (bb))) 6706 /* Remember that the EBB head and tail can change in 6707 inherit_in_ebb. */ 6708 update_ebb_live_info (BB_HEAD (start_bb), BB_END (bb)); 6709 } 6710 bitmap_release (&ebb_global_regs); 6711 bitmap_release (&temp_bitmap); 6712 bitmap_release (&live_regs); 6713 bitmap_release (&invalid_invariant_regs); 6714 bitmap_release (&check_only_regs); 6715 free (usage_insns); 6716 6717 timevar_pop (TV_LRA_INHERITANCE); 6718 } 6719 6720 6721 6722 /* This page contains code to undo failed inheritance/split 6723 transformations. */ 6724 6725 /* Current number of iteration undoing inheritance/split. */ 6726 int lra_undo_inheritance_iter; 6727 6728 /* Fix BB live info LIVE after removing pseudos created on pass doing 6729 inheritance/split which are REMOVED_PSEUDOS. */ 6730 static void 6731 fix_bb_live_info (bitmap live, bitmap removed_pseudos) 6732 { 6733 unsigned int regno; 6734 bitmap_iterator bi; 6735 6736 EXECUTE_IF_SET_IN_BITMAP (removed_pseudos, 0, regno, bi) 6737 if (bitmap_clear_bit (live, regno) 6738 && REG_P (lra_reg_info[regno].restore_rtx)) 6739 bitmap_set_bit (live, REGNO (lra_reg_info[regno].restore_rtx)); 6740 } 6741 6742 /* Return regno of the (subreg of) REG. Otherwise, return a negative 6743 number. */ 6744 static int 6745 get_regno (rtx reg) 6746 { 6747 if (GET_CODE (reg) == SUBREG) 6748 reg = SUBREG_REG (reg); 6749 if (REG_P (reg)) 6750 return REGNO (reg); 6751 return -1; 6752 } 6753 6754 /* Delete a move INSN with destination reg DREGNO and a previous 6755 clobber insn with the same regno. The inheritance/split code can 6756 generate moves with preceding clobber and when we delete such moves 6757 we should delete the clobber insn too to keep the correct life 6758 info. */ 6759 static void 6760 delete_move_and_clobber (rtx_insn *insn, int dregno) 6761 { 6762 rtx_insn *prev_insn = PREV_INSN (insn); 6763 6764 lra_set_insn_deleted (insn); 6765 lra_assert (dregno >= 0); 6766 if (prev_insn != NULL && NONDEBUG_INSN_P (prev_insn) 6767 && GET_CODE (PATTERN (prev_insn)) == CLOBBER 6768 && dregno == get_regno (XEXP (PATTERN (prev_insn), 0))) 6769 lra_set_insn_deleted (prev_insn); 6770 } 6771 6772 /* Remove inheritance/split pseudos which are in REMOVE_PSEUDOS and 6773 return true if we did any change. The undo transformations for 6774 inheritance looks like 6775 i <- i2 6776 p <- i => p <- i2 6777 or removing 6778 p <- i, i <- p, and i <- i3 6779 where p is original pseudo from which inheritance pseudo i was 6780 created, i and i3 are removed inheritance pseudos, i2 is another 6781 not removed inheritance pseudo. All split pseudos or other 6782 occurrences of removed inheritance pseudos are changed on the 6783 corresponding original pseudos. 6784 6785 The function also schedules insns changed and created during 6786 inheritance/split pass for processing by the subsequent constraint 6787 pass. */ 6788 static bool 6789 remove_inheritance_pseudos (bitmap remove_pseudos) 6790 { 6791 basic_block bb; 6792 int regno, sregno, prev_sregno, dregno; 6793 rtx restore_rtx; 6794 rtx set, prev_set; 6795 rtx_insn *prev_insn; 6796 bool change_p, done_p; 6797 6798 change_p = ! bitmap_empty_p (remove_pseudos); 6799 /* We cannot finish the function right away if CHANGE_P is true 6800 because we need to marks insns affected by previous 6801 inheritance/split pass for processing by the subsequent 6802 constraint pass. */ 6803 FOR_EACH_BB_FN (bb, cfun) 6804 { 6805 fix_bb_live_info (df_get_live_in (bb), remove_pseudos); 6806 fix_bb_live_info (df_get_live_out (bb), remove_pseudos); 6807 FOR_BB_INSNS_REVERSE (bb, curr_insn) 6808 { 6809 if (! INSN_P (curr_insn)) 6810 continue; 6811 done_p = false; 6812 sregno = dregno = -1; 6813 if (change_p && NONDEBUG_INSN_P (curr_insn) 6814 && (set = single_set (curr_insn)) != NULL_RTX) 6815 { 6816 dregno = get_regno (SET_DEST (set)); 6817 sregno = get_regno (SET_SRC (set)); 6818 } 6819 6820 if (sregno >= 0 && dregno >= 0) 6821 { 6822 if (bitmap_bit_p (remove_pseudos, dregno) 6823 && ! REG_P (lra_reg_info[dregno].restore_rtx)) 6824 { 6825 /* invariant inheritance pseudo <- original pseudo */ 6826 if (lra_dump_file != NULL) 6827 { 6828 fprintf (lra_dump_file, " Removing invariant inheritance:\n"); 6829 dump_insn_slim (lra_dump_file, curr_insn); 6830 fprintf (lra_dump_file, "\n"); 6831 } 6832 delete_move_and_clobber (curr_insn, dregno); 6833 done_p = true; 6834 } 6835 else if (bitmap_bit_p (remove_pseudos, sregno) 6836 && ! REG_P (lra_reg_info[sregno].restore_rtx)) 6837 { 6838 /* reload pseudo <- invariant inheritance pseudo */ 6839 start_sequence (); 6840 /* We cannot just change the source. It might be 6841 an insn different from the move. */ 6842 emit_insn (lra_reg_info[sregno].restore_rtx); 6843 rtx_insn *new_insns = get_insns (); 6844 end_sequence (); 6845 lra_assert (single_set (new_insns) != NULL 6846 && SET_DEST (set) == SET_DEST (single_set (new_insns))); 6847 lra_process_new_insns (curr_insn, NULL, new_insns, 6848 "Changing reload<-invariant inheritance"); 6849 delete_move_and_clobber (curr_insn, dregno); 6850 done_p = true; 6851 } 6852 else if ((bitmap_bit_p (remove_pseudos, sregno) 6853 && (get_regno (lra_reg_info[sregno].restore_rtx) == dregno 6854 || (bitmap_bit_p (remove_pseudos, dregno) 6855 && get_regno (lra_reg_info[sregno].restore_rtx) >= 0 6856 && (get_regno (lra_reg_info[sregno].restore_rtx) 6857 == get_regno (lra_reg_info[dregno].restore_rtx))))) 6858 || (bitmap_bit_p (remove_pseudos, dregno) 6859 && get_regno (lra_reg_info[dregno].restore_rtx) == sregno)) 6860 /* One of the following cases: 6861 original <- removed inheritance pseudo 6862 removed inherit pseudo <- another removed inherit pseudo 6863 removed inherit pseudo <- original pseudo 6864 Or 6865 removed_split_pseudo <- original_reg 6866 original_reg <- removed_split_pseudo */ 6867 { 6868 if (lra_dump_file != NULL) 6869 { 6870 fprintf (lra_dump_file, " Removing %s:\n", 6871 bitmap_bit_p (&lra_split_regs, sregno) 6872 || bitmap_bit_p (&lra_split_regs, dregno) 6873 ? "split" : "inheritance"); 6874 dump_insn_slim (lra_dump_file, curr_insn); 6875 } 6876 delete_move_and_clobber (curr_insn, dregno); 6877 done_p = true; 6878 } 6879 else if (bitmap_bit_p (remove_pseudos, sregno) 6880 && bitmap_bit_p (&lra_inheritance_pseudos, sregno)) 6881 { 6882 /* Search the following pattern: 6883 inherit_or_split_pseudo1 <- inherit_or_split_pseudo2 6884 original_pseudo <- inherit_or_split_pseudo1 6885 where the 2nd insn is the current insn and 6886 inherit_or_split_pseudo2 is not removed. If it is found, 6887 change the current insn onto: 6888 original_pseudo <- inherit_or_split_pseudo2. */ 6889 for (prev_insn = PREV_INSN (curr_insn); 6890 prev_insn != NULL_RTX && ! NONDEBUG_INSN_P (prev_insn); 6891 prev_insn = PREV_INSN (prev_insn)) 6892 ; 6893 if (prev_insn != NULL_RTX && BLOCK_FOR_INSN (prev_insn) == bb 6894 && (prev_set = single_set (prev_insn)) != NULL_RTX 6895 /* There should be no subregs in insn we are 6896 searching because only the original reg might 6897 be in subreg when we changed the mode of 6898 load/store for splitting. */ 6899 && REG_P (SET_DEST (prev_set)) 6900 && REG_P (SET_SRC (prev_set)) 6901 && (int) REGNO (SET_DEST (prev_set)) == sregno 6902 && ((prev_sregno = REGNO (SET_SRC (prev_set))) 6903 >= FIRST_PSEUDO_REGISTER) 6904 && (lra_reg_info[prev_sregno].restore_rtx == NULL_RTX 6905 || 6906 /* As we consider chain of inheritance or 6907 splitting described in above comment we should 6908 check that sregno and prev_sregno were 6909 inheritance/split pseudos created from the 6910 same original regno. */ 6911 (get_regno (lra_reg_info[sregno].restore_rtx) >= 0 6912 && (get_regno (lra_reg_info[sregno].restore_rtx) 6913 == get_regno (lra_reg_info[prev_sregno].restore_rtx)))) 6914 && ! bitmap_bit_p (remove_pseudos, prev_sregno)) 6915 { 6916 lra_assert (GET_MODE (SET_SRC (prev_set)) 6917 == GET_MODE (regno_reg_rtx[sregno])); 6918 /* Although we have a single set, the insn can 6919 contain more one sregno register occurrence 6920 as a source. Change all occurrences. */ 6921 lra_substitute_pseudo_within_insn (curr_insn, sregno, 6922 SET_SRC (prev_set), 6923 false); 6924 /* As we are finishing with processing the insn 6925 here, check the destination too as it might 6926 inheritance pseudo for another pseudo. */ 6927 if (bitmap_bit_p (remove_pseudos, dregno) 6928 && bitmap_bit_p (&lra_inheritance_pseudos, dregno) 6929 && (restore_rtx 6930 = lra_reg_info[dregno].restore_rtx) != NULL_RTX) 6931 { 6932 if (GET_CODE (SET_DEST (set)) == SUBREG) 6933 SUBREG_REG (SET_DEST (set)) = restore_rtx; 6934 else 6935 SET_DEST (set) = restore_rtx; 6936 } 6937 lra_push_insn_and_update_insn_regno_info (curr_insn); 6938 lra_set_used_insn_alternative_by_uid 6939 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); 6940 done_p = true; 6941 if (lra_dump_file != NULL) 6942 { 6943 fprintf (lra_dump_file, " Change reload insn:\n"); 6944 dump_insn_slim (lra_dump_file, curr_insn); 6945 } 6946 } 6947 } 6948 } 6949 if (! done_p) 6950 { 6951 struct lra_insn_reg *reg; 6952 bool restored_regs_p = false; 6953 bool kept_regs_p = false; 6954 6955 curr_id = lra_get_insn_recog_data (curr_insn); 6956 for (reg = curr_id->regs; reg != NULL; reg = reg->next) 6957 { 6958 regno = reg->regno; 6959 restore_rtx = lra_reg_info[regno].restore_rtx; 6960 if (restore_rtx != NULL_RTX) 6961 { 6962 if (change_p && bitmap_bit_p (remove_pseudos, regno)) 6963 { 6964 lra_substitute_pseudo_within_insn 6965 (curr_insn, regno, restore_rtx, false); 6966 restored_regs_p = true; 6967 } 6968 else 6969 kept_regs_p = true; 6970 } 6971 } 6972 if (NONDEBUG_INSN_P (curr_insn) && kept_regs_p) 6973 { 6974 /* The instruction has changed since the previous 6975 constraints pass. */ 6976 lra_push_insn_and_update_insn_regno_info (curr_insn); 6977 lra_set_used_insn_alternative_by_uid 6978 (INSN_UID (curr_insn), LRA_UNKNOWN_ALT); 6979 } 6980 else if (restored_regs_p) 6981 /* The instruction has been restored to the form that 6982 it had during the previous constraints pass. */ 6983 lra_update_insn_regno_info (curr_insn); 6984 if (restored_regs_p && lra_dump_file != NULL) 6985 { 6986 fprintf (lra_dump_file, " Insn after restoring regs:\n"); 6987 dump_insn_slim (lra_dump_file, curr_insn); 6988 } 6989 } 6990 } 6991 } 6992 return change_p; 6993 } 6994 6995 /* If optional reload pseudos failed to get a hard register or was not 6996 inherited, it is better to remove optional reloads. We do this 6997 transformation after undoing inheritance to figure out necessity to 6998 remove optional reloads easier. Return true if we do any 6999 change. */ 7000 static bool 7001 undo_optional_reloads (void) 7002 { 7003 bool change_p, keep_p; 7004 unsigned int regno, uid; 7005 bitmap_iterator bi, bi2; 7006 rtx_insn *insn; 7007 rtx set, src, dest; 7008 auto_bitmap removed_optional_reload_pseudos (®_obstack); 7009 7010 bitmap_copy (removed_optional_reload_pseudos, &lra_optional_reload_pseudos); 7011 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) 7012 { 7013 keep_p = false; 7014 /* Keep optional reloads from previous subpasses. */ 7015 if (lra_reg_info[regno].restore_rtx == NULL_RTX 7016 /* If the original pseudo changed its allocation, just 7017 removing the optional pseudo is dangerous as the original 7018 pseudo will have longer live range. */ 7019 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] >= 0) 7020 keep_p = true; 7021 else if (reg_renumber[regno] >= 0) 7022 EXECUTE_IF_SET_IN_BITMAP (&lra_reg_info[regno].insn_bitmap, 0, uid, bi2) 7023 { 7024 insn = lra_insn_recog_data[uid]->insn; 7025 if ((set = single_set (insn)) == NULL_RTX) 7026 continue; 7027 src = SET_SRC (set); 7028 dest = SET_DEST (set); 7029 if (! REG_P (src) || ! REG_P (dest)) 7030 continue; 7031 if (REGNO (dest) == regno 7032 /* Ignore insn for optional reloads itself. */ 7033 && REGNO (lra_reg_info[regno].restore_rtx) != REGNO (src) 7034 /* Check only inheritance on last inheritance pass. */ 7035 && (int) REGNO (src) >= new_regno_start 7036 /* Check that the optional reload was inherited. */ 7037 && bitmap_bit_p (&lra_inheritance_pseudos, REGNO (src))) 7038 { 7039 keep_p = true; 7040 break; 7041 } 7042 } 7043 if (keep_p) 7044 { 7045 bitmap_clear_bit (removed_optional_reload_pseudos, regno); 7046 if (lra_dump_file != NULL) 7047 fprintf (lra_dump_file, "Keep optional reload reg %d\n", regno); 7048 } 7049 } 7050 change_p = ! bitmap_empty_p (removed_optional_reload_pseudos); 7051 auto_bitmap insn_bitmap (®_obstack); 7052 EXECUTE_IF_SET_IN_BITMAP (removed_optional_reload_pseudos, 0, regno, bi) 7053 { 7054 if (lra_dump_file != NULL) 7055 fprintf (lra_dump_file, "Remove optional reload reg %d\n", regno); 7056 bitmap_copy (insn_bitmap, &lra_reg_info[regno].insn_bitmap); 7057 EXECUTE_IF_SET_IN_BITMAP (insn_bitmap, 0, uid, bi2) 7058 { 7059 insn = lra_insn_recog_data[uid]->insn; 7060 if ((set = single_set (insn)) != NULL_RTX) 7061 { 7062 src = SET_SRC (set); 7063 dest = SET_DEST (set); 7064 if (REG_P (src) && REG_P (dest) 7065 && ((REGNO (src) == regno 7066 && (REGNO (lra_reg_info[regno].restore_rtx) 7067 == REGNO (dest))) 7068 || (REGNO (dest) == regno 7069 && (REGNO (lra_reg_info[regno].restore_rtx) 7070 == REGNO (src))))) 7071 { 7072 if (lra_dump_file != NULL) 7073 { 7074 fprintf (lra_dump_file, " Deleting move %u\n", 7075 INSN_UID (insn)); 7076 dump_insn_slim (lra_dump_file, insn); 7077 } 7078 delete_move_and_clobber (insn, REGNO (dest)); 7079 continue; 7080 } 7081 /* We should not worry about generation memory-memory 7082 moves here as if the corresponding inheritance did 7083 not work (inheritance pseudo did not get a hard reg), 7084 we remove the inheritance pseudo and the optional 7085 reload. */ 7086 } 7087 lra_substitute_pseudo_within_insn 7088 (insn, regno, lra_reg_info[regno].restore_rtx, false); 7089 lra_update_insn_regno_info (insn); 7090 if (lra_dump_file != NULL) 7091 { 7092 fprintf (lra_dump_file, 7093 " Restoring original insn:\n"); 7094 dump_insn_slim (lra_dump_file, insn); 7095 } 7096 } 7097 } 7098 /* Clear restore_regnos. */ 7099 EXECUTE_IF_SET_IN_BITMAP (&lra_optional_reload_pseudos, 0, regno, bi) 7100 lra_reg_info[regno].restore_rtx = NULL_RTX; 7101 return change_p; 7102 } 7103 7104 /* Entry function for undoing inheritance/split transformation. Return true 7105 if we did any RTL change in this pass. */ 7106 bool 7107 lra_undo_inheritance (void) 7108 { 7109 unsigned int regno; 7110 int hard_regno; 7111 int n_all_inherit, n_inherit, n_all_split, n_split; 7112 rtx restore_rtx; 7113 bitmap_iterator bi; 7114 bool change_p; 7115 7116 lra_undo_inheritance_iter++; 7117 if (lra_undo_inheritance_iter > LRA_MAX_INHERITANCE_PASSES) 7118 return false; 7119 if (lra_dump_file != NULL) 7120 fprintf (lra_dump_file, 7121 "\n********** Undoing inheritance #%d: **********\n\n", 7122 lra_undo_inheritance_iter); 7123 auto_bitmap remove_pseudos (®_obstack); 7124 n_inherit = n_all_inherit = 0; 7125 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) 7126 if (lra_reg_info[regno].restore_rtx != NULL_RTX) 7127 { 7128 n_all_inherit++; 7129 if (reg_renumber[regno] < 0 7130 /* If the original pseudo changed its allocation, just 7131 removing inheritance is dangerous as for changing 7132 allocation we used shorter live-ranges. */ 7133 && (! REG_P (lra_reg_info[regno].restore_rtx) 7134 || reg_renumber[REGNO (lra_reg_info[regno].restore_rtx)] < 0)) 7135 bitmap_set_bit (remove_pseudos, regno); 7136 else 7137 n_inherit++; 7138 } 7139 if (lra_dump_file != NULL && n_all_inherit != 0) 7140 fprintf (lra_dump_file, "Inherit %d out of %d (%.2f%%)\n", 7141 n_inherit, n_all_inherit, 7142 (double) n_inherit / n_all_inherit * 100); 7143 n_split = n_all_split = 0; 7144 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) 7145 if ((restore_rtx = lra_reg_info[regno].restore_rtx) != NULL_RTX) 7146 { 7147 int restore_regno = REGNO (restore_rtx); 7148 7149 n_all_split++; 7150 hard_regno = (restore_regno >= FIRST_PSEUDO_REGISTER 7151 ? reg_renumber[restore_regno] : restore_regno); 7152 if (hard_regno < 0 || reg_renumber[regno] == hard_regno) 7153 bitmap_set_bit (remove_pseudos, regno); 7154 else 7155 { 7156 n_split++; 7157 if (lra_dump_file != NULL) 7158 fprintf (lra_dump_file, " Keep split r%d (orig=r%d)\n", 7159 regno, restore_regno); 7160 } 7161 } 7162 if (lra_dump_file != NULL && n_all_split != 0) 7163 fprintf (lra_dump_file, "Split %d out of %d (%.2f%%)\n", 7164 n_split, n_all_split, 7165 (double) n_split / n_all_split * 100); 7166 change_p = remove_inheritance_pseudos (remove_pseudos); 7167 /* Clear restore_regnos. */ 7168 EXECUTE_IF_SET_IN_BITMAP (&lra_inheritance_pseudos, 0, regno, bi) 7169 lra_reg_info[regno].restore_rtx = NULL_RTX; 7170 EXECUTE_IF_SET_IN_BITMAP (&lra_split_regs, 0, regno, bi) 7171 lra_reg_info[regno].restore_rtx = NULL_RTX; 7172 change_p = undo_optional_reloads () || change_p; 7173 return change_p; 7174 } 7175