1 /* Integrated Register Allocator (IRA) entry point. 2 Copyright (C) 2006-2016 Free Software Foundation, Inc. 3 Contributed by Vladimir Makarov <vmakarov@redhat.com>. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it under 8 the terms of the GNU General Public License as published by the Free 9 Software Foundation; either version 3, or (at your option) any later 10 version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 13 WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 15 for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 /* The integrated register allocator (IRA) is a 22 regional register allocator performing graph coloring on a top-down 23 traversal of nested regions. Graph coloring in a region is based 24 on Chaitin-Briggs algorithm. It is called integrated because 25 register coalescing, register live range splitting, and choosing a 26 better hard register are done on-the-fly during coloring. Register 27 coalescing and choosing a cheaper hard register is done by hard 28 register preferencing during hard register assigning. The live 29 range splitting is a byproduct of the regional register allocation. 30 31 Major IRA notions are: 32 33 o *Region* is a part of CFG where graph coloring based on 34 Chaitin-Briggs algorithm is done. IRA can work on any set of 35 nested CFG regions forming a tree. Currently the regions are 36 the entire function for the root region and natural loops for 37 the other regions. Therefore data structure representing a 38 region is called loop_tree_node. 39 40 o *Allocno class* is a register class used for allocation of 41 given allocno. It means that only hard register of given 42 register class can be assigned to given allocno. In reality, 43 even smaller subset of (*profitable*) hard registers can be 44 assigned. In rare cases, the subset can be even smaller 45 because our modification of Chaitin-Briggs algorithm requires 46 that sets of hard registers can be assigned to allocnos forms a 47 forest, i.e. the sets can be ordered in a way where any 48 previous set is not intersected with given set or is a superset 49 of given set. 50 51 o *Pressure class* is a register class belonging to a set of 52 register classes containing all of the hard-registers available 53 for register allocation. The set of all pressure classes for a 54 target is defined in the corresponding machine-description file 55 according some criteria. Register pressure is calculated only 56 for pressure classes and it affects some IRA decisions as 57 forming allocation regions. 58 59 o *Allocno* represents the live range of a pseudo-register in a 60 region. Besides the obvious attributes like the corresponding 61 pseudo-register number, allocno class, conflicting allocnos and 62 conflicting hard-registers, there are a few allocno attributes 63 which are important for understanding the allocation algorithm: 64 65 - *Live ranges*. This is a list of ranges of *program points* 66 where the allocno lives. Program points represent places 67 where a pseudo can be born or become dead (there are 68 approximately two times more program points than the insns) 69 and they are represented by integers starting with 0. The 70 live ranges are used to find conflicts between allocnos. 71 They also play very important role for the transformation of 72 the IRA internal representation of several regions into a one 73 region representation. The later is used during the reload 74 pass work because each allocno represents all of the 75 corresponding pseudo-registers. 76 77 - *Hard-register costs*. This is a vector of size equal to the 78 number of available hard-registers of the allocno class. The 79 cost of a callee-clobbered hard-register for an allocno is 80 increased by the cost of save/restore code around the calls 81 through the given allocno's life. If the allocno is a move 82 instruction operand and another operand is a hard-register of 83 the allocno class, the cost of the hard-register is decreased 84 by the move cost. 85 86 When an allocno is assigned, the hard-register with minimal 87 full cost is used. Initially, a hard-register's full cost is 88 the corresponding value from the hard-register's cost vector. 89 If the allocno is connected by a *copy* (see below) to 90 another allocno which has just received a hard-register, the 91 cost of the hard-register is decreased. Before choosing a 92 hard-register for an allocno, the allocno's current costs of 93 the hard-registers are modified by the conflict hard-register 94 costs of all of the conflicting allocnos which are not 95 assigned yet. 96 97 - *Conflict hard-register costs*. This is a vector of the same 98 size as the hard-register costs vector. To permit an 99 unassigned allocno to get a better hard-register, IRA uses 100 this vector to calculate the final full cost of the 101 available hard-registers. Conflict hard-register costs of an 102 unassigned allocno are also changed with a change of the 103 hard-register cost of the allocno when a copy involving the 104 allocno is processed as described above. This is done to 105 show other unassigned allocnos that a given allocno prefers 106 some hard-registers in order to remove the move instruction 107 corresponding to the copy. 108 109 o *Cap*. If a pseudo-register does not live in a region but 110 lives in a nested region, IRA creates a special allocno called 111 a cap in the outer region. A region cap is also created for a 112 subregion cap. 113 114 o *Copy*. Allocnos can be connected by copies. Copies are used 115 to modify hard-register costs for allocnos during coloring. 116 Such modifications reflects a preference to use the same 117 hard-register for the allocnos connected by copies. Usually 118 copies are created for move insns (in this case it results in 119 register coalescing). But IRA also creates copies for operands 120 of an insn which should be assigned to the same hard-register 121 due to constraints in the machine description (it usually 122 results in removing a move generated in reload to satisfy 123 the constraints) and copies referring to the allocno which is 124 the output operand of an instruction and the allocno which is 125 an input operand dying in the instruction (creation of such 126 copies results in less register shuffling). IRA *does not* 127 create copies between the same register allocnos from different 128 regions because we use another technique for propagating 129 hard-register preference on the borders of regions. 130 131 Allocnos (including caps) for the upper region in the region tree 132 *accumulate* information important for coloring from allocnos with 133 the same pseudo-register from nested regions. This includes 134 hard-register and memory costs, conflicts with hard-registers, 135 allocno conflicts, allocno copies and more. *Thus, attributes for 136 allocnos in a region have the same values as if the region had no 137 subregions*. It means that attributes for allocnos in the 138 outermost region corresponding to the function have the same values 139 as though the allocation used only one region which is the entire 140 function. It also means that we can look at IRA work as if the 141 first IRA did allocation for all function then it improved the 142 allocation for loops then their subloops and so on. 143 144 IRA major passes are: 145 146 o Building IRA internal representation which consists of the 147 following subpasses: 148 149 * First, IRA builds regions and creates allocnos (file 150 ira-build.c) and initializes most of their attributes. 151 152 * Then IRA finds an allocno class for each allocno and 153 calculates its initial (non-accumulated) cost of memory and 154 each hard-register of its allocno class (file ira-cost.c). 155 156 * IRA creates live ranges of each allocno, calculates register 157 pressure for each pressure class in each region, sets up 158 conflict hard registers for each allocno and info about calls 159 the allocno lives through (file ira-lives.c). 160 161 * IRA removes low register pressure loops from the regions 162 mostly to speed IRA up (file ira-build.c). 163 164 * IRA propagates accumulated allocno info from lower region 165 allocnos to corresponding upper region allocnos (file 166 ira-build.c). 167 168 * IRA creates all caps (file ira-build.c). 169 170 * Having live-ranges of allocnos and their classes, IRA creates 171 conflicting allocnos for each allocno. Conflicting allocnos 172 are stored as a bit vector or array of pointers to the 173 conflicting allocnos whatever is more profitable (file 174 ira-conflicts.c). At this point IRA creates allocno copies. 175 176 o Coloring. Now IRA has all necessary info to start graph coloring 177 process. It is done in each region on top-down traverse of the 178 region tree (file ira-color.c). There are following subpasses: 179 180 * Finding profitable hard registers of corresponding allocno 181 class for each allocno. For example, only callee-saved hard 182 registers are frequently profitable for allocnos living 183 through colors. If the profitable hard register set of 184 allocno does not form a tree based on subset relation, we use 185 some approximation to form the tree. This approximation is 186 used to figure out trivial colorability of allocnos. The 187 approximation is a pretty rare case. 188 189 * Putting allocnos onto the coloring stack. IRA uses Briggs 190 optimistic coloring which is a major improvement over 191 Chaitin's coloring. Therefore IRA does not spill allocnos at 192 this point. There is some freedom in the order of putting 193 allocnos on the stack which can affect the final result of 194 the allocation. IRA uses some heuristics to improve the 195 order. The major one is to form *threads* from colorable 196 allocnos and push them on the stack by threads. Thread is a 197 set of non-conflicting colorable allocnos connected by 198 copies. The thread contains allocnos from the colorable 199 bucket or colorable allocnos already pushed onto the coloring 200 stack. Pushing thread allocnos one after another onto the 201 stack increases chances of removing copies when the allocnos 202 get the same hard reg. 203 204 We also use a modification of Chaitin-Briggs algorithm which 205 works for intersected register classes of allocnos. To 206 figure out trivial colorability of allocnos, the mentioned 207 above tree of hard register sets is used. To get an idea how 208 the algorithm works in i386 example, let us consider an 209 allocno to which any general hard register can be assigned. 210 If the allocno conflicts with eight allocnos to which only 211 EAX register can be assigned, given allocno is still 212 trivially colorable because all conflicting allocnos might be 213 assigned only to EAX and all other general hard registers are 214 still free. 215 216 To get an idea of the used trivial colorability criterion, it 217 is also useful to read article "Graph-Coloring Register 218 Allocation for Irregular Architectures" by Michael D. Smith 219 and Glen Holloway. Major difference between the article 220 approach and approach used in IRA is that Smith's approach 221 takes register classes only from machine description and IRA 222 calculate register classes from intermediate code too 223 (e.g. an explicit usage of hard registers in RTL code for 224 parameter passing can result in creation of additional 225 register classes which contain or exclude the hard 226 registers). That makes IRA approach useful for improving 227 coloring even for architectures with regular register files 228 and in fact some benchmarking shows the improvement for 229 regular class architectures is even bigger than for irregular 230 ones. Another difference is that Smith's approach chooses 231 intersection of classes of all insn operands in which a given 232 pseudo occurs. IRA can use bigger classes if it is still 233 more profitable than memory usage. 234 235 * Popping the allocnos from the stack and assigning them hard 236 registers. If IRA can not assign a hard register to an 237 allocno and the allocno is coalesced, IRA undoes the 238 coalescing and puts the uncoalesced allocnos onto the stack in 239 the hope that some such allocnos will get a hard register 240 separately. If IRA fails to assign hard register or memory 241 is more profitable for it, IRA spills the allocno. IRA 242 assigns the allocno the hard-register with minimal full 243 allocation cost which reflects the cost of usage of the 244 hard-register for the allocno and cost of usage of the 245 hard-register for allocnos conflicting with given allocno. 246 247 * Chaitin-Briggs coloring assigns as many pseudos as possible 248 to hard registers. After coloring we try to improve 249 allocation with cost point of view. We improve the 250 allocation by spilling some allocnos and assigning the freed 251 hard registers to other allocnos if it decreases the overall 252 allocation cost. 253 254 * After allocno assigning in the region, IRA modifies the hard 255 register and memory costs for the corresponding allocnos in 256 the subregions to reflect the cost of possible loads, stores, 257 or moves on the border of the region and its subregions. 258 When default regional allocation algorithm is used 259 (-fira-algorithm=mixed), IRA just propagates the assignment 260 for allocnos if the register pressure in the region for the 261 corresponding pressure class is less than number of available 262 hard registers for given pressure class. 263 264 o Spill/restore code moving. When IRA performs an allocation 265 by traversing regions in top-down order, it does not know what 266 happens below in the region tree. Therefore, sometimes IRA 267 misses opportunities to perform a better allocation. A simple 268 optimization tries to improve allocation in a region having 269 subregions and containing in another region. If the 270 corresponding allocnos in the subregion are spilled, it spills 271 the region allocno if it is profitable. The optimization 272 implements a simple iterative algorithm performing profitable 273 transformations while they are still possible. It is fast in 274 practice, so there is no real need for a better time complexity 275 algorithm. 276 277 o Code change. After coloring, two allocnos representing the 278 same pseudo-register outside and inside a region respectively 279 may be assigned to different locations (hard-registers or 280 memory). In this case IRA creates and uses a new 281 pseudo-register inside the region and adds code to move allocno 282 values on the region's borders. This is done during top-down 283 traversal of the regions (file ira-emit.c). In some 284 complicated cases IRA can create a new allocno to move allocno 285 values (e.g. when a swap of values stored in two hard-registers 286 is needed). At this stage, the new allocno is marked as 287 spilled. IRA still creates the pseudo-register and the moves 288 on the region borders even when both allocnos were assigned to 289 the same hard-register. If the reload pass spills a 290 pseudo-register for some reason, the effect will be smaller 291 because another allocno will still be in the hard-register. In 292 most cases, this is better then spilling both allocnos. If 293 reload does not change the allocation for the two 294 pseudo-registers, the trivial move will be removed by 295 post-reload optimizations. IRA does not generate moves for 296 allocnos assigned to the same hard register when the default 297 regional allocation algorithm is used and the register pressure 298 in the region for the corresponding pressure class is less than 299 number of available hard registers for given pressure class. 300 IRA also does some optimizations to remove redundant stores and 301 to reduce code duplication on the region borders. 302 303 o Flattening internal representation. After changing code, IRA 304 transforms its internal representation for several regions into 305 one region representation (file ira-build.c). This process is 306 called IR flattening. Such process is more complicated than IR 307 rebuilding would be, but is much faster. 308 309 o After IR flattening, IRA tries to assign hard registers to all 310 spilled allocnos. This is implemented by a simple and fast 311 priority coloring algorithm (see function 312 ira_reassign_conflict_allocnos::ira-color.c). Here new allocnos 313 created during the code change pass can be assigned to hard 314 registers. 315 316 o At the end IRA calls the reload pass. The reload pass 317 communicates with IRA through several functions in file 318 ira-color.c to improve its decisions in 319 320 * sharing stack slots for the spilled pseudos based on IRA info 321 about pseudo-register conflicts. 322 323 * reassigning hard-registers to all spilled pseudos at the end 324 of each reload iteration. 325 326 * choosing a better hard-register to spill based on IRA info 327 about pseudo-register live ranges and the register pressure 328 in places where the pseudo-register lives. 329 330 IRA uses a lot of data representing the target processors. These 331 data are initialized in file ira.c. 332 333 If function has no loops (or the loops are ignored when 334 -fira-algorithm=CB is used), we have classic Chaitin-Briggs 335 coloring (only instead of separate pass of coalescing, we use hard 336 register preferencing). In such case, IRA works much faster 337 because many things are not made (like IR flattening, the 338 spill/restore optimization, and the code change). 339 340 Literature is worth to read for better understanding the code: 341 342 o Preston Briggs, Keith D. Cooper, Linda Torczon. Improvements to 343 Graph Coloring Register Allocation. 344 345 o David Callahan, Brian Koblenz. Register allocation via 346 hierarchical graph coloring. 347 348 o Keith Cooper, Anshuman Dasgupta, Jason Eckhardt. Revisiting Graph 349 Coloring Register Allocation: A Study of the Chaitin-Briggs and 350 Callahan-Koblenz Algorithms. 351 352 o Guei-Yuan Lueh, Thomas Gross, and Ali-Reza Adl-Tabatabai. Global 353 Register Allocation Based on Graph Fusion. 354 355 o Michael D. Smith and Glenn Holloway. Graph-Coloring Register 356 Allocation for Irregular Architectures 357 358 o Vladimir Makarov. The Integrated Register Allocator for GCC. 359 360 o Vladimir Makarov. The top-down register allocator for irregular 361 register file architectures. 362 363 */ 364 365 366 #include "config.h" 367 #include "system.h" 368 #include "coretypes.h" 369 #include "backend.h" 370 #include "target.h" 371 #include "rtl.h" 372 #include "tree.h" 373 #include "df.h" 374 #include "tm_p.h" 375 #include "insn-config.h" 376 #include "regs.h" 377 #include "ira.h" 378 #include "ira-int.h" 379 #include "diagnostic-core.h" 380 #include "cfgrtl.h" 381 #include "cfgbuild.h" 382 #include "cfgcleanup.h" 383 #include "expr.h" 384 #include "tree-pass.h" 385 #include "output.h" 386 #include "reload.h" 387 #include "cfgloop.h" 388 #include "lra.h" 389 #include "dce.h" 390 #include "dbgcnt.h" 391 #include "rtl-iter.h" 392 #include "shrink-wrap.h" 393 #include "print-rtl.h" 394 395 struct target_ira default_target_ira; 396 struct target_ira_int default_target_ira_int; 397 #if SWITCHABLE_TARGET 398 struct target_ira *this_target_ira = &default_target_ira; 399 struct target_ira_int *this_target_ira_int = &default_target_ira_int; 400 #endif 401 402 /* A modified value of flag `-fira-verbose' used internally. */ 403 int internal_flag_ira_verbose; 404 405 /* Dump file of the allocator if it is not NULL. */ 406 FILE *ira_dump_file; 407 408 /* The number of elements in the following array. */ 409 int ira_spilled_reg_stack_slots_num; 410 411 /* The following array contains info about spilled pseudo-registers 412 stack slots used in current function so far. */ 413 struct ira_spilled_reg_stack_slot *ira_spilled_reg_stack_slots; 414 415 /* Correspondingly overall cost of the allocation, overall cost before 416 reload, cost of the allocnos assigned to hard-registers, cost of 417 the allocnos assigned to memory, cost of loads, stores and register 418 move insns generated for pseudo-register live range splitting (see 419 ira-emit.c). */ 420 int64_t ira_overall_cost, overall_cost_before; 421 int64_t ira_reg_cost, ira_mem_cost; 422 int64_t ira_load_cost, ira_store_cost, ira_shuffle_cost; 423 int ira_move_loops_num, ira_additional_jumps_num; 424 425 /* All registers that can be eliminated. */ 426 427 HARD_REG_SET eliminable_regset; 428 429 /* Value of max_reg_num () before IRA work start. This value helps 430 us to recognize a situation when new pseudos were created during 431 IRA work. */ 432 static int max_regno_before_ira; 433 434 /* Temporary hard reg set used for a different calculation. */ 435 static HARD_REG_SET temp_hard_regset; 436 437 #define last_mode_for_init_move_cost \ 438 (this_target_ira_int->x_last_mode_for_init_move_cost) 439 440 441 /* The function sets up the map IRA_REG_MODE_HARD_REGSET. */ 442 static void 443 setup_reg_mode_hard_regset (void) 444 { 445 int i, m, hard_regno; 446 447 for (m = 0; m < NUM_MACHINE_MODES; m++) 448 for (hard_regno = 0; hard_regno < FIRST_PSEUDO_REGISTER; hard_regno++) 449 { 450 CLEAR_HARD_REG_SET (ira_reg_mode_hard_regset[hard_regno][m]); 451 for (i = hard_regno_nregs[hard_regno][m] - 1; i >= 0; i--) 452 if (hard_regno + i < FIRST_PSEUDO_REGISTER) 453 SET_HARD_REG_BIT (ira_reg_mode_hard_regset[hard_regno][m], 454 hard_regno + i); 455 } 456 } 457 458 459 #define no_unit_alloc_regs \ 460 (this_target_ira_int->x_no_unit_alloc_regs) 461 462 /* The function sets up the three arrays declared above. */ 463 static void 464 setup_class_hard_regs (void) 465 { 466 int cl, i, hard_regno, n; 467 HARD_REG_SET processed_hard_reg_set; 468 469 ira_assert (SHRT_MAX >= FIRST_PSEUDO_REGISTER); 470 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) 471 { 472 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); 473 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 474 CLEAR_HARD_REG_SET (processed_hard_reg_set); 475 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 476 { 477 ira_non_ordered_class_hard_regs[cl][i] = -1; 478 ira_class_hard_reg_index[cl][i] = -1; 479 } 480 for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) 481 { 482 #ifdef REG_ALLOC_ORDER 483 hard_regno = reg_alloc_order[i]; 484 #else 485 hard_regno = i; 486 #endif 487 if (TEST_HARD_REG_BIT (processed_hard_reg_set, hard_regno)) 488 continue; 489 SET_HARD_REG_BIT (processed_hard_reg_set, hard_regno); 490 if (! TEST_HARD_REG_BIT (temp_hard_regset, hard_regno)) 491 ira_class_hard_reg_index[cl][hard_regno] = -1; 492 else 493 { 494 ira_class_hard_reg_index[cl][hard_regno] = n; 495 ira_class_hard_regs[cl][n++] = hard_regno; 496 } 497 } 498 ira_class_hard_regs_num[cl] = n; 499 for (n = 0, i = 0; i < FIRST_PSEUDO_REGISTER; i++) 500 if (TEST_HARD_REG_BIT (temp_hard_regset, i)) 501 ira_non_ordered_class_hard_regs[cl][n++] = i; 502 ira_assert (ira_class_hard_regs_num[cl] == n); 503 } 504 } 505 506 /* Set up global variables defining info about hard registers for the 507 allocation. These depend on USE_HARD_FRAME_P whose TRUE value means 508 that we can use the hard frame pointer for the allocation. */ 509 static void 510 setup_alloc_regs (bool use_hard_frame_p) 511 { 512 #ifdef ADJUST_REG_ALLOC_ORDER 513 ADJUST_REG_ALLOC_ORDER; 514 #endif 515 COPY_HARD_REG_SET (no_unit_alloc_regs, fixed_reg_set); 516 if (! use_hard_frame_p) 517 SET_HARD_REG_BIT (no_unit_alloc_regs, HARD_FRAME_POINTER_REGNUM); 518 setup_class_hard_regs (); 519 } 520 521 522 523 #define alloc_reg_class_subclasses \ 524 (this_target_ira_int->x_alloc_reg_class_subclasses) 525 526 /* Initialize the table of subclasses of each reg class. */ 527 static void 528 setup_reg_subclasses (void) 529 { 530 int i, j; 531 HARD_REG_SET temp_hard_regset2; 532 533 for (i = 0; i < N_REG_CLASSES; i++) 534 for (j = 0; j < N_REG_CLASSES; j++) 535 alloc_reg_class_subclasses[i][j] = LIM_REG_CLASSES; 536 537 for (i = 0; i < N_REG_CLASSES; i++) 538 { 539 if (i == (int) NO_REGS) 540 continue; 541 542 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); 543 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 544 if (hard_reg_set_empty_p (temp_hard_regset)) 545 continue; 546 for (j = 0; j < N_REG_CLASSES; j++) 547 if (i != j) 548 { 549 enum reg_class *p; 550 551 COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[j]); 552 AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); 553 if (! hard_reg_set_subset_p (temp_hard_regset, 554 temp_hard_regset2)) 555 continue; 556 p = &alloc_reg_class_subclasses[j][0]; 557 while (*p != LIM_REG_CLASSES) p++; 558 *p = (enum reg_class) i; 559 } 560 } 561 } 562 563 564 565 /* Set up IRA_MEMORY_MOVE_COST and IRA_MAX_MEMORY_MOVE_COST. */ 566 static void 567 setup_class_subset_and_memory_move_costs (void) 568 { 569 int cl, cl2, mode, cost; 570 HARD_REG_SET temp_hard_regset2; 571 572 for (mode = 0; mode < MAX_MACHINE_MODE; mode++) 573 ira_memory_move_cost[mode][NO_REGS][0] 574 = ira_memory_move_cost[mode][NO_REGS][1] = SHRT_MAX; 575 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) 576 { 577 if (cl != (int) NO_REGS) 578 for (mode = 0; mode < MAX_MACHINE_MODE; mode++) 579 { 580 ira_max_memory_move_cost[mode][cl][0] 581 = ira_memory_move_cost[mode][cl][0] 582 = memory_move_cost ((machine_mode) mode, 583 (reg_class_t) cl, false); 584 ira_max_memory_move_cost[mode][cl][1] 585 = ira_memory_move_cost[mode][cl][1] 586 = memory_move_cost ((machine_mode) mode, 587 (reg_class_t) cl, true); 588 /* Costs for NO_REGS are used in cost calculation on the 589 1st pass when the preferred register classes are not 590 known yet. In this case we take the best scenario. */ 591 if (ira_memory_move_cost[mode][NO_REGS][0] 592 > ira_memory_move_cost[mode][cl][0]) 593 ira_max_memory_move_cost[mode][NO_REGS][0] 594 = ira_memory_move_cost[mode][NO_REGS][0] 595 = ira_memory_move_cost[mode][cl][0]; 596 if (ira_memory_move_cost[mode][NO_REGS][1] 597 > ira_memory_move_cost[mode][cl][1]) 598 ira_max_memory_move_cost[mode][NO_REGS][1] 599 = ira_memory_move_cost[mode][NO_REGS][1] 600 = ira_memory_move_cost[mode][cl][1]; 601 } 602 } 603 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) 604 for (cl2 = (int) N_REG_CLASSES - 1; cl2 >= 0; cl2--) 605 { 606 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); 607 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 608 COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); 609 AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); 610 ira_class_subset_p[cl][cl2] 611 = hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2); 612 if (! hard_reg_set_empty_p (temp_hard_regset2) 613 && hard_reg_set_subset_p (reg_class_contents[cl2], 614 reg_class_contents[cl])) 615 for (mode = 0; mode < MAX_MACHINE_MODE; mode++) 616 { 617 cost = ira_memory_move_cost[mode][cl2][0]; 618 if (cost > ira_max_memory_move_cost[mode][cl][0]) 619 ira_max_memory_move_cost[mode][cl][0] = cost; 620 cost = ira_memory_move_cost[mode][cl2][1]; 621 if (cost > ira_max_memory_move_cost[mode][cl][1]) 622 ira_max_memory_move_cost[mode][cl][1] = cost; 623 } 624 } 625 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) 626 for (mode = 0; mode < MAX_MACHINE_MODE; mode++) 627 { 628 ira_memory_move_cost[mode][cl][0] 629 = ira_max_memory_move_cost[mode][cl][0]; 630 ira_memory_move_cost[mode][cl][1] 631 = ira_max_memory_move_cost[mode][cl][1]; 632 } 633 setup_reg_subclasses (); 634 } 635 636 637 638 /* Define the following macro if allocation through malloc if 639 preferable. */ 640 #define IRA_NO_OBSTACK 641 642 #ifndef IRA_NO_OBSTACK 643 /* Obstack used for storing all dynamic data (except bitmaps) of the 644 IRA. */ 645 static struct obstack ira_obstack; 646 #endif 647 648 /* Obstack used for storing all bitmaps of the IRA. */ 649 static struct bitmap_obstack ira_bitmap_obstack; 650 651 /* Allocate memory of size LEN for IRA data. */ 652 void * 653 ira_allocate (size_t len) 654 { 655 void *res; 656 657 #ifndef IRA_NO_OBSTACK 658 res = obstack_alloc (&ira_obstack, len); 659 #else 660 res = xmalloc (len); 661 #endif 662 return res; 663 } 664 665 /* Free memory ADDR allocated for IRA data. */ 666 void 667 ira_free (void *addr ATTRIBUTE_UNUSED) 668 { 669 #ifndef IRA_NO_OBSTACK 670 /* do nothing */ 671 #else 672 free (addr); 673 #endif 674 } 675 676 677 /* Allocate and returns bitmap for IRA. */ 678 bitmap 679 ira_allocate_bitmap (void) 680 { 681 return BITMAP_ALLOC (&ira_bitmap_obstack); 682 } 683 684 /* Free bitmap B allocated for IRA. */ 685 void 686 ira_free_bitmap (bitmap b ATTRIBUTE_UNUSED) 687 { 688 /* do nothing */ 689 } 690 691 692 693 /* Output information about allocation of all allocnos (except for 694 caps) into file F. */ 695 void 696 ira_print_disposition (FILE *f) 697 { 698 int i, n, max_regno; 699 ira_allocno_t a; 700 basic_block bb; 701 702 fprintf (f, "Disposition:"); 703 max_regno = max_reg_num (); 704 for (n = 0, i = FIRST_PSEUDO_REGISTER; i < max_regno; i++) 705 for (a = ira_regno_allocno_map[i]; 706 a != NULL; 707 a = ALLOCNO_NEXT_REGNO_ALLOCNO (a)) 708 { 709 if (n % 4 == 0) 710 fprintf (f, "\n"); 711 n++; 712 fprintf (f, " %4d:r%-4d", ALLOCNO_NUM (a), ALLOCNO_REGNO (a)); 713 if ((bb = ALLOCNO_LOOP_TREE_NODE (a)->bb) != NULL) 714 fprintf (f, "b%-3d", bb->index); 715 else 716 fprintf (f, "l%-3d", ALLOCNO_LOOP_TREE_NODE (a)->loop_num); 717 if (ALLOCNO_HARD_REGNO (a) >= 0) 718 fprintf (f, " %3d", ALLOCNO_HARD_REGNO (a)); 719 else 720 fprintf (f, " mem"); 721 } 722 fprintf (f, "\n"); 723 } 724 725 /* Outputs information about allocation of all allocnos into 726 stderr. */ 727 void 728 ira_debug_disposition (void) 729 { 730 ira_print_disposition (stderr); 731 } 732 733 734 735 /* Set up ira_stack_reg_pressure_class which is the biggest pressure 736 register class containing stack registers or NO_REGS if there are 737 no stack registers. To find this class, we iterate through all 738 register pressure classes and choose the first register pressure 739 class containing all the stack registers and having the biggest 740 size. */ 741 static void 742 setup_stack_reg_pressure_class (void) 743 { 744 ira_stack_reg_pressure_class = NO_REGS; 745 #ifdef STACK_REGS 746 { 747 int i, best, size; 748 enum reg_class cl; 749 HARD_REG_SET temp_hard_regset2; 750 751 CLEAR_HARD_REG_SET (temp_hard_regset); 752 for (i = FIRST_STACK_REG; i <= LAST_STACK_REG; i++) 753 SET_HARD_REG_BIT (temp_hard_regset, i); 754 best = 0; 755 for (i = 0; i < ira_pressure_classes_num; i++) 756 { 757 cl = ira_pressure_classes[i]; 758 COPY_HARD_REG_SET (temp_hard_regset2, temp_hard_regset); 759 AND_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); 760 size = hard_reg_set_size (temp_hard_regset2); 761 if (best < size) 762 { 763 best = size; 764 ira_stack_reg_pressure_class = cl; 765 } 766 } 767 } 768 #endif 769 } 770 771 /* Find pressure classes which are register classes for which we 772 calculate register pressure in IRA, register pressure sensitive 773 insn scheduling, and register pressure sensitive loop invariant 774 motion. 775 776 To make register pressure calculation easy, we always use 777 non-intersected register pressure classes. A move of hard 778 registers from one register pressure class is not more expensive 779 than load and store of the hard registers. Most likely an allocno 780 class will be a subset of a register pressure class and in many 781 cases a register pressure class. That makes usage of register 782 pressure classes a good approximation to find a high register 783 pressure. */ 784 static void 785 setup_pressure_classes (void) 786 { 787 int cost, i, n, curr; 788 int cl, cl2; 789 enum reg_class pressure_classes[N_REG_CLASSES]; 790 int m; 791 HARD_REG_SET temp_hard_regset2; 792 bool insert_p; 793 794 n = 0; 795 for (cl = 0; cl < N_REG_CLASSES; cl++) 796 { 797 if (ira_class_hard_regs_num[cl] == 0) 798 continue; 799 if (ira_class_hard_regs_num[cl] != 1 800 /* A register class without subclasses may contain a few 801 hard registers and movement between them is costly 802 (e.g. SPARC FPCC registers). We still should consider it 803 as a candidate for a pressure class. */ 804 && alloc_reg_class_subclasses[cl][0] < cl) 805 { 806 /* Check that the moves between any hard registers of the 807 current class are not more expensive for a legal mode 808 than load/store of the hard registers of the current 809 class. Such class is a potential candidate to be a 810 register pressure class. */ 811 for (m = 0; m < NUM_MACHINE_MODES; m++) 812 { 813 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); 814 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 815 AND_COMPL_HARD_REG_SET (temp_hard_regset, 816 ira_prohibited_class_mode_regs[cl][m]); 817 if (hard_reg_set_empty_p (temp_hard_regset)) 818 continue; 819 ira_init_register_move_cost_if_necessary ((machine_mode) m); 820 cost = ira_register_move_cost[m][cl][cl]; 821 if (cost <= ira_max_memory_move_cost[m][cl][1] 822 || cost <= ira_max_memory_move_cost[m][cl][0]) 823 break; 824 } 825 if (m >= NUM_MACHINE_MODES) 826 continue; 827 } 828 curr = 0; 829 insert_p = true; 830 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); 831 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 832 /* Remove so far added pressure classes which are subset of the 833 current candidate class. Prefer GENERAL_REGS as a pressure 834 register class to another class containing the same 835 allocatable hard registers. We do this because machine 836 dependent cost hooks might give wrong costs for the latter 837 class but always give the right cost for the former class 838 (GENERAL_REGS). */ 839 for (i = 0; i < n; i++) 840 { 841 cl2 = pressure_classes[i]; 842 COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl2]); 843 AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); 844 if (hard_reg_set_subset_p (temp_hard_regset, temp_hard_regset2) 845 && (! hard_reg_set_equal_p (temp_hard_regset, temp_hard_regset2) 846 || cl2 == (int) GENERAL_REGS)) 847 { 848 pressure_classes[curr++] = (enum reg_class) cl2; 849 insert_p = false; 850 continue; 851 } 852 if (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset) 853 && (! hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset) 854 || cl == (int) GENERAL_REGS)) 855 continue; 856 if (hard_reg_set_equal_p (temp_hard_regset2, temp_hard_regset)) 857 insert_p = false; 858 pressure_classes[curr++] = (enum reg_class) cl2; 859 } 860 /* If the current candidate is a subset of a so far added 861 pressure class, don't add it to the list of the pressure 862 classes. */ 863 if (insert_p) 864 pressure_classes[curr++] = (enum reg_class) cl; 865 n = curr; 866 } 867 #ifdef ENABLE_IRA_CHECKING 868 { 869 HARD_REG_SET ignore_hard_regs; 870 871 /* Check pressure classes correctness: here we check that hard 872 registers from all register pressure classes contains all hard 873 registers available for the allocation. */ 874 CLEAR_HARD_REG_SET (temp_hard_regset); 875 CLEAR_HARD_REG_SET (temp_hard_regset2); 876 COPY_HARD_REG_SET (ignore_hard_regs, no_unit_alloc_regs); 877 for (cl = 0; cl < LIM_REG_CLASSES; cl++) 878 { 879 /* For some targets (like MIPS with MD_REGS), there are some 880 classes with hard registers available for allocation but 881 not able to hold value of any mode. */ 882 for (m = 0; m < NUM_MACHINE_MODES; m++) 883 if (contains_reg_of_mode[cl][m]) 884 break; 885 if (m >= NUM_MACHINE_MODES) 886 { 887 IOR_HARD_REG_SET (ignore_hard_regs, reg_class_contents[cl]); 888 continue; 889 } 890 for (i = 0; i < n; i++) 891 if ((int) pressure_classes[i] == cl) 892 break; 893 IOR_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); 894 if (i < n) 895 IOR_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); 896 } 897 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 898 /* Some targets (like SPARC with ICC reg) have allocatable regs 899 for which no reg class is defined. */ 900 if (REGNO_REG_CLASS (i) == NO_REGS) 901 SET_HARD_REG_BIT (ignore_hard_regs, i); 902 AND_COMPL_HARD_REG_SET (temp_hard_regset, ignore_hard_regs); 903 AND_COMPL_HARD_REG_SET (temp_hard_regset2, ignore_hard_regs); 904 ira_assert (hard_reg_set_subset_p (temp_hard_regset2, temp_hard_regset)); 905 } 906 #endif 907 ira_pressure_classes_num = 0; 908 for (i = 0; i < n; i++) 909 { 910 cl = (int) pressure_classes[i]; 911 ira_reg_pressure_class_p[cl] = true; 912 ira_pressure_classes[ira_pressure_classes_num++] = (enum reg_class) cl; 913 } 914 setup_stack_reg_pressure_class (); 915 } 916 917 /* Set up IRA_UNIFORM_CLASS_P. Uniform class is a register class 918 whose register move cost between any registers of the class is the 919 same as for all its subclasses. We use the data to speed up the 920 2nd pass of calculations of allocno costs. */ 921 static void 922 setup_uniform_class_p (void) 923 { 924 int i, cl, cl2, m; 925 926 for (cl = 0; cl < N_REG_CLASSES; cl++) 927 { 928 ira_uniform_class_p[cl] = false; 929 if (ira_class_hard_regs_num[cl] == 0) 930 continue; 931 /* We can not use alloc_reg_class_subclasses here because move 932 cost hooks does not take into account that some registers are 933 unavailable for the subtarget. E.g. for i686, INT_SSE_REGS 934 is element of alloc_reg_class_subclasses for GENERAL_REGS 935 because SSE regs are unavailable. */ 936 for (i = 0; (cl2 = reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; i++) 937 { 938 if (ira_class_hard_regs_num[cl2] == 0) 939 continue; 940 for (m = 0; m < NUM_MACHINE_MODES; m++) 941 if (contains_reg_of_mode[cl][m] && contains_reg_of_mode[cl2][m]) 942 { 943 ira_init_register_move_cost_if_necessary ((machine_mode) m); 944 if (ira_register_move_cost[m][cl][cl] 945 != ira_register_move_cost[m][cl2][cl2]) 946 break; 947 } 948 if (m < NUM_MACHINE_MODES) 949 break; 950 } 951 if (cl2 == LIM_REG_CLASSES) 952 ira_uniform_class_p[cl] = true; 953 } 954 } 955 956 /* Set up IRA_ALLOCNO_CLASSES, IRA_ALLOCNO_CLASSES_NUM, 957 IRA_IMPORTANT_CLASSES, and IRA_IMPORTANT_CLASSES_NUM. 958 959 Target may have many subtargets and not all target hard registers can 960 be used for allocation, e.g. x86 port in 32-bit mode can not use 961 hard registers introduced in x86-64 like r8-r15). Some classes 962 might have the same allocatable hard registers, e.g. INDEX_REGS 963 and GENERAL_REGS in x86 port in 32-bit mode. To decrease different 964 calculations efforts we introduce allocno classes which contain 965 unique non-empty sets of allocatable hard-registers. 966 967 Pseudo class cost calculation in ira-costs.c is very expensive. 968 Therefore we are trying to decrease number of classes involved in 969 such calculation. Register classes used in the cost calculation 970 are called important classes. They are allocno classes and other 971 non-empty classes whose allocatable hard register sets are inside 972 of an allocno class hard register set. From the first sight, it 973 looks like that they are just allocno classes. It is not true. In 974 example of x86-port in 32-bit mode, allocno classes will contain 975 GENERAL_REGS but not LEGACY_REGS (because allocatable hard 976 registers are the same for the both classes). The important 977 classes will contain GENERAL_REGS and LEGACY_REGS. It is done 978 because a machine description insn constraint may refers for 979 LEGACY_REGS and code in ira-costs.c is mostly base on investigation 980 of the insn constraints. */ 981 static void 982 setup_allocno_and_important_classes (void) 983 { 984 int i, j, n, cl; 985 bool set_p; 986 HARD_REG_SET temp_hard_regset2; 987 static enum reg_class classes[LIM_REG_CLASSES + 1]; 988 989 n = 0; 990 /* Collect classes which contain unique sets of allocatable hard 991 registers. Prefer GENERAL_REGS to other classes containing the 992 same set of hard registers. */ 993 for (i = 0; i < LIM_REG_CLASSES; i++) 994 { 995 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[i]); 996 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 997 for (j = 0; j < n; j++) 998 { 999 cl = classes[j]; 1000 COPY_HARD_REG_SET (temp_hard_regset2, reg_class_contents[cl]); 1001 AND_COMPL_HARD_REG_SET (temp_hard_regset2, 1002 no_unit_alloc_regs); 1003 if (hard_reg_set_equal_p (temp_hard_regset, 1004 temp_hard_regset2)) 1005 break; 1006 } 1007 if (j >= n) 1008 classes[n++] = (enum reg_class) i; 1009 else if (i == GENERAL_REGS) 1010 /* Prefer general regs. For i386 example, it means that 1011 we prefer GENERAL_REGS over INDEX_REGS or LEGACY_REGS 1012 (all of them consists of the same available hard 1013 registers). */ 1014 classes[j] = (enum reg_class) i; 1015 } 1016 classes[n] = LIM_REG_CLASSES; 1017 1018 /* Set up classes which can be used for allocnos as classes 1019 containing non-empty unique sets of allocatable hard 1020 registers. */ 1021 ira_allocno_classes_num = 0; 1022 for (i = 0; (cl = classes[i]) != LIM_REG_CLASSES; i++) 1023 if (ira_class_hard_regs_num[cl] > 0) 1024 ira_allocno_classes[ira_allocno_classes_num++] = (enum reg_class) cl; 1025 ira_important_classes_num = 0; 1026 /* Add non-allocno classes containing to non-empty set of 1027 allocatable hard regs. */ 1028 for (cl = 0; cl < N_REG_CLASSES; cl++) 1029 if (ira_class_hard_regs_num[cl] > 0) 1030 { 1031 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); 1032 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 1033 set_p = false; 1034 for (j = 0; j < ira_allocno_classes_num; j++) 1035 { 1036 COPY_HARD_REG_SET (temp_hard_regset2, 1037 reg_class_contents[ira_allocno_classes[j]]); 1038 AND_COMPL_HARD_REG_SET (temp_hard_regset2, no_unit_alloc_regs); 1039 if ((enum reg_class) cl == ira_allocno_classes[j]) 1040 break; 1041 else if (hard_reg_set_subset_p (temp_hard_regset, 1042 temp_hard_regset2)) 1043 set_p = true; 1044 } 1045 if (set_p && j >= ira_allocno_classes_num) 1046 ira_important_classes[ira_important_classes_num++] 1047 = (enum reg_class) cl; 1048 } 1049 /* Now add allocno classes to the important classes. */ 1050 for (j = 0; j < ira_allocno_classes_num; j++) 1051 ira_important_classes[ira_important_classes_num++] 1052 = ira_allocno_classes[j]; 1053 for (cl = 0; cl < N_REG_CLASSES; cl++) 1054 { 1055 ira_reg_allocno_class_p[cl] = false; 1056 ira_reg_pressure_class_p[cl] = false; 1057 } 1058 for (j = 0; j < ira_allocno_classes_num; j++) 1059 ira_reg_allocno_class_p[ira_allocno_classes[j]] = true; 1060 setup_pressure_classes (); 1061 setup_uniform_class_p (); 1062 } 1063 1064 /* Setup translation in CLASS_TRANSLATE of all classes into a class 1065 given by array CLASSES of length CLASSES_NUM. The function is used 1066 make translation any reg class to an allocno class or to an 1067 pressure class. This translation is necessary for some 1068 calculations when we can use only allocno or pressure classes and 1069 such translation represents an approximate representation of all 1070 classes. 1071 1072 The translation in case when allocatable hard register set of a 1073 given class is subset of allocatable hard register set of a class 1074 in CLASSES is pretty simple. We use smallest classes from CLASSES 1075 containing a given class. If allocatable hard register set of a 1076 given class is not a subset of any corresponding set of a class 1077 from CLASSES, we use the cheapest (with load/store point of view) 1078 class from CLASSES whose set intersects with given class set. */ 1079 static void 1080 setup_class_translate_array (enum reg_class *class_translate, 1081 int classes_num, enum reg_class *classes) 1082 { 1083 int cl, mode; 1084 enum reg_class aclass, best_class, *cl_ptr; 1085 int i, cost, min_cost, best_cost; 1086 1087 for (cl = 0; cl < N_REG_CLASSES; cl++) 1088 class_translate[cl] = NO_REGS; 1089 1090 for (i = 0; i < classes_num; i++) 1091 { 1092 aclass = classes[i]; 1093 for (cl_ptr = &alloc_reg_class_subclasses[aclass][0]; 1094 (cl = *cl_ptr) != LIM_REG_CLASSES; 1095 cl_ptr++) 1096 if (class_translate[cl] == NO_REGS) 1097 class_translate[cl] = aclass; 1098 class_translate[aclass] = aclass; 1099 } 1100 /* For classes which are not fully covered by one of given classes 1101 (in other words covered by more one given class), use the 1102 cheapest class. */ 1103 for (cl = 0; cl < N_REG_CLASSES; cl++) 1104 { 1105 if (cl == NO_REGS || class_translate[cl] != NO_REGS) 1106 continue; 1107 best_class = NO_REGS; 1108 best_cost = INT_MAX; 1109 for (i = 0; i < classes_num; i++) 1110 { 1111 aclass = classes[i]; 1112 COPY_HARD_REG_SET (temp_hard_regset, 1113 reg_class_contents[aclass]); 1114 AND_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); 1115 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 1116 if (! hard_reg_set_empty_p (temp_hard_regset)) 1117 { 1118 min_cost = INT_MAX; 1119 for (mode = 0; mode < MAX_MACHINE_MODE; mode++) 1120 { 1121 cost = (ira_memory_move_cost[mode][aclass][0] 1122 + ira_memory_move_cost[mode][aclass][1]); 1123 if (min_cost > cost) 1124 min_cost = cost; 1125 } 1126 if (best_class == NO_REGS || best_cost > min_cost) 1127 { 1128 best_class = aclass; 1129 best_cost = min_cost; 1130 } 1131 } 1132 } 1133 class_translate[cl] = best_class; 1134 } 1135 } 1136 1137 /* Set up array IRA_ALLOCNO_CLASS_TRANSLATE and 1138 IRA_PRESSURE_CLASS_TRANSLATE. */ 1139 static void 1140 setup_class_translate (void) 1141 { 1142 setup_class_translate_array (ira_allocno_class_translate, 1143 ira_allocno_classes_num, ira_allocno_classes); 1144 setup_class_translate_array (ira_pressure_class_translate, 1145 ira_pressure_classes_num, ira_pressure_classes); 1146 } 1147 1148 /* Order numbers of allocno classes in original target allocno class 1149 array, -1 for non-allocno classes. */ 1150 static int allocno_class_order[N_REG_CLASSES]; 1151 1152 /* The function used to sort the important classes. */ 1153 static int 1154 comp_reg_classes_func (const void *v1p, const void *v2p) 1155 { 1156 enum reg_class cl1 = *(const enum reg_class *) v1p; 1157 enum reg_class cl2 = *(const enum reg_class *) v2p; 1158 enum reg_class tcl1, tcl2; 1159 int diff; 1160 1161 tcl1 = ira_allocno_class_translate[cl1]; 1162 tcl2 = ira_allocno_class_translate[cl2]; 1163 if (tcl1 != NO_REGS && tcl2 != NO_REGS 1164 && (diff = allocno_class_order[tcl1] - allocno_class_order[tcl2]) != 0) 1165 return diff; 1166 return (int) cl1 - (int) cl2; 1167 } 1168 1169 /* For correct work of function setup_reg_class_relation we need to 1170 reorder important classes according to the order of their allocno 1171 classes. It places important classes containing the same 1172 allocatable hard register set adjacent to each other and allocno 1173 class with the allocatable hard register set right after the other 1174 important classes with the same set. 1175 1176 In example from comments of function 1177 setup_allocno_and_important_classes, it places LEGACY_REGS and 1178 GENERAL_REGS close to each other and GENERAL_REGS is after 1179 LEGACY_REGS. */ 1180 static void 1181 reorder_important_classes (void) 1182 { 1183 int i; 1184 1185 for (i = 0; i < N_REG_CLASSES; i++) 1186 allocno_class_order[i] = -1; 1187 for (i = 0; i < ira_allocno_classes_num; i++) 1188 allocno_class_order[ira_allocno_classes[i]] = i; 1189 qsort (ira_important_classes, ira_important_classes_num, 1190 sizeof (enum reg_class), comp_reg_classes_func); 1191 for (i = 0; i < ira_important_classes_num; i++) 1192 ira_important_class_nums[ira_important_classes[i]] = i; 1193 } 1194 1195 /* Set up IRA_REG_CLASS_SUBUNION, IRA_REG_CLASS_SUPERUNION, 1196 IRA_REG_CLASS_SUPER_CLASSES, IRA_REG_CLASSES_INTERSECT, and 1197 IRA_REG_CLASSES_INTERSECT_P. For the meaning of the relations, 1198 please see corresponding comments in ira-int.h. */ 1199 static void 1200 setup_reg_class_relations (void) 1201 { 1202 int i, cl1, cl2, cl3; 1203 HARD_REG_SET intersection_set, union_set, temp_set2; 1204 bool important_class_p[N_REG_CLASSES]; 1205 1206 memset (important_class_p, 0, sizeof (important_class_p)); 1207 for (i = 0; i < ira_important_classes_num; i++) 1208 important_class_p[ira_important_classes[i]] = true; 1209 for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) 1210 { 1211 ira_reg_class_super_classes[cl1][0] = LIM_REG_CLASSES; 1212 for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) 1213 { 1214 ira_reg_classes_intersect_p[cl1][cl2] = false; 1215 ira_reg_class_intersect[cl1][cl2] = NO_REGS; 1216 ira_reg_class_subset[cl1][cl2] = NO_REGS; 1217 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl1]); 1218 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 1219 COPY_HARD_REG_SET (temp_set2, reg_class_contents[cl2]); 1220 AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); 1221 if (hard_reg_set_empty_p (temp_hard_regset) 1222 && hard_reg_set_empty_p (temp_set2)) 1223 { 1224 /* The both classes have no allocatable hard registers 1225 -- take all class hard registers into account and use 1226 reg_class_subunion and reg_class_superunion. */ 1227 for (i = 0;; i++) 1228 { 1229 cl3 = reg_class_subclasses[cl1][i]; 1230 if (cl3 == LIM_REG_CLASSES) 1231 break; 1232 if (reg_class_subset_p (ira_reg_class_intersect[cl1][cl2], 1233 (enum reg_class) cl3)) 1234 ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; 1235 } 1236 ira_reg_class_subunion[cl1][cl2] = reg_class_subunion[cl1][cl2]; 1237 ira_reg_class_superunion[cl1][cl2] = reg_class_superunion[cl1][cl2]; 1238 continue; 1239 } 1240 ira_reg_classes_intersect_p[cl1][cl2] 1241 = hard_reg_set_intersect_p (temp_hard_regset, temp_set2); 1242 if (important_class_p[cl1] && important_class_p[cl2] 1243 && hard_reg_set_subset_p (temp_hard_regset, temp_set2)) 1244 { 1245 /* CL1 and CL2 are important classes and CL1 allocatable 1246 hard register set is inside of CL2 allocatable hard 1247 registers -- make CL1 a superset of CL2. */ 1248 enum reg_class *p; 1249 1250 p = &ira_reg_class_super_classes[cl1][0]; 1251 while (*p != LIM_REG_CLASSES) 1252 p++; 1253 *p++ = (enum reg_class) cl2; 1254 *p = LIM_REG_CLASSES; 1255 } 1256 ira_reg_class_subunion[cl1][cl2] = NO_REGS; 1257 ira_reg_class_superunion[cl1][cl2] = NO_REGS; 1258 COPY_HARD_REG_SET (intersection_set, reg_class_contents[cl1]); 1259 AND_HARD_REG_SET (intersection_set, reg_class_contents[cl2]); 1260 AND_COMPL_HARD_REG_SET (intersection_set, no_unit_alloc_regs); 1261 COPY_HARD_REG_SET (union_set, reg_class_contents[cl1]); 1262 IOR_HARD_REG_SET (union_set, reg_class_contents[cl2]); 1263 AND_COMPL_HARD_REG_SET (union_set, no_unit_alloc_regs); 1264 for (cl3 = 0; cl3 < N_REG_CLASSES; cl3++) 1265 { 1266 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl3]); 1267 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 1268 if (hard_reg_set_subset_p (temp_hard_regset, intersection_set)) 1269 { 1270 /* CL3 allocatable hard register set is inside of 1271 intersection of allocatable hard register sets 1272 of CL1 and CL2. */ 1273 if (important_class_p[cl3]) 1274 { 1275 COPY_HARD_REG_SET 1276 (temp_set2, 1277 reg_class_contents 1278 [(int) ira_reg_class_intersect[cl1][cl2]]); 1279 AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); 1280 if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) 1281 /* If the allocatable hard register sets are 1282 the same, prefer GENERAL_REGS or the 1283 smallest class for debugging 1284 purposes. */ 1285 || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) 1286 && (cl3 == GENERAL_REGS 1287 || ((ira_reg_class_intersect[cl1][cl2] 1288 != GENERAL_REGS) 1289 && hard_reg_set_subset_p 1290 (reg_class_contents[cl3], 1291 reg_class_contents 1292 [(int) 1293 ira_reg_class_intersect[cl1][cl2]]))))) 1294 ira_reg_class_intersect[cl1][cl2] = (enum reg_class) cl3; 1295 } 1296 COPY_HARD_REG_SET 1297 (temp_set2, 1298 reg_class_contents[(int) ira_reg_class_subset[cl1][cl2]]); 1299 AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); 1300 if (! hard_reg_set_subset_p (temp_hard_regset, temp_set2) 1301 /* Ignore unavailable hard registers and prefer 1302 smallest class for debugging purposes. */ 1303 || (hard_reg_set_equal_p (temp_hard_regset, temp_set2) 1304 && hard_reg_set_subset_p 1305 (reg_class_contents[cl3], 1306 reg_class_contents 1307 [(int) ira_reg_class_subset[cl1][cl2]]))) 1308 ira_reg_class_subset[cl1][cl2] = (enum reg_class) cl3; 1309 } 1310 if (important_class_p[cl3] 1311 && hard_reg_set_subset_p (temp_hard_regset, union_set)) 1312 { 1313 /* CL3 allocatable hard register set is inside of 1314 union of allocatable hard register sets of CL1 1315 and CL2. */ 1316 COPY_HARD_REG_SET 1317 (temp_set2, 1318 reg_class_contents[(int) ira_reg_class_subunion[cl1][cl2]]); 1319 AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); 1320 if (ira_reg_class_subunion[cl1][cl2] == NO_REGS 1321 || (hard_reg_set_subset_p (temp_set2, temp_hard_regset) 1322 1323 && (! hard_reg_set_equal_p (temp_set2, 1324 temp_hard_regset) 1325 || cl3 == GENERAL_REGS 1326 /* If the allocatable hard register sets are the 1327 same, prefer GENERAL_REGS or the smallest 1328 class for debugging purposes. */ 1329 || (ira_reg_class_subunion[cl1][cl2] != GENERAL_REGS 1330 && hard_reg_set_subset_p 1331 (reg_class_contents[cl3], 1332 reg_class_contents 1333 [(int) ira_reg_class_subunion[cl1][cl2]]))))) 1334 ira_reg_class_subunion[cl1][cl2] = (enum reg_class) cl3; 1335 } 1336 if (hard_reg_set_subset_p (union_set, temp_hard_regset)) 1337 { 1338 /* CL3 allocatable hard register set contains union 1339 of allocatable hard register sets of CL1 and 1340 CL2. */ 1341 COPY_HARD_REG_SET 1342 (temp_set2, 1343 reg_class_contents[(int) ira_reg_class_superunion[cl1][cl2]]); 1344 AND_COMPL_HARD_REG_SET (temp_set2, no_unit_alloc_regs); 1345 if (ira_reg_class_superunion[cl1][cl2] == NO_REGS 1346 || (hard_reg_set_subset_p (temp_hard_regset, temp_set2) 1347 1348 && (! hard_reg_set_equal_p (temp_set2, 1349 temp_hard_regset) 1350 || cl3 == GENERAL_REGS 1351 /* If the allocatable hard register sets are the 1352 same, prefer GENERAL_REGS or the smallest 1353 class for debugging purposes. */ 1354 || (ira_reg_class_superunion[cl1][cl2] != GENERAL_REGS 1355 && hard_reg_set_subset_p 1356 (reg_class_contents[cl3], 1357 reg_class_contents 1358 [(int) ira_reg_class_superunion[cl1][cl2]]))))) 1359 ira_reg_class_superunion[cl1][cl2] = (enum reg_class) cl3; 1360 } 1361 } 1362 } 1363 } 1364 } 1365 1366 /* Output all uniform and important classes into file F. */ 1367 static void 1368 print_uniform_and_important_classes (FILE *f) 1369 { 1370 int i, cl; 1371 1372 fprintf (f, "Uniform classes:\n"); 1373 for (cl = 0; cl < N_REG_CLASSES; cl++) 1374 if (ira_uniform_class_p[cl]) 1375 fprintf (f, " %s", reg_class_names[cl]); 1376 fprintf (f, "\nImportant classes:\n"); 1377 for (i = 0; i < ira_important_classes_num; i++) 1378 fprintf (f, " %s", reg_class_names[ira_important_classes[i]]); 1379 fprintf (f, "\n"); 1380 } 1381 1382 /* Output all possible allocno or pressure classes and their 1383 translation map into file F. */ 1384 static void 1385 print_translated_classes (FILE *f, bool pressure_p) 1386 { 1387 int classes_num = (pressure_p 1388 ? ira_pressure_classes_num : ira_allocno_classes_num); 1389 enum reg_class *classes = (pressure_p 1390 ? ira_pressure_classes : ira_allocno_classes); 1391 enum reg_class *class_translate = (pressure_p 1392 ? ira_pressure_class_translate 1393 : ira_allocno_class_translate); 1394 int i; 1395 1396 fprintf (f, "%s classes:\n", pressure_p ? "Pressure" : "Allocno"); 1397 for (i = 0; i < classes_num; i++) 1398 fprintf (f, " %s", reg_class_names[classes[i]]); 1399 fprintf (f, "\nClass translation:\n"); 1400 for (i = 0; i < N_REG_CLASSES; i++) 1401 fprintf (f, " %s -> %s\n", reg_class_names[i], 1402 reg_class_names[class_translate[i]]); 1403 } 1404 1405 /* Output all possible allocno and translation classes and the 1406 translation maps into stderr. */ 1407 void 1408 ira_debug_allocno_classes (void) 1409 { 1410 print_uniform_and_important_classes (stderr); 1411 print_translated_classes (stderr, false); 1412 print_translated_classes (stderr, true); 1413 } 1414 1415 /* Set up different arrays concerning class subsets, allocno and 1416 important classes. */ 1417 static void 1418 find_reg_classes (void) 1419 { 1420 setup_allocno_and_important_classes (); 1421 setup_class_translate (); 1422 reorder_important_classes (); 1423 setup_reg_class_relations (); 1424 } 1425 1426 1427 1428 /* Set up the array above. */ 1429 static void 1430 setup_hard_regno_aclass (void) 1431 { 1432 int i; 1433 1434 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 1435 { 1436 #if 1 1437 ira_hard_regno_allocno_class[i] 1438 = (TEST_HARD_REG_BIT (no_unit_alloc_regs, i) 1439 ? NO_REGS 1440 : ira_allocno_class_translate[REGNO_REG_CLASS (i)]); 1441 #else 1442 int j; 1443 enum reg_class cl; 1444 ira_hard_regno_allocno_class[i] = NO_REGS; 1445 for (j = 0; j < ira_allocno_classes_num; j++) 1446 { 1447 cl = ira_allocno_classes[j]; 1448 if (ira_class_hard_reg_index[cl][i] >= 0) 1449 { 1450 ira_hard_regno_allocno_class[i] = cl; 1451 break; 1452 } 1453 } 1454 #endif 1455 } 1456 } 1457 1458 1459 1460 /* Form IRA_REG_CLASS_MAX_NREGS and IRA_REG_CLASS_MIN_NREGS maps. */ 1461 static void 1462 setup_reg_class_nregs (void) 1463 { 1464 int i, cl, cl2, m; 1465 1466 for (m = 0; m < MAX_MACHINE_MODE; m++) 1467 { 1468 for (cl = 0; cl < N_REG_CLASSES; cl++) 1469 ira_reg_class_max_nregs[cl][m] 1470 = ira_reg_class_min_nregs[cl][m] 1471 = targetm.class_max_nregs ((reg_class_t) cl, (machine_mode) m); 1472 for (cl = 0; cl < N_REG_CLASSES; cl++) 1473 for (i = 0; 1474 (cl2 = alloc_reg_class_subclasses[cl][i]) != LIM_REG_CLASSES; 1475 i++) 1476 if (ira_reg_class_min_nregs[cl2][m] 1477 < ira_reg_class_min_nregs[cl][m]) 1478 ira_reg_class_min_nregs[cl][m] = ira_reg_class_min_nregs[cl2][m]; 1479 } 1480 } 1481 1482 1483 1484 /* Set up IRA_PROHIBITED_CLASS_MODE_REGS and IRA_CLASS_SINGLETON. 1485 This function is called once IRA_CLASS_HARD_REGS has been initialized. */ 1486 static void 1487 setup_prohibited_class_mode_regs (void) 1488 { 1489 int j, k, hard_regno, cl, last_hard_regno, count; 1490 1491 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) 1492 { 1493 COPY_HARD_REG_SET (temp_hard_regset, reg_class_contents[cl]); 1494 AND_COMPL_HARD_REG_SET (temp_hard_regset, no_unit_alloc_regs); 1495 for (j = 0; j < NUM_MACHINE_MODES; j++) 1496 { 1497 count = 0; 1498 last_hard_regno = -1; 1499 CLEAR_HARD_REG_SET (ira_prohibited_class_mode_regs[cl][j]); 1500 for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) 1501 { 1502 hard_regno = ira_class_hard_regs[cl][k]; 1503 if (! HARD_REGNO_MODE_OK (hard_regno, (machine_mode) j)) 1504 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], 1505 hard_regno); 1506 else if (in_hard_reg_set_p (temp_hard_regset, 1507 (machine_mode) j, hard_regno)) 1508 { 1509 last_hard_regno = hard_regno; 1510 count++; 1511 } 1512 } 1513 ira_class_singleton[cl][j] = (count == 1 ? last_hard_regno : -1); 1514 } 1515 } 1516 } 1517 1518 /* Clarify IRA_PROHIBITED_CLASS_MODE_REGS by excluding hard registers 1519 spanning from one register pressure class to another one. It is 1520 called after defining the pressure classes. */ 1521 static void 1522 clarify_prohibited_class_mode_regs (void) 1523 { 1524 int j, k, hard_regno, cl, pclass, nregs; 1525 1526 for (cl = (int) N_REG_CLASSES - 1; cl >= 0; cl--) 1527 for (j = 0; j < NUM_MACHINE_MODES; j++) 1528 { 1529 CLEAR_HARD_REG_SET (ira_useful_class_mode_regs[cl][j]); 1530 for (k = ira_class_hard_regs_num[cl] - 1; k >= 0; k--) 1531 { 1532 hard_regno = ira_class_hard_regs[cl][k]; 1533 if (TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], hard_regno)) 1534 continue; 1535 nregs = hard_regno_nregs[hard_regno][j]; 1536 if (hard_regno + nregs > FIRST_PSEUDO_REGISTER) 1537 { 1538 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], 1539 hard_regno); 1540 continue; 1541 } 1542 pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; 1543 for (nregs-- ;nregs >= 0; nregs--) 1544 if (((enum reg_class) pclass 1545 != ira_pressure_class_translate[REGNO_REG_CLASS 1546 (hard_regno + nregs)])) 1547 { 1548 SET_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], 1549 hard_regno); 1550 break; 1551 } 1552 if (!TEST_HARD_REG_BIT (ira_prohibited_class_mode_regs[cl][j], 1553 hard_regno)) 1554 add_to_hard_reg_set (&ira_useful_class_mode_regs[cl][j], 1555 (machine_mode) j, hard_regno); 1556 } 1557 } 1558 } 1559 1560 /* Allocate and initialize IRA_REGISTER_MOVE_COST, IRA_MAY_MOVE_IN_COST 1561 and IRA_MAY_MOVE_OUT_COST for MODE. */ 1562 void 1563 ira_init_register_move_cost (machine_mode mode) 1564 { 1565 static unsigned short last_move_cost[N_REG_CLASSES][N_REG_CLASSES]; 1566 bool all_match = true; 1567 unsigned int cl1, cl2; 1568 1569 ira_assert (ira_register_move_cost[mode] == NULL 1570 && ira_may_move_in_cost[mode] == NULL 1571 && ira_may_move_out_cost[mode] == NULL); 1572 ira_assert (have_regs_of_mode[mode]); 1573 for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) 1574 for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) 1575 { 1576 int cost; 1577 if (!contains_reg_of_mode[cl1][mode] 1578 || !contains_reg_of_mode[cl2][mode]) 1579 { 1580 if ((ira_reg_class_max_nregs[cl1][mode] 1581 > ira_class_hard_regs_num[cl1]) 1582 || (ira_reg_class_max_nregs[cl2][mode] 1583 > ira_class_hard_regs_num[cl2])) 1584 cost = 65535; 1585 else 1586 cost = (ira_memory_move_cost[mode][cl1][0] 1587 + ira_memory_move_cost[mode][cl2][1]) * 2; 1588 } 1589 else 1590 { 1591 cost = register_move_cost (mode, (enum reg_class) cl1, 1592 (enum reg_class) cl2); 1593 ira_assert (cost < 65535); 1594 } 1595 all_match &= (last_move_cost[cl1][cl2] == cost); 1596 last_move_cost[cl1][cl2] = cost; 1597 } 1598 if (all_match && last_mode_for_init_move_cost != -1) 1599 { 1600 ira_register_move_cost[mode] 1601 = ira_register_move_cost[last_mode_for_init_move_cost]; 1602 ira_may_move_in_cost[mode] 1603 = ira_may_move_in_cost[last_mode_for_init_move_cost]; 1604 ira_may_move_out_cost[mode] 1605 = ira_may_move_out_cost[last_mode_for_init_move_cost]; 1606 return; 1607 } 1608 last_mode_for_init_move_cost = mode; 1609 ira_register_move_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); 1610 ira_may_move_in_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); 1611 ira_may_move_out_cost[mode] = XNEWVEC (move_table, N_REG_CLASSES); 1612 for (cl1 = 0; cl1 < N_REG_CLASSES; cl1++) 1613 for (cl2 = 0; cl2 < N_REG_CLASSES; cl2++) 1614 { 1615 int cost; 1616 enum reg_class *p1, *p2; 1617 1618 if (last_move_cost[cl1][cl2] == 65535) 1619 { 1620 ira_register_move_cost[mode][cl1][cl2] = 65535; 1621 ira_may_move_in_cost[mode][cl1][cl2] = 65535; 1622 ira_may_move_out_cost[mode][cl1][cl2] = 65535; 1623 } 1624 else 1625 { 1626 cost = last_move_cost[cl1][cl2]; 1627 1628 for (p2 = ®_class_subclasses[cl2][0]; 1629 *p2 != LIM_REG_CLASSES; p2++) 1630 if (ira_class_hard_regs_num[*p2] > 0 1631 && (ira_reg_class_max_nregs[*p2][mode] 1632 <= ira_class_hard_regs_num[*p2])) 1633 cost = MAX (cost, ira_register_move_cost[mode][cl1][*p2]); 1634 1635 for (p1 = ®_class_subclasses[cl1][0]; 1636 *p1 != LIM_REG_CLASSES; p1++) 1637 if (ira_class_hard_regs_num[*p1] > 0 1638 && (ira_reg_class_max_nregs[*p1][mode] 1639 <= ira_class_hard_regs_num[*p1])) 1640 cost = MAX (cost, ira_register_move_cost[mode][*p1][cl2]); 1641 1642 ira_assert (cost <= 65535); 1643 ira_register_move_cost[mode][cl1][cl2] = cost; 1644 1645 if (ira_class_subset_p[cl1][cl2]) 1646 ira_may_move_in_cost[mode][cl1][cl2] = 0; 1647 else 1648 ira_may_move_in_cost[mode][cl1][cl2] = cost; 1649 1650 if (ira_class_subset_p[cl2][cl1]) 1651 ira_may_move_out_cost[mode][cl1][cl2] = 0; 1652 else 1653 ira_may_move_out_cost[mode][cl1][cl2] = cost; 1654 } 1655 } 1656 } 1657 1658 1659 1660 /* This is called once during compiler work. It sets up 1661 different arrays whose values don't depend on the compiled 1662 function. */ 1663 void 1664 ira_init_once (void) 1665 { 1666 ira_init_costs_once (); 1667 lra_init_once (); 1668 } 1669 1670 /* Free ira_max_register_move_cost, ira_may_move_in_cost and 1671 ira_may_move_out_cost for each mode. */ 1672 void 1673 target_ira_int::free_register_move_costs (void) 1674 { 1675 int mode, i; 1676 1677 /* Reset move_cost and friends, making sure we only free shared 1678 table entries once. */ 1679 for (mode = 0; mode < MAX_MACHINE_MODE; mode++) 1680 if (x_ira_register_move_cost[mode]) 1681 { 1682 for (i = 0; 1683 i < mode && (x_ira_register_move_cost[i] 1684 != x_ira_register_move_cost[mode]); 1685 i++) 1686 ; 1687 if (i == mode) 1688 { 1689 free (x_ira_register_move_cost[mode]); 1690 free (x_ira_may_move_in_cost[mode]); 1691 free (x_ira_may_move_out_cost[mode]); 1692 } 1693 } 1694 memset (x_ira_register_move_cost, 0, sizeof x_ira_register_move_cost); 1695 memset (x_ira_may_move_in_cost, 0, sizeof x_ira_may_move_in_cost); 1696 memset (x_ira_may_move_out_cost, 0, sizeof x_ira_may_move_out_cost); 1697 last_mode_for_init_move_cost = -1; 1698 } 1699 1700 target_ira_int::~target_ira_int () 1701 { 1702 free_ira_costs (); 1703 free_register_move_costs (); 1704 } 1705 1706 /* This is called every time when register related information is 1707 changed. */ 1708 void 1709 ira_init (void) 1710 { 1711 this_target_ira_int->free_register_move_costs (); 1712 setup_reg_mode_hard_regset (); 1713 setup_alloc_regs (flag_omit_frame_pointer != 0); 1714 setup_class_subset_and_memory_move_costs (); 1715 setup_reg_class_nregs (); 1716 setup_prohibited_class_mode_regs (); 1717 find_reg_classes (); 1718 clarify_prohibited_class_mode_regs (); 1719 setup_hard_regno_aclass (); 1720 ira_init_costs (); 1721 } 1722 1723 1724 #define ira_prohibited_mode_move_regs_initialized_p \ 1725 (this_target_ira_int->x_ira_prohibited_mode_move_regs_initialized_p) 1726 1727 /* Set up IRA_PROHIBITED_MODE_MOVE_REGS. */ 1728 static void 1729 setup_prohibited_mode_move_regs (void) 1730 { 1731 int i, j; 1732 rtx test_reg1, test_reg2, move_pat; 1733 rtx_insn *move_insn; 1734 1735 if (ira_prohibited_mode_move_regs_initialized_p) 1736 return; 1737 ira_prohibited_mode_move_regs_initialized_p = true; 1738 test_reg1 = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 1); 1739 test_reg2 = gen_rtx_REG (word_mode, LAST_VIRTUAL_REGISTER + 2); 1740 move_pat = gen_rtx_SET (test_reg1, test_reg2); 1741 move_insn = gen_rtx_INSN (VOIDmode, 0, 0, 0, move_pat, 0, -1, 0); 1742 for (i = 0; i < NUM_MACHINE_MODES; i++) 1743 { 1744 SET_HARD_REG_SET (ira_prohibited_mode_move_regs[i]); 1745 for (j = 0; j < FIRST_PSEUDO_REGISTER; j++) 1746 { 1747 if (! HARD_REGNO_MODE_OK (j, (machine_mode) i)) 1748 continue; 1749 set_mode_and_regno (test_reg1, (machine_mode) i, j); 1750 set_mode_and_regno (test_reg2, (machine_mode) i, j); 1751 INSN_CODE (move_insn) = -1; 1752 recog_memoized (move_insn); 1753 if (INSN_CODE (move_insn) < 0) 1754 continue; 1755 extract_insn (move_insn); 1756 /* We don't know whether the move will be in code that is optimized 1757 for size or speed, so consider all enabled alternatives. */ 1758 if (! constrain_operands (1, get_enabled_alternatives (move_insn))) 1759 continue; 1760 CLEAR_HARD_REG_BIT (ira_prohibited_mode_move_regs[i], j); 1761 } 1762 } 1763 } 1764 1765 1766 1767 /* Setup possible alternatives in ALTS for INSN. */ 1768 void 1769 ira_setup_alts (rtx_insn *insn, HARD_REG_SET &alts) 1770 { 1771 /* MAP nalt * nop -> start of constraints for given operand and 1772 alternative. */ 1773 static vec<const char *> insn_constraints; 1774 int nop, nalt; 1775 bool curr_swapped; 1776 const char *p; 1777 int commutative = -1; 1778 1779 extract_insn (insn); 1780 alternative_mask preferred = get_preferred_alternatives (insn); 1781 CLEAR_HARD_REG_SET (alts); 1782 insn_constraints.release (); 1783 insn_constraints.safe_grow_cleared (recog_data.n_operands 1784 * recog_data.n_alternatives + 1); 1785 /* Check that the hard reg set is enough for holding all 1786 alternatives. It is hard to imagine the situation when the 1787 assertion is wrong. */ 1788 ira_assert (recog_data.n_alternatives 1789 <= (int) MAX (sizeof (HARD_REG_ELT_TYPE) * CHAR_BIT, 1790 FIRST_PSEUDO_REGISTER)); 1791 for (curr_swapped = false;; curr_swapped = true) 1792 { 1793 /* Calculate some data common for all alternatives to speed up the 1794 function. */ 1795 for (nop = 0; nop < recog_data.n_operands; nop++) 1796 { 1797 for (nalt = 0, p = recog_data.constraints[nop]; 1798 nalt < recog_data.n_alternatives; 1799 nalt++) 1800 { 1801 insn_constraints[nop * recog_data.n_alternatives + nalt] = p; 1802 while (*p && *p != ',') 1803 { 1804 /* We only support one commutative marker, the first 1805 one. We already set commutative above. */ 1806 if (*p == '%' && commutative < 0) 1807 commutative = nop; 1808 p++; 1809 } 1810 if (*p) 1811 p++; 1812 } 1813 } 1814 for (nalt = 0; nalt < recog_data.n_alternatives; nalt++) 1815 { 1816 if (!TEST_BIT (preferred, nalt) 1817 || TEST_HARD_REG_BIT (alts, nalt)) 1818 continue; 1819 1820 for (nop = 0; nop < recog_data.n_operands; nop++) 1821 { 1822 int c, len; 1823 1824 rtx op = recog_data.operand[nop]; 1825 p = insn_constraints[nop * recog_data.n_alternatives + nalt]; 1826 if (*p == 0 || *p == ',') 1827 continue; 1828 1829 do 1830 switch (c = *p, len = CONSTRAINT_LEN (c, p), c) 1831 { 1832 case '#': 1833 case ',': 1834 c = '\0'; 1835 case '\0': 1836 len = 0; 1837 break; 1838 1839 case '%': 1840 /* The commutative modifier is handled above. */ 1841 break; 1842 1843 case '0': case '1': case '2': case '3': case '4': 1844 case '5': case '6': case '7': case '8': case '9': 1845 goto op_success; 1846 break; 1847 1848 case 'g': 1849 goto op_success; 1850 break; 1851 1852 default: 1853 { 1854 enum constraint_num cn = lookup_constraint (p); 1855 switch (get_constraint_type (cn)) 1856 { 1857 case CT_REGISTER: 1858 if (reg_class_for_constraint (cn) != NO_REGS) 1859 goto op_success; 1860 break; 1861 1862 case CT_CONST_INT: 1863 if (CONST_INT_P (op) 1864 && (insn_const_int_ok_for_constraint 1865 (INTVAL (op), cn))) 1866 goto op_success; 1867 break; 1868 1869 case CT_ADDRESS: 1870 case CT_MEMORY: 1871 case CT_SPECIAL_MEMORY: 1872 goto op_success; 1873 1874 case CT_FIXED_FORM: 1875 if (constraint_satisfied_p (op, cn)) 1876 goto op_success; 1877 break; 1878 } 1879 break; 1880 } 1881 } 1882 while (p += len, c); 1883 break; 1884 op_success: 1885 ; 1886 } 1887 if (nop >= recog_data.n_operands) 1888 SET_HARD_REG_BIT (alts, nalt); 1889 } 1890 if (commutative < 0) 1891 break; 1892 /* Swap forth and back to avoid changing recog_data. */ 1893 std::swap (recog_data.operand[commutative], 1894 recog_data.operand[commutative + 1]); 1895 if (curr_swapped) 1896 break; 1897 } 1898 } 1899 1900 /* Return the number of the output non-early clobber operand which 1901 should be the same in any case as operand with number OP_NUM (or 1902 negative value if there is no such operand). The function takes 1903 only really possible alternatives into consideration. */ 1904 int 1905 ira_get_dup_out_num (int op_num, HARD_REG_SET &alts) 1906 { 1907 int curr_alt, c, original, dup; 1908 bool ignore_p, use_commut_op_p; 1909 const char *str; 1910 1911 if (op_num < 0 || recog_data.n_alternatives == 0) 1912 return -1; 1913 /* We should find duplications only for input operands. */ 1914 if (recog_data.operand_type[op_num] != OP_IN) 1915 return -1; 1916 str = recog_data.constraints[op_num]; 1917 use_commut_op_p = false; 1918 for (;;) 1919 { 1920 rtx op = recog_data.operand[op_num]; 1921 1922 for (curr_alt = 0, ignore_p = !TEST_HARD_REG_BIT (alts, curr_alt), 1923 original = -1;;) 1924 { 1925 c = *str; 1926 if (c == '\0') 1927 break; 1928 if (c == '#') 1929 ignore_p = true; 1930 else if (c == ',') 1931 { 1932 curr_alt++; 1933 ignore_p = !TEST_HARD_REG_BIT (alts, curr_alt); 1934 } 1935 else if (! ignore_p) 1936 switch (c) 1937 { 1938 case 'g': 1939 goto fail; 1940 default: 1941 { 1942 enum constraint_num cn = lookup_constraint (str); 1943 enum reg_class cl = reg_class_for_constraint (cn); 1944 if (cl != NO_REGS 1945 && !targetm.class_likely_spilled_p (cl)) 1946 goto fail; 1947 if (constraint_satisfied_p (op, cn)) 1948 goto fail; 1949 break; 1950 } 1951 1952 case '0': case '1': case '2': case '3': case '4': 1953 case '5': case '6': case '7': case '8': case '9': 1954 if (original != -1 && original != c) 1955 goto fail; 1956 original = c; 1957 break; 1958 } 1959 str += CONSTRAINT_LEN (c, str); 1960 } 1961 if (original == -1) 1962 goto fail; 1963 dup = -1; 1964 for (ignore_p = false, str = recog_data.constraints[original - '0']; 1965 *str != 0; 1966 str++) 1967 if (ignore_p) 1968 { 1969 if (*str == ',') 1970 ignore_p = false; 1971 } 1972 else if (*str == '#') 1973 ignore_p = true; 1974 else if (! ignore_p) 1975 { 1976 if (*str == '=') 1977 dup = original - '0'; 1978 /* It is better ignore an alternative with early clobber. */ 1979 else if (*str == '&') 1980 goto fail; 1981 } 1982 if (dup >= 0) 1983 return dup; 1984 fail: 1985 if (use_commut_op_p) 1986 break; 1987 use_commut_op_p = true; 1988 if (recog_data.constraints[op_num][0] == '%') 1989 str = recog_data.constraints[op_num + 1]; 1990 else if (op_num > 0 && recog_data.constraints[op_num - 1][0] == '%') 1991 str = recog_data.constraints[op_num - 1]; 1992 else 1993 break; 1994 } 1995 return -1; 1996 } 1997 1998 1999 2000 /* Search forward to see if the source register of a copy insn dies 2001 before either it or the destination register is modified, but don't 2002 scan past the end of the basic block. If so, we can replace the 2003 source with the destination and let the source die in the copy 2004 insn. 2005 2006 This will reduce the number of registers live in that range and may 2007 enable the destination and the source coalescing, thus often saving 2008 one register in addition to a register-register copy. */ 2009 2010 static void 2011 decrease_live_ranges_number (void) 2012 { 2013 basic_block bb; 2014 rtx_insn *insn; 2015 rtx set, src, dest, dest_death, note; 2016 rtx_insn *p, *q; 2017 int sregno, dregno; 2018 2019 if (! flag_expensive_optimizations) 2020 return; 2021 2022 if (ira_dump_file) 2023 fprintf (ira_dump_file, "Starting decreasing number of live ranges...\n"); 2024 2025 FOR_EACH_BB_FN (bb, cfun) 2026 FOR_BB_INSNS (bb, insn) 2027 { 2028 set = single_set (insn); 2029 if (! set) 2030 continue; 2031 src = SET_SRC (set); 2032 dest = SET_DEST (set); 2033 if (! REG_P (src) || ! REG_P (dest) 2034 || find_reg_note (insn, REG_DEAD, src)) 2035 continue; 2036 sregno = REGNO (src); 2037 dregno = REGNO (dest); 2038 2039 /* We don't want to mess with hard regs if register classes 2040 are small. */ 2041 if (sregno == dregno 2042 || (targetm.small_register_classes_for_mode_p (GET_MODE (src)) 2043 && (sregno < FIRST_PSEUDO_REGISTER 2044 || dregno < FIRST_PSEUDO_REGISTER)) 2045 /* We don't see all updates to SP if they are in an 2046 auto-inc memory reference, so we must disallow this 2047 optimization on them. */ 2048 || sregno == STACK_POINTER_REGNUM 2049 || dregno == STACK_POINTER_REGNUM) 2050 continue; 2051 2052 dest_death = NULL_RTX; 2053 2054 for (p = NEXT_INSN (insn); p; p = NEXT_INSN (p)) 2055 { 2056 if (! INSN_P (p)) 2057 continue; 2058 if (BLOCK_FOR_INSN (p) != bb) 2059 break; 2060 2061 if (reg_set_p (src, p) || reg_set_p (dest, p) 2062 /* If SRC is an asm-declared register, it must not be 2063 replaced in any asm. Unfortunately, the REG_EXPR 2064 tree for the asm variable may be absent in the SRC 2065 rtx, so we can't check the actual register 2066 declaration easily (the asm operand will have it, 2067 though). To avoid complicating the test for a rare 2068 case, we just don't perform register replacement 2069 for a hard reg mentioned in an asm. */ 2070 || (sregno < FIRST_PSEUDO_REGISTER 2071 && asm_noperands (PATTERN (p)) >= 0 2072 && reg_overlap_mentioned_p (src, PATTERN (p))) 2073 /* Don't change hard registers used by a call. */ 2074 || (CALL_P (p) && sregno < FIRST_PSEUDO_REGISTER 2075 && find_reg_fusage (p, USE, src)) 2076 /* Don't change a USE of a register. */ 2077 || (GET_CODE (PATTERN (p)) == USE 2078 && reg_overlap_mentioned_p (src, XEXP (PATTERN (p), 0)))) 2079 break; 2080 2081 /* See if all of SRC dies in P. This test is slightly 2082 more conservative than it needs to be. */ 2083 if ((note = find_regno_note (p, REG_DEAD, sregno)) 2084 && GET_MODE (XEXP (note, 0)) == GET_MODE (src)) 2085 { 2086 int failed = 0; 2087 2088 /* We can do the optimization. Scan forward from INSN 2089 again, replacing regs as we go. Set FAILED if a 2090 replacement can't be done. In that case, we can't 2091 move the death note for SRC. This should be 2092 rare. */ 2093 2094 /* Set to stop at next insn. */ 2095 for (q = next_real_insn (insn); 2096 q != next_real_insn (p); 2097 q = next_real_insn (q)) 2098 { 2099 if (reg_overlap_mentioned_p (src, PATTERN (q))) 2100 { 2101 /* If SRC is a hard register, we might miss 2102 some overlapping registers with 2103 validate_replace_rtx, so we would have to 2104 undo it. We can't if DEST is present in 2105 the insn, so fail in that combination of 2106 cases. */ 2107 if (sregno < FIRST_PSEUDO_REGISTER 2108 && reg_mentioned_p (dest, PATTERN (q))) 2109 failed = 1; 2110 2111 /* Attempt to replace all uses. */ 2112 else if (!validate_replace_rtx (src, dest, q)) 2113 failed = 1; 2114 2115 /* If this succeeded, but some part of the 2116 register is still present, undo the 2117 replacement. */ 2118 else if (sregno < FIRST_PSEUDO_REGISTER 2119 && reg_overlap_mentioned_p (src, PATTERN (q))) 2120 { 2121 validate_replace_rtx (dest, src, q); 2122 failed = 1; 2123 } 2124 } 2125 2126 /* If DEST dies here, remove the death note and 2127 save it for later. Make sure ALL of DEST dies 2128 here; again, this is overly conservative. */ 2129 if (! dest_death 2130 && (dest_death = find_regno_note (q, REG_DEAD, dregno))) 2131 { 2132 if (GET_MODE (XEXP (dest_death, 0)) == GET_MODE (dest)) 2133 remove_note (q, dest_death); 2134 else 2135 { 2136 failed = 1; 2137 dest_death = 0; 2138 } 2139 } 2140 } 2141 2142 if (! failed) 2143 { 2144 /* Move death note of SRC from P to INSN. */ 2145 remove_note (p, note); 2146 XEXP (note, 1) = REG_NOTES (insn); 2147 REG_NOTES (insn) = note; 2148 } 2149 2150 /* DEST is also dead if INSN has a REG_UNUSED note for 2151 DEST. */ 2152 if (! dest_death 2153 && (dest_death 2154 = find_regno_note (insn, REG_UNUSED, dregno))) 2155 { 2156 PUT_REG_NOTE_KIND (dest_death, REG_DEAD); 2157 remove_note (insn, dest_death); 2158 } 2159 2160 /* Put death note of DEST on P if we saw it die. */ 2161 if (dest_death) 2162 { 2163 XEXP (dest_death, 1) = REG_NOTES (p); 2164 REG_NOTES (p) = dest_death; 2165 } 2166 break; 2167 } 2168 2169 /* If SRC is a hard register which is set or killed in 2170 some other way, we can't do this optimization. */ 2171 else if (sregno < FIRST_PSEUDO_REGISTER && dead_or_set_p (p, src)) 2172 break; 2173 } 2174 } 2175 } 2176 2177 2178 2179 /* Return nonzero if REGNO is a particularly bad choice for reloading X. */ 2180 static bool 2181 ira_bad_reload_regno_1 (int regno, rtx x) 2182 { 2183 int x_regno, n, i; 2184 ira_allocno_t a; 2185 enum reg_class pref; 2186 2187 /* We only deal with pseudo regs. */ 2188 if (! x || GET_CODE (x) != REG) 2189 return false; 2190 2191 x_regno = REGNO (x); 2192 if (x_regno < FIRST_PSEUDO_REGISTER) 2193 return false; 2194 2195 /* If the pseudo prefers REGNO explicitly, then do not consider 2196 REGNO a bad spill choice. */ 2197 pref = reg_preferred_class (x_regno); 2198 if (reg_class_size[pref] == 1) 2199 return !TEST_HARD_REG_BIT (reg_class_contents[pref], regno); 2200 2201 /* If the pseudo conflicts with REGNO, then we consider REGNO a 2202 poor choice for a reload regno. */ 2203 a = ira_regno_allocno_map[x_regno]; 2204 n = ALLOCNO_NUM_OBJECTS (a); 2205 for (i = 0; i < n; i++) 2206 { 2207 ira_object_t obj = ALLOCNO_OBJECT (a, i); 2208 if (TEST_HARD_REG_BIT (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), regno)) 2209 return true; 2210 } 2211 return false; 2212 } 2213 2214 /* Return nonzero if REGNO is a particularly bad choice for reloading 2215 IN or OUT. */ 2216 bool 2217 ira_bad_reload_regno (int regno, rtx in, rtx out) 2218 { 2219 return (ira_bad_reload_regno_1 (regno, in) 2220 || ira_bad_reload_regno_1 (regno, out)); 2221 } 2222 2223 /* Add register clobbers from asm statements. */ 2224 static void 2225 compute_regs_asm_clobbered (void) 2226 { 2227 basic_block bb; 2228 2229 FOR_EACH_BB_FN (bb, cfun) 2230 { 2231 rtx_insn *insn; 2232 FOR_BB_INSNS_REVERSE (bb, insn) 2233 { 2234 df_ref def; 2235 2236 if (NONDEBUG_INSN_P (insn) && extract_asm_operands (PATTERN (insn))) 2237 FOR_EACH_INSN_DEF (def, insn) 2238 { 2239 unsigned int dregno = DF_REF_REGNO (def); 2240 if (HARD_REGISTER_NUM_P (dregno)) 2241 add_to_hard_reg_set (&crtl->asm_clobbers, 2242 GET_MODE (DF_REF_REAL_REG (def)), 2243 dregno); 2244 } 2245 } 2246 } 2247 } 2248 2249 2250 /* Set up ELIMINABLE_REGSET, IRA_NO_ALLOC_REGS, and 2251 REGS_EVER_LIVE. */ 2252 void 2253 ira_setup_eliminable_regset (void) 2254 { 2255 #ifdef ELIMINABLE_REGS 2256 int i; 2257 static const struct {const int from, to; } eliminables[] = ELIMINABLE_REGS; 2258 #endif 2259 /* FIXME: If EXIT_IGNORE_STACK is set, we will not save and restore 2260 sp for alloca. So we can't eliminate the frame pointer in that 2261 case. At some point, we should improve this by emitting the 2262 sp-adjusting insns for this case. */ 2263 frame_pointer_needed 2264 = (! flag_omit_frame_pointer 2265 || (cfun->calls_alloca && EXIT_IGNORE_STACK) 2266 /* We need the frame pointer to catch stack overflow exceptions if 2267 the stack pointer is moving (as for the alloca case just above). */ 2268 || (STACK_CHECK_MOVING_SP 2269 && flag_stack_check 2270 && flag_exceptions 2271 && cfun->can_throw_non_call_exceptions) 2272 || crtl->accesses_prior_frames 2273 || (SUPPORTS_STACK_ALIGNMENT && crtl->stack_realign_needed) 2274 /* We need a frame pointer for all Cilk Plus functions that use 2275 Cilk keywords. */ 2276 || (flag_cilkplus && cfun->is_cilk_function) 2277 || targetm.frame_pointer_required ()); 2278 2279 /* The chance that FRAME_POINTER_NEEDED is changed from inspecting 2280 RTL is very small. So if we use frame pointer for RA and RTL 2281 actually prevents this, we will spill pseudos assigned to the 2282 frame pointer in LRA. */ 2283 2284 if (frame_pointer_needed) 2285 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); 2286 2287 COPY_HARD_REG_SET (ira_no_alloc_regs, no_unit_alloc_regs); 2288 CLEAR_HARD_REG_SET (eliminable_regset); 2289 2290 compute_regs_asm_clobbered (); 2291 2292 /* Build the regset of all eliminable registers and show we can't 2293 use those that we already know won't be eliminated. */ 2294 #ifdef ELIMINABLE_REGS 2295 for (i = 0; i < (int) ARRAY_SIZE (eliminables); i++) 2296 { 2297 bool cannot_elim 2298 = (! targetm.can_eliminate (eliminables[i].from, eliminables[i].to) 2299 || (eliminables[i].to == STACK_POINTER_REGNUM && frame_pointer_needed)); 2300 2301 if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, eliminables[i].from)) 2302 { 2303 SET_HARD_REG_BIT (eliminable_regset, eliminables[i].from); 2304 2305 if (cannot_elim) 2306 SET_HARD_REG_BIT (ira_no_alloc_regs, eliminables[i].from); 2307 } 2308 else if (cannot_elim) 2309 error ("%s cannot be used in asm here", 2310 reg_names[eliminables[i].from]); 2311 else 2312 df_set_regs_ever_live (eliminables[i].from, true); 2313 } 2314 if (!HARD_FRAME_POINTER_IS_FRAME_POINTER) 2315 { 2316 if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) 2317 { 2318 SET_HARD_REG_BIT (eliminable_regset, HARD_FRAME_POINTER_REGNUM); 2319 if (frame_pointer_needed) 2320 SET_HARD_REG_BIT (ira_no_alloc_regs, HARD_FRAME_POINTER_REGNUM); 2321 } 2322 else if (frame_pointer_needed) 2323 error ("%s cannot be used in asm here", 2324 reg_names[HARD_FRAME_POINTER_REGNUM]); 2325 else 2326 df_set_regs_ever_live (HARD_FRAME_POINTER_REGNUM, true); 2327 } 2328 2329 #else 2330 if (!TEST_HARD_REG_BIT (crtl->asm_clobbers, HARD_FRAME_POINTER_REGNUM)) 2331 { 2332 SET_HARD_REG_BIT (eliminable_regset, FRAME_POINTER_REGNUM); 2333 if (frame_pointer_needed) 2334 SET_HARD_REG_BIT (ira_no_alloc_regs, FRAME_POINTER_REGNUM); 2335 } 2336 else if (frame_pointer_needed) 2337 error ("%s cannot be used in asm here", reg_names[FRAME_POINTER_REGNUM]); 2338 else 2339 df_set_regs_ever_live (FRAME_POINTER_REGNUM, true); 2340 #endif 2341 } 2342 2343 2344 2345 /* Vector of substitutions of register numbers, 2346 used to map pseudo regs into hardware regs. 2347 This is set up as a result of register allocation. 2348 Element N is the hard reg assigned to pseudo reg N, 2349 or is -1 if no hard reg was assigned. 2350 If N is a hard reg number, element N is N. */ 2351 short *reg_renumber; 2352 2353 /* Set up REG_RENUMBER and CALLER_SAVE_NEEDED (used by reload) from 2354 the allocation found by IRA. */ 2355 static void 2356 setup_reg_renumber (void) 2357 { 2358 int regno, hard_regno; 2359 ira_allocno_t a; 2360 ira_allocno_iterator ai; 2361 2362 caller_save_needed = 0; 2363 FOR_EACH_ALLOCNO (a, ai) 2364 { 2365 if (ira_use_lra_p && ALLOCNO_CAP_MEMBER (a) != NULL) 2366 continue; 2367 /* There are no caps at this point. */ 2368 ira_assert (ALLOCNO_CAP_MEMBER (a) == NULL); 2369 if (! ALLOCNO_ASSIGNED_P (a)) 2370 /* It can happen if A is not referenced but partially anticipated 2371 somewhere in a region. */ 2372 ALLOCNO_ASSIGNED_P (a) = true; 2373 ira_free_allocno_updated_costs (a); 2374 hard_regno = ALLOCNO_HARD_REGNO (a); 2375 regno = ALLOCNO_REGNO (a); 2376 reg_renumber[regno] = (hard_regno < 0 ? -1 : hard_regno); 2377 if (hard_regno >= 0) 2378 { 2379 int i, nwords; 2380 enum reg_class pclass; 2381 ira_object_t obj; 2382 2383 pclass = ira_pressure_class_translate[REGNO_REG_CLASS (hard_regno)]; 2384 nwords = ALLOCNO_NUM_OBJECTS (a); 2385 for (i = 0; i < nwords; i++) 2386 { 2387 obj = ALLOCNO_OBJECT (a, i); 2388 IOR_COMPL_HARD_REG_SET (OBJECT_TOTAL_CONFLICT_HARD_REGS (obj), 2389 reg_class_contents[pclass]); 2390 } 2391 if (ALLOCNO_CALLS_CROSSED_NUM (a) != 0 2392 && ira_hard_reg_set_intersection_p (hard_regno, ALLOCNO_MODE (a), 2393 call_used_reg_set)) 2394 { 2395 ira_assert (!optimize || flag_caller_saves 2396 || (ALLOCNO_CALLS_CROSSED_NUM (a) 2397 == ALLOCNO_CHEAP_CALLS_CROSSED_NUM (a)) 2398 || regno >= ira_reg_equiv_len 2399 || ira_equiv_no_lvalue_p (regno)); 2400 caller_save_needed = 1; 2401 } 2402 } 2403 } 2404 } 2405 2406 /* Set up allocno assignment flags for further allocation 2407 improvements. */ 2408 static void 2409 setup_allocno_assignment_flags (void) 2410 { 2411 int hard_regno; 2412 ira_allocno_t a; 2413 ira_allocno_iterator ai; 2414 2415 FOR_EACH_ALLOCNO (a, ai) 2416 { 2417 if (! ALLOCNO_ASSIGNED_P (a)) 2418 /* It can happen if A is not referenced but partially anticipated 2419 somewhere in a region. */ 2420 ira_free_allocno_updated_costs (a); 2421 hard_regno = ALLOCNO_HARD_REGNO (a); 2422 /* Don't assign hard registers to allocnos which are destination 2423 of removed store at the end of loop. It has no sense to keep 2424 the same value in different hard registers. It is also 2425 impossible to assign hard registers correctly to such 2426 allocnos because the cost info and info about intersected 2427 calls are incorrect for them. */ 2428 ALLOCNO_ASSIGNED_P (a) = (hard_regno >= 0 2429 || ALLOCNO_EMIT_DATA (a)->mem_optimized_dest_p 2430 || (ALLOCNO_MEMORY_COST (a) 2431 - ALLOCNO_CLASS_COST (a)) < 0); 2432 ira_assert 2433 (hard_regno < 0 2434 || ira_hard_reg_in_set_p (hard_regno, ALLOCNO_MODE (a), 2435 reg_class_contents[ALLOCNO_CLASS (a)])); 2436 } 2437 } 2438 2439 /* Evaluate overall allocation cost and the costs for using hard 2440 registers and memory for allocnos. */ 2441 static void 2442 calculate_allocation_cost (void) 2443 { 2444 int hard_regno, cost; 2445 ira_allocno_t a; 2446 ira_allocno_iterator ai; 2447 2448 ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; 2449 FOR_EACH_ALLOCNO (a, ai) 2450 { 2451 hard_regno = ALLOCNO_HARD_REGNO (a); 2452 ira_assert (hard_regno < 0 2453 || (ira_hard_reg_in_set_p 2454 (hard_regno, ALLOCNO_MODE (a), 2455 reg_class_contents[ALLOCNO_CLASS (a)]))); 2456 if (hard_regno < 0) 2457 { 2458 cost = ALLOCNO_MEMORY_COST (a); 2459 ira_mem_cost += cost; 2460 } 2461 else if (ALLOCNO_HARD_REG_COSTS (a) != NULL) 2462 { 2463 cost = (ALLOCNO_HARD_REG_COSTS (a) 2464 [ira_class_hard_reg_index 2465 [ALLOCNO_CLASS (a)][hard_regno]]); 2466 ira_reg_cost += cost; 2467 } 2468 else 2469 { 2470 cost = ALLOCNO_CLASS_COST (a); 2471 ira_reg_cost += cost; 2472 } 2473 ira_overall_cost += cost; 2474 } 2475 2476 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) 2477 { 2478 fprintf (ira_dump_file, 2479 "+++Costs: overall %" PRId64 2480 ", reg %" PRId64 2481 ", mem %" PRId64 2482 ", ld %" PRId64 2483 ", st %" PRId64 2484 ", move %" PRId64, 2485 ira_overall_cost, ira_reg_cost, ira_mem_cost, 2486 ira_load_cost, ira_store_cost, ira_shuffle_cost); 2487 fprintf (ira_dump_file, "\n+++ move loops %d, new jumps %d\n", 2488 ira_move_loops_num, ira_additional_jumps_num); 2489 } 2490 2491 } 2492 2493 #ifdef ENABLE_IRA_CHECKING 2494 /* Check the correctness of the allocation. We do need this because 2495 of complicated code to transform more one region internal 2496 representation into one region representation. */ 2497 static void 2498 check_allocation (void) 2499 { 2500 ira_allocno_t a; 2501 int hard_regno, nregs, conflict_nregs; 2502 ira_allocno_iterator ai; 2503 2504 FOR_EACH_ALLOCNO (a, ai) 2505 { 2506 int n = ALLOCNO_NUM_OBJECTS (a); 2507 int i; 2508 2509 if (ALLOCNO_CAP_MEMBER (a) != NULL 2510 || (hard_regno = ALLOCNO_HARD_REGNO (a)) < 0) 2511 continue; 2512 nregs = hard_regno_nregs[hard_regno][ALLOCNO_MODE (a)]; 2513 if (nregs == 1) 2514 /* We allocated a single hard register. */ 2515 n = 1; 2516 else if (n > 1) 2517 /* We allocated multiple hard registers, and we will test 2518 conflicts in a granularity of single hard regs. */ 2519 nregs = 1; 2520 2521 for (i = 0; i < n; i++) 2522 { 2523 ira_object_t obj = ALLOCNO_OBJECT (a, i); 2524 ira_object_t conflict_obj; 2525 ira_object_conflict_iterator oci; 2526 int this_regno = hard_regno; 2527 if (n > 1) 2528 { 2529 if (REG_WORDS_BIG_ENDIAN) 2530 this_regno += n - i - 1; 2531 else 2532 this_regno += i; 2533 } 2534 FOR_EACH_OBJECT_CONFLICT (obj, conflict_obj, oci) 2535 { 2536 ira_allocno_t conflict_a = OBJECT_ALLOCNO (conflict_obj); 2537 int conflict_hard_regno = ALLOCNO_HARD_REGNO (conflict_a); 2538 if (conflict_hard_regno < 0) 2539 continue; 2540 2541 conflict_nregs 2542 = (hard_regno_nregs 2543 [conflict_hard_regno][ALLOCNO_MODE (conflict_a)]); 2544 2545 if (ALLOCNO_NUM_OBJECTS (conflict_a) > 1 2546 && conflict_nregs == ALLOCNO_NUM_OBJECTS (conflict_a)) 2547 { 2548 if (REG_WORDS_BIG_ENDIAN) 2549 conflict_hard_regno += (ALLOCNO_NUM_OBJECTS (conflict_a) 2550 - OBJECT_SUBWORD (conflict_obj) - 1); 2551 else 2552 conflict_hard_regno += OBJECT_SUBWORD (conflict_obj); 2553 conflict_nregs = 1; 2554 } 2555 2556 if ((conflict_hard_regno <= this_regno 2557 && this_regno < conflict_hard_regno + conflict_nregs) 2558 || (this_regno <= conflict_hard_regno 2559 && conflict_hard_regno < this_regno + nregs)) 2560 { 2561 fprintf (stderr, "bad allocation for %d and %d\n", 2562 ALLOCNO_REGNO (a), ALLOCNO_REGNO (conflict_a)); 2563 gcc_unreachable (); 2564 } 2565 } 2566 } 2567 } 2568 } 2569 #endif 2570 2571 /* Allocate REG_EQUIV_INIT. Set up it from IRA_REG_EQUIV which should 2572 be already calculated. */ 2573 static void 2574 setup_reg_equiv_init (void) 2575 { 2576 int i; 2577 int max_regno = max_reg_num (); 2578 2579 for (i = 0; i < max_regno; i++) 2580 reg_equiv_init (i) = ira_reg_equiv[i].init_insns; 2581 } 2582 2583 /* Update equiv regno from movement of FROM_REGNO to TO_REGNO. INSNS 2584 are insns which were generated for such movement. It is assumed 2585 that FROM_REGNO and TO_REGNO always have the same value at the 2586 point of any move containing such registers. This function is used 2587 to update equiv info for register shuffles on the region borders 2588 and for caller save/restore insns. */ 2589 void 2590 ira_update_equiv_info_by_shuffle_insn (int to_regno, int from_regno, rtx_insn *insns) 2591 { 2592 rtx_insn *insn; 2593 rtx x, note; 2594 2595 if (! ira_reg_equiv[from_regno].defined_p 2596 && (! ira_reg_equiv[to_regno].defined_p 2597 || ((x = ira_reg_equiv[to_regno].memory) != NULL_RTX 2598 && ! MEM_READONLY_P (x)))) 2599 return; 2600 insn = insns; 2601 if (NEXT_INSN (insn) != NULL_RTX) 2602 { 2603 if (! ira_reg_equiv[to_regno].defined_p) 2604 { 2605 ira_assert (ira_reg_equiv[to_regno].init_insns == NULL_RTX); 2606 return; 2607 } 2608 ira_reg_equiv[to_regno].defined_p = false; 2609 ira_reg_equiv[to_regno].memory 2610 = ira_reg_equiv[to_regno].constant 2611 = ira_reg_equiv[to_regno].invariant 2612 = ira_reg_equiv[to_regno].init_insns = NULL; 2613 if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) 2614 fprintf (ira_dump_file, 2615 " Invalidating equiv info for reg %d\n", to_regno); 2616 return; 2617 } 2618 /* It is possible that FROM_REGNO still has no equivalence because 2619 in shuffles to_regno<-from_regno and from_regno<-to_regno the 2nd 2620 insn was not processed yet. */ 2621 if (ira_reg_equiv[from_regno].defined_p) 2622 { 2623 ira_reg_equiv[to_regno].defined_p = true; 2624 if ((x = ira_reg_equiv[from_regno].memory) != NULL_RTX) 2625 { 2626 ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX 2627 && ira_reg_equiv[from_regno].constant == NULL_RTX); 2628 ira_assert (ira_reg_equiv[to_regno].memory == NULL_RTX 2629 || rtx_equal_p (ira_reg_equiv[to_regno].memory, x)); 2630 ira_reg_equiv[to_regno].memory = x; 2631 if (! MEM_READONLY_P (x)) 2632 /* We don't add the insn to insn init list because memory 2633 equivalence is just to say what memory is better to use 2634 when the pseudo is spilled. */ 2635 return; 2636 } 2637 else if ((x = ira_reg_equiv[from_regno].constant) != NULL_RTX) 2638 { 2639 ira_assert (ira_reg_equiv[from_regno].invariant == NULL_RTX); 2640 ira_assert (ira_reg_equiv[to_regno].constant == NULL_RTX 2641 || rtx_equal_p (ira_reg_equiv[to_regno].constant, x)); 2642 ira_reg_equiv[to_regno].constant = x; 2643 } 2644 else 2645 { 2646 x = ira_reg_equiv[from_regno].invariant; 2647 ira_assert (x != NULL_RTX); 2648 ira_assert (ira_reg_equiv[to_regno].invariant == NULL_RTX 2649 || rtx_equal_p (ira_reg_equiv[to_regno].invariant, x)); 2650 ira_reg_equiv[to_regno].invariant = x; 2651 } 2652 if (find_reg_note (insn, REG_EQUIV, x) == NULL_RTX) 2653 { 2654 note = set_unique_reg_note (insn, REG_EQUIV, x); 2655 gcc_assert (note != NULL_RTX); 2656 if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) 2657 { 2658 fprintf (ira_dump_file, 2659 " Adding equiv note to insn %u for reg %d ", 2660 INSN_UID (insn), to_regno); 2661 dump_value_slim (ira_dump_file, x, 1); 2662 fprintf (ira_dump_file, "\n"); 2663 } 2664 } 2665 } 2666 ira_reg_equiv[to_regno].init_insns 2667 = gen_rtx_INSN_LIST (VOIDmode, insn, 2668 ira_reg_equiv[to_regno].init_insns); 2669 if (internal_flag_ira_verbose > 3 && ira_dump_file != NULL) 2670 fprintf (ira_dump_file, 2671 " Adding equiv init move insn %u to reg %d\n", 2672 INSN_UID (insn), to_regno); 2673 } 2674 2675 /* Fix values of array REG_EQUIV_INIT after live range splitting done 2676 by IRA. */ 2677 static void 2678 fix_reg_equiv_init (void) 2679 { 2680 int max_regno = max_reg_num (); 2681 int i, new_regno, max; 2682 rtx set; 2683 rtx_insn_list *x, *next, *prev; 2684 rtx_insn *insn; 2685 2686 if (max_regno_before_ira < max_regno) 2687 { 2688 max = vec_safe_length (reg_equivs); 2689 grow_reg_equivs (); 2690 for (i = FIRST_PSEUDO_REGISTER; i < max; i++) 2691 for (prev = NULL, x = reg_equiv_init (i); 2692 x != NULL_RTX; 2693 x = next) 2694 { 2695 next = x->next (); 2696 insn = x->insn (); 2697 set = single_set (insn); 2698 ira_assert (set != NULL_RTX 2699 && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))); 2700 if (REG_P (SET_DEST (set)) 2701 && ((int) REGNO (SET_DEST (set)) == i 2702 || (int) ORIGINAL_REGNO (SET_DEST (set)) == i)) 2703 new_regno = REGNO (SET_DEST (set)); 2704 else if (REG_P (SET_SRC (set)) 2705 && ((int) REGNO (SET_SRC (set)) == i 2706 || (int) ORIGINAL_REGNO (SET_SRC (set)) == i)) 2707 new_regno = REGNO (SET_SRC (set)); 2708 else 2709 gcc_unreachable (); 2710 if (new_regno == i) 2711 prev = x; 2712 else 2713 { 2714 /* Remove the wrong list element. */ 2715 if (prev == NULL_RTX) 2716 reg_equiv_init (i) = next; 2717 else 2718 XEXP (prev, 1) = next; 2719 XEXP (x, 1) = reg_equiv_init (new_regno); 2720 reg_equiv_init (new_regno) = x; 2721 } 2722 } 2723 } 2724 } 2725 2726 #ifdef ENABLE_IRA_CHECKING 2727 /* Print redundant memory-memory copies. */ 2728 static void 2729 print_redundant_copies (void) 2730 { 2731 int hard_regno; 2732 ira_allocno_t a; 2733 ira_copy_t cp, next_cp; 2734 ira_allocno_iterator ai; 2735 2736 FOR_EACH_ALLOCNO (a, ai) 2737 { 2738 if (ALLOCNO_CAP_MEMBER (a) != NULL) 2739 /* It is a cap. */ 2740 continue; 2741 hard_regno = ALLOCNO_HARD_REGNO (a); 2742 if (hard_regno >= 0) 2743 continue; 2744 for (cp = ALLOCNO_COPIES (a); cp != NULL; cp = next_cp) 2745 if (cp->first == a) 2746 next_cp = cp->next_first_allocno_copy; 2747 else 2748 { 2749 next_cp = cp->next_second_allocno_copy; 2750 if (internal_flag_ira_verbose > 4 && ira_dump_file != NULL 2751 && cp->insn != NULL_RTX 2752 && ALLOCNO_HARD_REGNO (cp->first) == hard_regno) 2753 fprintf (ira_dump_file, 2754 " Redundant move from %d(freq %d):%d\n", 2755 INSN_UID (cp->insn), cp->freq, hard_regno); 2756 } 2757 } 2758 } 2759 #endif 2760 2761 /* Setup preferred and alternative classes for new pseudo-registers 2762 created by IRA starting with START. */ 2763 static void 2764 setup_preferred_alternate_classes_for_new_pseudos (int start) 2765 { 2766 int i, old_regno; 2767 int max_regno = max_reg_num (); 2768 2769 for (i = start; i < max_regno; i++) 2770 { 2771 old_regno = ORIGINAL_REGNO (regno_reg_rtx[i]); 2772 ira_assert (i != old_regno); 2773 setup_reg_classes (i, reg_preferred_class (old_regno), 2774 reg_alternate_class (old_regno), 2775 reg_allocno_class (old_regno)); 2776 if (internal_flag_ira_verbose > 2 && ira_dump_file != NULL) 2777 fprintf (ira_dump_file, 2778 " New r%d: setting preferred %s, alternative %s\n", 2779 i, reg_class_names[reg_preferred_class (old_regno)], 2780 reg_class_names[reg_alternate_class (old_regno)]); 2781 } 2782 } 2783 2784 2785 /* The number of entries allocated in reg_info. */ 2786 static int allocated_reg_info_size; 2787 2788 /* Regional allocation can create new pseudo-registers. This function 2789 expands some arrays for pseudo-registers. */ 2790 static void 2791 expand_reg_info (void) 2792 { 2793 int i; 2794 int size = max_reg_num (); 2795 2796 resize_reg_info (); 2797 for (i = allocated_reg_info_size; i < size; i++) 2798 setup_reg_classes (i, GENERAL_REGS, ALL_REGS, GENERAL_REGS); 2799 setup_preferred_alternate_classes_for_new_pseudos (allocated_reg_info_size); 2800 allocated_reg_info_size = size; 2801 } 2802 2803 /* Return TRUE if there is too high register pressure in the function. 2804 It is used to decide when stack slot sharing is worth to do. */ 2805 static bool 2806 too_high_register_pressure_p (void) 2807 { 2808 int i; 2809 enum reg_class pclass; 2810 2811 for (i = 0; i < ira_pressure_classes_num; i++) 2812 { 2813 pclass = ira_pressure_classes[i]; 2814 if (ira_loop_tree_root->reg_pressure[pclass] > 10000) 2815 return true; 2816 } 2817 return false; 2818 } 2819 2820 2821 2822 /* Indicate that hard register number FROM was eliminated and replaced with 2823 an offset from hard register number TO. The status of hard registers live 2824 at the start of a basic block is updated by replacing a use of FROM with 2825 a use of TO. */ 2826 2827 void 2828 mark_elimination (int from, int to) 2829 { 2830 basic_block bb; 2831 bitmap r; 2832 2833 FOR_EACH_BB_FN (bb, cfun) 2834 { 2835 r = DF_LR_IN (bb); 2836 if (bitmap_bit_p (r, from)) 2837 { 2838 bitmap_clear_bit (r, from); 2839 bitmap_set_bit (r, to); 2840 } 2841 if (! df_live) 2842 continue; 2843 r = DF_LIVE_IN (bb); 2844 if (bitmap_bit_p (r, from)) 2845 { 2846 bitmap_clear_bit (r, from); 2847 bitmap_set_bit (r, to); 2848 } 2849 } 2850 } 2851 2852 2853 2854 /* The length of the following array. */ 2855 int ira_reg_equiv_len; 2856 2857 /* Info about equiv. info for each register. */ 2858 struct ira_reg_equiv_s *ira_reg_equiv; 2859 2860 /* Expand ira_reg_equiv if necessary. */ 2861 void 2862 ira_expand_reg_equiv (void) 2863 { 2864 int old = ira_reg_equiv_len; 2865 2866 if (ira_reg_equiv_len > max_reg_num ()) 2867 return; 2868 ira_reg_equiv_len = max_reg_num () * 3 / 2 + 1; 2869 ira_reg_equiv 2870 = (struct ira_reg_equiv_s *) xrealloc (ira_reg_equiv, 2871 ira_reg_equiv_len 2872 * sizeof (struct ira_reg_equiv_s)); 2873 gcc_assert (old < ira_reg_equiv_len); 2874 memset (ira_reg_equiv + old, 0, 2875 sizeof (struct ira_reg_equiv_s) * (ira_reg_equiv_len - old)); 2876 } 2877 2878 static void 2879 init_reg_equiv (void) 2880 { 2881 ira_reg_equiv_len = 0; 2882 ira_reg_equiv = NULL; 2883 ira_expand_reg_equiv (); 2884 } 2885 2886 static void 2887 finish_reg_equiv (void) 2888 { 2889 free (ira_reg_equiv); 2890 } 2891 2892 2893 2894 struct equivalence 2895 { 2896 /* Set when a REG_EQUIV note is found or created. Use to 2897 keep track of what memory accesses might be created later, 2898 e.g. by reload. */ 2899 rtx replacement; 2900 rtx *src_p; 2901 2902 /* The list of each instruction which initializes this register. 2903 2904 NULL indicates we know nothing about this register's equivalence 2905 properties. 2906 2907 An INSN_LIST with a NULL insn indicates this pseudo is already 2908 known to not have a valid equivalence. */ 2909 rtx_insn_list *init_insns; 2910 2911 /* Loop depth is used to recognize equivalences which appear 2912 to be present within the same loop (or in an inner loop). */ 2913 short loop_depth; 2914 /* Nonzero if this had a preexisting REG_EQUIV note. */ 2915 unsigned char is_arg_equivalence : 1; 2916 /* Set when an attempt should be made to replace a register 2917 with the associated src_p entry. */ 2918 unsigned char replace : 1; 2919 /* Set if this register has no known equivalence. */ 2920 unsigned char no_equiv : 1; 2921 }; 2922 2923 /* reg_equiv[N] (where N is a pseudo reg number) is the equivalence 2924 structure for that register. */ 2925 static struct equivalence *reg_equiv; 2926 2927 /* Used for communication between the following two functions: contains 2928 a MEM that we wish to ensure remains unchanged. */ 2929 static rtx equiv_mem; 2930 2931 /* Set nonzero if EQUIV_MEM is modified. */ 2932 static int equiv_mem_modified; 2933 2934 /* If EQUIV_MEM is modified by modifying DEST, indicate that it is modified. 2935 Called via note_stores. */ 2936 static void 2937 validate_equiv_mem_from_store (rtx dest, const_rtx set ATTRIBUTE_UNUSED, 2938 void *data ATTRIBUTE_UNUSED) 2939 { 2940 if ((REG_P (dest) 2941 && reg_overlap_mentioned_p (dest, equiv_mem)) 2942 || (MEM_P (dest) 2943 && anti_dependence (equiv_mem, dest))) 2944 equiv_mem_modified = 1; 2945 } 2946 2947 /* Verify that no store between START and the death of REG invalidates 2948 MEMREF. MEMREF is invalidated by modifying a register used in MEMREF, 2949 by storing into an overlapping memory location, or with a non-const 2950 CALL_INSN. 2951 2952 Return 1 if MEMREF remains valid. */ 2953 static int 2954 validate_equiv_mem (rtx_insn *start, rtx reg, rtx memref) 2955 { 2956 rtx_insn *insn; 2957 rtx note; 2958 2959 equiv_mem = memref; 2960 equiv_mem_modified = 0; 2961 2962 /* If the memory reference has side effects or is volatile, it isn't a 2963 valid equivalence. */ 2964 if (side_effects_p (memref)) 2965 return 0; 2966 2967 for (insn = start; insn && ! equiv_mem_modified; insn = NEXT_INSN (insn)) 2968 { 2969 if (! INSN_P (insn)) 2970 continue; 2971 2972 if (find_reg_note (insn, REG_DEAD, reg)) 2973 return 1; 2974 2975 /* This used to ignore readonly memory and const/pure calls. The problem 2976 is the equivalent form may reference a pseudo which gets assigned a 2977 call clobbered hard reg. When we later replace REG with its 2978 equivalent form, the value in the call-clobbered reg has been 2979 changed and all hell breaks loose. */ 2980 if (CALL_P (insn)) 2981 return 0; 2982 2983 note_stores (PATTERN (insn), validate_equiv_mem_from_store, NULL); 2984 2985 /* If a register mentioned in MEMREF is modified via an 2986 auto-increment, we lose the equivalence. Do the same if one 2987 dies; although we could extend the life, it doesn't seem worth 2988 the trouble. */ 2989 2990 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 2991 if ((REG_NOTE_KIND (note) == REG_INC 2992 || REG_NOTE_KIND (note) == REG_DEAD) 2993 && REG_P (XEXP (note, 0)) 2994 && reg_overlap_mentioned_p (XEXP (note, 0), memref)) 2995 return 0; 2996 } 2997 2998 return 0; 2999 } 3000 3001 /* Returns zero if X is known to be invariant. */ 3002 static int 3003 equiv_init_varies_p (rtx x) 3004 { 3005 RTX_CODE code = GET_CODE (x); 3006 int i; 3007 const char *fmt; 3008 3009 switch (code) 3010 { 3011 case MEM: 3012 return !MEM_READONLY_P (x) || equiv_init_varies_p (XEXP (x, 0)); 3013 3014 case CONST: 3015 CASE_CONST_ANY: 3016 case SYMBOL_REF: 3017 case LABEL_REF: 3018 return 0; 3019 3020 case REG: 3021 return reg_equiv[REGNO (x)].replace == 0 && rtx_varies_p (x, 0); 3022 3023 case ASM_OPERANDS: 3024 if (MEM_VOLATILE_P (x)) 3025 return 1; 3026 3027 /* Fall through. */ 3028 3029 default: 3030 break; 3031 } 3032 3033 fmt = GET_RTX_FORMAT (code); 3034 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3035 if (fmt[i] == 'e') 3036 { 3037 if (equiv_init_varies_p (XEXP (x, i))) 3038 return 1; 3039 } 3040 else if (fmt[i] == 'E') 3041 { 3042 int j; 3043 for (j = 0; j < XVECLEN (x, i); j++) 3044 if (equiv_init_varies_p (XVECEXP (x, i, j))) 3045 return 1; 3046 } 3047 3048 return 0; 3049 } 3050 3051 /* Returns nonzero if X (used to initialize register REGNO) is movable. 3052 X is only movable if the registers it uses have equivalent initializations 3053 which appear to be within the same loop (or in an inner loop) and movable 3054 or if they are not candidates for local_alloc and don't vary. */ 3055 static int 3056 equiv_init_movable_p (rtx x, int regno) 3057 { 3058 int i, j; 3059 const char *fmt; 3060 enum rtx_code code = GET_CODE (x); 3061 3062 switch (code) 3063 { 3064 case SET: 3065 return equiv_init_movable_p (SET_SRC (x), regno); 3066 3067 case CC0: 3068 case CLOBBER: 3069 return 0; 3070 3071 case PRE_INC: 3072 case PRE_DEC: 3073 case POST_INC: 3074 case POST_DEC: 3075 case PRE_MODIFY: 3076 case POST_MODIFY: 3077 return 0; 3078 3079 case REG: 3080 return ((reg_equiv[REGNO (x)].loop_depth >= reg_equiv[regno].loop_depth 3081 && reg_equiv[REGNO (x)].replace) 3082 || (REG_BASIC_BLOCK (REGNO (x)) < NUM_FIXED_BLOCKS 3083 && ! rtx_varies_p (x, 0))); 3084 3085 case UNSPEC_VOLATILE: 3086 return 0; 3087 3088 case ASM_OPERANDS: 3089 if (MEM_VOLATILE_P (x)) 3090 return 0; 3091 3092 /* Fall through. */ 3093 3094 default: 3095 break; 3096 } 3097 3098 fmt = GET_RTX_FORMAT (code); 3099 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3100 switch (fmt[i]) 3101 { 3102 case 'e': 3103 if (! equiv_init_movable_p (XEXP (x, i), regno)) 3104 return 0; 3105 break; 3106 case 'E': 3107 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3108 if (! equiv_init_movable_p (XVECEXP (x, i, j), regno)) 3109 return 0; 3110 break; 3111 } 3112 3113 return 1; 3114 } 3115 3116 /* TRUE if X uses any registers for which reg_equiv[REGNO].replace is 3117 true. */ 3118 static int 3119 contains_replace_regs (rtx x) 3120 { 3121 int i, j; 3122 const char *fmt; 3123 enum rtx_code code = GET_CODE (x); 3124 3125 switch (code) 3126 { 3127 case CONST: 3128 case LABEL_REF: 3129 case SYMBOL_REF: 3130 CASE_CONST_ANY: 3131 case PC: 3132 case CC0: 3133 case HIGH: 3134 return 0; 3135 3136 case REG: 3137 return reg_equiv[REGNO (x)].replace; 3138 3139 default: 3140 break; 3141 } 3142 3143 fmt = GET_RTX_FORMAT (code); 3144 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3145 switch (fmt[i]) 3146 { 3147 case 'e': 3148 if (contains_replace_regs (XEXP (x, i))) 3149 return 1; 3150 break; 3151 case 'E': 3152 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3153 if (contains_replace_regs (XVECEXP (x, i, j))) 3154 return 1; 3155 break; 3156 } 3157 3158 return 0; 3159 } 3160 3161 /* TRUE if X references a memory location that would be affected by a store 3162 to MEMREF. */ 3163 static int 3164 memref_referenced_p (rtx memref, rtx x) 3165 { 3166 int i, j; 3167 const char *fmt; 3168 enum rtx_code code = GET_CODE (x); 3169 3170 switch (code) 3171 { 3172 case CONST: 3173 case LABEL_REF: 3174 case SYMBOL_REF: 3175 CASE_CONST_ANY: 3176 case PC: 3177 case CC0: 3178 case HIGH: 3179 case LO_SUM: 3180 return 0; 3181 3182 case REG: 3183 return (reg_equiv[REGNO (x)].replacement 3184 && memref_referenced_p (memref, 3185 reg_equiv[REGNO (x)].replacement)); 3186 3187 case MEM: 3188 if (true_dependence (memref, VOIDmode, x)) 3189 return 1; 3190 break; 3191 3192 case SET: 3193 /* If we are setting a MEM, it doesn't count (its address does), but any 3194 other SET_DEST that has a MEM in it is referencing the MEM. */ 3195 if (MEM_P (SET_DEST (x))) 3196 { 3197 if (memref_referenced_p (memref, XEXP (SET_DEST (x), 0))) 3198 return 1; 3199 } 3200 else if (memref_referenced_p (memref, SET_DEST (x))) 3201 return 1; 3202 3203 return memref_referenced_p (memref, SET_SRC (x)); 3204 3205 default: 3206 break; 3207 } 3208 3209 fmt = GET_RTX_FORMAT (code); 3210 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 3211 switch (fmt[i]) 3212 { 3213 case 'e': 3214 if (memref_referenced_p (memref, XEXP (x, i))) 3215 return 1; 3216 break; 3217 case 'E': 3218 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 3219 if (memref_referenced_p (memref, XVECEXP (x, i, j))) 3220 return 1; 3221 break; 3222 } 3223 3224 return 0; 3225 } 3226 3227 /* TRUE if some insn in the range (START, END] references a memory location 3228 that would be affected by a store to MEMREF. 3229 3230 Callers should not call this routine if START is after END in the 3231 RTL chain. */ 3232 3233 static int 3234 memref_used_between_p (rtx memref, rtx_insn *start, rtx_insn *end) 3235 { 3236 rtx_insn *insn; 3237 3238 for (insn = NEXT_INSN (start); 3239 insn && insn != NEXT_INSN (end); 3240 insn = NEXT_INSN (insn)) 3241 { 3242 if (!NONDEBUG_INSN_P (insn)) 3243 continue; 3244 3245 if (memref_referenced_p (memref, PATTERN (insn))) 3246 return 1; 3247 3248 /* Nonconst functions may access memory. */ 3249 if (CALL_P (insn) && (! RTL_CONST_CALL_P (insn))) 3250 return 1; 3251 } 3252 3253 gcc_assert (insn == NEXT_INSN (end)); 3254 return 0; 3255 } 3256 3257 /* Mark REG as having no known equivalence. 3258 Some instructions might have been processed before and furnished 3259 with REG_EQUIV notes for this register; these notes will have to be 3260 removed. 3261 STORE is the piece of RTL that does the non-constant / conflicting 3262 assignment - a SET, CLOBBER or REG_INC note. It is currently not used, 3263 but needs to be there because this function is called from note_stores. */ 3264 static void 3265 no_equiv (rtx reg, const_rtx store ATTRIBUTE_UNUSED, 3266 void *data ATTRIBUTE_UNUSED) 3267 { 3268 int regno; 3269 rtx_insn_list *list; 3270 3271 if (!REG_P (reg)) 3272 return; 3273 regno = REGNO (reg); 3274 reg_equiv[regno].no_equiv = 1; 3275 list = reg_equiv[regno].init_insns; 3276 if (list && list->insn () == NULL) 3277 return; 3278 reg_equiv[regno].init_insns = gen_rtx_INSN_LIST (VOIDmode, NULL_RTX, NULL); 3279 reg_equiv[regno].replacement = NULL_RTX; 3280 /* This doesn't matter for equivalences made for argument registers, we 3281 should keep their initialization insns. */ 3282 if (reg_equiv[regno].is_arg_equivalence) 3283 return; 3284 ira_reg_equiv[regno].defined_p = false; 3285 ira_reg_equiv[regno].init_insns = NULL; 3286 for (; list; list = list->next ()) 3287 { 3288 rtx_insn *insn = list->insn (); 3289 remove_note (insn, find_reg_note (insn, REG_EQUIV, NULL_RTX)); 3290 } 3291 } 3292 3293 /* Check whether the SUBREG is a paradoxical subreg and set the result 3294 in PDX_SUBREGS. */ 3295 3296 static void 3297 set_paradoxical_subreg (rtx_insn *insn, bool *pdx_subregs) 3298 { 3299 subrtx_iterator::array_type array; 3300 FOR_EACH_SUBRTX (iter, array, PATTERN (insn), NONCONST) 3301 { 3302 const_rtx subreg = *iter; 3303 if (GET_CODE (subreg) == SUBREG) 3304 { 3305 const_rtx reg = SUBREG_REG (subreg); 3306 if (REG_P (reg) && paradoxical_subreg_p (subreg)) 3307 pdx_subregs[REGNO (reg)] = true; 3308 } 3309 } 3310 } 3311 3312 /* In DEBUG_INSN location adjust REGs from CLEARED_REGS bitmap to the 3313 equivalent replacement. */ 3314 3315 static rtx 3316 adjust_cleared_regs (rtx loc, const_rtx old_rtx ATTRIBUTE_UNUSED, void *data) 3317 { 3318 if (REG_P (loc)) 3319 { 3320 bitmap cleared_regs = (bitmap) data; 3321 if (bitmap_bit_p (cleared_regs, REGNO (loc))) 3322 return simplify_replace_fn_rtx (copy_rtx (*reg_equiv[REGNO (loc)].src_p), 3323 NULL_RTX, adjust_cleared_regs, data); 3324 } 3325 return NULL_RTX; 3326 } 3327 3328 /* Find registers that are equivalent to a single value throughout the 3329 compilation (either because they can be referenced in memory or are 3330 set once from a single constant). Lower their priority for a 3331 register. 3332 3333 If such a register is only referenced once, try substituting its 3334 value into the using insn. If it succeeds, we can eliminate the 3335 register completely. 3336 3337 Initialize init_insns in ira_reg_equiv array. */ 3338 static void 3339 update_equiv_regs (void) 3340 { 3341 rtx_insn *insn; 3342 basic_block bb; 3343 int loop_depth; 3344 bitmap cleared_regs; 3345 bool *pdx_subregs; 3346 bitmap_head seen_insns; 3347 3348 /* Use pdx_subregs to show whether a reg is used in a paradoxical 3349 subreg. */ 3350 pdx_subregs = XCNEWVEC (bool, max_regno); 3351 3352 reg_equiv = XCNEWVEC (struct equivalence, max_regno); 3353 grow_reg_equivs (); 3354 3355 init_alias_analysis (); 3356 3357 /* Scan insns and set pdx_subregs[regno] if the reg is used in a 3358 paradoxical subreg. Don't set such reg equivalent to a mem, 3359 because lra will not substitute such equiv memory in order to 3360 prevent access beyond allocated memory for paradoxical memory subreg. */ 3361 FOR_EACH_BB_FN (bb, cfun) 3362 FOR_BB_INSNS (bb, insn) 3363 if (NONDEBUG_INSN_P (insn)) 3364 set_paradoxical_subreg (insn, pdx_subregs); 3365 3366 /* Scan the insns and find which registers have equivalences. Do this 3367 in a separate scan of the insns because (due to -fcse-follow-jumps) 3368 a register can be set below its use. */ 3369 FOR_EACH_BB_FN (bb, cfun) 3370 { 3371 loop_depth = bb_loop_depth (bb); 3372 3373 for (insn = BB_HEAD (bb); 3374 insn != NEXT_INSN (BB_END (bb)); 3375 insn = NEXT_INSN (insn)) 3376 { 3377 rtx note; 3378 rtx set; 3379 rtx dest, src; 3380 int regno; 3381 3382 if (! INSN_P (insn)) 3383 continue; 3384 3385 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 3386 if (REG_NOTE_KIND (note) == REG_INC) 3387 no_equiv (XEXP (note, 0), note, NULL); 3388 3389 set = single_set (insn); 3390 3391 /* If this insn contains more (or less) than a single SET, 3392 only mark all destinations as having no known equivalence. */ 3393 if (set == NULL_RTX 3394 || side_effects_p (SET_SRC (set))) 3395 { 3396 note_stores (PATTERN (insn), no_equiv, NULL); 3397 continue; 3398 } 3399 else if (GET_CODE (PATTERN (insn)) == PARALLEL) 3400 { 3401 int i; 3402 3403 for (i = XVECLEN (PATTERN (insn), 0) - 1; i >= 0; i--) 3404 { 3405 rtx part = XVECEXP (PATTERN (insn), 0, i); 3406 if (part != set) 3407 note_stores (part, no_equiv, NULL); 3408 } 3409 } 3410 3411 dest = SET_DEST (set); 3412 src = SET_SRC (set); 3413 3414 /* See if this is setting up the equivalence between an argument 3415 register and its stack slot. */ 3416 note = find_reg_note (insn, REG_EQUIV, NULL_RTX); 3417 if (note) 3418 { 3419 gcc_assert (REG_P (dest)); 3420 regno = REGNO (dest); 3421 3422 /* Note that we don't want to clear init_insns in 3423 ira_reg_equiv even if there are multiple sets of this 3424 register. */ 3425 reg_equiv[regno].is_arg_equivalence = 1; 3426 3427 /* The insn result can have equivalence memory although 3428 the equivalence is not set up by the insn. We add 3429 this insn to init insns as it is a flag for now that 3430 regno has an equivalence. We will remove the insn 3431 from init insn list later. */ 3432 if (rtx_equal_p (src, XEXP (note, 0)) || MEM_P (XEXP (note, 0))) 3433 ira_reg_equiv[regno].init_insns 3434 = gen_rtx_INSN_LIST (VOIDmode, insn, 3435 ira_reg_equiv[regno].init_insns); 3436 3437 /* Continue normally in case this is a candidate for 3438 replacements. */ 3439 } 3440 3441 if (!optimize) 3442 continue; 3443 3444 /* We only handle the case of a pseudo register being set 3445 once, or always to the same value. */ 3446 /* ??? The mn10200 port breaks if we add equivalences for 3447 values that need an ADDRESS_REGS register and set them equivalent 3448 to a MEM of a pseudo. The actual problem is in the over-conservative 3449 handling of INPADDR_ADDRESS / INPUT_ADDRESS / INPUT triples in 3450 calculate_needs, but we traditionally work around this problem 3451 here by rejecting equivalences when the destination is in a register 3452 that's likely spilled. This is fragile, of course, since the 3453 preferred class of a pseudo depends on all instructions that set 3454 or use it. */ 3455 3456 if (!REG_P (dest) 3457 || (regno = REGNO (dest)) < FIRST_PSEUDO_REGISTER 3458 || (reg_equiv[regno].init_insns 3459 && reg_equiv[regno].init_insns->insn () == NULL) 3460 || (targetm.class_likely_spilled_p (reg_preferred_class (regno)) 3461 && MEM_P (src) && ! reg_equiv[regno].is_arg_equivalence)) 3462 { 3463 /* This might be setting a SUBREG of a pseudo, a pseudo that is 3464 also set somewhere else to a constant. */ 3465 note_stores (set, no_equiv, NULL); 3466 continue; 3467 } 3468 3469 /* Don't set reg (if pdx_subregs[regno] == true) equivalent to a mem. */ 3470 if (MEM_P (src) && pdx_subregs[regno]) 3471 { 3472 note_stores (set, no_equiv, NULL); 3473 continue; 3474 } 3475 3476 note = find_reg_note (insn, REG_EQUAL, NULL_RTX); 3477 3478 /* cse sometimes generates function invariants, but doesn't put a 3479 REG_EQUAL note on the insn. Since this note would be redundant, 3480 there's no point creating it earlier than here. */ 3481 if (! note && ! rtx_varies_p (src, 0)) 3482 note = set_unique_reg_note (insn, REG_EQUAL, copy_rtx (src)); 3483 3484 /* Don't bother considering a REG_EQUAL note containing an EXPR_LIST 3485 since it represents a function call. */ 3486 if (note && GET_CODE (XEXP (note, 0)) == EXPR_LIST) 3487 note = NULL_RTX; 3488 3489 if (DF_REG_DEF_COUNT (regno) != 1) 3490 { 3491 bool equal_p = true; 3492 rtx_insn_list *list; 3493 3494 /* If we have already processed this pseudo and determined it 3495 can not have an equivalence, then honor that decision. */ 3496 if (reg_equiv[regno].no_equiv) 3497 continue; 3498 3499 if (! note 3500 || rtx_varies_p (XEXP (note, 0), 0) 3501 || (reg_equiv[regno].replacement 3502 && ! rtx_equal_p (XEXP (note, 0), 3503 reg_equiv[regno].replacement))) 3504 { 3505 no_equiv (dest, set, NULL); 3506 continue; 3507 } 3508 3509 list = reg_equiv[regno].init_insns; 3510 for (; list; list = list->next ()) 3511 { 3512 rtx note_tmp; 3513 rtx_insn *insn_tmp; 3514 3515 insn_tmp = list->insn (); 3516 note_tmp = find_reg_note (insn_tmp, REG_EQUAL, NULL_RTX); 3517 gcc_assert (note_tmp); 3518 if (! rtx_equal_p (XEXP (note, 0), XEXP (note_tmp, 0))) 3519 { 3520 equal_p = false; 3521 break; 3522 } 3523 } 3524 3525 if (! equal_p) 3526 { 3527 no_equiv (dest, set, NULL); 3528 continue; 3529 } 3530 } 3531 3532 /* Record this insn as initializing this register. */ 3533 reg_equiv[regno].init_insns 3534 = gen_rtx_INSN_LIST (VOIDmode, insn, reg_equiv[regno].init_insns); 3535 3536 /* If this register is known to be equal to a constant, record that 3537 it is always equivalent to the constant. */ 3538 if (DF_REG_DEF_COUNT (regno) == 1 3539 && note && ! rtx_varies_p (XEXP (note, 0), 0)) 3540 { 3541 rtx note_value = XEXP (note, 0); 3542 remove_note (insn, note); 3543 set_unique_reg_note (insn, REG_EQUIV, note_value); 3544 } 3545 3546 /* If this insn introduces a "constant" register, decrease the priority 3547 of that register. Record this insn if the register is only used once 3548 more and the equivalence value is the same as our source. 3549 3550 The latter condition is checked for two reasons: First, it is an 3551 indication that it may be more efficient to actually emit the insn 3552 as written (if no registers are available, reload will substitute 3553 the equivalence). Secondly, it avoids problems with any registers 3554 dying in this insn whose death notes would be missed. 3555 3556 If we don't have a REG_EQUIV note, see if this insn is loading 3557 a register used only in one basic block from a MEM. If so, and the 3558 MEM remains unchanged for the life of the register, add a REG_EQUIV 3559 note. */ 3560 note = find_reg_note (insn, REG_EQUIV, NULL_RTX); 3561 3562 if (note == NULL_RTX && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS 3563 && MEM_P (SET_SRC (set)) 3564 && validate_equiv_mem (insn, dest, SET_SRC (set))) 3565 note = set_unique_reg_note (insn, REG_EQUIV, copy_rtx (SET_SRC (set))); 3566 3567 if (note) 3568 { 3569 int regno = REGNO (dest); 3570 rtx x = XEXP (note, 0); 3571 3572 /* If we haven't done so, record for reload that this is an 3573 equivalencing insn. */ 3574 if (!reg_equiv[regno].is_arg_equivalence) 3575 ira_reg_equiv[regno].init_insns 3576 = gen_rtx_INSN_LIST (VOIDmode, insn, 3577 ira_reg_equiv[regno].init_insns); 3578 3579 reg_equiv[regno].replacement = x; 3580 reg_equiv[regno].src_p = &SET_SRC (set); 3581 reg_equiv[regno].loop_depth = (short) loop_depth; 3582 3583 /* Don't mess with things live during setjmp. */ 3584 if (REG_LIVE_LENGTH (regno) >= 0 && optimize) 3585 { 3586 /* Note that the statement below does not affect the priority 3587 in local-alloc! */ 3588 REG_LIVE_LENGTH (regno) *= 2; 3589 3590 /* If the register is referenced exactly twice, meaning it is 3591 set once and used once, indicate that the reference may be 3592 replaced by the equivalence we computed above. Do this 3593 even if the register is only used in one block so that 3594 dependencies can be handled where the last register is 3595 used in a different block (i.e. HIGH / LO_SUM sequences) 3596 and to reduce the number of registers alive across 3597 calls. */ 3598 3599 if (REG_N_REFS (regno) == 2 3600 && (rtx_equal_p (x, src) 3601 || ! equiv_init_varies_p (src)) 3602 && NONJUMP_INSN_P (insn) 3603 && equiv_init_movable_p (PATTERN (insn), regno)) 3604 reg_equiv[regno].replace = 1; 3605 } 3606 } 3607 } 3608 } 3609 3610 if (!optimize) 3611 goto out; 3612 3613 /* A second pass, to gather additional equivalences with memory. This needs 3614 to be done after we know which registers we are going to replace. */ 3615 3616 bitmap_initialize (&seen_insns, NULL); 3617 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 3618 { 3619 rtx set, src, dest; 3620 unsigned regno; 3621 3622 bitmap_set_bit (&seen_insns, INSN_UID (insn)); 3623 3624 if (! INSN_P (insn)) 3625 continue; 3626 3627 set = single_set (insn); 3628 if (! set) 3629 continue; 3630 3631 dest = SET_DEST (set); 3632 src = SET_SRC (set); 3633 3634 /* If this sets a MEM to the contents of a REG that is only used 3635 in a single basic block, see if the register is always equivalent 3636 to that memory location and if moving the store from INSN to the 3637 insn that set REG is safe. If so, put a REG_EQUIV note on the 3638 initializing insn. 3639 3640 Don't add a REG_EQUIV note if the insn already has one. The existing 3641 REG_EQUIV is likely more useful than the one we are adding. 3642 3643 If one of the regs in the address has reg_equiv[REGNO].replace set, 3644 then we can't add this REG_EQUIV note. The reg_equiv[REGNO].replace 3645 optimization may move the set of this register immediately before 3646 insn, which puts it after reg_equiv[REGNO].init_insns, and hence 3647 the mention in the REG_EQUIV note would be to an uninitialized 3648 pseudo. */ 3649 3650 if (MEM_P (dest) && REG_P (src) 3651 && (regno = REGNO (src)) >= FIRST_PSEUDO_REGISTER 3652 && REG_BASIC_BLOCK (regno) >= NUM_FIXED_BLOCKS 3653 && DF_REG_DEF_COUNT (regno) == 1 3654 && reg_equiv[regno].init_insns != NULL 3655 && reg_equiv[regno].init_insns->insn () != NULL 3656 && ! find_reg_note (XEXP (reg_equiv[regno].init_insns, 0), 3657 REG_EQUIV, NULL_RTX) 3658 && ! contains_replace_regs (XEXP (dest, 0)) 3659 && ! pdx_subregs[regno]) 3660 { 3661 rtx_insn *init_insn = 3662 as_a <rtx_insn *> (XEXP (reg_equiv[regno].init_insns, 0)); 3663 if (validate_equiv_mem (init_insn, src, dest) 3664 && bitmap_bit_p (&seen_insns, INSN_UID (init_insn)) 3665 && ! memref_used_between_p (dest, init_insn, insn) 3666 /* Attaching a REG_EQUIV note will fail if INIT_INSN has 3667 multiple sets. */ 3668 && set_unique_reg_note (init_insn, REG_EQUIV, copy_rtx (dest))) 3669 { 3670 /* This insn makes the equivalence, not the one initializing 3671 the register. */ 3672 ira_reg_equiv[regno].init_insns 3673 = gen_rtx_INSN_LIST (VOIDmode, insn, NULL_RTX); 3674 df_notes_rescan (init_insn); 3675 if (dump_file) 3676 fprintf (dump_file, 3677 "Adding REG_EQUIV to insn %d for source of insn %d\n", 3678 INSN_UID (init_insn), 3679 INSN_UID (insn)); 3680 } 3681 } 3682 } 3683 bitmap_clear (&seen_insns); 3684 3685 cleared_regs = BITMAP_ALLOC (NULL); 3686 /* Now scan all regs killed in an insn to see if any of them are 3687 registers only used that once. If so, see if we can replace the 3688 reference with the equivalent form. If we can, delete the 3689 initializing reference and this register will go away. If we 3690 can't replace the reference, and the initializing reference is 3691 within the same loop (or in an inner loop), then move the register 3692 initialization just before the use, so that they are in the same 3693 basic block. */ 3694 FOR_EACH_BB_REVERSE_FN (bb, cfun) 3695 { 3696 loop_depth = bb_loop_depth (bb); 3697 for (insn = BB_END (bb); 3698 insn != PREV_INSN (BB_HEAD (bb)); 3699 insn = PREV_INSN (insn)) 3700 { 3701 rtx link; 3702 3703 if (! INSN_P (insn)) 3704 continue; 3705 3706 /* Don't substitute into jumps. indirect_jump_optimize does 3707 this for anything we are prepared to handle. */ 3708 if (JUMP_P (insn)) 3709 continue; 3710 3711 for (link = REG_NOTES (insn); link; link = XEXP (link, 1)) 3712 { 3713 if (REG_NOTE_KIND (link) == REG_DEAD 3714 /* Make sure this insn still refers to the register. */ 3715 && reg_mentioned_p (XEXP (link, 0), PATTERN (insn))) 3716 { 3717 int regno = REGNO (XEXP (link, 0)); 3718 rtx equiv_insn; 3719 3720 if (! reg_equiv[regno].replace 3721 || reg_equiv[regno].loop_depth < (short) loop_depth 3722 /* There is no sense to move insns if live range 3723 shrinkage or register pressure-sensitive 3724 scheduling were done because it will not 3725 improve allocation but worsen insn schedule 3726 with a big probability. */ 3727 || flag_live_range_shrinkage 3728 || (flag_sched_pressure && flag_schedule_insns)) 3729 continue; 3730 3731 /* reg_equiv[REGNO].replace gets set only when 3732 REG_N_REFS[REGNO] is 2, i.e. the register is set 3733 once and used once. (If it were only set, but 3734 not used, flow would have deleted the setting 3735 insns.) Hence there can only be one insn in 3736 reg_equiv[REGNO].init_insns. */ 3737 gcc_assert (reg_equiv[regno].init_insns 3738 && !XEXP (reg_equiv[regno].init_insns, 1)); 3739 equiv_insn = XEXP (reg_equiv[regno].init_insns, 0); 3740 3741 /* We may not move instructions that can throw, since 3742 that changes basic block boundaries and we are not 3743 prepared to adjust the CFG to match. */ 3744 if (can_throw_internal (equiv_insn)) 3745 continue; 3746 3747 if (asm_noperands (PATTERN (equiv_insn)) < 0 3748 && validate_replace_rtx (regno_reg_rtx[regno], 3749 *(reg_equiv[regno].src_p), insn)) 3750 { 3751 rtx equiv_link; 3752 rtx last_link; 3753 rtx note; 3754 3755 /* Find the last note. */ 3756 for (last_link = link; XEXP (last_link, 1); 3757 last_link = XEXP (last_link, 1)) 3758 ; 3759 3760 /* Append the REG_DEAD notes from equiv_insn. */ 3761 equiv_link = REG_NOTES (equiv_insn); 3762 while (equiv_link) 3763 { 3764 note = equiv_link; 3765 equiv_link = XEXP (equiv_link, 1); 3766 if (REG_NOTE_KIND (note) == REG_DEAD) 3767 { 3768 remove_note (equiv_insn, note); 3769 XEXP (last_link, 1) = note; 3770 XEXP (note, 1) = NULL_RTX; 3771 last_link = note; 3772 } 3773 } 3774 3775 remove_death (regno, insn); 3776 SET_REG_N_REFS (regno, 0); 3777 REG_FREQ (regno) = 0; 3778 delete_insn (equiv_insn); 3779 3780 reg_equiv[regno].init_insns 3781 = reg_equiv[regno].init_insns->next (); 3782 3783 ira_reg_equiv[regno].init_insns = NULL; 3784 bitmap_set_bit (cleared_regs, regno); 3785 } 3786 /* Move the initialization of the register to just before 3787 INSN. Update the flow information. */ 3788 else if (prev_nondebug_insn (insn) != equiv_insn) 3789 { 3790 rtx_insn *new_insn; 3791 3792 new_insn = emit_insn_before (PATTERN (equiv_insn), insn); 3793 REG_NOTES (new_insn) = REG_NOTES (equiv_insn); 3794 REG_NOTES (equiv_insn) = 0; 3795 /* Rescan it to process the notes. */ 3796 df_insn_rescan (new_insn); 3797 3798 /* Make sure this insn is recognized before 3799 reload begins, otherwise 3800 eliminate_regs_in_insn will die. */ 3801 INSN_CODE (new_insn) = INSN_CODE (equiv_insn); 3802 3803 delete_insn (equiv_insn); 3804 3805 XEXP (reg_equiv[regno].init_insns, 0) = new_insn; 3806 3807 REG_BASIC_BLOCK (regno) = bb->index; 3808 REG_N_CALLS_CROSSED (regno) = 0; 3809 REG_FREQ_CALLS_CROSSED (regno) = 0; 3810 REG_N_THROWING_CALLS_CROSSED (regno) = 0; 3811 REG_LIVE_LENGTH (regno) = 2; 3812 3813 if (insn == BB_HEAD (bb)) 3814 BB_HEAD (bb) = PREV_INSN (insn); 3815 3816 ira_reg_equiv[regno].init_insns 3817 = gen_rtx_INSN_LIST (VOIDmode, new_insn, NULL_RTX); 3818 bitmap_set_bit (cleared_regs, regno); 3819 } 3820 } 3821 } 3822 } 3823 } 3824 3825 if (!bitmap_empty_p (cleared_regs)) 3826 { 3827 FOR_EACH_BB_FN (bb, cfun) 3828 { 3829 bitmap_and_compl_into (DF_LR_IN (bb), cleared_regs); 3830 bitmap_and_compl_into (DF_LR_OUT (bb), cleared_regs); 3831 if (! df_live) 3832 continue; 3833 bitmap_and_compl_into (DF_LIVE_IN (bb), cleared_regs); 3834 bitmap_and_compl_into (DF_LIVE_OUT (bb), cleared_regs); 3835 } 3836 3837 /* Last pass - adjust debug insns referencing cleared regs. */ 3838 if (MAY_HAVE_DEBUG_INSNS) 3839 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 3840 if (DEBUG_INSN_P (insn)) 3841 { 3842 rtx old_loc = INSN_VAR_LOCATION_LOC (insn); 3843 INSN_VAR_LOCATION_LOC (insn) 3844 = simplify_replace_fn_rtx (old_loc, NULL_RTX, 3845 adjust_cleared_regs, 3846 (void *) cleared_regs); 3847 if (old_loc != INSN_VAR_LOCATION_LOC (insn)) 3848 df_insn_rescan (insn); 3849 } 3850 } 3851 3852 BITMAP_FREE (cleared_regs); 3853 3854 out: 3855 /* Clean up. */ 3856 3857 end_alias_analysis (); 3858 free (reg_equiv); 3859 free (pdx_subregs); 3860 } 3861 3862 /* A pass over indirect jumps, converting simple cases to direct jumps. 3863 Combine does this optimization too, but only within a basic block. */ 3864 static void 3865 indirect_jump_optimize (void) 3866 { 3867 basic_block bb; 3868 bool rebuild_p = false; 3869 3870 FOR_EACH_BB_REVERSE_FN (bb, cfun) 3871 { 3872 rtx_insn *insn = BB_END (bb); 3873 if (!JUMP_P (insn) 3874 || find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) 3875 continue; 3876 3877 rtx x = pc_set (insn); 3878 if (!x || !REG_P (SET_SRC (x))) 3879 continue; 3880 3881 int regno = REGNO (SET_SRC (x)); 3882 if (DF_REG_DEF_COUNT (regno) == 1) 3883 { 3884 df_ref def = DF_REG_DEF_CHAIN (regno); 3885 if (!DF_REF_IS_ARTIFICIAL (def)) 3886 { 3887 rtx_insn *def_insn = DF_REF_INSN (def); 3888 rtx lab = NULL_RTX; 3889 rtx set = single_set (def_insn); 3890 if (set && GET_CODE (SET_SRC (set)) == LABEL_REF) 3891 lab = SET_SRC (set); 3892 else 3893 { 3894 rtx eqnote = find_reg_note (def_insn, REG_EQUAL, NULL_RTX); 3895 if (eqnote && GET_CODE (XEXP (eqnote, 0)) == LABEL_REF) 3896 lab = XEXP (eqnote, 0); 3897 } 3898 if (lab && validate_replace_rtx (SET_SRC (x), lab, insn)) 3899 rebuild_p = true; 3900 } 3901 } 3902 } 3903 3904 if (rebuild_p) 3905 { 3906 timevar_push (TV_JUMP); 3907 rebuild_jump_labels (get_insns ()); 3908 if (purge_all_dead_edges ()) 3909 delete_unreachable_blocks (); 3910 timevar_pop (TV_JUMP); 3911 } 3912 } 3913 3914 /* Set up fields memory, constant, and invariant from init_insns in 3915 the structures of array ira_reg_equiv. */ 3916 static void 3917 setup_reg_equiv (void) 3918 { 3919 int i; 3920 rtx_insn_list *elem, *prev_elem, *next_elem; 3921 rtx_insn *insn; 3922 rtx set, x; 3923 3924 for (i = FIRST_PSEUDO_REGISTER; i < ira_reg_equiv_len; i++) 3925 for (prev_elem = NULL, elem = ira_reg_equiv[i].init_insns; 3926 elem; 3927 prev_elem = elem, elem = next_elem) 3928 { 3929 next_elem = elem->next (); 3930 insn = elem->insn (); 3931 set = single_set (insn); 3932 3933 /* Init insns can set up equivalence when the reg is a destination or 3934 a source (in this case the destination is memory). */ 3935 if (set != 0 && (REG_P (SET_DEST (set)) || REG_P (SET_SRC (set)))) 3936 { 3937 if ((x = find_reg_note (insn, REG_EQUIV, NULL_RTX)) != NULL) 3938 { 3939 x = XEXP (x, 0); 3940 if (REG_P (SET_DEST (set)) 3941 && REGNO (SET_DEST (set)) == (unsigned int) i 3942 && ! rtx_equal_p (SET_SRC (set), x) && MEM_P (x)) 3943 { 3944 /* This insn reporting the equivalence but 3945 actually not setting it. Remove it from the 3946 list. */ 3947 if (prev_elem == NULL) 3948 ira_reg_equiv[i].init_insns = next_elem; 3949 else 3950 XEXP (prev_elem, 1) = next_elem; 3951 elem = prev_elem; 3952 } 3953 } 3954 else if (REG_P (SET_DEST (set)) 3955 && REGNO (SET_DEST (set)) == (unsigned int) i) 3956 x = SET_SRC (set); 3957 else 3958 { 3959 gcc_assert (REG_P (SET_SRC (set)) 3960 && REGNO (SET_SRC (set)) == (unsigned int) i); 3961 x = SET_DEST (set); 3962 } 3963 if (! function_invariant_p (x) 3964 || ! flag_pic 3965 /* A function invariant is often CONSTANT_P but may 3966 include a register. We promise to only pass 3967 CONSTANT_P objects to LEGITIMATE_PIC_OPERAND_P. */ 3968 || (CONSTANT_P (x) && LEGITIMATE_PIC_OPERAND_P (x))) 3969 { 3970 /* It can happen that a REG_EQUIV note contains a MEM 3971 that is not a legitimate memory operand. As later 3972 stages of reload assume that all addresses found in 3973 the lra_regno_equiv_* arrays were originally 3974 legitimate, we ignore such REG_EQUIV notes. */ 3975 if (memory_operand (x, VOIDmode)) 3976 { 3977 ira_reg_equiv[i].defined_p = true; 3978 ira_reg_equiv[i].memory = x; 3979 continue; 3980 } 3981 else if (function_invariant_p (x)) 3982 { 3983 machine_mode mode; 3984 3985 mode = GET_MODE (SET_DEST (set)); 3986 if (GET_CODE (x) == PLUS 3987 || x == frame_pointer_rtx || x == arg_pointer_rtx) 3988 /* This is PLUS of frame pointer and a constant, 3989 or fp, or argp. */ 3990 ira_reg_equiv[i].invariant = x; 3991 else if (targetm.legitimate_constant_p (mode, x)) 3992 ira_reg_equiv[i].constant = x; 3993 else 3994 { 3995 ira_reg_equiv[i].memory = force_const_mem (mode, x); 3996 if (ira_reg_equiv[i].memory == NULL_RTX) 3997 { 3998 ira_reg_equiv[i].defined_p = false; 3999 ira_reg_equiv[i].init_insns = NULL; 4000 break; 4001 } 4002 } 4003 ira_reg_equiv[i].defined_p = true; 4004 continue; 4005 } 4006 } 4007 } 4008 ira_reg_equiv[i].defined_p = false; 4009 ira_reg_equiv[i].init_insns = NULL; 4010 break; 4011 } 4012 } 4013 4014 4015 4016 /* Print chain C to FILE. */ 4017 static void 4018 print_insn_chain (FILE *file, struct insn_chain *c) 4019 { 4020 fprintf (file, "insn=%d, ", INSN_UID (c->insn)); 4021 bitmap_print (file, &c->live_throughout, "live_throughout: ", ", "); 4022 bitmap_print (file, &c->dead_or_set, "dead_or_set: ", "\n"); 4023 } 4024 4025 4026 /* Print all reload_insn_chains to FILE. */ 4027 static void 4028 print_insn_chains (FILE *file) 4029 { 4030 struct insn_chain *c; 4031 for (c = reload_insn_chain; c ; c = c->next) 4032 print_insn_chain (file, c); 4033 } 4034 4035 /* Return true if pseudo REGNO should be added to set live_throughout 4036 or dead_or_set of the insn chains for reload consideration. */ 4037 static bool 4038 pseudo_for_reload_consideration_p (int regno) 4039 { 4040 /* Consider spilled pseudos too for IRA because they still have a 4041 chance to get hard-registers in the reload when IRA is used. */ 4042 return (reg_renumber[regno] >= 0 || ira_conflicts_p); 4043 } 4044 4045 /* Init LIVE_SUBREGS[ALLOCNUM] and LIVE_SUBREGS_USED[ALLOCNUM] using 4046 REG to the number of nregs, and INIT_VALUE to get the 4047 initialization. ALLOCNUM need not be the regno of REG. */ 4048 static void 4049 init_live_subregs (bool init_value, sbitmap *live_subregs, 4050 bitmap live_subregs_used, int allocnum, rtx reg) 4051 { 4052 unsigned int regno = REGNO (SUBREG_REG (reg)); 4053 int size = GET_MODE_SIZE (GET_MODE (regno_reg_rtx[regno])); 4054 4055 gcc_assert (size > 0); 4056 4057 /* Been there, done that. */ 4058 if (bitmap_bit_p (live_subregs_used, allocnum)) 4059 return; 4060 4061 /* Create a new one. */ 4062 if (live_subregs[allocnum] == NULL) 4063 live_subregs[allocnum] = sbitmap_alloc (size); 4064 4065 /* If the entire reg was live before blasting into subregs, we need 4066 to init all of the subregs to ones else init to 0. */ 4067 if (init_value) 4068 bitmap_ones (live_subregs[allocnum]); 4069 else 4070 bitmap_clear (live_subregs[allocnum]); 4071 4072 bitmap_set_bit (live_subregs_used, allocnum); 4073 } 4074 4075 /* Walk the insns of the current function and build reload_insn_chain, 4076 and record register life information. */ 4077 static void 4078 build_insn_chain (void) 4079 { 4080 unsigned int i; 4081 struct insn_chain **p = &reload_insn_chain; 4082 basic_block bb; 4083 struct insn_chain *c = NULL; 4084 struct insn_chain *next = NULL; 4085 bitmap live_relevant_regs = BITMAP_ALLOC (NULL); 4086 bitmap elim_regset = BITMAP_ALLOC (NULL); 4087 /* live_subregs is a vector used to keep accurate information about 4088 which hardregs are live in multiword pseudos. live_subregs and 4089 live_subregs_used are indexed by pseudo number. The live_subreg 4090 entry for a particular pseudo is only used if the corresponding 4091 element is non zero in live_subregs_used. The sbitmap size of 4092 live_subreg[allocno] is number of bytes that the pseudo can 4093 occupy. */ 4094 sbitmap *live_subregs = XCNEWVEC (sbitmap, max_regno); 4095 bitmap live_subregs_used = BITMAP_ALLOC (NULL); 4096 4097 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 4098 if (TEST_HARD_REG_BIT (eliminable_regset, i)) 4099 bitmap_set_bit (elim_regset, i); 4100 FOR_EACH_BB_REVERSE_FN (bb, cfun) 4101 { 4102 bitmap_iterator bi; 4103 rtx_insn *insn; 4104 4105 CLEAR_REG_SET (live_relevant_regs); 4106 bitmap_clear (live_subregs_used); 4107 4108 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), 0, i, bi) 4109 { 4110 if (i >= FIRST_PSEUDO_REGISTER) 4111 break; 4112 bitmap_set_bit (live_relevant_regs, i); 4113 } 4114 4115 EXECUTE_IF_SET_IN_BITMAP (df_get_live_out (bb), 4116 FIRST_PSEUDO_REGISTER, i, bi) 4117 { 4118 if (pseudo_for_reload_consideration_p (i)) 4119 bitmap_set_bit (live_relevant_regs, i); 4120 } 4121 4122 FOR_BB_INSNS_REVERSE (bb, insn) 4123 { 4124 if (!NOTE_P (insn) && !BARRIER_P (insn)) 4125 { 4126 struct df_insn_info *insn_info = DF_INSN_INFO_GET (insn); 4127 df_ref def, use; 4128 4129 c = new_insn_chain (); 4130 c->next = next; 4131 next = c; 4132 *p = c; 4133 p = &c->prev; 4134 4135 c->insn = insn; 4136 c->block = bb->index; 4137 4138 if (NONDEBUG_INSN_P (insn)) 4139 FOR_EACH_INSN_INFO_DEF (def, insn_info) 4140 { 4141 unsigned int regno = DF_REF_REGNO (def); 4142 4143 /* Ignore may clobbers because these are generated 4144 from calls. However, every other kind of def is 4145 added to dead_or_set. */ 4146 if (!DF_REF_FLAGS_IS_SET (def, DF_REF_MAY_CLOBBER)) 4147 { 4148 if (regno < FIRST_PSEUDO_REGISTER) 4149 { 4150 if (!fixed_regs[regno]) 4151 bitmap_set_bit (&c->dead_or_set, regno); 4152 } 4153 else if (pseudo_for_reload_consideration_p (regno)) 4154 bitmap_set_bit (&c->dead_or_set, regno); 4155 } 4156 4157 if ((regno < FIRST_PSEUDO_REGISTER 4158 || reg_renumber[regno] >= 0 4159 || ira_conflicts_p) 4160 && (!DF_REF_FLAGS_IS_SET (def, DF_REF_CONDITIONAL))) 4161 { 4162 rtx reg = DF_REF_REG (def); 4163 4164 /* We can model subregs, but not if they are 4165 wrapped in ZERO_EXTRACTS. */ 4166 if (GET_CODE (reg) == SUBREG 4167 && !DF_REF_FLAGS_IS_SET (def, DF_REF_ZERO_EXTRACT)) 4168 { 4169 unsigned int start = SUBREG_BYTE (reg); 4170 unsigned int last = start 4171 + GET_MODE_SIZE (GET_MODE (reg)); 4172 4173 init_live_subregs 4174 (bitmap_bit_p (live_relevant_regs, regno), 4175 live_subregs, live_subregs_used, regno, reg); 4176 4177 if (!DF_REF_FLAGS_IS_SET 4178 (def, DF_REF_STRICT_LOW_PART)) 4179 { 4180 /* Expand the range to cover entire words. 4181 Bytes added here are "don't care". */ 4182 start 4183 = start / UNITS_PER_WORD * UNITS_PER_WORD; 4184 last = ((last + UNITS_PER_WORD - 1) 4185 / UNITS_PER_WORD * UNITS_PER_WORD); 4186 } 4187 4188 /* Ignore the paradoxical bits. */ 4189 if (last > SBITMAP_SIZE (live_subregs[regno])) 4190 last = SBITMAP_SIZE (live_subregs[regno]); 4191 4192 while (start < last) 4193 { 4194 bitmap_clear_bit (live_subregs[regno], start); 4195 start++; 4196 } 4197 4198 if (bitmap_empty_p (live_subregs[regno])) 4199 { 4200 bitmap_clear_bit (live_subregs_used, regno); 4201 bitmap_clear_bit (live_relevant_regs, regno); 4202 } 4203 else 4204 /* Set live_relevant_regs here because 4205 that bit has to be true to get us to 4206 look at the live_subregs fields. */ 4207 bitmap_set_bit (live_relevant_regs, regno); 4208 } 4209 else 4210 { 4211 /* DF_REF_PARTIAL is generated for 4212 subregs, STRICT_LOW_PART, and 4213 ZERO_EXTRACT. We handle the subreg 4214 case above so here we have to keep from 4215 modeling the def as a killing def. */ 4216 if (!DF_REF_FLAGS_IS_SET (def, DF_REF_PARTIAL)) 4217 { 4218 bitmap_clear_bit (live_subregs_used, regno); 4219 bitmap_clear_bit (live_relevant_regs, regno); 4220 } 4221 } 4222 } 4223 } 4224 4225 bitmap_and_compl_into (live_relevant_regs, elim_regset); 4226 bitmap_copy (&c->live_throughout, live_relevant_regs); 4227 4228 if (NONDEBUG_INSN_P (insn)) 4229 FOR_EACH_INSN_INFO_USE (use, insn_info) 4230 { 4231 unsigned int regno = DF_REF_REGNO (use); 4232 rtx reg = DF_REF_REG (use); 4233 4234 /* DF_REF_READ_WRITE on a use means that this use 4235 is fabricated from a def that is a partial set 4236 to a multiword reg. Here, we only model the 4237 subreg case that is not wrapped in ZERO_EXTRACT 4238 precisely so we do not need to look at the 4239 fabricated use. */ 4240 if (DF_REF_FLAGS_IS_SET (use, DF_REF_READ_WRITE) 4241 && !DF_REF_FLAGS_IS_SET (use, DF_REF_ZERO_EXTRACT) 4242 && DF_REF_FLAGS_IS_SET (use, DF_REF_SUBREG)) 4243 continue; 4244 4245 /* Add the last use of each var to dead_or_set. */ 4246 if (!bitmap_bit_p (live_relevant_regs, regno)) 4247 { 4248 if (regno < FIRST_PSEUDO_REGISTER) 4249 { 4250 if (!fixed_regs[regno]) 4251 bitmap_set_bit (&c->dead_or_set, regno); 4252 } 4253 else if (pseudo_for_reload_consideration_p (regno)) 4254 bitmap_set_bit (&c->dead_or_set, regno); 4255 } 4256 4257 if (regno < FIRST_PSEUDO_REGISTER 4258 || pseudo_for_reload_consideration_p (regno)) 4259 { 4260 if (GET_CODE (reg) == SUBREG 4261 && !DF_REF_FLAGS_IS_SET (use, 4262 DF_REF_SIGN_EXTRACT 4263 | DF_REF_ZERO_EXTRACT)) 4264 { 4265 unsigned int start = SUBREG_BYTE (reg); 4266 unsigned int last = start 4267 + GET_MODE_SIZE (GET_MODE (reg)); 4268 4269 init_live_subregs 4270 (bitmap_bit_p (live_relevant_regs, regno), 4271 live_subregs, live_subregs_used, regno, reg); 4272 4273 /* Ignore the paradoxical bits. */ 4274 if (last > SBITMAP_SIZE (live_subregs[regno])) 4275 last = SBITMAP_SIZE (live_subregs[regno]); 4276 4277 while (start < last) 4278 { 4279 bitmap_set_bit (live_subregs[regno], start); 4280 start++; 4281 } 4282 } 4283 else 4284 /* Resetting the live_subregs_used is 4285 effectively saying do not use the subregs 4286 because we are reading the whole 4287 pseudo. */ 4288 bitmap_clear_bit (live_subregs_used, regno); 4289 bitmap_set_bit (live_relevant_regs, regno); 4290 } 4291 } 4292 } 4293 } 4294 4295 /* FIXME!! The following code is a disaster. Reload needs to see the 4296 labels and jump tables that are just hanging out in between 4297 the basic blocks. See pr33676. */ 4298 insn = BB_HEAD (bb); 4299 4300 /* Skip over the barriers and cruft. */ 4301 while (insn && (BARRIER_P (insn) || NOTE_P (insn) 4302 || BLOCK_FOR_INSN (insn) == bb)) 4303 insn = PREV_INSN (insn); 4304 4305 /* While we add anything except barriers and notes, the focus is 4306 to get the labels and jump tables into the 4307 reload_insn_chain. */ 4308 while (insn) 4309 { 4310 if (!NOTE_P (insn) && !BARRIER_P (insn)) 4311 { 4312 if (BLOCK_FOR_INSN (insn)) 4313 break; 4314 4315 c = new_insn_chain (); 4316 c->next = next; 4317 next = c; 4318 *p = c; 4319 p = &c->prev; 4320 4321 /* The block makes no sense here, but it is what the old 4322 code did. */ 4323 c->block = bb->index; 4324 c->insn = insn; 4325 bitmap_copy (&c->live_throughout, live_relevant_regs); 4326 } 4327 insn = PREV_INSN (insn); 4328 } 4329 } 4330 4331 reload_insn_chain = c; 4332 *p = NULL; 4333 4334 for (i = 0; i < (unsigned int) max_regno; i++) 4335 if (live_subregs[i] != NULL) 4336 sbitmap_free (live_subregs[i]); 4337 free (live_subregs); 4338 BITMAP_FREE (live_subregs_used); 4339 BITMAP_FREE (live_relevant_regs); 4340 BITMAP_FREE (elim_regset); 4341 4342 if (dump_file) 4343 print_insn_chains (dump_file); 4344 } 4345 4346 /* Examine the rtx found in *LOC, which is read or written to as determined 4347 by TYPE. Return false if we find a reason why an insn containing this 4348 rtx should not be moved (such as accesses to non-constant memory), true 4349 otherwise. */ 4350 static bool 4351 rtx_moveable_p (rtx *loc, enum op_type type) 4352 { 4353 const char *fmt; 4354 rtx x = *loc; 4355 enum rtx_code code = GET_CODE (x); 4356 int i, j; 4357 4358 code = GET_CODE (x); 4359 switch (code) 4360 { 4361 case CONST: 4362 CASE_CONST_ANY: 4363 case SYMBOL_REF: 4364 case LABEL_REF: 4365 return true; 4366 4367 case PC: 4368 return type == OP_IN; 4369 4370 case CC0: 4371 return false; 4372 4373 case REG: 4374 if (x == frame_pointer_rtx) 4375 return true; 4376 if (HARD_REGISTER_P (x)) 4377 return false; 4378 4379 return true; 4380 4381 case MEM: 4382 if (type == OP_IN && MEM_READONLY_P (x)) 4383 return rtx_moveable_p (&XEXP (x, 0), OP_IN); 4384 return false; 4385 4386 case SET: 4387 return (rtx_moveable_p (&SET_SRC (x), OP_IN) 4388 && rtx_moveable_p (&SET_DEST (x), OP_OUT)); 4389 4390 case STRICT_LOW_PART: 4391 return rtx_moveable_p (&XEXP (x, 0), OP_OUT); 4392 4393 case ZERO_EXTRACT: 4394 case SIGN_EXTRACT: 4395 return (rtx_moveable_p (&XEXP (x, 0), type) 4396 && rtx_moveable_p (&XEXP (x, 1), OP_IN) 4397 && rtx_moveable_p (&XEXP (x, 2), OP_IN)); 4398 4399 case CLOBBER: 4400 return rtx_moveable_p (&SET_DEST (x), OP_OUT); 4401 4402 case UNSPEC_VOLATILE: 4403 /* It is a bad idea to consider insns with such rtl 4404 as moveable ones. The insn scheduler also considers them as barrier 4405 for a reason. */ 4406 return false; 4407 4408 default: 4409 break; 4410 } 4411 4412 fmt = GET_RTX_FORMAT (code); 4413 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 4414 { 4415 if (fmt[i] == 'e') 4416 { 4417 if (!rtx_moveable_p (&XEXP (x, i), type)) 4418 return false; 4419 } 4420 else if (fmt[i] == 'E') 4421 for (j = XVECLEN (x, i) - 1; j >= 0; j--) 4422 { 4423 if (!rtx_moveable_p (&XVECEXP (x, i, j), type)) 4424 return false; 4425 } 4426 } 4427 return true; 4428 } 4429 4430 /* A wrapper around dominated_by_p, which uses the information in UID_LUID 4431 to give dominance relationships between two insns I1 and I2. */ 4432 static bool 4433 insn_dominated_by_p (rtx i1, rtx i2, int *uid_luid) 4434 { 4435 basic_block bb1 = BLOCK_FOR_INSN (i1); 4436 basic_block bb2 = BLOCK_FOR_INSN (i2); 4437 4438 if (bb1 == bb2) 4439 return uid_luid[INSN_UID (i2)] < uid_luid[INSN_UID (i1)]; 4440 return dominated_by_p (CDI_DOMINATORS, bb1, bb2); 4441 } 4442 4443 /* Record the range of register numbers added by find_moveable_pseudos. */ 4444 int first_moveable_pseudo, last_moveable_pseudo; 4445 4446 /* These two vectors hold data for every register added by 4447 find_movable_pseudos, with index 0 holding data for the 4448 first_moveable_pseudo. */ 4449 /* The original home register. */ 4450 static vec<rtx> pseudo_replaced_reg; 4451 4452 /* Look for instances where we have an instruction that is known to increase 4453 register pressure, and whose result is not used immediately. If it is 4454 possible to move the instruction downwards to just before its first use, 4455 split its lifetime into two ranges. We create a new pseudo to compute the 4456 value, and emit a move instruction just before the first use. If, after 4457 register allocation, the new pseudo remains unallocated, the function 4458 move_unallocated_pseudos then deletes the move instruction and places 4459 the computation just before the first use. 4460 4461 Such a move is safe and profitable if all the input registers remain live 4462 and unchanged between the original computation and its first use. In such 4463 a situation, the computation is known to increase register pressure, and 4464 moving it is known to at least not worsen it. 4465 4466 We restrict moves to only those cases where a register remains unallocated, 4467 in order to avoid interfering too much with the instruction schedule. As 4468 an exception, we may move insns which only modify their input register 4469 (typically induction variables), as this increases the freedom for our 4470 intended transformation, and does not limit the second instruction 4471 scheduler pass. */ 4472 4473 static void 4474 find_moveable_pseudos (void) 4475 { 4476 unsigned i; 4477 int max_regs = max_reg_num (); 4478 int max_uid = get_max_uid (); 4479 basic_block bb; 4480 int *uid_luid = XNEWVEC (int, max_uid); 4481 rtx_insn **closest_uses = XNEWVEC (rtx_insn *, max_regs); 4482 /* A set of registers which are live but not modified throughout a block. */ 4483 bitmap_head *bb_transp_live = XNEWVEC (bitmap_head, 4484 last_basic_block_for_fn (cfun)); 4485 /* A set of registers which only exist in a given basic block. */ 4486 bitmap_head *bb_local = XNEWVEC (bitmap_head, 4487 last_basic_block_for_fn (cfun)); 4488 /* A set of registers which are set once, in an instruction that can be 4489 moved freely downwards, but are otherwise transparent to a block. */ 4490 bitmap_head *bb_moveable_reg_sets = XNEWVEC (bitmap_head, 4491 last_basic_block_for_fn (cfun)); 4492 bitmap_head live, used, set, interesting, unusable_as_input; 4493 bitmap_iterator bi; 4494 bitmap_initialize (&interesting, 0); 4495 4496 first_moveable_pseudo = max_regs; 4497 pseudo_replaced_reg.release (); 4498 pseudo_replaced_reg.safe_grow_cleared (max_regs); 4499 4500 df_analyze (); 4501 calculate_dominance_info (CDI_DOMINATORS); 4502 4503 i = 0; 4504 bitmap_initialize (&live, 0); 4505 bitmap_initialize (&used, 0); 4506 bitmap_initialize (&set, 0); 4507 bitmap_initialize (&unusable_as_input, 0); 4508 FOR_EACH_BB_FN (bb, cfun) 4509 { 4510 rtx_insn *insn; 4511 bitmap transp = bb_transp_live + bb->index; 4512 bitmap moveable = bb_moveable_reg_sets + bb->index; 4513 bitmap local = bb_local + bb->index; 4514 4515 bitmap_initialize (local, 0); 4516 bitmap_initialize (transp, 0); 4517 bitmap_initialize (moveable, 0); 4518 bitmap_copy (&live, df_get_live_out (bb)); 4519 bitmap_and_into (&live, df_get_live_in (bb)); 4520 bitmap_copy (transp, &live); 4521 bitmap_clear (moveable); 4522 bitmap_clear (&live); 4523 bitmap_clear (&used); 4524 bitmap_clear (&set); 4525 FOR_BB_INSNS (bb, insn) 4526 if (NONDEBUG_INSN_P (insn)) 4527 { 4528 df_insn_info *insn_info = DF_INSN_INFO_GET (insn); 4529 df_ref def, use; 4530 4531 uid_luid[INSN_UID (insn)] = i++; 4532 4533 def = df_single_def (insn_info); 4534 use = df_single_use (insn_info); 4535 if (use 4536 && def 4537 && DF_REF_REGNO (use) == DF_REF_REGNO (def) 4538 && !bitmap_bit_p (&set, DF_REF_REGNO (use)) 4539 && rtx_moveable_p (&PATTERN (insn), OP_IN)) 4540 { 4541 unsigned regno = DF_REF_REGNO (use); 4542 bitmap_set_bit (moveable, regno); 4543 bitmap_set_bit (&set, regno); 4544 bitmap_set_bit (&used, regno); 4545 bitmap_clear_bit (transp, regno); 4546 continue; 4547 } 4548 FOR_EACH_INSN_INFO_USE (use, insn_info) 4549 { 4550 unsigned regno = DF_REF_REGNO (use); 4551 bitmap_set_bit (&used, regno); 4552 if (bitmap_clear_bit (moveable, regno)) 4553 bitmap_clear_bit (transp, regno); 4554 } 4555 4556 FOR_EACH_INSN_INFO_DEF (def, insn_info) 4557 { 4558 unsigned regno = DF_REF_REGNO (def); 4559 bitmap_set_bit (&set, regno); 4560 bitmap_clear_bit (transp, regno); 4561 bitmap_clear_bit (moveable, regno); 4562 } 4563 } 4564 } 4565 4566 bitmap_clear (&live); 4567 bitmap_clear (&used); 4568 bitmap_clear (&set); 4569 4570 FOR_EACH_BB_FN (bb, cfun) 4571 { 4572 bitmap local = bb_local + bb->index; 4573 rtx_insn *insn; 4574 4575 FOR_BB_INSNS (bb, insn) 4576 if (NONDEBUG_INSN_P (insn)) 4577 { 4578 df_insn_info *insn_info = DF_INSN_INFO_GET (insn); 4579 rtx_insn *def_insn; 4580 rtx closest_use, note; 4581 df_ref def, use; 4582 unsigned regno; 4583 bool all_dominated, all_local; 4584 machine_mode mode; 4585 4586 def = df_single_def (insn_info); 4587 /* There must be exactly one def in this insn. */ 4588 if (!def || !single_set (insn)) 4589 continue; 4590 /* This must be the only definition of the reg. We also limit 4591 which modes we deal with so that we can assume we can generate 4592 move instructions. */ 4593 regno = DF_REF_REGNO (def); 4594 mode = GET_MODE (DF_REF_REG (def)); 4595 if (DF_REG_DEF_COUNT (regno) != 1 4596 || !DF_REF_INSN_INFO (def) 4597 || HARD_REGISTER_NUM_P (regno) 4598 || DF_REG_EQ_USE_COUNT (regno) > 0 4599 || (!INTEGRAL_MODE_P (mode) && !FLOAT_MODE_P (mode))) 4600 continue; 4601 def_insn = DF_REF_INSN (def); 4602 4603 for (note = REG_NOTES (def_insn); note; note = XEXP (note, 1)) 4604 if (REG_NOTE_KIND (note) == REG_EQUIV && MEM_P (XEXP (note, 0))) 4605 break; 4606 4607 if (note) 4608 { 4609 if (dump_file) 4610 fprintf (dump_file, "Ignoring reg %d, has equiv memory\n", 4611 regno); 4612 bitmap_set_bit (&unusable_as_input, regno); 4613 continue; 4614 } 4615 4616 use = DF_REG_USE_CHAIN (regno); 4617 all_dominated = true; 4618 all_local = true; 4619 closest_use = NULL_RTX; 4620 for (; use; use = DF_REF_NEXT_REG (use)) 4621 { 4622 rtx_insn *insn; 4623 if (!DF_REF_INSN_INFO (use)) 4624 { 4625 all_dominated = false; 4626 all_local = false; 4627 break; 4628 } 4629 insn = DF_REF_INSN (use); 4630 if (DEBUG_INSN_P (insn)) 4631 continue; 4632 if (BLOCK_FOR_INSN (insn) != BLOCK_FOR_INSN (def_insn)) 4633 all_local = false; 4634 if (!insn_dominated_by_p (insn, def_insn, uid_luid)) 4635 all_dominated = false; 4636 if (closest_use != insn && closest_use != const0_rtx) 4637 { 4638 if (closest_use == NULL_RTX) 4639 closest_use = insn; 4640 else if (insn_dominated_by_p (closest_use, insn, uid_luid)) 4641 closest_use = insn; 4642 else if (!insn_dominated_by_p (insn, closest_use, uid_luid)) 4643 closest_use = const0_rtx; 4644 } 4645 } 4646 if (!all_dominated) 4647 { 4648 if (dump_file) 4649 fprintf (dump_file, "Reg %d not all uses dominated by set\n", 4650 regno); 4651 continue; 4652 } 4653 if (all_local) 4654 bitmap_set_bit (local, regno); 4655 if (closest_use == const0_rtx || closest_use == NULL 4656 || next_nonnote_nondebug_insn (def_insn) == closest_use) 4657 { 4658 if (dump_file) 4659 fprintf (dump_file, "Reg %d uninteresting%s\n", regno, 4660 closest_use == const0_rtx || closest_use == NULL 4661 ? " (no unique first use)" : ""); 4662 continue; 4663 } 4664 if (HAVE_cc0 && reg_referenced_p (cc0_rtx, PATTERN (closest_use))) 4665 { 4666 if (dump_file) 4667 fprintf (dump_file, "Reg %d: closest user uses cc0\n", 4668 regno); 4669 continue; 4670 } 4671 4672 bitmap_set_bit (&interesting, regno); 4673 /* If we get here, we know closest_use is a non-NULL insn 4674 (as opposed to const_0_rtx). */ 4675 closest_uses[regno] = as_a <rtx_insn *> (closest_use); 4676 4677 if (dump_file && (all_local || all_dominated)) 4678 { 4679 fprintf (dump_file, "Reg %u:", regno); 4680 if (all_local) 4681 fprintf (dump_file, " local to bb %d", bb->index); 4682 if (all_dominated) 4683 fprintf (dump_file, " def dominates all uses"); 4684 if (closest_use != const0_rtx) 4685 fprintf (dump_file, " has unique first use"); 4686 fputs ("\n", dump_file); 4687 } 4688 } 4689 } 4690 4691 EXECUTE_IF_SET_IN_BITMAP (&interesting, 0, i, bi) 4692 { 4693 df_ref def = DF_REG_DEF_CHAIN (i); 4694 rtx_insn *def_insn = DF_REF_INSN (def); 4695 basic_block def_block = BLOCK_FOR_INSN (def_insn); 4696 bitmap def_bb_local = bb_local + def_block->index; 4697 bitmap def_bb_moveable = bb_moveable_reg_sets + def_block->index; 4698 bitmap def_bb_transp = bb_transp_live + def_block->index; 4699 bool local_to_bb_p = bitmap_bit_p (def_bb_local, i); 4700 rtx_insn *use_insn = closest_uses[i]; 4701 df_ref use; 4702 bool all_ok = true; 4703 bool all_transp = true; 4704 4705 if (!REG_P (DF_REF_REG (def))) 4706 continue; 4707 4708 if (!local_to_bb_p) 4709 { 4710 if (dump_file) 4711 fprintf (dump_file, "Reg %u not local to one basic block\n", 4712 i); 4713 continue; 4714 } 4715 if (reg_equiv_init (i) != NULL_RTX) 4716 { 4717 if (dump_file) 4718 fprintf (dump_file, "Ignoring reg %u with equiv init insn\n", 4719 i); 4720 continue; 4721 } 4722 if (!rtx_moveable_p (&PATTERN (def_insn), OP_IN)) 4723 { 4724 if (dump_file) 4725 fprintf (dump_file, "Found def insn %d for %d to be not moveable\n", 4726 INSN_UID (def_insn), i); 4727 continue; 4728 } 4729 if (dump_file) 4730 fprintf (dump_file, "Examining insn %d, def for %d\n", 4731 INSN_UID (def_insn), i); 4732 FOR_EACH_INSN_USE (use, def_insn) 4733 { 4734 unsigned regno = DF_REF_REGNO (use); 4735 if (bitmap_bit_p (&unusable_as_input, regno)) 4736 { 4737 all_ok = false; 4738 if (dump_file) 4739 fprintf (dump_file, " found unusable input reg %u.\n", regno); 4740 break; 4741 } 4742 if (!bitmap_bit_p (def_bb_transp, regno)) 4743 { 4744 if (bitmap_bit_p (def_bb_moveable, regno) 4745 && !control_flow_insn_p (use_insn) 4746 && (!HAVE_cc0 || !sets_cc0_p (use_insn))) 4747 { 4748 if (modified_between_p (DF_REF_REG (use), def_insn, use_insn)) 4749 { 4750 rtx_insn *x = NEXT_INSN (def_insn); 4751 while (!modified_in_p (DF_REF_REG (use), x)) 4752 { 4753 gcc_assert (x != use_insn); 4754 x = NEXT_INSN (x); 4755 } 4756 if (dump_file) 4757 fprintf (dump_file, " input reg %u modified but insn %d moveable\n", 4758 regno, INSN_UID (x)); 4759 emit_insn_after (PATTERN (x), use_insn); 4760 set_insn_deleted (x); 4761 } 4762 else 4763 { 4764 if (dump_file) 4765 fprintf (dump_file, " input reg %u modified between def and use\n", 4766 regno); 4767 all_transp = false; 4768 } 4769 } 4770 else 4771 all_transp = false; 4772 } 4773 } 4774 if (!all_ok) 4775 continue; 4776 if (!dbg_cnt (ira_move)) 4777 break; 4778 if (dump_file) 4779 fprintf (dump_file, " all ok%s\n", all_transp ? " and transp" : ""); 4780 4781 if (all_transp) 4782 { 4783 rtx def_reg = DF_REF_REG (def); 4784 rtx newreg = ira_create_new_reg (def_reg); 4785 if (validate_change (def_insn, DF_REF_REAL_LOC (def), newreg, 0)) 4786 { 4787 unsigned nregno = REGNO (newreg); 4788 emit_insn_before (gen_move_insn (def_reg, newreg), use_insn); 4789 nregno -= max_regs; 4790 pseudo_replaced_reg[nregno] = def_reg; 4791 } 4792 } 4793 } 4794 4795 FOR_EACH_BB_FN (bb, cfun) 4796 { 4797 bitmap_clear (bb_local + bb->index); 4798 bitmap_clear (bb_transp_live + bb->index); 4799 bitmap_clear (bb_moveable_reg_sets + bb->index); 4800 } 4801 bitmap_clear (&interesting); 4802 bitmap_clear (&unusable_as_input); 4803 free (uid_luid); 4804 free (closest_uses); 4805 free (bb_local); 4806 free (bb_transp_live); 4807 free (bb_moveable_reg_sets); 4808 4809 last_moveable_pseudo = max_reg_num (); 4810 4811 fix_reg_equiv_init (); 4812 expand_reg_info (); 4813 regstat_free_n_sets_and_refs (); 4814 regstat_free_ri (); 4815 regstat_init_n_sets_and_refs (); 4816 regstat_compute_ri (); 4817 free_dominance_info (CDI_DOMINATORS); 4818 } 4819 4820 /* If SET pattern SET is an assignment from a hard register to a pseudo which 4821 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), return 4822 the destination. Otherwise return NULL. */ 4823 4824 static rtx 4825 interesting_dest_for_shprep_1 (rtx set, basic_block call_dom) 4826 { 4827 rtx src = SET_SRC (set); 4828 rtx dest = SET_DEST (set); 4829 if (!REG_P (src) || !HARD_REGISTER_P (src) 4830 || !REG_P (dest) || HARD_REGISTER_P (dest) 4831 || (call_dom && !bitmap_bit_p (df_get_live_in (call_dom), REGNO (dest)))) 4832 return NULL; 4833 return dest; 4834 } 4835 4836 /* If insn is interesting for parameter range-splitting shrink-wrapping 4837 preparation, i.e. it is a single set from a hard register to a pseudo, which 4838 is live at CALL_DOM (if non-NULL, otherwise this check is omitted), or a 4839 parallel statement with only one such statement, return the destination. 4840 Otherwise return NULL. */ 4841 4842 static rtx 4843 interesting_dest_for_shprep (rtx_insn *insn, basic_block call_dom) 4844 { 4845 if (!INSN_P (insn)) 4846 return NULL; 4847 rtx pat = PATTERN (insn); 4848 if (GET_CODE (pat) == SET) 4849 return interesting_dest_for_shprep_1 (pat, call_dom); 4850 4851 if (GET_CODE (pat) != PARALLEL) 4852 return NULL; 4853 rtx ret = NULL; 4854 for (int i = 0; i < XVECLEN (pat, 0); i++) 4855 { 4856 rtx sub = XVECEXP (pat, 0, i); 4857 if (GET_CODE (sub) == USE || GET_CODE (sub) == CLOBBER) 4858 continue; 4859 if (GET_CODE (sub) != SET 4860 || side_effects_p (sub)) 4861 return NULL; 4862 rtx dest = interesting_dest_for_shprep_1 (sub, call_dom); 4863 if (dest && ret) 4864 return NULL; 4865 if (dest) 4866 ret = dest; 4867 } 4868 return ret; 4869 } 4870 4871 /* Split live ranges of pseudos that are loaded from hard registers in the 4872 first BB in a BB that dominates all non-sibling call if such a BB can be 4873 found and is not in a loop. Return true if the function has made any 4874 changes. */ 4875 4876 static bool 4877 split_live_ranges_for_shrink_wrap (void) 4878 { 4879 basic_block bb, call_dom = NULL; 4880 basic_block first = single_succ (ENTRY_BLOCK_PTR_FOR_FN (cfun)); 4881 rtx_insn *insn, *last_interesting_insn = NULL; 4882 bitmap_head need_new, reachable; 4883 vec<basic_block> queue; 4884 4885 if (!SHRINK_WRAPPING_ENABLED) 4886 return false; 4887 4888 bitmap_initialize (&need_new, 0); 4889 bitmap_initialize (&reachable, 0); 4890 queue.create (n_basic_blocks_for_fn (cfun)); 4891 4892 FOR_EACH_BB_FN (bb, cfun) 4893 FOR_BB_INSNS (bb, insn) 4894 if (CALL_P (insn) && !SIBLING_CALL_P (insn)) 4895 { 4896 if (bb == first) 4897 { 4898 bitmap_clear (&need_new); 4899 bitmap_clear (&reachable); 4900 queue.release (); 4901 return false; 4902 } 4903 4904 bitmap_set_bit (&need_new, bb->index); 4905 bitmap_set_bit (&reachable, bb->index); 4906 queue.quick_push (bb); 4907 break; 4908 } 4909 4910 if (queue.is_empty ()) 4911 { 4912 bitmap_clear (&need_new); 4913 bitmap_clear (&reachable); 4914 queue.release (); 4915 return false; 4916 } 4917 4918 while (!queue.is_empty ()) 4919 { 4920 edge e; 4921 edge_iterator ei; 4922 4923 bb = queue.pop (); 4924 FOR_EACH_EDGE (e, ei, bb->succs) 4925 if (e->dest != EXIT_BLOCK_PTR_FOR_FN (cfun) 4926 && bitmap_set_bit (&reachable, e->dest->index)) 4927 queue.quick_push (e->dest); 4928 } 4929 queue.release (); 4930 4931 FOR_BB_INSNS (first, insn) 4932 { 4933 rtx dest = interesting_dest_for_shprep (insn, NULL); 4934 if (!dest) 4935 continue; 4936 4937 if (DF_REG_DEF_COUNT (REGNO (dest)) > 1) 4938 { 4939 bitmap_clear (&need_new); 4940 bitmap_clear (&reachable); 4941 return false; 4942 } 4943 4944 for (df_ref use = DF_REG_USE_CHAIN (REGNO(dest)); 4945 use; 4946 use = DF_REF_NEXT_REG (use)) 4947 { 4948 int ubbi = DF_REF_BB (use)->index; 4949 if (bitmap_bit_p (&reachable, ubbi)) 4950 bitmap_set_bit (&need_new, ubbi); 4951 } 4952 last_interesting_insn = insn; 4953 } 4954 4955 bitmap_clear (&reachable); 4956 if (!last_interesting_insn) 4957 { 4958 bitmap_clear (&need_new); 4959 return false; 4960 } 4961 4962 call_dom = nearest_common_dominator_for_set (CDI_DOMINATORS, &need_new); 4963 bitmap_clear (&need_new); 4964 if (call_dom == first) 4965 return false; 4966 4967 loop_optimizer_init (AVOID_CFG_MODIFICATIONS); 4968 while (bb_loop_depth (call_dom) > 0) 4969 call_dom = get_immediate_dominator (CDI_DOMINATORS, call_dom); 4970 loop_optimizer_finalize (); 4971 4972 if (call_dom == first) 4973 return false; 4974 4975 calculate_dominance_info (CDI_POST_DOMINATORS); 4976 if (dominated_by_p (CDI_POST_DOMINATORS, first, call_dom)) 4977 { 4978 free_dominance_info (CDI_POST_DOMINATORS); 4979 return false; 4980 } 4981 free_dominance_info (CDI_POST_DOMINATORS); 4982 4983 if (dump_file) 4984 fprintf (dump_file, "Will split live ranges of parameters at BB %i\n", 4985 call_dom->index); 4986 4987 bool ret = false; 4988 FOR_BB_INSNS (first, insn) 4989 { 4990 rtx dest = interesting_dest_for_shprep (insn, call_dom); 4991 if (!dest || dest == pic_offset_table_rtx) 4992 continue; 4993 4994 bool need_newreg = false; 4995 df_ref use, next; 4996 for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next) 4997 { 4998 rtx_insn *uin = DF_REF_INSN (use); 4999 next = DF_REF_NEXT_REG (use); 5000 5001 if (DEBUG_INSN_P (uin)) 5002 continue; 5003 5004 basic_block ubb = BLOCK_FOR_INSN (uin); 5005 if (ubb == call_dom 5006 || dominated_by_p (CDI_DOMINATORS, ubb, call_dom)) 5007 { 5008 need_newreg = true; 5009 break; 5010 } 5011 } 5012 5013 if (need_newreg) 5014 { 5015 rtx newreg = ira_create_new_reg (dest); 5016 5017 for (use = DF_REG_USE_CHAIN (REGNO (dest)); use; use = next) 5018 { 5019 rtx_insn *uin = DF_REF_INSN (use); 5020 next = DF_REF_NEXT_REG (use); 5021 5022 basic_block ubb = BLOCK_FOR_INSN (uin); 5023 if (ubb == call_dom 5024 || dominated_by_p (CDI_DOMINATORS, ubb, call_dom)) 5025 validate_change (uin, DF_REF_REAL_LOC (use), newreg, true); 5026 } 5027 5028 rtx_insn *new_move = gen_move_insn (newreg, dest); 5029 emit_insn_after (new_move, bb_note (call_dom)); 5030 if (dump_file) 5031 { 5032 fprintf (dump_file, "Split live-range of register "); 5033 print_rtl_single (dump_file, dest); 5034 } 5035 ret = true; 5036 } 5037 5038 if (insn == last_interesting_insn) 5039 break; 5040 } 5041 apply_change_group (); 5042 return ret; 5043 } 5044 5045 /* Perform the second half of the transformation started in 5046 find_moveable_pseudos. We look for instances where the newly introduced 5047 pseudo remains unallocated, and remove it by moving the definition to 5048 just before its use, replacing the move instruction generated by 5049 find_moveable_pseudos. */ 5050 static void 5051 move_unallocated_pseudos (void) 5052 { 5053 int i; 5054 for (i = first_moveable_pseudo; i < last_moveable_pseudo; i++) 5055 if (reg_renumber[i] < 0) 5056 { 5057 int idx = i - first_moveable_pseudo; 5058 rtx other_reg = pseudo_replaced_reg[idx]; 5059 rtx_insn *def_insn = DF_REF_INSN (DF_REG_DEF_CHAIN (i)); 5060 /* The use must follow all definitions of OTHER_REG, so we can 5061 insert the new definition immediately after any of them. */ 5062 df_ref other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)); 5063 rtx_insn *move_insn = DF_REF_INSN (other_def); 5064 rtx_insn *newinsn = emit_insn_after (PATTERN (def_insn), move_insn); 5065 rtx set; 5066 int success; 5067 5068 if (dump_file) 5069 fprintf (dump_file, "moving def of %d (insn %d now) ", 5070 REGNO (other_reg), INSN_UID (def_insn)); 5071 5072 delete_insn (move_insn); 5073 while ((other_def = DF_REG_DEF_CHAIN (REGNO (other_reg)))) 5074 delete_insn (DF_REF_INSN (other_def)); 5075 delete_insn (def_insn); 5076 5077 set = single_set (newinsn); 5078 success = validate_change (newinsn, &SET_DEST (set), other_reg, 0); 5079 gcc_assert (success); 5080 if (dump_file) 5081 fprintf (dump_file, " %d) rather than keep unallocated replacement %d\n", 5082 INSN_UID (newinsn), i); 5083 SET_REG_N_REFS (i, 0); 5084 } 5085 } 5086 5087 /* If the backend knows where to allocate pseudos for hard 5088 register initial values, register these allocations now. */ 5089 static void 5090 allocate_initial_values (void) 5091 { 5092 if (targetm.allocate_initial_value) 5093 { 5094 rtx hreg, preg, x; 5095 int i, regno; 5096 5097 for (i = 0; HARD_REGISTER_NUM_P (i); i++) 5098 { 5099 if (! initial_value_entry (i, &hreg, &preg)) 5100 break; 5101 5102 x = targetm.allocate_initial_value (hreg); 5103 regno = REGNO (preg); 5104 if (x && REG_N_SETS (regno) <= 1) 5105 { 5106 if (MEM_P (x)) 5107 reg_equiv_memory_loc (regno) = x; 5108 else 5109 { 5110 basic_block bb; 5111 int new_regno; 5112 5113 gcc_assert (REG_P (x)); 5114 new_regno = REGNO (x); 5115 reg_renumber[regno] = new_regno; 5116 /* Poke the regno right into regno_reg_rtx so that even 5117 fixed regs are accepted. */ 5118 SET_REGNO (preg, new_regno); 5119 /* Update global register liveness information. */ 5120 FOR_EACH_BB_FN (bb, cfun) 5121 { 5122 if (REGNO_REG_SET_P (df_get_live_in (bb), regno)) 5123 SET_REGNO_REG_SET (df_get_live_in (bb), new_regno); 5124 if (REGNO_REG_SET_P (df_get_live_out (bb), regno)) 5125 SET_REGNO_REG_SET (df_get_live_out (bb), new_regno); 5126 } 5127 } 5128 } 5129 } 5130 5131 gcc_checking_assert (! initial_value_entry (FIRST_PSEUDO_REGISTER, 5132 &hreg, &preg)); 5133 } 5134 } 5135 5136 5137 /* True when we use LRA instead of reload pass for the current 5138 function. */ 5139 bool ira_use_lra_p; 5140 5141 /* True if we have allocno conflicts. It is false for non-optimized 5142 mode or when the conflict table is too big. */ 5143 bool ira_conflicts_p; 5144 5145 /* Saved between IRA and reload. */ 5146 static int saved_flag_ira_share_spill_slots; 5147 5148 /* This is the main entry of IRA. */ 5149 static void 5150 ira (FILE *f) 5151 { 5152 bool loops_p; 5153 int ira_max_point_before_emit; 5154 bool saved_flag_caller_saves = flag_caller_saves; 5155 enum ira_region saved_flag_ira_region = flag_ira_region; 5156 5157 /* Perform target specific PIC register initialization. */ 5158 targetm.init_pic_reg (); 5159 5160 ira_conflicts_p = optimize > 0; 5161 5162 ira_use_lra_p = targetm.lra_p (); 5163 /* If there are too many pseudos and/or basic blocks (e.g. 10K 5164 pseudos and 10K blocks or 100K pseudos and 1K blocks), we will 5165 use simplified and faster algorithms in LRA. */ 5166 lra_simple_p 5167 = (ira_use_lra_p 5168 && max_reg_num () >= (1 << 26) / last_basic_block_for_fn (cfun)); 5169 if (lra_simple_p) 5170 { 5171 /* It permits to skip live range splitting in LRA. */ 5172 flag_caller_saves = false; 5173 /* There is no sense to do regional allocation when we use 5174 simplified LRA. */ 5175 flag_ira_region = IRA_REGION_ONE; 5176 ira_conflicts_p = false; 5177 } 5178 5179 #ifndef IRA_NO_OBSTACK 5180 gcc_obstack_init (&ira_obstack); 5181 #endif 5182 bitmap_obstack_initialize (&ira_bitmap_obstack); 5183 5184 /* LRA uses its own infrastructure to handle caller save registers. */ 5185 if (flag_caller_saves && !ira_use_lra_p) 5186 init_caller_save (); 5187 5188 if (flag_ira_verbose < 10) 5189 { 5190 internal_flag_ira_verbose = flag_ira_verbose; 5191 ira_dump_file = f; 5192 } 5193 else 5194 { 5195 internal_flag_ira_verbose = flag_ira_verbose - 10; 5196 ira_dump_file = stderr; 5197 } 5198 5199 setup_prohibited_mode_move_regs (); 5200 decrease_live_ranges_number (); 5201 df_note_add_problem (); 5202 5203 /* DF_LIVE can't be used in the register allocator, too many other 5204 parts of the compiler depend on using the "classic" liveness 5205 interpretation of the DF_LR problem. See PR38711. 5206 Remove the problem, so that we don't spend time updating it in 5207 any of the df_analyze() calls during IRA/LRA. */ 5208 if (optimize > 1) 5209 df_remove_problem (df_live); 5210 gcc_checking_assert (df_live == NULL); 5211 5212 if (flag_checking) 5213 df->changeable_flags |= DF_VERIFY_SCHEDULED; 5214 5215 df_analyze (); 5216 5217 init_reg_equiv (); 5218 if (ira_conflicts_p) 5219 { 5220 calculate_dominance_info (CDI_DOMINATORS); 5221 5222 if (split_live_ranges_for_shrink_wrap ()) 5223 df_analyze (); 5224 5225 free_dominance_info (CDI_DOMINATORS); 5226 } 5227 5228 df_clear_flags (DF_NO_INSN_RESCAN); 5229 5230 indirect_jump_optimize (); 5231 if (delete_trivially_dead_insns (get_insns (), max_reg_num ())) 5232 df_analyze (); 5233 5234 regstat_init_n_sets_and_refs (); 5235 regstat_compute_ri (); 5236 5237 /* If we are not optimizing, then this is the only place before 5238 register allocation where dataflow is done. And that is needed 5239 to generate these warnings. */ 5240 if (warn_clobbered) 5241 generate_setjmp_warnings (); 5242 5243 /* Determine if the current function is a leaf before running IRA 5244 since this can impact optimizations done by the prologue and 5245 epilogue thus changing register elimination offsets. */ 5246 crtl->is_leaf = leaf_function_p (); 5247 5248 if (resize_reg_info () && flag_ira_loop_pressure) 5249 ira_set_pseudo_classes (true, ira_dump_file); 5250 5251 update_equiv_regs (); 5252 setup_reg_equiv (); 5253 setup_reg_equiv_init (); 5254 5255 allocated_reg_info_size = max_reg_num (); 5256 5257 /* It is not worth to do such improvement when we use a simple 5258 allocation because of -O0 usage or because the function is too 5259 big. */ 5260 if (ira_conflicts_p) 5261 find_moveable_pseudos (); 5262 5263 max_regno_before_ira = max_reg_num (); 5264 ira_setup_eliminable_regset (); 5265 5266 ira_overall_cost = ira_reg_cost = ira_mem_cost = 0; 5267 ira_load_cost = ira_store_cost = ira_shuffle_cost = 0; 5268 ira_move_loops_num = ira_additional_jumps_num = 0; 5269 5270 ira_assert (current_loops == NULL); 5271 if (flag_ira_region == IRA_REGION_ALL || flag_ira_region == IRA_REGION_MIXED) 5272 loop_optimizer_init (AVOID_CFG_MODIFICATIONS | LOOPS_HAVE_RECORDED_EXITS); 5273 5274 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) 5275 fprintf (ira_dump_file, "Building IRA IR\n"); 5276 loops_p = ira_build (); 5277 5278 ira_assert (ira_conflicts_p || !loops_p); 5279 5280 saved_flag_ira_share_spill_slots = flag_ira_share_spill_slots; 5281 if (too_high_register_pressure_p () || cfun->calls_setjmp) 5282 /* It is just wasting compiler's time to pack spilled pseudos into 5283 stack slots in this case -- prohibit it. We also do this if 5284 there is setjmp call because a variable not modified between 5285 setjmp and longjmp the compiler is required to preserve its 5286 value and sharing slots does not guarantee it. */ 5287 flag_ira_share_spill_slots = FALSE; 5288 5289 ira_color (); 5290 5291 ira_max_point_before_emit = ira_max_point; 5292 5293 ira_initiate_emit_data (); 5294 5295 ira_emit (loops_p); 5296 5297 max_regno = max_reg_num (); 5298 if (ira_conflicts_p) 5299 { 5300 if (! loops_p) 5301 { 5302 if (! ira_use_lra_p) 5303 ira_initiate_assign (); 5304 } 5305 else 5306 { 5307 expand_reg_info (); 5308 5309 if (ira_use_lra_p) 5310 { 5311 ira_allocno_t a; 5312 ira_allocno_iterator ai; 5313 5314 FOR_EACH_ALLOCNO (a, ai) 5315 { 5316 int old_regno = ALLOCNO_REGNO (a); 5317 int new_regno = REGNO (ALLOCNO_EMIT_DATA (a)->reg); 5318 5319 ALLOCNO_REGNO (a) = new_regno; 5320 5321 if (old_regno != new_regno) 5322 setup_reg_classes (new_regno, reg_preferred_class (old_regno), 5323 reg_alternate_class (old_regno), 5324 reg_allocno_class (old_regno)); 5325 } 5326 5327 } 5328 else 5329 { 5330 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL) 5331 fprintf (ira_dump_file, "Flattening IR\n"); 5332 ira_flattening (max_regno_before_ira, ira_max_point_before_emit); 5333 } 5334 /* New insns were generated: add notes and recalculate live 5335 info. */ 5336 df_analyze (); 5337 5338 /* ??? Rebuild the loop tree, but why? Does the loop tree 5339 change if new insns were generated? Can that be handled 5340 by updating the loop tree incrementally? */ 5341 loop_optimizer_finalize (); 5342 free_dominance_info (CDI_DOMINATORS); 5343 loop_optimizer_init (AVOID_CFG_MODIFICATIONS 5344 | LOOPS_HAVE_RECORDED_EXITS); 5345 5346 if (! ira_use_lra_p) 5347 { 5348 setup_allocno_assignment_flags (); 5349 ira_initiate_assign (); 5350 ira_reassign_conflict_allocnos (max_regno); 5351 } 5352 } 5353 } 5354 5355 ira_finish_emit_data (); 5356 5357 setup_reg_renumber (); 5358 5359 calculate_allocation_cost (); 5360 5361 #ifdef ENABLE_IRA_CHECKING 5362 if (ira_conflicts_p) 5363 check_allocation (); 5364 #endif 5365 5366 if (max_regno != max_regno_before_ira) 5367 { 5368 regstat_free_n_sets_and_refs (); 5369 regstat_free_ri (); 5370 regstat_init_n_sets_and_refs (); 5371 regstat_compute_ri (); 5372 } 5373 5374 overall_cost_before = ira_overall_cost; 5375 if (! ira_conflicts_p) 5376 grow_reg_equivs (); 5377 else 5378 { 5379 fix_reg_equiv_init (); 5380 5381 #ifdef ENABLE_IRA_CHECKING 5382 print_redundant_copies (); 5383 #endif 5384 if (! ira_use_lra_p) 5385 { 5386 ira_spilled_reg_stack_slots_num = 0; 5387 ira_spilled_reg_stack_slots 5388 = ((struct ira_spilled_reg_stack_slot *) 5389 ira_allocate (max_regno 5390 * sizeof (struct ira_spilled_reg_stack_slot))); 5391 memset (ira_spilled_reg_stack_slots, 0, 5392 max_regno * sizeof (struct ira_spilled_reg_stack_slot)); 5393 } 5394 } 5395 allocate_initial_values (); 5396 5397 /* See comment for find_moveable_pseudos call. */ 5398 if (ira_conflicts_p) 5399 move_unallocated_pseudos (); 5400 5401 /* Restore original values. */ 5402 if (lra_simple_p) 5403 { 5404 flag_caller_saves = saved_flag_caller_saves; 5405 flag_ira_region = saved_flag_ira_region; 5406 } 5407 } 5408 5409 static void 5410 do_reload (void) 5411 { 5412 basic_block bb; 5413 bool need_dce; 5414 unsigned pic_offset_table_regno = INVALID_REGNUM; 5415 5416 if (flag_ira_verbose < 10) 5417 ira_dump_file = dump_file; 5418 5419 /* If pic_offset_table_rtx is a pseudo register, then keep it so 5420 after reload to avoid possible wrong usages of hard reg assigned 5421 to it. */ 5422 if (pic_offset_table_rtx 5423 && REGNO (pic_offset_table_rtx) >= FIRST_PSEUDO_REGISTER) 5424 pic_offset_table_regno = REGNO (pic_offset_table_rtx); 5425 5426 timevar_push (TV_RELOAD); 5427 if (ira_use_lra_p) 5428 { 5429 if (current_loops != NULL) 5430 { 5431 loop_optimizer_finalize (); 5432 free_dominance_info (CDI_DOMINATORS); 5433 } 5434 FOR_ALL_BB_FN (bb, cfun) 5435 bb->loop_father = NULL; 5436 current_loops = NULL; 5437 5438 ira_destroy (); 5439 5440 lra (ira_dump_file); 5441 /* ???!!! Move it before lra () when we use ira_reg_equiv in 5442 LRA. */ 5443 vec_free (reg_equivs); 5444 reg_equivs = NULL; 5445 need_dce = false; 5446 } 5447 else 5448 { 5449 df_set_flags (DF_NO_INSN_RESCAN); 5450 build_insn_chain (); 5451 5452 need_dce = reload (get_insns (), ira_conflicts_p); 5453 } 5454 5455 timevar_pop (TV_RELOAD); 5456 5457 timevar_push (TV_IRA); 5458 5459 if (ira_conflicts_p && ! ira_use_lra_p) 5460 { 5461 ira_free (ira_spilled_reg_stack_slots); 5462 ira_finish_assign (); 5463 } 5464 5465 if (internal_flag_ira_verbose > 0 && ira_dump_file != NULL 5466 && overall_cost_before != ira_overall_cost) 5467 fprintf (ira_dump_file, "+++Overall after reload %" PRId64 "\n", 5468 ira_overall_cost); 5469 5470 flag_ira_share_spill_slots = saved_flag_ira_share_spill_slots; 5471 5472 if (! ira_use_lra_p) 5473 { 5474 ira_destroy (); 5475 if (current_loops != NULL) 5476 { 5477 loop_optimizer_finalize (); 5478 free_dominance_info (CDI_DOMINATORS); 5479 } 5480 FOR_ALL_BB_FN (bb, cfun) 5481 bb->loop_father = NULL; 5482 current_loops = NULL; 5483 5484 regstat_free_ri (); 5485 regstat_free_n_sets_and_refs (); 5486 } 5487 5488 if (optimize) 5489 cleanup_cfg (CLEANUP_EXPENSIVE); 5490 5491 finish_reg_equiv (); 5492 5493 bitmap_obstack_release (&ira_bitmap_obstack); 5494 #ifndef IRA_NO_OBSTACK 5495 obstack_free (&ira_obstack, NULL); 5496 #endif 5497 5498 /* The code after the reload has changed so much that at this point 5499 we might as well just rescan everything. Note that 5500 df_rescan_all_insns is not going to help here because it does not 5501 touch the artificial uses and defs. */ 5502 df_finish_pass (true); 5503 df_scan_alloc (NULL); 5504 df_scan_blocks (); 5505 5506 if (optimize > 1) 5507 { 5508 df_live_add_problem (); 5509 df_live_set_all_dirty (); 5510 } 5511 5512 if (optimize) 5513 df_analyze (); 5514 5515 if (need_dce && optimize) 5516 run_fast_dce (); 5517 5518 /* Diagnose uses of the hard frame pointer when it is used as a global 5519 register. Often we can get away with letting the user appropriate 5520 the frame pointer, but we should let them know when code generation 5521 makes that impossible. */ 5522 if (global_regs[HARD_FRAME_POINTER_REGNUM] && frame_pointer_needed) 5523 { 5524 tree decl = global_regs_decl[HARD_FRAME_POINTER_REGNUM]; 5525 error_at (DECL_SOURCE_LOCATION (current_function_decl), 5526 "frame pointer required, but reserved"); 5527 inform (DECL_SOURCE_LOCATION (decl), "for %qD", decl); 5528 } 5529 5530 /* If we are doing generic stack checking, give a warning if this 5531 function's frame size is larger than we expect. */ 5532 if (flag_stack_check == GENERIC_STACK_CHECK) 5533 { 5534 HOST_WIDE_INT size = get_frame_size () + STACK_CHECK_FIXED_FRAME_SIZE; 5535 5536 for (int i = 0; i < FIRST_PSEUDO_REGISTER; i++) 5537 if (df_regs_ever_live_p (i) && !fixed_regs[i] && call_used_regs[i]) 5538 size += UNITS_PER_WORD; 5539 5540 if (size > STACK_CHECK_MAX_FRAME_SIZE) 5541 warning (0, "frame size too large for reliable stack checking"); 5542 } 5543 5544 if (pic_offset_table_regno != INVALID_REGNUM) 5545 pic_offset_table_rtx = gen_rtx_REG (Pmode, pic_offset_table_regno); 5546 5547 timevar_pop (TV_IRA); 5548 } 5549 5550 /* Run the integrated register allocator. */ 5551 5552 namespace { 5553 5554 const pass_data pass_data_ira = 5555 { 5556 RTL_PASS, /* type */ 5557 "ira", /* name */ 5558 OPTGROUP_NONE, /* optinfo_flags */ 5559 TV_IRA, /* tv_id */ 5560 0, /* properties_required */ 5561 0, /* properties_provided */ 5562 0, /* properties_destroyed */ 5563 0, /* todo_flags_start */ 5564 TODO_do_not_ggc_collect, /* todo_flags_finish */ 5565 }; 5566 5567 class pass_ira : public rtl_opt_pass 5568 { 5569 public: 5570 pass_ira (gcc::context *ctxt) 5571 : rtl_opt_pass (pass_data_ira, ctxt) 5572 {} 5573 5574 /* opt_pass methods: */ 5575 virtual bool gate (function *) 5576 { 5577 return !targetm.no_register_allocation; 5578 } 5579 virtual unsigned int execute (function *) 5580 { 5581 ira (dump_file); 5582 return 0; 5583 } 5584 5585 }; // class pass_ira 5586 5587 } // anon namespace 5588 5589 rtl_opt_pass * 5590 make_pass_ira (gcc::context *ctxt) 5591 { 5592 return new pass_ira (ctxt); 5593 } 5594 5595 namespace { 5596 5597 const pass_data pass_data_reload = 5598 { 5599 RTL_PASS, /* type */ 5600 "reload", /* name */ 5601 OPTGROUP_NONE, /* optinfo_flags */ 5602 TV_RELOAD, /* tv_id */ 5603 0, /* properties_required */ 5604 0, /* properties_provided */ 5605 0, /* properties_destroyed */ 5606 0, /* todo_flags_start */ 5607 0, /* todo_flags_finish */ 5608 }; 5609 5610 class pass_reload : public rtl_opt_pass 5611 { 5612 public: 5613 pass_reload (gcc::context *ctxt) 5614 : rtl_opt_pass (pass_data_reload, ctxt) 5615 {} 5616 5617 /* opt_pass methods: */ 5618 virtual bool gate (function *) 5619 { 5620 return !targetm.no_register_allocation; 5621 } 5622 virtual unsigned int execute (function *) 5623 { 5624 do_reload (); 5625 return 0; 5626 } 5627 5628 }; // class pass_reload 5629 5630 } // anon namespace 5631 5632 rtl_opt_pass * 5633 make_pass_reload (gcc::context *ctxt) 5634 { 5635 return new pass_reload (ctxt); 5636 } 5637