1 /* Dwarf2 Call Frame Information helper routines. 2 Copyright (C) 1992-2019 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it under 7 the terms of the GNU General Public License as published by the Free 8 Software Foundation; either version 3, or (at your option) any later 9 version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 12 WARRANTY; without even the implied warranty of MERCHANTABILITY or 13 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 14 for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "target.h" 24 #include "function.h" 25 #include "rtl.h" 26 #include "tree.h" 27 #include "tree-pass.h" 28 #include "memmodel.h" 29 #include "tm_p.h" 30 #include "emit-rtl.h" 31 #include "stor-layout.h" 32 #include "cfgbuild.h" 33 #include "dwarf2out.h" 34 #include "dwarf2asm.h" 35 #include "common/common-target.h" 36 37 #include "except.h" /* expand_builtin_dwarf_sp_column */ 38 #include "profile-count.h" /* For expr.h */ 39 #include "expr.h" /* init_return_column_size */ 40 #include "output.h" /* asm_out_file */ 41 #include "debug.h" /* dwarf2out_do_frame, dwarf2out_do_cfi_asm */ 42 43 44 /* ??? Poison these here until it can be done generically. They've been 45 totally replaced in this file; make sure it stays that way. */ 46 #undef DWARF2_UNWIND_INFO 47 #undef DWARF2_FRAME_INFO 48 #if (GCC_VERSION >= 3000) 49 #pragma GCC poison DWARF2_UNWIND_INFO DWARF2_FRAME_INFO 50 #endif 51 52 #ifndef INCOMING_RETURN_ADDR_RTX 53 #define INCOMING_RETURN_ADDR_RTX (gcc_unreachable (), NULL_RTX) 54 #endif 55 56 #ifndef DEFAULT_INCOMING_FRAME_SP_OFFSET 57 #define DEFAULT_INCOMING_FRAME_SP_OFFSET INCOMING_FRAME_SP_OFFSET 58 #endif 59 60 /* A collected description of an entire row of the abstract CFI table. */ 61 struct GTY(()) dw_cfi_row 62 { 63 /* The expression that computes the CFA, expressed in two different ways. 64 The CFA member for the simple cases, and the full CFI expression for 65 the complex cases. The later will be a DW_CFA_cfa_expression. */ 66 dw_cfa_location cfa; 67 dw_cfi_ref cfa_cfi; 68 69 /* The expressions for any register column that is saved. */ 70 cfi_vec reg_save; 71 72 /* True if the register window is saved. */ 73 bool window_save; 74 }; 75 76 /* The caller's ORIG_REG is saved in SAVED_IN_REG. */ 77 struct GTY(()) reg_saved_in_data { 78 rtx orig_reg; 79 rtx saved_in_reg; 80 }; 81 82 83 /* Since we no longer have a proper CFG, we're going to create a facsimile 84 of one on the fly while processing the frame-related insns. 85 86 We create dw_trace_info structures for each extended basic block beginning 87 and ending at a "save point". Save points are labels, barriers, certain 88 notes, and of course the beginning and end of the function. 89 90 As we encounter control transfer insns, we propagate the "current" 91 row state across the edges to the starts of traces. When checking is 92 enabled, we validate that we propagate the same data from all sources. 93 94 All traces are members of the TRACE_INFO array, in the order in which 95 they appear in the instruction stream. 96 97 All save points are present in the TRACE_INDEX hash, mapping the insn 98 starting a trace to the dw_trace_info describing the trace. */ 99 100 struct dw_trace_info 101 { 102 /* The insn that begins the trace. */ 103 rtx_insn *head; 104 105 /* The row state at the beginning and end of the trace. */ 106 dw_cfi_row *beg_row, *end_row; 107 108 /* Tracking for DW_CFA_GNU_args_size. The "true" sizes are those we find 109 while scanning insns. However, the args_size value is irrelevant at 110 any point except can_throw_internal_p insns. Therefore the "delay" 111 sizes the values that must actually be emitted for this trace. */ 112 poly_int64_pod beg_true_args_size, end_true_args_size; 113 poly_int64_pod beg_delay_args_size, end_delay_args_size; 114 115 /* The first EH insn in the trace, where beg_delay_args_size must be set. */ 116 rtx_insn *eh_head; 117 118 /* The following variables contain data used in interpreting frame related 119 expressions. These are not part of the "real" row state as defined by 120 Dwarf, but it seems like they need to be propagated into a trace in case 121 frame related expressions have been sunk. */ 122 /* ??? This seems fragile. These variables are fragments of a larger 123 expression. If we do not keep the entire expression together, we risk 124 not being able to put it together properly. Consider forcing targets 125 to generate self-contained expressions and dropping all of the magic 126 interpretation code in this file. Or at least refusing to shrink wrap 127 any frame related insn that doesn't contain a complete expression. */ 128 129 /* The register used for saving registers to the stack, and its offset 130 from the CFA. */ 131 dw_cfa_location cfa_store; 132 133 /* A temporary register holding an integral value used in adjusting SP 134 or setting up the store_reg. The "offset" field holds the integer 135 value, not an offset. */ 136 dw_cfa_location cfa_temp; 137 138 /* A set of registers saved in other registers. This is the inverse of 139 the row->reg_save info, if the entry is a DW_CFA_register. This is 140 implemented as a flat array because it normally contains zero or 1 141 entry, depending on the target. IA-64 is the big spender here, using 142 a maximum of 5 entries. */ 143 vec<reg_saved_in_data> regs_saved_in_regs; 144 145 /* An identifier for this trace. Used only for debugging dumps. */ 146 unsigned id; 147 148 /* True if this trace immediately follows NOTE_INSN_SWITCH_TEXT_SECTIONS. */ 149 bool switch_sections; 150 151 /* True if we've seen different values incoming to beg_true_args_size. */ 152 bool args_size_undefined; 153 154 /* True if we've seen an insn with a REG_ARGS_SIZE note before EH_HEAD. */ 155 bool args_size_defined_for_eh; 156 }; 157 158 159 /* Hashtable helpers. */ 160 161 struct trace_info_hasher : nofree_ptr_hash <dw_trace_info> 162 { 163 static inline hashval_t hash (const dw_trace_info *); 164 static inline bool equal (const dw_trace_info *, const dw_trace_info *); 165 }; 166 167 inline hashval_t 168 trace_info_hasher::hash (const dw_trace_info *ti) 169 { 170 return INSN_UID (ti->head); 171 } 172 173 inline bool 174 trace_info_hasher::equal (const dw_trace_info *a, const dw_trace_info *b) 175 { 176 return a->head == b->head; 177 } 178 179 180 /* The variables making up the pseudo-cfg, as described above. */ 181 static vec<dw_trace_info> trace_info; 182 static vec<dw_trace_info *> trace_work_list; 183 static hash_table<trace_info_hasher> *trace_index; 184 185 /* A vector of call frame insns for the CIE. */ 186 cfi_vec cie_cfi_vec; 187 188 /* The state of the first row of the FDE table, which includes the 189 state provided by the CIE. */ 190 static GTY(()) dw_cfi_row *cie_cfi_row; 191 192 static GTY(()) reg_saved_in_data *cie_return_save; 193 194 static GTY(()) unsigned long dwarf2out_cfi_label_num; 195 196 /* The insn after which a new CFI note should be emitted. */ 197 static rtx_insn *add_cfi_insn; 198 199 /* When non-null, add_cfi will add the CFI to this vector. */ 200 static cfi_vec *add_cfi_vec; 201 202 /* The current instruction trace. */ 203 static dw_trace_info *cur_trace; 204 205 /* The current, i.e. most recently generated, row of the CFI table. */ 206 static dw_cfi_row *cur_row; 207 208 /* A copy of the current CFA, for use during the processing of a 209 single insn. */ 210 static dw_cfa_location *cur_cfa; 211 212 /* We delay emitting a register save until either (a) we reach the end 213 of the prologue or (b) the register is clobbered. This clusters 214 register saves so that there are fewer pc advances. */ 215 216 struct queued_reg_save { 217 rtx reg; 218 rtx saved_reg; 219 poly_int64_pod cfa_offset; 220 }; 221 222 223 static vec<queued_reg_save> queued_reg_saves; 224 225 /* True if any CFI directives were emitted at the current insn. */ 226 static bool any_cfis_emitted; 227 228 /* Short-hand for commonly used register numbers. */ 229 static unsigned dw_stack_pointer_regnum; 230 static unsigned dw_frame_pointer_regnum; 231 232 /* Hook used by __throw. */ 233 234 rtx 235 expand_builtin_dwarf_sp_column (void) 236 { 237 unsigned int dwarf_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); 238 return GEN_INT (DWARF2_FRAME_REG_OUT (dwarf_regnum, 1)); 239 } 240 241 /* MEM is a memory reference for the register size table, each element of 242 which has mode MODE. Initialize column C as a return address column. */ 243 244 static void 245 init_return_column_size (scalar_int_mode mode, rtx mem, unsigned int c) 246 { 247 HOST_WIDE_INT offset = c * GET_MODE_SIZE (mode); 248 HOST_WIDE_INT size = GET_MODE_SIZE (Pmode); 249 emit_move_insn (adjust_address (mem, mode, offset), 250 gen_int_mode (size, mode)); 251 } 252 253 /* Datastructure used by expand_builtin_init_dwarf_reg_sizes and 254 init_one_dwarf_reg_size to communicate on what has been done by the 255 latter. */ 256 257 struct init_one_dwarf_reg_state 258 { 259 /* Whether the dwarf return column was initialized. */ 260 bool wrote_return_column; 261 262 /* For each hard register REGNO, whether init_one_dwarf_reg_size 263 was given REGNO to process already. */ 264 bool processed_regno [FIRST_PSEUDO_REGISTER]; 265 266 }; 267 268 /* Helper for expand_builtin_init_dwarf_reg_sizes. Generate code to 269 initialize the dwarf register size table entry corresponding to register 270 REGNO in REGMODE. TABLE is the table base address, SLOTMODE is the mode to 271 use for the size entry to initialize, and INIT_STATE is the communication 272 datastructure conveying what we're doing to our caller. */ 273 274 static 275 void init_one_dwarf_reg_size (int regno, machine_mode regmode, 276 rtx table, machine_mode slotmode, 277 init_one_dwarf_reg_state *init_state) 278 { 279 const unsigned int dnum = DWARF_FRAME_REGNUM (regno); 280 const unsigned int rnum = DWARF2_FRAME_REG_OUT (dnum, 1); 281 const unsigned int dcol = DWARF_REG_TO_UNWIND_COLUMN (rnum); 282 283 poly_int64 slotoffset = dcol * GET_MODE_SIZE (slotmode); 284 poly_int64 regsize = GET_MODE_SIZE (regmode); 285 286 init_state->processed_regno[regno] = true; 287 288 if (rnum >= DWARF_FRAME_REGISTERS) 289 return; 290 291 if (dnum == DWARF_FRAME_RETURN_COLUMN) 292 { 293 if (regmode == VOIDmode) 294 return; 295 init_state->wrote_return_column = true; 296 } 297 298 /* ??? When is this true? Should it be a test based on DCOL instead? */ 299 if (maybe_lt (slotoffset, 0)) 300 return; 301 302 emit_move_insn (adjust_address (table, slotmode, slotoffset), 303 gen_int_mode (regsize, slotmode)); 304 } 305 306 /* Generate code to initialize the dwarf register size table located 307 at the provided ADDRESS. */ 308 309 void 310 expand_builtin_init_dwarf_reg_sizes (tree address) 311 { 312 unsigned int i; 313 scalar_int_mode mode = SCALAR_INT_TYPE_MODE (char_type_node); 314 rtx addr = expand_normal (address); 315 rtx mem = gen_rtx_MEM (BLKmode, addr); 316 317 init_one_dwarf_reg_state init_state; 318 319 memset ((char *)&init_state, 0, sizeof (init_state)); 320 321 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 322 { 323 machine_mode save_mode; 324 rtx span; 325 326 /* No point in processing a register multiple times. This could happen 327 with register spans, e.g. when a reg is first processed as a piece of 328 a span, then as a register on its own later on. */ 329 330 if (init_state.processed_regno[i]) 331 continue; 332 333 save_mode = targetm.dwarf_frame_reg_mode (i); 334 span = targetm.dwarf_register_span (gen_rtx_REG (save_mode, i)); 335 336 if (!span) 337 init_one_dwarf_reg_size (i, save_mode, mem, mode, &init_state); 338 else 339 { 340 for (int si = 0; si < XVECLEN (span, 0); si++) 341 { 342 rtx reg = XVECEXP (span, 0, si); 343 344 init_one_dwarf_reg_size 345 (REGNO (reg), GET_MODE (reg), mem, mode, &init_state); 346 } 347 } 348 } 349 350 if (!init_state.wrote_return_column) 351 init_return_column_size (mode, mem, DWARF_FRAME_RETURN_COLUMN); 352 353 #ifdef DWARF_ALT_FRAME_RETURN_COLUMN 354 init_return_column_size (mode, mem, DWARF_ALT_FRAME_RETURN_COLUMN); 355 #endif 356 357 targetm.init_dwarf_reg_sizes_extra (address); 358 } 359 360 361 static dw_trace_info * 362 get_trace_info (rtx_insn *insn) 363 { 364 dw_trace_info dummy; 365 dummy.head = insn; 366 return trace_index->find_with_hash (&dummy, INSN_UID (insn)); 367 } 368 369 static bool 370 save_point_p (rtx_insn *insn) 371 { 372 /* Labels, except those that are really jump tables. */ 373 if (LABEL_P (insn)) 374 return inside_basic_block_p (insn); 375 376 /* We split traces at the prologue/epilogue notes because those 377 are points at which the unwind info is usually stable. This 378 makes it easier to find spots with identical unwind info so 379 that we can use remember/restore_state opcodes. */ 380 if (NOTE_P (insn)) 381 switch (NOTE_KIND (insn)) 382 { 383 case NOTE_INSN_PROLOGUE_END: 384 case NOTE_INSN_EPILOGUE_BEG: 385 return true; 386 } 387 388 return false; 389 } 390 391 /* Divide OFF by DWARF_CIE_DATA_ALIGNMENT, asserting no remainder. */ 392 393 static inline HOST_WIDE_INT 394 div_data_align (HOST_WIDE_INT off) 395 { 396 HOST_WIDE_INT r = off / DWARF_CIE_DATA_ALIGNMENT; 397 gcc_assert (r * DWARF_CIE_DATA_ALIGNMENT == off); 398 return r; 399 } 400 401 /* Return true if we need a signed version of a given opcode 402 (e.g. DW_CFA_offset_extended_sf vs DW_CFA_offset_extended). */ 403 404 static inline bool 405 need_data_align_sf_opcode (HOST_WIDE_INT off) 406 { 407 return DWARF_CIE_DATA_ALIGNMENT < 0 ? off > 0 : off < 0; 408 } 409 410 /* Return a pointer to a newly allocated Call Frame Instruction. */ 411 412 static inline dw_cfi_ref 413 new_cfi (void) 414 { 415 dw_cfi_ref cfi = ggc_alloc<dw_cfi_node> (); 416 417 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = 0; 418 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = 0; 419 420 return cfi; 421 } 422 423 /* Return a newly allocated CFI row, with no defined data. */ 424 425 static dw_cfi_row * 426 new_cfi_row (void) 427 { 428 dw_cfi_row *row = ggc_cleared_alloc<dw_cfi_row> (); 429 430 row->cfa.reg = INVALID_REGNUM; 431 432 return row; 433 } 434 435 /* Return a copy of an existing CFI row. */ 436 437 static dw_cfi_row * 438 copy_cfi_row (dw_cfi_row *src) 439 { 440 dw_cfi_row *dst = ggc_alloc<dw_cfi_row> (); 441 442 *dst = *src; 443 dst->reg_save = vec_safe_copy (src->reg_save); 444 445 return dst; 446 } 447 448 /* Return a copy of an existing CFA location. */ 449 450 static dw_cfa_location * 451 copy_cfa (dw_cfa_location *src) 452 { 453 dw_cfa_location *dst = ggc_alloc<dw_cfa_location> (); 454 *dst = *src; 455 return dst; 456 } 457 458 /* Generate a new label for the CFI info to refer to. */ 459 460 static char * 461 dwarf2out_cfi_label (void) 462 { 463 int num = dwarf2out_cfi_label_num++; 464 char label[20]; 465 466 ASM_GENERATE_INTERNAL_LABEL (label, "LCFI", num); 467 468 return xstrdup (label); 469 } 470 471 /* Add CFI either to the current insn stream or to a vector, or both. */ 472 473 static void 474 add_cfi (dw_cfi_ref cfi) 475 { 476 any_cfis_emitted = true; 477 478 if (add_cfi_insn != NULL) 479 { 480 add_cfi_insn = emit_note_after (NOTE_INSN_CFI, add_cfi_insn); 481 NOTE_CFI (add_cfi_insn) = cfi; 482 } 483 484 if (add_cfi_vec != NULL) 485 vec_safe_push (*add_cfi_vec, cfi); 486 } 487 488 static void 489 add_cfi_args_size (poly_int64 size) 490 { 491 /* We don't yet have a representation for polynomial sizes. */ 492 HOST_WIDE_INT const_size = size.to_constant (); 493 494 dw_cfi_ref cfi = new_cfi (); 495 496 /* While we can occasionally have args_size < 0 internally, this state 497 should not persist at a point we actually need an opcode. */ 498 gcc_assert (const_size >= 0); 499 500 cfi->dw_cfi_opc = DW_CFA_GNU_args_size; 501 cfi->dw_cfi_oprnd1.dw_cfi_offset = const_size; 502 503 add_cfi (cfi); 504 } 505 506 static void 507 add_cfi_restore (unsigned reg) 508 { 509 dw_cfi_ref cfi = new_cfi (); 510 511 cfi->dw_cfi_opc = (reg & ~0x3f ? DW_CFA_restore_extended : DW_CFA_restore); 512 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; 513 514 add_cfi (cfi); 515 } 516 517 /* Perform ROW->REG_SAVE[COLUMN] = CFI. CFI may be null, indicating 518 that the register column is no longer saved. */ 519 520 static void 521 update_row_reg_save (dw_cfi_row *row, unsigned column, dw_cfi_ref cfi) 522 { 523 if (vec_safe_length (row->reg_save) <= column) 524 vec_safe_grow_cleared (row->reg_save, column + 1); 525 (*row->reg_save)[column] = cfi; 526 } 527 528 /* This function fills in aa dw_cfa_location structure from a dwarf location 529 descriptor sequence. */ 530 531 static void 532 get_cfa_from_loc_descr (dw_cfa_location *cfa, struct dw_loc_descr_node *loc) 533 { 534 struct dw_loc_descr_node *ptr; 535 cfa->offset = 0; 536 cfa->base_offset = 0; 537 cfa->indirect = 0; 538 cfa->reg = -1; 539 540 for (ptr = loc; ptr != NULL; ptr = ptr->dw_loc_next) 541 { 542 enum dwarf_location_atom op = ptr->dw_loc_opc; 543 544 switch (op) 545 { 546 case DW_OP_reg0: 547 case DW_OP_reg1: 548 case DW_OP_reg2: 549 case DW_OP_reg3: 550 case DW_OP_reg4: 551 case DW_OP_reg5: 552 case DW_OP_reg6: 553 case DW_OP_reg7: 554 case DW_OP_reg8: 555 case DW_OP_reg9: 556 case DW_OP_reg10: 557 case DW_OP_reg11: 558 case DW_OP_reg12: 559 case DW_OP_reg13: 560 case DW_OP_reg14: 561 case DW_OP_reg15: 562 case DW_OP_reg16: 563 case DW_OP_reg17: 564 case DW_OP_reg18: 565 case DW_OP_reg19: 566 case DW_OP_reg20: 567 case DW_OP_reg21: 568 case DW_OP_reg22: 569 case DW_OP_reg23: 570 case DW_OP_reg24: 571 case DW_OP_reg25: 572 case DW_OP_reg26: 573 case DW_OP_reg27: 574 case DW_OP_reg28: 575 case DW_OP_reg29: 576 case DW_OP_reg30: 577 case DW_OP_reg31: 578 cfa->reg = op - DW_OP_reg0; 579 break; 580 case DW_OP_regx: 581 cfa->reg = ptr->dw_loc_oprnd1.v.val_int; 582 break; 583 case DW_OP_breg0: 584 case DW_OP_breg1: 585 case DW_OP_breg2: 586 case DW_OP_breg3: 587 case DW_OP_breg4: 588 case DW_OP_breg5: 589 case DW_OP_breg6: 590 case DW_OP_breg7: 591 case DW_OP_breg8: 592 case DW_OP_breg9: 593 case DW_OP_breg10: 594 case DW_OP_breg11: 595 case DW_OP_breg12: 596 case DW_OP_breg13: 597 case DW_OP_breg14: 598 case DW_OP_breg15: 599 case DW_OP_breg16: 600 case DW_OP_breg17: 601 case DW_OP_breg18: 602 case DW_OP_breg19: 603 case DW_OP_breg20: 604 case DW_OP_breg21: 605 case DW_OP_breg22: 606 case DW_OP_breg23: 607 case DW_OP_breg24: 608 case DW_OP_breg25: 609 case DW_OP_breg26: 610 case DW_OP_breg27: 611 case DW_OP_breg28: 612 case DW_OP_breg29: 613 case DW_OP_breg30: 614 case DW_OP_breg31: 615 cfa->reg = op - DW_OP_breg0; 616 cfa->base_offset = ptr->dw_loc_oprnd1.v.val_int; 617 break; 618 case DW_OP_bregx: 619 cfa->reg = ptr->dw_loc_oprnd1.v.val_int; 620 cfa->base_offset = ptr->dw_loc_oprnd2.v.val_int; 621 break; 622 case DW_OP_deref: 623 cfa->indirect = 1; 624 break; 625 case DW_OP_plus_uconst: 626 cfa->offset = ptr->dw_loc_oprnd1.v.val_unsigned; 627 break; 628 default: 629 gcc_unreachable (); 630 } 631 } 632 } 633 634 /* Find the previous value for the CFA, iteratively. CFI is the opcode 635 to interpret, *LOC will be updated as necessary, *REMEMBER is used for 636 one level of remember/restore state processing. */ 637 638 void 639 lookup_cfa_1 (dw_cfi_ref cfi, dw_cfa_location *loc, dw_cfa_location *remember) 640 { 641 switch (cfi->dw_cfi_opc) 642 { 643 case DW_CFA_def_cfa_offset: 644 case DW_CFA_def_cfa_offset_sf: 645 loc->offset = cfi->dw_cfi_oprnd1.dw_cfi_offset; 646 break; 647 case DW_CFA_def_cfa_register: 648 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; 649 break; 650 case DW_CFA_def_cfa: 651 case DW_CFA_def_cfa_sf: 652 loc->reg = cfi->dw_cfi_oprnd1.dw_cfi_reg_num; 653 loc->offset = cfi->dw_cfi_oprnd2.dw_cfi_offset; 654 break; 655 case DW_CFA_def_cfa_expression: 656 if (cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc) 657 *loc = *cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc; 658 else 659 get_cfa_from_loc_descr (loc, cfi->dw_cfi_oprnd1.dw_cfi_loc); 660 break; 661 662 case DW_CFA_remember_state: 663 gcc_assert (!remember->in_use); 664 *remember = *loc; 665 remember->in_use = 1; 666 break; 667 case DW_CFA_restore_state: 668 gcc_assert (remember->in_use); 669 *loc = *remember; 670 remember->in_use = 0; 671 break; 672 673 default: 674 break; 675 } 676 } 677 678 /* Determine if two dw_cfa_location structures define the same data. */ 679 680 bool 681 cfa_equal_p (const dw_cfa_location *loc1, const dw_cfa_location *loc2) 682 { 683 return (loc1->reg == loc2->reg 684 && known_eq (loc1->offset, loc2->offset) 685 && loc1->indirect == loc2->indirect 686 && (loc1->indirect == 0 687 || known_eq (loc1->base_offset, loc2->base_offset))); 688 } 689 690 /* Determine if two CFI operands are identical. */ 691 692 static bool 693 cfi_oprnd_equal_p (enum dw_cfi_oprnd_type t, dw_cfi_oprnd *a, dw_cfi_oprnd *b) 694 { 695 switch (t) 696 { 697 case dw_cfi_oprnd_unused: 698 return true; 699 case dw_cfi_oprnd_reg_num: 700 return a->dw_cfi_reg_num == b->dw_cfi_reg_num; 701 case dw_cfi_oprnd_offset: 702 return a->dw_cfi_offset == b->dw_cfi_offset; 703 case dw_cfi_oprnd_addr: 704 return (a->dw_cfi_addr == b->dw_cfi_addr 705 || strcmp (a->dw_cfi_addr, b->dw_cfi_addr) == 0); 706 case dw_cfi_oprnd_loc: 707 return loc_descr_equal_p (a->dw_cfi_loc, b->dw_cfi_loc); 708 case dw_cfi_oprnd_cfa_loc: 709 return cfa_equal_p (a->dw_cfi_cfa_loc, b->dw_cfi_cfa_loc); 710 } 711 gcc_unreachable (); 712 } 713 714 /* Determine if two CFI entries are identical. */ 715 716 static bool 717 cfi_equal_p (dw_cfi_ref a, dw_cfi_ref b) 718 { 719 enum dwarf_call_frame_info opc; 720 721 /* Make things easier for our callers, including missing operands. */ 722 if (a == b) 723 return true; 724 if (a == NULL || b == NULL) 725 return false; 726 727 /* Obviously, the opcodes must match. */ 728 opc = a->dw_cfi_opc; 729 if (opc != b->dw_cfi_opc) 730 return false; 731 732 /* Compare the two operands, re-using the type of the operands as 733 already exposed elsewhere. */ 734 return (cfi_oprnd_equal_p (dw_cfi_oprnd1_desc (opc), 735 &a->dw_cfi_oprnd1, &b->dw_cfi_oprnd1) 736 && cfi_oprnd_equal_p (dw_cfi_oprnd2_desc (opc), 737 &a->dw_cfi_oprnd2, &b->dw_cfi_oprnd2)); 738 } 739 740 /* Determine if two CFI_ROW structures are identical. */ 741 742 static bool 743 cfi_row_equal_p (dw_cfi_row *a, dw_cfi_row *b) 744 { 745 size_t i, n_a, n_b, n_max; 746 747 if (a->cfa_cfi) 748 { 749 if (!cfi_equal_p (a->cfa_cfi, b->cfa_cfi)) 750 return false; 751 } 752 else if (!cfa_equal_p (&a->cfa, &b->cfa)) 753 return false; 754 755 n_a = vec_safe_length (a->reg_save); 756 n_b = vec_safe_length (b->reg_save); 757 n_max = MAX (n_a, n_b); 758 759 for (i = 0; i < n_max; ++i) 760 { 761 dw_cfi_ref r_a = NULL, r_b = NULL; 762 763 if (i < n_a) 764 r_a = (*a->reg_save)[i]; 765 if (i < n_b) 766 r_b = (*b->reg_save)[i]; 767 768 if (!cfi_equal_p (r_a, r_b)) 769 return false; 770 } 771 772 if (a->window_save != b->window_save) 773 return false; 774 775 return true; 776 } 777 778 /* The CFA is now calculated from NEW_CFA. Consider OLD_CFA in determining 779 what opcode to emit. Returns the CFI opcode to effect the change, or 780 NULL if NEW_CFA == OLD_CFA. */ 781 782 static dw_cfi_ref 783 def_cfa_0 (dw_cfa_location *old_cfa, dw_cfa_location *new_cfa) 784 { 785 dw_cfi_ref cfi; 786 787 /* If nothing changed, no need to issue any call frame instructions. */ 788 if (cfa_equal_p (old_cfa, new_cfa)) 789 return NULL; 790 791 cfi = new_cfi (); 792 793 HOST_WIDE_INT const_offset; 794 if (new_cfa->reg == old_cfa->reg 795 && !new_cfa->indirect 796 && !old_cfa->indirect 797 && new_cfa->offset.is_constant (&const_offset)) 798 { 799 /* Construct a "DW_CFA_def_cfa_offset <offset>" instruction, indicating 800 the CFA register did not change but the offset did. The data 801 factoring for DW_CFA_def_cfa_offset_sf happens in output_cfi, or 802 in the assembler via the .cfi_def_cfa_offset directive. */ 803 if (const_offset < 0) 804 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset_sf; 805 else 806 cfi->dw_cfi_opc = DW_CFA_def_cfa_offset; 807 cfi->dw_cfi_oprnd1.dw_cfi_offset = const_offset; 808 } 809 else if (new_cfa->offset.is_constant () 810 && known_eq (new_cfa->offset, old_cfa->offset) 811 && old_cfa->reg != INVALID_REGNUM 812 && !new_cfa->indirect 813 && !old_cfa->indirect) 814 { 815 /* Construct a "DW_CFA_def_cfa_register <register>" instruction, 816 indicating the CFA register has changed to <register> but the 817 offset has not changed. This requires the old CFA to have 818 been set as a register plus offset rather than a general 819 DW_CFA_def_cfa_expression. */ 820 cfi->dw_cfi_opc = DW_CFA_def_cfa_register; 821 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; 822 } 823 else if (new_cfa->indirect == 0 824 && new_cfa->offset.is_constant (&const_offset)) 825 { 826 /* Construct a "DW_CFA_def_cfa <register> <offset>" instruction, 827 indicating the CFA register has changed to <register> with 828 the specified offset. The data factoring for DW_CFA_def_cfa_sf 829 happens in output_cfi, or in the assembler via the .cfi_def_cfa 830 directive. */ 831 if (const_offset < 0) 832 cfi->dw_cfi_opc = DW_CFA_def_cfa_sf; 833 else 834 cfi->dw_cfi_opc = DW_CFA_def_cfa; 835 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = new_cfa->reg; 836 cfi->dw_cfi_oprnd2.dw_cfi_offset = const_offset; 837 } 838 else 839 { 840 /* Construct a DW_CFA_def_cfa_expression instruction to 841 calculate the CFA using a full location expression since no 842 register-offset pair is available. */ 843 struct dw_loc_descr_node *loc_list; 844 845 cfi->dw_cfi_opc = DW_CFA_def_cfa_expression; 846 loc_list = build_cfa_loc (new_cfa, 0); 847 cfi->dw_cfi_oprnd1.dw_cfi_loc = loc_list; 848 if (!new_cfa->offset.is_constant () 849 || !new_cfa->base_offset.is_constant ()) 850 /* It's hard to reconstruct the CFA location for a polynomial 851 expression, so just cache it instead. */ 852 cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc = copy_cfa (new_cfa); 853 else 854 cfi->dw_cfi_oprnd2.dw_cfi_cfa_loc = NULL; 855 } 856 857 return cfi; 858 } 859 860 /* Similarly, but take OLD_CFA from CUR_ROW, and update it after the fact. */ 861 862 static void 863 def_cfa_1 (dw_cfa_location *new_cfa) 864 { 865 dw_cfi_ref cfi; 866 867 if (cur_trace->cfa_store.reg == new_cfa->reg && new_cfa->indirect == 0) 868 cur_trace->cfa_store.offset = new_cfa->offset; 869 870 cfi = def_cfa_0 (&cur_row->cfa, new_cfa); 871 if (cfi) 872 { 873 cur_row->cfa = *new_cfa; 874 cur_row->cfa_cfi = (cfi->dw_cfi_opc == DW_CFA_def_cfa_expression 875 ? cfi : NULL); 876 877 add_cfi (cfi); 878 } 879 } 880 881 /* Add the CFI for saving a register. REG is the CFA column number. 882 If SREG is -1, the register is saved at OFFSET from the CFA; 883 otherwise it is saved in SREG. */ 884 885 static void 886 reg_save (unsigned int reg, unsigned int sreg, poly_int64 offset) 887 { 888 dw_fde_ref fde = cfun ? cfun->fde : NULL; 889 dw_cfi_ref cfi = new_cfi (); 890 891 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; 892 893 if (sreg == INVALID_REGNUM) 894 { 895 HOST_WIDE_INT const_offset; 896 /* When stack is aligned, store REG using DW_CFA_expression with FP. */ 897 if (fde && fde->stack_realign) 898 { 899 cfi->dw_cfi_opc = DW_CFA_expression; 900 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; 901 cfi->dw_cfi_oprnd2.dw_cfi_loc 902 = build_cfa_aligned_loc (&cur_row->cfa, offset, 903 fde->stack_realignment); 904 } 905 else if (offset.is_constant (&const_offset)) 906 { 907 if (need_data_align_sf_opcode (const_offset)) 908 cfi->dw_cfi_opc = DW_CFA_offset_extended_sf; 909 else if (reg & ~0x3f) 910 cfi->dw_cfi_opc = DW_CFA_offset_extended; 911 else 912 cfi->dw_cfi_opc = DW_CFA_offset; 913 cfi->dw_cfi_oprnd2.dw_cfi_offset = const_offset; 914 } 915 else 916 { 917 cfi->dw_cfi_opc = DW_CFA_expression; 918 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = reg; 919 cfi->dw_cfi_oprnd2.dw_cfi_loc 920 = build_cfa_loc (&cur_row->cfa, offset); 921 } 922 } 923 else if (sreg == reg) 924 { 925 /* While we could emit something like DW_CFA_same_value or 926 DW_CFA_restore, we never expect to see something like that 927 in a prologue. This is more likely to be a bug. A backend 928 can always bypass this by using REG_CFA_RESTORE directly. */ 929 gcc_unreachable (); 930 } 931 else 932 { 933 cfi->dw_cfi_opc = DW_CFA_register; 934 cfi->dw_cfi_oprnd2.dw_cfi_reg_num = sreg; 935 } 936 937 add_cfi (cfi); 938 update_row_reg_save (cur_row, reg, cfi); 939 } 940 941 /* A subroutine of scan_trace. Check INSN for a REG_ARGS_SIZE note 942 and adjust data structures to match. */ 943 944 static void 945 notice_args_size (rtx_insn *insn) 946 { 947 poly_int64 args_size, delta; 948 rtx note; 949 950 note = find_reg_note (insn, REG_ARGS_SIZE, NULL); 951 if (note == NULL) 952 return; 953 954 if (!cur_trace->eh_head) 955 cur_trace->args_size_defined_for_eh = true; 956 957 args_size = get_args_size (note); 958 delta = args_size - cur_trace->end_true_args_size; 959 if (known_eq (delta, 0)) 960 return; 961 962 cur_trace->end_true_args_size = args_size; 963 964 /* If the CFA is computed off the stack pointer, then we must adjust 965 the computation of the CFA as well. */ 966 if (cur_cfa->reg == dw_stack_pointer_regnum) 967 { 968 gcc_assert (!cur_cfa->indirect); 969 970 /* Convert a change in args_size (always a positive in the 971 direction of stack growth) to a change in stack pointer. */ 972 if (!STACK_GROWS_DOWNWARD) 973 delta = -delta; 974 975 cur_cfa->offset += delta; 976 } 977 } 978 979 /* A subroutine of scan_trace. INSN is can_throw_internal. Update the 980 data within the trace related to EH insns and args_size. */ 981 982 static void 983 notice_eh_throw (rtx_insn *insn) 984 { 985 poly_int64 args_size = cur_trace->end_true_args_size; 986 if (cur_trace->eh_head == NULL) 987 { 988 cur_trace->eh_head = insn; 989 cur_trace->beg_delay_args_size = args_size; 990 cur_trace->end_delay_args_size = args_size; 991 } 992 else if (maybe_ne (cur_trace->end_delay_args_size, args_size)) 993 { 994 cur_trace->end_delay_args_size = args_size; 995 996 /* ??? If the CFA is the stack pointer, search backward for the last 997 CFI note and insert there. Given that the stack changed for the 998 args_size change, there *must* be such a note in between here and 999 the last eh insn. */ 1000 add_cfi_args_size (args_size); 1001 } 1002 } 1003 1004 /* Short-hand inline for the very common D_F_R (REGNO (x)) operation. */ 1005 /* ??? This ought to go into dwarf2out.h, except that dwarf2out.h is 1006 used in places where rtl is prohibited. */ 1007 1008 static inline unsigned 1009 dwf_regno (const_rtx reg) 1010 { 1011 gcc_assert (REGNO (reg) < FIRST_PSEUDO_REGISTER); 1012 return DWARF_FRAME_REGNUM (REGNO (reg)); 1013 } 1014 1015 /* Compare X and Y for equivalence. The inputs may be REGs or PC_RTX. */ 1016 1017 static bool 1018 compare_reg_or_pc (rtx x, rtx y) 1019 { 1020 if (REG_P (x) && REG_P (y)) 1021 return REGNO (x) == REGNO (y); 1022 return x == y; 1023 } 1024 1025 /* Record SRC as being saved in DEST. DEST may be null to delete an 1026 existing entry. SRC may be a register or PC_RTX. */ 1027 1028 static void 1029 record_reg_saved_in_reg (rtx dest, rtx src) 1030 { 1031 reg_saved_in_data *elt; 1032 size_t i; 1033 1034 FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, elt) 1035 if (compare_reg_or_pc (elt->orig_reg, src)) 1036 { 1037 if (dest == NULL) 1038 cur_trace->regs_saved_in_regs.unordered_remove (i); 1039 else 1040 elt->saved_in_reg = dest; 1041 return; 1042 } 1043 1044 if (dest == NULL) 1045 return; 1046 1047 reg_saved_in_data e = {src, dest}; 1048 cur_trace->regs_saved_in_regs.safe_push (e); 1049 } 1050 1051 /* Add an entry to QUEUED_REG_SAVES saying that REG is now saved at 1052 SREG, or if SREG is NULL then it is saved at OFFSET to the CFA. */ 1053 1054 static void 1055 queue_reg_save (rtx reg, rtx sreg, poly_int64 offset) 1056 { 1057 queued_reg_save *q; 1058 queued_reg_save e = {reg, sreg, offset}; 1059 size_t i; 1060 1061 /* Duplicates waste space, but it's also necessary to remove them 1062 for correctness, since the queue gets output in reverse order. */ 1063 FOR_EACH_VEC_ELT (queued_reg_saves, i, q) 1064 if (compare_reg_or_pc (q->reg, reg)) 1065 { 1066 *q = e; 1067 return; 1068 } 1069 1070 queued_reg_saves.safe_push (e); 1071 } 1072 1073 /* Output all the entries in QUEUED_REG_SAVES. */ 1074 1075 static void 1076 dwarf2out_flush_queued_reg_saves (void) 1077 { 1078 queued_reg_save *q; 1079 size_t i; 1080 1081 FOR_EACH_VEC_ELT (queued_reg_saves, i, q) 1082 { 1083 unsigned int reg, sreg; 1084 1085 record_reg_saved_in_reg (q->saved_reg, q->reg); 1086 1087 if (q->reg == pc_rtx) 1088 reg = DWARF_FRAME_RETURN_COLUMN; 1089 else 1090 reg = dwf_regno (q->reg); 1091 if (q->saved_reg) 1092 sreg = dwf_regno (q->saved_reg); 1093 else 1094 sreg = INVALID_REGNUM; 1095 reg_save (reg, sreg, q->cfa_offset); 1096 } 1097 1098 queued_reg_saves.truncate (0); 1099 } 1100 1101 /* Does INSN clobber any register which QUEUED_REG_SAVES lists a saved 1102 location for? Or, does it clobber a register which we've previously 1103 said that some other register is saved in, and for which we now 1104 have a new location for? */ 1105 1106 static bool 1107 clobbers_queued_reg_save (const_rtx insn) 1108 { 1109 queued_reg_save *q; 1110 size_t iq; 1111 1112 FOR_EACH_VEC_ELT (queued_reg_saves, iq, q) 1113 { 1114 size_t ir; 1115 reg_saved_in_data *rir; 1116 1117 if (modified_in_p (q->reg, insn)) 1118 return true; 1119 1120 FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, ir, rir) 1121 if (compare_reg_or_pc (q->reg, rir->orig_reg) 1122 && modified_in_p (rir->saved_in_reg, insn)) 1123 return true; 1124 } 1125 1126 return false; 1127 } 1128 1129 /* What register, if any, is currently saved in REG? */ 1130 1131 static rtx 1132 reg_saved_in (rtx reg) 1133 { 1134 unsigned int regn = REGNO (reg); 1135 queued_reg_save *q; 1136 reg_saved_in_data *rir; 1137 size_t i; 1138 1139 FOR_EACH_VEC_ELT (queued_reg_saves, i, q) 1140 if (q->saved_reg && regn == REGNO (q->saved_reg)) 1141 return q->reg; 1142 1143 FOR_EACH_VEC_ELT (cur_trace->regs_saved_in_regs, i, rir) 1144 if (regn == REGNO (rir->saved_in_reg)) 1145 return rir->orig_reg; 1146 1147 return NULL_RTX; 1148 } 1149 1150 /* A subroutine of dwarf2out_frame_debug, process a REG_DEF_CFA note. */ 1151 1152 static void 1153 dwarf2out_frame_debug_def_cfa (rtx pat) 1154 { 1155 memset (cur_cfa, 0, sizeof (*cur_cfa)); 1156 1157 pat = strip_offset (pat, &cur_cfa->offset); 1158 if (MEM_P (pat)) 1159 { 1160 cur_cfa->indirect = 1; 1161 pat = strip_offset (XEXP (pat, 0), &cur_cfa->base_offset); 1162 } 1163 /* ??? If this fails, we could be calling into the _loc functions to 1164 define a full expression. So far no port does that. */ 1165 gcc_assert (REG_P (pat)); 1166 cur_cfa->reg = dwf_regno (pat); 1167 } 1168 1169 /* A subroutine of dwarf2out_frame_debug, process a REG_ADJUST_CFA note. */ 1170 1171 static void 1172 dwarf2out_frame_debug_adjust_cfa (rtx pat) 1173 { 1174 rtx src, dest; 1175 1176 gcc_assert (GET_CODE (pat) == SET); 1177 dest = XEXP (pat, 0); 1178 src = XEXP (pat, 1); 1179 1180 switch (GET_CODE (src)) 1181 { 1182 case PLUS: 1183 gcc_assert (dwf_regno (XEXP (src, 0)) == cur_cfa->reg); 1184 cur_cfa->offset -= rtx_to_poly_int64 (XEXP (src, 1)); 1185 break; 1186 1187 case REG: 1188 break; 1189 1190 default: 1191 gcc_unreachable (); 1192 } 1193 1194 cur_cfa->reg = dwf_regno (dest); 1195 gcc_assert (cur_cfa->indirect == 0); 1196 } 1197 1198 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_OFFSET note. */ 1199 1200 static void 1201 dwarf2out_frame_debug_cfa_offset (rtx set) 1202 { 1203 poly_int64 offset; 1204 rtx src, addr, span; 1205 unsigned int sregno; 1206 1207 src = XEXP (set, 1); 1208 addr = XEXP (set, 0); 1209 gcc_assert (MEM_P (addr)); 1210 addr = XEXP (addr, 0); 1211 1212 /* As documented, only consider extremely simple addresses. */ 1213 switch (GET_CODE (addr)) 1214 { 1215 case REG: 1216 gcc_assert (dwf_regno (addr) == cur_cfa->reg); 1217 offset = -cur_cfa->offset; 1218 break; 1219 case PLUS: 1220 gcc_assert (dwf_regno (XEXP (addr, 0)) == cur_cfa->reg); 1221 offset = rtx_to_poly_int64 (XEXP (addr, 1)) - cur_cfa->offset; 1222 break; 1223 default: 1224 gcc_unreachable (); 1225 } 1226 1227 if (src == pc_rtx) 1228 { 1229 span = NULL; 1230 sregno = DWARF_FRAME_RETURN_COLUMN; 1231 } 1232 else 1233 { 1234 span = targetm.dwarf_register_span (src); 1235 sregno = dwf_regno (src); 1236 } 1237 1238 /* ??? We'd like to use queue_reg_save, but we need to come up with 1239 a different flushing heuristic for epilogues. */ 1240 if (!span) 1241 reg_save (sregno, INVALID_REGNUM, offset); 1242 else 1243 { 1244 /* We have a PARALLEL describing where the contents of SRC live. 1245 Adjust the offset for each piece of the PARALLEL. */ 1246 poly_int64 span_offset = offset; 1247 1248 gcc_assert (GET_CODE (span) == PARALLEL); 1249 1250 const int par_len = XVECLEN (span, 0); 1251 for (int par_index = 0; par_index < par_len; par_index++) 1252 { 1253 rtx elem = XVECEXP (span, 0, par_index); 1254 sregno = dwf_regno (src); 1255 reg_save (sregno, INVALID_REGNUM, span_offset); 1256 span_offset += GET_MODE_SIZE (GET_MODE (elem)); 1257 } 1258 } 1259 } 1260 1261 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_REGISTER note. */ 1262 1263 static void 1264 dwarf2out_frame_debug_cfa_register (rtx set) 1265 { 1266 rtx src, dest; 1267 unsigned sregno, dregno; 1268 1269 src = XEXP (set, 1); 1270 dest = XEXP (set, 0); 1271 1272 record_reg_saved_in_reg (dest, src); 1273 if (src == pc_rtx) 1274 sregno = DWARF_FRAME_RETURN_COLUMN; 1275 else 1276 sregno = dwf_regno (src); 1277 1278 dregno = dwf_regno (dest); 1279 1280 /* ??? We'd like to use queue_reg_save, but we need to come up with 1281 a different flushing heuristic for epilogues. */ 1282 reg_save (sregno, dregno, 0); 1283 } 1284 1285 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_EXPRESSION note. */ 1286 1287 static void 1288 dwarf2out_frame_debug_cfa_expression (rtx set) 1289 { 1290 rtx src, dest, span; 1291 dw_cfi_ref cfi = new_cfi (); 1292 unsigned regno; 1293 1294 dest = SET_DEST (set); 1295 src = SET_SRC (set); 1296 1297 gcc_assert (REG_P (src)); 1298 gcc_assert (MEM_P (dest)); 1299 1300 span = targetm.dwarf_register_span (src); 1301 gcc_assert (!span); 1302 1303 regno = dwf_regno (src); 1304 1305 cfi->dw_cfi_opc = DW_CFA_expression; 1306 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = regno; 1307 cfi->dw_cfi_oprnd2.dw_cfi_loc 1308 = mem_loc_descriptor (XEXP (dest, 0), get_address_mode (dest), 1309 GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED); 1310 1311 /* ??? We'd like to use queue_reg_save, were the interface different, 1312 and, as above, we could manage flushing for epilogues. */ 1313 add_cfi (cfi); 1314 update_row_reg_save (cur_row, regno, cfi); 1315 } 1316 1317 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_VAL_EXPRESSION 1318 note. */ 1319 1320 static void 1321 dwarf2out_frame_debug_cfa_val_expression (rtx set) 1322 { 1323 rtx dest = SET_DEST (set); 1324 gcc_assert (REG_P (dest)); 1325 1326 rtx span = targetm.dwarf_register_span (dest); 1327 gcc_assert (!span); 1328 1329 rtx src = SET_SRC (set); 1330 dw_cfi_ref cfi = new_cfi (); 1331 cfi->dw_cfi_opc = DW_CFA_val_expression; 1332 cfi->dw_cfi_oprnd1.dw_cfi_reg_num = dwf_regno (dest); 1333 cfi->dw_cfi_oprnd2.dw_cfi_loc 1334 = mem_loc_descriptor (src, GET_MODE (src), 1335 GET_MODE (dest), VAR_INIT_STATUS_INITIALIZED); 1336 add_cfi (cfi); 1337 update_row_reg_save (cur_row, dwf_regno (dest), cfi); 1338 } 1339 1340 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_RESTORE note. */ 1341 1342 static void 1343 dwarf2out_frame_debug_cfa_restore (rtx reg) 1344 { 1345 gcc_assert (REG_P (reg)); 1346 1347 rtx span = targetm.dwarf_register_span (reg); 1348 if (!span) 1349 { 1350 unsigned int regno = dwf_regno (reg); 1351 add_cfi_restore (regno); 1352 update_row_reg_save (cur_row, regno, NULL); 1353 } 1354 else 1355 { 1356 /* We have a PARALLEL describing where the contents of REG live. 1357 Restore the register for each piece of the PARALLEL. */ 1358 gcc_assert (GET_CODE (span) == PARALLEL); 1359 1360 const int par_len = XVECLEN (span, 0); 1361 for (int par_index = 0; par_index < par_len; par_index++) 1362 { 1363 reg = XVECEXP (span, 0, par_index); 1364 gcc_assert (REG_P (reg)); 1365 unsigned int regno = dwf_regno (reg); 1366 add_cfi_restore (regno); 1367 update_row_reg_save (cur_row, regno, NULL); 1368 } 1369 } 1370 } 1371 1372 /* A subroutine of dwarf2out_frame_debug, process a REG_CFA_WINDOW_SAVE. 1373 FAKE is true if this is not really a window save but something else. 1374 1375 ??? Perhaps we should note in the CIE where windows are saved (instead 1376 of assuming 0(cfa)) and what registers are in the window. */ 1377 1378 static void 1379 dwarf2out_frame_debug_cfa_window_save (bool fake) 1380 { 1381 dw_cfi_ref cfi = new_cfi (); 1382 1383 cfi->dw_cfi_opc = DW_CFA_GNU_window_save; 1384 add_cfi (cfi); 1385 if (!fake) 1386 cur_row->window_save = true; 1387 } 1388 1389 /* Record call frame debugging information for an expression EXPR, 1390 which either sets SP or FP (adjusting how we calculate the frame 1391 address) or saves a register to the stack or another register. 1392 LABEL indicates the address of EXPR. 1393 1394 This function encodes a state machine mapping rtxes to actions on 1395 cfa, cfa_store, and cfa_temp.reg. We describe these rules so 1396 users need not read the source code. 1397 1398 The High-Level Picture 1399 1400 Changes in the register we use to calculate the CFA: Currently we 1401 assume that if you copy the CFA register into another register, we 1402 should take the other one as the new CFA register; this seems to 1403 work pretty well. If it's wrong for some target, it's simple 1404 enough not to set RTX_FRAME_RELATED_P on the insn in question. 1405 1406 Changes in the register we use for saving registers to the stack: 1407 This is usually SP, but not always. Again, we deduce that if you 1408 copy SP into another register (and SP is not the CFA register), 1409 then the new register is the one we will be using for register 1410 saves. This also seems to work. 1411 1412 Register saves: There's not much guesswork about this one; if 1413 RTX_FRAME_RELATED_P is set on an insn which modifies memory, it's a 1414 register save, and the register used to calculate the destination 1415 had better be the one we think we're using for this purpose. 1416 It's also assumed that a copy from a call-saved register to another 1417 register is saving that register if RTX_FRAME_RELATED_P is set on 1418 that instruction. If the copy is from a call-saved register to 1419 the *same* register, that means that the register is now the same 1420 value as in the caller. 1421 1422 Except: If the register being saved is the CFA register, and the 1423 offset is nonzero, we are saving the CFA, so we assume we have to 1424 use DW_CFA_def_cfa_expression. If the offset is 0, we assume that 1425 the intent is to save the value of SP from the previous frame. 1426 1427 In addition, if a register has previously been saved to a different 1428 register, 1429 1430 Invariants / Summaries of Rules 1431 1432 cfa current rule for calculating the CFA. It usually 1433 consists of a register and an offset. This is 1434 actually stored in *cur_cfa, but abbreviated 1435 for the purposes of this documentation. 1436 cfa_store register used by prologue code to save things to the stack 1437 cfa_store.offset is the offset from the value of 1438 cfa_store.reg to the actual CFA 1439 cfa_temp register holding an integral value. cfa_temp.offset 1440 stores the value, which will be used to adjust the 1441 stack pointer. cfa_temp is also used like cfa_store, 1442 to track stores to the stack via fp or a temp reg. 1443 1444 Rules 1- 4: Setting a register's value to cfa.reg or an expression 1445 with cfa.reg as the first operand changes the cfa.reg and its 1446 cfa.offset. Rule 1 and 4 also set cfa_temp.reg and 1447 cfa_temp.offset. 1448 1449 Rules 6- 9: Set a non-cfa.reg register value to a constant or an 1450 expression yielding a constant. This sets cfa_temp.reg 1451 and cfa_temp.offset. 1452 1453 Rule 5: Create a new register cfa_store used to save items to the 1454 stack. 1455 1456 Rules 10-14: Save a register to the stack. Define offset as the 1457 difference of the original location and cfa_store's 1458 location (or cfa_temp's location if cfa_temp is used). 1459 1460 Rules 16-20: If AND operation happens on sp in prologue, we assume 1461 stack is realigned. We will use a group of DW_OP_XXX 1462 expressions to represent the location of the stored 1463 register instead of CFA+offset. 1464 1465 The Rules 1466 1467 "{a,b}" indicates a choice of a xor b. 1468 "<reg>:cfa.reg" indicates that <reg> must equal cfa.reg. 1469 1470 Rule 1: 1471 (set <reg1> <reg2>:cfa.reg) 1472 effects: cfa.reg = <reg1> 1473 cfa.offset unchanged 1474 cfa_temp.reg = <reg1> 1475 cfa_temp.offset = cfa.offset 1476 1477 Rule 2: 1478 (set sp ({minus,plus,losum} {sp,fp}:cfa.reg 1479 {<const_int>,<reg>:cfa_temp.reg})) 1480 effects: cfa.reg = sp if fp used 1481 cfa.offset += {+/- <const_int>, cfa_temp.offset} if cfa.reg==sp 1482 cfa_store.offset += {+/- <const_int>, cfa_temp.offset} 1483 if cfa_store.reg==sp 1484 1485 Rule 3: 1486 (set fp ({minus,plus,losum} <reg>:cfa.reg <const_int>)) 1487 effects: cfa.reg = fp 1488 cfa_offset += +/- <const_int> 1489 1490 Rule 4: 1491 (set <reg1> ({plus,losum} <reg2>:cfa.reg <const_int>)) 1492 constraints: <reg1> != fp 1493 <reg1> != sp 1494 effects: cfa.reg = <reg1> 1495 cfa_temp.reg = <reg1> 1496 cfa_temp.offset = cfa.offset 1497 1498 Rule 5: 1499 (set <reg1> (plus <reg2>:cfa_temp.reg sp:cfa.reg)) 1500 constraints: <reg1> != fp 1501 <reg1> != sp 1502 effects: cfa_store.reg = <reg1> 1503 cfa_store.offset = cfa.offset - cfa_temp.offset 1504 1505 Rule 6: 1506 (set <reg> <const_int>) 1507 effects: cfa_temp.reg = <reg> 1508 cfa_temp.offset = <const_int> 1509 1510 Rule 7: 1511 (set <reg1>:cfa_temp.reg (ior <reg2>:cfa_temp.reg <const_int>)) 1512 effects: cfa_temp.reg = <reg1> 1513 cfa_temp.offset |= <const_int> 1514 1515 Rule 8: 1516 (set <reg> (high <exp>)) 1517 effects: none 1518 1519 Rule 9: 1520 (set <reg> (lo_sum <exp> <const_int>)) 1521 effects: cfa_temp.reg = <reg> 1522 cfa_temp.offset = <const_int> 1523 1524 Rule 10: 1525 (set (mem ({pre,post}_modify sp:cfa_store (???? <reg1> <const_int>))) <reg2>) 1526 effects: cfa_store.offset -= <const_int> 1527 cfa.offset = cfa_store.offset if cfa.reg == sp 1528 cfa.reg = sp 1529 cfa.base_offset = -cfa_store.offset 1530 1531 Rule 11: 1532 (set (mem ({pre_inc,pre_dec,post_dec} sp:cfa_store.reg)) <reg>) 1533 effects: cfa_store.offset += -/+ mode_size(mem) 1534 cfa.offset = cfa_store.offset if cfa.reg == sp 1535 cfa.reg = sp 1536 cfa.base_offset = -cfa_store.offset 1537 1538 Rule 12: 1539 (set (mem ({minus,plus,losum} <reg1>:{cfa_store,cfa_temp} <const_int>)) 1540 1541 <reg2>) 1542 effects: cfa.reg = <reg1> 1543 cfa.base_offset = -/+ <const_int> - {cfa_store,cfa_temp}.offset 1544 1545 Rule 13: 1546 (set (mem <reg1>:{cfa_store,cfa_temp}) <reg2>) 1547 effects: cfa.reg = <reg1> 1548 cfa.base_offset = -{cfa_store,cfa_temp}.offset 1549 1550 Rule 14: 1551 (set (mem (post_inc <reg1>:cfa_temp <const_int>)) <reg2>) 1552 effects: cfa.reg = <reg1> 1553 cfa.base_offset = -cfa_temp.offset 1554 cfa_temp.offset -= mode_size(mem) 1555 1556 Rule 15: 1557 (set <reg> {unspec, unspec_volatile}) 1558 effects: target-dependent 1559 1560 Rule 16: 1561 (set sp (and: sp <const_int>)) 1562 constraints: cfa_store.reg == sp 1563 effects: cfun->fde.stack_realign = 1 1564 cfa_store.offset = 0 1565 fde->drap_reg = cfa.reg if cfa.reg != sp and cfa.reg != fp 1566 1567 Rule 17: 1568 (set (mem ({pre_inc, pre_dec} sp)) (mem (plus (cfa.reg) (const_int)))) 1569 effects: cfa_store.offset += -/+ mode_size(mem) 1570 1571 Rule 18: 1572 (set (mem ({pre_inc, pre_dec} sp)) fp) 1573 constraints: fde->stack_realign == 1 1574 effects: cfa_store.offset = 0 1575 cfa.reg != HARD_FRAME_POINTER_REGNUM 1576 1577 Rule 19: 1578 (set (mem ({pre_inc, pre_dec} sp)) cfa.reg) 1579 constraints: fde->stack_realign == 1 1580 && cfa.offset == 0 1581 && cfa.indirect == 0 1582 && cfa.reg != HARD_FRAME_POINTER_REGNUM 1583 effects: Use DW_CFA_def_cfa_expression to define cfa 1584 cfa.reg == fde->drap_reg */ 1585 1586 static void 1587 dwarf2out_frame_debug_expr (rtx expr) 1588 { 1589 rtx src, dest, span; 1590 poly_int64 offset; 1591 dw_fde_ref fde; 1592 1593 /* If RTX_FRAME_RELATED_P is set on a PARALLEL, process each member of 1594 the PARALLEL independently. The first element is always processed if 1595 it is a SET. This is for backward compatibility. Other elements 1596 are processed only if they are SETs and the RTX_FRAME_RELATED_P 1597 flag is set in them. */ 1598 if (GET_CODE (expr) == PARALLEL || GET_CODE (expr) == SEQUENCE) 1599 { 1600 int par_index; 1601 int limit = XVECLEN (expr, 0); 1602 rtx elem; 1603 1604 /* PARALLELs have strict read-modify-write semantics, so we 1605 ought to evaluate every rvalue before changing any lvalue. 1606 It's cumbersome to do that in general, but there's an 1607 easy approximation that is enough for all current users: 1608 handle register saves before register assignments. */ 1609 if (GET_CODE (expr) == PARALLEL) 1610 for (par_index = 0; par_index < limit; par_index++) 1611 { 1612 elem = XVECEXP (expr, 0, par_index); 1613 if (GET_CODE (elem) == SET 1614 && MEM_P (SET_DEST (elem)) 1615 && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) 1616 dwarf2out_frame_debug_expr (elem); 1617 } 1618 1619 for (par_index = 0; par_index < limit; par_index++) 1620 { 1621 elem = XVECEXP (expr, 0, par_index); 1622 if (GET_CODE (elem) == SET 1623 && (!MEM_P (SET_DEST (elem)) || GET_CODE (expr) == SEQUENCE) 1624 && (RTX_FRAME_RELATED_P (elem) || par_index == 0)) 1625 dwarf2out_frame_debug_expr (elem); 1626 } 1627 return; 1628 } 1629 1630 gcc_assert (GET_CODE (expr) == SET); 1631 1632 src = SET_SRC (expr); 1633 dest = SET_DEST (expr); 1634 1635 if (REG_P (src)) 1636 { 1637 rtx rsi = reg_saved_in (src); 1638 if (rsi) 1639 src = rsi; 1640 } 1641 1642 fde = cfun->fde; 1643 1644 switch (GET_CODE (dest)) 1645 { 1646 case REG: 1647 switch (GET_CODE (src)) 1648 { 1649 /* Setting FP from SP. */ 1650 case REG: 1651 if (cur_cfa->reg == dwf_regno (src)) 1652 { 1653 /* Rule 1 */ 1654 /* Update the CFA rule wrt SP or FP. Make sure src is 1655 relative to the current CFA register. 1656 1657 We used to require that dest be either SP or FP, but the 1658 ARM copies SP to a temporary register, and from there to 1659 FP. So we just rely on the backends to only set 1660 RTX_FRAME_RELATED_P on appropriate insns. */ 1661 cur_cfa->reg = dwf_regno (dest); 1662 cur_trace->cfa_temp.reg = cur_cfa->reg; 1663 cur_trace->cfa_temp.offset = cur_cfa->offset; 1664 } 1665 else 1666 { 1667 /* Saving a register in a register. */ 1668 gcc_assert (!fixed_regs [REGNO (dest)] 1669 /* For the SPARC and its register window. */ 1670 || (dwf_regno (src) == DWARF_FRAME_RETURN_COLUMN)); 1671 1672 /* After stack is aligned, we can only save SP in FP 1673 if drap register is used. In this case, we have 1674 to restore stack pointer with the CFA value and we 1675 don't generate this DWARF information. */ 1676 if (fde 1677 && fde->stack_realign 1678 && REGNO (src) == STACK_POINTER_REGNUM) 1679 gcc_assert (REGNO (dest) == HARD_FRAME_POINTER_REGNUM 1680 && fde->drap_reg != INVALID_REGNUM 1681 && cur_cfa->reg != dwf_regno (src)); 1682 else 1683 queue_reg_save (src, dest, 0); 1684 } 1685 break; 1686 1687 case PLUS: 1688 case MINUS: 1689 case LO_SUM: 1690 if (dest == stack_pointer_rtx) 1691 { 1692 /* Rule 2 */ 1693 /* Adjusting SP. */ 1694 if (REG_P (XEXP (src, 1))) 1695 { 1696 gcc_assert (dwf_regno (XEXP (src, 1)) 1697 == cur_trace->cfa_temp.reg); 1698 offset = cur_trace->cfa_temp.offset; 1699 } 1700 else if (!poly_int_rtx_p (XEXP (src, 1), &offset)) 1701 gcc_unreachable (); 1702 1703 if (XEXP (src, 0) == hard_frame_pointer_rtx) 1704 { 1705 /* Restoring SP from FP in the epilogue. */ 1706 gcc_assert (cur_cfa->reg == dw_frame_pointer_regnum); 1707 cur_cfa->reg = dw_stack_pointer_regnum; 1708 } 1709 else if (GET_CODE (src) == LO_SUM) 1710 /* Assume we've set the source reg of the LO_SUM from sp. */ 1711 ; 1712 else 1713 gcc_assert (XEXP (src, 0) == stack_pointer_rtx); 1714 1715 if (GET_CODE (src) != MINUS) 1716 offset = -offset; 1717 if (cur_cfa->reg == dw_stack_pointer_regnum) 1718 cur_cfa->offset += offset; 1719 if (cur_trace->cfa_store.reg == dw_stack_pointer_regnum) 1720 cur_trace->cfa_store.offset += offset; 1721 } 1722 else if (dest == hard_frame_pointer_rtx) 1723 { 1724 /* Rule 3 */ 1725 /* Either setting the FP from an offset of the SP, 1726 or adjusting the FP */ 1727 gcc_assert (frame_pointer_needed); 1728 1729 gcc_assert (REG_P (XEXP (src, 0)) 1730 && dwf_regno (XEXP (src, 0)) == cur_cfa->reg); 1731 offset = rtx_to_poly_int64 (XEXP (src, 1)); 1732 if (GET_CODE (src) != MINUS) 1733 offset = -offset; 1734 cur_cfa->offset += offset; 1735 cur_cfa->reg = dw_frame_pointer_regnum; 1736 } 1737 else 1738 { 1739 gcc_assert (GET_CODE (src) != MINUS); 1740 1741 /* Rule 4 */ 1742 if (REG_P (XEXP (src, 0)) 1743 && dwf_regno (XEXP (src, 0)) == cur_cfa->reg 1744 && poly_int_rtx_p (XEXP (src, 1), &offset)) 1745 { 1746 /* Setting a temporary CFA register that will be copied 1747 into the FP later on. */ 1748 offset = -offset; 1749 cur_cfa->offset += offset; 1750 cur_cfa->reg = dwf_regno (dest); 1751 /* Or used to save regs to the stack. */ 1752 cur_trace->cfa_temp.reg = cur_cfa->reg; 1753 cur_trace->cfa_temp.offset = cur_cfa->offset; 1754 } 1755 1756 /* Rule 5 */ 1757 else if (REG_P (XEXP (src, 0)) 1758 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg 1759 && XEXP (src, 1) == stack_pointer_rtx) 1760 { 1761 /* Setting a scratch register that we will use instead 1762 of SP for saving registers to the stack. */ 1763 gcc_assert (cur_cfa->reg == dw_stack_pointer_regnum); 1764 cur_trace->cfa_store.reg = dwf_regno (dest); 1765 cur_trace->cfa_store.offset 1766 = cur_cfa->offset - cur_trace->cfa_temp.offset; 1767 } 1768 1769 /* Rule 9 */ 1770 else if (GET_CODE (src) == LO_SUM 1771 && poly_int_rtx_p (XEXP (src, 1), 1772 &cur_trace->cfa_temp.offset)) 1773 cur_trace->cfa_temp.reg = dwf_regno (dest); 1774 else 1775 gcc_unreachable (); 1776 } 1777 break; 1778 1779 /* Rule 6 */ 1780 case CONST_INT: 1781 case CONST_POLY_INT: 1782 cur_trace->cfa_temp.reg = dwf_regno (dest); 1783 cur_trace->cfa_temp.offset = rtx_to_poly_int64 (src); 1784 break; 1785 1786 /* Rule 7 */ 1787 case IOR: 1788 gcc_assert (REG_P (XEXP (src, 0)) 1789 && dwf_regno (XEXP (src, 0)) == cur_trace->cfa_temp.reg 1790 && CONST_INT_P (XEXP (src, 1))); 1791 1792 cur_trace->cfa_temp.reg = dwf_regno (dest); 1793 if (!can_ior_p (cur_trace->cfa_temp.offset, INTVAL (XEXP (src, 1)), 1794 &cur_trace->cfa_temp.offset)) 1795 /* The target shouldn't generate this kind of CFI note if we 1796 can't represent it. */ 1797 gcc_unreachable (); 1798 break; 1799 1800 /* Skip over HIGH, assuming it will be followed by a LO_SUM, 1801 which will fill in all of the bits. */ 1802 /* Rule 8 */ 1803 case HIGH: 1804 break; 1805 1806 /* Rule 15 */ 1807 case UNSPEC: 1808 case UNSPEC_VOLATILE: 1809 /* All unspecs should be represented by REG_CFA_* notes. */ 1810 gcc_unreachable (); 1811 return; 1812 1813 /* Rule 16 */ 1814 case AND: 1815 /* If this AND operation happens on stack pointer in prologue, 1816 we assume the stack is realigned and we extract the 1817 alignment. */ 1818 if (fde && XEXP (src, 0) == stack_pointer_rtx) 1819 { 1820 /* We interpret reg_save differently with stack_realign set. 1821 Thus we must flush whatever we have queued first. */ 1822 dwarf2out_flush_queued_reg_saves (); 1823 1824 gcc_assert (cur_trace->cfa_store.reg 1825 == dwf_regno (XEXP (src, 0))); 1826 fde->stack_realign = 1; 1827 fde->stack_realignment = INTVAL (XEXP (src, 1)); 1828 cur_trace->cfa_store.offset = 0; 1829 1830 if (cur_cfa->reg != dw_stack_pointer_regnum 1831 && cur_cfa->reg != dw_frame_pointer_regnum) 1832 fde->drap_reg = cur_cfa->reg; 1833 } 1834 return; 1835 1836 default: 1837 gcc_unreachable (); 1838 } 1839 break; 1840 1841 case MEM: 1842 1843 /* Saving a register to the stack. Make sure dest is relative to the 1844 CFA register. */ 1845 switch (GET_CODE (XEXP (dest, 0))) 1846 { 1847 /* Rule 10 */ 1848 /* With a push. */ 1849 case PRE_MODIFY: 1850 case POST_MODIFY: 1851 /* We can't handle variable size modifications. */ 1852 offset = -rtx_to_poly_int64 (XEXP (XEXP (XEXP (dest, 0), 1), 1)); 1853 1854 gcc_assert (REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM 1855 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); 1856 1857 cur_trace->cfa_store.offset += offset; 1858 if (cur_cfa->reg == dw_stack_pointer_regnum) 1859 cur_cfa->offset = cur_trace->cfa_store.offset; 1860 1861 if (GET_CODE (XEXP (dest, 0)) == POST_MODIFY) 1862 offset -= cur_trace->cfa_store.offset; 1863 else 1864 offset = -cur_trace->cfa_store.offset; 1865 break; 1866 1867 /* Rule 11 */ 1868 case PRE_INC: 1869 case PRE_DEC: 1870 case POST_DEC: 1871 offset = GET_MODE_SIZE (GET_MODE (dest)); 1872 if (GET_CODE (XEXP (dest, 0)) == PRE_INC) 1873 offset = -offset; 1874 1875 gcc_assert ((REGNO (XEXP (XEXP (dest, 0), 0)) 1876 == STACK_POINTER_REGNUM) 1877 && cur_trace->cfa_store.reg == dw_stack_pointer_regnum); 1878 1879 cur_trace->cfa_store.offset += offset; 1880 1881 /* Rule 18: If stack is aligned, we will use FP as a 1882 reference to represent the address of the stored 1883 regiser. */ 1884 if (fde 1885 && fde->stack_realign 1886 && REG_P (src) 1887 && REGNO (src) == HARD_FRAME_POINTER_REGNUM) 1888 { 1889 gcc_assert (cur_cfa->reg != dw_frame_pointer_regnum); 1890 cur_trace->cfa_store.offset = 0; 1891 } 1892 1893 if (cur_cfa->reg == dw_stack_pointer_regnum) 1894 cur_cfa->offset = cur_trace->cfa_store.offset; 1895 1896 if (GET_CODE (XEXP (dest, 0)) == POST_DEC) 1897 offset += -cur_trace->cfa_store.offset; 1898 else 1899 offset = -cur_trace->cfa_store.offset; 1900 break; 1901 1902 /* Rule 12 */ 1903 /* With an offset. */ 1904 case PLUS: 1905 case MINUS: 1906 case LO_SUM: 1907 { 1908 unsigned int regno; 1909 1910 gcc_assert (REG_P (XEXP (XEXP (dest, 0), 0))); 1911 offset = rtx_to_poly_int64 (XEXP (XEXP (dest, 0), 1)); 1912 if (GET_CODE (XEXP (dest, 0)) == MINUS) 1913 offset = -offset; 1914 1915 regno = dwf_regno (XEXP (XEXP (dest, 0), 0)); 1916 1917 if (cur_cfa->reg == regno) 1918 offset -= cur_cfa->offset; 1919 else if (cur_trace->cfa_store.reg == regno) 1920 offset -= cur_trace->cfa_store.offset; 1921 else 1922 { 1923 gcc_assert (cur_trace->cfa_temp.reg == regno); 1924 offset -= cur_trace->cfa_temp.offset; 1925 } 1926 } 1927 break; 1928 1929 /* Rule 13 */ 1930 /* Without an offset. */ 1931 case REG: 1932 { 1933 unsigned int regno = dwf_regno (XEXP (dest, 0)); 1934 1935 if (cur_cfa->reg == regno) 1936 offset = -cur_cfa->offset; 1937 else if (cur_trace->cfa_store.reg == regno) 1938 offset = -cur_trace->cfa_store.offset; 1939 else 1940 { 1941 gcc_assert (cur_trace->cfa_temp.reg == regno); 1942 offset = -cur_trace->cfa_temp.offset; 1943 } 1944 } 1945 break; 1946 1947 /* Rule 14 */ 1948 case POST_INC: 1949 gcc_assert (cur_trace->cfa_temp.reg 1950 == dwf_regno (XEXP (XEXP (dest, 0), 0))); 1951 offset = -cur_trace->cfa_temp.offset; 1952 cur_trace->cfa_temp.offset -= GET_MODE_SIZE (GET_MODE (dest)); 1953 break; 1954 1955 default: 1956 gcc_unreachable (); 1957 } 1958 1959 /* Rule 17 */ 1960 /* If the source operand of this MEM operation is a memory, 1961 we only care how much stack grew. */ 1962 if (MEM_P (src)) 1963 break; 1964 1965 if (REG_P (src) 1966 && REGNO (src) != STACK_POINTER_REGNUM 1967 && REGNO (src) != HARD_FRAME_POINTER_REGNUM 1968 && dwf_regno (src) == cur_cfa->reg) 1969 { 1970 /* We're storing the current CFA reg into the stack. */ 1971 1972 if (known_eq (cur_cfa->offset, 0)) 1973 { 1974 /* Rule 19 */ 1975 /* If stack is aligned, putting CFA reg into stack means 1976 we can no longer use reg + offset to represent CFA. 1977 Here we use DW_CFA_def_cfa_expression instead. The 1978 result of this expression equals to the original CFA 1979 value. */ 1980 if (fde 1981 && fde->stack_realign 1982 && cur_cfa->indirect == 0 1983 && cur_cfa->reg != dw_frame_pointer_regnum) 1984 { 1985 gcc_assert (fde->drap_reg == cur_cfa->reg); 1986 1987 cur_cfa->indirect = 1; 1988 cur_cfa->reg = dw_frame_pointer_regnum; 1989 cur_cfa->base_offset = offset; 1990 cur_cfa->offset = 0; 1991 1992 fde->drap_reg_saved = 1; 1993 break; 1994 } 1995 1996 /* If the source register is exactly the CFA, assume 1997 we're saving SP like any other register; this happens 1998 on the ARM. */ 1999 queue_reg_save (stack_pointer_rtx, NULL_RTX, offset); 2000 break; 2001 } 2002 else 2003 { 2004 /* Otherwise, we'll need to look in the stack to 2005 calculate the CFA. */ 2006 rtx x = XEXP (dest, 0); 2007 2008 if (!REG_P (x)) 2009 x = XEXP (x, 0); 2010 gcc_assert (REG_P (x)); 2011 2012 cur_cfa->reg = dwf_regno (x); 2013 cur_cfa->base_offset = offset; 2014 cur_cfa->indirect = 1; 2015 break; 2016 } 2017 } 2018 2019 if (REG_P (src)) 2020 span = targetm.dwarf_register_span (src); 2021 else 2022 span = NULL; 2023 2024 if (!span) 2025 queue_reg_save (src, NULL_RTX, offset); 2026 else 2027 { 2028 /* We have a PARALLEL describing where the contents of SRC live. 2029 Queue register saves for each piece of the PARALLEL. */ 2030 poly_int64 span_offset = offset; 2031 2032 gcc_assert (GET_CODE (span) == PARALLEL); 2033 2034 const int par_len = XVECLEN (span, 0); 2035 for (int par_index = 0; par_index < par_len; par_index++) 2036 { 2037 rtx elem = XVECEXP (span, 0, par_index); 2038 queue_reg_save (elem, NULL_RTX, span_offset); 2039 span_offset += GET_MODE_SIZE (GET_MODE (elem)); 2040 } 2041 } 2042 break; 2043 2044 default: 2045 gcc_unreachable (); 2046 } 2047 } 2048 2049 /* Record call frame debugging information for INSN, which either sets 2050 SP or FP (adjusting how we calculate the frame address) or saves a 2051 register to the stack. */ 2052 2053 static void 2054 dwarf2out_frame_debug (rtx_insn *insn) 2055 { 2056 rtx note, n, pat; 2057 bool handled_one = false; 2058 2059 for (note = REG_NOTES (insn); note; note = XEXP (note, 1)) 2060 switch (REG_NOTE_KIND (note)) 2061 { 2062 case REG_FRAME_RELATED_EXPR: 2063 pat = XEXP (note, 0); 2064 goto do_frame_expr; 2065 2066 case REG_CFA_DEF_CFA: 2067 dwarf2out_frame_debug_def_cfa (XEXP (note, 0)); 2068 handled_one = true; 2069 break; 2070 2071 case REG_CFA_ADJUST_CFA: 2072 n = XEXP (note, 0); 2073 if (n == NULL) 2074 { 2075 n = PATTERN (insn); 2076 if (GET_CODE (n) == PARALLEL) 2077 n = XVECEXP (n, 0, 0); 2078 } 2079 dwarf2out_frame_debug_adjust_cfa (n); 2080 handled_one = true; 2081 break; 2082 2083 case REG_CFA_OFFSET: 2084 n = XEXP (note, 0); 2085 if (n == NULL) 2086 n = single_set (insn); 2087 dwarf2out_frame_debug_cfa_offset (n); 2088 handled_one = true; 2089 break; 2090 2091 case REG_CFA_REGISTER: 2092 n = XEXP (note, 0); 2093 if (n == NULL) 2094 { 2095 n = PATTERN (insn); 2096 if (GET_CODE (n) == PARALLEL) 2097 n = XVECEXP (n, 0, 0); 2098 } 2099 dwarf2out_frame_debug_cfa_register (n); 2100 handled_one = true; 2101 break; 2102 2103 case REG_CFA_EXPRESSION: 2104 case REG_CFA_VAL_EXPRESSION: 2105 n = XEXP (note, 0); 2106 if (n == NULL) 2107 n = single_set (insn); 2108 2109 if (REG_NOTE_KIND (note) == REG_CFA_EXPRESSION) 2110 dwarf2out_frame_debug_cfa_expression (n); 2111 else 2112 dwarf2out_frame_debug_cfa_val_expression (n); 2113 2114 handled_one = true; 2115 break; 2116 2117 case REG_CFA_RESTORE: 2118 n = XEXP (note, 0); 2119 if (n == NULL) 2120 { 2121 n = PATTERN (insn); 2122 if (GET_CODE (n) == PARALLEL) 2123 n = XVECEXP (n, 0, 0); 2124 n = XEXP (n, 0); 2125 } 2126 dwarf2out_frame_debug_cfa_restore (n); 2127 handled_one = true; 2128 break; 2129 2130 case REG_CFA_SET_VDRAP: 2131 n = XEXP (note, 0); 2132 if (REG_P (n)) 2133 { 2134 dw_fde_ref fde = cfun->fde; 2135 if (fde) 2136 { 2137 gcc_assert (fde->vdrap_reg == INVALID_REGNUM); 2138 if (REG_P (n)) 2139 fde->vdrap_reg = dwf_regno (n); 2140 } 2141 } 2142 handled_one = true; 2143 break; 2144 2145 case REG_CFA_TOGGLE_RA_MANGLE: 2146 /* This uses the same DWARF opcode as the next operation. */ 2147 dwarf2out_frame_debug_cfa_window_save (true); 2148 handled_one = true; 2149 break; 2150 2151 case REG_CFA_WINDOW_SAVE: 2152 dwarf2out_frame_debug_cfa_window_save (false); 2153 handled_one = true; 2154 break; 2155 2156 case REG_CFA_FLUSH_QUEUE: 2157 /* The actual flush happens elsewhere. */ 2158 handled_one = true; 2159 break; 2160 2161 default: 2162 break; 2163 } 2164 2165 if (!handled_one) 2166 { 2167 pat = PATTERN (insn); 2168 do_frame_expr: 2169 dwarf2out_frame_debug_expr (pat); 2170 2171 /* Check again. A parallel can save and update the same register. 2172 We could probably check just once, here, but this is safer than 2173 removing the check at the start of the function. */ 2174 if (clobbers_queued_reg_save (pat)) 2175 dwarf2out_flush_queued_reg_saves (); 2176 } 2177 } 2178 2179 /* Emit CFI info to change the state from OLD_ROW to NEW_ROW. */ 2180 2181 static void 2182 change_cfi_row (dw_cfi_row *old_row, dw_cfi_row *new_row) 2183 { 2184 size_t i, n_old, n_new, n_max; 2185 dw_cfi_ref cfi; 2186 2187 if (new_row->cfa_cfi && !cfi_equal_p (old_row->cfa_cfi, new_row->cfa_cfi)) 2188 add_cfi (new_row->cfa_cfi); 2189 else 2190 { 2191 cfi = def_cfa_0 (&old_row->cfa, &new_row->cfa); 2192 if (cfi) 2193 add_cfi (cfi); 2194 } 2195 2196 n_old = vec_safe_length (old_row->reg_save); 2197 n_new = vec_safe_length (new_row->reg_save); 2198 n_max = MAX (n_old, n_new); 2199 2200 for (i = 0; i < n_max; ++i) 2201 { 2202 dw_cfi_ref r_old = NULL, r_new = NULL; 2203 2204 if (i < n_old) 2205 r_old = (*old_row->reg_save)[i]; 2206 if (i < n_new) 2207 r_new = (*new_row->reg_save)[i]; 2208 2209 if (r_old == r_new) 2210 ; 2211 else if (r_new == NULL) 2212 add_cfi_restore (i); 2213 else if (!cfi_equal_p (r_old, r_new)) 2214 add_cfi (r_new); 2215 } 2216 2217 if (!old_row->window_save && new_row->window_save) 2218 { 2219 dw_cfi_ref cfi = new_cfi (); 2220 2221 cfi->dw_cfi_opc = DW_CFA_GNU_window_save; 2222 add_cfi (cfi); 2223 } 2224 } 2225 2226 /* Examine CFI and return true if a cfi label and set_loc is needed 2227 beforehand. Even when generating CFI assembler instructions, we 2228 still have to add the cfi to the list so that lookup_cfa_1 works 2229 later on. When -g2 and above we even need to force emitting of 2230 CFI labels and add to list a DW_CFA_set_loc for convert_cfa_to_fb_loc_list 2231 purposes. If we're generating DWARF3 output we use DW_OP_call_frame_cfa 2232 and so don't use convert_cfa_to_fb_loc_list. */ 2233 2234 static bool 2235 cfi_label_required_p (dw_cfi_ref cfi) 2236 { 2237 if (!dwarf2out_do_cfi_asm ()) 2238 return true; 2239 2240 if (dwarf_version == 2 2241 && debug_info_level > DINFO_LEVEL_TERSE 2242 && (write_symbols == DWARF2_DEBUG 2243 || write_symbols == VMS_AND_DWARF2_DEBUG)) 2244 { 2245 switch (cfi->dw_cfi_opc) 2246 { 2247 case DW_CFA_def_cfa_offset: 2248 case DW_CFA_def_cfa_offset_sf: 2249 case DW_CFA_def_cfa_register: 2250 case DW_CFA_def_cfa: 2251 case DW_CFA_def_cfa_sf: 2252 case DW_CFA_def_cfa_expression: 2253 case DW_CFA_restore_state: 2254 return true; 2255 default: 2256 return false; 2257 } 2258 } 2259 return false; 2260 } 2261 2262 /* Walk the function, looking for NOTE_INSN_CFI notes. Add the CFIs to the 2263 function's FDE, adding CFI labels and set_loc/advance_loc opcodes as 2264 necessary. */ 2265 static void 2266 add_cfis_to_fde (void) 2267 { 2268 dw_fde_ref fde = cfun->fde; 2269 rtx_insn *insn, *next; 2270 2271 for (insn = get_insns (); insn; insn = next) 2272 { 2273 next = NEXT_INSN (insn); 2274 2275 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) 2276 fde->dw_fde_switch_cfi_index = vec_safe_length (fde->dw_fde_cfi); 2277 2278 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI) 2279 { 2280 bool required = cfi_label_required_p (NOTE_CFI (insn)); 2281 while (next) 2282 if (NOTE_P (next) && NOTE_KIND (next) == NOTE_INSN_CFI) 2283 { 2284 required |= cfi_label_required_p (NOTE_CFI (next)); 2285 next = NEXT_INSN (next); 2286 } 2287 else if (active_insn_p (next) 2288 || (NOTE_P (next) && (NOTE_KIND (next) 2289 == NOTE_INSN_SWITCH_TEXT_SECTIONS))) 2290 break; 2291 else 2292 next = NEXT_INSN (next); 2293 if (required) 2294 { 2295 int num = dwarf2out_cfi_label_num; 2296 const char *label = dwarf2out_cfi_label (); 2297 dw_cfi_ref xcfi; 2298 2299 /* Set the location counter to the new label. */ 2300 xcfi = new_cfi (); 2301 xcfi->dw_cfi_opc = DW_CFA_advance_loc4; 2302 xcfi->dw_cfi_oprnd1.dw_cfi_addr = label; 2303 vec_safe_push (fde->dw_fde_cfi, xcfi); 2304 2305 rtx_note *tmp = emit_note_before (NOTE_INSN_CFI_LABEL, insn); 2306 NOTE_LABEL_NUMBER (tmp) = num; 2307 } 2308 2309 do 2310 { 2311 if (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_CFI) 2312 vec_safe_push (fde->dw_fde_cfi, NOTE_CFI (insn)); 2313 insn = NEXT_INSN (insn); 2314 } 2315 while (insn != next); 2316 } 2317 } 2318 } 2319 2320 static void dump_cfi_row (FILE *f, dw_cfi_row *row); 2321 2322 /* If LABEL is the start of a trace, then initialize the state of that 2323 trace from CUR_TRACE and CUR_ROW. */ 2324 2325 static void 2326 maybe_record_trace_start (rtx_insn *start, rtx_insn *origin) 2327 { 2328 dw_trace_info *ti; 2329 2330 ti = get_trace_info (start); 2331 gcc_assert (ti != NULL); 2332 2333 if (dump_file) 2334 { 2335 fprintf (dump_file, " saw edge from trace %u to %u (via %s %d)\n", 2336 cur_trace->id, ti->id, 2337 (origin ? rtx_name[(int) GET_CODE (origin)] : "fallthru"), 2338 (origin ? INSN_UID (origin) : 0)); 2339 } 2340 2341 poly_int64 args_size = cur_trace->end_true_args_size; 2342 if (ti->beg_row == NULL) 2343 { 2344 /* This is the first time we've encountered this trace. Propagate 2345 state across the edge and push the trace onto the work list. */ 2346 ti->beg_row = copy_cfi_row (cur_row); 2347 ti->beg_true_args_size = args_size; 2348 2349 ti->cfa_store = cur_trace->cfa_store; 2350 ti->cfa_temp = cur_trace->cfa_temp; 2351 ti->regs_saved_in_regs = cur_trace->regs_saved_in_regs.copy (); 2352 2353 trace_work_list.safe_push (ti); 2354 2355 if (dump_file) 2356 fprintf (dump_file, "\tpush trace %u to worklist\n", ti->id); 2357 } 2358 else 2359 { 2360 2361 /* We ought to have the same state incoming to a given trace no 2362 matter how we arrive at the trace. Anything else means we've 2363 got some kind of optimization error. */ 2364 #if CHECKING_P 2365 if (!cfi_row_equal_p (cur_row, ti->beg_row)) 2366 { 2367 if (dump_file) 2368 { 2369 fprintf (dump_file, "Inconsistent CFI state!\n"); 2370 fprintf (dump_file, "SHOULD have:\n"); 2371 dump_cfi_row (dump_file, ti->beg_row); 2372 fprintf (dump_file, "DO have:\n"); 2373 dump_cfi_row (dump_file, cur_row); 2374 } 2375 2376 gcc_unreachable (); 2377 } 2378 #endif 2379 2380 /* The args_size is allowed to conflict if it isn't actually used. */ 2381 if (maybe_ne (ti->beg_true_args_size, args_size)) 2382 ti->args_size_undefined = true; 2383 } 2384 } 2385 2386 /* Similarly, but handle the args_size and CFA reset across EH 2387 and non-local goto edges. */ 2388 2389 static void 2390 maybe_record_trace_start_abnormal (rtx_insn *start, rtx_insn *origin) 2391 { 2392 poly_int64 save_args_size, delta; 2393 dw_cfa_location save_cfa; 2394 2395 save_args_size = cur_trace->end_true_args_size; 2396 if (known_eq (save_args_size, 0)) 2397 { 2398 maybe_record_trace_start (start, origin); 2399 return; 2400 } 2401 2402 delta = -save_args_size; 2403 cur_trace->end_true_args_size = 0; 2404 2405 save_cfa = cur_row->cfa; 2406 if (cur_row->cfa.reg == dw_stack_pointer_regnum) 2407 { 2408 /* Convert a change in args_size (always a positive in the 2409 direction of stack growth) to a change in stack pointer. */ 2410 if (!STACK_GROWS_DOWNWARD) 2411 delta = -delta; 2412 2413 cur_row->cfa.offset += delta; 2414 } 2415 2416 maybe_record_trace_start (start, origin); 2417 2418 cur_trace->end_true_args_size = save_args_size; 2419 cur_row->cfa = save_cfa; 2420 } 2421 2422 /* Propagate CUR_TRACE state to the destinations implied by INSN. */ 2423 /* ??? Sadly, this is in large part a duplicate of make_edges. */ 2424 2425 static void 2426 create_trace_edges (rtx_insn *insn) 2427 { 2428 rtx tmp; 2429 int i, n; 2430 2431 if (JUMP_P (insn)) 2432 { 2433 rtx_jump_table_data *table; 2434 2435 if (find_reg_note (insn, REG_NON_LOCAL_GOTO, NULL_RTX)) 2436 return; 2437 2438 if (tablejump_p (insn, NULL, &table)) 2439 { 2440 rtvec vec = table->get_labels (); 2441 2442 n = GET_NUM_ELEM (vec); 2443 for (i = 0; i < n; ++i) 2444 { 2445 rtx_insn *lab = as_a <rtx_insn *> (XEXP (RTVEC_ELT (vec, i), 0)); 2446 maybe_record_trace_start (lab, insn); 2447 } 2448 } 2449 else if (computed_jump_p (insn)) 2450 { 2451 rtx_insn *temp; 2452 unsigned int i; 2453 FOR_EACH_VEC_SAFE_ELT (forced_labels, i, temp) 2454 maybe_record_trace_start (temp, insn); 2455 } 2456 else if (returnjump_p (insn)) 2457 ; 2458 else if ((tmp = extract_asm_operands (PATTERN (insn))) != NULL) 2459 { 2460 n = ASM_OPERANDS_LABEL_LENGTH (tmp); 2461 for (i = 0; i < n; ++i) 2462 { 2463 rtx_insn *lab = 2464 as_a <rtx_insn *> (XEXP (ASM_OPERANDS_LABEL (tmp, i), 0)); 2465 maybe_record_trace_start (lab, insn); 2466 } 2467 } 2468 else 2469 { 2470 rtx_insn *lab = JUMP_LABEL_AS_INSN (insn); 2471 gcc_assert (lab != NULL); 2472 maybe_record_trace_start (lab, insn); 2473 } 2474 } 2475 else if (CALL_P (insn)) 2476 { 2477 /* Sibling calls don't have edges inside this function. */ 2478 if (SIBLING_CALL_P (insn)) 2479 return; 2480 2481 /* Process non-local goto edges. */ 2482 if (can_nonlocal_goto (insn)) 2483 for (rtx_insn_list *lab = nonlocal_goto_handler_labels; 2484 lab; 2485 lab = lab->next ()) 2486 maybe_record_trace_start_abnormal (lab->insn (), insn); 2487 } 2488 else if (rtx_sequence *seq = dyn_cast <rtx_sequence *> (PATTERN (insn))) 2489 { 2490 int i, n = seq->len (); 2491 for (i = 0; i < n; ++i) 2492 create_trace_edges (seq->insn (i)); 2493 return; 2494 } 2495 2496 /* Process EH edges. */ 2497 if (CALL_P (insn) || cfun->can_throw_non_call_exceptions) 2498 { 2499 eh_landing_pad lp = get_eh_landing_pad_from_rtx (insn); 2500 if (lp) 2501 maybe_record_trace_start_abnormal (lp->landing_pad, insn); 2502 } 2503 } 2504 2505 /* A subroutine of scan_trace. Do what needs to be done "after" INSN. */ 2506 2507 static void 2508 scan_insn_after (rtx_insn *insn) 2509 { 2510 if (RTX_FRAME_RELATED_P (insn)) 2511 dwarf2out_frame_debug (insn); 2512 notice_args_size (insn); 2513 } 2514 2515 /* Scan the trace beginning at INSN and create the CFI notes for the 2516 instructions therein. */ 2517 2518 static void 2519 scan_trace (dw_trace_info *trace, bool entry) 2520 { 2521 rtx_insn *prev, *insn = trace->head; 2522 dw_cfa_location this_cfa; 2523 2524 if (dump_file) 2525 fprintf (dump_file, "Processing trace %u : start at %s %d\n", 2526 trace->id, rtx_name[(int) GET_CODE (insn)], 2527 INSN_UID (insn)); 2528 2529 trace->end_row = copy_cfi_row (trace->beg_row); 2530 trace->end_true_args_size = trace->beg_true_args_size; 2531 2532 cur_trace = trace; 2533 cur_row = trace->end_row; 2534 2535 this_cfa = cur_row->cfa; 2536 cur_cfa = &this_cfa; 2537 2538 /* If the current function starts with a non-standard incoming frame 2539 sp offset, emit a note before the first instruction. */ 2540 if (entry 2541 && DEFAULT_INCOMING_FRAME_SP_OFFSET != INCOMING_FRAME_SP_OFFSET) 2542 { 2543 add_cfi_insn = insn; 2544 gcc_assert (NOTE_P (insn) && NOTE_KIND (insn) == NOTE_INSN_DELETED); 2545 this_cfa.offset = INCOMING_FRAME_SP_OFFSET; 2546 def_cfa_1 (&this_cfa); 2547 } 2548 2549 for (prev = insn, insn = NEXT_INSN (insn); 2550 insn; 2551 prev = insn, insn = NEXT_INSN (insn)) 2552 { 2553 rtx_insn *control; 2554 2555 /* Do everything that happens "before" the insn. */ 2556 add_cfi_insn = prev; 2557 2558 /* Notice the end of a trace. */ 2559 if (BARRIER_P (insn)) 2560 { 2561 /* Don't bother saving the unneeded queued registers at all. */ 2562 queued_reg_saves.truncate (0); 2563 break; 2564 } 2565 if (save_point_p (insn)) 2566 { 2567 /* Propagate across fallthru edges. */ 2568 dwarf2out_flush_queued_reg_saves (); 2569 maybe_record_trace_start (insn, NULL); 2570 break; 2571 } 2572 2573 if (DEBUG_INSN_P (insn) || !inside_basic_block_p (insn)) 2574 continue; 2575 2576 /* Handle all changes to the row state. Sequences require special 2577 handling for the positioning of the notes. */ 2578 if (rtx_sequence *pat = dyn_cast <rtx_sequence *> (PATTERN (insn))) 2579 { 2580 rtx_insn *elt; 2581 int i, n = pat->len (); 2582 2583 control = pat->insn (0); 2584 if (can_throw_internal (control)) 2585 notice_eh_throw (control); 2586 dwarf2out_flush_queued_reg_saves (); 2587 2588 if (JUMP_P (control) && INSN_ANNULLED_BRANCH_P (control)) 2589 { 2590 /* ??? Hopefully multiple delay slots are not annulled. */ 2591 gcc_assert (n == 2); 2592 gcc_assert (!RTX_FRAME_RELATED_P (control)); 2593 gcc_assert (!find_reg_note (control, REG_ARGS_SIZE, NULL)); 2594 2595 elt = pat->insn (1); 2596 2597 if (INSN_FROM_TARGET_P (elt)) 2598 { 2599 cfi_vec save_row_reg_save; 2600 2601 /* If ELT is an instruction from target of an annulled 2602 branch, the effects are for the target only and so 2603 the args_size and CFA along the current path 2604 shouldn't change. */ 2605 add_cfi_insn = NULL; 2606 poly_int64 restore_args_size = cur_trace->end_true_args_size; 2607 cur_cfa = &cur_row->cfa; 2608 save_row_reg_save = vec_safe_copy (cur_row->reg_save); 2609 2610 scan_insn_after (elt); 2611 2612 /* ??? Should we instead save the entire row state? */ 2613 gcc_assert (!queued_reg_saves.length ()); 2614 2615 create_trace_edges (control); 2616 2617 cur_trace->end_true_args_size = restore_args_size; 2618 cur_row->cfa = this_cfa; 2619 cur_row->reg_save = save_row_reg_save; 2620 cur_cfa = &this_cfa; 2621 } 2622 else 2623 { 2624 /* If ELT is a annulled branch-taken instruction (i.e. 2625 executed only when branch is not taken), the args_size 2626 and CFA should not change through the jump. */ 2627 create_trace_edges (control); 2628 2629 /* Update and continue with the trace. */ 2630 add_cfi_insn = insn; 2631 scan_insn_after (elt); 2632 def_cfa_1 (&this_cfa); 2633 } 2634 continue; 2635 } 2636 2637 /* The insns in the delay slot should all be considered to happen 2638 "before" a call insn. Consider a call with a stack pointer 2639 adjustment in the delay slot. The backtrace from the callee 2640 should include the sp adjustment. Unfortunately, that leaves 2641 us with an unavoidable unwinding error exactly at the call insn 2642 itself. For jump insns we'd prefer to avoid this error by 2643 placing the notes after the sequence. */ 2644 if (JUMP_P (control)) 2645 add_cfi_insn = insn; 2646 2647 for (i = 1; i < n; ++i) 2648 { 2649 elt = pat->insn (i); 2650 scan_insn_after (elt); 2651 } 2652 2653 /* Make sure any register saves are visible at the jump target. */ 2654 dwarf2out_flush_queued_reg_saves (); 2655 any_cfis_emitted = false; 2656 2657 /* However, if there is some adjustment on the call itself, e.g. 2658 a call_pop, that action should be considered to happen after 2659 the call returns. */ 2660 add_cfi_insn = insn; 2661 scan_insn_after (control); 2662 } 2663 else 2664 { 2665 /* Flush data before calls and jumps, and of course if necessary. */ 2666 if (can_throw_internal (insn)) 2667 { 2668 notice_eh_throw (insn); 2669 dwarf2out_flush_queued_reg_saves (); 2670 } 2671 else if (!NONJUMP_INSN_P (insn) 2672 || clobbers_queued_reg_save (insn) 2673 || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)) 2674 dwarf2out_flush_queued_reg_saves (); 2675 any_cfis_emitted = false; 2676 2677 add_cfi_insn = insn; 2678 scan_insn_after (insn); 2679 control = insn; 2680 } 2681 2682 /* Between frame-related-p and args_size we might have otherwise 2683 emitted two cfa adjustments. Do it now. */ 2684 def_cfa_1 (&this_cfa); 2685 2686 /* Minimize the number of advances by emitting the entire queue 2687 once anything is emitted. */ 2688 if (any_cfis_emitted 2689 || find_reg_note (insn, REG_CFA_FLUSH_QUEUE, NULL)) 2690 dwarf2out_flush_queued_reg_saves (); 2691 2692 /* Note that a test for control_flow_insn_p does exactly the 2693 same tests as are done to actually create the edges. So 2694 always call the routine and let it not create edges for 2695 non-control-flow insns. */ 2696 create_trace_edges (control); 2697 } 2698 2699 add_cfi_insn = NULL; 2700 cur_row = NULL; 2701 cur_trace = NULL; 2702 cur_cfa = NULL; 2703 } 2704 2705 /* Scan the function and create the initial set of CFI notes. */ 2706 2707 static void 2708 create_cfi_notes (void) 2709 { 2710 dw_trace_info *ti; 2711 2712 gcc_checking_assert (!queued_reg_saves.exists ()); 2713 gcc_checking_assert (!trace_work_list.exists ()); 2714 2715 /* Always begin at the entry trace. */ 2716 ti = &trace_info[0]; 2717 scan_trace (ti, true); 2718 2719 while (!trace_work_list.is_empty ()) 2720 { 2721 ti = trace_work_list.pop (); 2722 scan_trace (ti, false); 2723 } 2724 2725 queued_reg_saves.release (); 2726 trace_work_list.release (); 2727 } 2728 2729 /* Return the insn before the first NOTE_INSN_CFI after START. */ 2730 2731 static rtx_insn * 2732 before_next_cfi_note (rtx_insn *start) 2733 { 2734 rtx_insn *prev = start; 2735 while (start) 2736 { 2737 if (NOTE_P (start) && NOTE_KIND (start) == NOTE_INSN_CFI) 2738 return prev; 2739 prev = start; 2740 start = NEXT_INSN (start); 2741 } 2742 gcc_unreachable (); 2743 } 2744 2745 /* Insert CFI notes between traces to properly change state between them. */ 2746 2747 static void 2748 connect_traces (void) 2749 { 2750 unsigned i, n; 2751 dw_trace_info *prev_ti, *ti; 2752 2753 /* ??? Ideally, we should have both queued and processed every trace. 2754 However the current representation of constant pools on various targets 2755 is indistinguishable from unreachable code. Assume for the moment that 2756 we can simply skip over such traces. */ 2757 /* ??? Consider creating a DATA_INSN rtx code to indicate that 2758 these are not "real" instructions, and should not be considered. 2759 This could be generically useful for tablejump data as well. */ 2760 /* Remove all unprocessed traces from the list. */ 2761 unsigned ix, ix2; 2762 VEC_ORDERED_REMOVE_IF_FROM_TO (trace_info, ix, ix2, ti, 1, 2763 trace_info.length (), ti->beg_row == NULL); 2764 FOR_EACH_VEC_ELT (trace_info, ix, ti) 2765 gcc_assert (ti->end_row != NULL); 2766 2767 /* Work from the end back to the beginning. This lets us easily insert 2768 remember/restore_state notes in the correct order wrt other notes. */ 2769 n = trace_info.length (); 2770 prev_ti = &trace_info[n - 1]; 2771 for (i = n - 1; i > 0; --i) 2772 { 2773 dw_cfi_row *old_row; 2774 2775 ti = prev_ti; 2776 prev_ti = &trace_info[i - 1]; 2777 2778 add_cfi_insn = ti->head; 2779 2780 /* In dwarf2out_switch_text_section, we'll begin a new FDE 2781 for the portion of the function in the alternate text 2782 section. The row state at the very beginning of that 2783 new FDE will be exactly the row state from the CIE. */ 2784 if (ti->switch_sections) 2785 old_row = cie_cfi_row; 2786 else 2787 { 2788 old_row = prev_ti->end_row; 2789 /* If there's no change from the previous end state, fine. */ 2790 if (cfi_row_equal_p (old_row, ti->beg_row)) 2791 ; 2792 /* Otherwise check for the common case of sharing state with 2793 the beginning of an epilogue, but not the end. Insert 2794 remember/restore opcodes in that case. */ 2795 else if (cfi_row_equal_p (prev_ti->beg_row, ti->beg_row)) 2796 { 2797 dw_cfi_ref cfi; 2798 2799 /* Note that if we blindly insert the remember at the 2800 start of the trace, we can wind up increasing the 2801 size of the unwind info due to extra advance opcodes. 2802 Instead, put the remember immediately before the next 2803 state change. We know there must be one, because the 2804 state at the beginning and head of the trace differ. */ 2805 add_cfi_insn = before_next_cfi_note (prev_ti->head); 2806 cfi = new_cfi (); 2807 cfi->dw_cfi_opc = DW_CFA_remember_state; 2808 add_cfi (cfi); 2809 2810 add_cfi_insn = ti->head; 2811 cfi = new_cfi (); 2812 cfi->dw_cfi_opc = DW_CFA_restore_state; 2813 add_cfi (cfi); 2814 2815 old_row = prev_ti->beg_row; 2816 } 2817 /* Otherwise, we'll simply change state from the previous end. */ 2818 } 2819 2820 change_cfi_row (old_row, ti->beg_row); 2821 2822 if (dump_file && add_cfi_insn != ti->head) 2823 { 2824 rtx_insn *note; 2825 2826 fprintf (dump_file, "Fixup between trace %u and %u:\n", 2827 prev_ti->id, ti->id); 2828 2829 note = ti->head; 2830 do 2831 { 2832 note = NEXT_INSN (note); 2833 gcc_assert (NOTE_P (note) && NOTE_KIND (note) == NOTE_INSN_CFI); 2834 output_cfi_directive (dump_file, NOTE_CFI (note)); 2835 } 2836 while (note != add_cfi_insn); 2837 } 2838 } 2839 2840 /* Connect args_size between traces that have can_throw_internal insns. */ 2841 if (cfun->eh->lp_array) 2842 { 2843 poly_int64 prev_args_size = 0; 2844 2845 for (i = 0; i < n; ++i) 2846 { 2847 ti = &trace_info[i]; 2848 2849 if (ti->switch_sections) 2850 prev_args_size = 0; 2851 2852 if (ti->eh_head == NULL) 2853 continue; 2854 2855 /* We require either the incoming args_size values to match or the 2856 presence of an insn setting it before the first EH insn. */ 2857 gcc_assert (!ti->args_size_undefined || ti->args_size_defined_for_eh); 2858 2859 /* In the latter case, we force the creation of a CFI note. */ 2860 if (ti->args_size_undefined 2861 || maybe_ne (ti->beg_delay_args_size, prev_args_size)) 2862 { 2863 /* ??? Search back to previous CFI note. */ 2864 add_cfi_insn = PREV_INSN (ti->eh_head); 2865 add_cfi_args_size (ti->beg_delay_args_size); 2866 } 2867 2868 prev_args_size = ti->end_delay_args_size; 2869 } 2870 } 2871 } 2872 2873 /* Set up the pseudo-cfg of instruction traces, as described at the 2874 block comment at the top of the file. */ 2875 2876 static void 2877 create_pseudo_cfg (void) 2878 { 2879 bool saw_barrier, switch_sections; 2880 dw_trace_info ti; 2881 rtx_insn *insn; 2882 unsigned i; 2883 2884 /* The first trace begins at the start of the function, 2885 and begins with the CIE row state. */ 2886 trace_info.create (16); 2887 memset (&ti, 0, sizeof (ti)); 2888 ti.head = get_insns (); 2889 ti.beg_row = cie_cfi_row; 2890 ti.cfa_store = cie_cfi_row->cfa; 2891 ti.cfa_temp.reg = INVALID_REGNUM; 2892 trace_info.quick_push (ti); 2893 2894 if (cie_return_save) 2895 ti.regs_saved_in_regs.safe_push (*cie_return_save); 2896 2897 /* Walk all the insns, collecting start of trace locations. */ 2898 saw_barrier = false; 2899 switch_sections = false; 2900 for (insn = get_insns (); insn; insn = NEXT_INSN (insn)) 2901 { 2902 if (BARRIER_P (insn)) 2903 saw_barrier = true; 2904 else if (NOTE_P (insn) 2905 && NOTE_KIND (insn) == NOTE_INSN_SWITCH_TEXT_SECTIONS) 2906 { 2907 /* We should have just seen a barrier. */ 2908 gcc_assert (saw_barrier); 2909 switch_sections = true; 2910 } 2911 /* Watch out for save_point notes between basic blocks. 2912 In particular, a note after a barrier. Do not record these, 2913 delaying trace creation until the label. */ 2914 else if (save_point_p (insn) 2915 && (LABEL_P (insn) || !saw_barrier)) 2916 { 2917 memset (&ti, 0, sizeof (ti)); 2918 ti.head = insn; 2919 ti.switch_sections = switch_sections; 2920 ti.id = trace_info.length (); 2921 trace_info.safe_push (ti); 2922 2923 saw_barrier = false; 2924 switch_sections = false; 2925 } 2926 } 2927 2928 /* Create the trace index after we've finished building trace_info, 2929 avoiding stale pointer problems due to reallocation. */ 2930 trace_index 2931 = new hash_table<trace_info_hasher> (trace_info.length ()); 2932 dw_trace_info *tp; 2933 FOR_EACH_VEC_ELT (trace_info, i, tp) 2934 { 2935 dw_trace_info **slot; 2936 2937 if (dump_file) 2938 fprintf (dump_file, "Creating trace %u : start at %s %d%s\n", tp->id, 2939 rtx_name[(int) GET_CODE (tp->head)], INSN_UID (tp->head), 2940 tp->switch_sections ? " (section switch)" : ""); 2941 2942 slot = trace_index->find_slot_with_hash (tp, INSN_UID (tp->head), INSERT); 2943 gcc_assert (*slot == NULL); 2944 *slot = tp; 2945 } 2946 } 2947 2948 /* Record the initial position of the return address. RTL is 2949 INCOMING_RETURN_ADDR_RTX. */ 2950 2951 static void 2952 initial_return_save (rtx rtl) 2953 { 2954 unsigned int reg = INVALID_REGNUM; 2955 poly_int64 offset = 0; 2956 2957 switch (GET_CODE (rtl)) 2958 { 2959 case REG: 2960 /* RA is in a register. */ 2961 reg = dwf_regno (rtl); 2962 break; 2963 2964 case MEM: 2965 /* RA is on the stack. */ 2966 rtl = XEXP (rtl, 0); 2967 switch (GET_CODE (rtl)) 2968 { 2969 case REG: 2970 gcc_assert (REGNO (rtl) == STACK_POINTER_REGNUM); 2971 offset = 0; 2972 break; 2973 2974 case PLUS: 2975 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); 2976 offset = rtx_to_poly_int64 (XEXP (rtl, 1)); 2977 break; 2978 2979 case MINUS: 2980 gcc_assert (REGNO (XEXP (rtl, 0)) == STACK_POINTER_REGNUM); 2981 offset = -rtx_to_poly_int64 (XEXP (rtl, 1)); 2982 break; 2983 2984 default: 2985 gcc_unreachable (); 2986 } 2987 2988 break; 2989 2990 case PLUS: 2991 /* The return address is at some offset from any value we can 2992 actually load. For instance, on the SPARC it is in %i7+8. Just 2993 ignore the offset for now; it doesn't matter for unwinding frames. */ 2994 gcc_assert (CONST_INT_P (XEXP (rtl, 1))); 2995 initial_return_save (XEXP (rtl, 0)); 2996 return; 2997 2998 default: 2999 gcc_unreachable (); 3000 } 3001 3002 if (reg != DWARF_FRAME_RETURN_COLUMN) 3003 { 3004 if (reg != INVALID_REGNUM) 3005 record_reg_saved_in_reg (rtl, pc_rtx); 3006 reg_save (DWARF_FRAME_RETURN_COLUMN, reg, offset - cur_row->cfa.offset); 3007 } 3008 } 3009 3010 static void 3011 create_cie_data (void) 3012 { 3013 dw_cfa_location loc; 3014 dw_trace_info cie_trace; 3015 3016 dw_stack_pointer_regnum = DWARF_FRAME_REGNUM (STACK_POINTER_REGNUM); 3017 3018 memset (&cie_trace, 0, sizeof (cie_trace)); 3019 cur_trace = &cie_trace; 3020 3021 add_cfi_vec = &cie_cfi_vec; 3022 cie_cfi_row = cur_row = new_cfi_row (); 3023 3024 /* On entry, the Canonical Frame Address is at SP. */ 3025 memset (&loc, 0, sizeof (loc)); 3026 loc.reg = dw_stack_pointer_regnum; 3027 /* create_cie_data is called just once per TU, and when using .cfi_startproc 3028 is even done by the assembler rather than the compiler. If the target 3029 has different incoming frame sp offsets depending on what kind of 3030 function it is, use a single constant offset for the target and 3031 if needed, adjust before the first instruction in insn stream. */ 3032 loc.offset = DEFAULT_INCOMING_FRAME_SP_OFFSET; 3033 def_cfa_1 (&loc); 3034 3035 if (targetm.debug_unwind_info () == UI_DWARF2 3036 || targetm_common.except_unwind_info (&global_options) == UI_DWARF2) 3037 { 3038 initial_return_save (INCOMING_RETURN_ADDR_RTX); 3039 3040 /* For a few targets, we have the return address incoming into a 3041 register, but choose a different return column. This will result 3042 in a DW_CFA_register for the return, and an entry in 3043 regs_saved_in_regs to match. If the target later stores that 3044 return address register to the stack, we want to be able to emit 3045 the DW_CFA_offset against the return column, not the intermediate 3046 save register. Save the contents of regs_saved_in_regs so that 3047 we can re-initialize it at the start of each function. */ 3048 switch (cie_trace.regs_saved_in_regs.length ()) 3049 { 3050 case 0: 3051 break; 3052 case 1: 3053 cie_return_save = ggc_alloc<reg_saved_in_data> (); 3054 *cie_return_save = cie_trace.regs_saved_in_regs[0]; 3055 cie_trace.regs_saved_in_regs.release (); 3056 break; 3057 default: 3058 gcc_unreachable (); 3059 } 3060 } 3061 3062 add_cfi_vec = NULL; 3063 cur_row = NULL; 3064 cur_trace = NULL; 3065 } 3066 3067 /* Annotate the function with NOTE_INSN_CFI notes to record the CFI 3068 state at each location within the function. These notes will be 3069 emitted during pass_final. */ 3070 3071 static unsigned int 3072 execute_dwarf2_frame (void) 3073 { 3074 /* Different HARD_FRAME_POINTER_REGNUM might coexist in the same file. */ 3075 dw_frame_pointer_regnum = DWARF_FRAME_REGNUM (HARD_FRAME_POINTER_REGNUM); 3076 3077 /* The first time we're called, compute the incoming frame state. */ 3078 if (cie_cfi_vec == NULL) 3079 create_cie_data (); 3080 3081 dwarf2out_alloc_current_fde (); 3082 3083 create_pseudo_cfg (); 3084 3085 /* Do the work. */ 3086 create_cfi_notes (); 3087 connect_traces (); 3088 add_cfis_to_fde (); 3089 3090 /* Free all the data we allocated. */ 3091 { 3092 size_t i; 3093 dw_trace_info *ti; 3094 3095 FOR_EACH_VEC_ELT (trace_info, i, ti) 3096 ti->regs_saved_in_regs.release (); 3097 } 3098 trace_info.release (); 3099 3100 delete trace_index; 3101 trace_index = NULL; 3102 3103 return 0; 3104 } 3105 3106 /* Convert a DWARF call frame info. operation to its string name */ 3107 3108 static const char * 3109 dwarf_cfi_name (unsigned int cfi_opc) 3110 { 3111 const char *name = get_DW_CFA_name (cfi_opc); 3112 3113 if (name != NULL) 3114 return name; 3115 3116 return "DW_CFA_<unknown>"; 3117 } 3118 3119 /* This routine will generate the correct assembly data for a location 3120 description based on a cfi entry with a complex address. */ 3121 3122 static void 3123 output_cfa_loc (dw_cfi_ref cfi, int for_eh) 3124 { 3125 dw_loc_descr_ref loc; 3126 unsigned long size; 3127 3128 if (cfi->dw_cfi_opc == DW_CFA_expression 3129 || cfi->dw_cfi_opc == DW_CFA_val_expression) 3130 { 3131 unsigned r = 3132 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); 3133 dw2_asm_output_data (1, r, NULL); 3134 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; 3135 } 3136 else 3137 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; 3138 3139 /* Output the size of the block. */ 3140 size = size_of_locs (loc); 3141 dw2_asm_output_data_uleb128 (size, NULL); 3142 3143 /* Now output the operations themselves. */ 3144 output_loc_sequence (loc, for_eh); 3145 } 3146 3147 /* Similar, but used for .cfi_escape. */ 3148 3149 static void 3150 output_cfa_loc_raw (dw_cfi_ref cfi) 3151 { 3152 dw_loc_descr_ref loc; 3153 unsigned long size; 3154 3155 if (cfi->dw_cfi_opc == DW_CFA_expression 3156 || cfi->dw_cfi_opc == DW_CFA_val_expression) 3157 { 3158 unsigned r = 3159 DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); 3160 fprintf (asm_out_file, "%#x,", r); 3161 loc = cfi->dw_cfi_oprnd2.dw_cfi_loc; 3162 } 3163 else 3164 loc = cfi->dw_cfi_oprnd1.dw_cfi_loc; 3165 3166 /* Output the size of the block. */ 3167 size = size_of_locs (loc); 3168 dw2_asm_output_data_uleb128_raw (size); 3169 fputc (',', asm_out_file); 3170 3171 /* Now output the operations themselves. */ 3172 output_loc_sequence_raw (loc); 3173 } 3174 3175 /* Output a Call Frame Information opcode and its operand(s). */ 3176 3177 void 3178 output_cfi (dw_cfi_ref cfi, dw_fde_ref fde, int for_eh) 3179 { 3180 unsigned long r; 3181 HOST_WIDE_INT off; 3182 3183 if (cfi->dw_cfi_opc == DW_CFA_advance_loc) 3184 dw2_asm_output_data (1, (cfi->dw_cfi_opc 3185 | (cfi->dw_cfi_oprnd1.dw_cfi_offset & 0x3f)), 3186 "DW_CFA_advance_loc " HOST_WIDE_INT_PRINT_HEX, 3187 ((unsigned HOST_WIDE_INT) 3188 cfi->dw_cfi_oprnd1.dw_cfi_offset)); 3189 else if (cfi->dw_cfi_opc == DW_CFA_offset) 3190 { 3191 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); 3192 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), 3193 "DW_CFA_offset, column %#lx", r); 3194 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); 3195 dw2_asm_output_data_uleb128 (off, NULL); 3196 } 3197 else if (cfi->dw_cfi_opc == DW_CFA_restore) 3198 { 3199 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); 3200 dw2_asm_output_data (1, (cfi->dw_cfi_opc | (r & 0x3f)), 3201 "DW_CFA_restore, column %#lx", r); 3202 } 3203 else 3204 { 3205 dw2_asm_output_data (1, cfi->dw_cfi_opc, 3206 "%s", dwarf_cfi_name (cfi->dw_cfi_opc)); 3207 3208 switch (cfi->dw_cfi_opc) 3209 { 3210 case DW_CFA_set_loc: 3211 if (for_eh) 3212 dw2_asm_output_encoded_addr_rtx ( 3213 ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/1, /*global=*/0), 3214 gen_rtx_SYMBOL_REF (Pmode, cfi->dw_cfi_oprnd1.dw_cfi_addr), 3215 false, NULL); 3216 else 3217 dw2_asm_output_addr (DWARF2_ADDR_SIZE, 3218 cfi->dw_cfi_oprnd1.dw_cfi_addr, NULL); 3219 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; 3220 break; 3221 3222 case DW_CFA_advance_loc1: 3223 dw2_asm_output_delta (1, cfi->dw_cfi_oprnd1.dw_cfi_addr, 3224 fde->dw_fde_current_label, NULL); 3225 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; 3226 break; 3227 3228 case DW_CFA_advance_loc2: 3229 dw2_asm_output_delta (2, cfi->dw_cfi_oprnd1.dw_cfi_addr, 3230 fde->dw_fde_current_label, NULL); 3231 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; 3232 break; 3233 3234 case DW_CFA_advance_loc4: 3235 dw2_asm_output_delta (4, cfi->dw_cfi_oprnd1.dw_cfi_addr, 3236 fde->dw_fde_current_label, NULL); 3237 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; 3238 break; 3239 3240 case DW_CFA_MIPS_advance_loc8: 3241 dw2_asm_output_delta (8, cfi->dw_cfi_oprnd1.dw_cfi_addr, 3242 fde->dw_fde_current_label, NULL); 3243 fde->dw_fde_current_label = cfi->dw_cfi_oprnd1.dw_cfi_addr; 3244 break; 3245 3246 case DW_CFA_offset_extended: 3247 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); 3248 dw2_asm_output_data_uleb128 (r, NULL); 3249 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); 3250 dw2_asm_output_data_uleb128 (off, NULL); 3251 break; 3252 3253 case DW_CFA_def_cfa: 3254 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); 3255 dw2_asm_output_data_uleb128 (r, NULL); 3256 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd2.dw_cfi_offset, NULL); 3257 break; 3258 3259 case DW_CFA_offset_extended_sf: 3260 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); 3261 dw2_asm_output_data_uleb128 (r, NULL); 3262 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); 3263 dw2_asm_output_data_sleb128 (off, NULL); 3264 break; 3265 3266 case DW_CFA_def_cfa_sf: 3267 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); 3268 dw2_asm_output_data_uleb128 (r, NULL); 3269 off = div_data_align (cfi->dw_cfi_oprnd2.dw_cfi_offset); 3270 dw2_asm_output_data_sleb128 (off, NULL); 3271 break; 3272 3273 case DW_CFA_restore_extended: 3274 case DW_CFA_undefined: 3275 case DW_CFA_same_value: 3276 case DW_CFA_def_cfa_register: 3277 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); 3278 dw2_asm_output_data_uleb128 (r, NULL); 3279 break; 3280 3281 case DW_CFA_register: 3282 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, for_eh); 3283 dw2_asm_output_data_uleb128 (r, NULL); 3284 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, for_eh); 3285 dw2_asm_output_data_uleb128 (r, NULL); 3286 break; 3287 3288 case DW_CFA_def_cfa_offset: 3289 case DW_CFA_GNU_args_size: 3290 dw2_asm_output_data_uleb128 (cfi->dw_cfi_oprnd1.dw_cfi_offset, NULL); 3291 break; 3292 3293 case DW_CFA_def_cfa_offset_sf: 3294 off = div_data_align (cfi->dw_cfi_oprnd1.dw_cfi_offset); 3295 dw2_asm_output_data_sleb128 (off, NULL); 3296 break; 3297 3298 case DW_CFA_GNU_window_save: 3299 break; 3300 3301 case DW_CFA_def_cfa_expression: 3302 case DW_CFA_expression: 3303 case DW_CFA_val_expression: 3304 output_cfa_loc (cfi, for_eh); 3305 break; 3306 3307 case DW_CFA_GNU_negative_offset_extended: 3308 /* Obsoleted by DW_CFA_offset_extended_sf. */ 3309 gcc_unreachable (); 3310 3311 default: 3312 break; 3313 } 3314 } 3315 } 3316 3317 /* Similar, but do it via assembler directives instead. */ 3318 3319 void 3320 output_cfi_directive (FILE *f, dw_cfi_ref cfi) 3321 { 3322 unsigned long r, r2; 3323 3324 switch (cfi->dw_cfi_opc) 3325 { 3326 case DW_CFA_advance_loc: 3327 case DW_CFA_advance_loc1: 3328 case DW_CFA_advance_loc2: 3329 case DW_CFA_advance_loc4: 3330 case DW_CFA_MIPS_advance_loc8: 3331 case DW_CFA_set_loc: 3332 /* Should only be created in a code path not followed when emitting 3333 via directives. The assembler is going to take care of this for 3334 us. But this routines is also used for debugging dumps, so 3335 print something. */ 3336 gcc_assert (f != asm_out_file); 3337 fprintf (f, "\t.cfi_advance_loc\n"); 3338 break; 3339 3340 case DW_CFA_offset: 3341 case DW_CFA_offset_extended: 3342 case DW_CFA_offset_extended_sf: 3343 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); 3344 fprintf (f, "\t.cfi_offset %lu, " HOST_WIDE_INT_PRINT_DEC"\n", 3345 r, cfi->dw_cfi_oprnd2.dw_cfi_offset); 3346 break; 3347 3348 case DW_CFA_restore: 3349 case DW_CFA_restore_extended: 3350 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); 3351 fprintf (f, "\t.cfi_restore %lu\n", r); 3352 break; 3353 3354 case DW_CFA_undefined: 3355 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); 3356 fprintf (f, "\t.cfi_undefined %lu\n", r); 3357 break; 3358 3359 case DW_CFA_same_value: 3360 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); 3361 fprintf (f, "\t.cfi_same_value %lu\n", r); 3362 break; 3363 3364 case DW_CFA_def_cfa: 3365 case DW_CFA_def_cfa_sf: 3366 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); 3367 fprintf (f, "\t.cfi_def_cfa %lu, " HOST_WIDE_INT_PRINT_DEC"\n", 3368 r, cfi->dw_cfi_oprnd2.dw_cfi_offset); 3369 break; 3370 3371 case DW_CFA_def_cfa_register: 3372 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); 3373 fprintf (f, "\t.cfi_def_cfa_register %lu\n", r); 3374 break; 3375 3376 case DW_CFA_register: 3377 r = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd1.dw_cfi_reg_num, 1); 3378 r2 = DWARF2_FRAME_REG_OUT (cfi->dw_cfi_oprnd2.dw_cfi_reg_num, 1); 3379 fprintf (f, "\t.cfi_register %lu, %lu\n", r, r2); 3380 break; 3381 3382 case DW_CFA_def_cfa_offset: 3383 case DW_CFA_def_cfa_offset_sf: 3384 fprintf (f, "\t.cfi_def_cfa_offset " 3385 HOST_WIDE_INT_PRINT_DEC"\n", 3386 cfi->dw_cfi_oprnd1.dw_cfi_offset); 3387 break; 3388 3389 case DW_CFA_remember_state: 3390 fprintf (f, "\t.cfi_remember_state\n"); 3391 break; 3392 case DW_CFA_restore_state: 3393 fprintf (f, "\t.cfi_restore_state\n"); 3394 break; 3395 3396 case DW_CFA_GNU_args_size: 3397 if (f == asm_out_file) 3398 { 3399 fprintf (f, "\t.cfi_escape %#x,", DW_CFA_GNU_args_size); 3400 dw2_asm_output_data_uleb128_raw (cfi->dw_cfi_oprnd1.dw_cfi_offset); 3401 if (flag_debug_asm) 3402 fprintf (f, "\t%s args_size " HOST_WIDE_INT_PRINT_DEC, 3403 ASM_COMMENT_START, cfi->dw_cfi_oprnd1.dw_cfi_offset); 3404 fputc ('\n', f); 3405 } 3406 else 3407 { 3408 fprintf (f, "\t.cfi_GNU_args_size " HOST_WIDE_INT_PRINT_DEC "\n", 3409 cfi->dw_cfi_oprnd1.dw_cfi_offset); 3410 } 3411 break; 3412 3413 case DW_CFA_GNU_window_save: 3414 fprintf (f, "\t.cfi_window_save\n"); 3415 break; 3416 3417 case DW_CFA_def_cfa_expression: 3418 case DW_CFA_expression: 3419 case DW_CFA_val_expression: 3420 if (f != asm_out_file) 3421 { 3422 fprintf (f, "\t.cfi_%scfa_%sexpression ...\n", 3423 cfi->dw_cfi_opc == DW_CFA_def_cfa_expression ? "def_" : "", 3424 cfi->dw_cfi_opc == DW_CFA_val_expression ? "val_" : ""); 3425 break; 3426 } 3427 fprintf (f, "\t.cfi_escape %#x,", cfi->dw_cfi_opc); 3428 output_cfa_loc_raw (cfi); 3429 fputc ('\n', f); 3430 break; 3431 3432 default: 3433 gcc_unreachable (); 3434 } 3435 } 3436 3437 void 3438 dwarf2out_emit_cfi (dw_cfi_ref cfi) 3439 { 3440 if (dwarf2out_do_cfi_asm ()) 3441 output_cfi_directive (asm_out_file, cfi); 3442 } 3443 3444 static void 3445 dump_cfi_row (FILE *f, dw_cfi_row *row) 3446 { 3447 dw_cfi_ref cfi; 3448 unsigned i; 3449 3450 cfi = row->cfa_cfi; 3451 if (!cfi) 3452 { 3453 dw_cfa_location dummy; 3454 memset (&dummy, 0, sizeof (dummy)); 3455 dummy.reg = INVALID_REGNUM; 3456 cfi = def_cfa_0 (&dummy, &row->cfa); 3457 } 3458 output_cfi_directive (f, cfi); 3459 3460 FOR_EACH_VEC_SAFE_ELT (row->reg_save, i, cfi) 3461 if (cfi) 3462 output_cfi_directive (f, cfi); 3463 } 3464 3465 void debug_cfi_row (dw_cfi_row *row); 3466 3467 void 3468 debug_cfi_row (dw_cfi_row *row) 3469 { 3470 dump_cfi_row (stderr, row); 3471 } 3472 3473 3474 /* Save the result of dwarf2out_do_frame across PCH. 3475 This variable is tri-state, with 0 unset, >0 true, <0 false. */ 3476 static GTY(()) signed char saved_do_cfi_asm = 0; 3477 3478 /* Decide whether to emit EH frame unwind information for the current 3479 translation unit. */ 3480 3481 bool 3482 dwarf2out_do_eh_frame (void) 3483 { 3484 return 3485 (flag_unwind_tables || flag_exceptions) 3486 && targetm_common.except_unwind_info (&global_options) == UI_DWARF2; 3487 } 3488 3489 /* Decide whether we want to emit frame unwind information for the current 3490 translation unit. */ 3491 3492 bool 3493 dwarf2out_do_frame (void) 3494 { 3495 /* We want to emit correct CFA location expressions or lists, so we 3496 have to return true if we're going to output debug info, even if 3497 we're not going to output frame or unwind info. */ 3498 if (write_symbols == DWARF2_DEBUG || write_symbols == VMS_AND_DWARF2_DEBUG) 3499 return true; 3500 3501 if (saved_do_cfi_asm > 0) 3502 return true; 3503 3504 if (targetm.debug_unwind_info () == UI_DWARF2) 3505 return true; 3506 3507 if (dwarf2out_do_eh_frame ()) 3508 return true; 3509 3510 return false; 3511 } 3512 3513 /* Decide whether to emit frame unwind via assembler directives. */ 3514 3515 bool 3516 dwarf2out_do_cfi_asm (void) 3517 { 3518 int enc; 3519 3520 if (saved_do_cfi_asm != 0) 3521 return saved_do_cfi_asm > 0; 3522 3523 /* Assume failure for a moment. */ 3524 saved_do_cfi_asm = -1; 3525 3526 if (!flag_dwarf2_cfi_asm || !dwarf2out_do_frame ()) 3527 return false; 3528 if (!HAVE_GAS_CFI_PERSONALITY_DIRECTIVE) 3529 return false; 3530 3531 /* Make sure the personality encoding is one the assembler can support. 3532 In particular, aligned addresses can't be handled. */ 3533 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/2,/*global=*/1); 3534 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) 3535 return false; 3536 enc = ASM_PREFERRED_EH_DATA_FORMAT (/*code=*/0,/*global=*/0); 3537 if ((enc & 0x70) != 0 && (enc & 0x70) != DW_EH_PE_pcrel) 3538 return false; 3539 3540 /* If we can't get the assembler to emit only .debug_frame, and we don't need 3541 dwarf2 unwind info for exceptions, then emit .debug_frame by hand. */ 3542 if (!HAVE_GAS_CFI_SECTIONS_DIRECTIVE && !dwarf2out_do_eh_frame ()) 3543 return false; 3544 3545 /* Success! */ 3546 saved_do_cfi_asm = 1; 3547 return true; 3548 } 3549 3550 namespace { 3551 3552 const pass_data pass_data_dwarf2_frame = 3553 { 3554 RTL_PASS, /* type */ 3555 "dwarf2", /* name */ 3556 OPTGROUP_NONE, /* optinfo_flags */ 3557 TV_FINAL, /* tv_id */ 3558 0, /* properties_required */ 3559 0, /* properties_provided */ 3560 0, /* properties_destroyed */ 3561 0, /* todo_flags_start */ 3562 0, /* todo_flags_finish */ 3563 }; 3564 3565 class pass_dwarf2_frame : public rtl_opt_pass 3566 { 3567 public: 3568 pass_dwarf2_frame (gcc::context *ctxt) 3569 : rtl_opt_pass (pass_data_dwarf2_frame, ctxt) 3570 {} 3571 3572 /* opt_pass methods: */ 3573 virtual bool gate (function *); 3574 virtual unsigned int execute (function *) { return execute_dwarf2_frame (); } 3575 3576 }; // class pass_dwarf2_frame 3577 3578 bool 3579 pass_dwarf2_frame::gate (function *) 3580 { 3581 /* Targets which still implement the prologue in assembler text 3582 cannot use the generic dwarf2 unwinding. */ 3583 if (!targetm.have_prologue ()) 3584 return false; 3585 3586 /* ??? What to do for UI_TARGET unwinding? They might be able to benefit 3587 from the optimized shrink-wrapping annotations that we will compute. 3588 For now, only produce the CFI notes for dwarf2. */ 3589 return dwarf2out_do_frame (); 3590 } 3591 3592 } // anon namespace 3593 3594 rtl_opt_pass * 3595 make_pass_dwarf2_frame (gcc::context *ctxt) 3596 { 3597 return new pass_dwarf2_frame (ctxt); 3598 } 3599 3600 #include "gt-dwarf2cfi.h" 3601