1;; Machine description for GNU compiler, VAX Version 2;; Copyright (C) 1987-2013 Free Software Foundation, Inc. 3 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20 21;;- Instruction patterns. When multiple patterns apply, 22;;- the first one in the file is chosen. 23;;- 24;;- See file "rtl.def" for documentation on define_insn, match_*, et al. 25;;- 26;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 27;;- updates for most instructions. 28 29;; UNSPEC_VOLATILE usage: 30 31(define_c_enum "unspecv" [ 32 VUNSPEC_BLOCKAGE ; 'blockage' insn to prevent scheduling across an 33 ; insn in the code. 34 VUNSPEC_SYNC_ISTREAM ; sequence of insns to sync the I-stream 35 VUNSPEC_PEM ; 'procedure_entry_mask' insn. 36]) 37 38(define_constants 39 [(VAX_AP_REGNUM 12) ; Register 12 contains the argument pointer 40 (VAX_FP_REGNUM 13) ; Register 13 contains the frame pointer 41 (VAX_SP_REGNUM 14) ; Register 14 contains the stack pointer 42 (VAX_PC_REGNUM 15) ; Register 15 contains the program counter 43 (VAX_PSW_REGNUM 16) ; Program Status Word 44 ] 45) 46 47;; Integer modes supported on VAX, with a mapping from machine mode 48;; to mnemonic suffix. DImode is always a special case. 49(define_mode_iterator VAXint [QI HI SI]) 50(define_mode_iterator VAXintQH [QI HI]) 51(define_mode_iterator VAXintQHSD [QI HI SI DI]) 52(define_mode_attr isfx [(QI "b") (HI "w") (SI "l") (DI "q")]) 53 54;; Similar for float modes supported on VAX. 55(define_mode_iterator VAXfp [SF DF]) 56(define_mode_attr fsfx [(SF "f") (DF "%#")]) 57 58;; Some output patterns want integer immediates with a prefix... 59(define_mode_attr iprefx [(QI "B") (HI "H") (SI "N")]) 60 61;; 62(include "constraints.md") 63(include "predicates.md") 64 65(define_insn "*cmp<mode>" 66 [(set (cc0) 67 (compare (match_operand:VAXint 0 "nonimmediate_operand" "nrmT,nrmT") 68 (match_operand:VAXint 1 "general_operand" "I,nrmT")))] 69 "" 70 "@ 71 tst<VAXint:isfx> %0 72 cmp<VAXint:isfx> %0,%1") 73 74(define_insn "*cmp<mode>" 75 [(set (cc0) 76 (compare (match_operand:VAXfp 0 "general_operand" "gF,gF") 77 (match_operand:VAXfp 1 "general_operand" "G,gF")))] 78 "" 79 "@ 80 tst<VAXfp:fsfx> %0 81 cmp<VAXfp:fsfx> %0,%1") 82 83(define_insn "*bit<mode>" 84 [(set (cc0) 85 (compare (and:VAXint (match_operand:VAXint 0 "general_operand" "nrmT") 86 (match_operand:VAXint 1 "general_operand" "nrmT")) 87 (const_int 0)))] 88 "" 89 "bit<VAXint:isfx> %0,%1") 90 91;; The VAX has no sCOND insns. It does have add/subtract with carry 92;; which could be used to implement the sltu and sgeu patterns. However, 93;; to do this properly requires a complete rewrite of the compare insns 94;; to keep them together with the sltu/sgeu insns until after the 95;; reload pass is complete. The previous implementation didn't do this 96;; and has been deleted. 97 98 99(define_insn "mov<mode>" 100 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 101 (match_operand:VAXfp 1 "general_operand" "G,gF"))] 102 "" 103 "@ 104 clr<VAXfp:fsfx> %0 105 mov<VAXfp:fsfx> %1,%0") 106 107;; Some VAXen don't support this instruction. 108;;(define_insn "movti" 109;; [(set (match_operand:TI 0 "general_operand" "=g") 110;; (match_operand:TI 1 "general_operand" "g"))] 111;; "" 112;; "movh %1,%0") 113 114(define_insn "movdi" 115 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 116 (match_operand:DI 1 "general_operand" "g"))] 117 "" 118 "* return vax_output_int_move (insn, operands, DImode);") 119 120;; The VAX move instructions have space-time tradeoffs. On a MicroVAX 121;; register-register mov instructions take 3 bytes and 2 CPU cycles. clrl 122;; takes 2 bytes and 3 cycles. mov from constant to register takes 2 cycles 123;; if the constant is smaller than 4 bytes, 3 cycles for a longword 124;; constant. movz, mneg, and mcom are as fast as mov, so movzwl is faster 125;; than movl for positive constants that fit in 16 bits but not 6 bits. cvt 126;; instructions take 4 cycles. inc takes 3 cycles. The machine description 127;; is willing to trade 1 byte for 1 cycle (clrl instead of movl $0; cvtwl 128;; instead of movl). 129 130;; Cycle counts for other models may vary (on a VAX 750 they are similar, 131;; but on a VAX 9000 most move and add instructions with one constant 132;; operand take 1 cycle). 133 134;; Loads of constants between 64 and 128 used to be done with 135;; "addl3 $63,#,dst" but this is slower than movzbl and takes as much space. 136 137(define_expand "movsi" 138 [(set (match_operand:SI 0 "nonimmediate_operand" "") 139 (match_operand:SI 1 "general_operand" ""))] 140 "" 141 " 142{ 143#ifdef NO_EXTERNAL_INDIRECT_ADDRESS 144 if (flag_pic 145 && GET_CODE (operands[1]) == CONST 146 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF 147 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0))) 148 { 149 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0); 150 rtx const_int = XEXP (XEXP (operands[1], 0), 1); 151 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); 152 emit_move_insn (temp, symbol_ref); 153 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int)); 154 DONE; 155 } 156#endif 157}") 158 159(define_insn "movsi_2" 160 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 161 (match_operand:SI 1 "nonsymbolic_operand" "nrmT"))] 162 "" 163 "* return vax_output_int_move (insn, operands, SImode);") 164 165(define_insn "mov<mode>" 166 [(set (match_operand:VAXintQH 0 "nonimmediate_operand" "=g") 167 (match_operand:VAXintQH 1 "general_operand" "g"))] 168 "" 169 "* return vax_output_int_move (insn, operands, <MODE>mode);") 170 171(define_insn "movstricthi" 172 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+g")) 173 (match_operand:HI 1 "general_operand" "g"))] 174 "" 175 "* 176{ 177 if (CONST_INT_P (operands[1])) 178 { 179 int i = INTVAL (operands[1]); 180 if (i == 0) 181 return \"clrw %0\"; 182 else if ((unsigned int)i < 64) 183 return \"movw %1,%0\"; 184 else if ((unsigned int)~i < 64) 185 return \"mcomw %H1,%0\"; 186 else if ((unsigned int)i < 256) 187 return \"movzbw %1,%0\"; 188 } 189 return \"movw %1,%0\"; 190}") 191 192(define_insn "movstrictqi" 193 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+g")) 194 (match_operand:QI 1 "general_operand" "g"))] 195 "" 196 "* 197{ 198 if (CONST_INT_P (operands[1])) 199 { 200 int i = INTVAL (operands[1]); 201 if (i == 0) 202 return \"clrb %0\"; 203 else if ((unsigned int)~i < 64) 204 return \"mcomb %B1,%0\"; 205 } 206 return \"movb %1,%0\"; 207}") 208 209;; This is here to accept 4 arguments and pass the first 3 along 210;; to the movmemhi1 pattern that really does the work. 211(define_expand "movmemhi" 212 [(set (match_operand:BLK 0 "general_operand" "=g") 213 (match_operand:BLK 1 "general_operand" "g")) 214 (use (match_operand:HI 2 "general_operand" "g")) 215 (match_operand 3 "" "")] 216 "" 217 " 218{ 219 if (CONST_INT_P (operands[2]) && INTVAL (operands[2]) <= 48) 220 { 221 emit_insn (gen_movmemsi1_2 (operands[0], operands[1], operands[2])); 222 DONE; 223 } 224 emit_insn (gen_movmemhi1 (operands[0], operands[1], operands[2])); 225 DONE; 226}") 227 228;; The definition of this insn does not really explain what it does, 229;; but it should suffice 230;; that anything generated as this insn will be recognized as one 231;; and that it won't successfully combine with anything. 232 233(define_insn "movmemsi1_2" 234 [(set (match_operand:BLK 0 "memory_operand" "=B") 235 (match_operand:BLK 1 "memory_operand" "B")) 236 (use (match_operand:SI 2 "const_int_operand" "g"))] 237 "INTVAL (operands[2]) <= 48" 238 "* return vax_output_movmemsi (insn, operands);") 239 240(define_insn "movmemhi1" 241 [(set (match_operand:BLK 0 "memory_operand" "=o") 242 (match_operand:BLK 1 "memory_operand" "o")) 243 (use (match_operand:HI 2 "general_operand" "g")) 244 (clobber (reg:SI 0)) 245 (clobber (reg:SI 1)) 246 (clobber (reg:SI 2)) 247 (clobber (reg:SI 3)) 248 (clobber (reg:SI 4)) 249 (clobber (reg:SI 5))] 250 "" 251 "movc3 %2,%1,%0") 252 253;; Extension and truncation insns. 254 255(define_insn "truncsiqi2" 256 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 257 (truncate:QI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))] 258 "" 259 "cvtlb %1,%0") 260 261(define_insn "truncsihi2" 262 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 263 (truncate:HI (match_operand:SI 1 "nonimmediate_operand" "nrmT")))] 264 "" 265 "cvtlw %1,%0") 266 267(define_insn "trunchiqi2" 268 [(set (match_operand:QI 0 "nonimmediate_operand" "=g") 269 (truncate:QI (match_operand:HI 1 "nonimmediate_operand" "g")))] 270 "" 271 "cvtwb %1,%0") 272 273(define_insn "extendhisi2" 274 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 275 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 276 "" 277 "cvtwl %1,%0") 278 279(define_insn "extendqihi2" 280 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 281 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 282 "" 283 "cvtbw %1,%0") 284 285(define_insn "extendqisi2" 286 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 287 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 288 "" 289 "cvtbl %1,%0") 290 291(define_insn "extendsfdf2" 292 [(set (match_operand:DF 0 "nonimmediate_operand" "=g") 293 (float_extend:DF (match_operand:SF 1 "general_operand" "gF")))] 294 "" 295 "cvtf%# %1,%0") 296 297(define_insn "truncdfsf2" 298 [(set (match_operand:SF 0 "nonimmediate_operand" "=g") 299 (float_truncate:SF (match_operand:DF 1 "general_operand" "gF")))] 300 "" 301 "cvt%#f %1,%0") 302 303(define_insn "zero_extendhisi2" 304 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 305 (zero_extend:SI (match_operand:HI 1 "nonimmediate_operand" "g")))] 306 "" 307 "movzwl %1,%0") 308 309(define_insn "zero_extendqihi2" 310 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 311 (zero_extend:HI (match_operand:QI 1 "nonimmediate_operand" "g")))] 312 "" 313 "movzbw %1,%0") 314 315(define_insn "zero_extendqisi2" 316 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 317 (zero_extend:SI (match_operand:QI 1 "nonimmediate_operand" "g")))] 318 "" 319 "movzbl %1,%0") 320 321;; Fix-to-float conversion insns. 322 323(define_insn "float<VAXint:mode><VAXfp:mode>2" 324 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 325 (float:VAXfp (match_operand:VAXint 1 "nonimmediate_operand" "g")))] 326 "" 327 "cvt<VAXint:isfx><VAXfp:fsfx> %1,%0") 328 329;; Float-to-fix conversion insns. 330 331(define_insn "fix_trunc<VAXfp:mode><VAXint:mode>2" 332 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 333 (fix:VAXint (match_operand:VAXfp 1 "general_operand" "gF")))] 334 "" 335 "cvt<VAXfp:fsfx><VAXint:isfx> %1,%0") 336 337(define_expand "fixuns_trunc<VAXfp:mode><VAXint:mode>2" 338 [(set (match_operand:VAXint 0 "nonimmediate_operand" "") 339 (fix:VAXint (match_operand:VAXfp 1 "general_operand")))] 340 "") 341 342;;- All kinds of add instructions. 343 344(define_insn "add<mode>3" 345 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 346 (plus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 347 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))] 348 "" 349 "@ 350 add<VAXfp:fsfx>2 %2,%0 351 add<VAXfp:fsfx>2 %1,%0 352 add<VAXfp:fsfx>3 %1,%2,%0") 353 354(define_insn "pushlclsymreg" 355 [(set (match_operand:SI 0 "push_operand" "=g") 356 (plus:SI (match_operand:SI 1 "register_operand" "%r") 357 (match_operand:SI 2 "local_symbolic_operand" "i")))] 358 "flag_pic" 359 "pushab %a2[%1]") 360 361(define_insn "pushextsymreg" 362 [(set (match_operand:SI 0 "push_operand" "=g") 363 (plus:SI (match_operand:SI 1 "register_operand" "%r") 364 (match_operand:SI 2 "external_symbolic_operand" "i")))] 365 "flag_pic" 366 "pushab %a2[%1]") 367 368(define_insn "movlclsymreg" 369 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 370 (plus:SI (match_operand:SI 1 "register_operand" "%r") 371 (match_operand:SI 2 "local_symbolic_operand" "i")))] 372 "flag_pic" 373 "movab %a2[%1],%0") 374 375(define_insn "movextsymreg" 376 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 377 (plus:SI (match_operand:SI 1 "register_operand" "%r") 378 (match_operand:SI 2 "external_symbolic_operand" "i")))] 379 "flag_pic" 380 "movab %a2[%1],%0") 381 382(define_insn "add<mode>3" 383 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 384 (plus:VAXint (match_operand:VAXint 1 "general_operand" "nrmT") 385 (match_operand:VAXint 2 "general_operand" "nrmT")))] 386 "" 387 "* return vax_output_int_add (insn, operands, <MODE>mode);") 388 389(define_expand "adddi3" 390 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 391 (plus:DI (match_operand:DI 1 "general_operand" "g") 392 (match_operand:DI 2 "general_operand" "g")))] 393 "!reload_in_progress" 394 "vax_expand_addsub_di_operands (operands, PLUS); DONE;") 395 396(define_insn "adcdi3" 397 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr") 398 (plus:DI (match_operand:DI 1 "general_addsub_di_operand" "%0") 399 (match_operand:DI 2 "general_addsub_di_operand" "nRr")))] 400 "TARGET_QMATH" 401 "* return vax_output_int_add (insn, operands, DImode);") 402 403;; The add-with-carry (adwc) instruction only accepts two operands. 404(define_insn "adddi3_old" 405 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro>,ro>") 406 (plus:DI (match_operand:DI 1 "general_operand" "%0,ro>") 407 (match_operand:DI 2 "general_operand" "Fsro,Fs")))] 408 "!TARGET_QMATH" 409 "* return vax_output_int_add (insn, operands, DImode);") 410 411;;- All kinds of subtract instructions. 412 413(define_insn "sub<mode>3" 414 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 415 (minus:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 416 (match_operand:VAXfp 2 "general_operand" "gF,gF")))] 417 "" 418 "@ 419 sub<VAXfp:fsfx>2 %2,%0 420 sub<VAXfp:fsfx>3 %2,%1,%0") 421 422(define_insn "sub<mode>3" 423 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 424 (minus:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 425 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))] 426 "" 427 "@ 428 sub<VAXint:isfx>2 %2,%0 429 sub<VAXint:isfx>3 %2,%1,%0") 430 431(define_expand "subdi3" 432 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 433 (minus:DI (match_operand:DI 1 "general_operand" "g") 434 (match_operand:DI 2 "general_operand" "g")))] 435 "!reload_in_progress" 436 "vax_expand_addsub_di_operands (operands, MINUS); DONE;") 437 438(define_insn "sbcdi3" 439 [(set (match_operand:DI 0 "nonimmediate_addsub_di_operand" "=Rr,=Rr") 440 (minus:DI (match_operand:DI 1 "general_addsub_di_operand" "0,I") 441 (match_operand:DI 2 "general_addsub_di_operand" "nRr,Rr")))] 442 "TARGET_QMATH" 443 "* return vax_output_int_subtract (insn, operands, DImode);") 444 445;; The subtract-with-carry (sbwc) instruction only takes two operands. 446(define_insn "subdi3_old" 447 [(set (match_operand:DI 0 "nonimmediate_operand" "=or>,or>") 448 (minus:DI (match_operand:DI 1 "general_operand" "0,or>") 449 (match_operand:DI 2 "general_operand" "Fsor,Fs")))] 450 "!TARGET_QMATH" 451 "* return vax_output_int_subtract (insn, operands, DImode);") 452 453;;- Multiply instructions. 454 455(define_insn "mul<mode>3" 456 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g,g") 457 (mult:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF,gF") 458 (match_operand:VAXfp 2 "general_operand" "gF,0,gF")))] 459 "" 460 "@ 461 mul<VAXfp:fsfx>2 %2,%0 462 mul<VAXfp:fsfx>2 %1,%0 463 mul<VAXfp:fsfx>3 %1,%2,%0") 464 465(define_insn "mul<mode>3" 466 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 467 (mult:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 468 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))] 469 "" 470 "@ 471 mul<VAXint:isfx>2 %2,%0 472 mul<VAXint:isfx>2 %1,%0 473 mul<VAXint:isfx>3 %1,%2,%0") 474 475(define_insn "mulsidi3" 476 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 477 (mult:DI (sign_extend:DI 478 (match_operand:SI 1 "nonimmediate_operand" "nrmT")) 479 (sign_extend:DI 480 (match_operand:SI 2 "nonimmediate_operand" "nrmT"))))] 481 "" 482 "emul %1,%2,$0,%0") 483 484(define_insn "" 485 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 486 (plus:DI 487 (mult:DI (sign_extend:DI 488 (match_operand:SI 1 "nonimmediate_operand" "nrmT")) 489 (sign_extend:DI 490 (match_operand:SI 2 "nonimmediate_operand" "nrmT"))) 491 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "g"))))] 492 "" 493 "emul %1,%2,%3,%0") 494 495;; 'F' constraint means type CONST_DOUBLE 496(define_insn "" 497 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 498 (plus:DI 499 (mult:DI (sign_extend:DI 500 (match_operand:SI 1 "nonimmediate_operand" "nrmT")) 501 (sign_extend:DI 502 (match_operand:SI 2 "nonimmediate_operand" "nrmT"))) 503 (match_operand:DI 3 "immediate_operand" "F")))] 504 "GET_CODE (operands[3]) == CONST_DOUBLE 505 && CONST_DOUBLE_HIGH (operands[3]) == (CONST_DOUBLE_LOW (operands[3]) >> 31)" 506 "* 507{ 508 if (CONST_DOUBLE_HIGH (operands[3])) 509 operands[3] = GEN_INT (CONST_DOUBLE_LOW (operands[3])); 510 return \"emul %1,%2,%3,%0\"; 511}") 512 513;;- Divide instructions. 514 515(define_insn "div<mode>3" 516 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g,g") 517 (div:VAXfp (match_operand:VAXfp 1 "general_operand" "0,gF") 518 (match_operand:VAXfp 2 "general_operand" "gF,gF")))] 519 "" 520 "@ 521 div<VAXfp:fsfx>2 %2,%0 522 div<VAXfp:fsfx>3 %2,%1,%0") 523 524(define_insn "div<mode>3" 525 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 526 (div:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 527 (match_operand:VAXint 2 "general_operand" "nrmT,nrmT")))] 528 "" 529 "@ 530 div<VAXint:isfx>2 %2,%0 531 div<VAXint:isfx>3 %2,%1,%0") 532 533;This is left out because it is very slow; 534;we are better off programming around the "lack" of this insn. 535;(define_insn "divmoddisi4" 536; [(set (match_operand:SI 0 "general_operand" "=g") 537; (div:SI (match_operand:DI 1 "general_operand" "g") 538; (match_operand:SI 2 "general_operand" "g"))) 539; (set (match_operand:SI 3 "general_operand" "=g") 540; (mod:SI (match_operand:DI 1 "general_operand" "g") 541; (match_operand:SI 2 "general_operand" "g")))] 542; "" 543; "ediv %2,%1,%0,%3") 544 545;; Bit-and on the VAX is done with a clear-bits insn. 546(define_expand "and<mode>3" 547 [(set (match_operand:VAXint 0 "nonimmediate_operand" "") 548 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "")) 549 (match_operand:VAXint 2 "general_operand" "")))] 550 "" 551 " 552{ 553 rtx op1 = operands[1]; 554 555 /* If there is a constant argument, complement that one. */ 556 if (CONST_INT_P (operands[2]) && ! CONST_INT_P (op1)) 557 { 558 operands[1] = operands[2]; 559 operands[2] = op1; 560 op1 = operands[1]; 561 } 562 563 if (CONST_INT_P (op1)) 564 operands[1] = GEN_INT (~INTVAL (op1)); 565 else 566 operands[1] = expand_unop (<MODE>mode, one_cmpl_optab, op1, 0, 1); 567}") 568 569(define_insn "*and<mode>" 570 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 571 (and:VAXint (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT,nrmT")) 572 (match_operand:VAXint 2 "general_operand" "0,nrmT")))] 573 "" 574 "@ 575 bic<VAXint:isfx>2 %1,%0 576 bic<VAXint:isfx>3 %1,%2,%0") 577 578;; The following used to be needed because constant propagation can 579;; create them starting from the bic insn patterns above. This is no 580;; longer a problem. However, having these patterns allows optimization 581;; opportunities in combine.c. 582 583(define_insn "*and<mode>_const_int" 584 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g") 585 (and:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT") 586 (match_operand:VAXint 2 "const_int_operand" "n,n")))] 587 "" 588 "@ 589 bic<VAXint:isfx>2 %<VAXint:iprefx>2,%0 590 bic<VAXint:isfx>3 %<VAXint:iprefx>2,%1,%0") 591 592 593;;- Bit set instructions. 594 595(define_insn "ior<mode>3" 596 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 597 (ior:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 598 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))] 599 "" 600 "@ 601 bis<VAXint:isfx>2 %2,%0 602 bis<VAXint:isfx>2 %1,%0 603 bis<VAXint:isfx>3 %2,%1,%0") 604 605;;- xor instructions. 606 607(define_insn "xor<mode>3" 608 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g,g,g") 609 (xor:VAXint (match_operand:VAXint 1 "general_operand" "0,nrmT,nrmT") 610 (match_operand:VAXint 2 "general_operand" "nrmT,0,nrmT")))] 611 "" 612 "@ 613 xor<VAXint:isfx>2 %2,%0 614 xor<VAXint:isfx>2 %1,%0 615 xor<VAXint:isfx>3 %2,%1,%0") 616 617 618(define_insn "neg<mode>2" 619 [(set (match_operand:VAXfp 0 "nonimmediate_operand" "=g") 620 (neg:VAXfp (match_operand:VAXfp 1 "general_operand" "gF")))] 621 "" 622 "mneg<VAXfp:fsfx> %1,%0") 623 624(define_insn "neg<mode>2" 625 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 626 (neg:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))] 627 "" 628 "mneg<VAXint:isfx> %1,%0") 629 630(define_insn "one_cmpl<mode>2" 631 [(set (match_operand:VAXint 0 "nonimmediate_operand" "=g") 632 (not:VAXint (match_operand:VAXint 1 "general_operand" "nrmT")))] 633 "" 634 "mcom<VAXint:isfx> %1,%0") 635 636 637;; Arithmetic right shift on the VAX works by negating the shift count, 638;; then emitting a right shift with the shift count negated. This means 639;; that all actual shift counts in the RTL will be positive. This 640;; prevents converting shifts to ZERO_EXTRACTs with negative positions, 641;; which isn't valid. 642(define_expand "ashrsi3" 643 [(set (match_operand:SI 0 "general_operand" "=g") 644 (ashiftrt:SI (match_operand:SI 1 "general_operand" "g") 645 (match_operand:QI 2 "general_operand" "g")))] 646 "" 647 " 648{ 649 if (! CONST_INT_P (operands[2])) 650 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 651}") 652 653(define_insn "" 654 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 655 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 656 (match_operand:QI 2 "const_int_operand" "n")))] 657 "" 658 "ashl $%n2,%1,%0") 659 660(define_insn "" 661 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 662 (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 663 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 664 "" 665 "ashl %2,%1,%0") 666 667(define_insn "ashlsi3" 668 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 669 (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 670 (match_operand:QI 2 "general_operand" "g")))] 671 "" 672 "* 673{ 674 if (operands[2] == const1_rtx && rtx_equal_p (operands[0], operands[1])) 675 return \"addl2 %0,%0\"; 676 if (REG_P (operands[1]) && CONST_INT_P (operands[2])) 677 { 678 int i = INTVAL (operands[2]); 679 if (i == 1) 680 return \"addl3 %1,%1,%0\"; 681 if (i == 2 && !optimize_size) 682 { 683 if (push_operand (operands[0], SImode)) 684 return \"pushal 0[%1]\"; 685 return \"moval 0[%1],%0\"; 686 } 687 if (i == 3 && !optimize_size) 688 { 689 if (push_operand (operands[0], SImode)) 690 return \"pushaq 0[%1]\"; 691 return \"movaq 0[%1],%0\"; 692 } 693 } 694 return \"ashl %2,%1,%0\"; 695}") 696 697;; Arithmetic right shift on the VAX works by negating the shift count. 698(define_expand "ashrdi3" 699 [(set (match_operand:DI 0 "general_operand" "=g") 700 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 701 (match_operand:QI 2 "general_operand" "g")))] 702 "" 703 " 704{ 705 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 706}") 707 708(define_insn "ashldi3" 709 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 710 (ashift:DI (match_operand:DI 1 "general_operand" "g") 711 (match_operand:QI 2 "general_operand" "g")))] 712 "" 713 "ashq %2,%D1,%0") 714 715(define_insn "" 716 [(set (match_operand:DI 0 "nonimmediate_operand" "=g") 717 (ashiftrt:DI (match_operand:DI 1 "general_operand" "g") 718 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 719 "" 720 "ashq %2,%D1,%0") 721 722;; We used to have expand_shift handle logical right shifts by using extzv, 723;; but this make it very difficult to do lshrdi3. Since the VAX is the 724;; only machine with this kludge, it's better to just do this with a 725;; define_expand and remove that case from expand_shift. 726 727(define_expand "lshrsi3" 728 [(set (match_dup 3) 729 (minus:QI (const_int 32) 730 (match_dup 4))) 731 (set (match_operand:SI 0 "nonimmediate_operand" "=g") 732 (zero_extract:SI (match_operand:SI 1 "register_operand" "r") 733 (match_dup 3) 734 (match_operand:SI 2 "register_operand" "g")))] 735 "" 736 " 737{ 738 operands[3] = gen_reg_rtx (QImode); 739 operands[4] = gen_lowpart (QImode, operands[2]); 740}") 741 742;; Rotate right on the VAX works by negating the shift count. 743(define_expand "rotrsi3" 744 [(set (match_operand:SI 0 "general_operand" "=g") 745 (rotatert:SI (match_operand:SI 1 "general_operand" "g") 746 (match_operand:QI 2 "general_operand" "g")))] 747 "" 748 " 749{ 750 if (! CONST_INT_P (operands[2])) 751 operands[2] = gen_rtx_NEG (QImode, negate_rtx (QImode, operands[2])); 752}") 753 754(define_insn "rotlsi3" 755 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 756 (rotate:SI (match_operand:SI 1 "general_operand" "nrmT") 757 (match_operand:QI 2 "general_operand" "g")))] 758 "" 759 "rotl %2,%1,%0") 760 761(define_insn "" 762 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 763 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 764 (match_operand:QI 2 "const_int_operand" "n")))] 765 "" 766 "rotl %R2,%1,%0") 767 768(define_insn "" 769 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 770 (rotatert:SI (match_operand:SI 1 "general_operand" "nrmT") 771 (neg:QI (match_operand:QI 2 "general_operand" "g"))))] 772 "" 773 "rotl %2,%1,%0") 774 775;This insn is probably slower than a multiply and an add. 776;(define_insn "" 777; [(set (match_operand:SI 0 "general_operand" "=g") 778; (mult:SI (plus:SI (match_operand:SI 1 "general_operand" "g") 779; (match_operand:SI 2 "general_operand" "g")) 780; (match_operand:SI 3 "general_operand" "g")))] 781; "" 782; "index %1,$0x80000000,$0x7fffffff,%3,%2,%0") 783 784;; Special cases of bit-field insns which we should 785;; recognize in preference to the general case. 786;; These handle aligned 8-bit and 16-bit fields, 787;; which can usually be done with move instructions. 788 789(define_insn "" 790 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+ro") 791 (match_operand:QI 1 "const_int_operand" "n") 792 (match_operand:SI 2 "const_int_operand" "n")) 793 (match_operand:SI 3 "general_operand" "g"))] 794 "(INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 795 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0 796 && (REG_P (operands[0]) 797 || (MEM_P (operands[0]) 798 && ! mode_dependent_address_p (XEXP (operands[0], 0), 799 MEM_ADDR_SPACE (operands[0]))))" 800 "* 801{ 802 if (REG_P (operands[0])) 803 { 804 if (INTVAL (operands[2]) != 0) 805 return \"insv %3,%2,%1,%0\"; 806 } 807 else 808 operands[0] 809 = adjust_address (operands[0], 810 INTVAL (operands[1]) == 8 ? QImode : HImode, 811 INTVAL (operands[2]) / 8); 812 813 CC_STATUS_INIT; 814 if (INTVAL (operands[1]) == 8) 815 return \"movb %3,%0\"; 816 return \"movw %3,%0\"; 817}") 818 819(define_insn "" 820 [(set (match_operand:SI 0 "nonimmediate_operand" "=&g") 821 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro") 822 (match_operand:QI 2 "const_int_operand" "n") 823 (match_operand:SI 3 "const_int_operand" "n")))] 824 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 825 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 826 && (REG_P (operands[1]) 827 || (MEM_P (operands[1]) 828 && ! mode_dependent_address_p (XEXP (operands[1], 0), 829 MEM_ADDR_SPACE (operands[1]))))" 830 "* 831{ 832 if (REG_P (operands[1])) 833 { 834 if (INTVAL (operands[3]) != 0) 835 return \"extzv %3,%2,%1,%0\"; 836 } 837 else 838 operands[1] 839 = adjust_address (operands[1], 840 INTVAL (operands[2]) == 8 ? QImode : HImode, 841 INTVAL (operands[3]) / 8); 842 843 if (INTVAL (operands[2]) == 8) 844 return \"movzbl %1,%0\"; 845 return \"movzwl %1,%0\"; 846}") 847 848(define_insn "" 849 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 850 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro") 851 (match_operand:QI 2 "const_int_operand" "n") 852 (match_operand:SI 3 "const_int_operand" "n")))] 853 "(INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 854 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0 855 && (REG_P (operands[1]) 856 || (MEM_P (operands[1]) 857 && ! mode_dependent_address_p (XEXP (operands[1], 0), 858 MEM_ADDR_SPACE (operands[1]))))" 859 "* 860{ 861 if (REG_P (operands[1])) 862 { 863 if (INTVAL (operands[3]) != 0) 864 return \"extv %3,%2,%1,%0\"; 865 } 866 else 867 operands[1] 868 = adjust_address (operands[1], 869 INTVAL (operands[2]) == 8 ? QImode : HImode, 870 INTVAL (operands[3]) / 8); 871 872 if (INTVAL (operands[2]) == 8) 873 return \"cvtbl %1,%0\"; 874 return \"cvtwl %1,%0\"; 875}") 876 877;; Register-only SImode cases of bit-field insns. 878 879(define_insn "" 880 [(set (cc0) 881 (compare 882 (sign_extract:SI (match_operand:SI 0 "register_operand" "r") 883 (match_operand:QI 1 "general_operand" "g") 884 (match_operand:SI 2 "general_operand" "nrmT")) 885 (match_operand:SI 3 "general_operand" "nrmT")))] 886 "" 887 "cmpv %2,%1,%0,%3") 888 889(define_insn "" 890 [(set (cc0) 891 (compare 892 (zero_extract:SI (match_operand:SI 0 "register_operand" "r") 893 (match_operand:QI 1 "general_operand" "g") 894 (match_operand:SI 2 "general_operand" "nrmT")) 895 (match_operand:SI 3 "general_operand" "nrmT")))] 896 "" 897 "cmpzv %2,%1,%0,%3") 898 899;; When the field position and size are constant and the destination 900;; is a register, extv and extzv are much slower than a rotate followed 901;; by a bicl or sign extension. Because we might end up choosing ext[z]v 902;; anyway, we can't allow immediate values for the primary source operand. 903 904(define_insn "" 905 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 906 (sign_extract:SI (match_operand:SI 1 "register_operand" "ro") 907 (match_operand:QI 2 "general_operand" "g") 908 (match_operand:SI 3 "general_operand" "nrmT")))] 909 "" 910 "* 911{ 912 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2]) 913 || ! REG_P (operands[0]) 914 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16)) 915 return \"extv %3,%2,%1,%0\"; 916 if (INTVAL (operands[2]) == 8) 917 return \"rotl %R3,%1,%0\;cvtbl %0,%0\"; 918 return \"rotl %R3,%1,%0\;cvtwl %0,%0\"; 919}") 920 921(define_insn "" 922 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 923 (zero_extract:SI (match_operand:SI 1 "register_operand" "ro") 924 (match_operand:QI 2 "general_operand" "g") 925 (match_operand:SI 3 "general_operand" "nrmT")))] 926 "" 927 "* 928{ 929 if (! CONST_INT_P (operands[3]) || ! CONST_INT_P (operands[2]) 930 || ! REG_P (operands[0])) 931 return \"extzv %3,%2,%1,%0\"; 932 if (INTVAL (operands[2]) == 8) 933 return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 934 if (INTVAL (operands[2]) == 16) 935 return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 936 if (INTVAL (operands[3]) & 31) 937 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\"; 938 if (rtx_equal_p (operands[0], operands[1])) 939 return \"bicl2 %M2,%0\"; 940 return \"bicl3 %M2,%1,%0\"; 941}") 942 943;; Non-register cases. 944;; nonimmediate_operand is used to make sure that mode-ambiguous cases 945;; don't match these (and therefore match the cases above instead). 946 947(define_insn "" 948 [(set (cc0) 949 (compare 950 (sign_extract:SI (match_operand:QI 0 "memory_operand" "m") 951 (match_operand:QI 1 "general_operand" "g") 952 (match_operand:SI 2 "general_operand" "nrmT")) 953 (match_operand:SI 3 "general_operand" "nrmT")))] 954 "" 955 "cmpv %2,%1,%0,%3") 956 957(define_insn "" 958 [(set (cc0) 959 (compare 960 (zero_extract:SI (match_operand:QI 0 "nonimmediate_operand" "rm") 961 (match_operand:QI 1 "general_operand" "g") 962 (match_operand:SI 2 "general_operand" "nrmT")) 963 (match_operand:SI 3 "general_operand" "nrmT")))] 964 "" 965 "cmpzv %2,%1,%0,%3") 966 967(define_insn "extv" 968 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 969 (sign_extract:SI (match_operand:QI 1 "memory_operand" "m") 970 (match_operand:QI 2 "general_operand" "g") 971 (match_operand:SI 3 "general_operand" "nrmT")))] 972 "" 973 "* 974{ 975 if (! REG_P (operands[0]) || ! CONST_INT_P (operands[2]) 976 || ! CONST_INT_P (operands[3]) 977 || (INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16) 978 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 979 || side_effects_p (operands[1]) 980 || (MEM_P (operands[1]) 981 && mode_dependent_address_p (XEXP (operands[1], 0), 982 MEM_ADDR_SPACE (operands[1])))) 983 return \"extv %3,%2,%1,%0\"; 984 if (INTVAL (operands[2]) == 8) 985 return \"rotl %R3,%1,%0\;cvtbl %0,%0\"; 986 return \"rotl %R3,%1,%0\;cvtwl %0,%0\"; 987}") 988 989(define_expand "extzv" 990 [(set (match_operand:SI 0 "general_operand" "") 991 (zero_extract:SI (match_operand:SI 1 "general_operand" "") 992 (match_operand:QI 2 "general_operand" "") 993 (match_operand:SI 3 "general_operand" "")))] 994 "" 995 "") 996 997(define_insn "" 998 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 999 (zero_extract:SI (match_operand:QI 1 "memory_operand" "m") 1000 (match_operand:QI 2 "general_operand" "g") 1001 (match_operand:SI 3 "general_operand" "nrmT")))] 1002 "" 1003 "* 1004{ 1005 if (! REG_P (operands[0]) || ! CONST_INT_P (operands[2]) 1006 || ! CONST_INT_P (operands[3]) 1007 || INTVAL (operands[2]) + INTVAL (operands[3]) > 32 1008 || side_effects_p (operands[1]) 1009 || (MEM_P (operands[1]) 1010 && mode_dependent_address_p (XEXP (operands[1], 0), 1011 MEM_ADDR_SPACE (operands[1])))) 1012 return \"extzv %3,%2,%1,%0\"; 1013 if (INTVAL (operands[2]) == 8) 1014 return \"rotl %R3,%1,%0\;movzbl %0,%0\"; 1015 if (INTVAL (operands[2]) == 16) 1016 return \"rotl %R3,%1,%0\;movzwl %0,%0\"; 1017 if (MEM_P (operands[1]) 1018 && GET_CODE (XEXP (operands[1], 0)) == PLUS 1019 && REG_P (XEXP (XEXP (operands[1], 0), 0)) 1020 && CONST_INT_P (XEXP (XEXP (operands[1], 0), 1)) 1021 && CONST_INT_P (operands[2]) 1022 && CONST_INT_P (operands[3])) 1023 { 1024 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[1], 0), 1)); 1025 HOST_WIDE_INT l = INTVAL (operands[2]); 1026 HOST_WIDE_INT v = INTVAL (operands[3]); 1027 if ((o & 3) && (o & 3) * 8 + v + l <= 32) 1028 { 1029 rtx tmp; 1030 tmp = XEXP (XEXP (operands[1], 0), 0); 1031 if (o & ~3) 1032 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3)); 1033 operands[1] = gen_rtx_MEM (QImode, tmp); 1034 operands[3] = GEN_INT (v + (o & 3) * 8); 1035 } 1036 if (optimize_size) 1037 return \"extzv %3,%2,%1,%0\"; 1038 } 1039 return \"rotl %R3,%1,%0\;bicl2 %M2,%0\"; 1040}") 1041 1042(define_expand "insv" 1043 [(set (zero_extract:SI (match_operand:SI 0 "general_operand" "") 1044 (match_operand:QI 1 "general_operand" "") 1045 (match_operand:SI 2 "general_operand" "")) 1046 (match_operand:SI 3 "general_operand" ""))] 1047 "" 1048 "") 1049 1050(define_insn "" 1051 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+g") 1052 (match_operand:QI 1 "general_operand" "g") 1053 (match_operand:SI 2 "general_operand" "nrmT")) 1054 (match_operand:SI 3 "general_operand" "nrmT"))] 1055 "" 1056 "* 1057{ 1058 if (MEM_P (operands[0]) 1059 && GET_CODE (XEXP (operands[0], 0)) == PLUS 1060 && REG_P (XEXP (XEXP (operands[0], 0), 0)) 1061 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1)) 1062 && CONST_INT_P (operands[1]) 1063 && CONST_INT_P (operands[2])) 1064 { 1065 HOST_WIDE_INT o = INTVAL (XEXP (XEXP (operands[0], 0), 1)); 1066 HOST_WIDE_INT v = INTVAL (operands[2]); 1067 HOST_WIDE_INT l = INTVAL (operands[1]); 1068 if ((o & 3) && (o & 3) * 8 + v + l <= 32) 1069 { 1070 rtx tmp; 1071 tmp = XEXP (XEXP (operands[0], 0), 0); 1072 if (o & ~3) 1073 tmp = gen_rtx_PLUS (SImode, tmp, GEN_INT (o & ~3)); 1074 operands[0] = gen_rtx_MEM (QImode, tmp); 1075 operands[2] = GEN_INT (v + (o & 3) * 8); 1076 } 1077 } 1078 return \"insv %3,%2,%1,%0\"; 1079}") 1080 1081(define_insn "" 1082 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 1083 (match_operand:QI 1 "general_operand" "g") 1084 (match_operand:SI 2 "general_operand" "nrmT")) 1085 (match_operand:SI 3 "general_operand" "nrmT"))] 1086 "" 1087 "insv %3,%2,%1,%0") 1088 1089;; Unconditional jump 1090(define_insn "jump" 1091 [(set (pc) 1092 (label_ref (match_operand 0 "" "")))] 1093 "" 1094 "jbr %l0") 1095 1096;; Conditional jumps 1097 1098(define_expand "cbranch<mode>4" 1099 [(set (cc0) 1100 (compare (match_operand:VAXint 1 "nonimmediate_operand" "") 1101 (match_operand:VAXint 2 "general_operand" ""))) 1102 (set (pc) 1103 (if_then_else 1104 (match_operator 0 "ordered_comparison_operator" [(cc0) 1105 (const_int 0)]) 1106 (label_ref (match_operand 3 "" "")) 1107 (pc)))] 1108 "") 1109 1110(define_expand "cbranch<mode>4" 1111 [(set (cc0) 1112 (compare (match_operand:VAXfp 1 "general_operand" "") 1113 (match_operand:VAXfp 2 "general_operand" ""))) 1114 (set (pc) 1115 (if_then_else 1116 (match_operator 0 "ordered_comparison_operator" [(cc0) 1117 (const_int 0)]) 1118 (label_ref (match_operand 3 "" "")) 1119 (pc)))] 1120 "") 1121 1122(define_insn "*branch" 1123 [(set (pc) 1124 (if_then_else (match_operator 0 "ordered_comparison_operator" 1125 [(cc0) 1126 (const_int 0)]) 1127 (label_ref (match_operand 1 "" "")) 1128 (pc)))] 1129 "" 1130 "j%c0 %l1") 1131 1132;; Recognize reversed jumps. 1133(define_insn "*branch_reversed" 1134 [(set (pc) 1135 (if_then_else (match_operator 0 "ordered_comparison_operator" 1136 [(cc0) 1137 (const_int 0)]) 1138 (pc) 1139 (label_ref (match_operand 1 "" ""))))] 1140 "" 1141 "j%C0 %l1") ; %C0 negates condition 1142 1143;; Recognize jbs, jlbs, jbc and jlbc instructions. Note that the operand 1144;; of jlbs and jlbc insns are SImode in the hardware. However, if it is 1145;; memory, we use QImode in the insn. So we can't use those instructions 1146;; for mode-dependent addresses. 1147 1148(define_insn "" 1149 [(set (pc) 1150 (if_then_else 1151 (ne (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g") 1152 (const_int 1) 1153 (match_operand:SI 1 "general_operand" "I,nrmT")) 1154 (const_int 0)) 1155 (label_ref (match_operand 2 "" "")) 1156 (pc)))] 1157 "" 1158 "@ 1159 jlbs %0,%l2 1160 jbs %1,%0,%l2") 1161 1162(define_insn "" 1163 [(set (pc) 1164 (if_then_else 1165 (eq (zero_extract:SI (match_operand:QI 0 "memory_operand" "Q,g") 1166 (const_int 1) 1167 (match_operand:SI 1 "general_operand" "I,nrmT")) 1168 (const_int 0)) 1169 (label_ref (match_operand 2 "" "")) 1170 (pc)))] 1171 "" 1172 "@ 1173 jlbc %0,%l2 1174 jbc %1,%0,%l2") 1175 1176(define_insn "" 1177 [(set (pc) 1178 (if_then_else 1179 (ne (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 1180 (const_int 1) 1181 (match_operand:SI 1 "general_operand" "I,nrmT")) 1182 (const_int 0)) 1183 (label_ref (match_operand 2 "" "")) 1184 (pc)))] 1185 "" 1186 "@ 1187 jlbs %0,%l2 1188 jbs %1,%0,%l2") 1189 1190(define_insn "" 1191 [(set (pc) 1192 (if_then_else 1193 (eq (zero_extract:SI (match_operand:SI 0 "register_operand" "r,r") 1194 (const_int 1) 1195 (match_operand:SI 1 "general_operand" "I,nrmT")) 1196 (const_int 0)) 1197 (label_ref (match_operand 2 "" "")) 1198 (pc)))] 1199 "" 1200 "@ 1201 jlbc %0,%l2 1202 jbc %1,%0,%l2") 1203 1204;; Subtract-and-jump and Add-and-jump insns. 1205;; These are not used when output is for the Unix assembler 1206;; because it does not know how to modify them to reach far. 1207 1208;; Normal sob insns. 1209 1210(define_insn "" 1211 [(set (pc) 1212 (if_then_else 1213 (gt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 1214 (const_int -1)) 1215 (const_int 0)) 1216 (label_ref (match_operand 1 "" "")) 1217 (pc))) 1218 (set (match_dup 0) 1219 (plus:SI (match_dup 0) 1220 (const_int -1)))] 1221 "!TARGET_UNIX_ASM" 1222 "jsobgtr %0,%l1") 1223 1224(define_insn "" 1225 [(set (pc) 1226 (if_then_else 1227 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 1228 (const_int -1)) 1229 (const_int 0)) 1230 (label_ref (match_operand 1 "" "")) 1231 (pc))) 1232 (set (match_dup 0) 1233 (plus:SI (match_dup 0) 1234 (const_int -1)))] 1235 "!TARGET_UNIX_ASM" 1236 "jsobgeq %0,%l1") 1237 1238;; Normal aob insns. Define a version for when operands[1] is a constant. 1239(define_insn "" 1240 [(set (pc) 1241 (if_then_else 1242 (lt (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 1243 (const_int 1)) 1244 (match_operand:SI 1 "general_operand" "nrmT")) 1245 (label_ref (match_operand 2 "" "")) 1246 (pc))) 1247 (set (match_dup 0) 1248 (plus:SI (match_dup 0) 1249 (const_int 1)))] 1250 "!TARGET_UNIX_ASM" 1251 "jaoblss %1,%0,%l2") 1252 1253(define_insn "" 1254 [(set (pc) 1255 (if_then_else 1256 (lt (match_operand:SI 0 "nonimmediate_operand" "+g") 1257 (match_operand:SI 1 "general_operand" "nrmT")) 1258 (label_ref (match_operand 2 "" "")) 1259 (pc))) 1260 (set (match_dup 0) 1261 (plus:SI (match_dup 0) 1262 (const_int 1)))] 1263 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])" 1264 "jaoblss %P1,%0,%l2") 1265 1266(define_insn "" 1267 [(set (pc) 1268 (if_then_else 1269 (le (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+g") 1270 (const_int 1)) 1271 (match_operand:SI 1 "general_operand" "nrmT")) 1272 (label_ref (match_operand 2 "" "")) 1273 (pc))) 1274 (set (match_dup 0) 1275 (plus:SI (match_dup 0) 1276 (const_int 1)))] 1277 "!TARGET_UNIX_ASM" 1278 "jaobleq %1,%0,%l2") 1279 1280(define_insn "" 1281 [(set (pc) 1282 (if_then_else 1283 (le (match_operand:SI 0 "nonimmediate_operand" "+g") 1284 (match_operand:SI 1 "general_operand" "nrmT")) 1285 (label_ref (match_operand 2 "" "")) 1286 (pc))) 1287 (set (match_dup 0) 1288 (plus:SI (match_dup 0) 1289 (const_int 1)))] 1290 "!TARGET_UNIX_ASM && CONST_INT_P (operands[1])" 1291 "jaobleq %P1,%0,%l2") 1292 1293;; Something like a sob insn, but compares against -1. 1294;; This finds `while (foo--)' which was changed to `while (--foo != -1)'. 1295 1296(define_insn "" 1297 [(set (pc) 1298 (if_then_else 1299 (ne (match_operand:SI 0 "nonimmediate_operand" "+g") 1300 (const_int 0)) 1301 (label_ref (match_operand 1 "" "")) 1302 (pc))) 1303 (set (match_dup 0) 1304 (plus:SI (match_dup 0) 1305 (const_int -1)))] 1306 "" 1307 "decl %0\;jgequ %l1") 1308 1309(define_expand "call_pop" 1310 [(parallel [(call (match_operand:QI 0 "memory_operand" "") 1311 (match_operand:SI 1 "const_int_operand" "")) 1312 (set (reg:SI VAX_SP_REGNUM) 1313 (plus:SI (reg:SI VAX_SP_REGNUM) 1314 (match_operand:SI 3 "immediate_operand" "")))])] 1315 "" 1316{ 1317 gcc_assert (INTVAL (operands[3]) <= 255 * 4 && INTVAL (operands[3]) % 4 == 0); 1318 1319 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size 1320 during EH unwinding. We must include the argument count pushed by 1321 the calls instruction. */ 1322 operands[1] = GEN_INT (INTVAL (operands[3]) + 4); 1323}) 1324 1325(define_insn "*call_pop" 1326 [(call (match_operand:QI 0 "memory_operand" "m") 1327 (match_operand:SI 1 "const_int_operand" "n")) 1328 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM) 1329 (match_operand:SI 2 "immediate_operand" "i")))] 1330 "" 1331{ 1332 operands[1] = GEN_INT ((INTVAL (operands[1]) - 4) / 4); 1333 return "calls %1,%0"; 1334}) 1335 1336(define_expand "call_value_pop" 1337 [(parallel [(set (match_operand 0 "" "") 1338 (call (match_operand:QI 1 "memory_operand" "") 1339 (match_operand:SI 2 "const_int_operand" ""))) 1340 (set (reg:SI VAX_SP_REGNUM) 1341 (plus:SI (reg:SI VAX_SP_REGNUM) 1342 (match_operand:SI 4 "immediate_operand" "")))])] 1343 "" 1344{ 1345 gcc_assert (INTVAL (operands[4]) <= 255 * 4 && INTVAL (operands[4]) % 4 == 0); 1346 1347 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size 1348 during EH unwinding. We must include the argument count pushed by 1349 the calls instruction. */ 1350 operands[2] = GEN_INT (INTVAL (operands[4]) + 4); 1351}) 1352 1353(define_insn "*call_value_pop" 1354 [(set (match_operand 0 "" "") 1355 (call (match_operand:QI 1 "memory_operand" "m") 1356 (match_operand:SI 2 "const_int_operand" "n"))) 1357 (set (reg:SI VAX_SP_REGNUM) (plus:SI (reg:SI VAX_SP_REGNUM) 1358 (match_operand:SI 3 "immediate_operand" "i")))] 1359 "" 1360 "* 1361{ 1362 operands[2] = GEN_INT ((INTVAL (operands[2]) - 4) / 4); 1363 return \"calls %2,%1\"; 1364}") 1365 1366(define_expand "call" 1367 [(call (match_operand:QI 0 "memory_operand" "") 1368 (match_operand:SI 1 "const_int_operand" ""))] 1369 "" 1370 " 1371{ 1372 /* Operand 1 is the number of bytes to be popped by DW_CFA_GNU_args_size 1373 during EH unwinding. We must include the argument count pushed by 1374 the calls instruction. */ 1375 operands[1] = GEN_INT (INTVAL (operands[1]) + 4); 1376}") 1377 1378(define_insn "*call" 1379 [(call (match_operand:QI 0 "memory_operand" "m") 1380 (match_operand:SI 1 "const_int_operand" ""))] 1381 "" 1382 "calls $0,%0") 1383 1384(define_expand "call_value" 1385 [(set (match_operand 0 "" "") 1386 (call (match_operand:QI 1 "memory_operand" "") 1387 (match_operand:SI 2 "const_int_operand" "")))] 1388 "" 1389 " 1390{ 1391 /* Operand 2 is the number of bytes to be popped by DW_CFA_GNU_args_size 1392 during EH unwinding. We must include the argument count pushed by 1393 the calls instruction. */ 1394 operands[2] = GEN_INT (INTVAL (operands[2]) + 4); 1395}") 1396 1397(define_insn "*call_value" 1398 [(set (match_operand 0 "" "") 1399 (call (match_operand:QI 1 "memory_operand" "m") 1400 (match_operand:SI 2 "const_int_operand" "")))] 1401 "" 1402 "calls $0,%1") 1403 1404;; Call subroutine returning any type. 1405 1406(define_expand "untyped_call" 1407 [(parallel [(call (match_operand 0 "" "") 1408 (const_int 0)) 1409 (match_operand 1 "" "") 1410 (match_operand 2 "" "")])] 1411 "" 1412 " 1413{ 1414 int i; 1415 1416 emit_call_insn (gen_call_pop (operands[0], const0_rtx, NULL, const0_rtx)); 1417 1418 for (i = 0; i < XVECLEN (operands[2], 0); i++) 1419 { 1420 rtx set = XVECEXP (operands[2], 0, i); 1421 emit_move_insn (SET_DEST (set), SET_SRC (set)); 1422 } 1423 1424 /* The optimizer does not know that the call sets the function value 1425 registers we stored in the result block. We avoid problems by 1426 claiming that all hard registers are used and clobbered at this 1427 point. */ 1428 emit_insn (gen_blockage ()); 1429 1430 DONE; 1431}") 1432 1433;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 1434;; all of memory. This blocks insns from being moved across this point. 1435 1436(define_insn "blockage" 1437 [(unspec_volatile [(const_int 0)] VUNSPEC_BLOCKAGE)] 1438 "" 1439 "") 1440 1441(define_insn "procedure_entry_mask" 1442 [(unspec_volatile [(match_operand 0 "const_int_operand")] VUNSPEC_PEM)] 1443 "" 1444 ".word %x0") 1445 1446(define_insn "return" 1447 [(return)] 1448 "" 1449 "ret") 1450 1451(define_expand "prologue" 1452 [(const_int 0)] 1453 "" 1454{ 1455 vax_expand_prologue (); 1456 DONE; 1457}) 1458 1459(define_expand "epilogue" 1460 [(return)] 1461 "" 1462 " 1463{ 1464 emit_jump_insn (gen_return ()); 1465 DONE; 1466}") 1467 1468(define_insn "nop" 1469 [(const_int 0)] 1470 "" 1471 "nop") 1472 1473;; This had a wider constraint once, and it had trouble. 1474;; If you are tempted to try `g', please don't--it's not worth 1475;; the risk we will reopen the same bug. 1476(define_insn "indirect_jump" 1477 [(set (pc) (match_operand:SI 0 "register_operand" "r"))] 1478 "" 1479 "jmp (%0)") 1480 1481;; This is here to accept 5 arguments (as passed by expand_end_case) 1482;; and pass the first 4 along to the casesi1 pattern that really does 1483;; the actual casesi work. We emit a jump here to the default label 1484;; _before_ the casesi so that we can be sure that the casesi never 1485;; drops through. 1486;; This is suboptimal perhaps, but so is much of the rest of this 1487;; machine description. For what it's worth, HPPA uses the same trick. 1488;; 1489;; operand 0 is index 1490;; operand 1 is the minimum bound (a const_int) 1491;; operand 2 is the maximum bound - minimum bound + 1 (also a const_int) 1492;; operand 3 is CODE_LABEL for the table; 1493;; operand 4 is the CODE_LABEL to go to if index out of range (ie. default). 1494;; 1495;; We emit: 1496;; i = index - minimum_bound 1497;; if (i > (maximum_bound - minimum_bound + 1) goto default; 1498;; casesi (i, 0, table); 1499;; 1500(define_expand "casesi" 1501 [(match_operand:SI 0 "general_operand" "") 1502 (match_operand:SI 1 "general_operand" "") 1503 (match_operand:SI 2 "general_operand" "") 1504 (match_operand 3 "" "") 1505 (match_operand 4 "" "")] 1506 "" 1507{ 1508 rtx test; 1509 1510 /* i = index - minimum_bound; 1511 But only if the lower bound is not already zero. */ 1512 if (operands[1] != const0_rtx) 1513 { 1514 rtx index = gen_reg_rtx (SImode); 1515 emit_insn (gen_addsi3 (index, 1516 operands[0], 1517 GEN_INT (-INTVAL (operands[1])))); 1518 operands[0] = index; 1519 } 1520 1521 /* if (i > (maximum_bound - minimum_bound + 1)) goto default; */ 1522 test = gen_rtx_fmt_ee (GTU, VOIDmode, operands[0], operands[2]); 1523 emit_jump_insn (gen_cbranchsi4 (test, operands[0], operands[2], operands[4])); 1524 1525 /* casesi (i, 0, table); */ 1526 emit_jump_insn (gen_casesi1 (operands[0], operands[2], operands[3])); 1527 DONE; 1528}) 1529 1530;; This insn is a bit of a lier. It actually falls through if no case 1531;; matches. But, we prevent that from ever happening by emitting a jump 1532;; before this, see the define_expand above. 1533(define_insn "casesi1" 1534 [(match_operand:SI 1 "const_int_operand" "n") 1535 (set (pc) 1536 (plus:SI (sign_extend:SI 1537 (mem:HI (plus:SI (mult:SI (match_operand:SI 0 "general_operand" "nrmT") 1538 (const_int 2)) 1539 (pc)))) 1540 (label_ref:SI (match_operand 2 "" ""))))] 1541 "" 1542 "casel %0,$0,%1") 1543 1544(define_insn "pushextsym" 1545 [(set (match_operand:SI 0 "push_operand" "=g") 1546 (match_operand:SI 1 "external_symbolic_operand" "i"))] 1547 "" 1548 "pushab %a1") 1549 1550(define_insn "movextsym" 1551 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1552 (match_operand:SI 1 "external_symbolic_operand" "i"))] 1553 "" 1554 "movab %a1,%0") 1555 1556(define_insn "pushlclsym" 1557 [(set (match_operand:SI 0 "push_operand" "=g") 1558 (match_operand:SI 1 "local_symbolic_operand" "i"))] 1559 "" 1560 "pushab %a1") 1561 1562(define_insn "movlclsym" 1563 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1564 (match_operand:SI 1 "local_symbolic_operand" "i"))] 1565 "" 1566 "movab %a1,%0") 1567 1568;;- load or push effective address 1569;; These come after the move and add/sub patterns 1570;; because we don't want pushl $1 turned into pushad 1. 1571;; or addl3 r1,r2,r3 turned into movab 0(r1)[r2],r3. 1572 1573;; It does not work to use constraints to distinguish pushes from moves, 1574;; because < matches any autodecrement, not just a push. 1575 1576(define_insn "pushaddr<mode>" 1577 [(set (match_operand:SI 0 "push_operand" "=g") 1578 (match_operand:VAXintQHSD 1 "address_operand" "p"))] 1579 "" 1580 "pusha<VAXintQHSD:isfx> %a1") 1581 1582(define_insn "movaddr<mode>" 1583 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1584 (match_operand:VAXintQHSD 1 "address_operand" "p"))] 1585 "" 1586 "mova<VAXintQHSD:isfx> %a1,%0") 1587 1588(define_insn "pushaddr<mode>" 1589 [(set (match_operand:SI 0 "push_operand" "=g") 1590 (match_operand:VAXfp 1 "address_operand" "p"))] 1591 "" 1592 "pusha<VAXfp:fsfx> %a1") 1593 1594(define_insn "movaddr<mode>" 1595 [(set (match_operand:SI 0 "nonimmediate_operand" "=g") 1596 (match_operand:VAXfp 1 "address_operand" "p"))] 1597 "" 1598 "mova<VAXfp:fsfx> %a1,%0") 1599 1600;; These used to be peepholes, but it is more straightforward to do them 1601;; as single insns. However, we must force the output to be a register 1602;; if it is not an offsettable address so that we know that we can assign 1603;; to it twice. 1604 1605;; If we had a good way of evaluating the relative costs, these could be 1606;; machine-independent. 1607 1608;; Optimize extzv ...,z; andl2 ...,z 1609;; or ashl ...,z; andl2 ...,z 1610;; with other operands constant. This is what the combiner converts the 1611;; above sequences to before attempting to recognize the new insn. 1612 1613(define_insn "" 1614 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 1615 (and:SI (ashiftrt:SI (match_operand:SI 1 "general_operand" "nrmT") 1616 (match_operand:QI 2 "const_int_operand" "n")) 1617 (match_operand:SI 3 "const_int_operand" "n")))] 1618 "(INTVAL (operands[3]) & ~((1 << (32 - INTVAL (operands[2]))) - 1)) == 0" 1619 "* 1620{ 1621 unsigned long mask1 = INTVAL (operands[3]); 1622 unsigned long mask2 = (1 << (32 - INTVAL (operands[2]))) - 1; 1623 1624 if ((mask1 & mask2) != mask1) 1625 operands[3] = GEN_INT (mask1 & mask2); 1626 1627 return \"rotl %R2,%1,%0\;bicl2 %N3,%0\"; 1628}") 1629 1630;; left-shift and mask 1631;; The only case where `ashl' is better is if the mask only turns off 1632;; bits that the ashl would anyways, in which case it should have been 1633;; optimized away. 1634 1635(define_insn "" 1636 [(set (match_operand:SI 0 "nonimmediate_operand" "=ro") 1637 (and:SI (ashift:SI (match_operand:SI 1 "general_operand" "nrmT") 1638 (match_operand:QI 2 "const_int_operand" "n")) 1639 (match_operand:SI 3 "const_int_operand" "n")))] 1640 "" 1641 "* 1642{ 1643 operands[3] 1644 = GEN_INT (INTVAL (operands[3]) & ~((1 << INTVAL (operands[2])) - 1)); 1645 return \"rotl %2,%1,%0\;bicl2 %N3,%0\"; 1646}") 1647 1648;; Instruction sequence to sync the VAX instruction stream. 1649(define_insn "sync_istream" 1650 [(unspec_volatile [(const_int 0)] VUNSPEC_SYNC_ISTREAM)] 1651 "" 1652 "movpsl -(%|sp)\;pushal 1(%|pc)\;rei") 1653 1654(define_expand "nonlocal_goto" 1655 [(use (match_operand 0 "general_operand" "")) 1656 (use (match_operand 1 "general_operand" "")) 1657 (use (match_operand 2 "general_operand" "")) 1658 (use (match_operand 3 "general_operand" ""))] 1659 "" 1660{ 1661 rtx lab = operands[1]; 1662 rtx stack = operands[2]; 1663 rtx fp = operands[3]; 1664 1665 emit_clobber (gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (VOIDmode))); 1666 emit_clobber (gen_rtx_MEM (BLKmode, hard_frame_pointer_rtx)); 1667 1668 emit_move_insn (hard_frame_pointer_rtx, fp); 1669 emit_stack_restore (SAVE_NONLOCAL, stack); 1670 1671 emit_use (hard_frame_pointer_rtx); 1672 emit_use (stack_pointer_rtx); 1673 1674 /* We'll convert this to direct jump via a peephole optimization. */ 1675 emit_indirect_jump (copy_to_reg (lab)); 1676 emit_barrier (); 1677 DONE; 1678}) 1679 1680(include "builtins.md") 1681 1682(define_peephole2 1683 [(set (match_operand:SI 0 "push_operand" "") 1684 (const_int 0)) 1685 (set (match_dup 0) 1686 (match_operand:SI 1 "const_int_operand" ""))] 1687 "INTVAL (operands[1]) >= 0" 1688 [(set (match_dup 0) 1689 (match_dup 1))] 1690 "operands[0] = gen_rtx_MEM(DImode, XEXP (operands[0], 0));") 1691 1692(define_peephole2 1693 [(set (match_operand:SI 0 "push_operand" "") 1694 (match_operand:SI 1 "general_operand" "")) 1695 (set (match_dup 0) 1696 (match_operand:SI 2 "general_operand" ""))] 1697 "vax_decomposed_dimode_operand_p (operands[2], operands[1])" 1698 [(set (match_dup 0) 1699 (match_dup 2))] 1700 "{ 1701 operands[0] = gen_rtx_MEM(DImode, XEXP (operands[0], 0)); 1702 operands[2] = REG_P (operands[2]) 1703 ? gen_rtx_REG(DImode, REGNO (operands[2])) 1704 : gen_rtx_MEM(DImode, XEXP (operands[2], 0)); 1705}") 1706 1707; Leave this commented out until we can determine whether the second move 1708; precedes a jump which relies on the CC flags being set correctly. 1709(define_peephole2 1710 [(set (match_operand:SI 0 "nonimmediate_operand" "") 1711 (match_operand:SI 1 "general_operand" "")) 1712 (set (match_operand:SI 2 "nonimmediate_operand" "") 1713 (match_operand:SI 3 "general_operand" ""))] 1714 "0 && vax_decomposed_dimode_operand_p (operands[1], operands[3]) 1715 && vax_decomposed_dimode_operand_p (operands[0], operands[2])" 1716 [(set (match_dup 0) 1717 (match_dup 1))] 1718 "{ 1719 operands[0] = REG_P (operands[0]) 1720 ? gen_rtx_REG(DImode, REGNO (operands[0])) 1721 : gen_rtx_MEM(DImode, XEXP (operands[0], 0)); 1722 operands[1] = REG_P (operands[1]) 1723 ? gen_rtx_REG(DImode, REGNO (operands[1])) 1724 : gen_rtx_MEM(DImode, XEXP (operands[1], 0)); 1725}") 1726