1;; GCC machine description for SPARC synchronization instructions. 2;; Copyright (C) 2005-2013 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_mode_iterator I12MODE [QI HI]) 21(define_mode_iterator I124MODE [QI HI SI]) 22(define_mode_iterator I24MODE [HI SI]) 23(define_mode_iterator I48MODE [SI (DI "TARGET_ARCH64 || TARGET_V8PLUS")]) 24(define_mode_attr modesuffix [(SI "") (DI "x")]) 25 26(define_expand "mem_thread_fence" 27 [(match_operand:SI 0 "const_int_operand")] 28 "TARGET_V8 || TARGET_V9" 29{ 30 enum memmodel model = (enum memmodel) INTVAL (operands[0]); 31 sparc_emit_membar_for_model (model, 3, 3); 32 DONE; 33}) 34 35(define_expand "membar" 36 [(set (match_dup 1) 37 (unspec:BLK [(match_dup 1) (match_operand:SI 0 "const_int_operand")] 38 UNSPEC_MEMBAR))] 39 "TARGET_V8 || TARGET_V9" 40{ 41 operands[1] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 42 MEM_VOLATILE_P (operands[1]) = 1; 43}) 44 45;; A compiler-only memory barrier. Generic code, when checking for the 46;; existence of various named patterns, uses asm("":::"memory") when we 47;; don't need an actual instruction. Here, it's easiest to pretend that 48;; membar 0 is such a barrier. Further, this gives us a nice hook to 49;; ignore all such barriers on Sparc V7. 50(define_insn "*membar_empty" 51 [(set (match_operand:BLK 0 "" "") 52 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "zero_or_v7_operand")] 53 UNSPEC_MEMBAR))] 54 "" 55 "" 56 [(set_attr "type" "multi") 57 (set_attr "length" "0")]) 58 59;; For V8, STBAR is exactly membar #StoreStore, by definition. 60(define_insn "*membar_storestore" 61 [(set (match_operand:BLK 0 "" "") 62 (unspec:BLK [(match_dup 0) (const_int 8)] UNSPEC_MEMBAR))] 63 "TARGET_V8" 64 "stbar" 65 [(set_attr "type" "multi")]) 66 67;; For LEON3, STB has the effect of membar #StoreLoad. 68(define_insn "*membar_storeload_leon3" 69 [(set (match_operand:BLK 0 "" "") 70 (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))] 71 "TARGET_LEON3" 72 "stb\t%%g0, [%%sp-1]" 73 [(set_attr "type" "store")]) 74 75;; For V8, LDSTUB has the effect of membar #StoreLoad. 76(define_insn "*membar_storeload" 77 [(set (match_operand:BLK 0 "" "") 78 (unspec:BLK [(match_dup 0) (const_int 2)] UNSPEC_MEMBAR))] 79 "TARGET_V8 && !TARGET_LEON3" 80 "ldstub\t[%%sp-1], %%g0" 81 [(set_attr "type" "multi")]) 82 83;; Put the two together, in combination with the fact that V8 implements PSO 84;; as its weakest memory model, means a full barrier. Match all remaining 85;; instances of the membar pattern for Sparc V8. 86(define_insn "*membar_v8" 87 [(set (match_operand:BLK 0 "" "") 88 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] 89 UNSPEC_MEMBAR))] 90 "TARGET_V8" 91 "stbar\n\tldstub\t[%%sp-1], %%g0" 92 [(set_attr "type" "multi") 93 (set_attr "length" "2")]) 94 95;; For V9, we have the full membar instruction. 96(define_insn "*membar" 97 [(set (match_operand:BLK 0 "" "") 98 (unspec:BLK [(match_dup 0) (match_operand:SI 1 "const_int_operand")] 99 UNSPEC_MEMBAR))] 100 "TARGET_V9" 101 "membar\t%1" 102 [(set_attr "type" "multi")]) 103 104(define_expand "atomic_load<mode>" 105 [(match_operand:I 0 "register_operand" "") 106 (match_operand:I 1 "memory_operand" "") 107 (match_operand:SI 2 "const_int_operand" "")] 108 "" 109{ 110 enum memmodel model = (enum memmodel) INTVAL (operands[2]); 111 112 sparc_emit_membar_for_model (model, 1, 1); 113 114 if (TARGET_ARCH64 || <MODE>mode != DImode) 115 emit_move_insn (operands[0], operands[1]); 116 else 117 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); 118 119 sparc_emit_membar_for_model (model, 1, 2); 120 DONE; 121}) 122 123(define_insn "atomic_loaddi_1" 124 [(set (match_operand:DI 0 "register_operand" "=U,?*f") 125 (unspec:DI [(match_operand:DI 1 "memory_operand" "m,m")] 126 UNSPEC_ATOMIC))] 127 "!TARGET_ARCH64" 128 "ldd\t%1, %0" 129 [(set_attr "type" "load,fpload")]) 130 131(define_expand "atomic_store<mode>" 132 [(match_operand:I 0 "memory_operand" "") 133 (match_operand:I 1 "register_operand" "") 134 (match_operand:SI 2 "const_int_operand" "")] 135 "" 136{ 137 enum memmodel model = (enum memmodel) INTVAL (operands[2]); 138 139 sparc_emit_membar_for_model (model, 2, 1); 140 141 if (TARGET_ARCH64 || <MODE>mode != DImode) 142 emit_move_insn (operands[0], operands[1]); 143 else 144 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); 145 146 sparc_emit_membar_for_model (model, 2, 2); 147 DONE; 148}) 149 150(define_insn "atomic_storedi_1" 151 [(set (match_operand:DI 0 "memory_operand" "=m,m,m") 152 (unspec:DI 153 [(match_operand:DI 1 "register_or_v9_zero_operand" "J,U,?*f")] 154 UNSPEC_ATOMIC))] 155 "!TARGET_ARCH64" 156 "@ 157 stx\t%r1, %0 158 std\t%1, %0 159 std\t%1, %0" 160 [(set_attr "type" "store,store,fpstore") 161 (set_attr "cpu_feature" "v9,*,*")]) 162 163(define_expand "atomic_compare_and_swap<mode>" 164 [(match_operand:SI 0 "register_operand" "") ;; bool output 165 (match_operand:I 1 "register_operand" "") ;; val output 166 (match_operand:I 2 "mem_noofs_operand" "") ;; memory 167 (match_operand:I 3 "register_operand" "") ;; expected 168 (match_operand:I 4 "register_operand" "") ;; desired 169 (match_operand:SI 5 "const_int_operand" "") ;; is_weak 170 (match_operand:SI 6 "const_int_operand" "") ;; mod_s 171 (match_operand:SI 7 "const_int_operand" "")] ;; mod_f 172 "(TARGET_V9 || TARGET_LEON3) 173 && (<MODE>mode != DImode || TARGET_ARCH64 || TARGET_V8PLUS)" 174{ 175 sparc_expand_compare_and_swap (operands); 176 DONE; 177}) 178 179(define_expand "atomic_compare_and_swap<mode>_1" 180 [(parallel 181 [(set (match_operand:I48MODE 0 "register_operand" "") 182 (match_operand:I48MODE 1 "mem_noofs_operand" "")) 183 (set (match_dup 1) 184 (unspec_volatile:I48MODE 185 [(match_operand:I48MODE 2 "register_operand" "") 186 (match_operand:I48MODE 3 "register_operand" "")] 187 UNSPECV_CAS))])] 188 "TARGET_V9 || TARGET_LEON3" 189 "") 190 191(define_insn "*atomic_compare_and_swap<mode>_1" 192 [(set (match_operand:I48MODE 0 "register_operand" "=r") 193 (match_operand:I48MODE 1 "mem_noofs_operand" "+w")) 194 (set (match_dup 1) 195 (unspec_volatile:I48MODE 196 [(match_operand:I48MODE 2 "register_operand" "r") 197 (match_operand:I48MODE 3 "register_operand" "0")] 198 UNSPECV_CAS))] 199 "TARGET_V9 && (<MODE>mode != DImode || TARGET_ARCH64)" 200 "cas<modesuffix>\t%1, %2, %0" 201 [(set_attr "type" "multi")]) 202 203(define_insn "*atomic_compare_and_swap_leon3_1" 204 [(set (match_operand:SI 0 "register_operand" "=r") 205 (match_operand:SI 1 "mem_noofs_operand" "+w")) 206 (set (match_dup 1) 207 (unspec_volatile:SI 208 [(match_operand:SI 2 "register_operand" "r") 209 (match_operand:SI 3 "register_operand" "0")] 210 UNSPECV_CAS))] 211 "TARGET_LEON3" 212{ 213 if (TARGET_USER_MODE) 214 return "casa\t%1 0xa, %2, %0"; /* ASI for user data space. */ 215 else 216 return "casa\t%1 0xb, %2, %0"; /* ASI for supervisor data space. */ 217} 218 [(set_attr "type" "multi")]) 219 220(define_insn "*atomic_compare_and_swapdi_v8plus" 221 [(set (match_operand:DI 0 "register_operand" "=h") 222 (match_operand:DI 1 "mem_noofs_operand" "+w")) 223 (set (match_dup 1) 224 (unspec_volatile:DI 225 [(match_operand:DI 2 "register_operand" "h") 226 (match_operand:DI 3 "register_operand" "0")] 227 UNSPECV_CAS))] 228 "TARGET_V8PLUS" 229{ 230 if (sparc_check_64 (operands[3], insn) <= 0) 231 output_asm_insn ("srl\t%L3, 0, %L3", operands); 232 output_asm_insn ("sllx\t%H3, 32, %H3", operands); 233 output_asm_insn ("or\t%L3, %H3, %L3", operands); 234 if (sparc_check_64 (operands[2], insn) <= 0) 235 output_asm_insn ("srl\t%L2, 0, %L2", operands); 236 output_asm_insn ("sllx\t%H2, 32, %H3", operands); 237 output_asm_insn ("or\t%L2, %H3, %H3", operands); 238 output_asm_insn ("casx\t%1, %H3, %L3", operands); 239 return "srlx\t%L3, 32, %H3"; 240} 241 [(set_attr "type" "multi") 242 (set_attr "length" "8")]) 243 244(define_expand "atomic_exchangesi" 245 [(match_operand:SI 0 "register_operand" "") 246 (match_operand:SI 1 "memory_operand" "") 247 (match_operand:SI 2 "register_operand" "") 248 (match_operand:SI 3 "const_int_operand" "")] 249 "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699" 250{ 251 enum memmodel model = (enum memmodel) INTVAL (operands[3]); 252 253 sparc_emit_membar_for_model (model, 3, 1); 254 emit_insn (gen_swapsi (operands[0], operands[1], operands[2])); 255 sparc_emit_membar_for_model (model, 3, 2); 256 DONE; 257}) 258 259(define_insn "swapsi" 260 [(set (match_operand:SI 0 "register_operand" "=r") 261 (unspec_volatile:SI [(match_operand:SI 1 "memory_operand" "+m")] 262 UNSPECV_SWAP)) 263 (set (match_dup 1) 264 (match_operand:SI 2 "register_operand" "0"))] 265 "(TARGET_V8 || TARGET_V9) && !sparc_fix_ut699" 266 "swap\t%1, %0" 267 [(set_attr "type" "multi")]) 268 269(define_expand "atomic_test_and_set" 270 [(match_operand:QI 0 "register_operand" "") 271 (match_operand:QI 1 "memory_operand" "") 272 (match_operand:SI 2 "const_int_operand" "")] 273 "!sparc_fix_ut699" 274{ 275 enum memmodel model = (enum memmodel) INTVAL (operands[2]); 276 rtx ret; 277 278 sparc_emit_membar_for_model (model, 3, 1); 279 emit_insn (gen_ldstub (operands[0], operands[1])); 280 sparc_emit_membar_for_model (model, 3, 2); 281 282 /* Convert the 0/0xff result we would otherwise have to a boolean. 283 I.e. ignore all but bit 0. */ 284 ret = expand_simple_binop (QImode, AND, operands[0], const1_rtx, 285 operands[0], true, OPTAB_LIB_WIDEN); 286 if (ret != operands[0]) 287 emit_move_insn (operands[0], ret); 288 289 DONE; 290}) 291 292(define_insn "ldstub" 293 [(set (match_operand:QI 0 "register_operand" "=r") 294 (unspec_volatile:QI [(match_operand:QI 1 "memory_operand" "+m")] 295 UNSPECV_LDSTUB)) 296 (set (match_dup 1) (const_int -1))] 297 "!sparc_fix_ut699" 298 "ldstub\t%1, %0" 299 [(set_attr "type" "multi")]) 300