1 /* Subroutines for insn-output.c for SPARC. 2 Copyright (C) 1987-2017 Free Software Foundation, Inc. 3 Contributed by Michael Tiemann (tiemann@cygnus.com) 4 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans, 5 at Cygnus Support. 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 GCC is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #include "config.h" 24 #include "system.h" 25 #include "coretypes.h" 26 #include "backend.h" 27 #include "target.h" 28 #include "rtl.h" 29 #include "tree.h" 30 #include "memmodel.h" 31 #include "gimple.h" 32 #include "df.h" 33 #include "tm_p.h" 34 #include "stringpool.h" 35 #include "expmed.h" 36 #include "optabs.h" 37 #include "regs.h" 38 #include "emit-rtl.h" 39 #include "recog.h" 40 #include "diagnostic-core.h" 41 #include "alias.h" 42 #include "fold-const.h" 43 #include "stor-layout.h" 44 #include "calls.h" 45 #include "varasm.h" 46 #include "output.h" 47 #include "insn-attr.h" 48 #include "explow.h" 49 #include "expr.h" 50 #include "debug.h" 51 #include "common/common-target.h" 52 #include "gimplify.h" 53 #include "langhooks.h" 54 #include "reload.h" 55 #include "params.h" 56 #include "tree-pass.h" 57 #include "context.h" 58 #include "builtins.h" 59 60 /* This file should be included last. */ 61 #include "target-def.h" 62 63 /* Processor costs */ 64 65 struct processor_costs { 66 /* Integer load */ 67 const int int_load; 68 69 /* Integer signed load */ 70 const int int_sload; 71 72 /* Integer zeroed load */ 73 const int int_zload; 74 75 /* Float load */ 76 const int float_load; 77 78 /* fmov, fneg, fabs */ 79 const int float_move; 80 81 /* fadd, fsub */ 82 const int float_plusminus; 83 84 /* fcmp */ 85 const int float_cmp; 86 87 /* fmov, fmovr */ 88 const int float_cmove; 89 90 /* fmul */ 91 const int float_mul; 92 93 /* fdivs */ 94 const int float_div_sf; 95 96 /* fdivd */ 97 const int float_div_df; 98 99 /* fsqrts */ 100 const int float_sqrt_sf; 101 102 /* fsqrtd */ 103 const int float_sqrt_df; 104 105 /* umul/smul */ 106 const int int_mul; 107 108 /* mulX */ 109 const int int_mulX; 110 111 /* integer multiply cost for each bit set past the most 112 significant 3, so the formula for multiply cost becomes: 113 114 if (rs1 < 0) 115 highest_bit = highest_clear_bit(rs1); 116 else 117 highest_bit = highest_set_bit(rs1); 118 if (highest_bit < 3) 119 highest_bit = 3; 120 cost = int_mul{,X} + ((highest_bit - 3) / int_mul_bit_factor); 121 122 A value of zero indicates that the multiply costs is fixed, 123 and not variable. */ 124 const int int_mul_bit_factor; 125 126 /* udiv/sdiv */ 127 const int int_div; 128 129 /* divX */ 130 const int int_divX; 131 132 /* movcc, movr */ 133 const int int_cmove; 134 135 /* penalty for shifts, due to scheduling rules etc. */ 136 const int shift_penalty; 137 }; 138 139 static const 140 struct processor_costs cypress_costs = { 141 COSTS_N_INSNS (2), /* int load */ 142 COSTS_N_INSNS (2), /* int signed load */ 143 COSTS_N_INSNS (2), /* int zeroed load */ 144 COSTS_N_INSNS (2), /* float load */ 145 COSTS_N_INSNS (5), /* fmov, fneg, fabs */ 146 COSTS_N_INSNS (5), /* fadd, fsub */ 147 COSTS_N_INSNS (1), /* fcmp */ 148 COSTS_N_INSNS (1), /* fmov, fmovr */ 149 COSTS_N_INSNS (7), /* fmul */ 150 COSTS_N_INSNS (37), /* fdivs */ 151 COSTS_N_INSNS (37), /* fdivd */ 152 COSTS_N_INSNS (63), /* fsqrts */ 153 COSTS_N_INSNS (63), /* fsqrtd */ 154 COSTS_N_INSNS (1), /* imul */ 155 COSTS_N_INSNS (1), /* imulX */ 156 0, /* imul bit factor */ 157 COSTS_N_INSNS (1), /* idiv */ 158 COSTS_N_INSNS (1), /* idivX */ 159 COSTS_N_INSNS (1), /* movcc/movr */ 160 0, /* shift penalty */ 161 }; 162 163 static const 164 struct processor_costs supersparc_costs = { 165 COSTS_N_INSNS (1), /* int load */ 166 COSTS_N_INSNS (1), /* int signed load */ 167 COSTS_N_INSNS (1), /* int zeroed load */ 168 COSTS_N_INSNS (0), /* float load */ 169 COSTS_N_INSNS (3), /* fmov, fneg, fabs */ 170 COSTS_N_INSNS (3), /* fadd, fsub */ 171 COSTS_N_INSNS (3), /* fcmp */ 172 COSTS_N_INSNS (1), /* fmov, fmovr */ 173 COSTS_N_INSNS (3), /* fmul */ 174 COSTS_N_INSNS (6), /* fdivs */ 175 COSTS_N_INSNS (9), /* fdivd */ 176 COSTS_N_INSNS (12), /* fsqrts */ 177 COSTS_N_INSNS (12), /* fsqrtd */ 178 COSTS_N_INSNS (4), /* imul */ 179 COSTS_N_INSNS (4), /* imulX */ 180 0, /* imul bit factor */ 181 COSTS_N_INSNS (4), /* idiv */ 182 COSTS_N_INSNS (4), /* idivX */ 183 COSTS_N_INSNS (1), /* movcc/movr */ 184 1, /* shift penalty */ 185 }; 186 187 static const 188 struct processor_costs hypersparc_costs = { 189 COSTS_N_INSNS (1), /* int load */ 190 COSTS_N_INSNS (1), /* int signed load */ 191 COSTS_N_INSNS (1), /* int zeroed load */ 192 COSTS_N_INSNS (1), /* float load */ 193 COSTS_N_INSNS (1), /* fmov, fneg, fabs */ 194 COSTS_N_INSNS (1), /* fadd, fsub */ 195 COSTS_N_INSNS (1), /* fcmp */ 196 COSTS_N_INSNS (1), /* fmov, fmovr */ 197 COSTS_N_INSNS (1), /* fmul */ 198 COSTS_N_INSNS (8), /* fdivs */ 199 COSTS_N_INSNS (12), /* fdivd */ 200 COSTS_N_INSNS (17), /* fsqrts */ 201 COSTS_N_INSNS (17), /* fsqrtd */ 202 COSTS_N_INSNS (17), /* imul */ 203 COSTS_N_INSNS (17), /* imulX */ 204 0, /* imul bit factor */ 205 COSTS_N_INSNS (17), /* idiv */ 206 COSTS_N_INSNS (17), /* idivX */ 207 COSTS_N_INSNS (1), /* movcc/movr */ 208 0, /* shift penalty */ 209 }; 210 211 static const 212 struct processor_costs leon_costs = { 213 COSTS_N_INSNS (1), /* int load */ 214 COSTS_N_INSNS (1), /* int signed load */ 215 COSTS_N_INSNS (1), /* int zeroed load */ 216 COSTS_N_INSNS (1), /* float load */ 217 COSTS_N_INSNS (1), /* fmov, fneg, fabs */ 218 COSTS_N_INSNS (1), /* fadd, fsub */ 219 COSTS_N_INSNS (1), /* fcmp */ 220 COSTS_N_INSNS (1), /* fmov, fmovr */ 221 COSTS_N_INSNS (1), /* fmul */ 222 COSTS_N_INSNS (15), /* fdivs */ 223 COSTS_N_INSNS (15), /* fdivd */ 224 COSTS_N_INSNS (23), /* fsqrts */ 225 COSTS_N_INSNS (23), /* fsqrtd */ 226 COSTS_N_INSNS (5), /* imul */ 227 COSTS_N_INSNS (5), /* imulX */ 228 0, /* imul bit factor */ 229 COSTS_N_INSNS (5), /* idiv */ 230 COSTS_N_INSNS (5), /* idivX */ 231 COSTS_N_INSNS (1), /* movcc/movr */ 232 0, /* shift penalty */ 233 }; 234 235 static const 236 struct processor_costs leon3_costs = { 237 COSTS_N_INSNS (1), /* int load */ 238 COSTS_N_INSNS (1), /* int signed load */ 239 COSTS_N_INSNS (1), /* int zeroed load */ 240 COSTS_N_INSNS (1), /* float load */ 241 COSTS_N_INSNS (1), /* fmov, fneg, fabs */ 242 COSTS_N_INSNS (1), /* fadd, fsub */ 243 COSTS_N_INSNS (1), /* fcmp */ 244 COSTS_N_INSNS (1), /* fmov, fmovr */ 245 COSTS_N_INSNS (1), /* fmul */ 246 COSTS_N_INSNS (14), /* fdivs */ 247 COSTS_N_INSNS (15), /* fdivd */ 248 COSTS_N_INSNS (22), /* fsqrts */ 249 COSTS_N_INSNS (23), /* fsqrtd */ 250 COSTS_N_INSNS (5), /* imul */ 251 COSTS_N_INSNS (5), /* imulX */ 252 0, /* imul bit factor */ 253 COSTS_N_INSNS (35), /* idiv */ 254 COSTS_N_INSNS (35), /* idivX */ 255 COSTS_N_INSNS (1), /* movcc/movr */ 256 0, /* shift penalty */ 257 }; 258 259 static const 260 struct processor_costs sparclet_costs = { 261 COSTS_N_INSNS (3), /* int load */ 262 COSTS_N_INSNS (3), /* int signed load */ 263 COSTS_N_INSNS (1), /* int zeroed load */ 264 COSTS_N_INSNS (1), /* float load */ 265 COSTS_N_INSNS (1), /* fmov, fneg, fabs */ 266 COSTS_N_INSNS (1), /* fadd, fsub */ 267 COSTS_N_INSNS (1), /* fcmp */ 268 COSTS_N_INSNS (1), /* fmov, fmovr */ 269 COSTS_N_INSNS (1), /* fmul */ 270 COSTS_N_INSNS (1), /* fdivs */ 271 COSTS_N_INSNS (1), /* fdivd */ 272 COSTS_N_INSNS (1), /* fsqrts */ 273 COSTS_N_INSNS (1), /* fsqrtd */ 274 COSTS_N_INSNS (5), /* imul */ 275 COSTS_N_INSNS (5), /* imulX */ 276 0, /* imul bit factor */ 277 COSTS_N_INSNS (5), /* idiv */ 278 COSTS_N_INSNS (5), /* idivX */ 279 COSTS_N_INSNS (1), /* movcc/movr */ 280 0, /* shift penalty */ 281 }; 282 283 static const 284 struct processor_costs ultrasparc_costs = { 285 COSTS_N_INSNS (2), /* int load */ 286 COSTS_N_INSNS (3), /* int signed load */ 287 COSTS_N_INSNS (2), /* int zeroed load */ 288 COSTS_N_INSNS (2), /* float load */ 289 COSTS_N_INSNS (1), /* fmov, fneg, fabs */ 290 COSTS_N_INSNS (4), /* fadd, fsub */ 291 COSTS_N_INSNS (1), /* fcmp */ 292 COSTS_N_INSNS (2), /* fmov, fmovr */ 293 COSTS_N_INSNS (4), /* fmul */ 294 COSTS_N_INSNS (13), /* fdivs */ 295 COSTS_N_INSNS (23), /* fdivd */ 296 COSTS_N_INSNS (13), /* fsqrts */ 297 COSTS_N_INSNS (23), /* fsqrtd */ 298 COSTS_N_INSNS (4), /* imul */ 299 COSTS_N_INSNS (4), /* imulX */ 300 2, /* imul bit factor */ 301 COSTS_N_INSNS (37), /* idiv */ 302 COSTS_N_INSNS (68), /* idivX */ 303 COSTS_N_INSNS (2), /* movcc/movr */ 304 2, /* shift penalty */ 305 }; 306 307 static const 308 struct processor_costs ultrasparc3_costs = { 309 COSTS_N_INSNS (2), /* int load */ 310 COSTS_N_INSNS (3), /* int signed load */ 311 COSTS_N_INSNS (3), /* int zeroed load */ 312 COSTS_N_INSNS (2), /* float load */ 313 COSTS_N_INSNS (3), /* fmov, fneg, fabs */ 314 COSTS_N_INSNS (4), /* fadd, fsub */ 315 COSTS_N_INSNS (5), /* fcmp */ 316 COSTS_N_INSNS (3), /* fmov, fmovr */ 317 COSTS_N_INSNS (4), /* fmul */ 318 COSTS_N_INSNS (17), /* fdivs */ 319 COSTS_N_INSNS (20), /* fdivd */ 320 COSTS_N_INSNS (20), /* fsqrts */ 321 COSTS_N_INSNS (29), /* fsqrtd */ 322 COSTS_N_INSNS (6), /* imul */ 323 COSTS_N_INSNS (6), /* imulX */ 324 0, /* imul bit factor */ 325 COSTS_N_INSNS (40), /* idiv */ 326 COSTS_N_INSNS (71), /* idivX */ 327 COSTS_N_INSNS (2), /* movcc/movr */ 328 0, /* shift penalty */ 329 }; 330 331 static const 332 struct processor_costs niagara_costs = { 333 COSTS_N_INSNS (3), /* int load */ 334 COSTS_N_INSNS (3), /* int signed load */ 335 COSTS_N_INSNS (3), /* int zeroed load */ 336 COSTS_N_INSNS (9), /* float load */ 337 COSTS_N_INSNS (8), /* fmov, fneg, fabs */ 338 COSTS_N_INSNS (8), /* fadd, fsub */ 339 COSTS_N_INSNS (26), /* fcmp */ 340 COSTS_N_INSNS (8), /* fmov, fmovr */ 341 COSTS_N_INSNS (29), /* fmul */ 342 COSTS_N_INSNS (54), /* fdivs */ 343 COSTS_N_INSNS (83), /* fdivd */ 344 COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */ 345 COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */ 346 COSTS_N_INSNS (11), /* imul */ 347 COSTS_N_INSNS (11), /* imulX */ 348 0, /* imul bit factor */ 349 COSTS_N_INSNS (72), /* idiv */ 350 COSTS_N_INSNS (72), /* idivX */ 351 COSTS_N_INSNS (1), /* movcc/movr */ 352 0, /* shift penalty */ 353 }; 354 355 static const 356 struct processor_costs niagara2_costs = { 357 COSTS_N_INSNS (3), /* int load */ 358 COSTS_N_INSNS (3), /* int signed load */ 359 COSTS_N_INSNS (3), /* int zeroed load */ 360 COSTS_N_INSNS (3), /* float load */ 361 COSTS_N_INSNS (6), /* fmov, fneg, fabs */ 362 COSTS_N_INSNS (6), /* fadd, fsub */ 363 COSTS_N_INSNS (6), /* fcmp */ 364 COSTS_N_INSNS (6), /* fmov, fmovr */ 365 COSTS_N_INSNS (6), /* fmul */ 366 COSTS_N_INSNS (19), /* fdivs */ 367 COSTS_N_INSNS (33), /* fdivd */ 368 COSTS_N_INSNS (19), /* fsqrts */ 369 COSTS_N_INSNS (33), /* fsqrtd */ 370 COSTS_N_INSNS (5), /* imul */ 371 COSTS_N_INSNS (5), /* imulX */ 372 0, /* imul bit factor */ 373 COSTS_N_INSNS (26), /* idiv, average of 12 - 41 cycle range */ 374 COSTS_N_INSNS (26), /* idivX, average of 12 - 41 cycle range */ 375 COSTS_N_INSNS (1), /* movcc/movr */ 376 0, /* shift penalty */ 377 }; 378 379 static const 380 struct processor_costs niagara3_costs = { 381 COSTS_N_INSNS (3), /* int load */ 382 COSTS_N_INSNS (3), /* int signed load */ 383 COSTS_N_INSNS (3), /* int zeroed load */ 384 COSTS_N_INSNS (3), /* float load */ 385 COSTS_N_INSNS (9), /* fmov, fneg, fabs */ 386 COSTS_N_INSNS (9), /* fadd, fsub */ 387 COSTS_N_INSNS (9), /* fcmp */ 388 COSTS_N_INSNS (9), /* fmov, fmovr */ 389 COSTS_N_INSNS (9), /* fmul */ 390 COSTS_N_INSNS (23), /* fdivs */ 391 COSTS_N_INSNS (37), /* fdivd */ 392 COSTS_N_INSNS (23), /* fsqrts */ 393 COSTS_N_INSNS (37), /* fsqrtd */ 394 COSTS_N_INSNS (9), /* imul */ 395 COSTS_N_INSNS (9), /* imulX */ 396 0, /* imul bit factor */ 397 COSTS_N_INSNS (31), /* idiv, average of 17 - 45 cycle range */ 398 COSTS_N_INSNS (30), /* idivX, average of 16 - 44 cycle range */ 399 COSTS_N_INSNS (1), /* movcc/movr */ 400 0, /* shift penalty */ 401 }; 402 403 static const 404 struct processor_costs niagara4_costs = { 405 COSTS_N_INSNS (5), /* int load */ 406 COSTS_N_INSNS (5), /* int signed load */ 407 COSTS_N_INSNS (5), /* int zeroed load */ 408 COSTS_N_INSNS (5), /* float load */ 409 COSTS_N_INSNS (11), /* fmov, fneg, fabs */ 410 COSTS_N_INSNS (11), /* fadd, fsub */ 411 COSTS_N_INSNS (11), /* fcmp */ 412 COSTS_N_INSNS (11), /* fmov, fmovr */ 413 COSTS_N_INSNS (11), /* fmul */ 414 COSTS_N_INSNS (24), /* fdivs */ 415 COSTS_N_INSNS (37), /* fdivd */ 416 COSTS_N_INSNS (24), /* fsqrts */ 417 COSTS_N_INSNS (37), /* fsqrtd */ 418 COSTS_N_INSNS (12), /* imul */ 419 COSTS_N_INSNS (12), /* imulX */ 420 0, /* imul bit factor */ 421 COSTS_N_INSNS (50), /* idiv, average of 41 - 60 cycle range */ 422 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */ 423 COSTS_N_INSNS (1), /* movcc/movr */ 424 0, /* shift penalty */ 425 }; 426 427 static const 428 struct processor_costs niagara7_costs = { 429 COSTS_N_INSNS (5), /* int load */ 430 COSTS_N_INSNS (5), /* int signed load */ 431 COSTS_N_INSNS (5), /* int zeroed load */ 432 COSTS_N_INSNS (5), /* float load */ 433 COSTS_N_INSNS (11), /* fmov, fneg, fabs */ 434 COSTS_N_INSNS (11), /* fadd, fsub */ 435 COSTS_N_INSNS (11), /* fcmp */ 436 COSTS_N_INSNS (11), /* fmov, fmovr */ 437 COSTS_N_INSNS (11), /* fmul */ 438 COSTS_N_INSNS (24), /* fdivs */ 439 COSTS_N_INSNS (37), /* fdivd */ 440 COSTS_N_INSNS (24), /* fsqrts */ 441 COSTS_N_INSNS (37), /* fsqrtd */ 442 COSTS_N_INSNS (12), /* imul */ 443 COSTS_N_INSNS (12), /* imulX */ 444 0, /* imul bit factor */ 445 COSTS_N_INSNS (51), /* idiv, average of 42 - 61 cycle range */ 446 COSTS_N_INSNS (35), /* idivX, average of 26 - 44 cycle range */ 447 COSTS_N_INSNS (1), /* movcc/movr */ 448 0, /* shift penalty */ 449 }; 450 451 static const 452 struct processor_costs m8_costs = { 453 COSTS_N_INSNS (3), /* int load */ 454 COSTS_N_INSNS (3), /* int signed load */ 455 COSTS_N_INSNS (3), /* int zeroed load */ 456 COSTS_N_INSNS (3), /* float load */ 457 COSTS_N_INSNS (9), /* fmov, fneg, fabs */ 458 COSTS_N_INSNS (9), /* fadd, fsub */ 459 COSTS_N_INSNS (9), /* fcmp */ 460 COSTS_N_INSNS (9), /* fmov, fmovr */ 461 COSTS_N_INSNS (9), /* fmul */ 462 COSTS_N_INSNS (26), /* fdivs */ 463 COSTS_N_INSNS (30), /* fdivd */ 464 COSTS_N_INSNS (33), /* fsqrts */ 465 COSTS_N_INSNS (41), /* fsqrtd */ 466 COSTS_N_INSNS (12), /* imul */ 467 COSTS_N_INSNS (10), /* imulX */ 468 0, /* imul bit factor */ 469 COSTS_N_INSNS (57), /* udiv/sdiv */ 470 COSTS_N_INSNS (30), /* udivx/sdivx */ 471 COSTS_N_INSNS (1), /* movcc/movr */ 472 0, /* shift penalty */ 473 }; 474 475 static const struct processor_costs *sparc_costs = &cypress_costs; 476 477 #ifdef HAVE_AS_RELAX_OPTION 478 /* If 'as' and 'ld' are relaxing tail call insns into branch always, use 479 "or %o7,%g0,X; call Y; or X,%g0,%o7" always, so that it can be optimized. 480 With sethi/jmp, neither 'as' nor 'ld' has an easy way how to find out if 481 somebody does not branch between the sethi and jmp. */ 482 #define LEAF_SIBCALL_SLOT_RESERVED_P 1 483 #else 484 #define LEAF_SIBCALL_SLOT_RESERVED_P \ 485 ((TARGET_ARCH64 && !TARGET_CM_MEDLOW) || flag_pic) 486 #endif 487 488 /* Vector to say how input registers are mapped to output registers. 489 HARD_FRAME_POINTER_REGNUM cannot be remapped by this function to 490 eliminate it. You must use -fomit-frame-pointer to get that. */ 491 char leaf_reg_remap[] = 492 { 0, 1, 2, 3, 4, 5, 6, 7, 493 -1, -1, -1, -1, -1, -1, 14, -1, 494 -1, -1, -1, -1, -1, -1, -1, -1, 495 8, 9, 10, 11, 12, 13, -1, 15, 496 497 32, 33, 34, 35, 36, 37, 38, 39, 498 40, 41, 42, 43, 44, 45, 46, 47, 499 48, 49, 50, 51, 52, 53, 54, 55, 500 56, 57, 58, 59, 60, 61, 62, 63, 501 64, 65, 66, 67, 68, 69, 70, 71, 502 72, 73, 74, 75, 76, 77, 78, 79, 503 80, 81, 82, 83, 84, 85, 86, 87, 504 88, 89, 90, 91, 92, 93, 94, 95, 505 96, 97, 98, 99, 100, 101, 102}; 506 507 /* Vector, indexed by hard register number, which contains 1 508 for a register that is allowable in a candidate for leaf 509 function treatment. */ 510 char sparc_leaf_regs[] = 511 { 1, 1, 1, 1, 1, 1, 1, 1, 512 0, 0, 0, 0, 0, 0, 1, 0, 513 0, 0, 0, 0, 0, 0, 0, 0, 514 1, 1, 1, 1, 1, 1, 0, 1, 515 1, 1, 1, 1, 1, 1, 1, 1, 516 1, 1, 1, 1, 1, 1, 1, 1, 517 1, 1, 1, 1, 1, 1, 1, 1, 518 1, 1, 1, 1, 1, 1, 1, 1, 519 1, 1, 1, 1, 1, 1, 1, 1, 520 1, 1, 1, 1, 1, 1, 1, 1, 521 1, 1, 1, 1, 1, 1, 1, 1, 522 1, 1, 1, 1, 1, 1, 1, 1, 523 1, 1, 1, 1, 1, 1, 1}; 524 525 struct GTY(()) machine_function 526 { 527 /* Size of the frame of the function. */ 528 HOST_WIDE_INT frame_size; 529 530 /* Size of the frame of the function minus the register window save area 531 and the outgoing argument area. */ 532 HOST_WIDE_INT apparent_frame_size; 533 534 /* Register we pretend the frame pointer is allocated to. Normally, this 535 is %fp, but if we are in a leaf procedure, this is (%sp + offset). We 536 record "offset" separately as it may be too big for (reg + disp). */ 537 rtx frame_base_reg; 538 HOST_WIDE_INT frame_base_offset; 539 540 /* Number of global or FP registers to be saved (as 4-byte quantities). */ 541 int n_global_fp_regs; 542 543 /* True if the current function is leaf and uses only leaf regs, 544 so that the SPARC leaf function optimization can be applied. 545 Private version of crtl->uses_only_leaf_regs, see 546 sparc_expand_prologue for the rationale. */ 547 int leaf_function_p; 548 549 /* True if the prologue saves local or in registers. */ 550 bool save_local_in_regs_p; 551 552 /* True if the data calculated by sparc_expand_prologue are valid. */ 553 bool prologue_data_valid_p; 554 }; 555 556 #define sparc_frame_size cfun->machine->frame_size 557 #define sparc_apparent_frame_size cfun->machine->apparent_frame_size 558 #define sparc_frame_base_reg cfun->machine->frame_base_reg 559 #define sparc_frame_base_offset cfun->machine->frame_base_offset 560 #define sparc_n_global_fp_regs cfun->machine->n_global_fp_regs 561 #define sparc_leaf_function_p cfun->machine->leaf_function_p 562 #define sparc_save_local_in_regs_p cfun->machine->save_local_in_regs_p 563 #define sparc_prologue_data_valid_p cfun->machine->prologue_data_valid_p 564 565 /* 1 if the next opcode is to be specially indented. */ 566 int sparc_indent_opcode = 0; 567 568 static void sparc_option_override (void); 569 static void sparc_init_modes (void); 570 static int function_arg_slotno (const CUMULATIVE_ARGS *, machine_mode, 571 const_tree, bool, bool, int *, int *); 572 573 static int supersparc_adjust_cost (rtx_insn *, int, rtx_insn *, int); 574 static int hypersparc_adjust_cost (rtx_insn *, int, rtx_insn *, int); 575 576 static void sparc_emit_set_const32 (rtx, rtx); 577 static void sparc_emit_set_const64 (rtx, rtx); 578 static void sparc_output_addr_vec (rtx); 579 static void sparc_output_addr_diff_vec (rtx); 580 static void sparc_output_deferred_case_vectors (void); 581 static bool sparc_legitimate_address_p (machine_mode, rtx, bool); 582 static bool sparc_legitimate_constant_p (machine_mode, rtx); 583 static rtx sparc_builtin_saveregs (void); 584 static int epilogue_renumber (rtx *, int); 585 static bool sparc_assemble_integer (rtx, unsigned int, int); 586 static int set_extends (rtx_insn *); 587 static void sparc_asm_function_prologue (FILE *, HOST_WIDE_INT); 588 static void sparc_asm_function_epilogue (FILE *, HOST_WIDE_INT); 589 #ifdef TARGET_SOLARIS 590 static void sparc_solaris_elf_asm_named_section (const char *, unsigned int, 591 tree) ATTRIBUTE_UNUSED; 592 #endif 593 static int sparc_adjust_cost (rtx_insn *, int, rtx_insn *, int, unsigned int); 594 static int sparc_issue_rate (void); 595 static void sparc_sched_init (FILE *, int, int); 596 static int sparc_use_sched_lookahead (void); 597 598 static void emit_soft_tfmode_libcall (const char *, int, rtx *); 599 static void emit_soft_tfmode_binop (enum rtx_code, rtx *); 600 static void emit_soft_tfmode_unop (enum rtx_code, rtx *); 601 static void emit_soft_tfmode_cvt (enum rtx_code, rtx *); 602 static void emit_hard_tfmode_operation (enum rtx_code, rtx *); 603 604 static bool sparc_function_ok_for_sibcall (tree, tree); 605 static void sparc_init_libfuncs (void); 606 static void sparc_init_builtins (void); 607 static void sparc_fpu_init_builtins (void); 608 static void sparc_vis_init_builtins (void); 609 static tree sparc_builtin_decl (unsigned, bool); 610 static rtx sparc_expand_builtin (tree, rtx, rtx, machine_mode, int); 611 static tree sparc_fold_builtin (tree, int, tree *, bool); 612 static void sparc_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, 613 HOST_WIDE_INT, tree); 614 static bool sparc_can_output_mi_thunk (const_tree, HOST_WIDE_INT, 615 HOST_WIDE_INT, const_tree); 616 static struct machine_function * sparc_init_machine_status (void); 617 static bool sparc_cannot_force_const_mem (machine_mode, rtx); 618 static rtx sparc_tls_get_addr (void); 619 static rtx sparc_tls_got (void); 620 static int sparc_register_move_cost (machine_mode, 621 reg_class_t, reg_class_t); 622 static bool sparc_rtx_costs (rtx, machine_mode, int, int, int *, bool); 623 static rtx sparc_function_value (const_tree, const_tree, bool); 624 static rtx sparc_libcall_value (machine_mode, const_rtx); 625 static bool sparc_function_value_regno_p (const unsigned int); 626 static rtx sparc_struct_value_rtx (tree, int); 627 static machine_mode sparc_promote_function_mode (const_tree, machine_mode, 628 int *, const_tree, int); 629 static bool sparc_return_in_memory (const_tree, const_tree); 630 static bool sparc_strict_argument_naming (cumulative_args_t); 631 static void sparc_va_start (tree, rtx); 632 static tree sparc_gimplify_va_arg (tree, tree, gimple_seq *, gimple_seq *); 633 static bool sparc_vector_mode_supported_p (machine_mode); 634 static bool sparc_tls_referenced_p (rtx); 635 static rtx sparc_legitimize_tls_address (rtx); 636 static rtx sparc_legitimize_pic_address (rtx, rtx); 637 static rtx sparc_legitimize_address (rtx, rtx, machine_mode); 638 static rtx sparc_delegitimize_address (rtx); 639 static bool sparc_mode_dependent_address_p (const_rtx, addr_space_t); 640 static bool sparc_pass_by_reference (cumulative_args_t, 641 machine_mode, const_tree, bool); 642 static void sparc_function_arg_advance (cumulative_args_t, 643 machine_mode, const_tree, bool); 644 static rtx sparc_function_arg_1 (cumulative_args_t, 645 machine_mode, const_tree, bool, bool); 646 static rtx sparc_function_arg (cumulative_args_t, 647 machine_mode, const_tree, bool); 648 static rtx sparc_function_incoming_arg (cumulative_args_t, 649 machine_mode, const_tree, bool); 650 static unsigned int sparc_function_arg_boundary (machine_mode, 651 const_tree); 652 static int sparc_arg_partial_bytes (cumulative_args_t, 653 machine_mode, tree, bool); 654 static void sparc_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; 655 static void sparc_file_end (void); 656 static bool sparc_frame_pointer_required (void); 657 static bool sparc_can_eliminate (const int, const int); 658 static rtx sparc_builtin_setjmp_frame_value (void); 659 static void sparc_conditional_register_usage (void); 660 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING 661 static const char *sparc_mangle_type (const_tree); 662 #endif 663 static void sparc_trampoline_init (rtx, tree, rtx); 664 static machine_mode sparc_preferred_simd_mode (machine_mode); 665 static reg_class_t sparc_preferred_reload_class (rtx x, reg_class_t rclass); 666 static bool sparc_lra_p (void); 667 static bool sparc_print_operand_punct_valid_p (unsigned char); 668 static void sparc_print_operand (FILE *, rtx, int); 669 static void sparc_print_operand_address (FILE *, machine_mode, rtx); 670 static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t, 671 machine_mode, 672 secondary_reload_info *); 673 static machine_mode sparc_cstore_mode (enum insn_code icode); 674 static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *); 675 static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *); 676 static unsigned int sparc_min_arithmetic_precision (void); 677 678 #ifdef SUBTARGET_ATTRIBUTE_TABLE 679 /* Table of valid machine attributes. */ 680 static const struct attribute_spec sparc_attribute_table[] = 681 { 682 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, 683 do_diagnostic } */ 684 SUBTARGET_ATTRIBUTE_TABLE, 685 { NULL, 0, 0, false, false, false, NULL, false } 686 }; 687 #endif 688 689 /* Option handling. */ 690 691 /* Parsed value. */ 692 enum cmodel sparc_cmodel; 693 694 char sparc_hard_reg_printed[8]; 695 696 /* Initialize the GCC target structure. */ 697 698 /* The default is to use .half rather than .short for aligned HI objects. */ 699 #undef TARGET_ASM_ALIGNED_HI_OP 700 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 701 702 #undef TARGET_ASM_UNALIGNED_HI_OP 703 #define TARGET_ASM_UNALIGNED_HI_OP "\t.uahalf\t" 704 #undef TARGET_ASM_UNALIGNED_SI_OP 705 #define TARGET_ASM_UNALIGNED_SI_OP "\t.uaword\t" 706 #undef TARGET_ASM_UNALIGNED_DI_OP 707 #define TARGET_ASM_UNALIGNED_DI_OP "\t.uaxword\t" 708 709 /* The target hook has to handle DI-mode values. */ 710 #undef TARGET_ASM_INTEGER 711 #define TARGET_ASM_INTEGER sparc_assemble_integer 712 713 #undef TARGET_ASM_FUNCTION_PROLOGUE 714 #define TARGET_ASM_FUNCTION_PROLOGUE sparc_asm_function_prologue 715 #undef TARGET_ASM_FUNCTION_EPILOGUE 716 #define TARGET_ASM_FUNCTION_EPILOGUE sparc_asm_function_epilogue 717 718 #undef TARGET_SCHED_ADJUST_COST 719 #define TARGET_SCHED_ADJUST_COST sparc_adjust_cost 720 #undef TARGET_SCHED_ISSUE_RATE 721 #define TARGET_SCHED_ISSUE_RATE sparc_issue_rate 722 #undef TARGET_SCHED_INIT 723 #define TARGET_SCHED_INIT sparc_sched_init 724 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 725 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD sparc_use_sched_lookahead 726 727 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 728 #define TARGET_FUNCTION_OK_FOR_SIBCALL sparc_function_ok_for_sibcall 729 730 #undef TARGET_INIT_LIBFUNCS 731 #define TARGET_INIT_LIBFUNCS sparc_init_libfuncs 732 733 #undef TARGET_LEGITIMIZE_ADDRESS 734 #define TARGET_LEGITIMIZE_ADDRESS sparc_legitimize_address 735 #undef TARGET_DELEGITIMIZE_ADDRESS 736 #define TARGET_DELEGITIMIZE_ADDRESS sparc_delegitimize_address 737 #undef TARGET_MODE_DEPENDENT_ADDRESS_P 738 #define TARGET_MODE_DEPENDENT_ADDRESS_P sparc_mode_dependent_address_p 739 740 #undef TARGET_INIT_BUILTINS 741 #define TARGET_INIT_BUILTINS sparc_init_builtins 742 #undef TARGET_BUILTIN_DECL 743 #define TARGET_BUILTIN_DECL sparc_builtin_decl 744 #undef TARGET_EXPAND_BUILTIN 745 #define TARGET_EXPAND_BUILTIN sparc_expand_builtin 746 #undef TARGET_FOLD_BUILTIN 747 #define TARGET_FOLD_BUILTIN sparc_fold_builtin 748 749 #if TARGET_TLS 750 #undef TARGET_HAVE_TLS 751 #define TARGET_HAVE_TLS true 752 #endif 753 754 #undef TARGET_CANNOT_FORCE_CONST_MEM 755 #define TARGET_CANNOT_FORCE_CONST_MEM sparc_cannot_force_const_mem 756 757 #undef TARGET_ASM_OUTPUT_MI_THUNK 758 #define TARGET_ASM_OUTPUT_MI_THUNK sparc_output_mi_thunk 759 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 760 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK sparc_can_output_mi_thunk 761 762 #undef TARGET_RTX_COSTS 763 #define TARGET_RTX_COSTS sparc_rtx_costs 764 #undef TARGET_ADDRESS_COST 765 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 766 #undef TARGET_REGISTER_MOVE_COST 767 #define TARGET_REGISTER_MOVE_COST sparc_register_move_cost 768 769 #undef TARGET_PROMOTE_FUNCTION_MODE 770 #define TARGET_PROMOTE_FUNCTION_MODE sparc_promote_function_mode 771 772 #undef TARGET_FUNCTION_VALUE 773 #define TARGET_FUNCTION_VALUE sparc_function_value 774 #undef TARGET_LIBCALL_VALUE 775 #define TARGET_LIBCALL_VALUE sparc_libcall_value 776 #undef TARGET_FUNCTION_VALUE_REGNO_P 777 #define TARGET_FUNCTION_VALUE_REGNO_P sparc_function_value_regno_p 778 779 #undef TARGET_STRUCT_VALUE_RTX 780 #define TARGET_STRUCT_VALUE_RTX sparc_struct_value_rtx 781 #undef TARGET_RETURN_IN_MEMORY 782 #define TARGET_RETURN_IN_MEMORY sparc_return_in_memory 783 #undef TARGET_MUST_PASS_IN_STACK 784 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 785 #undef TARGET_PASS_BY_REFERENCE 786 #define TARGET_PASS_BY_REFERENCE sparc_pass_by_reference 787 #undef TARGET_ARG_PARTIAL_BYTES 788 #define TARGET_ARG_PARTIAL_BYTES sparc_arg_partial_bytes 789 #undef TARGET_FUNCTION_ARG_ADVANCE 790 #define TARGET_FUNCTION_ARG_ADVANCE sparc_function_arg_advance 791 #undef TARGET_FUNCTION_ARG 792 #define TARGET_FUNCTION_ARG sparc_function_arg 793 #undef TARGET_FUNCTION_INCOMING_ARG 794 #define TARGET_FUNCTION_INCOMING_ARG sparc_function_incoming_arg 795 #undef TARGET_FUNCTION_ARG_BOUNDARY 796 #define TARGET_FUNCTION_ARG_BOUNDARY sparc_function_arg_boundary 797 798 #undef TARGET_EXPAND_BUILTIN_SAVEREGS 799 #define TARGET_EXPAND_BUILTIN_SAVEREGS sparc_builtin_saveregs 800 #undef TARGET_STRICT_ARGUMENT_NAMING 801 #define TARGET_STRICT_ARGUMENT_NAMING sparc_strict_argument_naming 802 803 #undef TARGET_EXPAND_BUILTIN_VA_START 804 #define TARGET_EXPAND_BUILTIN_VA_START sparc_va_start 805 #undef TARGET_GIMPLIFY_VA_ARG_EXPR 806 #define TARGET_GIMPLIFY_VA_ARG_EXPR sparc_gimplify_va_arg 807 808 #undef TARGET_VECTOR_MODE_SUPPORTED_P 809 #define TARGET_VECTOR_MODE_SUPPORTED_P sparc_vector_mode_supported_p 810 811 #undef TARGET_VECTORIZE_PREFERRED_SIMD_MODE 812 #define TARGET_VECTORIZE_PREFERRED_SIMD_MODE sparc_preferred_simd_mode 813 814 #ifdef SUBTARGET_INSERT_ATTRIBUTES 815 #undef TARGET_INSERT_ATTRIBUTES 816 #define TARGET_INSERT_ATTRIBUTES SUBTARGET_INSERT_ATTRIBUTES 817 #endif 818 819 #ifdef SUBTARGET_ATTRIBUTE_TABLE 820 #undef TARGET_ATTRIBUTE_TABLE 821 #define TARGET_ATTRIBUTE_TABLE sparc_attribute_table 822 #endif 823 824 #undef TARGET_OPTION_OVERRIDE 825 #define TARGET_OPTION_OVERRIDE sparc_option_override 826 827 #ifdef TARGET_THREAD_SSP_OFFSET 828 #undef TARGET_STACK_PROTECT_GUARD 829 #define TARGET_STACK_PROTECT_GUARD hook_tree_void_null 830 #endif 831 832 #if TARGET_GNU_TLS && defined(HAVE_AS_SPARC_UA_PCREL) 833 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL 834 #define TARGET_ASM_OUTPUT_DWARF_DTPREL sparc_output_dwarf_dtprel 835 #endif 836 837 #undef TARGET_ASM_FILE_END 838 #define TARGET_ASM_FILE_END sparc_file_end 839 840 #undef TARGET_FRAME_POINTER_REQUIRED 841 #define TARGET_FRAME_POINTER_REQUIRED sparc_frame_pointer_required 842 843 #undef TARGET_BUILTIN_SETJMP_FRAME_VALUE 844 #define TARGET_BUILTIN_SETJMP_FRAME_VALUE sparc_builtin_setjmp_frame_value 845 846 #undef TARGET_CAN_ELIMINATE 847 #define TARGET_CAN_ELIMINATE sparc_can_eliminate 848 849 #undef TARGET_PREFERRED_RELOAD_CLASS 850 #define TARGET_PREFERRED_RELOAD_CLASS sparc_preferred_reload_class 851 852 #undef TARGET_SECONDARY_RELOAD 853 #define TARGET_SECONDARY_RELOAD sparc_secondary_reload 854 855 #undef TARGET_CONDITIONAL_REGISTER_USAGE 856 #define TARGET_CONDITIONAL_REGISTER_USAGE sparc_conditional_register_usage 857 858 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING 859 #undef TARGET_MANGLE_TYPE 860 #define TARGET_MANGLE_TYPE sparc_mangle_type 861 #endif 862 863 #undef TARGET_LRA_P 864 #define TARGET_LRA_P sparc_lra_p 865 866 #undef TARGET_LEGITIMATE_ADDRESS_P 867 #define TARGET_LEGITIMATE_ADDRESS_P sparc_legitimate_address_p 868 869 #undef TARGET_LEGITIMATE_CONSTANT_P 870 #define TARGET_LEGITIMATE_CONSTANT_P sparc_legitimate_constant_p 871 872 #undef TARGET_TRAMPOLINE_INIT 873 #define TARGET_TRAMPOLINE_INIT sparc_trampoline_init 874 875 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 876 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P sparc_print_operand_punct_valid_p 877 #undef TARGET_PRINT_OPERAND 878 #define TARGET_PRINT_OPERAND sparc_print_operand 879 #undef TARGET_PRINT_OPERAND_ADDRESS 880 #define TARGET_PRINT_OPERAND_ADDRESS sparc_print_operand_address 881 882 /* The value stored by LDSTUB. */ 883 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 884 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 0xff 885 886 #undef TARGET_CSTORE_MODE 887 #define TARGET_CSTORE_MODE sparc_cstore_mode 888 889 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV 890 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV sparc_atomic_assign_expand_fenv 891 892 #undef TARGET_FIXED_CONDITION_CODE_REGS 893 #define TARGET_FIXED_CONDITION_CODE_REGS sparc_fixed_condition_code_regs 894 895 #undef TARGET_MIN_ARITHMETIC_PRECISION 896 #define TARGET_MIN_ARITHMETIC_PRECISION sparc_min_arithmetic_precision 897 898 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS 899 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1 900 901 struct gcc_target targetm = TARGET_INITIALIZER; 902 903 /* Return the memory reference contained in X if any, zero otherwise. */ 904 905 static rtx 906 mem_ref (rtx x) 907 { 908 if (GET_CODE (x) == SIGN_EXTEND || GET_CODE (x) == ZERO_EXTEND) 909 x = XEXP (x, 0); 910 911 if (MEM_P (x)) 912 return x; 913 914 return NULL_RTX; 915 } 916 917 /* True if any of INSN's source register(s) is REG. */ 918 919 static bool 920 insn_uses_reg_p (rtx_insn *insn, unsigned int reg) 921 { 922 extract_insn (insn); 923 return ((REG_P (recog_data.operand[1]) 924 && REGNO (recog_data.operand[1]) == reg) 925 || (recog_data.n_operands == 3 926 && REG_P (recog_data.operand[2]) 927 && REGNO (recog_data.operand[2]) == reg)); 928 } 929 930 /* True if INSN is a floating-point division or square-root. */ 931 932 static bool 933 div_sqrt_insn_p (rtx_insn *insn) 934 { 935 if (GET_CODE (PATTERN (insn)) != SET) 936 return false; 937 938 switch (get_attr_type (insn)) 939 { 940 case TYPE_FPDIVS: 941 case TYPE_FPSQRTS: 942 case TYPE_FPDIVD: 943 case TYPE_FPSQRTD: 944 return true; 945 default: 946 return false; 947 } 948 } 949 950 /* True if INSN is a floating-point instruction. */ 951 952 static bool 953 fpop_insn_p (rtx_insn *insn) 954 { 955 if (GET_CODE (PATTERN (insn)) != SET) 956 return false; 957 958 switch (get_attr_type (insn)) 959 { 960 case TYPE_FPMOVE: 961 case TYPE_FPCMOVE: 962 case TYPE_FP: 963 case TYPE_FPCMP: 964 case TYPE_FPMUL: 965 case TYPE_FPDIVS: 966 case TYPE_FPSQRTS: 967 case TYPE_FPDIVD: 968 case TYPE_FPSQRTD: 969 return true; 970 default: 971 return false; 972 } 973 } 974 975 /* True if INSN is an atomic instruction. */ 976 977 static bool 978 atomic_insn_for_leon3_p (rtx_insn *insn) 979 { 980 switch (INSN_CODE (insn)) 981 { 982 case CODE_FOR_swapsi: 983 case CODE_FOR_ldstub: 984 case CODE_FOR_atomic_compare_and_swap_leon3_1: 985 return true; 986 default: 987 return false; 988 } 989 } 990 991 /* We use a machine specific pass to enable workarounds for errata. 992 993 We need to have the (essentially) final form of the insn stream in order 994 to properly detect the various hazards. Therefore, this machine specific 995 pass runs as late as possible. */ 996 997 /* True if INSN is a md pattern or asm statement. */ 998 #define USEFUL_INSN_P(INSN) \ 999 (NONDEBUG_INSN_P (INSN) \ 1000 && GET_CODE (PATTERN (INSN)) != USE \ 1001 && GET_CODE (PATTERN (INSN)) != CLOBBER) 1002 1003 static unsigned int 1004 sparc_do_work_around_errata (void) 1005 { 1006 rtx_insn *insn, *next; 1007 1008 /* Force all instructions to be split into their final form. */ 1009 split_all_insns_noflow (); 1010 1011 /* Now look for specific patterns in the insn stream. */ 1012 for (insn = get_insns (); insn; insn = next) 1013 { 1014 bool insert_nop = false; 1015 rtx set; 1016 rtx_insn *jump; 1017 rtx_sequence *seq; 1018 1019 /* Look into the instruction in a delay slot. */ 1020 if (NONJUMP_INSN_P (insn) 1021 && (seq = dyn_cast <rtx_sequence *> (PATTERN (insn)))) 1022 { 1023 jump = seq->insn (0); 1024 insn = seq->insn (1); 1025 } 1026 else if (JUMP_P (insn)) 1027 jump = insn; 1028 else 1029 jump = NULL; 1030 1031 /* Place a NOP at the branch target of an integer branch if it is a 1032 floating-point operation or a floating-point branch. */ 1033 if (sparc_fix_gr712rc 1034 && jump 1035 && jump_to_label_p (jump) 1036 && get_attr_branch_type (jump) == BRANCH_TYPE_ICC) 1037 { 1038 rtx_insn *target = next_active_insn (JUMP_LABEL_AS_INSN (jump)); 1039 if (target 1040 && (fpop_insn_p (target) 1041 || (JUMP_P (target) 1042 && get_attr_branch_type (target) == BRANCH_TYPE_FCC))) 1043 emit_insn_before (gen_nop (), target); 1044 } 1045 1046 /* Insert a NOP between load instruction and atomic instruction. Insert 1047 a NOP at branch target if there is a load in delay slot and an atomic 1048 instruction at branch target. */ 1049 if (sparc_fix_ut700 1050 && NONJUMP_INSN_P (insn) 1051 && (set = single_set (insn)) != NULL_RTX 1052 && mem_ref (SET_SRC (set)) 1053 && REG_P (SET_DEST (set))) 1054 { 1055 if (jump && jump_to_label_p (jump)) 1056 { 1057 rtx_insn *target = next_active_insn (JUMP_LABEL_AS_INSN (jump)); 1058 if (target && atomic_insn_for_leon3_p (target)) 1059 emit_insn_before (gen_nop (), target); 1060 } 1061 1062 next = next_active_insn (insn); 1063 if (!next) 1064 break; 1065 1066 if (atomic_insn_for_leon3_p (next)) 1067 insert_nop = true; 1068 } 1069 1070 /* Look for a sequence that starts with a fdiv or fsqrt instruction and 1071 ends with another fdiv or fsqrt instruction with no dependencies on 1072 the former, along with an appropriate pattern in between. */ 1073 if (sparc_fix_lost_divsqrt 1074 && NONJUMP_INSN_P (insn) 1075 && div_sqrt_insn_p (insn)) 1076 { 1077 int i; 1078 int fp_found = 0; 1079 rtx_insn *after; 1080 1081 const unsigned int dest_reg = REGNO (SET_DEST (single_set (insn))); 1082 1083 next = next_active_insn (insn); 1084 if (!next) 1085 break; 1086 1087 for (after = next, i = 0; i < 4; i++) 1088 { 1089 /* Count floating-point operations. */ 1090 if (i != 3 && fpop_insn_p (after)) 1091 { 1092 /* If the insn uses the destination register of 1093 the div/sqrt, then it cannot be problematic. */ 1094 if (insn_uses_reg_p (after, dest_reg)) 1095 break; 1096 fp_found++; 1097 } 1098 1099 /* Count floating-point loads. */ 1100 if (i != 3 1101 && (set = single_set (after)) != NULL_RTX 1102 && REG_P (SET_DEST (set)) 1103 && REGNO (SET_DEST (set)) > 31) 1104 { 1105 /* If the insn uses the destination register of 1106 the div/sqrt, then it cannot be problematic. */ 1107 if (REGNO (SET_DEST (set)) == dest_reg) 1108 break; 1109 fp_found++; 1110 } 1111 1112 /* Check if this is a problematic sequence. */ 1113 if (i > 1 1114 && fp_found >= 2 1115 && div_sqrt_insn_p (after)) 1116 { 1117 /* If this is the short version of the problematic 1118 sequence we add two NOPs in a row to also prevent 1119 the long version. */ 1120 if (i == 2) 1121 emit_insn_before (gen_nop (), next); 1122 insert_nop = true; 1123 break; 1124 } 1125 1126 /* No need to scan past a second div/sqrt. */ 1127 if (div_sqrt_insn_p (after)) 1128 break; 1129 1130 /* Insert NOP before branch. */ 1131 if (i < 3 1132 && (!NONJUMP_INSN_P (after) 1133 || GET_CODE (PATTERN (after)) == SEQUENCE)) 1134 { 1135 insert_nop = true; 1136 break; 1137 } 1138 1139 after = next_active_insn (after); 1140 if (!after) 1141 break; 1142 } 1143 } 1144 1145 /* Look for either of these two sequences: 1146 1147 Sequence A: 1148 1. store of word size or less (e.g. st / stb / sth / stf) 1149 2. any single instruction that is not a load or store 1150 3. any store instruction (e.g. st / stb / sth / stf / std / stdf) 1151 1152 Sequence B: 1153 1. store of double word size (e.g. std / stdf) 1154 2. any store instruction (e.g. st / stb / sth / stf / std / stdf) */ 1155 if (sparc_fix_b2bst 1156 && NONJUMP_INSN_P (insn) 1157 && (set = single_set (insn)) != NULL_RTX 1158 && MEM_P (SET_DEST (set))) 1159 { 1160 /* Sequence B begins with a double-word store. */ 1161 bool seq_b = GET_MODE_SIZE (GET_MODE (SET_DEST (set))) == 8; 1162 rtx_insn *after; 1163 int i; 1164 1165 next = next_active_insn (insn); 1166 if (!next) 1167 break; 1168 1169 for (after = next, i = 0; i < 2; i++) 1170 { 1171 /* Skip empty assembly statements. */ 1172 if ((GET_CODE (PATTERN (after)) == UNSPEC_VOLATILE) 1173 || (USEFUL_INSN_P (after) 1174 && (asm_noperands (PATTERN (after))>=0) 1175 && !strcmp (decode_asm_operands (PATTERN (after), 1176 NULL, NULL, NULL, 1177 NULL, NULL), ""))) 1178 after = next_active_insn (after); 1179 if (!after) 1180 break; 1181 1182 /* If the insn is a branch, then it cannot be problematic. */ 1183 if (!NONJUMP_INSN_P (after) 1184 || GET_CODE (PATTERN (after)) == SEQUENCE) 1185 break; 1186 1187 /* Sequence B is only two instructions long. */ 1188 if (seq_b) 1189 { 1190 /* Add NOP if followed by a store. */ 1191 if ((set = single_set (after)) != NULL_RTX 1192 && MEM_P (SET_DEST (set))) 1193 insert_nop = true; 1194 1195 /* Otherwise it is ok. */ 1196 break; 1197 } 1198 1199 /* If the second instruction is a load or a store, 1200 then the sequence cannot be problematic. */ 1201 if (i == 0) 1202 { 1203 if ((set = single_set (after)) != NULL_RTX 1204 && (MEM_P (SET_DEST (set)) || mem_ref (SET_SRC (set)))) 1205 break; 1206 1207 after = next_active_insn (after); 1208 if (!after) 1209 break; 1210 } 1211 1212 /* Add NOP if third instruction is a store. */ 1213 if (i == 1 1214 && (set = single_set (after)) != NULL_RTX 1215 && MEM_P (SET_DEST (set))) 1216 insert_nop = true; 1217 } 1218 } 1219 1220 /* Look for a single-word load into an odd-numbered FP register. */ 1221 else if (sparc_fix_at697f 1222 && NONJUMP_INSN_P (insn) 1223 && (set = single_set (insn)) != NULL_RTX 1224 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 1225 && mem_ref (SET_SRC (set)) 1226 && REG_P (SET_DEST (set)) 1227 && REGNO (SET_DEST (set)) > 31 1228 && REGNO (SET_DEST (set)) % 2 != 0) 1229 { 1230 /* The wrong dependency is on the enclosing double register. */ 1231 const unsigned int x = REGNO (SET_DEST (set)) - 1; 1232 unsigned int src1, src2, dest; 1233 int code; 1234 1235 next = next_active_insn (insn); 1236 if (!next) 1237 break; 1238 /* If the insn is a branch, then it cannot be problematic. */ 1239 if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE) 1240 continue; 1241 1242 extract_insn (next); 1243 code = INSN_CODE (next); 1244 1245 switch (code) 1246 { 1247 case CODE_FOR_adddf3: 1248 case CODE_FOR_subdf3: 1249 case CODE_FOR_muldf3: 1250 case CODE_FOR_divdf3: 1251 dest = REGNO (recog_data.operand[0]); 1252 src1 = REGNO (recog_data.operand[1]); 1253 src2 = REGNO (recog_data.operand[2]); 1254 if (src1 != src2) 1255 { 1256 /* Case [1-4]: 1257 ld [address], %fx+1 1258 FPOPd %f{x,y}, %f{y,x}, %f{x,y} */ 1259 if ((src1 == x || src2 == x) 1260 && (dest == src1 || dest == src2)) 1261 insert_nop = true; 1262 } 1263 else 1264 { 1265 /* Case 5: 1266 ld [address], %fx+1 1267 FPOPd %fx, %fx, %fx */ 1268 if (src1 == x 1269 && dest == src1 1270 && (code == CODE_FOR_adddf3 || code == CODE_FOR_muldf3)) 1271 insert_nop = true; 1272 } 1273 break; 1274 1275 case CODE_FOR_sqrtdf2: 1276 dest = REGNO (recog_data.operand[0]); 1277 src1 = REGNO (recog_data.operand[1]); 1278 /* Case 6: 1279 ld [address], %fx+1 1280 fsqrtd %fx, %fx */ 1281 if (src1 == x && dest == src1) 1282 insert_nop = true; 1283 break; 1284 1285 default: 1286 break; 1287 } 1288 } 1289 1290 /* Look for a single-word load into an integer register. */ 1291 else if (sparc_fix_ut699 1292 && NONJUMP_INSN_P (insn) 1293 && (set = single_set (insn)) != NULL_RTX 1294 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) <= 4 1295 && (mem_ref (SET_SRC (set)) != NULL_RTX 1296 || INSN_CODE (insn) == CODE_FOR_movsi_pic_gotdata_op) 1297 && REG_P (SET_DEST (set)) 1298 && REGNO (SET_DEST (set)) < 32) 1299 { 1300 /* There is no problem if the second memory access has a data 1301 dependency on the first single-cycle load. */ 1302 rtx x = SET_DEST (set); 1303 1304 next = next_active_insn (insn); 1305 if (!next) 1306 break; 1307 /* If the insn is a branch, then it cannot be problematic. */ 1308 if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE) 1309 continue; 1310 1311 /* Look for a second memory access to/from an integer register. */ 1312 if ((set = single_set (next)) != NULL_RTX) 1313 { 1314 rtx src = SET_SRC (set); 1315 rtx dest = SET_DEST (set); 1316 rtx mem; 1317 1318 /* LDD is affected. */ 1319 if ((mem = mem_ref (src)) != NULL_RTX 1320 && REG_P (dest) 1321 && REGNO (dest) < 32 1322 && !reg_mentioned_p (x, XEXP (mem, 0))) 1323 insert_nop = true; 1324 1325 /* STD is *not* affected. */ 1326 else if (MEM_P (dest) 1327 && GET_MODE_SIZE (GET_MODE (dest)) <= 4 1328 && (src == CONST0_RTX (GET_MODE (dest)) 1329 || (REG_P (src) 1330 && REGNO (src) < 32 1331 && REGNO (src) != REGNO (x))) 1332 && !reg_mentioned_p (x, XEXP (dest, 0))) 1333 insert_nop = true; 1334 1335 /* GOT accesses uses LD. */ 1336 else if (INSN_CODE (next) == CODE_FOR_movsi_pic_gotdata_op 1337 && !reg_mentioned_p (x, XEXP (XEXP (src, 0), 1))) 1338 insert_nop = true; 1339 } 1340 } 1341 1342 /* Look for a single-word load/operation into an FP register. */ 1343 else if (sparc_fix_ut699 1344 && NONJUMP_INSN_P (insn) 1345 && (set = single_set (insn)) != NULL_RTX 1346 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 1347 && REG_P (SET_DEST (set)) 1348 && REGNO (SET_DEST (set)) > 31) 1349 { 1350 /* Number of instructions in the problematic window. */ 1351 const int n_insns = 4; 1352 /* The problematic combination is with the sibling FP register. */ 1353 const unsigned int x = REGNO (SET_DEST (set)); 1354 const unsigned int y = x ^ 1; 1355 rtx_insn *after; 1356 int i; 1357 1358 next = next_active_insn (insn); 1359 if (!next) 1360 break; 1361 /* If the insn is a branch, then it cannot be problematic. */ 1362 if (!NONJUMP_INSN_P (next) || GET_CODE (PATTERN (next)) == SEQUENCE) 1363 continue; 1364 1365 /* Look for a second load/operation into the sibling FP register. */ 1366 if (!((set = single_set (next)) != NULL_RTX 1367 && GET_MODE_SIZE (GET_MODE (SET_SRC (set))) == 4 1368 && REG_P (SET_DEST (set)) 1369 && REGNO (SET_DEST (set)) == y)) 1370 continue; 1371 1372 /* Look for a (possible) store from the FP register in the next N 1373 instructions, but bail out if it is again modified or if there 1374 is a store from the sibling FP register before this store. */ 1375 for (after = next, i = 0; i < n_insns; i++) 1376 { 1377 bool branch_p; 1378 1379 after = next_active_insn (after); 1380 if (!after) 1381 break; 1382 1383 /* This is a branch with an empty delay slot. */ 1384 if (!NONJUMP_INSN_P (after)) 1385 { 1386 if (++i == n_insns) 1387 break; 1388 branch_p = true; 1389 after = NULL; 1390 } 1391 /* This is a branch with a filled delay slot. */ 1392 else if (rtx_sequence *seq = 1393 dyn_cast <rtx_sequence *> (PATTERN (after))) 1394 { 1395 if (++i == n_insns) 1396 break; 1397 branch_p = true; 1398 after = seq->insn (1); 1399 } 1400 /* This is a regular instruction. */ 1401 else 1402 branch_p = false; 1403 1404 if (after && (set = single_set (after)) != NULL_RTX) 1405 { 1406 const rtx src = SET_SRC (set); 1407 const rtx dest = SET_DEST (set); 1408 const unsigned int size = GET_MODE_SIZE (GET_MODE (dest)); 1409 1410 /* If the FP register is again modified before the store, 1411 then the store isn't affected. */ 1412 if (REG_P (dest) 1413 && (REGNO (dest) == x 1414 || (REGNO (dest) == y && size == 8))) 1415 break; 1416 1417 if (MEM_P (dest) && REG_P (src)) 1418 { 1419 /* If there is a store from the sibling FP register 1420 before the store, then the store is not affected. */ 1421 if (REGNO (src) == y || (REGNO (src) == x && size == 8)) 1422 break; 1423 1424 /* Otherwise, the store is affected. */ 1425 if (REGNO (src) == x && size == 4) 1426 { 1427 insert_nop = true; 1428 break; 1429 } 1430 } 1431 } 1432 1433 /* If we have a branch in the first M instructions, then we 1434 cannot see the (M+2)th instruction so we play safe. */ 1435 if (branch_p && i <= (n_insns - 2)) 1436 { 1437 insert_nop = true; 1438 break; 1439 } 1440 } 1441 } 1442 1443 else 1444 next = NEXT_INSN (insn); 1445 1446 if (insert_nop) 1447 emit_insn_before (gen_nop (), next); 1448 } 1449 1450 return 0; 1451 } 1452 1453 namespace { 1454 1455 const pass_data pass_data_work_around_errata = 1456 { 1457 RTL_PASS, /* type */ 1458 "errata", /* name */ 1459 OPTGROUP_NONE, /* optinfo_flags */ 1460 TV_MACH_DEP, /* tv_id */ 1461 0, /* properties_required */ 1462 0, /* properties_provided */ 1463 0, /* properties_destroyed */ 1464 0, /* todo_flags_start */ 1465 0, /* todo_flags_finish */ 1466 }; 1467 1468 class pass_work_around_errata : public rtl_opt_pass 1469 { 1470 public: 1471 pass_work_around_errata(gcc::context *ctxt) 1472 : rtl_opt_pass(pass_data_work_around_errata, ctxt) 1473 {} 1474 1475 /* opt_pass methods: */ 1476 virtual bool gate (function *) 1477 { 1478 return sparc_fix_at697f || sparc_fix_ut699 || sparc_fix_b2bst 1479 || sparc_fix_gr712rc || sparc_fix_ut700 || sparc_fix_lost_divsqrt; 1480 } 1481 1482 virtual unsigned int execute (function *) 1483 { 1484 return sparc_do_work_around_errata (); 1485 } 1486 1487 }; // class pass_work_around_errata 1488 1489 } // anon namespace 1490 1491 rtl_opt_pass * 1492 make_pass_work_around_errata (gcc::context *ctxt) 1493 { 1494 return new pass_work_around_errata (ctxt); 1495 } 1496 1497 /* Helpers for TARGET_DEBUG_OPTIONS. */ 1498 static void 1499 dump_target_flag_bits (const int flags) 1500 { 1501 if (flags & MASK_64BIT) 1502 fprintf (stderr, "64BIT "); 1503 if (flags & MASK_APP_REGS) 1504 fprintf (stderr, "APP_REGS "); 1505 if (flags & MASK_FASTER_STRUCTS) 1506 fprintf (stderr, "FASTER_STRUCTS "); 1507 if (flags & MASK_FLAT) 1508 fprintf (stderr, "FLAT "); 1509 if (flags & MASK_FMAF) 1510 fprintf (stderr, "FMAF "); 1511 if (flags & MASK_FSMULD) 1512 fprintf (stderr, "FSMULD "); 1513 if (flags & MASK_FPU) 1514 fprintf (stderr, "FPU "); 1515 if (flags & MASK_HARD_QUAD) 1516 fprintf (stderr, "HARD_QUAD "); 1517 if (flags & MASK_POPC) 1518 fprintf (stderr, "POPC "); 1519 if (flags & MASK_PTR64) 1520 fprintf (stderr, "PTR64 "); 1521 if (flags & MASK_STACK_BIAS) 1522 fprintf (stderr, "STACK_BIAS "); 1523 if (flags & MASK_UNALIGNED_DOUBLES) 1524 fprintf (stderr, "UNALIGNED_DOUBLES "); 1525 if (flags & MASK_V8PLUS) 1526 fprintf (stderr, "V8PLUS "); 1527 if (flags & MASK_VIS) 1528 fprintf (stderr, "VIS "); 1529 if (flags & MASK_VIS2) 1530 fprintf (stderr, "VIS2 "); 1531 if (flags & MASK_VIS3) 1532 fprintf (stderr, "VIS3 "); 1533 if (flags & MASK_VIS4) 1534 fprintf (stderr, "VIS4 "); 1535 if (flags & MASK_VIS4B) 1536 fprintf (stderr, "VIS4B "); 1537 if (flags & MASK_CBCOND) 1538 fprintf (stderr, "CBCOND "); 1539 if (flags & MASK_DEPRECATED_V8_INSNS) 1540 fprintf (stderr, "DEPRECATED_V8_INSNS "); 1541 if (flags & MASK_SPARCLET) 1542 fprintf (stderr, "SPARCLET "); 1543 if (flags & MASK_SPARCLITE) 1544 fprintf (stderr, "SPARCLITE "); 1545 if (flags & MASK_V8) 1546 fprintf (stderr, "V8 "); 1547 if (flags & MASK_V9) 1548 fprintf (stderr, "V9 "); 1549 } 1550 1551 static void 1552 dump_target_flags (const char *prefix, const int flags) 1553 { 1554 fprintf (stderr, "%s: (%08x) [ ", prefix, flags); 1555 dump_target_flag_bits (flags); 1556 fprintf(stderr, "]\n"); 1557 } 1558 1559 /* Validate and override various options, and do some machine dependent 1560 initialization. */ 1561 1562 static void 1563 sparc_option_override (void) 1564 { 1565 static struct code_model { 1566 const char *const name; 1567 const enum cmodel value; 1568 } const cmodels[] = { 1569 { "32", CM_32 }, 1570 { "medlow", CM_MEDLOW }, 1571 { "medmid", CM_MEDMID }, 1572 { "medany", CM_MEDANY }, 1573 { "embmedany", CM_EMBMEDANY }, 1574 { NULL, (enum cmodel) 0 } 1575 }; 1576 const struct code_model *cmodel; 1577 /* Map TARGET_CPU_DEFAULT to value for -m{cpu,tune}=. */ 1578 static struct cpu_default { 1579 const int cpu; 1580 const enum processor_type processor; 1581 } const cpu_default[] = { 1582 /* There must be one entry here for each TARGET_CPU value. */ 1583 { TARGET_CPU_sparc, PROCESSOR_CYPRESS }, 1584 { TARGET_CPU_v8, PROCESSOR_V8 }, 1585 { TARGET_CPU_supersparc, PROCESSOR_SUPERSPARC }, 1586 { TARGET_CPU_hypersparc, PROCESSOR_HYPERSPARC }, 1587 { TARGET_CPU_leon, PROCESSOR_LEON }, 1588 { TARGET_CPU_leon3, PROCESSOR_LEON3 }, 1589 { TARGET_CPU_leon3v7, PROCESSOR_LEON3V7 }, 1590 { TARGET_CPU_sparclite, PROCESSOR_F930 }, 1591 { TARGET_CPU_sparclite86x, PROCESSOR_SPARCLITE86X }, 1592 { TARGET_CPU_sparclet, PROCESSOR_TSC701 }, 1593 { TARGET_CPU_v9, PROCESSOR_V9 }, 1594 { TARGET_CPU_ultrasparc, PROCESSOR_ULTRASPARC }, 1595 { TARGET_CPU_ultrasparc3, PROCESSOR_ULTRASPARC3 }, 1596 { TARGET_CPU_niagara, PROCESSOR_NIAGARA }, 1597 { TARGET_CPU_niagara2, PROCESSOR_NIAGARA2 }, 1598 { TARGET_CPU_niagara3, PROCESSOR_NIAGARA3 }, 1599 { TARGET_CPU_niagara4, PROCESSOR_NIAGARA4 }, 1600 { TARGET_CPU_niagara7, PROCESSOR_NIAGARA7 }, 1601 { TARGET_CPU_m8, PROCESSOR_M8 }, 1602 { -1, PROCESSOR_V7 } 1603 }; 1604 const struct cpu_default *def; 1605 /* Table of values for -m{cpu,tune}=. This must match the order of 1606 the enum processor_type in sparc-opts.h. */ 1607 static struct cpu_table { 1608 const char *const name; 1609 const int disable; 1610 const int enable; 1611 } const cpu_table[] = { 1612 { "v7", MASK_ISA|MASK_FSMULD, 0 }, 1613 { "cypress", MASK_ISA|MASK_FSMULD, 0 }, 1614 { "v8", MASK_ISA, MASK_V8 }, 1615 /* TI TMS390Z55 supersparc */ 1616 { "supersparc", MASK_ISA, MASK_V8 }, 1617 { "hypersparc", MASK_ISA, MASK_V8 }, 1618 { "leon", MASK_ISA|MASK_FSMULD, MASK_V8|MASK_LEON }, 1619 { "leon3", MASK_ISA, MASK_V8|MASK_LEON3 }, 1620 { "leon3v7", MASK_ISA|MASK_FSMULD, MASK_LEON3 }, 1621 { "sparclite", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE }, 1622 /* The Fujitsu MB86930 is the original sparclite chip, with no FPU. */ 1623 { "f930", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, 1624 /* The Fujitsu MB86934 is the recent sparclite chip, with an FPU. */ 1625 { "f934", MASK_ISA|MASK_FSMULD, MASK_SPARCLITE }, 1626 { "sparclite86x", MASK_ISA|MASK_FPU, MASK_SPARCLITE }, 1627 { "sparclet", MASK_ISA|MASK_FSMULD, MASK_SPARCLET }, 1628 /* TEMIC sparclet */ 1629 { "tsc701", MASK_ISA|MASK_FSMULD, MASK_SPARCLET }, 1630 { "v9", MASK_ISA, MASK_V9 }, 1631 /* UltraSPARC I, II, IIi */ 1632 { "ultrasparc", MASK_ISA, 1633 /* Although insns using %y are deprecated, it is a clear win. */ 1634 MASK_V9|MASK_DEPRECATED_V8_INSNS }, 1635 /* UltraSPARC III */ 1636 /* ??? Check if %y issue still holds true. */ 1637 { "ultrasparc3", MASK_ISA, 1638 MASK_V9|MASK_DEPRECATED_V8_INSNS|MASK_VIS2 }, 1639 /* UltraSPARC T1 */ 1640 { "niagara", MASK_ISA, 1641 MASK_V9|MASK_DEPRECATED_V8_INSNS }, 1642 /* UltraSPARC T2 */ 1643 { "niagara2", MASK_ISA, 1644 MASK_V9|MASK_POPC|MASK_VIS2 }, 1645 /* UltraSPARC T3 */ 1646 { "niagara3", MASK_ISA, 1647 MASK_V9|MASK_POPC|MASK_VIS3|MASK_FMAF }, 1648 /* UltraSPARC T4 */ 1649 { "niagara4", MASK_ISA, 1650 MASK_V9|MASK_POPC|MASK_VIS3|MASK_FMAF|MASK_CBCOND }, 1651 /* UltraSPARC M7 */ 1652 { "niagara7", MASK_ISA, 1653 MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC }, 1654 /* UltraSPARC M8 */ 1655 { "m8", MASK_ISA, 1656 MASK_V9|MASK_POPC|MASK_VIS4|MASK_FMAF|MASK_CBCOND|MASK_SUBXC|MASK_VIS4B } 1657 }; 1658 const struct cpu_table *cpu; 1659 unsigned int i; 1660 1661 if (sparc_debug_string != NULL) 1662 { 1663 const char *q; 1664 char *p; 1665 1666 p = ASTRDUP (sparc_debug_string); 1667 while ((q = strtok (p, ",")) != NULL) 1668 { 1669 bool invert; 1670 int mask; 1671 1672 p = NULL; 1673 if (*q == '!') 1674 { 1675 invert = true; 1676 q++; 1677 } 1678 else 1679 invert = false; 1680 1681 if (! strcmp (q, "all")) 1682 mask = MASK_DEBUG_ALL; 1683 else if (! strcmp (q, "options")) 1684 mask = MASK_DEBUG_OPTIONS; 1685 else 1686 error ("unknown -mdebug-%s switch", q); 1687 1688 if (invert) 1689 sparc_debug &= ~mask; 1690 else 1691 sparc_debug |= mask; 1692 } 1693 } 1694 1695 /* Enable the FsMULd instruction by default if not explicitly specified by 1696 the user. It may be later disabled by the CPU (explicitly or not). */ 1697 if (TARGET_FPU && !(target_flags_explicit & MASK_FSMULD)) 1698 target_flags |= MASK_FSMULD; 1699 1700 if (TARGET_DEBUG_OPTIONS) 1701 { 1702 dump_target_flags("Initial target_flags", target_flags); 1703 dump_target_flags("target_flags_explicit", target_flags_explicit); 1704 } 1705 1706 #ifdef SUBTARGET_OVERRIDE_OPTIONS 1707 SUBTARGET_OVERRIDE_OPTIONS; 1708 #endif 1709 1710 #ifndef SPARC_BI_ARCH 1711 /* Check for unsupported architecture size. */ 1712 if (!TARGET_64BIT != DEFAULT_ARCH32_P) 1713 error ("%s is not supported by this configuration", 1714 DEFAULT_ARCH32_P ? "-m64" : "-m32"); 1715 #endif 1716 1717 /* We force all 64bit archs to use 128 bit long double */ 1718 if (TARGET_ARCH64 && !TARGET_LONG_DOUBLE_128) 1719 { 1720 error ("-mlong-double-64 not allowed with -m64"); 1721 target_flags |= MASK_LONG_DOUBLE_128; 1722 } 1723 1724 /* Code model selection. */ 1725 sparc_cmodel = SPARC_DEFAULT_CMODEL; 1726 1727 #ifdef SPARC_BI_ARCH 1728 if (TARGET_ARCH32) 1729 sparc_cmodel = CM_32; 1730 #endif 1731 1732 if (sparc_cmodel_string != NULL) 1733 { 1734 if (TARGET_ARCH64) 1735 { 1736 for (cmodel = &cmodels[0]; cmodel->name; cmodel++) 1737 if (strcmp (sparc_cmodel_string, cmodel->name) == 0) 1738 break; 1739 if (cmodel->name == NULL) 1740 error ("bad value (%s) for -mcmodel= switch", sparc_cmodel_string); 1741 else 1742 sparc_cmodel = cmodel->value; 1743 } 1744 else 1745 error ("-mcmodel= is not supported on 32-bit systems"); 1746 } 1747 1748 /* Check that -fcall-saved-REG wasn't specified for out registers. */ 1749 for (i = 8; i < 16; i++) 1750 if (!call_used_regs [i]) 1751 { 1752 error ("-fcall-saved-REG is not supported for out registers"); 1753 call_used_regs [i] = 1; 1754 } 1755 1756 /* Set the default CPU if no -mcpu option was specified. */ 1757 if (!global_options_set.x_sparc_cpu_and_features) 1758 { 1759 for (def = &cpu_default[0]; def->cpu != -1; ++def) 1760 if (def->cpu == TARGET_CPU_DEFAULT) 1761 break; 1762 gcc_assert (def->cpu != -1); 1763 sparc_cpu_and_features = def->processor; 1764 } 1765 1766 /* Set the default CPU if no -mtune option was specified. */ 1767 if (!global_options_set.x_sparc_cpu) 1768 sparc_cpu = sparc_cpu_and_features; 1769 1770 cpu = &cpu_table[(int) sparc_cpu_and_features]; 1771 1772 if (TARGET_DEBUG_OPTIONS) 1773 { 1774 fprintf (stderr, "sparc_cpu_and_features: %s\n", cpu->name); 1775 dump_target_flags ("cpu->disable", cpu->disable); 1776 dump_target_flags ("cpu->enable", cpu->enable); 1777 } 1778 1779 target_flags &= ~cpu->disable; 1780 target_flags |= (cpu->enable 1781 #ifndef HAVE_AS_FMAF_HPC_VIS3 1782 & ~(MASK_FMAF | MASK_VIS3) 1783 #endif 1784 #ifndef HAVE_AS_SPARC4 1785 & ~MASK_CBCOND 1786 #endif 1787 #ifndef HAVE_AS_SPARC5_VIS4 1788 & ~(MASK_VIS4 | MASK_SUBXC) 1789 #endif 1790 #ifndef HAVE_AS_SPARC6 1791 & ~(MASK_VIS4B) 1792 #endif 1793 #ifndef HAVE_AS_LEON 1794 & ~(MASK_LEON | MASK_LEON3) 1795 #endif 1796 & ~(target_flags_explicit & MASK_FEATURES) 1797 ); 1798 1799 /* -mvis2 implies -mvis. */ 1800 if (TARGET_VIS2) 1801 target_flags |= MASK_VIS; 1802 1803 /* -mvis3 implies -mvis2 and -mvis. */ 1804 if (TARGET_VIS3) 1805 target_flags |= MASK_VIS2 | MASK_VIS; 1806 1807 /* -mvis4 implies -mvis3, -mvis2 and -mvis. */ 1808 if (TARGET_VIS4) 1809 target_flags |= MASK_VIS3 | MASK_VIS2 | MASK_VIS; 1810 1811 /* -mvis4b implies -mvis4, -mvis3, -mvis2 and -mvis */ 1812 if (TARGET_VIS4B) 1813 target_flags |= MASK_VIS4 | MASK_VIS3 | MASK_VIS2 | MASK_VIS; 1814 1815 /* Don't allow -mvis, -mvis2, -mvis3, -mvis4, -mvis4b, -mfmaf and -mfsmuld if 1816 FPU is disabled. */ 1817 if (!TARGET_FPU) 1818 target_flags &= ~(MASK_VIS | MASK_VIS2 | MASK_VIS3 | MASK_VIS4 1819 | MASK_VIS4B | MASK_FMAF | MASK_FSMULD); 1820 1821 /* -mvis assumes UltraSPARC+, so we are sure v9 instructions 1822 are available; -m64 also implies v9. */ 1823 if (TARGET_VIS || TARGET_ARCH64) 1824 { 1825 target_flags |= MASK_V9; 1826 target_flags &= ~(MASK_V8 | MASK_SPARCLET | MASK_SPARCLITE); 1827 } 1828 1829 /* -mvis also implies -mv8plus on 32-bit. */ 1830 if (TARGET_VIS && !TARGET_ARCH64) 1831 target_flags |= MASK_V8PLUS; 1832 1833 /* Use the deprecated v8 insns for sparc64 in 32-bit mode. */ 1834 if (TARGET_V9 && TARGET_ARCH32) 1835 target_flags |= MASK_DEPRECATED_V8_INSNS; 1836 1837 /* V8PLUS requires V9 and makes no sense in 64-bit mode. */ 1838 if (!TARGET_V9 || TARGET_ARCH64) 1839 target_flags &= ~MASK_V8PLUS; 1840 1841 /* Don't use stack biasing in 32-bit mode. */ 1842 if (TARGET_ARCH32) 1843 target_flags &= ~MASK_STACK_BIAS; 1844 1845 /* Use LRA instead of reload, unless otherwise instructed. */ 1846 if (!(target_flags_explicit & MASK_LRA)) 1847 target_flags |= MASK_LRA; 1848 1849 /* Enable applicable errata workarounds for LEON3FT. */ 1850 if (sparc_fix_ut699 || sparc_fix_ut700 || sparc_fix_gr712rc) 1851 { 1852 sparc_fix_b2bst = 1; 1853 sparc_fix_lost_divsqrt = 1; 1854 } 1855 1856 /* Disable FsMULd for the UT699 since it doesn't work correctly. */ 1857 if (sparc_fix_ut699) 1858 target_flags &= ~MASK_FSMULD; 1859 1860 /* Supply a default value for align_functions. */ 1861 if (align_functions == 0) 1862 { 1863 if (sparc_cpu == PROCESSOR_ULTRASPARC 1864 || sparc_cpu == PROCESSOR_ULTRASPARC3 1865 || sparc_cpu == PROCESSOR_NIAGARA 1866 || sparc_cpu == PROCESSOR_NIAGARA2 1867 || sparc_cpu == PROCESSOR_NIAGARA3 1868 || sparc_cpu == PROCESSOR_NIAGARA4) 1869 align_functions = 32; 1870 else if (sparc_cpu == PROCESSOR_NIAGARA7 1871 || sparc_cpu == PROCESSOR_M8) 1872 align_functions = 64; 1873 } 1874 1875 /* Validate PCC_STRUCT_RETURN. */ 1876 if (flag_pcc_struct_return == DEFAULT_PCC_STRUCT_RETURN) 1877 flag_pcc_struct_return = (TARGET_ARCH64 ? 0 : 1); 1878 1879 /* Only use .uaxword when compiling for a 64-bit target. */ 1880 if (!TARGET_ARCH64) 1881 targetm.asm_out.unaligned_op.di = NULL; 1882 1883 /* Do various machine dependent initializations. */ 1884 sparc_init_modes (); 1885 1886 /* Set up function hooks. */ 1887 init_machine_status = sparc_init_machine_status; 1888 1889 switch (sparc_cpu) 1890 { 1891 case PROCESSOR_V7: 1892 case PROCESSOR_CYPRESS: 1893 sparc_costs = &cypress_costs; 1894 break; 1895 case PROCESSOR_V8: 1896 case PROCESSOR_SPARCLITE: 1897 case PROCESSOR_SUPERSPARC: 1898 sparc_costs = &supersparc_costs; 1899 break; 1900 case PROCESSOR_F930: 1901 case PROCESSOR_F934: 1902 case PROCESSOR_HYPERSPARC: 1903 case PROCESSOR_SPARCLITE86X: 1904 sparc_costs = &hypersparc_costs; 1905 break; 1906 case PROCESSOR_LEON: 1907 sparc_costs = &leon_costs; 1908 break; 1909 case PROCESSOR_LEON3: 1910 case PROCESSOR_LEON3V7: 1911 sparc_costs = &leon3_costs; 1912 break; 1913 case PROCESSOR_SPARCLET: 1914 case PROCESSOR_TSC701: 1915 sparc_costs = &sparclet_costs; 1916 break; 1917 case PROCESSOR_V9: 1918 case PROCESSOR_ULTRASPARC: 1919 sparc_costs = &ultrasparc_costs; 1920 break; 1921 case PROCESSOR_ULTRASPARC3: 1922 sparc_costs = &ultrasparc3_costs; 1923 break; 1924 case PROCESSOR_NIAGARA: 1925 sparc_costs = &niagara_costs; 1926 break; 1927 case PROCESSOR_NIAGARA2: 1928 sparc_costs = &niagara2_costs; 1929 break; 1930 case PROCESSOR_NIAGARA3: 1931 sparc_costs = &niagara3_costs; 1932 break; 1933 case PROCESSOR_NIAGARA4: 1934 sparc_costs = &niagara4_costs; 1935 break; 1936 case PROCESSOR_NIAGARA7: 1937 sparc_costs = &niagara7_costs; 1938 break; 1939 case PROCESSOR_M8: 1940 sparc_costs = &m8_costs; 1941 break; 1942 case PROCESSOR_NATIVE: 1943 gcc_unreachable (); 1944 }; 1945 1946 if (sparc_memory_model == SMM_DEFAULT) 1947 { 1948 /* Choose the memory model for the operating system. */ 1949 enum sparc_memory_model_type os_default = SUBTARGET_DEFAULT_MEMORY_MODEL; 1950 if (os_default != SMM_DEFAULT) 1951 sparc_memory_model = os_default; 1952 /* Choose the most relaxed model for the processor. */ 1953 else if (TARGET_V9) 1954 sparc_memory_model = SMM_RMO; 1955 else if (TARGET_LEON3) 1956 sparc_memory_model = SMM_TSO; 1957 else if (TARGET_LEON) 1958 sparc_memory_model = SMM_SC; 1959 else if (TARGET_V8) 1960 sparc_memory_model = SMM_PSO; 1961 else 1962 sparc_memory_model = SMM_SC; 1963 } 1964 1965 #ifdef TARGET_DEFAULT_LONG_DOUBLE_128 1966 if (!(target_flags_explicit & MASK_LONG_DOUBLE_128)) 1967 target_flags |= MASK_LONG_DOUBLE_128; 1968 #endif 1969 1970 if (TARGET_DEBUG_OPTIONS) 1971 dump_target_flags ("Final target_flags", target_flags); 1972 1973 /* PARAM_SIMULTANEOUS_PREFETCHES is the number of prefetches that 1974 can run at the same time. More important, it is the threshold 1975 defining when additional prefetches will be dropped by the 1976 hardware. 1977 1978 The UltraSPARC-III features a documented prefetch queue with a 1979 size of 8. Additional prefetches issued in the cpu are 1980 dropped. 1981 1982 Niagara processors are different. In these processors prefetches 1983 are handled much like regular loads. The L1 miss buffer is 32 1984 entries, but prefetches start getting affected when 30 entries 1985 become occupied. That occupation could be a mix of regular loads 1986 and prefetches though. And that buffer is shared by all threads. 1987 Once the threshold is reached, if the core is running a single 1988 thread the prefetch will retry. If more than one thread is 1989 running, the prefetch will be dropped. 1990 1991 All this makes it very difficult to determine how many 1992 simultaneous prefetches can be issued simultaneously, even in a 1993 single-threaded program. Experimental results show that setting 1994 this parameter to 32 works well when the number of threads is not 1995 high. */ 1996 maybe_set_param_value (PARAM_SIMULTANEOUS_PREFETCHES, 1997 ((sparc_cpu == PROCESSOR_ULTRASPARC 1998 || sparc_cpu == PROCESSOR_NIAGARA 1999 || sparc_cpu == PROCESSOR_NIAGARA2 2000 || sparc_cpu == PROCESSOR_NIAGARA3 2001 || sparc_cpu == PROCESSOR_NIAGARA4) 2002 ? 2 2003 : (sparc_cpu == PROCESSOR_ULTRASPARC3 2004 ? 8 : ((sparc_cpu == PROCESSOR_NIAGARA7 2005 || sparc_cpu == PROCESSOR_M8) 2006 ? 32 : 3))), 2007 global_options.x_param_values, 2008 global_options_set.x_param_values); 2009 2010 /* PARAM_L1_CACHE_LINE_SIZE is the size of the L1 cache line, in 2011 bytes. 2012 2013 The Oracle SPARC Architecture (previously the UltraSPARC 2014 Architecture) specification states that when a PREFETCH[A] 2015 instruction is executed an implementation-specific amount of data 2016 is prefetched, and that it is at least 64 bytes long (aligned to 2017 at least 64 bytes). 2018 2019 However, this is not correct. The M7 (and implementations prior 2020 to that) does not guarantee a 64B prefetch into a cache if the 2021 line size is smaller. A single cache line is all that is ever 2022 prefetched. So for the M7, where the L1D$ has 32B lines and the 2023 L2D$ and L3 have 64B lines, a prefetch will prefetch 64B into the 2024 L2 and L3, but only 32B are brought into the L1D$. (Assuming it 2025 is a read_n prefetch, which is the only type which allocates to 2026 the L1.) */ 2027 maybe_set_param_value (PARAM_L1_CACHE_LINE_SIZE, 2028 (sparc_cpu == PROCESSOR_M8 2029 ? 64 : 32), 2030 global_options.x_param_values, 2031 global_options_set.x_param_values); 2032 2033 /* PARAM_L1_CACHE_SIZE is the size of the L1D$ (most SPARC chips use 2034 Hardvard level-1 caches) in kilobytes. Both UltraSPARC and 2035 Niagara processors feature a L1D$ of 16KB. */ 2036 maybe_set_param_value (PARAM_L1_CACHE_SIZE, 2037 ((sparc_cpu == PROCESSOR_ULTRASPARC 2038 || sparc_cpu == PROCESSOR_ULTRASPARC3 2039 || sparc_cpu == PROCESSOR_NIAGARA 2040 || sparc_cpu == PROCESSOR_NIAGARA2 2041 || sparc_cpu == PROCESSOR_NIAGARA3 2042 || sparc_cpu == PROCESSOR_NIAGARA4 2043 || sparc_cpu == PROCESSOR_NIAGARA7 2044 || sparc_cpu == PROCESSOR_M8) 2045 ? 16 : 64), 2046 global_options.x_param_values, 2047 global_options_set.x_param_values); 2048 2049 2050 /* PARAM_L2_CACHE_SIZE is the size fo the L2 in kilobytes. Note 2051 that 512 is the default in params.def. */ 2052 maybe_set_param_value (PARAM_L2_CACHE_SIZE, 2053 ((sparc_cpu == PROCESSOR_NIAGARA4 2054 || sparc_cpu == PROCESSOR_M8) 2055 ? 128 : (sparc_cpu == PROCESSOR_NIAGARA7 2056 ? 256 : 512)), 2057 global_options.x_param_values, 2058 global_options_set.x_param_values); 2059 2060 2061 /* Disable save slot sharing for call-clobbered registers by default. 2062 The IRA sharing algorithm works on single registers only and this 2063 pessimizes for double floating-point registers. */ 2064 if (!global_options_set.x_flag_ira_share_save_slots) 2065 flag_ira_share_save_slots = 0; 2066 2067 /* Only enable REE by default in 64-bit mode where it helps to eliminate 2068 redundant 32-to-64-bit extensions. */ 2069 if (!global_options_set.x_flag_ree && TARGET_ARCH32) 2070 flag_ree = 0; 2071 } 2072 2073 /* Miscellaneous utilities. */ 2074 2075 /* Nonzero if CODE, a comparison, is suitable for use in v9 conditional move 2076 or branch on register contents instructions. */ 2077 2078 int 2079 v9_regcmp_p (enum rtx_code code) 2080 { 2081 return (code == EQ || code == NE || code == GE || code == LT 2082 || code == LE || code == GT); 2083 } 2084 2085 /* Nonzero if OP is a floating point constant which can 2086 be loaded into an integer register using a single 2087 sethi instruction. */ 2088 2089 int 2090 fp_sethi_p (rtx op) 2091 { 2092 if (GET_CODE (op) == CONST_DOUBLE) 2093 { 2094 long i; 2095 2096 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), i); 2097 return !SPARC_SIMM13_P (i) && SPARC_SETHI_P (i); 2098 } 2099 2100 return 0; 2101 } 2102 2103 /* Nonzero if OP is a floating point constant which can 2104 be loaded into an integer register using a single 2105 mov instruction. */ 2106 2107 int 2108 fp_mov_p (rtx op) 2109 { 2110 if (GET_CODE (op) == CONST_DOUBLE) 2111 { 2112 long i; 2113 2114 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), i); 2115 return SPARC_SIMM13_P (i); 2116 } 2117 2118 return 0; 2119 } 2120 2121 /* Nonzero if OP is a floating point constant which can 2122 be loaded into an integer register using a high/losum 2123 instruction sequence. */ 2124 2125 int 2126 fp_high_losum_p (rtx op) 2127 { 2128 /* The constraints calling this should only be in 2129 SFmode move insns, so any constant which cannot 2130 be moved using a single insn will do. */ 2131 if (GET_CODE (op) == CONST_DOUBLE) 2132 { 2133 long i; 2134 2135 REAL_VALUE_TO_TARGET_SINGLE (*CONST_DOUBLE_REAL_VALUE (op), i); 2136 return !SPARC_SIMM13_P (i) && !SPARC_SETHI_P (i); 2137 } 2138 2139 return 0; 2140 } 2141 2142 /* Return true if the address of LABEL can be loaded by means of the 2143 mov{si,di}_pic_label_ref patterns in PIC mode. */ 2144 2145 static bool 2146 can_use_mov_pic_label_ref (rtx label) 2147 { 2148 /* VxWorks does not impose a fixed gap between segments; the run-time 2149 gap can be different from the object-file gap. We therefore can't 2150 assume X - _GLOBAL_OFFSET_TABLE_ is a link-time constant unless we 2151 are absolutely sure that X is in the same segment as the GOT. 2152 Unfortunately, the flexibility of linker scripts means that we 2153 can't be sure of that in general, so assume that GOT-relative 2154 accesses are never valid on VxWorks. */ 2155 if (TARGET_VXWORKS_RTP) 2156 return false; 2157 2158 /* Similarly, if the label is non-local, it might end up being placed 2159 in a different section than the current one; now mov_pic_label_ref 2160 requires the label and the code to be in the same section. */ 2161 if (LABEL_REF_NONLOCAL_P (label)) 2162 return false; 2163 2164 /* Finally, if we are reordering basic blocks and partition into hot 2165 and cold sections, this might happen for any label. */ 2166 if (flag_reorder_blocks_and_partition) 2167 return false; 2168 2169 return true; 2170 } 2171 2172 /* Expand a move instruction. Return true if all work is done. */ 2173 2174 bool 2175 sparc_expand_move (machine_mode mode, rtx *operands) 2176 { 2177 /* Handle sets of MEM first. */ 2178 if (GET_CODE (operands[0]) == MEM) 2179 { 2180 /* 0 is a register (or a pair of registers) on SPARC. */ 2181 if (register_or_zero_operand (operands[1], mode)) 2182 return false; 2183 2184 if (!reload_in_progress) 2185 { 2186 operands[0] = validize_mem (operands[0]); 2187 operands[1] = force_reg (mode, operands[1]); 2188 } 2189 } 2190 2191 /* Fix up TLS cases. */ 2192 if (TARGET_HAVE_TLS 2193 && CONSTANT_P (operands[1]) 2194 && sparc_tls_referenced_p (operands [1])) 2195 { 2196 operands[1] = sparc_legitimize_tls_address (operands[1]); 2197 return false; 2198 } 2199 2200 /* Fix up PIC cases. */ 2201 if (flag_pic && CONSTANT_P (operands[1])) 2202 { 2203 if (pic_address_needs_scratch (operands[1])) 2204 operands[1] = sparc_legitimize_pic_address (operands[1], NULL_RTX); 2205 2206 /* We cannot use the mov{si,di}_pic_label_ref patterns in all cases. */ 2207 if ((GET_CODE (operands[1]) == LABEL_REF 2208 && can_use_mov_pic_label_ref (operands[1])) 2209 || (GET_CODE (operands[1]) == CONST 2210 && GET_CODE (XEXP (operands[1], 0)) == PLUS 2211 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == LABEL_REF 2212 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT 2213 && can_use_mov_pic_label_ref (XEXP (XEXP (operands[1], 0), 0)))) 2214 { 2215 if (mode == SImode) 2216 { 2217 emit_insn (gen_movsi_pic_label_ref (operands[0], operands[1])); 2218 return true; 2219 } 2220 2221 if (mode == DImode) 2222 { 2223 emit_insn (gen_movdi_pic_label_ref (operands[0], operands[1])); 2224 return true; 2225 } 2226 } 2227 2228 if (symbolic_operand (operands[1], mode)) 2229 { 2230 operands[1] 2231 = sparc_legitimize_pic_address (operands[1], 2232 reload_in_progress 2233 ? operands[0] : NULL_RTX); 2234 return false; 2235 } 2236 } 2237 2238 /* If we are trying to toss an integer constant into FP registers, 2239 or loading a FP or vector constant, force it into memory. */ 2240 if (CONSTANT_P (operands[1]) 2241 && REG_P (operands[0]) 2242 && (SPARC_FP_REG_P (REGNO (operands[0])) 2243 || SCALAR_FLOAT_MODE_P (mode) 2244 || VECTOR_MODE_P (mode))) 2245 { 2246 /* emit_group_store will send such bogosity to us when it is 2247 not storing directly into memory. So fix this up to avoid 2248 crashes in output_constant_pool. */ 2249 if (operands [1] == const0_rtx) 2250 operands[1] = CONST0_RTX (mode); 2251 2252 /* We can clear or set to all-ones FP registers if TARGET_VIS, and 2253 always other regs. */ 2254 if ((TARGET_VIS || REGNO (operands[0]) < SPARC_FIRST_FP_REG) 2255 && (const_zero_operand (operands[1], mode) 2256 || const_all_ones_operand (operands[1], mode))) 2257 return false; 2258 2259 if (REGNO (operands[0]) < SPARC_FIRST_FP_REG 2260 /* We are able to build any SF constant in integer registers 2261 with at most 2 instructions. */ 2262 && (mode == SFmode 2263 /* And any DF constant in integer registers if needed. */ 2264 || (mode == DFmode && !can_create_pseudo_p ()))) 2265 return false; 2266 2267 operands[1] = force_const_mem (mode, operands[1]); 2268 if (!reload_in_progress) 2269 operands[1] = validize_mem (operands[1]); 2270 return false; 2271 } 2272 2273 /* Accept non-constants and valid constants unmodified. */ 2274 if (!CONSTANT_P (operands[1]) 2275 || GET_CODE (operands[1]) == HIGH 2276 || input_operand (operands[1], mode)) 2277 return false; 2278 2279 switch (mode) 2280 { 2281 case QImode: 2282 /* All QImode constants require only one insn, so proceed. */ 2283 break; 2284 2285 case HImode: 2286 case SImode: 2287 sparc_emit_set_const32 (operands[0], operands[1]); 2288 return true; 2289 2290 case DImode: 2291 /* input_operand should have filtered out 32-bit mode. */ 2292 sparc_emit_set_const64 (operands[0], operands[1]); 2293 return true; 2294 2295 case TImode: 2296 { 2297 rtx high, low; 2298 /* TImode isn't available in 32-bit mode. */ 2299 split_double (operands[1], &high, &low); 2300 emit_insn (gen_movdi (operand_subword (operands[0], 0, 0, TImode), 2301 high)); 2302 emit_insn (gen_movdi (operand_subword (operands[0], 1, 0, TImode), 2303 low)); 2304 } 2305 return true; 2306 2307 default: 2308 gcc_unreachable (); 2309 } 2310 2311 return false; 2312 } 2313 2314 /* Load OP1, a 32-bit constant, into OP0, a register. 2315 We know it can't be done in one insn when we get 2316 here, the move expander guarantees this. */ 2317 2318 static void 2319 sparc_emit_set_const32 (rtx op0, rtx op1) 2320 { 2321 machine_mode mode = GET_MODE (op0); 2322 rtx temp = op0; 2323 2324 if (can_create_pseudo_p ()) 2325 temp = gen_reg_rtx (mode); 2326 2327 if (GET_CODE (op1) == CONST_INT) 2328 { 2329 gcc_assert (!small_int_operand (op1, mode) 2330 && !const_high_operand (op1, mode)); 2331 2332 /* Emit them as real moves instead of a HIGH/LO_SUM, 2333 this way CSE can see everything and reuse intermediate 2334 values if it wants. */ 2335 emit_insn (gen_rtx_SET (temp, GEN_INT (INTVAL (op1) 2336 & ~(HOST_WIDE_INT) 0x3ff))); 2337 2338 emit_insn (gen_rtx_SET (op0, 2339 gen_rtx_IOR (mode, temp, 2340 GEN_INT (INTVAL (op1) & 0x3ff)))); 2341 } 2342 else 2343 { 2344 /* A symbol, emit in the traditional way. */ 2345 emit_insn (gen_rtx_SET (temp, gen_rtx_HIGH (mode, op1))); 2346 emit_insn (gen_rtx_SET (op0, gen_rtx_LO_SUM (mode, temp, op1))); 2347 } 2348 } 2349 2350 /* Load OP1, a symbolic 64-bit constant, into OP0, a DImode register. 2351 If TEMP is nonzero, we are forbidden to use any other scratch 2352 registers. Otherwise, we are allowed to generate them as needed. 2353 2354 Note that TEMP may have TImode if the code model is TARGET_CM_MEDANY 2355 or TARGET_CM_EMBMEDANY (see the reload_indi and reload_outdi patterns). */ 2356 2357 void 2358 sparc_emit_set_symbolic_const64 (rtx op0, rtx op1, rtx temp) 2359 { 2360 rtx temp1, temp2, temp3, temp4, temp5; 2361 rtx ti_temp = 0; 2362 2363 if (temp && GET_MODE (temp) == TImode) 2364 { 2365 ti_temp = temp; 2366 temp = gen_rtx_REG (DImode, REGNO (temp)); 2367 } 2368 2369 /* SPARC-V9 code-model support. */ 2370 switch (sparc_cmodel) 2371 { 2372 case CM_MEDLOW: 2373 /* The range spanned by all instructions in the object is less 2374 than 2^31 bytes (2GB) and the distance from any instruction 2375 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 2376 than 2^31 bytes (2GB). 2377 2378 The executable must be in the low 4TB of the virtual address 2379 space. 2380 2381 sethi %hi(symbol), %temp1 2382 or %temp1, %lo(symbol), %reg */ 2383 if (temp) 2384 temp1 = temp; /* op0 is allowed. */ 2385 else 2386 temp1 = gen_reg_rtx (DImode); 2387 2388 emit_insn (gen_rtx_SET (temp1, gen_rtx_HIGH (DImode, op1))); 2389 emit_insn (gen_rtx_SET (op0, gen_rtx_LO_SUM (DImode, temp1, op1))); 2390 break; 2391 2392 case CM_MEDMID: 2393 /* The range spanned by all instructions in the object is less 2394 than 2^31 bytes (2GB) and the distance from any instruction 2395 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 2396 than 2^31 bytes (2GB). 2397 2398 The executable must be in the low 16TB of the virtual address 2399 space. 2400 2401 sethi %h44(symbol), %temp1 2402 or %temp1, %m44(symbol), %temp2 2403 sllx %temp2, 12, %temp3 2404 or %temp3, %l44(symbol), %reg */ 2405 if (temp) 2406 { 2407 temp1 = op0; 2408 temp2 = op0; 2409 temp3 = temp; /* op0 is allowed. */ 2410 } 2411 else 2412 { 2413 temp1 = gen_reg_rtx (DImode); 2414 temp2 = gen_reg_rtx (DImode); 2415 temp3 = gen_reg_rtx (DImode); 2416 } 2417 2418 emit_insn (gen_seth44 (temp1, op1)); 2419 emit_insn (gen_setm44 (temp2, temp1, op1)); 2420 emit_insn (gen_rtx_SET (temp3, 2421 gen_rtx_ASHIFT (DImode, temp2, GEN_INT (12)))); 2422 emit_insn (gen_setl44 (op0, temp3, op1)); 2423 break; 2424 2425 case CM_MEDANY: 2426 /* The range spanned by all instructions in the object is less 2427 than 2^31 bytes (2GB) and the distance from any instruction 2428 to the location of the label _GLOBAL_OFFSET_TABLE_ is less 2429 than 2^31 bytes (2GB). 2430 2431 The executable can be placed anywhere in the virtual address 2432 space. 2433 2434 sethi %hh(symbol), %temp1 2435 sethi %lm(symbol), %temp2 2436 or %temp1, %hm(symbol), %temp3 2437 sllx %temp3, 32, %temp4 2438 or %temp4, %temp2, %temp5 2439 or %temp5, %lo(symbol), %reg */ 2440 if (temp) 2441 { 2442 /* It is possible that one of the registers we got for operands[2] 2443 might coincide with that of operands[0] (which is why we made 2444 it TImode). Pick the other one to use as our scratch. */ 2445 if (rtx_equal_p (temp, op0)) 2446 { 2447 gcc_assert (ti_temp); 2448 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); 2449 } 2450 temp1 = op0; 2451 temp2 = temp; /* op0 is _not_ allowed, see above. */ 2452 temp3 = op0; 2453 temp4 = op0; 2454 temp5 = op0; 2455 } 2456 else 2457 { 2458 temp1 = gen_reg_rtx (DImode); 2459 temp2 = gen_reg_rtx (DImode); 2460 temp3 = gen_reg_rtx (DImode); 2461 temp4 = gen_reg_rtx (DImode); 2462 temp5 = gen_reg_rtx (DImode); 2463 } 2464 2465 emit_insn (gen_sethh (temp1, op1)); 2466 emit_insn (gen_setlm (temp2, op1)); 2467 emit_insn (gen_sethm (temp3, temp1, op1)); 2468 emit_insn (gen_rtx_SET (temp4, 2469 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); 2470 emit_insn (gen_rtx_SET (temp5, gen_rtx_PLUS (DImode, temp4, temp2))); 2471 emit_insn (gen_setlo (op0, temp5, op1)); 2472 break; 2473 2474 case CM_EMBMEDANY: 2475 /* Old old old backwards compatibility kruft here. 2476 Essentially it is MEDLOW with a fixed 64-bit 2477 virtual base added to all data segment addresses. 2478 Text-segment stuff is computed like MEDANY, we can't 2479 reuse the code above because the relocation knobs 2480 look different. 2481 2482 Data segment: sethi %hi(symbol), %temp1 2483 add %temp1, EMBMEDANY_BASE_REG, %temp2 2484 or %temp2, %lo(symbol), %reg */ 2485 if (data_segment_operand (op1, GET_MODE (op1))) 2486 { 2487 if (temp) 2488 { 2489 temp1 = temp; /* op0 is allowed. */ 2490 temp2 = op0; 2491 } 2492 else 2493 { 2494 temp1 = gen_reg_rtx (DImode); 2495 temp2 = gen_reg_rtx (DImode); 2496 } 2497 2498 emit_insn (gen_embmedany_sethi (temp1, op1)); 2499 emit_insn (gen_embmedany_brsum (temp2, temp1)); 2500 emit_insn (gen_embmedany_losum (op0, temp2, op1)); 2501 } 2502 2503 /* Text segment: sethi %uhi(symbol), %temp1 2504 sethi %hi(symbol), %temp2 2505 or %temp1, %ulo(symbol), %temp3 2506 sllx %temp3, 32, %temp4 2507 or %temp4, %temp2, %temp5 2508 or %temp5, %lo(symbol), %reg */ 2509 else 2510 { 2511 if (temp) 2512 { 2513 /* It is possible that one of the registers we got for operands[2] 2514 might coincide with that of operands[0] (which is why we made 2515 it TImode). Pick the other one to use as our scratch. */ 2516 if (rtx_equal_p (temp, op0)) 2517 { 2518 gcc_assert (ti_temp); 2519 temp = gen_rtx_REG (DImode, REGNO (temp) + 1); 2520 } 2521 temp1 = op0; 2522 temp2 = temp; /* op0 is _not_ allowed, see above. */ 2523 temp3 = op0; 2524 temp4 = op0; 2525 temp5 = op0; 2526 } 2527 else 2528 { 2529 temp1 = gen_reg_rtx (DImode); 2530 temp2 = gen_reg_rtx (DImode); 2531 temp3 = gen_reg_rtx (DImode); 2532 temp4 = gen_reg_rtx (DImode); 2533 temp5 = gen_reg_rtx (DImode); 2534 } 2535 2536 emit_insn (gen_embmedany_textuhi (temp1, op1)); 2537 emit_insn (gen_embmedany_texthi (temp2, op1)); 2538 emit_insn (gen_embmedany_textulo (temp3, temp1, op1)); 2539 emit_insn (gen_rtx_SET (temp4, 2540 gen_rtx_ASHIFT (DImode, temp3, GEN_INT (32)))); 2541 emit_insn (gen_rtx_SET (temp5, gen_rtx_PLUS (DImode, temp4, temp2))); 2542 emit_insn (gen_embmedany_textlo (op0, temp5, op1)); 2543 } 2544 break; 2545 2546 default: 2547 gcc_unreachable (); 2548 } 2549 } 2550 2551 /* These avoid problems when cross compiling. If we do not 2552 go through all this hair then the optimizer will see 2553 invalid REG_EQUAL notes or in some cases none at all. */ 2554 static rtx gen_safe_HIGH64 (rtx, HOST_WIDE_INT); 2555 static rtx gen_safe_SET64 (rtx, HOST_WIDE_INT); 2556 static rtx gen_safe_OR64 (rtx, HOST_WIDE_INT); 2557 static rtx gen_safe_XOR64 (rtx, HOST_WIDE_INT); 2558 2559 /* The optimizer is not to assume anything about exactly 2560 which bits are set for a HIGH, they are unspecified. 2561 Unfortunately this leads to many missed optimizations 2562 during CSE. We mask out the non-HIGH bits, and matches 2563 a plain movdi, to alleviate this problem. */ 2564 static rtx 2565 gen_safe_HIGH64 (rtx dest, HOST_WIDE_INT val) 2566 { 2567 return gen_rtx_SET (dest, GEN_INT (val & ~(HOST_WIDE_INT)0x3ff)); 2568 } 2569 2570 static rtx 2571 gen_safe_SET64 (rtx dest, HOST_WIDE_INT val) 2572 { 2573 return gen_rtx_SET (dest, GEN_INT (val)); 2574 } 2575 2576 static rtx 2577 gen_safe_OR64 (rtx src, HOST_WIDE_INT val) 2578 { 2579 return gen_rtx_IOR (DImode, src, GEN_INT (val)); 2580 } 2581 2582 static rtx 2583 gen_safe_XOR64 (rtx src, HOST_WIDE_INT val) 2584 { 2585 return gen_rtx_XOR (DImode, src, GEN_INT (val)); 2586 } 2587 2588 /* Worker routines for 64-bit constant formation on arch64. 2589 One of the key things to be doing in these emissions is 2590 to create as many temp REGs as possible. This makes it 2591 possible for half-built constants to be used later when 2592 such values are similar to something required later on. 2593 Without doing this, the optimizer cannot see such 2594 opportunities. */ 2595 2596 static void sparc_emit_set_const64_quick1 (rtx, rtx, 2597 unsigned HOST_WIDE_INT, int); 2598 2599 static void 2600 sparc_emit_set_const64_quick1 (rtx op0, rtx temp, 2601 unsigned HOST_WIDE_INT low_bits, int is_neg) 2602 { 2603 unsigned HOST_WIDE_INT high_bits; 2604 2605 if (is_neg) 2606 high_bits = (~low_bits) & 0xffffffff; 2607 else 2608 high_bits = low_bits; 2609 2610 emit_insn (gen_safe_HIGH64 (temp, high_bits)); 2611 if (!is_neg) 2612 { 2613 emit_insn (gen_rtx_SET (op0, gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 2614 } 2615 else 2616 { 2617 /* If we are XOR'ing with -1, then we should emit a one's complement 2618 instead. This way the combiner will notice logical operations 2619 such as ANDN later on and substitute. */ 2620 if ((low_bits & 0x3ff) == 0x3ff) 2621 { 2622 emit_insn (gen_rtx_SET (op0, gen_rtx_NOT (DImode, temp))); 2623 } 2624 else 2625 { 2626 emit_insn (gen_rtx_SET (op0, 2627 gen_safe_XOR64 (temp, 2628 (-(HOST_WIDE_INT)0x400 2629 | (low_bits & 0x3ff))))); 2630 } 2631 } 2632 } 2633 2634 static void sparc_emit_set_const64_quick2 (rtx, rtx, unsigned HOST_WIDE_INT, 2635 unsigned HOST_WIDE_INT, int); 2636 2637 static void 2638 sparc_emit_set_const64_quick2 (rtx op0, rtx temp, 2639 unsigned HOST_WIDE_INT high_bits, 2640 unsigned HOST_WIDE_INT low_immediate, 2641 int shift_count) 2642 { 2643 rtx temp2 = op0; 2644 2645 if ((high_bits & 0xfffffc00) != 0) 2646 { 2647 emit_insn (gen_safe_HIGH64 (temp, high_bits)); 2648 if ((high_bits & ~0xfffffc00) != 0) 2649 emit_insn (gen_rtx_SET (op0, 2650 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 2651 else 2652 temp2 = temp; 2653 } 2654 else 2655 { 2656 emit_insn (gen_safe_SET64 (temp, high_bits)); 2657 temp2 = temp; 2658 } 2659 2660 /* Now shift it up into place. */ 2661 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, temp2, 2662 GEN_INT (shift_count)))); 2663 2664 /* If there is a low immediate part piece, finish up by 2665 putting that in as well. */ 2666 if (low_immediate != 0) 2667 emit_insn (gen_rtx_SET (op0, gen_safe_OR64 (op0, low_immediate))); 2668 } 2669 2670 static void sparc_emit_set_const64_longway (rtx, rtx, unsigned HOST_WIDE_INT, 2671 unsigned HOST_WIDE_INT); 2672 2673 /* Full 64-bit constant decomposition. Even though this is the 2674 'worst' case, we still optimize a few things away. */ 2675 static void 2676 sparc_emit_set_const64_longway (rtx op0, rtx temp, 2677 unsigned HOST_WIDE_INT high_bits, 2678 unsigned HOST_WIDE_INT low_bits) 2679 { 2680 rtx sub_temp = op0; 2681 2682 if (can_create_pseudo_p ()) 2683 sub_temp = gen_reg_rtx (DImode); 2684 2685 if ((high_bits & 0xfffffc00) != 0) 2686 { 2687 emit_insn (gen_safe_HIGH64 (temp, high_bits)); 2688 if ((high_bits & ~0xfffffc00) != 0) 2689 emit_insn (gen_rtx_SET (sub_temp, 2690 gen_safe_OR64 (temp, (high_bits & 0x3ff)))); 2691 else 2692 sub_temp = temp; 2693 } 2694 else 2695 { 2696 emit_insn (gen_safe_SET64 (temp, high_bits)); 2697 sub_temp = temp; 2698 } 2699 2700 if (can_create_pseudo_p ()) 2701 { 2702 rtx temp2 = gen_reg_rtx (DImode); 2703 rtx temp3 = gen_reg_rtx (DImode); 2704 rtx temp4 = gen_reg_rtx (DImode); 2705 2706 emit_insn (gen_rtx_SET (temp4, gen_rtx_ASHIFT (DImode, sub_temp, 2707 GEN_INT (32)))); 2708 2709 emit_insn (gen_safe_HIGH64 (temp2, low_bits)); 2710 if ((low_bits & ~0xfffffc00) != 0) 2711 { 2712 emit_insn (gen_rtx_SET (temp3, 2713 gen_safe_OR64 (temp2, (low_bits & 0x3ff)))); 2714 emit_insn (gen_rtx_SET (op0, gen_rtx_PLUS (DImode, temp4, temp3))); 2715 } 2716 else 2717 { 2718 emit_insn (gen_rtx_SET (op0, gen_rtx_PLUS (DImode, temp4, temp2))); 2719 } 2720 } 2721 else 2722 { 2723 rtx low1 = GEN_INT ((low_bits >> (32 - 12)) & 0xfff); 2724 rtx low2 = GEN_INT ((low_bits >> (32 - 12 - 12)) & 0xfff); 2725 rtx low3 = GEN_INT ((low_bits >> (32 - 12 - 12 - 8)) & 0x0ff); 2726 int to_shift = 12; 2727 2728 /* We are in the middle of reload, so this is really 2729 painful. However we do still make an attempt to 2730 avoid emitting truly stupid code. */ 2731 if (low1 != const0_rtx) 2732 { 2733 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, sub_temp, 2734 GEN_INT (to_shift)))); 2735 emit_insn (gen_rtx_SET (op0, gen_rtx_IOR (DImode, op0, low1))); 2736 sub_temp = op0; 2737 to_shift = 12; 2738 } 2739 else 2740 { 2741 to_shift += 12; 2742 } 2743 if (low2 != const0_rtx) 2744 { 2745 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, sub_temp, 2746 GEN_INT (to_shift)))); 2747 emit_insn (gen_rtx_SET (op0, gen_rtx_IOR (DImode, op0, low2))); 2748 sub_temp = op0; 2749 to_shift = 8; 2750 } 2751 else 2752 { 2753 to_shift += 8; 2754 } 2755 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, sub_temp, 2756 GEN_INT (to_shift)))); 2757 if (low3 != const0_rtx) 2758 emit_insn (gen_rtx_SET (op0, gen_rtx_IOR (DImode, op0, low3))); 2759 /* phew... */ 2760 } 2761 } 2762 2763 /* Analyze a 64-bit constant for certain properties. */ 2764 static void analyze_64bit_constant (unsigned HOST_WIDE_INT, 2765 unsigned HOST_WIDE_INT, 2766 int *, int *, int *); 2767 2768 static void 2769 analyze_64bit_constant (unsigned HOST_WIDE_INT high_bits, 2770 unsigned HOST_WIDE_INT low_bits, 2771 int *hbsp, int *lbsp, int *abbasp) 2772 { 2773 int lowest_bit_set, highest_bit_set, all_bits_between_are_set; 2774 int i; 2775 2776 lowest_bit_set = highest_bit_set = -1; 2777 i = 0; 2778 do 2779 { 2780 if ((lowest_bit_set == -1) 2781 && ((low_bits >> i) & 1)) 2782 lowest_bit_set = i; 2783 if ((highest_bit_set == -1) 2784 && ((high_bits >> (32 - i - 1)) & 1)) 2785 highest_bit_set = (64 - i - 1); 2786 } 2787 while (++i < 32 2788 && ((highest_bit_set == -1) 2789 || (lowest_bit_set == -1))); 2790 if (i == 32) 2791 { 2792 i = 0; 2793 do 2794 { 2795 if ((lowest_bit_set == -1) 2796 && ((high_bits >> i) & 1)) 2797 lowest_bit_set = i + 32; 2798 if ((highest_bit_set == -1) 2799 && ((low_bits >> (32 - i - 1)) & 1)) 2800 highest_bit_set = 32 - i - 1; 2801 } 2802 while (++i < 32 2803 && ((highest_bit_set == -1) 2804 || (lowest_bit_set == -1))); 2805 } 2806 /* If there are no bits set this should have gone out 2807 as one instruction! */ 2808 gcc_assert (lowest_bit_set != -1 && highest_bit_set != -1); 2809 all_bits_between_are_set = 1; 2810 for (i = lowest_bit_set; i <= highest_bit_set; i++) 2811 { 2812 if (i < 32) 2813 { 2814 if ((low_bits & (1 << i)) != 0) 2815 continue; 2816 } 2817 else 2818 { 2819 if ((high_bits & (1 << (i - 32))) != 0) 2820 continue; 2821 } 2822 all_bits_between_are_set = 0; 2823 break; 2824 } 2825 *hbsp = highest_bit_set; 2826 *lbsp = lowest_bit_set; 2827 *abbasp = all_bits_between_are_set; 2828 } 2829 2830 static int const64_is_2insns (unsigned HOST_WIDE_INT, unsigned HOST_WIDE_INT); 2831 2832 static int 2833 const64_is_2insns (unsigned HOST_WIDE_INT high_bits, 2834 unsigned HOST_WIDE_INT low_bits) 2835 { 2836 int highest_bit_set, lowest_bit_set, all_bits_between_are_set; 2837 2838 if (high_bits == 0 2839 || high_bits == 0xffffffff) 2840 return 1; 2841 2842 analyze_64bit_constant (high_bits, low_bits, 2843 &highest_bit_set, &lowest_bit_set, 2844 &all_bits_between_are_set); 2845 2846 if ((highest_bit_set == 63 2847 || lowest_bit_set == 0) 2848 && all_bits_between_are_set != 0) 2849 return 1; 2850 2851 if ((highest_bit_set - lowest_bit_set) < 21) 2852 return 1; 2853 2854 return 0; 2855 } 2856 2857 static unsigned HOST_WIDE_INT create_simple_focus_bits (unsigned HOST_WIDE_INT, 2858 unsigned HOST_WIDE_INT, 2859 int, int); 2860 2861 static unsigned HOST_WIDE_INT 2862 create_simple_focus_bits (unsigned HOST_WIDE_INT high_bits, 2863 unsigned HOST_WIDE_INT low_bits, 2864 int lowest_bit_set, int shift) 2865 { 2866 HOST_WIDE_INT hi, lo; 2867 2868 if (lowest_bit_set < 32) 2869 { 2870 lo = (low_bits >> lowest_bit_set) << shift; 2871 hi = ((high_bits << (32 - lowest_bit_set)) << shift); 2872 } 2873 else 2874 { 2875 lo = 0; 2876 hi = ((high_bits >> (lowest_bit_set - 32)) << shift); 2877 } 2878 gcc_assert (! (hi & lo)); 2879 return (hi | lo); 2880 } 2881 2882 /* Here we are sure to be arch64 and this is an integer constant 2883 being loaded into a register. Emit the most efficient 2884 insn sequence possible. Detection of all the 1-insn cases 2885 has been done already. */ 2886 static void 2887 sparc_emit_set_const64 (rtx op0, rtx op1) 2888 { 2889 unsigned HOST_WIDE_INT high_bits, low_bits; 2890 int lowest_bit_set, highest_bit_set; 2891 int all_bits_between_are_set; 2892 rtx temp = 0; 2893 2894 /* Sanity check that we know what we are working with. */ 2895 gcc_assert (TARGET_ARCH64 2896 && (GET_CODE (op0) == SUBREG 2897 || (REG_P (op0) && ! SPARC_FP_REG_P (REGNO (op0))))); 2898 2899 if (! can_create_pseudo_p ()) 2900 temp = op0; 2901 2902 if (GET_CODE (op1) != CONST_INT) 2903 { 2904 sparc_emit_set_symbolic_const64 (op0, op1, temp); 2905 return; 2906 } 2907 2908 if (! temp) 2909 temp = gen_reg_rtx (DImode); 2910 2911 high_bits = ((INTVAL (op1) >> 32) & 0xffffffff); 2912 low_bits = (INTVAL (op1) & 0xffffffff); 2913 2914 /* low_bits bits 0 --> 31 2915 high_bits bits 32 --> 63 */ 2916 2917 analyze_64bit_constant (high_bits, low_bits, 2918 &highest_bit_set, &lowest_bit_set, 2919 &all_bits_between_are_set); 2920 2921 /* First try for a 2-insn sequence. */ 2922 2923 /* These situations are preferred because the optimizer can 2924 * do more things with them: 2925 * 1) mov -1, %reg 2926 * sllx %reg, shift, %reg 2927 * 2) mov -1, %reg 2928 * srlx %reg, shift, %reg 2929 * 3) mov some_small_const, %reg 2930 * sllx %reg, shift, %reg 2931 */ 2932 if (((highest_bit_set == 63 2933 || lowest_bit_set == 0) 2934 && all_bits_between_are_set != 0) 2935 || ((highest_bit_set - lowest_bit_set) < 12)) 2936 { 2937 HOST_WIDE_INT the_const = -1; 2938 int shift = lowest_bit_set; 2939 2940 if ((highest_bit_set != 63 2941 && lowest_bit_set != 0) 2942 || all_bits_between_are_set == 0) 2943 { 2944 the_const = 2945 create_simple_focus_bits (high_bits, low_bits, 2946 lowest_bit_set, 0); 2947 } 2948 else if (lowest_bit_set == 0) 2949 shift = -(63 - highest_bit_set); 2950 2951 gcc_assert (SPARC_SIMM13_P (the_const)); 2952 gcc_assert (shift != 0); 2953 2954 emit_insn (gen_safe_SET64 (temp, the_const)); 2955 if (shift > 0) 2956 emit_insn (gen_rtx_SET (op0, gen_rtx_ASHIFT (DImode, temp, 2957 GEN_INT (shift)))); 2958 else if (shift < 0) 2959 emit_insn (gen_rtx_SET (op0, gen_rtx_LSHIFTRT (DImode, temp, 2960 GEN_INT (-shift)))); 2961 return; 2962 } 2963 2964 /* Now a range of 22 or less bits set somewhere. 2965 * 1) sethi %hi(focus_bits), %reg 2966 * sllx %reg, shift, %reg 2967 * 2) sethi %hi(focus_bits), %reg 2968 * srlx %reg, shift, %reg 2969 */ 2970 if ((highest_bit_set - lowest_bit_set) < 21) 2971 { 2972 unsigned HOST_WIDE_INT focus_bits = 2973 create_simple_focus_bits (high_bits, low_bits, 2974 lowest_bit_set, 10); 2975 2976 gcc_assert (SPARC_SETHI_P (focus_bits)); 2977 gcc_assert (lowest_bit_set != 10); 2978 2979 emit_insn (gen_safe_HIGH64 (temp, focus_bits)); 2980 2981 /* If lowest_bit_set == 10 then a sethi alone could have done it. */ 2982 if (lowest_bit_set < 10) 2983 emit_insn (gen_rtx_SET (op0, 2984 gen_rtx_LSHIFTRT (DImode, temp, 2985 GEN_INT (10 - lowest_bit_set)))); 2986 else if (lowest_bit_set > 10) 2987 emit_insn (gen_rtx_SET (op0, 2988 gen_rtx_ASHIFT (DImode, temp, 2989 GEN_INT (lowest_bit_set - 10)))); 2990 return; 2991 } 2992 2993 /* 1) sethi %hi(low_bits), %reg 2994 * or %reg, %lo(low_bits), %reg 2995 * 2) sethi %hi(~low_bits), %reg 2996 * xor %reg, %lo(-0x400 | (low_bits & 0x3ff)), %reg 2997 */ 2998 if (high_bits == 0 2999 || high_bits == 0xffffffff) 3000 { 3001 sparc_emit_set_const64_quick1 (op0, temp, low_bits, 3002 (high_bits == 0xffffffff)); 3003 return; 3004 } 3005 3006 /* Now, try 3-insn sequences. */ 3007 3008 /* 1) sethi %hi(high_bits), %reg 3009 * or %reg, %lo(high_bits), %reg 3010 * sllx %reg, 32, %reg 3011 */ 3012 if (low_bits == 0) 3013 { 3014 sparc_emit_set_const64_quick2 (op0, temp, high_bits, 0, 32); 3015 return; 3016 } 3017 3018 /* We may be able to do something quick 3019 when the constant is negated, so try that. */ 3020 if (const64_is_2insns ((~high_bits) & 0xffffffff, 3021 (~low_bits) & 0xfffffc00)) 3022 { 3023 /* NOTE: The trailing bits get XOR'd so we need the 3024 non-negated bits, not the negated ones. */ 3025 unsigned HOST_WIDE_INT trailing_bits = low_bits & 0x3ff; 3026 3027 if ((((~high_bits) & 0xffffffff) == 0 3028 && ((~low_bits) & 0x80000000) == 0) 3029 || (((~high_bits) & 0xffffffff) == 0xffffffff 3030 && ((~low_bits) & 0x80000000) != 0)) 3031 { 3032 unsigned HOST_WIDE_INT fast_int = (~low_bits & 0xffffffff); 3033 3034 if ((SPARC_SETHI_P (fast_int) 3035 && (~high_bits & 0xffffffff) == 0) 3036 || SPARC_SIMM13_P (fast_int)) 3037 emit_insn (gen_safe_SET64 (temp, fast_int)); 3038 else 3039 sparc_emit_set_const64 (temp, GEN_INT (fast_int)); 3040 } 3041 else 3042 { 3043 rtx negated_const; 3044 negated_const = GEN_INT (((~low_bits) & 0xfffffc00) | 3045 (((HOST_WIDE_INT)((~high_bits) & 0xffffffff))<<32)); 3046 sparc_emit_set_const64 (temp, negated_const); 3047 } 3048 3049 /* If we are XOR'ing with -1, then we should emit a one's complement 3050 instead. This way the combiner will notice logical operations 3051 such as ANDN later on and substitute. */ 3052 if (trailing_bits == 0x3ff) 3053 { 3054 emit_insn (gen_rtx_SET (op0, gen_rtx_NOT (DImode, temp))); 3055 } 3056 else 3057 { 3058 emit_insn (gen_rtx_SET (op0, 3059 gen_safe_XOR64 (temp, 3060 (-0x400 | trailing_bits)))); 3061 } 3062 return; 3063 } 3064 3065 /* 1) sethi %hi(xxx), %reg 3066 * or %reg, %lo(xxx), %reg 3067 * sllx %reg, yyy, %reg 3068 * 3069 * ??? This is just a generalized version of the low_bits==0 3070 * thing above, FIXME... 3071 */ 3072 if ((highest_bit_set - lowest_bit_set) < 32) 3073 { 3074 unsigned HOST_WIDE_INT focus_bits = 3075 create_simple_focus_bits (high_bits, low_bits, 3076 lowest_bit_set, 0); 3077 3078 /* We can't get here in this state. */ 3079 gcc_assert (highest_bit_set >= 32 && lowest_bit_set < 32); 3080 3081 /* So what we know is that the set bits straddle the 3082 middle of the 64-bit word. */ 3083 sparc_emit_set_const64_quick2 (op0, temp, 3084 focus_bits, 0, 3085 lowest_bit_set); 3086 return; 3087 } 3088 3089 /* 1) sethi %hi(high_bits), %reg 3090 * or %reg, %lo(high_bits), %reg 3091 * sllx %reg, 32, %reg 3092 * or %reg, low_bits, %reg 3093 */ 3094 if (SPARC_SIMM13_P (low_bits) && ((int)low_bits > 0)) 3095 { 3096 sparc_emit_set_const64_quick2 (op0, temp, high_bits, low_bits, 32); 3097 return; 3098 } 3099 3100 /* The easiest way when all else fails, is full decomposition. */ 3101 sparc_emit_set_const64_longway (op0, temp, high_bits, low_bits); 3102 } 3103 3104 /* Implement TARGET_FIXED_CONDITION_CODE_REGS. */ 3105 3106 static bool 3107 sparc_fixed_condition_code_regs (unsigned int *p1, unsigned int *p2) 3108 { 3109 *p1 = SPARC_ICC_REG; 3110 *p2 = SPARC_FCC_REG; 3111 return true; 3112 } 3113 3114 /* Implement TARGET_MIN_ARITHMETIC_PRECISION. */ 3115 3116 static unsigned int 3117 sparc_min_arithmetic_precision (void) 3118 { 3119 return 32; 3120 } 3121 3122 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 3123 return the mode to be used for the comparison. For floating-point, 3124 CCFP[E]mode is used. CCNZmode should be used when the first operand 3125 is a PLUS, MINUS, NEG, or ASHIFT. CCmode should be used when no special 3126 processing is needed. */ 3127 3128 machine_mode 3129 select_cc_mode (enum rtx_code op, rtx x, rtx y) 3130 { 3131 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 3132 { 3133 switch (op) 3134 { 3135 case EQ: 3136 case NE: 3137 case UNORDERED: 3138 case ORDERED: 3139 case UNLT: 3140 case UNLE: 3141 case UNGT: 3142 case UNGE: 3143 case UNEQ: 3144 case LTGT: 3145 return CCFPmode; 3146 3147 case LT: 3148 case LE: 3149 case GT: 3150 case GE: 3151 return CCFPEmode; 3152 3153 default: 3154 gcc_unreachable (); 3155 } 3156 } 3157 else if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS 3158 || GET_CODE (x) == NEG || GET_CODE (x) == ASHIFT) 3159 && y == const0_rtx) 3160 { 3161 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 3162 return CCXNZmode; 3163 else 3164 return CCNZmode; 3165 } 3166 else 3167 { 3168 /* This is for the cmp<mode>_sne pattern. */ 3169 if (GET_CODE (x) == NOT && y == constm1_rtx) 3170 { 3171 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 3172 return CCXCmode; 3173 else 3174 return CCCmode; 3175 } 3176 3177 /* This is for the [u]addvdi4_sp32 and [u]subvdi4_sp32 patterns. */ 3178 if (!TARGET_ARCH64 && GET_MODE (x) == DImode) 3179 { 3180 if (GET_CODE (y) == UNSPEC 3181 && (XINT (y, 1) == UNSPEC_ADDV 3182 || XINT (y, 1) == UNSPEC_SUBV 3183 || XINT (y, 1) == UNSPEC_NEGV)) 3184 return CCVmode; 3185 else 3186 return CCCmode; 3187 } 3188 3189 if (TARGET_ARCH64 && GET_MODE (x) == DImode) 3190 return CCXmode; 3191 else 3192 return CCmode; 3193 } 3194 } 3195 3196 /* Emit the compare insn and return the CC reg for a CODE comparison 3197 with operands X and Y. */ 3198 3199 static rtx 3200 gen_compare_reg_1 (enum rtx_code code, rtx x, rtx y) 3201 { 3202 machine_mode mode; 3203 rtx cc_reg; 3204 3205 if (GET_MODE_CLASS (GET_MODE (x)) == MODE_CC) 3206 return x; 3207 3208 mode = SELECT_CC_MODE (code, x, y); 3209 3210 /* ??? We don't have movcc patterns so we cannot generate pseudo regs for the 3211 fcc regs (cse can't tell they're really call clobbered regs and will 3212 remove a duplicate comparison even if there is an intervening function 3213 call - it will then try to reload the cc reg via an int reg which is why 3214 we need the movcc patterns). It is possible to provide the movcc 3215 patterns by using the ldxfsr/stxfsr v9 insns. I tried it: you need two 3216 registers (say %g1,%g5) and it takes about 6 insns. A better fix would be 3217 to tell cse that CCFPE mode registers (even pseudos) are call 3218 clobbered. */ 3219 3220 /* ??? This is an experiment. Rather than making changes to cse which may 3221 or may not be easy/clean, we do our own cse. This is possible because 3222 we will generate hard registers. Cse knows they're call clobbered (it 3223 doesn't know the same thing about pseudos). If we guess wrong, no big 3224 deal, but if we win, great! */ 3225 3226 if (TARGET_V9 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 3227 #if 1 /* experiment */ 3228 { 3229 int reg; 3230 /* We cycle through the registers to ensure they're all exercised. */ 3231 static int next_fcc_reg = 0; 3232 /* Previous x,y for each fcc reg. */ 3233 static rtx prev_args[4][2]; 3234 3235 /* Scan prev_args for x,y. */ 3236 for (reg = 0; reg < 4; reg++) 3237 if (prev_args[reg][0] == x && prev_args[reg][1] == y) 3238 break; 3239 if (reg == 4) 3240 { 3241 reg = next_fcc_reg; 3242 prev_args[reg][0] = x; 3243 prev_args[reg][1] = y; 3244 next_fcc_reg = (next_fcc_reg + 1) & 3; 3245 } 3246 cc_reg = gen_rtx_REG (mode, reg + SPARC_FIRST_V9_FCC_REG); 3247 } 3248 #else 3249 cc_reg = gen_reg_rtx (mode); 3250 #endif /* ! experiment */ 3251 else if (GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 3252 cc_reg = gen_rtx_REG (mode, SPARC_FCC_REG); 3253 else 3254 cc_reg = gen_rtx_REG (mode, SPARC_ICC_REG); 3255 3256 /* We shouldn't get there for TFmode if !TARGET_HARD_QUAD. If we do, this 3257 will only result in an unrecognizable insn so no point in asserting. */ 3258 emit_insn (gen_rtx_SET (cc_reg, gen_rtx_COMPARE (mode, x, y))); 3259 3260 return cc_reg; 3261 } 3262 3263 3264 /* Emit the compare insn and return the CC reg for the comparison in CMP. */ 3265 3266 rtx 3267 gen_compare_reg (rtx cmp) 3268 { 3269 return gen_compare_reg_1 (GET_CODE (cmp), XEXP (cmp, 0), XEXP (cmp, 1)); 3270 } 3271 3272 /* This function is used for v9 only. 3273 DEST is the target of the Scc insn. 3274 CODE is the code for an Scc's comparison. 3275 X and Y are the values we compare. 3276 3277 This function is needed to turn 3278 3279 (set (reg:SI 110) 3280 (gt (reg:CCX 100 %icc) 3281 (const_int 0))) 3282 into 3283 (set (reg:SI 110) 3284 (gt:DI (reg:CCX 100 %icc) 3285 (const_int 0))) 3286 3287 IE: The instruction recognizer needs to see the mode of the comparison to 3288 find the right instruction. We could use "gt:DI" right in the 3289 define_expand, but leaving it out allows us to handle DI, SI, etc. */ 3290 3291 static int 3292 gen_v9_scc (rtx dest, enum rtx_code compare_code, rtx x, rtx y) 3293 { 3294 if (! TARGET_ARCH64 3295 && (GET_MODE (x) == DImode 3296 || GET_MODE (dest) == DImode)) 3297 return 0; 3298 3299 /* Try to use the movrCC insns. */ 3300 if (TARGET_ARCH64 3301 && GET_MODE_CLASS (GET_MODE (x)) == MODE_INT 3302 && y == const0_rtx 3303 && v9_regcmp_p (compare_code)) 3304 { 3305 rtx op0 = x; 3306 rtx temp; 3307 3308 /* Special case for op0 != 0. This can be done with one instruction if 3309 dest == x. */ 3310 3311 if (compare_code == NE 3312 && GET_MODE (dest) == DImode 3313 && rtx_equal_p (op0, dest)) 3314 { 3315 emit_insn (gen_rtx_SET (dest, 3316 gen_rtx_IF_THEN_ELSE (DImode, 3317 gen_rtx_fmt_ee (compare_code, DImode, 3318 op0, const0_rtx), 3319 const1_rtx, 3320 dest))); 3321 return 1; 3322 } 3323 3324 if (reg_overlap_mentioned_p (dest, op0)) 3325 { 3326 /* Handle the case where dest == x. 3327 We "early clobber" the result. */ 3328 op0 = gen_reg_rtx (GET_MODE (x)); 3329 emit_move_insn (op0, x); 3330 } 3331 3332 emit_insn (gen_rtx_SET (dest, const0_rtx)); 3333 if (GET_MODE (op0) != DImode) 3334 { 3335 temp = gen_reg_rtx (DImode); 3336 convert_move (temp, op0, 0); 3337 } 3338 else 3339 temp = op0; 3340 emit_insn (gen_rtx_SET (dest, 3341 gen_rtx_IF_THEN_ELSE (GET_MODE (dest), 3342 gen_rtx_fmt_ee (compare_code, DImode, 3343 temp, const0_rtx), 3344 const1_rtx, 3345 dest))); 3346 return 1; 3347 } 3348 else 3349 { 3350 x = gen_compare_reg_1 (compare_code, x, y); 3351 y = const0_rtx; 3352 3353 emit_insn (gen_rtx_SET (dest, const0_rtx)); 3354 emit_insn (gen_rtx_SET (dest, 3355 gen_rtx_IF_THEN_ELSE (GET_MODE (dest), 3356 gen_rtx_fmt_ee (compare_code, 3357 GET_MODE (x), x, y), 3358 const1_rtx, dest))); 3359 return 1; 3360 } 3361 } 3362 3363 3364 /* Emit an scc insn. For seq, sne, sgeu, and sltu, we can do this 3365 without jumps using the addx/subx instructions. */ 3366 3367 bool 3368 emit_scc_insn (rtx operands[]) 3369 { 3370 rtx tem, x, y; 3371 enum rtx_code code; 3372 machine_mode mode; 3373 3374 /* The quad-word fp compare library routines all return nonzero to indicate 3375 true, which is different from the equivalent libgcc routines, so we must 3376 handle them specially here. */ 3377 if (GET_MODE (operands[2]) == TFmode && ! TARGET_HARD_QUAD) 3378 { 3379 operands[1] = sparc_emit_float_lib_cmp (operands[2], operands[3], 3380 GET_CODE (operands[1])); 3381 operands[2] = XEXP (operands[1], 0); 3382 operands[3] = XEXP (operands[1], 1); 3383 } 3384 3385 code = GET_CODE (operands[1]); 3386 x = operands[2]; 3387 y = operands[3]; 3388 mode = GET_MODE (x); 3389 3390 /* For seq/sne on v9 we use the same code as v8 (the addx/subx method has 3391 more applications). The exception to this is "reg != 0" which can 3392 be done in one instruction on v9 (so we do it). */ 3393 if ((code == EQ || code == NE) && (mode == SImode || mode == DImode)) 3394 { 3395 if (y != const0_rtx) 3396 x = force_reg (mode, gen_rtx_XOR (mode, x, y)); 3397 3398 rtx pat = gen_rtx_SET (operands[0], 3399 gen_rtx_fmt_ee (code, GET_MODE (operands[0]), 3400 x, const0_rtx)); 3401 3402 /* If we can use addx/subx or addxc, add a clobber for CC. */ 3403 if (mode == SImode || (code == NE && TARGET_VIS3)) 3404 { 3405 rtx clobber 3406 = gen_rtx_CLOBBER (VOIDmode, 3407 gen_rtx_REG (mode == SImode ? CCmode : CCXmode, 3408 SPARC_ICC_REG)); 3409 pat = gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clobber)); 3410 } 3411 3412 emit_insn (pat); 3413 return true; 3414 } 3415 3416 /* We can do LTU in DImode using the addxc instruction with VIS3. */ 3417 if (TARGET_ARCH64 3418 && mode == DImode 3419 && !((code == LTU || code == GTU) && TARGET_VIS3) 3420 && gen_v9_scc (operands[0], code, x, y)) 3421 return true; 3422 3423 /* We can do LTU and GEU using the addx/subx instructions too. And 3424 for GTU/LEU, if both operands are registers swap them and fall 3425 back to the easy case. */ 3426 if (code == GTU || code == LEU) 3427 { 3428 if ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG) 3429 && (GET_CODE (y) == REG || GET_CODE (y) == SUBREG)) 3430 { 3431 tem = x; 3432 x = y; 3433 y = tem; 3434 code = swap_condition (code); 3435 } 3436 } 3437 3438 if (code == LTU || code == GEU) 3439 { 3440 emit_insn (gen_rtx_SET (operands[0], 3441 gen_rtx_fmt_ee (code, GET_MODE (operands[0]), 3442 gen_compare_reg_1 (code, x, y), 3443 const0_rtx))); 3444 return true; 3445 } 3446 3447 /* All the posibilities to use addx/subx based sequences has been 3448 exhausted, try for a 3 instruction sequence using v9 conditional 3449 moves. */ 3450 if (TARGET_V9 && gen_v9_scc (operands[0], code, x, y)) 3451 return true; 3452 3453 /* Nope, do branches. */ 3454 return false; 3455 } 3456 3457 /* Emit a conditional jump insn for the v9 architecture using comparison code 3458 CODE and jump target LABEL. 3459 This function exists to take advantage of the v9 brxx insns. */ 3460 3461 static void 3462 emit_v9_brxx_insn (enum rtx_code code, rtx op0, rtx label) 3463 { 3464 emit_jump_insn (gen_rtx_SET (pc_rtx, 3465 gen_rtx_IF_THEN_ELSE (VOIDmode, 3466 gen_rtx_fmt_ee (code, GET_MODE (op0), 3467 op0, const0_rtx), 3468 gen_rtx_LABEL_REF (VOIDmode, label), 3469 pc_rtx))); 3470 } 3471 3472 /* Emit a conditional jump insn for the UA2011 architecture using 3473 comparison code CODE and jump target LABEL. This function exists 3474 to take advantage of the UA2011 Compare and Branch insns. */ 3475 3476 static void 3477 emit_cbcond_insn (enum rtx_code code, rtx op0, rtx op1, rtx label) 3478 { 3479 rtx if_then_else; 3480 3481 if_then_else = gen_rtx_IF_THEN_ELSE (VOIDmode, 3482 gen_rtx_fmt_ee(code, GET_MODE(op0), 3483 op0, op1), 3484 gen_rtx_LABEL_REF (VOIDmode, label), 3485 pc_rtx); 3486 3487 emit_jump_insn (gen_rtx_SET (pc_rtx, if_then_else)); 3488 } 3489 3490 void 3491 emit_conditional_branch_insn (rtx operands[]) 3492 { 3493 /* The quad-word fp compare library routines all return nonzero to indicate 3494 true, which is different from the equivalent libgcc routines, so we must 3495 handle them specially here. */ 3496 if (GET_MODE (operands[1]) == TFmode && ! TARGET_HARD_QUAD) 3497 { 3498 operands[0] = sparc_emit_float_lib_cmp (operands[1], operands[2], 3499 GET_CODE (operands[0])); 3500 operands[1] = XEXP (operands[0], 0); 3501 operands[2] = XEXP (operands[0], 1); 3502 } 3503 3504 /* If we can tell early on that the comparison is against a constant 3505 that won't fit in the 5-bit signed immediate field of a cbcond, 3506 use one of the other v9 conditional branch sequences. */ 3507 if (TARGET_CBCOND 3508 && GET_CODE (operands[1]) == REG 3509 && (GET_MODE (operands[1]) == SImode 3510 || (TARGET_ARCH64 && GET_MODE (operands[1]) == DImode)) 3511 && (GET_CODE (operands[2]) != CONST_INT 3512 || SPARC_SIMM5_P (INTVAL (operands[2])))) 3513 { 3514 emit_cbcond_insn (GET_CODE (operands[0]), operands[1], operands[2], operands[3]); 3515 return; 3516 } 3517 3518 if (TARGET_ARCH64 && operands[2] == const0_rtx 3519 && GET_CODE (operands[1]) == REG 3520 && GET_MODE (operands[1]) == DImode) 3521 { 3522 emit_v9_brxx_insn (GET_CODE (operands[0]), operands[1], operands[3]); 3523 return; 3524 } 3525 3526 operands[1] = gen_compare_reg (operands[0]); 3527 operands[2] = const0_rtx; 3528 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), VOIDmode, 3529 operands[1], operands[2]); 3530 emit_jump_insn (gen_cbranchcc4 (operands[0], operands[1], operands[2], 3531 operands[3])); 3532 } 3533 3534 3535 /* Generate a DFmode part of a hard TFmode register. 3536 REG is the TFmode hard register, LOW is 1 for the 3537 low 64bit of the register and 0 otherwise. 3538 */ 3539 rtx 3540 gen_df_reg (rtx reg, int low) 3541 { 3542 int regno = REGNO (reg); 3543 3544 if ((WORDS_BIG_ENDIAN == 0) ^ (low != 0)) 3545 regno += (TARGET_ARCH64 && SPARC_INT_REG_P (regno)) ? 1 : 2; 3546 return gen_rtx_REG (DFmode, regno); 3547 } 3548 3549 /* Generate a call to FUNC with OPERANDS. Operand 0 is the return value. 3550 Unlike normal calls, TFmode operands are passed by reference. It is 3551 assumed that no more than 3 operands are required. */ 3552 3553 static void 3554 emit_soft_tfmode_libcall (const char *func_name, int nargs, rtx *operands) 3555 { 3556 rtx ret_slot = NULL, arg[3], func_sym; 3557 int i; 3558 3559 /* We only expect to be called for conversions, unary, and binary ops. */ 3560 gcc_assert (nargs == 2 || nargs == 3); 3561 3562 for (i = 0; i < nargs; ++i) 3563 { 3564 rtx this_arg = operands[i]; 3565 rtx this_slot; 3566 3567 /* TFmode arguments and return values are passed by reference. */ 3568 if (GET_MODE (this_arg) == TFmode) 3569 { 3570 int force_stack_temp; 3571 3572 force_stack_temp = 0; 3573 if (TARGET_BUGGY_QP_LIB && i == 0) 3574 force_stack_temp = 1; 3575 3576 if (GET_CODE (this_arg) == MEM 3577 && ! force_stack_temp) 3578 { 3579 tree expr = MEM_EXPR (this_arg); 3580 if (expr) 3581 mark_addressable (expr); 3582 this_arg = XEXP (this_arg, 0); 3583 } 3584 else if (CONSTANT_P (this_arg) 3585 && ! force_stack_temp) 3586 { 3587 this_slot = force_const_mem (TFmode, this_arg); 3588 this_arg = XEXP (this_slot, 0); 3589 } 3590 else 3591 { 3592 this_slot = assign_stack_temp (TFmode, GET_MODE_SIZE (TFmode)); 3593 3594 /* Operand 0 is the return value. We'll copy it out later. */ 3595 if (i > 0) 3596 emit_move_insn (this_slot, this_arg); 3597 else 3598 ret_slot = this_slot; 3599 3600 this_arg = XEXP (this_slot, 0); 3601 } 3602 } 3603 3604 arg[i] = this_arg; 3605 } 3606 3607 func_sym = gen_rtx_SYMBOL_REF (Pmode, func_name); 3608 3609 if (GET_MODE (operands[0]) == TFmode) 3610 { 3611 if (nargs == 2) 3612 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 2, 3613 arg[0], GET_MODE (arg[0]), 3614 arg[1], GET_MODE (arg[1])); 3615 else 3616 emit_library_call (func_sym, LCT_NORMAL, VOIDmode, 3, 3617 arg[0], GET_MODE (arg[0]), 3618 arg[1], GET_MODE (arg[1]), 3619 arg[2], GET_MODE (arg[2])); 3620 3621 if (ret_slot) 3622 emit_move_insn (operands[0], ret_slot); 3623 } 3624 else 3625 { 3626 rtx ret; 3627 3628 gcc_assert (nargs == 2); 3629 3630 ret = emit_library_call_value (func_sym, operands[0], LCT_NORMAL, 3631 GET_MODE (operands[0]), 1, 3632 arg[1], GET_MODE (arg[1])); 3633 3634 if (ret != operands[0]) 3635 emit_move_insn (operands[0], ret); 3636 } 3637 } 3638 3639 /* Expand soft-float TFmode calls to sparc abi routines. */ 3640 3641 static void 3642 emit_soft_tfmode_binop (enum rtx_code code, rtx *operands) 3643 { 3644 const char *func; 3645 3646 switch (code) 3647 { 3648 case PLUS: 3649 func = "_Qp_add"; 3650 break; 3651 case MINUS: 3652 func = "_Qp_sub"; 3653 break; 3654 case MULT: 3655 func = "_Qp_mul"; 3656 break; 3657 case DIV: 3658 func = "_Qp_div"; 3659 break; 3660 default: 3661 gcc_unreachable (); 3662 } 3663 3664 emit_soft_tfmode_libcall (func, 3, operands); 3665 } 3666 3667 static void 3668 emit_soft_tfmode_unop (enum rtx_code code, rtx *operands) 3669 { 3670 const char *func; 3671 3672 gcc_assert (code == SQRT); 3673 func = "_Qp_sqrt"; 3674 3675 emit_soft_tfmode_libcall (func, 2, operands); 3676 } 3677 3678 static void 3679 emit_soft_tfmode_cvt (enum rtx_code code, rtx *operands) 3680 { 3681 const char *func; 3682 3683 switch (code) 3684 { 3685 case FLOAT_EXTEND: 3686 switch (GET_MODE (operands[1])) 3687 { 3688 case SFmode: 3689 func = "_Qp_stoq"; 3690 break; 3691 case DFmode: 3692 func = "_Qp_dtoq"; 3693 break; 3694 default: 3695 gcc_unreachable (); 3696 } 3697 break; 3698 3699 case FLOAT_TRUNCATE: 3700 switch (GET_MODE (operands[0])) 3701 { 3702 case SFmode: 3703 func = "_Qp_qtos"; 3704 break; 3705 case DFmode: 3706 func = "_Qp_qtod"; 3707 break; 3708 default: 3709 gcc_unreachable (); 3710 } 3711 break; 3712 3713 case FLOAT: 3714 switch (GET_MODE (operands[1])) 3715 { 3716 case SImode: 3717 func = "_Qp_itoq"; 3718 if (TARGET_ARCH64) 3719 operands[1] = gen_rtx_SIGN_EXTEND (DImode, operands[1]); 3720 break; 3721 case DImode: 3722 func = "_Qp_xtoq"; 3723 break; 3724 default: 3725 gcc_unreachable (); 3726 } 3727 break; 3728 3729 case UNSIGNED_FLOAT: 3730 switch (GET_MODE (operands[1])) 3731 { 3732 case SImode: 3733 func = "_Qp_uitoq"; 3734 if (TARGET_ARCH64) 3735 operands[1] = gen_rtx_ZERO_EXTEND (DImode, operands[1]); 3736 break; 3737 case DImode: 3738 func = "_Qp_uxtoq"; 3739 break; 3740 default: 3741 gcc_unreachable (); 3742 } 3743 break; 3744 3745 case FIX: 3746 switch (GET_MODE (operands[0])) 3747 { 3748 case SImode: 3749 func = "_Qp_qtoi"; 3750 break; 3751 case DImode: 3752 func = "_Qp_qtox"; 3753 break; 3754 default: 3755 gcc_unreachable (); 3756 } 3757 break; 3758 3759 case UNSIGNED_FIX: 3760 switch (GET_MODE (operands[0])) 3761 { 3762 case SImode: 3763 func = "_Qp_qtoui"; 3764 break; 3765 case DImode: 3766 func = "_Qp_qtoux"; 3767 break; 3768 default: 3769 gcc_unreachable (); 3770 } 3771 break; 3772 3773 default: 3774 gcc_unreachable (); 3775 } 3776 3777 emit_soft_tfmode_libcall (func, 2, operands); 3778 } 3779 3780 /* Expand a hard-float tfmode operation. All arguments must be in 3781 registers. */ 3782 3783 static void 3784 emit_hard_tfmode_operation (enum rtx_code code, rtx *operands) 3785 { 3786 rtx op, dest; 3787 3788 if (GET_RTX_CLASS (code) == RTX_UNARY) 3789 { 3790 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 3791 op = gen_rtx_fmt_e (code, GET_MODE (operands[0]), operands[1]); 3792 } 3793 else 3794 { 3795 operands[1] = force_reg (GET_MODE (operands[1]), operands[1]); 3796 operands[2] = force_reg (GET_MODE (operands[2]), operands[2]); 3797 op = gen_rtx_fmt_ee (code, GET_MODE (operands[0]), 3798 operands[1], operands[2]); 3799 } 3800 3801 if (register_operand (operands[0], VOIDmode)) 3802 dest = operands[0]; 3803 else 3804 dest = gen_reg_rtx (GET_MODE (operands[0])); 3805 3806 emit_insn (gen_rtx_SET (dest, op)); 3807 3808 if (dest != operands[0]) 3809 emit_move_insn (operands[0], dest); 3810 } 3811 3812 void 3813 emit_tfmode_binop (enum rtx_code code, rtx *operands) 3814 { 3815 if (TARGET_HARD_QUAD) 3816 emit_hard_tfmode_operation (code, operands); 3817 else 3818 emit_soft_tfmode_binop (code, operands); 3819 } 3820 3821 void 3822 emit_tfmode_unop (enum rtx_code code, rtx *operands) 3823 { 3824 if (TARGET_HARD_QUAD) 3825 emit_hard_tfmode_operation (code, operands); 3826 else 3827 emit_soft_tfmode_unop (code, operands); 3828 } 3829 3830 void 3831 emit_tfmode_cvt (enum rtx_code code, rtx *operands) 3832 { 3833 if (TARGET_HARD_QUAD) 3834 emit_hard_tfmode_operation (code, operands); 3835 else 3836 emit_soft_tfmode_cvt (code, operands); 3837 } 3838 3839 /* Return nonzero if a branch/jump/call instruction will be emitting 3840 nop into its delay slot. */ 3841 3842 int 3843 empty_delay_slot (rtx_insn *insn) 3844 { 3845 rtx seq; 3846 3847 /* If no previous instruction (should not happen), return true. */ 3848 if (PREV_INSN (insn) == NULL) 3849 return 1; 3850 3851 seq = NEXT_INSN (PREV_INSN (insn)); 3852 if (GET_CODE (PATTERN (seq)) == SEQUENCE) 3853 return 0; 3854 3855 return 1; 3856 } 3857 3858 /* Return nonzero if we should emit a nop after a cbcond instruction. 3859 The cbcond instruction does not have a delay slot, however there is 3860 a severe performance penalty if a control transfer appears right 3861 after a cbcond. Therefore we emit a nop when we detect this 3862 situation. */ 3863 3864 int 3865 emit_cbcond_nop (rtx_insn *insn) 3866 { 3867 rtx next = next_active_insn (insn); 3868 3869 if (!next) 3870 return 1; 3871 3872 if (NONJUMP_INSN_P (next) 3873 && GET_CODE (PATTERN (next)) == SEQUENCE) 3874 next = XVECEXP (PATTERN (next), 0, 0); 3875 else if (CALL_P (next) 3876 && GET_CODE (PATTERN (next)) == PARALLEL) 3877 { 3878 rtx delay = XVECEXP (PATTERN (next), 0, 1); 3879 3880 if (GET_CODE (delay) == RETURN) 3881 { 3882 /* It's a sibling call. Do not emit the nop if we're going 3883 to emit something other than the jump itself as the first 3884 instruction of the sibcall sequence. */ 3885 if (sparc_leaf_function_p || TARGET_FLAT) 3886 return 0; 3887 } 3888 } 3889 3890 if (NONJUMP_INSN_P (next)) 3891 return 0; 3892 3893 return 1; 3894 } 3895 3896 /* Return nonzero if TRIAL can go into the call delay slot. */ 3897 3898 int 3899 eligible_for_call_delay (rtx_insn *trial) 3900 { 3901 rtx pat; 3902 3903 if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE) 3904 return 0; 3905 3906 /* Binutils allows 3907 call __tls_get_addr, %tgd_call (foo) 3908 add %l7, %o0, %o0, %tgd_add (foo) 3909 while Sun as/ld does not. */ 3910 if (TARGET_GNU_TLS || !TARGET_TLS) 3911 return 1; 3912 3913 pat = PATTERN (trial); 3914 3915 /* We must reject tgd_add{32|64}, i.e. 3916 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSGD))) 3917 and tldm_add{32|64}, i.e. 3918 (set (reg) (plus (reg) (unspec [(reg) (symbol_ref)] UNSPEC_TLSLDM))) 3919 for Sun as/ld. */ 3920 if (GET_CODE (pat) == SET 3921 && GET_CODE (SET_SRC (pat)) == PLUS) 3922 { 3923 rtx unspec = XEXP (SET_SRC (pat), 1); 3924 3925 if (GET_CODE (unspec) == UNSPEC 3926 && (XINT (unspec, 1) == UNSPEC_TLSGD 3927 || XINT (unspec, 1) == UNSPEC_TLSLDM)) 3928 return 0; 3929 } 3930 3931 return 1; 3932 } 3933 3934 /* Return nonzero if TRIAL, an insn, can be combined with a 'restore' 3935 instruction. RETURN_P is true if the v9 variant 'return' is to be 3936 considered in the test too. 3937 3938 TRIAL must be a SET whose destination is a REG appropriate for the 3939 'restore' instruction or, if RETURN_P is true, for the 'return' 3940 instruction. */ 3941 3942 static int 3943 eligible_for_restore_insn (rtx trial, bool return_p) 3944 { 3945 rtx pat = PATTERN (trial); 3946 rtx src = SET_SRC (pat); 3947 bool src_is_freg = false; 3948 rtx src_reg; 3949 3950 /* Since we now can do moves between float and integer registers when 3951 VIS3 is enabled, we have to catch this case. We can allow such 3952 moves when doing a 'return' however. */ 3953 src_reg = src; 3954 if (GET_CODE (src_reg) == SUBREG) 3955 src_reg = SUBREG_REG (src_reg); 3956 if (GET_CODE (src_reg) == REG 3957 && SPARC_FP_REG_P (REGNO (src_reg))) 3958 src_is_freg = true; 3959 3960 /* The 'restore src,%g0,dest' pattern for word mode and below. */ 3961 if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 3962 && arith_operand (src, GET_MODE (src)) 3963 && ! src_is_freg) 3964 { 3965 if (TARGET_ARCH64) 3966 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 3967 else 3968 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (SImode); 3969 } 3970 3971 /* The 'restore src,%g0,dest' pattern for double-word mode. */ 3972 else if (GET_MODE_CLASS (GET_MODE (src)) != MODE_FLOAT 3973 && arith_double_operand (src, GET_MODE (src)) 3974 && ! src_is_freg) 3975 return GET_MODE_SIZE (GET_MODE (src)) <= GET_MODE_SIZE (DImode); 3976 3977 /* The 'restore src,%g0,dest' pattern for float if no FPU. */ 3978 else if (! TARGET_FPU && register_operand (src, SFmode)) 3979 return 1; 3980 3981 /* The 'restore src,%g0,dest' pattern for double if no FPU. */ 3982 else if (! TARGET_FPU && TARGET_ARCH64 && register_operand (src, DFmode)) 3983 return 1; 3984 3985 /* If we have the 'return' instruction, anything that does not use 3986 local or output registers and can go into a delay slot wins. */ 3987 else if (return_p && TARGET_V9 && !epilogue_renumber (&pat, 1)) 3988 return 1; 3989 3990 /* The 'restore src1,src2,dest' pattern for SImode. */ 3991 else if (GET_CODE (src) == PLUS 3992 && register_operand (XEXP (src, 0), SImode) 3993 && arith_operand (XEXP (src, 1), SImode)) 3994 return 1; 3995 3996 /* The 'restore src1,src2,dest' pattern for DImode. */ 3997 else if (GET_CODE (src) == PLUS 3998 && register_operand (XEXP (src, 0), DImode) 3999 && arith_double_operand (XEXP (src, 1), DImode)) 4000 return 1; 4001 4002 /* The 'restore src1,%lo(src2),dest' pattern. */ 4003 else if (GET_CODE (src) == LO_SUM 4004 && ! TARGET_CM_MEDMID 4005 && ((register_operand (XEXP (src, 0), SImode) 4006 && immediate_operand (XEXP (src, 1), SImode)) 4007 || (TARGET_ARCH64 4008 && register_operand (XEXP (src, 0), DImode) 4009 && immediate_operand (XEXP (src, 1), DImode)))) 4010 return 1; 4011 4012 /* The 'restore src,src,dest' pattern. */ 4013 else if (GET_CODE (src) == ASHIFT 4014 && (register_operand (XEXP (src, 0), SImode) 4015 || register_operand (XEXP (src, 0), DImode)) 4016 && XEXP (src, 1) == const1_rtx) 4017 return 1; 4018 4019 return 0; 4020 } 4021 4022 /* Return nonzero if TRIAL can go into the function return's delay slot. */ 4023 4024 int 4025 eligible_for_return_delay (rtx_insn *trial) 4026 { 4027 int regno; 4028 rtx pat; 4029 4030 /* If the function uses __builtin_eh_return, the eh_return machinery 4031 occupies the delay slot. */ 4032 if (crtl->calls_eh_return) 4033 return 0; 4034 4035 if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE) 4036 return 0; 4037 4038 /* In the case of a leaf or flat function, anything can go into the slot. */ 4039 if (sparc_leaf_function_p || TARGET_FLAT) 4040 return 1; 4041 4042 if (!NONJUMP_INSN_P (trial)) 4043 return 0; 4044 4045 pat = PATTERN (trial); 4046 if (GET_CODE (pat) == PARALLEL) 4047 { 4048 int i; 4049 4050 if (! TARGET_V9) 4051 return 0; 4052 for (i = XVECLEN (pat, 0) - 1; i >= 0; i--) 4053 { 4054 rtx expr = XVECEXP (pat, 0, i); 4055 if (GET_CODE (expr) != SET) 4056 return 0; 4057 if (GET_CODE (SET_DEST (expr)) != REG) 4058 return 0; 4059 regno = REGNO (SET_DEST (expr)); 4060 if (regno >= 8 && regno < 24) 4061 return 0; 4062 } 4063 return !epilogue_renumber (&pat, 1); 4064 } 4065 4066 if (GET_CODE (pat) != SET) 4067 return 0; 4068 4069 if (GET_CODE (SET_DEST (pat)) != REG) 4070 return 0; 4071 4072 regno = REGNO (SET_DEST (pat)); 4073 4074 /* Otherwise, only operations which can be done in tandem with 4075 a `restore' or `return' insn can go into the delay slot. */ 4076 if (regno >= 8 && regno < 24) 4077 return 0; 4078 4079 /* If this instruction sets up floating point register and we have a return 4080 instruction, it can probably go in. But restore will not work 4081 with FP_REGS. */ 4082 if (! SPARC_INT_REG_P (regno)) 4083 return TARGET_V9 && !epilogue_renumber (&pat, 1); 4084 4085 return eligible_for_restore_insn (trial, true); 4086 } 4087 4088 /* Return nonzero if TRIAL can go into the sibling call's delay slot. */ 4089 4090 int 4091 eligible_for_sibcall_delay (rtx_insn *trial) 4092 { 4093 rtx pat; 4094 4095 if (get_attr_in_branch_delay (trial) == IN_BRANCH_DELAY_FALSE) 4096 return 0; 4097 4098 if (!NONJUMP_INSN_P (trial)) 4099 return 0; 4100 4101 pat = PATTERN (trial); 4102 4103 if (sparc_leaf_function_p || TARGET_FLAT) 4104 { 4105 /* If the tail call is done using the call instruction, 4106 we have to restore %o7 in the delay slot. */ 4107 if (LEAF_SIBCALL_SLOT_RESERVED_P) 4108 return 0; 4109 4110 /* %g1 is used to build the function address */ 4111 if (reg_mentioned_p (gen_rtx_REG (Pmode, 1), pat)) 4112 return 0; 4113 4114 return 1; 4115 } 4116 4117 if (GET_CODE (pat) != SET) 4118 return 0; 4119 4120 /* Otherwise, only operations which can be done in tandem with 4121 a `restore' insn can go into the delay slot. */ 4122 if (GET_CODE (SET_DEST (pat)) != REG 4123 || (REGNO (SET_DEST (pat)) >= 8 && REGNO (SET_DEST (pat)) < 24) 4124 || ! SPARC_INT_REG_P (REGNO (SET_DEST (pat)))) 4125 return 0; 4126 4127 /* If it mentions %o7, it can't go in, because sibcall will clobber it 4128 in most cases. */ 4129 if (reg_mentioned_p (gen_rtx_REG (Pmode, 15), pat)) 4130 return 0; 4131 4132 return eligible_for_restore_insn (trial, false); 4133 } 4134 4135 /* Determine if it's legal to put X into the constant pool. This 4136 is not possible if X contains the address of a symbol that is 4137 not constant (TLS) or not known at final link time (PIC). */ 4138 4139 static bool 4140 sparc_cannot_force_const_mem (machine_mode mode, rtx x) 4141 { 4142 switch (GET_CODE (x)) 4143 { 4144 case CONST_INT: 4145 case CONST_WIDE_INT: 4146 case CONST_DOUBLE: 4147 case CONST_VECTOR: 4148 /* Accept all non-symbolic constants. */ 4149 return false; 4150 4151 case LABEL_REF: 4152 /* Labels are OK iff we are non-PIC. */ 4153 return flag_pic != 0; 4154 4155 case SYMBOL_REF: 4156 /* 'Naked' TLS symbol references are never OK, 4157 non-TLS symbols are OK iff we are non-PIC. */ 4158 if (SYMBOL_REF_TLS_MODEL (x)) 4159 return true; 4160 else 4161 return flag_pic != 0; 4162 4163 case CONST: 4164 return sparc_cannot_force_const_mem (mode, XEXP (x, 0)); 4165 case PLUS: 4166 case MINUS: 4167 return sparc_cannot_force_const_mem (mode, XEXP (x, 0)) 4168 || sparc_cannot_force_const_mem (mode, XEXP (x, 1)); 4169 case UNSPEC: 4170 return true; 4171 default: 4172 gcc_unreachable (); 4173 } 4174 } 4175 4176 /* Global Offset Table support. */ 4177 static GTY(()) rtx got_helper_rtx = NULL_RTX; 4178 static GTY(()) rtx global_offset_table_rtx = NULL_RTX; 4179 4180 /* Return the SYMBOL_REF for the Global Offset Table. */ 4181 4182 static GTY(()) rtx sparc_got_symbol = NULL_RTX; 4183 4184 static rtx 4185 sparc_got (void) 4186 { 4187 if (!sparc_got_symbol) 4188 sparc_got_symbol = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 4189 4190 return sparc_got_symbol; 4191 } 4192 4193 /* Ensure that we are not using patterns that are not OK with PIC. */ 4194 4195 int 4196 check_pic (int i) 4197 { 4198 rtx op; 4199 4200 switch (flag_pic) 4201 { 4202 case 1: 4203 op = recog_data.operand[i]; 4204 gcc_assert (GET_CODE (op) != SYMBOL_REF 4205 && (GET_CODE (op) != CONST 4206 || (GET_CODE (XEXP (op, 0)) == MINUS 4207 && XEXP (XEXP (op, 0), 0) == sparc_got () 4208 && GET_CODE (XEXP (XEXP (op, 0), 1)) == CONST))); 4209 /* fallthrough */ 4210 case 2: 4211 default: 4212 return 1; 4213 } 4214 } 4215 4216 /* Return true if X is an address which needs a temporary register when 4217 reloaded while generating PIC code. */ 4218 4219 int 4220 pic_address_needs_scratch (rtx x) 4221 { 4222 /* An address which is a symbolic plus a non SMALL_INT needs a temp reg. */ 4223 if (GET_CODE (x) == CONST 4224 && GET_CODE (XEXP (x, 0)) == PLUS 4225 && GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 4226 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 4227 && !SMALL_INT (XEXP (XEXP (x, 0), 1))) 4228 return 1; 4229 4230 return 0; 4231 } 4232 4233 /* Determine if a given RTX is a valid constant. We already know this 4234 satisfies CONSTANT_P. */ 4235 4236 static bool 4237 sparc_legitimate_constant_p (machine_mode mode, rtx x) 4238 { 4239 switch (GET_CODE (x)) 4240 { 4241 case CONST: 4242 case SYMBOL_REF: 4243 if (sparc_tls_referenced_p (x)) 4244 return false; 4245 break; 4246 4247 case CONST_DOUBLE: 4248 /* Floating point constants are generally not ok. 4249 The only exception is 0.0 and all-ones in VIS. */ 4250 if (TARGET_VIS 4251 && SCALAR_FLOAT_MODE_P (mode) 4252 && (const_zero_operand (x, mode) 4253 || const_all_ones_operand (x, mode))) 4254 return true; 4255 4256 return false; 4257 4258 case CONST_VECTOR: 4259 /* Vector constants are generally not ok. 4260 The only exception is 0 or -1 in VIS. */ 4261 if (TARGET_VIS 4262 && (const_zero_operand (x, mode) 4263 || const_all_ones_operand (x, mode))) 4264 return true; 4265 4266 return false; 4267 4268 default: 4269 break; 4270 } 4271 4272 return true; 4273 } 4274 4275 /* Determine if a given RTX is a valid constant address. */ 4276 4277 bool 4278 constant_address_p (rtx x) 4279 { 4280 switch (GET_CODE (x)) 4281 { 4282 case LABEL_REF: 4283 case CONST_INT: 4284 case HIGH: 4285 return true; 4286 4287 case CONST: 4288 if (flag_pic && pic_address_needs_scratch (x)) 4289 return false; 4290 return sparc_legitimate_constant_p (Pmode, x); 4291 4292 case SYMBOL_REF: 4293 return !flag_pic && sparc_legitimate_constant_p (Pmode, x); 4294 4295 default: 4296 return false; 4297 } 4298 } 4299 4300 /* Nonzero if the constant value X is a legitimate general operand 4301 when generating PIC code. It is given that flag_pic is on and 4302 that X satisfies CONSTANT_P. */ 4303 4304 bool 4305 legitimate_pic_operand_p (rtx x) 4306 { 4307 if (pic_address_needs_scratch (x)) 4308 return false; 4309 if (sparc_tls_referenced_p (x)) 4310 return false; 4311 return true; 4312 } 4313 4314 #define RTX_OK_FOR_OFFSET_P(X, MODE) \ 4315 (CONST_INT_P (X) \ 4316 && INTVAL (X) >= -0x1000 \ 4317 && INTVAL (X) <= (0x1000 - GET_MODE_SIZE (MODE))) 4318 4319 #define RTX_OK_FOR_OLO10_P(X, MODE) \ 4320 (CONST_INT_P (X) \ 4321 && INTVAL (X) >= -0x1000 \ 4322 && INTVAL (X) <= (0xc00 - GET_MODE_SIZE (MODE))) 4323 4324 /* Handle the TARGET_LEGITIMATE_ADDRESS_P target hook. 4325 4326 On SPARC, the actual legitimate addresses must be REG+REG or REG+SMALLINT 4327 ordinarily. This changes a bit when generating PIC. */ 4328 4329 static bool 4330 sparc_legitimate_address_p (machine_mode mode, rtx addr, bool strict) 4331 { 4332 rtx rs1 = NULL, rs2 = NULL, imm1 = NULL; 4333 4334 if (REG_P (addr) || GET_CODE (addr) == SUBREG) 4335 rs1 = addr; 4336 else if (GET_CODE (addr) == PLUS) 4337 { 4338 rs1 = XEXP (addr, 0); 4339 rs2 = XEXP (addr, 1); 4340 4341 /* Canonicalize. REG comes first, if there are no regs, 4342 LO_SUM comes first. */ 4343 if (!REG_P (rs1) 4344 && GET_CODE (rs1) != SUBREG 4345 && (REG_P (rs2) 4346 || GET_CODE (rs2) == SUBREG 4347 || (GET_CODE (rs2) == LO_SUM && GET_CODE (rs1) != LO_SUM))) 4348 { 4349 rs1 = XEXP (addr, 1); 4350 rs2 = XEXP (addr, 0); 4351 } 4352 4353 if ((flag_pic == 1 4354 && rs1 == pic_offset_table_rtx 4355 && !REG_P (rs2) 4356 && GET_CODE (rs2) != SUBREG 4357 && GET_CODE (rs2) != LO_SUM 4358 && GET_CODE (rs2) != MEM 4359 && !(GET_CODE (rs2) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs2)) 4360 && (! symbolic_operand (rs2, VOIDmode) || mode == Pmode) 4361 && (GET_CODE (rs2) != CONST_INT || SMALL_INT (rs2))) 4362 || ((REG_P (rs1) 4363 || GET_CODE (rs1) == SUBREG) 4364 && RTX_OK_FOR_OFFSET_P (rs2, mode))) 4365 { 4366 imm1 = rs2; 4367 rs2 = NULL; 4368 } 4369 else if ((REG_P (rs1) || GET_CODE (rs1) == SUBREG) 4370 && (REG_P (rs2) || GET_CODE (rs2) == SUBREG)) 4371 { 4372 /* We prohibit REG + REG for TFmode when there are no quad move insns 4373 and we consequently need to split. We do this because REG+REG 4374 is not an offsettable address. If we get the situation in reload 4375 where source and destination of a movtf pattern are both MEMs with 4376 REG+REG address, then only one of them gets converted to an 4377 offsettable address. */ 4378 if (mode == TFmode 4379 && ! (TARGET_ARCH64 && TARGET_HARD_QUAD)) 4380 return 0; 4381 4382 /* Likewise for TImode, but in all cases. */ 4383 if (mode == TImode) 4384 return 0; 4385 4386 /* We prohibit REG + REG on ARCH32 if not optimizing for 4387 DFmode/DImode because then mem_min_alignment is likely to be zero 4388 after reload and the forced split would lack a matching splitter 4389 pattern. */ 4390 if (TARGET_ARCH32 && !optimize 4391 && (mode == DFmode || mode == DImode)) 4392 return 0; 4393 } 4394 else if (USE_AS_OFFSETABLE_LO10 4395 && GET_CODE (rs1) == LO_SUM 4396 && TARGET_ARCH64 4397 && ! TARGET_CM_MEDMID 4398 && RTX_OK_FOR_OLO10_P (rs2, mode)) 4399 { 4400 rs2 = NULL; 4401 imm1 = XEXP (rs1, 1); 4402 rs1 = XEXP (rs1, 0); 4403 if (!CONSTANT_P (imm1) 4404 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1))) 4405 return 0; 4406 } 4407 } 4408 else if (GET_CODE (addr) == LO_SUM) 4409 { 4410 rs1 = XEXP (addr, 0); 4411 imm1 = XEXP (addr, 1); 4412 4413 if (!CONSTANT_P (imm1) 4414 || (GET_CODE (rs1) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (rs1))) 4415 return 0; 4416 4417 /* We can't allow TFmode in 32-bit mode, because an offset greater 4418 than the alignment (8) may cause the LO_SUM to overflow. */ 4419 if (mode == TFmode && TARGET_ARCH32) 4420 return 0; 4421 4422 /* During reload, accept the HIGH+LO_SUM construct generated by 4423 sparc_legitimize_reload_address. */ 4424 if (reload_in_progress 4425 && GET_CODE (rs1) == HIGH 4426 && XEXP (rs1, 0) == imm1) 4427 return 1; 4428 } 4429 else if (GET_CODE (addr) == CONST_INT && SMALL_INT (addr)) 4430 return 1; 4431 else 4432 return 0; 4433 4434 if (GET_CODE (rs1) == SUBREG) 4435 rs1 = SUBREG_REG (rs1); 4436 if (!REG_P (rs1)) 4437 return 0; 4438 4439 if (rs2) 4440 { 4441 if (GET_CODE (rs2) == SUBREG) 4442 rs2 = SUBREG_REG (rs2); 4443 if (!REG_P (rs2)) 4444 return 0; 4445 } 4446 4447 if (strict) 4448 { 4449 if (!REGNO_OK_FOR_BASE_P (REGNO (rs1)) 4450 || (rs2 && !REGNO_OK_FOR_BASE_P (REGNO (rs2)))) 4451 return 0; 4452 } 4453 else 4454 { 4455 if ((! SPARC_INT_REG_P (REGNO (rs1)) 4456 && REGNO (rs1) != FRAME_POINTER_REGNUM 4457 && REGNO (rs1) < FIRST_PSEUDO_REGISTER) 4458 || (rs2 4459 && (! SPARC_INT_REG_P (REGNO (rs2)) 4460 && REGNO (rs2) != FRAME_POINTER_REGNUM 4461 && REGNO (rs2) < FIRST_PSEUDO_REGISTER))) 4462 return 0; 4463 } 4464 return 1; 4465 } 4466 4467 /* Return the SYMBOL_REF for the tls_get_addr function. */ 4468 4469 static GTY(()) rtx sparc_tls_symbol = NULL_RTX; 4470 4471 static rtx 4472 sparc_tls_get_addr (void) 4473 { 4474 if (!sparc_tls_symbol) 4475 sparc_tls_symbol = gen_rtx_SYMBOL_REF (Pmode, "__tls_get_addr"); 4476 4477 return sparc_tls_symbol; 4478 } 4479 4480 /* Return the Global Offset Table to be used in TLS mode. */ 4481 4482 static rtx 4483 sparc_tls_got (void) 4484 { 4485 /* In PIC mode, this is just the PIC offset table. */ 4486 if (flag_pic) 4487 { 4488 crtl->uses_pic_offset_table = 1; 4489 return pic_offset_table_rtx; 4490 } 4491 4492 /* In non-PIC mode, Sun as (unlike GNU as) emits PC-relative relocations for 4493 the GOT symbol with the 32-bit ABI, so we reload the GOT register. */ 4494 if (TARGET_SUN_TLS && TARGET_ARCH32) 4495 { 4496 load_got_register (); 4497 return global_offset_table_rtx; 4498 } 4499 4500 /* In all other cases, we load a new pseudo with the GOT symbol. */ 4501 return copy_to_reg (sparc_got ()); 4502 } 4503 4504 /* Return true if X contains a thread-local symbol. */ 4505 4506 static bool 4507 sparc_tls_referenced_p (rtx x) 4508 { 4509 if (!TARGET_HAVE_TLS) 4510 return false; 4511 4512 if (GET_CODE (x) == CONST && GET_CODE (XEXP (x, 0)) == PLUS) 4513 x = XEXP (XEXP (x, 0), 0); 4514 4515 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x)) 4516 return true; 4517 4518 /* That's all we handle in sparc_legitimize_tls_address for now. */ 4519 return false; 4520 } 4521 4522 /* ADDR contains a thread-local SYMBOL_REF. Generate code to compute 4523 this (thread-local) address. */ 4524 4525 static rtx 4526 sparc_legitimize_tls_address (rtx addr) 4527 { 4528 rtx temp1, temp2, temp3, ret, o0, got; 4529 rtx_insn *insn; 4530 4531 gcc_assert (can_create_pseudo_p ()); 4532 4533 if (GET_CODE (addr) == SYMBOL_REF) 4534 switch (SYMBOL_REF_TLS_MODEL (addr)) 4535 { 4536 case TLS_MODEL_GLOBAL_DYNAMIC: 4537 start_sequence (); 4538 temp1 = gen_reg_rtx (SImode); 4539 temp2 = gen_reg_rtx (SImode); 4540 ret = gen_reg_rtx (Pmode); 4541 o0 = gen_rtx_REG (Pmode, 8); 4542 got = sparc_tls_got (); 4543 emit_insn (gen_tgd_hi22 (temp1, addr)); 4544 emit_insn (gen_tgd_lo10 (temp2, temp1, addr)); 4545 if (TARGET_ARCH32) 4546 { 4547 emit_insn (gen_tgd_add32 (o0, got, temp2, addr)); 4548 insn = emit_call_insn (gen_tgd_call32 (o0, sparc_tls_get_addr (), 4549 addr, const1_rtx)); 4550 } 4551 else 4552 { 4553 emit_insn (gen_tgd_add64 (o0, got, temp2, addr)); 4554 insn = emit_call_insn (gen_tgd_call64 (o0, sparc_tls_get_addr (), 4555 addr, const1_rtx)); 4556 } 4557 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0); 4558 insn = get_insns (); 4559 end_sequence (); 4560 emit_libcall_block (insn, ret, o0, addr); 4561 break; 4562 4563 case TLS_MODEL_LOCAL_DYNAMIC: 4564 start_sequence (); 4565 temp1 = gen_reg_rtx (SImode); 4566 temp2 = gen_reg_rtx (SImode); 4567 temp3 = gen_reg_rtx (Pmode); 4568 ret = gen_reg_rtx (Pmode); 4569 o0 = gen_rtx_REG (Pmode, 8); 4570 got = sparc_tls_got (); 4571 emit_insn (gen_tldm_hi22 (temp1)); 4572 emit_insn (gen_tldm_lo10 (temp2, temp1)); 4573 if (TARGET_ARCH32) 4574 { 4575 emit_insn (gen_tldm_add32 (o0, got, temp2)); 4576 insn = emit_call_insn (gen_tldm_call32 (o0, sparc_tls_get_addr (), 4577 const1_rtx)); 4578 } 4579 else 4580 { 4581 emit_insn (gen_tldm_add64 (o0, got, temp2)); 4582 insn = emit_call_insn (gen_tldm_call64 (o0, sparc_tls_get_addr (), 4583 const1_rtx)); 4584 } 4585 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), o0); 4586 insn = get_insns (); 4587 end_sequence (); 4588 emit_libcall_block (insn, temp3, o0, 4589 gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), 4590 UNSPEC_TLSLD_BASE)); 4591 temp1 = gen_reg_rtx (SImode); 4592 temp2 = gen_reg_rtx (SImode); 4593 emit_insn (gen_tldo_hix22 (temp1, addr)); 4594 emit_insn (gen_tldo_lox10 (temp2, temp1, addr)); 4595 if (TARGET_ARCH32) 4596 emit_insn (gen_tldo_add32 (ret, temp3, temp2, addr)); 4597 else 4598 emit_insn (gen_tldo_add64 (ret, temp3, temp2, addr)); 4599 break; 4600 4601 case TLS_MODEL_INITIAL_EXEC: 4602 temp1 = gen_reg_rtx (SImode); 4603 temp2 = gen_reg_rtx (SImode); 4604 temp3 = gen_reg_rtx (Pmode); 4605 got = sparc_tls_got (); 4606 emit_insn (gen_tie_hi22 (temp1, addr)); 4607 emit_insn (gen_tie_lo10 (temp2, temp1, addr)); 4608 if (TARGET_ARCH32) 4609 emit_insn (gen_tie_ld32 (temp3, got, temp2, addr)); 4610 else 4611 emit_insn (gen_tie_ld64 (temp3, got, temp2, addr)); 4612 if (TARGET_SUN_TLS) 4613 { 4614 ret = gen_reg_rtx (Pmode); 4615 if (TARGET_ARCH32) 4616 emit_insn (gen_tie_add32 (ret, gen_rtx_REG (Pmode, 7), 4617 temp3, addr)); 4618 else 4619 emit_insn (gen_tie_add64 (ret, gen_rtx_REG (Pmode, 7), 4620 temp3, addr)); 4621 } 4622 else 4623 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp3); 4624 break; 4625 4626 case TLS_MODEL_LOCAL_EXEC: 4627 temp1 = gen_reg_rtx (Pmode); 4628 temp2 = gen_reg_rtx (Pmode); 4629 if (TARGET_ARCH32) 4630 { 4631 emit_insn (gen_tle_hix22_sp32 (temp1, addr)); 4632 emit_insn (gen_tle_lox10_sp32 (temp2, temp1, addr)); 4633 } 4634 else 4635 { 4636 emit_insn (gen_tle_hix22_sp64 (temp1, addr)); 4637 emit_insn (gen_tle_lox10_sp64 (temp2, temp1, addr)); 4638 } 4639 ret = gen_rtx_PLUS (Pmode, gen_rtx_REG (Pmode, 7), temp2); 4640 break; 4641 4642 default: 4643 gcc_unreachable (); 4644 } 4645 4646 else if (GET_CODE (addr) == CONST) 4647 { 4648 rtx base, offset; 4649 4650 gcc_assert (GET_CODE (XEXP (addr, 0)) == PLUS); 4651 4652 base = sparc_legitimize_tls_address (XEXP (XEXP (addr, 0), 0)); 4653 offset = XEXP (XEXP (addr, 0), 1); 4654 4655 base = force_operand (base, NULL_RTX); 4656 if (!(GET_CODE (offset) == CONST_INT && SMALL_INT (offset))) 4657 offset = force_reg (Pmode, offset); 4658 ret = gen_rtx_PLUS (Pmode, base, offset); 4659 } 4660 4661 else 4662 gcc_unreachable (); /* for now ... */ 4663 4664 return ret; 4665 } 4666 4667 /* Legitimize PIC addresses. If the address is already position-independent, 4668 we return ORIG. Newly generated position-independent addresses go into a 4669 reg. This is REG if nonzero, otherwise we allocate register(s) as 4670 necessary. */ 4671 4672 static rtx 4673 sparc_legitimize_pic_address (rtx orig, rtx reg) 4674 { 4675 if (GET_CODE (orig) == SYMBOL_REF 4676 /* See the comment in sparc_expand_move. */ 4677 || (GET_CODE (orig) == LABEL_REF && !can_use_mov_pic_label_ref (orig))) 4678 { 4679 bool gotdata_op = false; 4680 rtx pic_ref, address; 4681 rtx_insn *insn; 4682 4683 if (!reg) 4684 { 4685 gcc_assert (can_create_pseudo_p ()); 4686 reg = gen_reg_rtx (Pmode); 4687 } 4688 4689 if (flag_pic == 2) 4690 { 4691 /* If not during reload, allocate another temp reg here for loading 4692 in the address, so that these instructions can be optimized 4693 properly. */ 4694 rtx temp_reg = can_create_pseudo_p () ? gen_reg_rtx (Pmode) : reg; 4695 4696 /* Must put the SYMBOL_REF inside an UNSPEC here so that cse 4697 won't get confused into thinking that these two instructions 4698 are loading in the true address of the symbol. If in the 4699 future a PIC rtx exists, that should be used instead. */ 4700 if (TARGET_ARCH64) 4701 { 4702 emit_insn (gen_movdi_high_pic (temp_reg, orig)); 4703 emit_insn (gen_movdi_lo_sum_pic (temp_reg, temp_reg, orig)); 4704 } 4705 else 4706 { 4707 emit_insn (gen_movsi_high_pic (temp_reg, orig)); 4708 emit_insn (gen_movsi_lo_sum_pic (temp_reg, temp_reg, orig)); 4709 } 4710 4711 address = temp_reg; 4712 gotdata_op = true; 4713 } 4714 else 4715 address = orig; 4716 4717 crtl->uses_pic_offset_table = 1; 4718 if (gotdata_op) 4719 { 4720 if (TARGET_ARCH64) 4721 insn = emit_insn (gen_movdi_pic_gotdata_op (reg, 4722 pic_offset_table_rtx, 4723 address, orig)); 4724 else 4725 insn = emit_insn (gen_movsi_pic_gotdata_op (reg, 4726 pic_offset_table_rtx, 4727 address, orig)); 4728 } 4729 else 4730 { 4731 pic_ref 4732 = gen_const_mem (Pmode, 4733 gen_rtx_PLUS (Pmode, 4734 pic_offset_table_rtx, address)); 4735 insn = emit_move_insn (reg, pic_ref); 4736 } 4737 4738 /* Put a REG_EQUAL note on this insn, so that it can be optimized 4739 by loop. */ 4740 set_unique_reg_note (insn, REG_EQUAL, orig); 4741 return reg; 4742 } 4743 else if (GET_CODE (orig) == CONST) 4744 { 4745 rtx base, offset; 4746 4747 if (GET_CODE (XEXP (orig, 0)) == PLUS 4748 && XEXP (XEXP (orig, 0), 0) == pic_offset_table_rtx) 4749 return orig; 4750 4751 if (!reg) 4752 { 4753 gcc_assert (can_create_pseudo_p ()); 4754 reg = gen_reg_rtx (Pmode); 4755 } 4756 4757 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); 4758 base = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg); 4759 offset = sparc_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), 4760 base == reg ? NULL_RTX : reg); 4761 4762 if (GET_CODE (offset) == CONST_INT) 4763 { 4764 if (SMALL_INT (offset)) 4765 return plus_constant (Pmode, base, INTVAL (offset)); 4766 else if (can_create_pseudo_p ()) 4767 offset = force_reg (Pmode, offset); 4768 else 4769 /* If we reach here, then something is seriously wrong. */ 4770 gcc_unreachable (); 4771 } 4772 return gen_rtx_PLUS (Pmode, base, offset); 4773 } 4774 else if (GET_CODE (orig) == LABEL_REF) 4775 /* ??? We ought to be checking that the register is live instead, in case 4776 it is eliminated. */ 4777 crtl->uses_pic_offset_table = 1; 4778 4779 return orig; 4780 } 4781 4782 /* Try machine-dependent ways of modifying an illegitimate address X 4783 to be legitimate. If we find one, return the new, valid address. 4784 4785 OLDX is the address as it was before break_out_memory_refs was called. 4786 In some cases it is useful to look at this to decide what needs to be done. 4787 4788 MODE is the mode of the operand pointed to by X. 4789 4790 On SPARC, change REG+N into REG+REG, and REG+(X*Y) into REG+REG. */ 4791 4792 static rtx 4793 sparc_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, 4794 machine_mode mode) 4795 { 4796 rtx orig_x = x; 4797 4798 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == MULT) 4799 x = gen_rtx_PLUS (Pmode, XEXP (x, 1), 4800 force_operand (XEXP (x, 0), NULL_RTX)); 4801 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == MULT) 4802 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 4803 force_operand (XEXP (x, 1), NULL_RTX)); 4804 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 0)) == PLUS) 4805 x = gen_rtx_PLUS (Pmode, force_operand (XEXP (x, 0), NULL_RTX), 4806 XEXP (x, 1)); 4807 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == PLUS) 4808 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 4809 force_operand (XEXP (x, 1), NULL_RTX)); 4810 4811 if (x != orig_x && sparc_legitimate_address_p (mode, x, FALSE)) 4812 return x; 4813 4814 if (sparc_tls_referenced_p (x)) 4815 x = sparc_legitimize_tls_address (x); 4816 else if (flag_pic) 4817 x = sparc_legitimize_pic_address (x, NULL_RTX); 4818 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 1))) 4819 x = gen_rtx_PLUS (Pmode, XEXP (x, 0), 4820 copy_to_mode_reg (Pmode, XEXP (x, 1))); 4821 else if (GET_CODE (x) == PLUS && CONSTANT_ADDRESS_P (XEXP (x, 0))) 4822 x = gen_rtx_PLUS (Pmode, XEXP (x, 1), 4823 copy_to_mode_reg (Pmode, XEXP (x, 0))); 4824 else if (GET_CODE (x) == SYMBOL_REF 4825 || GET_CODE (x) == CONST 4826 || GET_CODE (x) == LABEL_REF) 4827 x = copy_to_suggested_reg (x, NULL_RTX, Pmode); 4828 4829 return x; 4830 } 4831 4832 /* Delegitimize an address that was legitimized by the above function. */ 4833 4834 static rtx 4835 sparc_delegitimize_address (rtx x) 4836 { 4837 x = delegitimize_mem_from_attrs (x); 4838 4839 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 1)) == UNSPEC) 4840 switch (XINT (XEXP (x, 1), 1)) 4841 { 4842 case UNSPEC_MOVE_PIC: 4843 case UNSPEC_TLSLE: 4844 x = XVECEXP (XEXP (x, 1), 0, 0); 4845 gcc_assert (GET_CODE (x) == SYMBOL_REF); 4846 break; 4847 default: 4848 break; 4849 } 4850 4851 /* This is generated by mov{si,di}_pic_label_ref in PIC mode. */ 4852 if (GET_CODE (x) == MINUS 4853 && REG_P (XEXP (x, 0)) 4854 && REGNO (XEXP (x, 0)) == PIC_OFFSET_TABLE_REGNUM 4855 && GET_CODE (XEXP (x, 1)) == LO_SUM 4856 && GET_CODE (XEXP (XEXP (x, 1), 1)) == UNSPEC 4857 && XINT (XEXP (XEXP (x, 1), 1), 1) == UNSPEC_MOVE_PIC_LABEL) 4858 { 4859 x = XVECEXP (XEXP (XEXP (x, 1), 1), 0, 0); 4860 gcc_assert (GET_CODE (x) == LABEL_REF 4861 || (GET_CODE (x) == CONST 4862 && GET_CODE (XEXP (x, 0)) == PLUS 4863 && GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF 4864 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT)); 4865 } 4866 4867 return x; 4868 } 4869 4870 /* SPARC implementation of LEGITIMIZE_RELOAD_ADDRESS. Returns a value to 4871 replace the input X, or the original X if no replacement is called for. 4872 The output parameter *WIN is 1 if the calling macro should goto WIN, 4873 0 if it should not. 4874 4875 For SPARC, we wish to handle addresses by splitting them into 4876 HIGH+LO_SUM pairs, retaining the LO_SUM in the memory reference. 4877 This cuts the number of extra insns by one. 4878 4879 Do nothing when generating PIC code and the address is a symbolic 4880 operand or requires a scratch register. */ 4881 4882 rtx 4883 sparc_legitimize_reload_address (rtx x, machine_mode mode, 4884 int opnum, int type, 4885 int ind_levels ATTRIBUTE_UNUSED, int *win) 4886 { 4887 /* Decompose SImode constants into HIGH+LO_SUM. */ 4888 if (CONSTANT_P (x) 4889 && (mode != TFmode || TARGET_ARCH64) 4890 && GET_MODE (x) == SImode 4891 && GET_CODE (x) != LO_SUM 4892 && GET_CODE (x) != HIGH 4893 && sparc_cmodel <= CM_MEDLOW 4894 && !(flag_pic 4895 && (symbolic_operand (x, Pmode) || pic_address_needs_scratch (x)))) 4896 { 4897 x = gen_rtx_LO_SUM (GET_MODE (x), gen_rtx_HIGH (GET_MODE (x), x), x); 4898 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, 4899 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, 4900 opnum, (enum reload_type)type); 4901 *win = 1; 4902 return x; 4903 } 4904 4905 /* We have to recognize what we have already generated above. */ 4906 if (GET_CODE (x) == LO_SUM && GET_CODE (XEXP (x, 0)) == HIGH) 4907 { 4908 push_reload (XEXP (x, 0), NULL_RTX, &XEXP (x, 0), NULL, 4909 BASE_REG_CLASS, GET_MODE (x), VOIDmode, 0, 0, 4910 opnum, (enum reload_type)type); 4911 *win = 1; 4912 return x; 4913 } 4914 4915 *win = 0; 4916 return x; 4917 } 4918 4919 /* Return true if ADDR (a legitimate address expression) 4920 has an effect that depends on the machine mode it is used for. 4921 4922 In PIC mode, 4923 4924 (mem:HI [%l7+a]) 4925 4926 is not equivalent to 4927 4928 (mem:QI [%l7+a]) (mem:QI [%l7+a+1]) 4929 4930 because [%l7+a+1] is interpreted as the address of (a+1). */ 4931 4932 4933 static bool 4934 sparc_mode_dependent_address_p (const_rtx addr, 4935 addr_space_t as ATTRIBUTE_UNUSED) 4936 { 4937 if (flag_pic && GET_CODE (addr) == PLUS) 4938 { 4939 rtx op0 = XEXP (addr, 0); 4940 rtx op1 = XEXP (addr, 1); 4941 if (op0 == pic_offset_table_rtx 4942 && symbolic_operand (op1, VOIDmode)) 4943 return true; 4944 } 4945 4946 return false; 4947 } 4948 4949 #ifdef HAVE_GAS_HIDDEN 4950 # define USE_HIDDEN_LINKONCE 1 4951 #else 4952 # define USE_HIDDEN_LINKONCE 0 4953 #endif 4954 4955 static void 4956 get_pc_thunk_name (char name[32], unsigned int regno) 4957 { 4958 const char *reg_name = reg_names[regno]; 4959 4960 /* Skip the leading '%' as that cannot be used in a 4961 symbol name. */ 4962 reg_name += 1; 4963 4964 if (USE_HIDDEN_LINKONCE) 4965 sprintf (name, "__sparc_get_pc_thunk.%s", reg_name); 4966 else 4967 ASM_GENERATE_INTERNAL_LABEL (name, "LADDPC", regno); 4968 } 4969 4970 /* Wrapper around the load_pcrel_sym{si,di} patterns. */ 4971 4972 static rtx 4973 gen_load_pcrel_sym (rtx op0, rtx op1, rtx op2, rtx op3) 4974 { 4975 int orig_flag_pic = flag_pic; 4976 rtx insn; 4977 4978 /* The load_pcrel_sym{si,di} patterns require absolute addressing. */ 4979 flag_pic = 0; 4980 if (TARGET_ARCH64) 4981 insn = gen_load_pcrel_symdi (op0, op1, op2, op3); 4982 else 4983 insn = gen_load_pcrel_symsi (op0, op1, op2, op3); 4984 flag_pic = orig_flag_pic; 4985 4986 return insn; 4987 } 4988 4989 /* Emit code to load the GOT register. */ 4990 4991 void 4992 load_got_register (void) 4993 { 4994 /* In PIC mode, this will retrieve pic_offset_table_rtx. */ 4995 if (!global_offset_table_rtx) 4996 global_offset_table_rtx = gen_rtx_REG (Pmode, GLOBAL_OFFSET_TABLE_REGNUM); 4997 4998 if (TARGET_VXWORKS_RTP) 4999 emit_insn (gen_vxworks_load_got ()); 5000 else 5001 { 5002 /* The GOT symbol is subject to a PC-relative relocation so we need a 5003 helper function to add the PC value and thus get the final value. */ 5004 if (!got_helper_rtx) 5005 { 5006 char name[32]; 5007 get_pc_thunk_name (name, GLOBAL_OFFSET_TABLE_REGNUM); 5008 got_helper_rtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (name)); 5009 } 5010 5011 emit_insn (gen_load_pcrel_sym (global_offset_table_rtx, sparc_got (), 5012 got_helper_rtx, 5013 GEN_INT (GLOBAL_OFFSET_TABLE_REGNUM))); 5014 } 5015 5016 /* Need to emit this whether or not we obey regdecls, 5017 since setjmp/longjmp can cause life info to screw up. 5018 ??? In the case where we don't obey regdecls, this is not sufficient 5019 since we may not fall out the bottom. */ 5020 emit_use (global_offset_table_rtx); 5021 } 5022 5023 /* Emit a call instruction with the pattern given by PAT. ADDR is the 5024 address of the call target. */ 5025 5026 void 5027 sparc_emit_call_insn (rtx pat, rtx addr) 5028 { 5029 rtx_insn *insn; 5030 5031 insn = emit_call_insn (pat); 5032 5033 /* The PIC register is live on entry to VxWorks PIC PLT entries. */ 5034 if (TARGET_VXWORKS_RTP 5035 && flag_pic 5036 && GET_CODE (addr) == SYMBOL_REF 5037 && (SYMBOL_REF_DECL (addr) 5038 ? !targetm.binds_local_p (SYMBOL_REF_DECL (addr)) 5039 : !SYMBOL_REF_LOCAL_P (addr))) 5040 { 5041 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), pic_offset_table_rtx); 5042 crtl->uses_pic_offset_table = 1; 5043 } 5044 } 5045 5046 /* Return 1 if RTX is a MEM which is known to be aligned to at 5047 least a DESIRED byte boundary. */ 5048 5049 int 5050 mem_min_alignment (rtx mem, int desired) 5051 { 5052 rtx addr, base, offset; 5053 5054 /* If it's not a MEM we can't accept it. */ 5055 if (GET_CODE (mem) != MEM) 5056 return 0; 5057 5058 /* Obviously... */ 5059 if (!TARGET_UNALIGNED_DOUBLES 5060 && MEM_ALIGN (mem) / BITS_PER_UNIT >= (unsigned)desired) 5061 return 1; 5062 5063 /* ??? The rest of the function predates MEM_ALIGN so 5064 there is probably a bit of redundancy. */ 5065 addr = XEXP (mem, 0); 5066 base = offset = NULL_RTX; 5067 if (GET_CODE (addr) == PLUS) 5068 { 5069 if (GET_CODE (XEXP (addr, 0)) == REG) 5070 { 5071 base = XEXP (addr, 0); 5072 5073 /* What we are saying here is that if the base 5074 REG is aligned properly, the compiler will make 5075 sure any REG based index upon it will be so 5076 as well. */ 5077 if (GET_CODE (XEXP (addr, 1)) == CONST_INT) 5078 offset = XEXP (addr, 1); 5079 else 5080 offset = const0_rtx; 5081 } 5082 } 5083 else if (GET_CODE (addr) == REG) 5084 { 5085 base = addr; 5086 offset = const0_rtx; 5087 } 5088 5089 if (base != NULL_RTX) 5090 { 5091 int regno = REGNO (base); 5092 5093 if (regno != HARD_FRAME_POINTER_REGNUM && regno != STACK_POINTER_REGNUM) 5094 { 5095 /* Check if the compiler has recorded some information 5096 about the alignment of the base REG. If reload has 5097 completed, we already matched with proper alignments. 5098 If not running global_alloc, reload might give us 5099 unaligned pointer to local stack though. */ 5100 if (((cfun != 0 5101 && REGNO_POINTER_ALIGN (regno) >= desired * BITS_PER_UNIT) 5102 || (optimize && reload_completed)) 5103 && (INTVAL (offset) & (desired - 1)) == 0) 5104 return 1; 5105 } 5106 else 5107 { 5108 if (((INTVAL (offset) - SPARC_STACK_BIAS) & (desired - 1)) == 0) 5109 return 1; 5110 } 5111 } 5112 else if (! TARGET_UNALIGNED_DOUBLES 5113 || CONSTANT_P (addr) 5114 || GET_CODE (addr) == LO_SUM) 5115 { 5116 /* Anything else we know is properly aligned unless TARGET_UNALIGNED_DOUBLES 5117 is true, in which case we can only assume that an access is aligned if 5118 it is to a constant address, or the address involves a LO_SUM. */ 5119 return 1; 5120 } 5121 5122 /* An obviously unaligned address. */ 5123 return 0; 5124 } 5125 5126 5127 /* Vectors to keep interesting information about registers where it can easily 5128 be got. We used to use the actual mode value as the bit number, but there 5129 are more than 32 modes now. Instead we use two tables: one indexed by 5130 hard register number, and one indexed by mode. */ 5131 5132 /* The purpose of sparc_mode_class is to shrink the range of modes so that 5133 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is 5134 mapped into one sparc_mode_class mode. */ 5135 5136 enum sparc_mode_class { 5137 H_MODE, S_MODE, D_MODE, T_MODE, O_MODE, 5138 SF_MODE, DF_MODE, TF_MODE, OF_MODE, 5139 CC_MODE, CCFP_MODE 5140 }; 5141 5142 /* Modes for single-word and smaller quantities. */ 5143 #define S_MODES \ 5144 ((1 << (int) H_MODE) | (1 << (int) S_MODE) | (1 << (int) SF_MODE)) 5145 5146 /* Modes for double-word and smaller quantities. */ 5147 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE)) 5148 5149 /* Modes for quad-word and smaller quantities. */ 5150 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) 5151 5152 /* Modes for 8-word and smaller quantities. */ 5153 #define O_MODES (T_MODES | (1 << (int) O_MODE) | (1 << (int) OF_MODE)) 5154 5155 /* Modes for single-float quantities. */ 5156 #define SF_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) 5157 5158 /* Modes for double-float and smaller quantities. */ 5159 #define DF_MODES (SF_MODES | (1 << (int) D_MODE) | (1 << (int) DF_MODE)) 5160 5161 /* Modes for quad-float and smaller quantities. */ 5162 #define TF_MODES (DF_MODES | (1 << (int) TF_MODE)) 5163 5164 /* Modes for quad-float pairs and smaller quantities. */ 5165 #define OF_MODES (TF_MODES | (1 << (int) OF_MODE)) 5166 5167 /* Modes for double-float only quantities. */ 5168 #define DF_MODES_NO_S ((1 << (int) D_MODE) | (1 << (int) DF_MODE)) 5169 5170 /* Modes for quad-float and double-float only quantities. */ 5171 #define TF_MODES_NO_S (DF_MODES_NO_S | (1 << (int) TF_MODE)) 5172 5173 /* Modes for quad-float pairs and double-float only quantities. */ 5174 #define OF_MODES_NO_S (TF_MODES_NO_S | (1 << (int) OF_MODE)) 5175 5176 /* Modes for condition codes. */ 5177 #define CC_MODES (1 << (int) CC_MODE) 5178 #define CCFP_MODES (1 << (int) CCFP_MODE) 5179 5180 /* Value is 1 if register/mode pair is acceptable on sparc. 5181 5182 The funny mixture of D and T modes is because integer operations 5183 do not specially operate on tetra quantities, so non-quad-aligned 5184 registers can hold quadword quantities (except %o4 and %i4 because 5185 they cross fixed registers). 5186 5187 ??? Note that, despite the settings, non-double-aligned parameter 5188 registers can hold double-word quantities in 32-bit mode. */ 5189 5190 /* This points to either the 32-bit or the 64-bit version. */ 5191 const int *hard_regno_mode_classes; 5192 5193 static const int hard_32bit_mode_classes[] = { 5194 S_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 5195 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 5196 T_MODES, S_MODES, T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, 5197 T_MODES, S_MODES, T_MODES, S_MODES, D_MODES, S_MODES, D_MODES, S_MODES, 5198 5199 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 5200 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 5201 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 5202 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 5203 5204 /* FP regs f32 to f63. Only the even numbered registers actually exist, 5205 and none can hold SFmode/SImode values. */ 5206 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 5207 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 5208 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 5209 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 5210 5211 /* %fcc[0123] */ 5212 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 5213 5214 /* %icc, %sfp, %gsr */ 5215 CC_MODES, 0, D_MODES 5216 }; 5217 5218 static const int hard_64bit_mode_classes[] = { 5219 D_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 5220 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 5221 T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 5222 O_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, T_MODES, D_MODES, 5223 5224 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 5225 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 5226 OF_MODES, SF_MODES, DF_MODES, SF_MODES, OF_MODES, SF_MODES, DF_MODES, SF_MODES, 5227 OF_MODES, SF_MODES, DF_MODES, SF_MODES, TF_MODES, SF_MODES, DF_MODES, SF_MODES, 5228 5229 /* FP regs f32 to f63. Only the even numbered registers actually exist, 5230 and none can hold SFmode/SImode values. */ 5231 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 5232 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 5233 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 5234 OF_MODES_NO_S, 0, DF_MODES_NO_S, 0, TF_MODES_NO_S, 0, DF_MODES_NO_S, 0, 5235 5236 /* %fcc[0123] */ 5237 CCFP_MODES, CCFP_MODES, CCFP_MODES, CCFP_MODES, 5238 5239 /* %icc, %sfp, %gsr */ 5240 CC_MODES, 0, D_MODES 5241 }; 5242 5243 int sparc_mode_class [NUM_MACHINE_MODES]; 5244 5245 enum reg_class sparc_regno_reg_class[FIRST_PSEUDO_REGISTER]; 5246 5247 static void 5248 sparc_init_modes (void) 5249 { 5250 int i; 5251 5252 for (i = 0; i < NUM_MACHINE_MODES; i++) 5253 { 5254 machine_mode m = (machine_mode) i; 5255 unsigned int size = GET_MODE_SIZE (m); 5256 5257 switch (GET_MODE_CLASS (m)) 5258 { 5259 case MODE_INT: 5260 case MODE_PARTIAL_INT: 5261 case MODE_COMPLEX_INT: 5262 if (size < 4) 5263 sparc_mode_class[i] = 1 << (int) H_MODE; 5264 else if (size == 4) 5265 sparc_mode_class[i] = 1 << (int) S_MODE; 5266 else if (size == 8) 5267 sparc_mode_class[i] = 1 << (int) D_MODE; 5268 else if (size == 16) 5269 sparc_mode_class[i] = 1 << (int) T_MODE; 5270 else if (size == 32) 5271 sparc_mode_class[i] = 1 << (int) O_MODE; 5272 else 5273 sparc_mode_class[i] = 0; 5274 break; 5275 case MODE_VECTOR_INT: 5276 if (size == 4) 5277 sparc_mode_class[i] = 1 << (int) SF_MODE; 5278 else if (size == 8) 5279 sparc_mode_class[i] = 1 << (int) DF_MODE; 5280 else 5281 sparc_mode_class[i] = 0; 5282 break; 5283 case MODE_FLOAT: 5284 case MODE_COMPLEX_FLOAT: 5285 if (size == 4) 5286 sparc_mode_class[i] = 1 << (int) SF_MODE; 5287 else if (size == 8) 5288 sparc_mode_class[i] = 1 << (int) DF_MODE; 5289 else if (size == 16) 5290 sparc_mode_class[i] = 1 << (int) TF_MODE; 5291 else if (size == 32) 5292 sparc_mode_class[i] = 1 << (int) OF_MODE; 5293 else 5294 sparc_mode_class[i] = 0; 5295 break; 5296 case MODE_CC: 5297 if (m == CCFPmode || m == CCFPEmode) 5298 sparc_mode_class[i] = 1 << (int) CCFP_MODE; 5299 else 5300 sparc_mode_class[i] = 1 << (int) CC_MODE; 5301 break; 5302 default: 5303 sparc_mode_class[i] = 0; 5304 break; 5305 } 5306 } 5307 5308 if (TARGET_ARCH64) 5309 hard_regno_mode_classes = hard_64bit_mode_classes; 5310 else 5311 hard_regno_mode_classes = hard_32bit_mode_classes; 5312 5313 /* Initialize the array used by REGNO_REG_CLASS. */ 5314 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 5315 { 5316 if (i < 16 && TARGET_V8PLUS) 5317 sparc_regno_reg_class[i] = I64_REGS; 5318 else if (i < 32 || i == FRAME_POINTER_REGNUM) 5319 sparc_regno_reg_class[i] = GENERAL_REGS; 5320 else if (i < 64) 5321 sparc_regno_reg_class[i] = FP_REGS; 5322 else if (i < 96) 5323 sparc_regno_reg_class[i] = EXTRA_FP_REGS; 5324 else if (i < 100) 5325 sparc_regno_reg_class[i] = FPCC_REGS; 5326 else 5327 sparc_regno_reg_class[i] = NO_REGS; 5328 } 5329 } 5330 5331 /* Return whether REGNO, a global or FP register, must be saved/restored. */ 5332 5333 static inline bool 5334 save_global_or_fp_reg_p (unsigned int regno, 5335 int leaf_function ATTRIBUTE_UNUSED) 5336 { 5337 return !call_used_regs[regno] && df_regs_ever_live_p (regno); 5338 } 5339 5340 /* Return whether the return address register (%i7) is needed. */ 5341 5342 static inline bool 5343 return_addr_reg_needed_p (int leaf_function) 5344 { 5345 /* If it is live, for example because of __builtin_return_address (0). */ 5346 if (df_regs_ever_live_p (RETURN_ADDR_REGNUM)) 5347 return true; 5348 5349 /* Otherwise, it is needed as save register if %o7 is clobbered. */ 5350 if (!leaf_function 5351 /* Loading the GOT register clobbers %o7. */ 5352 || crtl->uses_pic_offset_table 5353 || df_regs_ever_live_p (INCOMING_RETURN_ADDR_REGNUM)) 5354 return true; 5355 5356 return false; 5357 } 5358 5359 /* Return whether REGNO, a local or in register, must be saved/restored. */ 5360 5361 static bool 5362 save_local_or_in_reg_p (unsigned int regno, int leaf_function) 5363 { 5364 /* General case: call-saved registers live at some point. */ 5365 if (!call_used_regs[regno] && df_regs_ever_live_p (regno)) 5366 return true; 5367 5368 /* Frame pointer register (%fp) if needed. */ 5369 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) 5370 return true; 5371 5372 /* Return address register (%i7) if needed. */ 5373 if (regno == RETURN_ADDR_REGNUM && return_addr_reg_needed_p (leaf_function)) 5374 return true; 5375 5376 /* GOT register (%l7) if needed. */ 5377 if (regno == PIC_OFFSET_TABLE_REGNUM && crtl->uses_pic_offset_table) 5378 return true; 5379 5380 /* If the function accesses prior frames, the frame pointer and the return 5381 address of the previous frame must be saved on the stack. */ 5382 if (crtl->accesses_prior_frames 5383 && (regno == HARD_FRAME_POINTER_REGNUM || regno == RETURN_ADDR_REGNUM)) 5384 return true; 5385 5386 return false; 5387 } 5388 5389 /* Compute the frame size required by the function. This function is called 5390 during the reload pass and also by sparc_expand_prologue. */ 5391 5392 HOST_WIDE_INT 5393 sparc_compute_frame_size (HOST_WIDE_INT size, int leaf_function) 5394 { 5395 HOST_WIDE_INT frame_size, apparent_frame_size; 5396 int args_size, n_global_fp_regs = 0; 5397 bool save_local_in_regs_p = false; 5398 unsigned int i; 5399 5400 /* If the function allocates dynamic stack space, the dynamic offset is 5401 computed early and contains REG_PARM_STACK_SPACE, so we need to cope. */ 5402 if (leaf_function && !cfun->calls_alloca) 5403 args_size = 0; 5404 else 5405 args_size = crtl->outgoing_args_size + REG_PARM_STACK_SPACE (cfun->decl); 5406 5407 /* Calculate space needed for global registers. */ 5408 if (TARGET_ARCH64) 5409 { 5410 for (i = 0; i < 8; i++) 5411 if (save_global_or_fp_reg_p (i, 0)) 5412 n_global_fp_regs += 2; 5413 } 5414 else 5415 { 5416 for (i = 0; i < 8; i += 2) 5417 if (save_global_or_fp_reg_p (i, 0) 5418 || save_global_or_fp_reg_p (i + 1, 0)) 5419 n_global_fp_regs += 2; 5420 } 5421 5422 /* In the flat window model, find out which local and in registers need to 5423 be saved. We don't reserve space in the current frame for them as they 5424 will be spilled into the register window save area of the caller's frame. 5425 However, as soon as we use this register window save area, we must create 5426 that of the current frame to make it the live one. */ 5427 if (TARGET_FLAT) 5428 for (i = 16; i < 32; i++) 5429 if (save_local_or_in_reg_p (i, leaf_function)) 5430 { 5431 save_local_in_regs_p = true; 5432 break; 5433 } 5434 5435 /* Calculate space needed for FP registers. */ 5436 for (i = 32; i < (TARGET_V9 ? 96 : 64); i += 2) 5437 if (save_global_or_fp_reg_p (i, 0) || save_global_or_fp_reg_p (i + 1, 0)) 5438 n_global_fp_regs += 2; 5439 5440 if (size == 0 5441 && n_global_fp_regs == 0 5442 && args_size == 0 5443 && !save_local_in_regs_p) 5444 frame_size = apparent_frame_size = 0; 5445 else 5446 { 5447 /* We subtract STARTING_FRAME_OFFSET, remember it's negative. */ 5448 apparent_frame_size = ROUND_UP (size - STARTING_FRAME_OFFSET, 8); 5449 apparent_frame_size += n_global_fp_regs * 4; 5450 5451 /* We need to add the size of the outgoing argument area. */ 5452 frame_size = apparent_frame_size + ROUND_UP (args_size, 8); 5453 5454 /* And that of the register window save area. */ 5455 frame_size += FIRST_PARM_OFFSET (cfun->decl); 5456 5457 /* Finally, bump to the appropriate alignment. */ 5458 frame_size = SPARC_STACK_ALIGN (frame_size); 5459 } 5460 5461 /* Set up values for use in prologue and epilogue. */ 5462 sparc_frame_size = frame_size; 5463 sparc_apparent_frame_size = apparent_frame_size; 5464 sparc_n_global_fp_regs = n_global_fp_regs; 5465 sparc_save_local_in_regs_p = save_local_in_regs_p; 5466 5467 return frame_size; 5468 } 5469 5470 /* Implement the macro INITIAL_ELIMINATION_OFFSET, return the OFFSET. */ 5471 5472 int 5473 sparc_initial_elimination_offset (int to) 5474 { 5475 int offset; 5476 5477 if (to == STACK_POINTER_REGNUM) 5478 offset = sparc_compute_frame_size (get_frame_size (), crtl->is_leaf); 5479 else 5480 offset = 0; 5481 5482 offset += SPARC_STACK_BIAS; 5483 return offset; 5484 } 5485 5486 /* Output any necessary .register pseudo-ops. */ 5487 5488 void 5489 sparc_output_scratch_registers (FILE *file ATTRIBUTE_UNUSED) 5490 { 5491 #ifdef HAVE_AS_REGISTER_PSEUDO_OP 5492 int i; 5493 5494 if (TARGET_ARCH32) 5495 return; 5496 5497 /* Check if %g[2367] were used without 5498 .register being printed for them already. */ 5499 for (i = 2; i < 8; i++) 5500 { 5501 if (df_regs_ever_live_p (i) 5502 && ! sparc_hard_reg_printed [i]) 5503 { 5504 sparc_hard_reg_printed [i] = 1; 5505 /* %g7 is used as TLS base register, use #ignore 5506 for it instead of #scratch. */ 5507 fprintf (file, "\t.register\t%%g%d, #%s\n", i, 5508 i == 7 ? "ignore" : "scratch"); 5509 } 5510 if (i == 3) i = 5; 5511 } 5512 #endif 5513 } 5514 5515 #define PROBE_INTERVAL (1 << STACK_CHECK_PROBE_INTERVAL_EXP) 5516 5517 #if PROBE_INTERVAL > 4096 5518 #error Cannot use indexed addressing mode for stack probing 5519 #endif 5520 5521 /* Emit code to probe a range of stack addresses from FIRST to FIRST+SIZE, 5522 inclusive. These are offsets from the current stack pointer. 5523 5524 Note that we don't use the REG+REG addressing mode for the probes because 5525 of the stack bias in 64-bit mode. And it doesn't really buy us anything 5526 so the advantages of having a single code win here. */ 5527 5528 static void 5529 sparc_emit_probe_stack_range (HOST_WIDE_INT first, HOST_WIDE_INT size) 5530 { 5531 rtx g1 = gen_rtx_REG (Pmode, 1); 5532 5533 /* See if we have a constant small number of probes to generate. If so, 5534 that's the easy case. */ 5535 if (size <= PROBE_INTERVAL) 5536 { 5537 emit_move_insn (g1, GEN_INT (first)); 5538 emit_insn (gen_rtx_SET (g1, 5539 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1))); 5540 emit_stack_probe (plus_constant (Pmode, g1, -size)); 5541 } 5542 5543 /* The run-time loop is made up of 9 insns in the generic case while the 5544 compile-time loop is made up of 4+2*(n-2) insns for n # of intervals. */ 5545 else if (size <= 4 * PROBE_INTERVAL) 5546 { 5547 HOST_WIDE_INT i; 5548 5549 emit_move_insn (g1, GEN_INT (first + PROBE_INTERVAL)); 5550 emit_insn (gen_rtx_SET (g1, 5551 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1))); 5552 emit_stack_probe (g1); 5553 5554 /* Probe at FIRST + N * PROBE_INTERVAL for values of N from 2 until 5555 it exceeds SIZE. If only two probes are needed, this will not 5556 generate any code. Then probe at FIRST + SIZE. */ 5557 for (i = 2 * PROBE_INTERVAL; i < size; i += PROBE_INTERVAL) 5558 { 5559 emit_insn (gen_rtx_SET (g1, 5560 plus_constant (Pmode, g1, -PROBE_INTERVAL))); 5561 emit_stack_probe (g1); 5562 } 5563 5564 emit_stack_probe (plus_constant (Pmode, g1, 5565 (i - PROBE_INTERVAL) - size)); 5566 } 5567 5568 /* Otherwise, do the same as above, but in a loop. Note that we must be 5569 extra careful with variables wrapping around because we might be at 5570 the very top (or the very bottom) of the address space and we have 5571 to be able to handle this case properly; in particular, we use an 5572 equality test for the loop condition. */ 5573 else 5574 { 5575 HOST_WIDE_INT rounded_size; 5576 rtx g4 = gen_rtx_REG (Pmode, 4); 5577 5578 emit_move_insn (g1, GEN_INT (first)); 5579 5580 5581 /* Step 1: round SIZE to the previous multiple of the interval. */ 5582 5583 rounded_size = ROUND_DOWN (size, PROBE_INTERVAL); 5584 emit_move_insn (g4, GEN_INT (rounded_size)); 5585 5586 5587 /* Step 2: compute initial and final value of the loop counter. */ 5588 5589 /* TEST_ADDR = SP + FIRST. */ 5590 emit_insn (gen_rtx_SET (g1, 5591 gen_rtx_MINUS (Pmode, stack_pointer_rtx, g1))); 5592 5593 /* LAST_ADDR = SP + FIRST + ROUNDED_SIZE. */ 5594 emit_insn (gen_rtx_SET (g4, gen_rtx_MINUS (Pmode, g1, g4))); 5595 5596 5597 /* Step 3: the loop 5598 5599 while (TEST_ADDR != LAST_ADDR) 5600 { 5601 TEST_ADDR = TEST_ADDR + PROBE_INTERVAL 5602 probe at TEST_ADDR 5603 } 5604 5605 probes at FIRST + N * PROBE_INTERVAL for values of N from 1 5606 until it is equal to ROUNDED_SIZE. */ 5607 5608 if (TARGET_ARCH64) 5609 emit_insn (gen_probe_stack_rangedi (g1, g1, g4)); 5610 else 5611 emit_insn (gen_probe_stack_rangesi (g1, g1, g4)); 5612 5613 5614 /* Step 4: probe at FIRST + SIZE if we cannot assert at compile-time 5615 that SIZE is equal to ROUNDED_SIZE. */ 5616 5617 if (size != rounded_size) 5618 emit_stack_probe (plus_constant (Pmode, g4, rounded_size - size)); 5619 } 5620 5621 /* Make sure nothing is scheduled before we are done. */ 5622 emit_insn (gen_blockage ()); 5623 } 5624 5625 /* Probe a range of stack addresses from REG1 to REG2 inclusive. These are 5626 absolute addresses. */ 5627 5628 const char * 5629 output_probe_stack_range (rtx reg1, rtx reg2) 5630 { 5631 static int labelno = 0; 5632 char loop_lab[32]; 5633 rtx xops[2]; 5634 5635 ASM_GENERATE_INTERNAL_LABEL (loop_lab, "LPSRL", labelno++); 5636 5637 /* Loop. */ 5638 ASM_OUTPUT_INTERNAL_LABEL (asm_out_file, loop_lab); 5639 5640 /* TEST_ADDR = TEST_ADDR + PROBE_INTERVAL. */ 5641 xops[0] = reg1; 5642 xops[1] = GEN_INT (-PROBE_INTERVAL); 5643 output_asm_insn ("add\t%0, %1, %0", xops); 5644 5645 /* Test if TEST_ADDR == LAST_ADDR. */ 5646 xops[1] = reg2; 5647 output_asm_insn ("cmp\t%0, %1", xops); 5648 5649 /* Probe at TEST_ADDR and branch. */ 5650 if (TARGET_ARCH64) 5651 fputs ("\tbne,pt\t%xcc,", asm_out_file); 5652 else 5653 fputs ("\tbne\t", asm_out_file); 5654 assemble_name_raw (asm_out_file, loop_lab); 5655 fputc ('\n', asm_out_file); 5656 xops[1] = GEN_INT (SPARC_STACK_BIAS); 5657 output_asm_insn (" st\t%%g0, [%0+%1]", xops); 5658 5659 return ""; 5660 } 5661 5662 /* Emit code to save/restore registers from LOW to HIGH at BASE+OFFSET as 5663 needed. LOW is supposed to be double-word aligned for 32-bit registers. 5664 SAVE_P decides whether a register must be saved/restored. ACTION_TRUE 5665 is the action to be performed if SAVE_P returns true and ACTION_FALSE 5666 the action to be performed if it returns false. Return the new offset. */ 5667 5668 typedef bool (*sorr_pred_t) (unsigned int, int); 5669 typedef enum { SORR_NONE, SORR_ADVANCE, SORR_SAVE, SORR_RESTORE } sorr_act_t; 5670 5671 static int 5672 emit_save_or_restore_regs (unsigned int low, unsigned int high, rtx base, 5673 int offset, int leaf_function, sorr_pred_t save_p, 5674 sorr_act_t action_true, sorr_act_t action_false) 5675 { 5676 unsigned int i; 5677 rtx mem; 5678 rtx_insn *insn; 5679 5680 if (TARGET_ARCH64 && high <= 32) 5681 { 5682 int fp_offset = -1; 5683 5684 for (i = low; i < high; i++) 5685 { 5686 if (save_p (i, leaf_function)) 5687 { 5688 mem = gen_frame_mem (DImode, plus_constant (Pmode, 5689 base, offset)); 5690 if (action_true == SORR_SAVE) 5691 { 5692 insn = emit_move_insn (mem, gen_rtx_REG (DImode, i)); 5693 RTX_FRAME_RELATED_P (insn) = 1; 5694 } 5695 else /* action_true == SORR_RESTORE */ 5696 { 5697 /* The frame pointer must be restored last since its old 5698 value may be used as base address for the frame. This 5699 is problematic in 64-bit mode only because of the lack 5700 of double-word load instruction. */ 5701 if (i == HARD_FRAME_POINTER_REGNUM) 5702 fp_offset = offset; 5703 else 5704 emit_move_insn (gen_rtx_REG (DImode, i), mem); 5705 } 5706 offset += 8; 5707 } 5708 else if (action_false == SORR_ADVANCE) 5709 offset += 8; 5710 } 5711 5712 if (fp_offset >= 0) 5713 { 5714 mem = gen_frame_mem (DImode, plus_constant (Pmode, base, fp_offset)); 5715 emit_move_insn (hard_frame_pointer_rtx, mem); 5716 } 5717 } 5718 else 5719 { 5720 for (i = low; i < high; i += 2) 5721 { 5722 bool reg0 = save_p (i, leaf_function); 5723 bool reg1 = save_p (i + 1, leaf_function); 5724 machine_mode mode; 5725 int regno; 5726 5727 if (reg0 && reg1) 5728 { 5729 mode = SPARC_INT_REG_P (i) ? DImode : DFmode; 5730 regno = i; 5731 } 5732 else if (reg0) 5733 { 5734 mode = SPARC_INT_REG_P (i) ? SImode : SFmode; 5735 regno = i; 5736 } 5737 else if (reg1) 5738 { 5739 mode = SPARC_INT_REG_P (i) ? SImode : SFmode; 5740 regno = i + 1; 5741 offset += 4; 5742 } 5743 else 5744 { 5745 if (action_false == SORR_ADVANCE) 5746 offset += 8; 5747 continue; 5748 } 5749 5750 mem = gen_frame_mem (mode, plus_constant (Pmode, base, offset)); 5751 if (action_true == SORR_SAVE) 5752 { 5753 insn = emit_move_insn (mem, gen_rtx_REG (mode, regno)); 5754 RTX_FRAME_RELATED_P (insn) = 1; 5755 if (mode == DImode) 5756 { 5757 rtx set1, set2; 5758 mem = gen_frame_mem (SImode, plus_constant (Pmode, base, 5759 offset)); 5760 set1 = gen_rtx_SET (mem, gen_rtx_REG (SImode, regno)); 5761 RTX_FRAME_RELATED_P (set1) = 1; 5762 mem 5763 = gen_frame_mem (SImode, plus_constant (Pmode, base, 5764 offset + 4)); 5765 set2 = gen_rtx_SET (mem, gen_rtx_REG (SImode, regno + 1)); 5766 RTX_FRAME_RELATED_P (set2) = 1; 5767 add_reg_note (insn, REG_FRAME_RELATED_EXPR, 5768 gen_rtx_PARALLEL (VOIDmode, 5769 gen_rtvec (2, set1, set2))); 5770 } 5771 } 5772 else /* action_true == SORR_RESTORE */ 5773 emit_move_insn (gen_rtx_REG (mode, regno), mem); 5774 5775 /* Bump and round down to double word 5776 in case we already bumped by 4. */ 5777 offset = ROUND_DOWN (offset + 8, 8); 5778 } 5779 } 5780 5781 return offset; 5782 } 5783 5784 /* Emit code to adjust BASE to OFFSET. Return the new base. */ 5785 5786 static rtx 5787 emit_adjust_base_to_offset (rtx base, int offset) 5788 { 5789 /* ??? This might be optimized a little as %g1 might already have a 5790 value close enough that a single add insn will do. */ 5791 /* ??? Although, all of this is probably only a temporary fix because 5792 if %g1 can hold a function result, then sparc_expand_epilogue will 5793 lose (the result will be clobbered). */ 5794 rtx new_base = gen_rtx_REG (Pmode, 1); 5795 emit_move_insn (new_base, GEN_INT (offset)); 5796 emit_insn (gen_rtx_SET (new_base, gen_rtx_PLUS (Pmode, base, new_base))); 5797 return new_base; 5798 } 5799 5800 /* Emit code to save/restore call-saved global and FP registers. */ 5801 5802 static void 5803 emit_save_or_restore_global_fp_regs (rtx base, int offset, sorr_act_t action) 5804 { 5805 if (offset < -4096 || offset + sparc_n_global_fp_regs * 4 > 4095) 5806 { 5807 base = emit_adjust_base_to_offset (base, offset); 5808 offset = 0; 5809 } 5810 5811 offset 5812 = emit_save_or_restore_regs (0, 8, base, offset, 0, 5813 save_global_or_fp_reg_p, action, SORR_NONE); 5814 emit_save_or_restore_regs (32, TARGET_V9 ? 96 : 64, base, offset, 0, 5815 save_global_or_fp_reg_p, action, SORR_NONE); 5816 } 5817 5818 /* Emit code to save/restore call-saved local and in registers. */ 5819 5820 static void 5821 emit_save_or_restore_local_in_regs (rtx base, int offset, sorr_act_t action) 5822 { 5823 if (offset < -4096 || offset + 16 * UNITS_PER_WORD > 4095) 5824 { 5825 base = emit_adjust_base_to_offset (base, offset); 5826 offset = 0; 5827 } 5828 5829 emit_save_or_restore_regs (16, 32, base, offset, sparc_leaf_function_p, 5830 save_local_or_in_reg_p, action, SORR_ADVANCE); 5831 } 5832 5833 /* Emit a window_save insn. */ 5834 5835 static rtx_insn * 5836 emit_window_save (rtx increment) 5837 { 5838 rtx_insn *insn = emit_insn (gen_window_save (increment)); 5839 RTX_FRAME_RELATED_P (insn) = 1; 5840 5841 /* The incoming return address (%o7) is saved in %i7. */ 5842 add_reg_note (insn, REG_CFA_REGISTER, 5843 gen_rtx_SET (gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM), 5844 gen_rtx_REG (Pmode, 5845 INCOMING_RETURN_ADDR_REGNUM))); 5846 5847 /* The window save event. */ 5848 add_reg_note (insn, REG_CFA_WINDOW_SAVE, const0_rtx); 5849 5850 /* The CFA is %fp, the hard frame pointer. */ 5851 add_reg_note (insn, REG_CFA_DEF_CFA, 5852 plus_constant (Pmode, hard_frame_pointer_rtx, 5853 INCOMING_FRAME_SP_OFFSET)); 5854 5855 return insn; 5856 } 5857 5858 /* Generate an increment for the stack pointer. */ 5859 5860 static rtx 5861 gen_stack_pointer_inc (rtx increment) 5862 { 5863 return gen_rtx_SET (stack_pointer_rtx, 5864 gen_rtx_PLUS (Pmode, 5865 stack_pointer_rtx, 5866 increment)); 5867 } 5868 5869 /* Expand the function prologue. The prologue is responsible for reserving 5870 storage for the frame, saving the call-saved registers and loading the 5871 GOT register if needed. */ 5872 5873 void 5874 sparc_expand_prologue (void) 5875 { 5876 HOST_WIDE_INT size; 5877 rtx_insn *insn; 5878 5879 /* Compute a snapshot of crtl->uses_only_leaf_regs. Relying 5880 on the final value of the flag means deferring the prologue/epilogue 5881 expansion until just before the second scheduling pass, which is too 5882 late to emit multiple epilogues or return insns. 5883 5884 Of course we are making the assumption that the value of the flag 5885 will not change between now and its final value. Of the three parts 5886 of the formula, only the last one can reasonably vary. Let's take a 5887 closer look, after assuming that the first two ones are set to true 5888 (otherwise the last value is effectively silenced). 5889 5890 If only_leaf_regs_used returns false, the global predicate will also 5891 be false so the actual frame size calculated below will be positive. 5892 As a consequence, the save_register_window insn will be emitted in 5893 the instruction stream; now this insn explicitly references %fp 5894 which is not a leaf register so only_leaf_regs_used will always 5895 return false subsequently. 5896 5897 If only_leaf_regs_used returns true, we hope that the subsequent 5898 optimization passes won't cause non-leaf registers to pop up. For 5899 example, the regrename pass has special provisions to not rename to 5900 non-leaf registers in a leaf function. */ 5901 sparc_leaf_function_p 5902 = optimize > 0 && crtl->is_leaf && only_leaf_regs_used (); 5903 5904 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p); 5905 5906 if (flag_stack_usage_info) 5907 current_function_static_stack_size = size; 5908 5909 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) 5910 { 5911 if (crtl->is_leaf && !cfun->calls_alloca) 5912 { 5913 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT) 5914 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, 5915 size - STACK_CHECK_PROTECT); 5916 } 5917 else if (size > 0) 5918 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size); 5919 } 5920 5921 if (size == 0) 5922 ; /* do nothing. */ 5923 else if (sparc_leaf_function_p) 5924 { 5925 rtx size_int_rtx = GEN_INT (-size); 5926 5927 if (size <= 4096) 5928 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx)); 5929 else if (size <= 8192) 5930 { 5931 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096))); 5932 RTX_FRAME_RELATED_P (insn) = 1; 5933 5934 /* %sp is still the CFA register. */ 5935 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size))); 5936 } 5937 else 5938 { 5939 rtx size_rtx = gen_rtx_REG (Pmode, 1); 5940 emit_move_insn (size_rtx, size_int_rtx); 5941 insn = emit_insn (gen_stack_pointer_inc (size_rtx)); 5942 add_reg_note (insn, REG_FRAME_RELATED_EXPR, 5943 gen_stack_pointer_inc (size_int_rtx)); 5944 } 5945 5946 RTX_FRAME_RELATED_P (insn) = 1; 5947 } 5948 else 5949 { 5950 rtx size_int_rtx = GEN_INT (-size); 5951 5952 if (size <= 4096) 5953 emit_window_save (size_int_rtx); 5954 else if (size <= 8192) 5955 { 5956 emit_window_save (GEN_INT (-4096)); 5957 5958 /* %sp is not the CFA register anymore. */ 5959 emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size))); 5960 5961 /* Make sure no %fp-based store is issued until after the frame is 5962 established. The offset between the frame pointer and the stack 5963 pointer is calculated relative to the value of the stack pointer 5964 at the end of the function prologue, and moving instructions that 5965 access the stack via the frame pointer between the instructions 5966 that decrement the stack pointer could result in accessing the 5967 register window save area, which is volatile. */ 5968 emit_insn (gen_frame_blockage ()); 5969 } 5970 else 5971 { 5972 rtx size_rtx = gen_rtx_REG (Pmode, 1); 5973 emit_move_insn (size_rtx, size_int_rtx); 5974 emit_window_save (size_rtx); 5975 } 5976 } 5977 5978 if (sparc_leaf_function_p) 5979 { 5980 sparc_frame_base_reg = stack_pointer_rtx; 5981 sparc_frame_base_offset = size + SPARC_STACK_BIAS; 5982 } 5983 else 5984 { 5985 sparc_frame_base_reg = hard_frame_pointer_rtx; 5986 sparc_frame_base_offset = SPARC_STACK_BIAS; 5987 } 5988 5989 if (sparc_n_global_fp_regs > 0) 5990 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg, 5991 sparc_frame_base_offset 5992 - sparc_apparent_frame_size, 5993 SORR_SAVE); 5994 5995 /* Load the GOT register if needed. */ 5996 if (crtl->uses_pic_offset_table) 5997 load_got_register (); 5998 5999 /* Advertise that the data calculated just above are now valid. */ 6000 sparc_prologue_data_valid_p = true; 6001 } 6002 6003 /* Expand the function prologue. The prologue is responsible for reserving 6004 storage for the frame, saving the call-saved registers and loading the 6005 GOT register if needed. */ 6006 6007 void 6008 sparc_flat_expand_prologue (void) 6009 { 6010 HOST_WIDE_INT size; 6011 rtx_insn *insn; 6012 6013 sparc_leaf_function_p = optimize > 0 && crtl->is_leaf; 6014 6015 size = sparc_compute_frame_size (get_frame_size(), sparc_leaf_function_p); 6016 6017 if (flag_stack_usage_info) 6018 current_function_static_stack_size = size; 6019 6020 if (flag_stack_check == STATIC_BUILTIN_STACK_CHECK) 6021 { 6022 if (crtl->is_leaf && !cfun->calls_alloca) 6023 { 6024 if (size > PROBE_INTERVAL && size > STACK_CHECK_PROTECT) 6025 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, 6026 size - STACK_CHECK_PROTECT); 6027 } 6028 else if (size > 0) 6029 sparc_emit_probe_stack_range (STACK_CHECK_PROTECT, size); 6030 } 6031 6032 if (sparc_save_local_in_regs_p) 6033 emit_save_or_restore_local_in_regs (stack_pointer_rtx, SPARC_STACK_BIAS, 6034 SORR_SAVE); 6035 6036 if (size == 0) 6037 ; /* do nothing. */ 6038 else 6039 { 6040 rtx size_int_rtx, size_rtx; 6041 6042 size_rtx = size_int_rtx = GEN_INT (-size); 6043 6044 /* We establish the frame (i.e. decrement the stack pointer) first, even 6045 if we use a frame pointer, because we cannot clobber any call-saved 6046 registers, including the frame pointer, if we haven't created a new 6047 register save area, for the sake of compatibility with the ABI. */ 6048 if (size <= 4096) 6049 insn = emit_insn (gen_stack_pointer_inc (size_int_rtx)); 6050 else if (size <= 8192 && !frame_pointer_needed) 6051 { 6052 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (-4096))); 6053 RTX_FRAME_RELATED_P (insn) = 1; 6054 insn = emit_insn (gen_stack_pointer_inc (GEN_INT (4096 - size))); 6055 } 6056 else 6057 { 6058 size_rtx = gen_rtx_REG (Pmode, 1); 6059 emit_move_insn (size_rtx, size_int_rtx); 6060 insn = emit_insn (gen_stack_pointer_inc (size_rtx)); 6061 add_reg_note (insn, REG_CFA_ADJUST_CFA, 6062 gen_stack_pointer_inc (size_int_rtx)); 6063 } 6064 RTX_FRAME_RELATED_P (insn) = 1; 6065 6066 /* Ensure nothing is scheduled until after the frame is established. */ 6067 emit_insn (gen_blockage ()); 6068 6069 if (frame_pointer_needed) 6070 { 6071 insn = emit_insn (gen_rtx_SET (hard_frame_pointer_rtx, 6072 gen_rtx_MINUS (Pmode, 6073 stack_pointer_rtx, 6074 size_rtx))); 6075 RTX_FRAME_RELATED_P (insn) = 1; 6076 6077 add_reg_note (insn, REG_CFA_ADJUST_CFA, 6078 gen_rtx_SET (hard_frame_pointer_rtx, 6079 plus_constant (Pmode, stack_pointer_rtx, 6080 size))); 6081 } 6082 6083 if (return_addr_reg_needed_p (sparc_leaf_function_p)) 6084 { 6085 rtx o7 = gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM); 6086 rtx i7 = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); 6087 6088 insn = emit_move_insn (i7, o7); 6089 RTX_FRAME_RELATED_P (insn) = 1; 6090 6091 add_reg_note (insn, REG_CFA_REGISTER, gen_rtx_SET (i7, o7)); 6092 6093 /* Prevent this instruction from ever being considered dead, 6094 even if this function has no epilogue. */ 6095 emit_use (i7); 6096 } 6097 } 6098 6099 if (frame_pointer_needed) 6100 { 6101 sparc_frame_base_reg = hard_frame_pointer_rtx; 6102 sparc_frame_base_offset = SPARC_STACK_BIAS; 6103 } 6104 else 6105 { 6106 sparc_frame_base_reg = stack_pointer_rtx; 6107 sparc_frame_base_offset = size + SPARC_STACK_BIAS; 6108 } 6109 6110 if (sparc_n_global_fp_regs > 0) 6111 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg, 6112 sparc_frame_base_offset 6113 - sparc_apparent_frame_size, 6114 SORR_SAVE); 6115 6116 /* Load the GOT register if needed. */ 6117 if (crtl->uses_pic_offset_table) 6118 load_got_register (); 6119 6120 /* Advertise that the data calculated just above are now valid. */ 6121 sparc_prologue_data_valid_p = true; 6122 } 6123 6124 /* This function generates the assembly code for function entry, which boils 6125 down to emitting the necessary .register directives. */ 6126 6127 static void 6128 sparc_asm_function_prologue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 6129 { 6130 /* Check that the assumption we made in sparc_expand_prologue is valid. */ 6131 if (!TARGET_FLAT) 6132 gcc_assert (sparc_leaf_function_p == crtl->uses_only_leaf_regs); 6133 6134 sparc_output_scratch_registers (file); 6135 } 6136 6137 /* Expand the function epilogue, either normal or part of a sibcall. 6138 We emit all the instructions except the return or the call. */ 6139 6140 void 6141 sparc_expand_epilogue (bool for_eh) 6142 { 6143 HOST_WIDE_INT size = sparc_frame_size; 6144 6145 if (cfun->calls_alloca) 6146 emit_insn (gen_frame_blockage ()); 6147 6148 if (sparc_n_global_fp_regs > 0) 6149 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg, 6150 sparc_frame_base_offset 6151 - sparc_apparent_frame_size, 6152 SORR_RESTORE); 6153 6154 if (size == 0 || for_eh) 6155 ; /* do nothing. */ 6156 else if (sparc_leaf_function_p) 6157 { 6158 if (size <= 4096) 6159 emit_insn (gen_stack_pointer_inc (GEN_INT (size))); 6160 else if (size <= 8192) 6161 { 6162 emit_insn (gen_stack_pointer_inc (GEN_INT (4096))); 6163 emit_insn (gen_stack_pointer_inc (GEN_INT (size - 4096))); 6164 } 6165 else 6166 { 6167 rtx reg = gen_rtx_REG (Pmode, 1); 6168 emit_move_insn (reg, GEN_INT (size)); 6169 emit_insn (gen_stack_pointer_inc (reg)); 6170 } 6171 } 6172 } 6173 6174 /* Expand the function epilogue, either normal or part of a sibcall. 6175 We emit all the instructions except the return or the call. */ 6176 6177 void 6178 sparc_flat_expand_epilogue (bool for_eh) 6179 { 6180 HOST_WIDE_INT size = sparc_frame_size; 6181 6182 if (sparc_n_global_fp_regs > 0) 6183 emit_save_or_restore_global_fp_regs (sparc_frame_base_reg, 6184 sparc_frame_base_offset 6185 - sparc_apparent_frame_size, 6186 SORR_RESTORE); 6187 6188 /* If we have a frame pointer, we'll need both to restore it before the 6189 frame is destroyed and use its current value in destroying the frame. 6190 Since we don't have an atomic way to do that in the flat window model, 6191 we save the current value into a temporary register (%g1). */ 6192 if (frame_pointer_needed && !for_eh) 6193 emit_move_insn (gen_rtx_REG (Pmode, 1), hard_frame_pointer_rtx); 6194 6195 if (return_addr_reg_needed_p (sparc_leaf_function_p)) 6196 emit_move_insn (gen_rtx_REG (Pmode, INCOMING_RETURN_ADDR_REGNUM), 6197 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM)); 6198 6199 if (sparc_save_local_in_regs_p) 6200 emit_save_or_restore_local_in_regs (sparc_frame_base_reg, 6201 sparc_frame_base_offset, 6202 SORR_RESTORE); 6203 6204 if (size == 0 || for_eh) 6205 ; /* do nothing. */ 6206 else if (frame_pointer_needed) 6207 { 6208 /* Make sure the frame is destroyed after everything else is done. */ 6209 emit_insn (gen_blockage ()); 6210 6211 emit_move_insn (stack_pointer_rtx, gen_rtx_REG (Pmode, 1)); 6212 } 6213 else 6214 { 6215 /* Likewise. */ 6216 emit_insn (gen_blockage ()); 6217 6218 if (size <= 4096) 6219 emit_insn (gen_stack_pointer_inc (GEN_INT (size))); 6220 else if (size <= 8192) 6221 { 6222 emit_insn (gen_stack_pointer_inc (GEN_INT (4096))); 6223 emit_insn (gen_stack_pointer_inc (GEN_INT (size - 4096))); 6224 } 6225 else 6226 { 6227 rtx reg = gen_rtx_REG (Pmode, 1); 6228 emit_move_insn (reg, GEN_INT (size)); 6229 emit_insn (gen_stack_pointer_inc (reg)); 6230 } 6231 } 6232 } 6233 6234 /* Return true if it is appropriate to emit `return' instructions in the 6235 body of a function. */ 6236 6237 bool 6238 sparc_can_use_return_insn_p (void) 6239 { 6240 return sparc_prologue_data_valid_p 6241 && sparc_n_global_fp_regs == 0 6242 && TARGET_FLAT 6243 ? (sparc_frame_size == 0 && !sparc_save_local_in_regs_p) 6244 : (sparc_frame_size == 0 || !sparc_leaf_function_p); 6245 } 6246 6247 /* This function generates the assembly code for function exit. */ 6248 6249 static void 6250 sparc_asm_function_epilogue (FILE *file, HOST_WIDE_INT size ATTRIBUTE_UNUSED) 6251 { 6252 /* If the last two instructions of a function are "call foo; dslot;" 6253 the return address might point to the first instruction in the next 6254 function and we have to output a dummy nop for the sake of sane 6255 backtraces in such cases. This is pointless for sibling calls since 6256 the return address is explicitly adjusted. */ 6257 6258 rtx_insn *insn = get_last_insn (); 6259 6260 rtx last_real_insn = prev_real_insn (insn); 6261 if (last_real_insn 6262 && NONJUMP_INSN_P (last_real_insn) 6263 && GET_CODE (PATTERN (last_real_insn)) == SEQUENCE) 6264 last_real_insn = XVECEXP (PATTERN (last_real_insn), 0, 0); 6265 6266 if (last_real_insn 6267 && CALL_P (last_real_insn) 6268 && !SIBLING_CALL_P (last_real_insn)) 6269 fputs("\tnop\n", file); 6270 6271 sparc_output_deferred_case_vectors (); 6272 } 6273 6274 /* Output a 'restore' instruction. */ 6275 6276 static void 6277 output_restore (rtx pat) 6278 { 6279 rtx operands[3]; 6280 6281 if (! pat) 6282 { 6283 fputs ("\t restore\n", asm_out_file); 6284 return; 6285 } 6286 6287 gcc_assert (GET_CODE (pat) == SET); 6288 6289 operands[0] = SET_DEST (pat); 6290 pat = SET_SRC (pat); 6291 6292 switch (GET_CODE (pat)) 6293 { 6294 case PLUS: 6295 operands[1] = XEXP (pat, 0); 6296 operands[2] = XEXP (pat, 1); 6297 output_asm_insn (" restore %r1, %2, %Y0", operands); 6298 break; 6299 case LO_SUM: 6300 operands[1] = XEXP (pat, 0); 6301 operands[2] = XEXP (pat, 1); 6302 output_asm_insn (" restore %r1, %%lo(%a2), %Y0", operands); 6303 break; 6304 case ASHIFT: 6305 operands[1] = XEXP (pat, 0); 6306 gcc_assert (XEXP (pat, 1) == const1_rtx); 6307 output_asm_insn (" restore %r1, %r1, %Y0", operands); 6308 break; 6309 default: 6310 operands[1] = pat; 6311 output_asm_insn (" restore %%g0, %1, %Y0", operands); 6312 break; 6313 } 6314 } 6315 6316 /* Output a return. */ 6317 6318 const char * 6319 output_return (rtx_insn *insn) 6320 { 6321 if (crtl->calls_eh_return) 6322 { 6323 /* If the function uses __builtin_eh_return, the eh_return 6324 machinery occupies the delay slot. */ 6325 gcc_assert (!final_sequence); 6326 6327 if (flag_delayed_branch) 6328 { 6329 if (!TARGET_FLAT && TARGET_V9) 6330 fputs ("\treturn\t%i7+8\n", asm_out_file); 6331 else 6332 { 6333 if (!TARGET_FLAT) 6334 fputs ("\trestore\n", asm_out_file); 6335 6336 fputs ("\tjmp\t%o7+8\n", asm_out_file); 6337 } 6338 6339 fputs ("\t add\t%sp, %g1, %sp\n", asm_out_file); 6340 } 6341 else 6342 { 6343 if (!TARGET_FLAT) 6344 fputs ("\trestore\n", asm_out_file); 6345 6346 fputs ("\tadd\t%sp, %g1, %sp\n", asm_out_file); 6347 fputs ("\tjmp\t%o7+8\n\t nop\n", asm_out_file); 6348 } 6349 } 6350 else if (sparc_leaf_function_p || TARGET_FLAT) 6351 { 6352 /* This is a leaf or flat function so we don't have to bother restoring 6353 the register window, which frees us from dealing with the convoluted 6354 semantics of restore/return. We simply output the jump to the 6355 return address and the insn in the delay slot (if any). */ 6356 6357 return "jmp\t%%o7+%)%#"; 6358 } 6359 else 6360 { 6361 /* This is a regular function so we have to restore the register window. 6362 We may have a pending insn for the delay slot, which will be either 6363 combined with the 'restore' instruction or put in the delay slot of 6364 the 'return' instruction. */ 6365 6366 if (final_sequence) 6367 { 6368 rtx delay, pat; 6369 6370 delay = NEXT_INSN (insn); 6371 gcc_assert (delay); 6372 6373 pat = PATTERN (delay); 6374 6375 if (TARGET_V9 && ! epilogue_renumber (&pat, 1)) 6376 { 6377 epilogue_renumber (&pat, 0); 6378 return "return\t%%i7+%)%#"; 6379 } 6380 else 6381 { 6382 output_asm_insn ("jmp\t%%i7+%)", NULL); 6383 output_restore (pat); 6384 PATTERN (delay) = gen_blockage (); 6385 INSN_CODE (delay) = -1; 6386 } 6387 } 6388 else 6389 { 6390 /* The delay slot is empty. */ 6391 if (TARGET_V9) 6392 return "return\t%%i7+%)\n\t nop"; 6393 else if (flag_delayed_branch) 6394 return "jmp\t%%i7+%)\n\t restore"; 6395 else 6396 return "restore\n\tjmp\t%%o7+%)\n\t nop"; 6397 } 6398 } 6399 6400 return ""; 6401 } 6402 6403 /* Output a sibling call. */ 6404 6405 const char * 6406 output_sibcall (rtx_insn *insn, rtx call_operand) 6407 { 6408 rtx operands[1]; 6409 6410 gcc_assert (flag_delayed_branch); 6411 6412 operands[0] = call_operand; 6413 6414 if (sparc_leaf_function_p || TARGET_FLAT) 6415 { 6416 /* This is a leaf or flat function so we don't have to bother restoring 6417 the register window. We simply output the jump to the function and 6418 the insn in the delay slot (if any). */ 6419 6420 gcc_assert (!(LEAF_SIBCALL_SLOT_RESERVED_P && final_sequence)); 6421 6422 if (final_sequence) 6423 output_asm_insn ("sethi\t%%hi(%a0), %%g1\n\tjmp\t%%g1 + %%lo(%a0)%#", 6424 operands); 6425 else 6426 /* Use or with rs2 %%g0 instead of mov, so that as/ld can optimize 6427 it into branch if possible. */ 6428 output_asm_insn ("or\t%%o7, %%g0, %%g1\n\tcall\t%a0, 0\n\t or\t%%g1, %%g0, %%o7", 6429 operands); 6430 } 6431 else 6432 { 6433 /* This is a regular function so we have to restore the register window. 6434 We may have a pending insn for the delay slot, which will be combined 6435 with the 'restore' instruction. */ 6436 6437 output_asm_insn ("call\t%a0, 0", operands); 6438 6439 if (final_sequence) 6440 { 6441 rtx_insn *delay = NEXT_INSN (insn); 6442 gcc_assert (delay); 6443 6444 output_restore (PATTERN (delay)); 6445 6446 PATTERN (delay) = gen_blockage (); 6447 INSN_CODE (delay) = -1; 6448 } 6449 else 6450 output_restore (NULL_RTX); 6451 } 6452 6453 return ""; 6454 } 6455 6456 /* Functions for handling argument passing. 6457 6458 For 32-bit, the first 6 args are normally in registers and the rest are 6459 pushed. Any arg that starts within the first 6 words is at least 6460 partially passed in a register unless its data type forbids. 6461 6462 For 64-bit, the argument registers are laid out as an array of 16 elements 6463 and arguments are added sequentially. The first 6 int args and up to the 6464 first 16 fp args (depending on size) are passed in regs. 6465 6466 Slot Stack Integral Float Float in structure Double Long Double 6467 ---- ----- -------- ----- ------------------ ------ ----------- 6468 15 [SP+248] %f31 %f30,%f31 %d30 6469 14 [SP+240] %f29 %f28,%f29 %d28 %q28 6470 13 [SP+232] %f27 %f26,%f27 %d26 6471 12 [SP+224] %f25 %f24,%f25 %d24 %q24 6472 11 [SP+216] %f23 %f22,%f23 %d22 6473 10 [SP+208] %f21 %f20,%f21 %d20 %q20 6474 9 [SP+200] %f19 %f18,%f19 %d18 6475 8 [SP+192] %f17 %f16,%f17 %d16 %q16 6476 7 [SP+184] %f15 %f14,%f15 %d14 6477 6 [SP+176] %f13 %f12,%f13 %d12 %q12 6478 5 [SP+168] %o5 %f11 %f10,%f11 %d10 6479 4 [SP+160] %o4 %f9 %f8,%f9 %d8 %q8 6480 3 [SP+152] %o3 %f7 %f6,%f7 %d6 6481 2 [SP+144] %o2 %f5 %f4,%f5 %d4 %q4 6482 1 [SP+136] %o1 %f3 %f2,%f3 %d2 6483 0 [SP+128] %o0 %f1 %f0,%f1 %d0 %q0 6484 6485 Here SP = %sp if -mno-stack-bias or %sp+stack_bias otherwise. 6486 6487 Integral arguments are always passed as 64-bit quantities appropriately 6488 extended. 6489 6490 Passing of floating point values is handled as follows. 6491 If a prototype is in scope: 6492 If the value is in a named argument (i.e. not a stdarg function or a 6493 value not part of the `...') then the value is passed in the appropriate 6494 fp reg. 6495 If the value is part of the `...' and is passed in one of the first 6 6496 slots then the value is passed in the appropriate int reg. 6497 If the value is part of the `...' and is not passed in one of the first 6 6498 slots then the value is passed in memory. 6499 If a prototype is not in scope: 6500 If the value is one of the first 6 arguments the value is passed in the 6501 appropriate integer reg and the appropriate fp reg. 6502 If the value is not one of the first 6 arguments the value is passed in 6503 the appropriate fp reg and in memory. 6504 6505 6506 Summary of the calling conventions implemented by GCC on the SPARC: 6507 6508 32-bit ABI: 6509 size argument return value 6510 6511 small integer <4 int. reg. int. reg. 6512 word 4 int. reg. int. reg. 6513 double word 8 int. reg. int. reg. 6514 6515 _Complex small integer <8 int. reg. int. reg. 6516 _Complex word 8 int. reg. int. reg. 6517 _Complex double word 16 memory int. reg. 6518 6519 vector integer <=8 int. reg. FP reg. 6520 vector integer >8 memory memory 6521 6522 float 4 int. reg. FP reg. 6523 double 8 int. reg. FP reg. 6524 long double 16 memory memory 6525 6526 _Complex float 8 memory FP reg. 6527 _Complex double 16 memory FP reg. 6528 _Complex long double 32 memory FP reg. 6529 6530 vector float any memory memory 6531 6532 aggregate any memory memory 6533 6534 6535 6536 64-bit ABI: 6537 size argument return value 6538 6539 small integer <8 int. reg. int. reg. 6540 word 8 int. reg. int. reg. 6541 double word 16 int. reg. int. reg. 6542 6543 _Complex small integer <16 int. reg. int. reg. 6544 _Complex word 16 int. reg. int. reg. 6545 _Complex double word 32 memory int. reg. 6546 6547 vector integer <=16 FP reg. FP reg. 6548 vector integer 16<s<=32 memory FP reg. 6549 vector integer >32 memory memory 6550 6551 float 4 FP reg. FP reg. 6552 double 8 FP reg. FP reg. 6553 long double 16 FP reg. FP reg. 6554 6555 _Complex float 8 FP reg. FP reg. 6556 _Complex double 16 FP reg. FP reg. 6557 _Complex long double 32 memory FP reg. 6558 6559 vector float <=16 FP reg. FP reg. 6560 vector float 16<s<=32 memory FP reg. 6561 vector float >32 memory memory 6562 6563 aggregate <=16 reg. reg. 6564 aggregate 16<s<=32 memory reg. 6565 aggregate >32 memory memory 6566 6567 6568 6569 Note #1: complex floating-point types follow the extended SPARC ABIs as 6570 implemented by the Sun compiler. 6571 6572 Note #2: integral vector types follow the scalar floating-point types 6573 conventions to match what is implemented by the Sun VIS SDK. 6574 6575 Note #3: floating-point vector types follow the aggregate types 6576 conventions. */ 6577 6578 6579 /* Maximum number of int regs for args. */ 6580 #define SPARC_INT_ARG_MAX 6 6581 /* Maximum number of fp regs for args. */ 6582 #define SPARC_FP_ARG_MAX 16 6583 /* Number of words (partially) occupied for a given size in units. */ 6584 #define CEIL_NWORDS(SIZE) CEIL((SIZE), UNITS_PER_WORD) 6585 6586 /* Handle the INIT_CUMULATIVE_ARGS macro. 6587 Initialize a variable CUM of type CUMULATIVE_ARGS 6588 for a call to a function whose data type is FNTYPE. 6589 For a library call, FNTYPE is 0. */ 6590 6591 void 6592 init_cumulative_args (struct sparc_args *cum, tree fntype, rtx, tree) 6593 { 6594 cum->words = 0; 6595 cum->prototype_p = fntype && prototype_p (fntype); 6596 cum->libcall_p = !fntype; 6597 } 6598 6599 /* Handle promotion of pointer and integer arguments. */ 6600 6601 static machine_mode 6602 sparc_promote_function_mode (const_tree type, machine_mode mode, 6603 int *punsignedp, const_tree, int) 6604 { 6605 if (type && POINTER_TYPE_P (type)) 6606 { 6607 *punsignedp = POINTERS_EXTEND_UNSIGNED; 6608 return Pmode; 6609 } 6610 6611 /* Integral arguments are passed as full words, as per the ABI. */ 6612 if (GET_MODE_CLASS (mode) == MODE_INT 6613 && GET_MODE_SIZE (mode) < UNITS_PER_WORD) 6614 return word_mode; 6615 6616 return mode; 6617 } 6618 6619 /* Handle the TARGET_STRICT_ARGUMENT_NAMING target hook. */ 6620 6621 static bool 6622 sparc_strict_argument_naming (cumulative_args_t ca ATTRIBUTE_UNUSED) 6623 { 6624 return TARGET_ARCH64 ? true : false; 6625 } 6626 6627 /* Traverse the record TYPE recursively and call FUNC on its fields. 6628 NAMED is true if this is for a named parameter. DATA is passed 6629 to FUNC for each field. OFFSET is the starting position and 6630 PACKED is true if we are inside a packed record. */ 6631 6632 template <typename T, void Func (const_tree, HOST_WIDE_INT, bool, T*)> 6633 static void 6634 traverse_record_type (const_tree type, bool named, T *data, 6635 HOST_WIDE_INT offset = 0, bool packed = false) 6636 { 6637 /* The ABI obviously doesn't specify how packed structures are passed. 6638 These are passed in integer regs if possible, otherwise memory. */ 6639 if (!packed) 6640 for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) 6641 if (TREE_CODE (field) == FIELD_DECL && DECL_PACKED (field)) 6642 { 6643 packed = true; 6644 break; 6645 } 6646 6647 /* Walk the real fields, but skip those with no size or a zero size. 6648 ??? Fields with variable offset are handled as having zero offset. */ 6649 for (tree field = TYPE_FIELDS (type); field; field = DECL_CHAIN (field)) 6650 if (TREE_CODE (field) == FIELD_DECL) 6651 { 6652 if (!DECL_SIZE (field) || integer_zerop (DECL_SIZE (field))) 6653 continue; 6654 6655 HOST_WIDE_INT bitpos = offset; 6656 if (TREE_CODE (DECL_FIELD_OFFSET (field)) == INTEGER_CST) 6657 bitpos += int_bit_position (field); 6658 6659 tree field_type = TREE_TYPE (field); 6660 if (TREE_CODE (field_type) == RECORD_TYPE) 6661 traverse_record_type<T, Func> (field_type, named, data, bitpos, 6662 packed); 6663 else 6664 { 6665 const bool fp_type 6666 = FLOAT_TYPE_P (field_type) || VECTOR_TYPE_P (field_type); 6667 Func (field, bitpos, fp_type && named && !packed && TARGET_FPU, 6668 data); 6669 } 6670 } 6671 } 6672 6673 /* Handle recursive register classifying for structure layout. */ 6674 6675 typedef struct 6676 { 6677 bool fp_regs; /* true if field eligible to FP registers. */ 6678 bool fp_regs_in_first_word; /* true if such field in first word. */ 6679 } classify_data_t; 6680 6681 /* A subroutine of function_arg_slotno. Classify the field. */ 6682 6683 inline void 6684 classify_registers (const_tree, HOST_WIDE_INT bitpos, bool fp, 6685 classify_data_t *data) 6686 { 6687 if (fp) 6688 { 6689 data->fp_regs = true; 6690 if (bitpos < BITS_PER_WORD) 6691 data->fp_regs_in_first_word = true; 6692 } 6693 } 6694 6695 /* Compute the slot number to pass an argument in. 6696 Return the slot number or -1 if passing on the stack. 6697 6698 CUM is a variable of type CUMULATIVE_ARGS which gives info about 6699 the preceding args and about the function being called. 6700 MODE is the argument's machine mode. 6701 TYPE is the data type of the argument (as a tree). 6702 This is null for libcalls where that information may 6703 not be available. 6704 NAMED is nonzero if this argument is a named parameter 6705 (otherwise it is an extra parameter matching an ellipsis). 6706 INCOMING is zero for FUNCTION_ARG, nonzero for FUNCTION_INCOMING_ARG. 6707 *PREGNO records the register number to use if scalar type. 6708 *PPADDING records the amount of padding needed in words. */ 6709 6710 static int 6711 function_arg_slotno (const struct sparc_args *cum, machine_mode mode, 6712 const_tree type, bool named, bool incoming, 6713 int *pregno, int *ppadding) 6714 { 6715 int regbase = (incoming 6716 ? SPARC_INCOMING_INT_ARG_FIRST 6717 : SPARC_OUTGOING_INT_ARG_FIRST); 6718 int slotno = cum->words; 6719 enum mode_class mclass; 6720 int regno; 6721 6722 *ppadding = 0; 6723 6724 if (type && TREE_ADDRESSABLE (type)) 6725 return -1; 6726 6727 if (TARGET_ARCH32 6728 && mode == BLKmode 6729 && type 6730 && TYPE_ALIGN (type) % PARM_BOUNDARY != 0) 6731 return -1; 6732 6733 /* For SPARC64, objects requiring 16-byte alignment get it. */ 6734 if (TARGET_ARCH64 6735 && (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) >= 128 6736 && (slotno & 1) != 0) 6737 slotno++, *ppadding = 1; 6738 6739 mclass = GET_MODE_CLASS (mode); 6740 if (type && TREE_CODE (type) == VECTOR_TYPE) 6741 { 6742 /* Vector types deserve special treatment because they are 6743 polymorphic wrt their mode, depending upon whether VIS 6744 instructions are enabled. */ 6745 if (TREE_CODE (TREE_TYPE (type)) == REAL_TYPE) 6746 { 6747 /* The SPARC port defines no floating-point vector modes. */ 6748 gcc_assert (mode == BLKmode); 6749 } 6750 else 6751 { 6752 /* Integral vector types should either have a vector 6753 mode or an integral mode, because we are guaranteed 6754 by pass_by_reference that their size is not greater 6755 than 16 bytes and TImode is 16-byte wide. */ 6756 gcc_assert (mode != BLKmode); 6757 6758 /* Vector integers are handled like floats according to 6759 the Sun VIS SDK. */ 6760 mclass = MODE_FLOAT; 6761 } 6762 } 6763 6764 switch (mclass) 6765 { 6766 case MODE_FLOAT: 6767 case MODE_COMPLEX_FLOAT: 6768 case MODE_VECTOR_INT: 6769 if (TARGET_ARCH64 && TARGET_FPU && named) 6770 { 6771 /* If all arg slots are filled, then must pass on stack. */ 6772 if (slotno >= SPARC_FP_ARG_MAX) 6773 return -1; 6774 6775 regno = SPARC_FP_ARG_FIRST + slotno * 2; 6776 /* Arguments filling only one single FP register are 6777 right-justified in the outer double FP register. */ 6778 if (GET_MODE_SIZE (mode) <= 4) 6779 regno++; 6780 break; 6781 } 6782 /* fallthrough */ 6783 6784 case MODE_INT: 6785 case MODE_COMPLEX_INT: 6786 /* If all arg slots are filled, then must pass on stack. */ 6787 if (slotno >= SPARC_INT_ARG_MAX) 6788 return -1; 6789 6790 regno = regbase + slotno; 6791 break; 6792 6793 case MODE_RANDOM: 6794 if (mode == VOIDmode) 6795 /* MODE is VOIDmode when generating the actual call. */ 6796 return -1; 6797 6798 gcc_assert (mode == BLKmode); 6799 6800 if (TARGET_ARCH32 6801 || !type 6802 || (TREE_CODE (type) != RECORD_TYPE 6803 && TREE_CODE (type) != VECTOR_TYPE)) 6804 { 6805 /* If all arg slots are filled, then must pass on stack. */ 6806 if (slotno >= SPARC_INT_ARG_MAX) 6807 return -1; 6808 6809 regno = regbase + slotno; 6810 } 6811 else /* TARGET_ARCH64 && type */ 6812 { 6813 /* If all arg slots are filled, then must pass on stack. */ 6814 if (slotno >= SPARC_FP_ARG_MAX) 6815 return -1; 6816 6817 if (TREE_CODE (type) == RECORD_TYPE) 6818 { 6819 classify_data_t data = { false, false }; 6820 traverse_record_type<classify_data_t, classify_registers> 6821 (type, named, &data); 6822 6823 if (data.fp_regs) 6824 { 6825 /* If all FP slots are filled except for the last one and 6826 there is no FP field in the first word, then must pass 6827 on stack. */ 6828 if (slotno >= SPARC_FP_ARG_MAX - 1 6829 && !data.fp_regs_in_first_word) 6830 return -1; 6831 } 6832 else 6833 { 6834 /* If all int slots are filled, then must pass on stack. */ 6835 if (slotno >= SPARC_INT_ARG_MAX) 6836 return -1; 6837 } 6838 } 6839 6840 /* PREGNO isn't set since both int and FP regs can be used. */ 6841 return slotno; 6842 } 6843 break; 6844 6845 default : 6846 gcc_unreachable (); 6847 } 6848 6849 *pregno = regno; 6850 return slotno; 6851 } 6852 6853 /* Handle recursive register counting/assigning for structure layout. */ 6854 6855 typedef struct 6856 { 6857 int slotno; /* slot number of the argument. */ 6858 int regbase; /* regno of the base register. */ 6859 int intoffset; /* offset of the first pending integer field. */ 6860 int nregs; /* number of words passed in registers. */ 6861 bool stack; /* true if part of the argument is on the stack. */ 6862 rtx ret; /* return expression being built. */ 6863 } assign_data_t; 6864 6865 /* A subroutine of function_arg_record_value. Compute the number of integer 6866 registers to be assigned between PARMS->intoffset and BITPOS. Return 6867 true if at least one integer register is assigned or false otherwise. */ 6868 6869 static bool 6870 compute_int_layout (HOST_WIDE_INT bitpos, assign_data_t *data, int *pnregs) 6871 { 6872 if (data->intoffset < 0) 6873 return false; 6874 6875 const int intoffset = data->intoffset; 6876 data->intoffset = -1; 6877 6878 const int this_slotno = data->slotno + intoffset / BITS_PER_WORD; 6879 const unsigned int startbit = ROUND_DOWN (intoffset, BITS_PER_WORD); 6880 const unsigned int endbit = ROUND_UP (bitpos, BITS_PER_WORD); 6881 int nregs = (endbit - startbit) / BITS_PER_WORD; 6882 6883 if (nregs > 0 && nregs > SPARC_INT_ARG_MAX - this_slotno) 6884 { 6885 nregs = SPARC_INT_ARG_MAX - this_slotno; 6886 6887 /* We need to pass this field (partly) on the stack. */ 6888 data->stack = 1; 6889 } 6890 6891 if (nregs <= 0) 6892 return false; 6893 6894 *pnregs = nregs; 6895 return true; 6896 } 6897 6898 /* A subroutine of function_arg_record_value. Compute the number and the mode 6899 of the FP registers to be assigned for FIELD. Return true if at least one 6900 FP register is assigned or false otherwise. */ 6901 6902 static bool 6903 compute_fp_layout (const_tree field, HOST_WIDE_INT bitpos, 6904 assign_data_t *data, 6905 int *pnregs, machine_mode *pmode) 6906 { 6907 const int this_slotno = data->slotno + bitpos / BITS_PER_WORD; 6908 machine_mode mode = DECL_MODE (field); 6909 int nregs, nslots; 6910 6911 /* Slots are counted as words while regs are counted as having the size of 6912 the (inner) mode. */ 6913 if (TREE_CODE (TREE_TYPE (field)) == VECTOR_TYPE && mode == BLKmode) 6914 { 6915 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field))); 6916 nregs = TYPE_VECTOR_SUBPARTS (TREE_TYPE (field)); 6917 } 6918 else if (TREE_CODE (TREE_TYPE (field)) == COMPLEX_TYPE) 6919 { 6920 mode = TYPE_MODE (TREE_TYPE (TREE_TYPE (field))); 6921 nregs = 2; 6922 } 6923 else 6924 nregs = 1; 6925 6926 nslots = CEIL_NWORDS (nregs * GET_MODE_SIZE (mode)); 6927 6928 if (nslots > SPARC_FP_ARG_MAX - this_slotno) 6929 { 6930 nslots = SPARC_FP_ARG_MAX - this_slotno; 6931 nregs = (nslots * UNITS_PER_WORD) / GET_MODE_SIZE (mode); 6932 6933 /* We need to pass this field (partly) on the stack. */ 6934 data->stack = 1; 6935 6936 if (nregs <= 0) 6937 return false; 6938 } 6939 6940 *pnregs = nregs; 6941 *pmode = mode; 6942 return true; 6943 } 6944 6945 /* A subroutine of function_arg_record_value. Count the number of registers 6946 to be assigned for FIELD and between PARMS->intoffset and BITPOS. */ 6947 6948 inline void 6949 count_registers (const_tree field, HOST_WIDE_INT bitpos, bool fp, 6950 assign_data_t *data) 6951 { 6952 if (fp) 6953 { 6954 int nregs; 6955 machine_mode mode; 6956 6957 if (compute_int_layout (bitpos, data, &nregs)) 6958 data->nregs += nregs; 6959 6960 if (compute_fp_layout (field, bitpos, data, &nregs, &mode)) 6961 data->nregs += nregs; 6962 } 6963 else 6964 { 6965 if (data->intoffset < 0) 6966 data->intoffset = bitpos; 6967 } 6968 } 6969 6970 /* A subroutine of function_arg_record_value. Assign the bits of the 6971 structure between PARMS->intoffset and BITPOS to integer registers. */ 6972 6973 static void 6974 assign_int_registers (HOST_WIDE_INT bitpos, assign_data_t *data) 6975 { 6976 int intoffset = data->intoffset; 6977 machine_mode mode; 6978 int nregs; 6979 6980 if (!compute_int_layout (bitpos, data, &nregs)) 6981 return; 6982 6983 /* If this is the trailing part of a word, only load that much into 6984 the register. Otherwise load the whole register. Note that in 6985 the latter case we may pick up unwanted bits. It's not a problem 6986 at the moment but may wish to revisit. */ 6987 if (intoffset % BITS_PER_WORD != 0) 6988 mode = smallest_mode_for_size (BITS_PER_WORD - intoffset % BITS_PER_WORD, 6989 MODE_INT); 6990 else 6991 mode = word_mode; 6992 6993 const int this_slotno = data->slotno + intoffset / BITS_PER_WORD; 6994 unsigned int regno = data->regbase + this_slotno; 6995 intoffset /= BITS_PER_UNIT; 6996 6997 do 6998 { 6999 rtx reg = gen_rtx_REG (mode, regno); 7000 XVECEXP (data->ret, 0, data->stack + data->nregs) 7001 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (intoffset)); 7002 data->nregs += 1; 7003 mode = word_mode; 7004 regno += 1; 7005 intoffset = (intoffset | (UNITS_PER_WORD - 1)) + 1; 7006 } 7007 while (--nregs > 0); 7008 } 7009 7010 /* A subroutine of function_arg_record_value. Assign FIELD at position 7011 BITPOS to FP registers. */ 7012 7013 static void 7014 assign_fp_registers (const_tree field, HOST_WIDE_INT bitpos, 7015 assign_data_t *data) 7016 { 7017 int nregs; 7018 machine_mode mode; 7019 7020 if (!compute_fp_layout (field, bitpos, data, &nregs, &mode)) 7021 return; 7022 7023 const int this_slotno = data->slotno + bitpos / BITS_PER_WORD; 7024 int regno = SPARC_FP_ARG_FIRST + this_slotno * 2; 7025 if (GET_MODE_SIZE (mode) <= 4 && (bitpos & 32) != 0) 7026 regno++; 7027 int pos = bitpos / BITS_PER_UNIT; 7028 7029 do 7030 { 7031 rtx reg = gen_rtx_REG (mode, regno); 7032 XVECEXP (data->ret, 0, data->stack + data->nregs) 7033 = gen_rtx_EXPR_LIST (VOIDmode, reg, GEN_INT (pos)); 7034 data->nregs += 1; 7035 regno += GET_MODE_SIZE (mode) / 4; 7036 pos += GET_MODE_SIZE (mode); 7037 } 7038 while (--nregs > 0); 7039 } 7040 7041 /* A subroutine of function_arg_record_value. Assign FIELD and the bits of 7042 the structure between PARMS->intoffset and BITPOS to registers. */ 7043 7044 inline void 7045 assign_registers (const_tree field, HOST_WIDE_INT bitpos, bool fp, 7046 assign_data_t *data) 7047 { 7048 if (fp) 7049 { 7050 assign_int_registers (bitpos, data); 7051 7052 assign_fp_registers (field, bitpos, data); 7053 } 7054 else 7055 { 7056 if (data->intoffset < 0) 7057 data->intoffset = bitpos; 7058 } 7059 } 7060 7061 /* Used by function_arg and sparc_function_value_1 to implement the complex 7062 conventions of the 64-bit ABI for passing and returning structures. 7063 Return an expression valid as a return value for the FUNCTION_ARG 7064 and TARGET_FUNCTION_VALUE. 7065 7066 TYPE is the data type of the argument (as a tree). 7067 This is null for libcalls where that information may 7068 not be available. 7069 MODE is the argument's machine mode. 7070 SLOTNO is the index number of the argument's slot in the parameter array. 7071 NAMED is true if this argument is a named parameter 7072 (otherwise it is an extra parameter matching an ellipsis). 7073 REGBASE is the regno of the base register for the parameter array. */ 7074 7075 static rtx 7076 function_arg_record_value (const_tree type, machine_mode mode, 7077 int slotno, bool named, int regbase) 7078 { 7079 HOST_WIDE_INT typesize = int_size_in_bytes (type); 7080 assign_data_t data; 7081 int nregs; 7082 7083 data.slotno = slotno; 7084 data.regbase = regbase; 7085 7086 /* Count how many registers we need. */ 7087 data.nregs = 0; 7088 data.intoffset = 0; 7089 data.stack = false; 7090 traverse_record_type<assign_data_t, count_registers> (type, named, &data); 7091 7092 /* Take into account pending integer fields. */ 7093 if (compute_int_layout (typesize * BITS_PER_UNIT, &data, &nregs)) 7094 data.nregs += nregs; 7095 7096 /* Allocate the vector and handle some annoying special cases. */ 7097 nregs = data.nregs; 7098 7099 if (nregs == 0) 7100 { 7101 /* ??? Empty structure has no value? Duh? */ 7102 if (typesize <= 0) 7103 { 7104 /* Though there's nothing really to store, return a word register 7105 anyway so the rest of gcc doesn't go nuts. Returning a PARALLEL 7106 leads to breakage due to the fact that there are zero bytes to 7107 load. */ 7108 return gen_rtx_REG (mode, regbase); 7109 } 7110 7111 /* ??? C++ has structures with no fields, and yet a size. Give up 7112 for now and pass everything back in integer registers. */ 7113 nregs = (typesize + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 7114 if (nregs + slotno > SPARC_INT_ARG_MAX) 7115 nregs = SPARC_INT_ARG_MAX - slotno; 7116 } 7117 7118 gcc_assert (nregs > 0); 7119 7120 data.ret = gen_rtx_PARALLEL (mode, rtvec_alloc (data.stack + nregs)); 7121 7122 /* If at least one field must be passed on the stack, generate 7123 (parallel [(expr_list (nil) ...) ...]) so that all fields will 7124 also be passed on the stack. We can't do much better because the 7125 semantics of TARGET_ARG_PARTIAL_BYTES doesn't handle the case 7126 of structures for which the fields passed exclusively in registers 7127 are not at the beginning of the structure. */ 7128 if (data.stack) 7129 XVECEXP (data.ret, 0, 0) 7130 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 7131 7132 /* Assign the registers. */ 7133 data.nregs = 0; 7134 data.intoffset = 0; 7135 traverse_record_type<assign_data_t, assign_registers> (type, named, &data); 7136 7137 /* Assign pending integer fields. */ 7138 assign_int_registers (typesize * BITS_PER_UNIT, &data); 7139 7140 gcc_assert (data.nregs == nregs); 7141 7142 return data.ret; 7143 } 7144 7145 /* Used by function_arg and sparc_function_value_1 to implement the conventions 7146 of the 64-bit ABI for passing and returning unions. 7147 Return an expression valid as a return value for the FUNCTION_ARG 7148 and TARGET_FUNCTION_VALUE. 7149 7150 SIZE is the size in bytes of the union. 7151 MODE is the argument's machine mode. 7152 REGNO is the hard register the union will be passed in. */ 7153 7154 static rtx 7155 function_arg_union_value (int size, machine_mode mode, int slotno, 7156 int regno) 7157 { 7158 int nwords = CEIL_NWORDS (size), i; 7159 rtx regs; 7160 7161 /* See comment in previous function for empty structures. */ 7162 if (nwords == 0) 7163 return gen_rtx_REG (mode, regno); 7164 7165 if (slotno == SPARC_INT_ARG_MAX - 1) 7166 nwords = 1; 7167 7168 regs = gen_rtx_PARALLEL (mode, rtvec_alloc (nwords)); 7169 7170 for (i = 0; i < nwords; i++) 7171 { 7172 /* Unions are passed left-justified. */ 7173 XVECEXP (regs, 0, i) 7174 = gen_rtx_EXPR_LIST (VOIDmode, 7175 gen_rtx_REG (word_mode, regno), 7176 GEN_INT (UNITS_PER_WORD * i)); 7177 regno++; 7178 } 7179 7180 return regs; 7181 } 7182 7183 /* Used by function_arg and sparc_function_value_1 to implement the conventions 7184 for passing and returning BLKmode vectors. 7185 Return an expression valid as a return value for the FUNCTION_ARG 7186 and TARGET_FUNCTION_VALUE. 7187 7188 SIZE is the size in bytes of the vector. 7189 REGNO is the FP hard register the vector will be passed in. */ 7190 7191 static rtx 7192 function_arg_vector_value (int size, int regno) 7193 { 7194 const int nregs = MAX (1, size / 8); 7195 rtx regs = gen_rtx_PARALLEL (BLKmode, rtvec_alloc (nregs)); 7196 7197 if (size < 8) 7198 XVECEXP (regs, 0, 0) 7199 = gen_rtx_EXPR_LIST (VOIDmode, 7200 gen_rtx_REG (SImode, regno), 7201 const0_rtx); 7202 else 7203 for (int i = 0; i < nregs; i++) 7204 XVECEXP (regs, 0, i) 7205 = gen_rtx_EXPR_LIST (VOIDmode, 7206 gen_rtx_REG (DImode, regno + 2*i), 7207 GEN_INT (i*8)); 7208 7209 return regs; 7210 } 7211 7212 /* Determine where to put an argument to a function. 7213 Value is zero to push the argument on the stack, 7214 or a hard register in which to store the argument. 7215 7216 CUM is a variable of type CUMULATIVE_ARGS which gives info about 7217 the preceding args and about the function being called. 7218 MODE is the argument's machine mode. 7219 TYPE is the data type of the argument (as a tree). 7220 This is null for libcalls where that information may 7221 not be available. 7222 NAMED is true if this argument is a named parameter 7223 (otherwise it is an extra parameter matching an ellipsis). 7224 INCOMING_P is false for TARGET_FUNCTION_ARG, true for 7225 TARGET_FUNCTION_INCOMING_ARG. */ 7226 7227 static rtx 7228 sparc_function_arg_1 (cumulative_args_t cum_v, machine_mode mode, 7229 const_tree type, bool named, bool incoming) 7230 { 7231 const CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 7232 7233 int regbase = (incoming 7234 ? SPARC_INCOMING_INT_ARG_FIRST 7235 : SPARC_OUTGOING_INT_ARG_FIRST); 7236 int slotno, regno, padding; 7237 enum mode_class mclass = GET_MODE_CLASS (mode); 7238 7239 slotno = function_arg_slotno (cum, mode, type, named, incoming, 7240 ®no, &padding); 7241 if (slotno == -1) 7242 return 0; 7243 7244 /* Vector types deserve special treatment because they are polymorphic wrt 7245 their mode, depending upon whether VIS instructions are enabled. */ 7246 if (type && TREE_CODE (type) == VECTOR_TYPE) 7247 { 7248 HOST_WIDE_INT size = int_size_in_bytes (type); 7249 gcc_assert ((TARGET_ARCH32 && size <= 8) 7250 || (TARGET_ARCH64 && size <= 16)); 7251 7252 if (mode == BLKmode) 7253 return function_arg_vector_value (size, SPARC_FP_ARG_FIRST + 2*slotno); 7254 7255 mclass = MODE_FLOAT; 7256 } 7257 7258 if (TARGET_ARCH32) 7259 return gen_rtx_REG (mode, regno); 7260 7261 /* Structures up to 16 bytes in size are passed in arg slots on the stack 7262 and are promoted to registers if possible. */ 7263 if (type && TREE_CODE (type) == RECORD_TYPE) 7264 { 7265 HOST_WIDE_INT size = int_size_in_bytes (type); 7266 gcc_assert (size <= 16); 7267 7268 return function_arg_record_value (type, mode, slotno, named, regbase); 7269 } 7270 7271 /* Unions up to 16 bytes in size are passed in integer registers. */ 7272 else if (type && TREE_CODE (type) == UNION_TYPE) 7273 { 7274 HOST_WIDE_INT size = int_size_in_bytes (type); 7275 gcc_assert (size <= 16); 7276 7277 return function_arg_union_value (size, mode, slotno, regno); 7278 } 7279 7280 /* v9 fp args in reg slots beyond the int reg slots get passed in regs 7281 but also have the slot allocated for them. 7282 If no prototype is in scope fp values in register slots get passed 7283 in two places, either fp regs and int regs or fp regs and memory. */ 7284 else if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) 7285 && SPARC_FP_REG_P (regno)) 7286 { 7287 rtx reg = gen_rtx_REG (mode, regno); 7288 if (cum->prototype_p || cum->libcall_p) 7289 return reg; 7290 else 7291 { 7292 rtx v0, v1; 7293 7294 if ((regno - SPARC_FP_ARG_FIRST) < SPARC_INT_ARG_MAX * 2) 7295 { 7296 int intreg; 7297 7298 /* On incoming, we don't need to know that the value 7299 is passed in %f0 and %i0, and it confuses other parts 7300 causing needless spillage even on the simplest cases. */ 7301 if (incoming) 7302 return reg; 7303 7304 intreg = (SPARC_OUTGOING_INT_ARG_FIRST 7305 + (regno - SPARC_FP_ARG_FIRST) / 2); 7306 7307 v0 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 7308 v1 = gen_rtx_EXPR_LIST (VOIDmode, gen_rtx_REG (mode, intreg), 7309 const0_rtx); 7310 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 7311 } 7312 else 7313 { 7314 v0 = gen_rtx_EXPR_LIST (VOIDmode, NULL_RTX, const0_rtx); 7315 v1 = gen_rtx_EXPR_LIST (VOIDmode, reg, const0_rtx); 7316 return gen_rtx_PARALLEL (mode, gen_rtvec (2, v0, v1)); 7317 } 7318 } 7319 } 7320 7321 /* All other aggregate types are passed in an integer register in a mode 7322 corresponding to the size of the type. */ 7323 else if (type && AGGREGATE_TYPE_P (type)) 7324 { 7325 HOST_WIDE_INT size = int_size_in_bytes (type); 7326 gcc_assert (size <= 16); 7327 7328 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); 7329 } 7330 7331 return gen_rtx_REG (mode, regno); 7332 } 7333 7334 /* Handle the TARGET_FUNCTION_ARG target hook. */ 7335 7336 static rtx 7337 sparc_function_arg (cumulative_args_t cum, machine_mode mode, 7338 const_tree type, bool named) 7339 { 7340 return sparc_function_arg_1 (cum, mode, type, named, false); 7341 } 7342 7343 /* Handle the TARGET_FUNCTION_INCOMING_ARG target hook. */ 7344 7345 static rtx 7346 sparc_function_incoming_arg (cumulative_args_t cum, machine_mode mode, 7347 const_tree type, bool named) 7348 { 7349 return sparc_function_arg_1 (cum, mode, type, named, true); 7350 } 7351 7352 /* For sparc64, objects requiring 16 byte alignment are passed that way. */ 7353 7354 static unsigned int 7355 sparc_function_arg_boundary (machine_mode mode, const_tree type) 7356 { 7357 return ((TARGET_ARCH64 7358 && (GET_MODE_ALIGNMENT (mode) == 128 7359 || (type && TYPE_ALIGN (type) == 128))) 7360 ? 128 7361 : PARM_BOUNDARY); 7362 } 7363 7364 /* For an arg passed partly in registers and partly in memory, 7365 this is the number of bytes of registers used. 7366 For args passed entirely in registers or entirely in memory, zero. 7367 7368 Any arg that starts in the first 6 regs but won't entirely fit in them 7369 needs partial registers on v8. On v9, structures with integer 7370 values in arg slots 5,6 will be passed in %o5 and SP+176, and complex fp 7371 values that begin in the last fp reg [where "last fp reg" varies with the 7372 mode] will be split between that reg and memory. */ 7373 7374 static int 7375 sparc_arg_partial_bytes (cumulative_args_t cum, machine_mode mode, 7376 tree type, bool named) 7377 { 7378 int slotno, regno, padding; 7379 7380 /* We pass false for incoming here, it doesn't matter. */ 7381 slotno = function_arg_slotno (get_cumulative_args (cum), mode, type, named, 7382 false, ®no, &padding); 7383 7384 if (slotno == -1) 7385 return 0; 7386 7387 if (TARGET_ARCH32) 7388 { 7389 if ((slotno + (mode == BLKmode 7390 ? CEIL_NWORDS (int_size_in_bytes (type)) 7391 : CEIL_NWORDS (GET_MODE_SIZE (mode)))) 7392 > SPARC_INT_ARG_MAX) 7393 return (SPARC_INT_ARG_MAX - slotno) * UNITS_PER_WORD; 7394 } 7395 else 7396 { 7397 /* We are guaranteed by pass_by_reference that the size of the 7398 argument is not greater than 16 bytes, so we only need to return 7399 one word if the argument is partially passed in registers. */ 7400 7401 if (type && AGGREGATE_TYPE_P (type)) 7402 { 7403 int size = int_size_in_bytes (type); 7404 7405 if (size > UNITS_PER_WORD 7406 && (slotno == SPARC_INT_ARG_MAX - 1 7407 || slotno == SPARC_FP_ARG_MAX - 1)) 7408 return UNITS_PER_WORD; 7409 } 7410 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_INT 7411 || (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT 7412 && ! (TARGET_FPU && named))) 7413 { 7414 /* The complex types are passed as packed types. */ 7415 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 7416 && slotno == SPARC_INT_ARG_MAX - 1) 7417 return UNITS_PER_WORD; 7418 } 7419 else if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 7420 { 7421 if ((slotno + GET_MODE_SIZE (mode) / UNITS_PER_WORD) 7422 > SPARC_FP_ARG_MAX) 7423 return UNITS_PER_WORD; 7424 } 7425 } 7426 7427 return 0; 7428 } 7429 7430 /* Handle the TARGET_PASS_BY_REFERENCE target hook. 7431 Specify whether to pass the argument by reference. */ 7432 7433 static bool 7434 sparc_pass_by_reference (cumulative_args_t cum ATTRIBUTE_UNUSED, 7435 machine_mode mode, const_tree type, 7436 bool named ATTRIBUTE_UNUSED) 7437 { 7438 if (TARGET_ARCH32) 7439 /* Original SPARC 32-bit ABI says that structures and unions, 7440 and quad-precision floats are passed by reference. For Pascal, 7441 also pass arrays by reference. All other base types are passed 7442 in registers. 7443 7444 Extended ABI (as implemented by the Sun compiler) says that all 7445 complex floats are passed by reference. Pass complex integers 7446 in registers up to 8 bytes. More generally, enforce the 2-word 7447 cap for passing arguments in registers. 7448 7449 Vector ABI (as implemented by the Sun VIS SDK) says that vector 7450 integers are passed like floats of the same size, that is in 7451 registers up to 8 bytes. Pass all vector floats by reference 7452 like structure and unions. */ 7453 return ((type && (AGGREGATE_TYPE_P (type) || VECTOR_FLOAT_TYPE_P (type))) 7454 || mode == SCmode 7455 /* Catch CDImode, TFmode, DCmode and TCmode. */ 7456 || GET_MODE_SIZE (mode) > 8 7457 || (type 7458 && TREE_CODE (type) == VECTOR_TYPE 7459 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)); 7460 else 7461 /* Original SPARC 64-bit ABI says that structures and unions 7462 smaller than 16 bytes are passed in registers, as well as 7463 all other base types. 7464 7465 Extended ABI (as implemented by the Sun compiler) says that 7466 complex floats are passed in registers up to 16 bytes. Pass 7467 all complex integers in registers up to 16 bytes. More generally, 7468 enforce the 2-word cap for passing arguments in registers. 7469 7470 Vector ABI (as implemented by the Sun VIS SDK) says that vector 7471 integers are passed like floats of the same size, that is in 7472 registers (up to 16 bytes). Pass all vector floats like structure 7473 and unions. */ 7474 return ((type 7475 && (AGGREGATE_TYPE_P (type) || TREE_CODE (type) == VECTOR_TYPE) 7476 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 16) 7477 /* Catch CTImode and TCmode. */ 7478 || GET_MODE_SIZE (mode) > 16); 7479 } 7480 7481 /* Handle the TARGET_FUNCTION_ARG_ADVANCE hook. 7482 Update the data in CUM to advance over an argument 7483 of mode MODE and data type TYPE. 7484 TYPE is null for libcalls where that information may not be available. */ 7485 7486 static void 7487 sparc_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, 7488 const_tree type, bool named) 7489 { 7490 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 7491 int regno, padding; 7492 7493 /* We pass false for incoming here, it doesn't matter. */ 7494 function_arg_slotno (cum, mode, type, named, false, ®no, &padding); 7495 7496 /* If argument requires leading padding, add it. */ 7497 cum->words += padding; 7498 7499 if (TARGET_ARCH32) 7500 cum->words += (mode == BLKmode 7501 ? CEIL_NWORDS (int_size_in_bytes (type)) 7502 : CEIL_NWORDS (GET_MODE_SIZE (mode))); 7503 else 7504 { 7505 if (type && AGGREGATE_TYPE_P (type)) 7506 { 7507 int size = int_size_in_bytes (type); 7508 7509 if (size <= 8) 7510 ++cum->words; 7511 else if (size <= 16) 7512 cum->words += 2; 7513 else /* passed by reference */ 7514 ++cum->words; 7515 } 7516 else 7517 cum->words += (mode == BLKmode 7518 ? CEIL_NWORDS (int_size_in_bytes (type)) 7519 : CEIL_NWORDS (GET_MODE_SIZE (mode))); 7520 } 7521 } 7522 7523 /* Handle the FUNCTION_ARG_PADDING macro. 7524 For the 64-bit ABI structs are always stored left shifted in their 7525 argument slot. */ 7526 7527 enum direction 7528 function_arg_padding (machine_mode mode, const_tree type) 7529 { 7530 if (TARGET_ARCH64 && type && AGGREGATE_TYPE_P (type)) 7531 return upward; 7532 7533 /* Fall back to the default. */ 7534 return DEFAULT_FUNCTION_ARG_PADDING (mode, type); 7535 } 7536 7537 /* Handle the TARGET_RETURN_IN_MEMORY target hook. 7538 Specify whether to return the return value in memory. */ 7539 7540 static bool 7541 sparc_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 7542 { 7543 if (TARGET_ARCH32) 7544 /* Original SPARC 32-bit ABI says that structures and unions, 7545 and quad-precision floats are returned in memory. All other 7546 base types are returned in registers. 7547 7548 Extended ABI (as implemented by the Sun compiler) says that 7549 all complex floats are returned in registers (8 FP registers 7550 at most for '_Complex long double'). Return all complex integers 7551 in registers (4 at most for '_Complex long long'). 7552 7553 Vector ABI (as implemented by the Sun VIS SDK) says that vector 7554 integers are returned like floats of the same size, that is in 7555 registers up to 8 bytes and in memory otherwise. Return all 7556 vector floats in memory like structure and unions; note that 7557 they always have BLKmode like the latter. */ 7558 return (TYPE_MODE (type) == BLKmode 7559 || TYPE_MODE (type) == TFmode 7560 || (TREE_CODE (type) == VECTOR_TYPE 7561 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 8)); 7562 else 7563 /* Original SPARC 64-bit ABI says that structures and unions 7564 smaller than 32 bytes are returned in registers, as well as 7565 all other base types. 7566 7567 Extended ABI (as implemented by the Sun compiler) says that all 7568 complex floats are returned in registers (8 FP registers at most 7569 for '_Complex long double'). Return all complex integers in 7570 registers (4 at most for '_Complex TItype'). 7571 7572 Vector ABI (as implemented by the Sun VIS SDK) says that vector 7573 integers are returned like floats of the same size, that is in 7574 registers. Return all vector floats like structure and unions; 7575 note that they always have BLKmode like the latter. */ 7576 return (TYPE_MODE (type) == BLKmode 7577 && (unsigned HOST_WIDE_INT) int_size_in_bytes (type) > 32); 7578 } 7579 7580 /* Handle the TARGET_STRUCT_VALUE target hook. 7581 Return where to find the structure return value address. */ 7582 7583 static rtx 7584 sparc_struct_value_rtx (tree fndecl, int incoming) 7585 { 7586 if (TARGET_ARCH64) 7587 return 0; 7588 else 7589 { 7590 rtx mem; 7591 7592 if (incoming) 7593 mem = gen_frame_mem (Pmode, plus_constant (Pmode, frame_pointer_rtx, 7594 STRUCT_VALUE_OFFSET)); 7595 else 7596 mem = gen_frame_mem (Pmode, plus_constant (Pmode, stack_pointer_rtx, 7597 STRUCT_VALUE_OFFSET)); 7598 7599 /* Only follow the SPARC ABI for fixed-size structure returns. 7600 Variable size structure returns are handled per the normal 7601 procedures in GCC. This is enabled by -mstd-struct-return */ 7602 if (incoming == 2 7603 && sparc_std_struct_return 7604 && TYPE_SIZE_UNIT (TREE_TYPE (fndecl)) 7605 && TREE_CODE (TYPE_SIZE_UNIT (TREE_TYPE (fndecl))) == INTEGER_CST) 7606 { 7607 /* We must check and adjust the return address, as it is optional 7608 as to whether the return object is really provided. */ 7609 rtx ret_reg = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); 7610 rtx scratch = gen_reg_rtx (SImode); 7611 rtx_code_label *endlab = gen_label_rtx (); 7612 7613 /* Calculate the return object size. */ 7614 tree size = TYPE_SIZE_UNIT (TREE_TYPE (fndecl)); 7615 rtx size_rtx = GEN_INT (TREE_INT_CST_LOW (size) & 0xfff); 7616 /* Construct a temporary return value. */ 7617 rtx temp_val 7618 = assign_stack_local (Pmode, TREE_INT_CST_LOW (size), 0); 7619 7620 /* Implement SPARC 32-bit psABI callee return struct checking: 7621 7622 Fetch the instruction where we will return to and see if 7623 it's an unimp instruction (the most significant 10 bits 7624 will be zero). */ 7625 emit_move_insn (scratch, gen_rtx_MEM (SImode, 7626 plus_constant (Pmode, 7627 ret_reg, 8))); 7628 /* Assume the size is valid and pre-adjust. */ 7629 emit_insn (gen_add3_insn (ret_reg, ret_reg, GEN_INT (4))); 7630 emit_cmp_and_jump_insns (scratch, size_rtx, EQ, const0_rtx, SImode, 7631 0, endlab); 7632 emit_insn (gen_sub3_insn (ret_reg, ret_reg, GEN_INT (4))); 7633 /* Write the address of the memory pointed to by temp_val into 7634 the memory pointed to by mem. */ 7635 emit_move_insn (mem, XEXP (temp_val, 0)); 7636 emit_label (endlab); 7637 } 7638 7639 return mem; 7640 } 7641 } 7642 7643 /* Handle TARGET_FUNCTION_VALUE, and TARGET_LIBCALL_VALUE target hook. 7644 For v9, function return values are subject to the same rules as arguments, 7645 except that up to 32 bytes may be returned in registers. */ 7646 7647 static rtx 7648 sparc_function_value_1 (const_tree type, machine_mode mode, 7649 bool outgoing) 7650 { 7651 /* Beware that the two values are swapped here wrt function_arg. */ 7652 int regbase = (outgoing 7653 ? SPARC_INCOMING_INT_ARG_FIRST 7654 : SPARC_OUTGOING_INT_ARG_FIRST); 7655 enum mode_class mclass = GET_MODE_CLASS (mode); 7656 int regno; 7657 7658 /* Vector types deserve special treatment because they are polymorphic wrt 7659 their mode, depending upon whether VIS instructions are enabled. */ 7660 if (type && TREE_CODE (type) == VECTOR_TYPE) 7661 { 7662 HOST_WIDE_INT size = int_size_in_bytes (type); 7663 gcc_assert ((TARGET_ARCH32 && size <= 8) 7664 || (TARGET_ARCH64 && size <= 32)); 7665 7666 if (mode == BLKmode) 7667 return function_arg_vector_value (size, SPARC_FP_ARG_FIRST); 7668 7669 mclass = MODE_FLOAT; 7670 } 7671 7672 if (TARGET_ARCH64 && type) 7673 { 7674 /* Structures up to 32 bytes in size are returned in registers. */ 7675 if (TREE_CODE (type) == RECORD_TYPE) 7676 { 7677 HOST_WIDE_INT size = int_size_in_bytes (type); 7678 gcc_assert (size <= 32); 7679 7680 return function_arg_record_value (type, mode, 0, 1, regbase); 7681 } 7682 7683 /* Unions up to 32 bytes in size are returned in integer registers. */ 7684 else if (TREE_CODE (type) == UNION_TYPE) 7685 { 7686 HOST_WIDE_INT size = int_size_in_bytes (type); 7687 gcc_assert (size <= 32); 7688 7689 return function_arg_union_value (size, mode, 0, regbase); 7690 } 7691 7692 /* Objects that require it are returned in FP registers. */ 7693 else if (mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) 7694 ; 7695 7696 /* All other aggregate types are returned in an integer register in a 7697 mode corresponding to the size of the type. */ 7698 else if (AGGREGATE_TYPE_P (type)) 7699 { 7700 /* All other aggregate types are passed in an integer register 7701 in a mode corresponding to the size of the type. */ 7702 HOST_WIDE_INT size = int_size_in_bytes (type); 7703 gcc_assert (size <= 32); 7704 7705 mode = mode_for_size (size * BITS_PER_UNIT, MODE_INT, 0); 7706 7707 /* ??? We probably should have made the same ABI change in 7708 3.4.0 as the one we made for unions. The latter was 7709 required by the SCD though, while the former is not 7710 specified, so we favored compatibility and efficiency. 7711 7712 Now we're stuck for aggregates larger than 16 bytes, 7713 because OImode vanished in the meantime. Let's not 7714 try to be unduly clever, and simply follow the ABI 7715 for unions in that case. */ 7716 if (mode == BLKmode) 7717 return function_arg_union_value (size, mode, 0, regbase); 7718 else 7719 mclass = MODE_INT; 7720 } 7721 7722 /* We should only have pointer and integer types at this point. This 7723 must match sparc_promote_function_mode. */ 7724 else if (mclass == MODE_INT && GET_MODE_SIZE (mode) < UNITS_PER_WORD) 7725 mode = word_mode; 7726 } 7727 7728 /* We should only have pointer and integer types at this point, except with 7729 -freg-struct-return. This must match sparc_promote_function_mode. */ 7730 else if (TARGET_ARCH32 7731 && !(type && AGGREGATE_TYPE_P (type)) 7732 && mclass == MODE_INT 7733 && GET_MODE_SIZE (mode) < UNITS_PER_WORD) 7734 mode = word_mode; 7735 7736 if ((mclass == MODE_FLOAT || mclass == MODE_COMPLEX_FLOAT) && TARGET_FPU) 7737 regno = SPARC_FP_ARG_FIRST; 7738 else 7739 regno = regbase; 7740 7741 return gen_rtx_REG (mode, regno); 7742 } 7743 7744 /* Handle TARGET_FUNCTION_VALUE. 7745 On the SPARC, the value is found in the first "output" register, but the 7746 called function leaves it in the first "input" register. */ 7747 7748 static rtx 7749 sparc_function_value (const_tree valtype, 7750 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 7751 bool outgoing) 7752 { 7753 return sparc_function_value_1 (valtype, TYPE_MODE (valtype), outgoing); 7754 } 7755 7756 /* Handle TARGET_LIBCALL_VALUE. */ 7757 7758 static rtx 7759 sparc_libcall_value (machine_mode mode, 7760 const_rtx fun ATTRIBUTE_UNUSED) 7761 { 7762 return sparc_function_value_1 (NULL_TREE, mode, false); 7763 } 7764 7765 /* Handle FUNCTION_VALUE_REGNO_P. 7766 On the SPARC, the first "output" reg is used for integer values, and the 7767 first floating point register is used for floating point values. */ 7768 7769 static bool 7770 sparc_function_value_regno_p (const unsigned int regno) 7771 { 7772 return (regno == 8 || (TARGET_FPU && regno == 32)); 7773 } 7774 7775 /* Do what is necessary for `va_start'. We look at the current function 7776 to determine if stdarg or varargs is used and return the address of 7777 the first unnamed parameter. */ 7778 7779 static rtx 7780 sparc_builtin_saveregs (void) 7781 { 7782 int first_reg = crtl->args.info.words; 7783 rtx address; 7784 int regno; 7785 7786 for (regno = first_reg; regno < SPARC_INT_ARG_MAX; regno++) 7787 emit_move_insn (gen_rtx_MEM (word_mode, 7788 gen_rtx_PLUS (Pmode, 7789 frame_pointer_rtx, 7790 GEN_INT (FIRST_PARM_OFFSET (0) 7791 + (UNITS_PER_WORD 7792 * regno)))), 7793 gen_rtx_REG (word_mode, 7794 SPARC_INCOMING_INT_ARG_FIRST + regno)); 7795 7796 address = gen_rtx_PLUS (Pmode, 7797 frame_pointer_rtx, 7798 GEN_INT (FIRST_PARM_OFFSET (0) 7799 + UNITS_PER_WORD * first_reg)); 7800 7801 return address; 7802 } 7803 7804 /* Implement `va_start' for stdarg. */ 7805 7806 static void 7807 sparc_va_start (tree valist, rtx nextarg) 7808 { 7809 nextarg = expand_builtin_saveregs (); 7810 std_expand_builtin_va_start (valist, nextarg); 7811 } 7812 7813 /* Implement `va_arg' for stdarg. */ 7814 7815 static tree 7816 sparc_gimplify_va_arg (tree valist, tree type, gimple_seq *pre_p, 7817 gimple_seq *post_p) 7818 { 7819 HOST_WIDE_INT size, rsize, align; 7820 tree addr, incr; 7821 bool indirect; 7822 tree ptrtype = build_pointer_type (type); 7823 7824 if (pass_by_reference (NULL, TYPE_MODE (type), type, false)) 7825 { 7826 indirect = true; 7827 size = rsize = UNITS_PER_WORD; 7828 align = 0; 7829 } 7830 else 7831 { 7832 indirect = false; 7833 size = int_size_in_bytes (type); 7834 rsize = ROUND_UP (size, UNITS_PER_WORD); 7835 align = 0; 7836 7837 if (TARGET_ARCH64) 7838 { 7839 /* For SPARC64, objects requiring 16-byte alignment get it. */ 7840 if (TYPE_ALIGN (type) >= 2 * (unsigned) BITS_PER_WORD) 7841 align = 2 * UNITS_PER_WORD; 7842 7843 /* SPARC-V9 ABI states that structures up to 16 bytes in size 7844 are left-justified in their slots. */ 7845 if (AGGREGATE_TYPE_P (type)) 7846 { 7847 if (size == 0) 7848 size = rsize = UNITS_PER_WORD; 7849 else 7850 size = rsize; 7851 } 7852 } 7853 } 7854 7855 incr = valist; 7856 if (align) 7857 { 7858 incr = fold_build_pointer_plus_hwi (incr, align - 1); 7859 incr = fold_convert (sizetype, incr); 7860 incr = fold_build2 (BIT_AND_EXPR, sizetype, incr, 7861 size_int (-align)); 7862 incr = fold_convert (ptr_type_node, incr); 7863 } 7864 7865 gimplify_expr (&incr, pre_p, post_p, is_gimple_val, fb_rvalue); 7866 addr = incr; 7867 7868 if (BYTES_BIG_ENDIAN && size < rsize) 7869 addr = fold_build_pointer_plus_hwi (incr, rsize - size); 7870 7871 if (indirect) 7872 { 7873 addr = fold_convert (build_pointer_type (ptrtype), addr); 7874 addr = build_va_arg_indirect_ref (addr); 7875 } 7876 7877 /* If the address isn't aligned properly for the type, we need a temporary. 7878 FIXME: This is inefficient, usually we can do this in registers. */ 7879 else if (align == 0 && TYPE_ALIGN (type) > BITS_PER_WORD) 7880 { 7881 tree tmp = create_tmp_var (type, "va_arg_tmp"); 7882 tree dest_addr = build_fold_addr_expr (tmp); 7883 tree copy = build_call_expr (builtin_decl_implicit (BUILT_IN_MEMCPY), 7884 3, dest_addr, addr, size_int (rsize)); 7885 TREE_ADDRESSABLE (tmp) = 1; 7886 gimplify_and_add (copy, pre_p); 7887 addr = dest_addr; 7888 } 7889 7890 else 7891 addr = fold_convert (ptrtype, addr); 7892 7893 incr = fold_build_pointer_plus_hwi (incr, rsize); 7894 gimplify_assign (valist, incr, post_p); 7895 7896 return build_va_arg_indirect_ref (addr); 7897 } 7898 7899 /* Implement the TARGET_VECTOR_MODE_SUPPORTED_P target hook. 7900 Specify whether the vector mode is supported by the hardware. */ 7901 7902 static bool 7903 sparc_vector_mode_supported_p (machine_mode mode) 7904 { 7905 return TARGET_VIS && VECTOR_MODE_P (mode) ? true : false; 7906 } 7907 7908 /* Implement the TARGET_VECTORIZE_PREFERRED_SIMD_MODE target hook. */ 7909 7910 static machine_mode 7911 sparc_preferred_simd_mode (machine_mode mode) 7912 { 7913 if (TARGET_VIS) 7914 switch (mode) 7915 { 7916 case SImode: 7917 return V2SImode; 7918 case HImode: 7919 return V4HImode; 7920 case QImode: 7921 return V8QImode; 7922 7923 default:; 7924 } 7925 7926 return word_mode; 7927 } 7928 7929 /* Return the string to output an unconditional branch to LABEL, which is 7930 the operand number of the label. 7931 7932 DEST is the destination insn (i.e. the label), INSN is the source. */ 7933 7934 const char * 7935 output_ubranch (rtx dest, rtx_insn *insn) 7936 { 7937 static char string[64]; 7938 bool v9_form = false; 7939 int delta; 7940 char *p; 7941 7942 /* Even if we are trying to use cbcond for this, evaluate 7943 whether we can use V9 branches as our backup plan. */ 7944 7945 delta = 5000000; 7946 if (INSN_ADDRESSES_SET_P ()) 7947 delta = (INSN_ADDRESSES (INSN_UID (dest)) 7948 - INSN_ADDRESSES (INSN_UID (insn))); 7949 7950 /* Leave some instructions for "slop". */ 7951 if (TARGET_V9 && delta >= -260000 && delta < 260000) 7952 v9_form = true; 7953 7954 if (TARGET_CBCOND) 7955 { 7956 bool emit_nop = emit_cbcond_nop (insn); 7957 bool far = false; 7958 const char *rval; 7959 7960 if (delta < -500 || delta > 500) 7961 far = true; 7962 7963 if (far) 7964 { 7965 if (v9_form) 7966 rval = "ba,a,pt\t%%xcc, %l0"; 7967 else 7968 rval = "b,a\t%l0"; 7969 } 7970 else 7971 { 7972 if (emit_nop) 7973 rval = "cwbe\t%%g0, %%g0, %l0\n\tnop"; 7974 else 7975 rval = "cwbe\t%%g0, %%g0, %l0"; 7976 } 7977 return rval; 7978 } 7979 7980 if (v9_form) 7981 strcpy (string, "ba%*,pt\t%%xcc, "); 7982 else 7983 strcpy (string, "b%*\t"); 7984 7985 p = strchr (string, '\0'); 7986 *p++ = '%'; 7987 *p++ = 'l'; 7988 *p++ = '0'; 7989 *p++ = '%'; 7990 *p++ = '('; 7991 *p = '\0'; 7992 7993 return string; 7994 } 7995 7996 /* Return the string to output a conditional branch to LABEL, which is 7997 the operand number of the label. OP is the conditional expression. 7998 XEXP (OP, 0) is assumed to be a condition code register (integer or 7999 floating point) and its mode specifies what kind of comparison we made. 8000 8001 DEST is the destination insn (i.e. the label), INSN is the source. 8002 8003 REVERSED is nonzero if we should reverse the sense of the comparison. 8004 8005 ANNUL is nonzero if we should generate an annulling branch. */ 8006 8007 const char * 8008 output_cbranch (rtx op, rtx dest, int label, int reversed, int annul, 8009 rtx_insn *insn) 8010 { 8011 static char string[64]; 8012 enum rtx_code code = GET_CODE (op); 8013 rtx cc_reg = XEXP (op, 0); 8014 machine_mode mode = GET_MODE (cc_reg); 8015 const char *labelno, *branch; 8016 int spaces = 8, far; 8017 char *p; 8018 8019 /* v9 branches are limited to +-1MB. If it is too far away, 8020 change 8021 8022 bne,pt %xcc, .LC30 8023 8024 to 8025 8026 be,pn %xcc, .+12 8027 nop 8028 ba .LC30 8029 8030 and 8031 8032 fbne,a,pn %fcc2, .LC29 8033 8034 to 8035 8036 fbe,pt %fcc2, .+16 8037 nop 8038 ba .LC29 */ 8039 8040 far = TARGET_V9 && (get_attr_length (insn) >= 3); 8041 if (reversed ^ far) 8042 { 8043 /* Reversal of FP compares takes care -- an ordered compare 8044 becomes an unordered compare and vice versa. */ 8045 if (mode == CCFPmode || mode == CCFPEmode) 8046 code = reverse_condition_maybe_unordered (code); 8047 else 8048 code = reverse_condition (code); 8049 } 8050 8051 /* Start by writing the branch condition. */ 8052 if (mode == CCFPmode || mode == CCFPEmode) 8053 { 8054 switch (code) 8055 { 8056 case NE: 8057 branch = "fbne"; 8058 break; 8059 case EQ: 8060 branch = "fbe"; 8061 break; 8062 case GE: 8063 branch = "fbge"; 8064 break; 8065 case GT: 8066 branch = "fbg"; 8067 break; 8068 case LE: 8069 branch = "fble"; 8070 break; 8071 case LT: 8072 branch = "fbl"; 8073 break; 8074 case UNORDERED: 8075 branch = "fbu"; 8076 break; 8077 case ORDERED: 8078 branch = "fbo"; 8079 break; 8080 case UNGT: 8081 branch = "fbug"; 8082 break; 8083 case UNLT: 8084 branch = "fbul"; 8085 break; 8086 case UNEQ: 8087 branch = "fbue"; 8088 break; 8089 case UNGE: 8090 branch = "fbuge"; 8091 break; 8092 case UNLE: 8093 branch = "fbule"; 8094 break; 8095 case LTGT: 8096 branch = "fblg"; 8097 break; 8098 default: 8099 gcc_unreachable (); 8100 } 8101 8102 /* ??? !v9: FP branches cannot be preceded by another floating point 8103 insn. Because there is currently no concept of pre-delay slots, 8104 we can fix this only by always emitting a nop before a floating 8105 point branch. */ 8106 8107 string[0] = '\0'; 8108 if (! TARGET_V9) 8109 strcpy (string, "nop\n\t"); 8110 strcat (string, branch); 8111 } 8112 else 8113 { 8114 switch (code) 8115 { 8116 case NE: 8117 if (mode == CCVmode || mode == CCXVmode) 8118 branch = "bvs"; 8119 else 8120 branch = "bne"; 8121 break; 8122 case EQ: 8123 if (mode == CCVmode || mode == CCXVmode) 8124 branch = "bvc"; 8125 else 8126 branch = "be"; 8127 break; 8128 case GE: 8129 if (mode == CCNZmode || mode == CCXNZmode) 8130 branch = "bpos"; 8131 else 8132 branch = "bge"; 8133 break; 8134 case GT: 8135 branch = "bg"; 8136 break; 8137 case LE: 8138 branch = "ble"; 8139 break; 8140 case LT: 8141 if (mode == CCNZmode || mode == CCXNZmode) 8142 branch = "bneg"; 8143 else 8144 branch = "bl"; 8145 break; 8146 case GEU: 8147 branch = "bgeu"; 8148 break; 8149 case GTU: 8150 branch = "bgu"; 8151 break; 8152 case LEU: 8153 branch = "bleu"; 8154 break; 8155 case LTU: 8156 branch = "blu"; 8157 break; 8158 default: 8159 gcc_unreachable (); 8160 } 8161 strcpy (string, branch); 8162 } 8163 spaces -= strlen (branch); 8164 p = strchr (string, '\0'); 8165 8166 /* Now add the annulling, the label, and a possible noop. */ 8167 if (annul && ! far) 8168 { 8169 strcpy (p, ",a"); 8170 p += 2; 8171 spaces -= 2; 8172 } 8173 8174 if (TARGET_V9) 8175 { 8176 rtx note; 8177 int v8 = 0; 8178 8179 if (! far && insn && INSN_ADDRESSES_SET_P ()) 8180 { 8181 int delta = (INSN_ADDRESSES (INSN_UID (dest)) 8182 - INSN_ADDRESSES (INSN_UID (insn))); 8183 /* Leave some instructions for "slop". */ 8184 if (delta < -260000 || delta >= 260000) 8185 v8 = 1; 8186 } 8187 8188 switch (mode) 8189 { 8190 case CCmode: 8191 case CCNZmode: 8192 case CCCmode: 8193 case CCVmode: 8194 labelno = "%%icc, "; 8195 if (v8) 8196 labelno = ""; 8197 break; 8198 case CCXmode: 8199 case CCXNZmode: 8200 case CCXCmode: 8201 case CCXVmode: 8202 labelno = "%%xcc, "; 8203 gcc_assert (!v8); 8204 break; 8205 case CCFPmode: 8206 case CCFPEmode: 8207 { 8208 static char v9_fcc_labelno[] = "%%fccX, "; 8209 /* Set the char indicating the number of the fcc reg to use. */ 8210 v9_fcc_labelno[5] = REGNO (cc_reg) - SPARC_FIRST_V9_FCC_REG + '0'; 8211 labelno = v9_fcc_labelno; 8212 if (v8) 8213 { 8214 gcc_assert (REGNO (cc_reg) == SPARC_FCC_REG); 8215 labelno = ""; 8216 } 8217 } 8218 break; 8219 default: 8220 gcc_unreachable (); 8221 } 8222 8223 if (*labelno && insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 8224 { 8225 strcpy (p, 8226 ((XINT (note, 0) >= REG_BR_PROB_BASE / 2) ^ far) 8227 ? ",pt" : ",pn"); 8228 p += 3; 8229 spaces -= 3; 8230 } 8231 } 8232 else 8233 labelno = ""; 8234 8235 if (spaces > 0) 8236 *p++ = '\t'; 8237 else 8238 *p++ = ' '; 8239 strcpy (p, labelno); 8240 p = strchr (p, '\0'); 8241 if (far) 8242 { 8243 strcpy (p, ".+12\n\t nop\n\tb\t"); 8244 /* Skip the next insn if requested or 8245 if we know that it will be a nop. */ 8246 if (annul || ! final_sequence) 8247 p[3] = '6'; 8248 p += 14; 8249 } 8250 *p++ = '%'; 8251 *p++ = 'l'; 8252 *p++ = label + '0'; 8253 *p++ = '%'; 8254 *p++ = '#'; 8255 *p = '\0'; 8256 8257 return string; 8258 } 8259 8260 /* Emit a library call comparison between floating point X and Y. 8261 COMPARISON is the operator to compare with (EQ, NE, GT, etc). 8262 Return the new operator to be used in the comparison sequence. 8263 8264 TARGET_ARCH64 uses _Qp_* functions, which use pointers to TFmode 8265 values as arguments instead of the TFmode registers themselves, 8266 that's why we cannot call emit_float_lib_cmp. */ 8267 8268 rtx 8269 sparc_emit_float_lib_cmp (rtx x, rtx y, enum rtx_code comparison) 8270 { 8271 const char *qpfunc; 8272 rtx slot0, slot1, result, tem, tem2, libfunc; 8273 machine_mode mode; 8274 enum rtx_code new_comparison; 8275 8276 switch (comparison) 8277 { 8278 case EQ: 8279 qpfunc = (TARGET_ARCH64 ? "_Qp_feq" : "_Q_feq"); 8280 break; 8281 8282 case NE: 8283 qpfunc = (TARGET_ARCH64 ? "_Qp_fne" : "_Q_fne"); 8284 break; 8285 8286 case GT: 8287 qpfunc = (TARGET_ARCH64 ? "_Qp_fgt" : "_Q_fgt"); 8288 break; 8289 8290 case GE: 8291 qpfunc = (TARGET_ARCH64 ? "_Qp_fge" : "_Q_fge"); 8292 break; 8293 8294 case LT: 8295 qpfunc = (TARGET_ARCH64 ? "_Qp_flt" : "_Q_flt"); 8296 break; 8297 8298 case LE: 8299 qpfunc = (TARGET_ARCH64 ? "_Qp_fle" : "_Q_fle"); 8300 break; 8301 8302 case ORDERED: 8303 case UNORDERED: 8304 case UNGT: 8305 case UNLT: 8306 case UNEQ: 8307 case UNGE: 8308 case UNLE: 8309 case LTGT: 8310 qpfunc = (TARGET_ARCH64 ? "_Qp_cmp" : "_Q_cmp"); 8311 break; 8312 8313 default: 8314 gcc_unreachable (); 8315 } 8316 8317 if (TARGET_ARCH64) 8318 { 8319 if (MEM_P (x)) 8320 { 8321 tree expr = MEM_EXPR (x); 8322 if (expr) 8323 mark_addressable (expr); 8324 slot0 = x; 8325 } 8326 else 8327 { 8328 slot0 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode)); 8329 emit_move_insn (slot0, x); 8330 } 8331 8332 if (MEM_P (y)) 8333 { 8334 tree expr = MEM_EXPR (y); 8335 if (expr) 8336 mark_addressable (expr); 8337 slot1 = y; 8338 } 8339 else 8340 { 8341 slot1 = assign_stack_temp (TFmode, GET_MODE_SIZE(TFmode)); 8342 emit_move_insn (slot1, y); 8343 } 8344 8345 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc); 8346 emit_library_call (libfunc, LCT_NORMAL, 8347 DImode, 2, 8348 XEXP (slot0, 0), Pmode, 8349 XEXP (slot1, 0), Pmode); 8350 mode = DImode; 8351 } 8352 else 8353 { 8354 libfunc = gen_rtx_SYMBOL_REF (Pmode, qpfunc); 8355 emit_library_call (libfunc, LCT_NORMAL, 8356 SImode, 2, 8357 x, TFmode, y, TFmode); 8358 mode = SImode; 8359 } 8360 8361 8362 /* Immediately move the result of the libcall into a pseudo 8363 register so reload doesn't clobber the value if it needs 8364 the return register for a spill reg. */ 8365 result = gen_reg_rtx (mode); 8366 emit_move_insn (result, hard_libcall_value (mode, libfunc)); 8367 8368 switch (comparison) 8369 { 8370 default: 8371 return gen_rtx_NE (VOIDmode, result, const0_rtx); 8372 case ORDERED: 8373 case UNORDERED: 8374 new_comparison = (comparison == UNORDERED ? EQ : NE); 8375 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, GEN_INT(3)); 8376 case UNGT: 8377 case UNGE: 8378 new_comparison = (comparison == UNGT ? GT : NE); 8379 return gen_rtx_fmt_ee (new_comparison, VOIDmode, result, const1_rtx); 8380 case UNLE: 8381 return gen_rtx_NE (VOIDmode, result, const2_rtx); 8382 case UNLT: 8383 tem = gen_reg_rtx (mode); 8384 if (TARGET_ARCH32) 8385 emit_insn (gen_andsi3 (tem, result, const1_rtx)); 8386 else 8387 emit_insn (gen_anddi3 (tem, result, const1_rtx)); 8388 return gen_rtx_NE (VOIDmode, tem, const0_rtx); 8389 case UNEQ: 8390 case LTGT: 8391 tem = gen_reg_rtx (mode); 8392 if (TARGET_ARCH32) 8393 emit_insn (gen_addsi3 (tem, result, const1_rtx)); 8394 else 8395 emit_insn (gen_adddi3 (tem, result, const1_rtx)); 8396 tem2 = gen_reg_rtx (mode); 8397 if (TARGET_ARCH32) 8398 emit_insn (gen_andsi3 (tem2, tem, const2_rtx)); 8399 else 8400 emit_insn (gen_anddi3 (tem2, tem, const2_rtx)); 8401 new_comparison = (comparison == UNEQ ? EQ : NE); 8402 return gen_rtx_fmt_ee (new_comparison, VOIDmode, tem2, const0_rtx); 8403 } 8404 8405 gcc_unreachable (); 8406 } 8407 8408 /* Generate an unsigned DImode to FP conversion. This is the same code 8409 optabs would emit if we didn't have TFmode patterns. */ 8410 8411 void 8412 sparc_emit_floatunsdi (rtx *operands, machine_mode mode) 8413 { 8414 rtx i0, i1, f0, in, out; 8415 8416 out = operands[0]; 8417 in = force_reg (DImode, operands[1]); 8418 rtx_code_label *neglab = gen_label_rtx (); 8419 rtx_code_label *donelab = gen_label_rtx (); 8420 i0 = gen_reg_rtx (DImode); 8421 i1 = gen_reg_rtx (DImode); 8422 f0 = gen_reg_rtx (mode); 8423 8424 emit_cmp_and_jump_insns (in, const0_rtx, LT, const0_rtx, DImode, 0, neglab); 8425 8426 emit_insn (gen_rtx_SET (out, gen_rtx_FLOAT (mode, in))); 8427 emit_jump_insn (gen_jump (donelab)); 8428 emit_barrier (); 8429 8430 emit_label (neglab); 8431 8432 emit_insn (gen_lshrdi3 (i0, in, const1_rtx)); 8433 emit_insn (gen_anddi3 (i1, in, const1_rtx)); 8434 emit_insn (gen_iordi3 (i0, i0, i1)); 8435 emit_insn (gen_rtx_SET (f0, gen_rtx_FLOAT (mode, i0))); 8436 emit_insn (gen_rtx_SET (out, gen_rtx_PLUS (mode, f0, f0))); 8437 8438 emit_label (donelab); 8439 } 8440 8441 /* Generate an FP to unsigned DImode conversion. This is the same code 8442 optabs would emit if we didn't have TFmode patterns. */ 8443 8444 void 8445 sparc_emit_fixunsdi (rtx *operands, machine_mode mode) 8446 { 8447 rtx i0, i1, f0, in, out, limit; 8448 8449 out = operands[0]; 8450 in = force_reg (mode, operands[1]); 8451 rtx_code_label *neglab = gen_label_rtx (); 8452 rtx_code_label *donelab = gen_label_rtx (); 8453 i0 = gen_reg_rtx (DImode); 8454 i1 = gen_reg_rtx (DImode); 8455 limit = gen_reg_rtx (mode); 8456 f0 = gen_reg_rtx (mode); 8457 8458 emit_move_insn (limit, 8459 const_double_from_real_value ( 8460 REAL_VALUE_ATOF ("9223372036854775808.0", mode), mode)); 8461 emit_cmp_and_jump_insns (in, limit, GE, NULL_RTX, mode, 0, neglab); 8462 8463 emit_insn (gen_rtx_SET (out, 8464 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, in)))); 8465 emit_jump_insn (gen_jump (donelab)); 8466 emit_barrier (); 8467 8468 emit_label (neglab); 8469 8470 emit_insn (gen_rtx_SET (f0, gen_rtx_MINUS (mode, in, limit))); 8471 emit_insn (gen_rtx_SET (i0, 8472 gen_rtx_FIX (DImode, gen_rtx_FIX (mode, f0)))); 8473 emit_insn (gen_movdi (i1, const1_rtx)); 8474 emit_insn (gen_ashldi3 (i1, i1, GEN_INT (63))); 8475 emit_insn (gen_xordi3 (out, i0, i1)); 8476 8477 emit_label (donelab); 8478 } 8479 8480 /* Return the string to output a compare and branch instruction to DEST. 8481 DEST is the destination insn (i.e. the label), INSN is the source, 8482 and OP is the conditional expression. */ 8483 8484 const char * 8485 output_cbcond (rtx op, rtx dest, rtx_insn *insn) 8486 { 8487 machine_mode mode = GET_MODE (XEXP (op, 0)); 8488 enum rtx_code code = GET_CODE (op); 8489 const char *cond_str, *tmpl; 8490 int far, emit_nop, len; 8491 static char string[64]; 8492 char size_char; 8493 8494 /* Compare and Branch is limited to +-2KB. If it is too far away, 8495 change 8496 8497 cxbne X, Y, .LC30 8498 8499 to 8500 8501 cxbe X, Y, .+16 8502 nop 8503 ba,pt xcc, .LC30 8504 nop */ 8505 8506 len = get_attr_length (insn); 8507 8508 far = len == 4; 8509 emit_nop = len == 2; 8510 8511 if (far) 8512 code = reverse_condition (code); 8513 8514 size_char = ((mode == SImode) ? 'w' : 'x'); 8515 8516 switch (code) 8517 { 8518 case NE: 8519 cond_str = "ne"; 8520 break; 8521 8522 case EQ: 8523 cond_str = "e"; 8524 break; 8525 8526 case GE: 8527 cond_str = "ge"; 8528 break; 8529 8530 case GT: 8531 cond_str = "g"; 8532 break; 8533 8534 case LE: 8535 cond_str = "le"; 8536 break; 8537 8538 case LT: 8539 cond_str = "l"; 8540 break; 8541 8542 case GEU: 8543 cond_str = "cc"; 8544 break; 8545 8546 case GTU: 8547 cond_str = "gu"; 8548 break; 8549 8550 case LEU: 8551 cond_str = "leu"; 8552 break; 8553 8554 case LTU: 8555 cond_str = "cs"; 8556 break; 8557 8558 default: 8559 gcc_unreachable (); 8560 } 8561 8562 if (far) 8563 { 8564 int veryfar = 1, delta; 8565 8566 if (INSN_ADDRESSES_SET_P ()) 8567 { 8568 delta = (INSN_ADDRESSES (INSN_UID (dest)) 8569 - INSN_ADDRESSES (INSN_UID (insn))); 8570 /* Leave some instructions for "slop". */ 8571 if (delta >= -260000 && delta < 260000) 8572 veryfar = 0; 8573 } 8574 8575 if (veryfar) 8576 tmpl = "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tb\t%%3\n\tnop"; 8577 else 8578 tmpl = "c%cb%s\t%%1, %%2, .+16\n\tnop\n\tba,pt\t%%%%xcc, %%3\n\tnop"; 8579 } 8580 else 8581 { 8582 if (emit_nop) 8583 tmpl = "c%cb%s\t%%1, %%2, %%3\n\tnop"; 8584 else 8585 tmpl = "c%cb%s\t%%1, %%2, %%3"; 8586 } 8587 8588 snprintf (string, sizeof(string), tmpl, size_char, cond_str); 8589 8590 return string; 8591 } 8592 8593 /* Return the string to output a conditional branch to LABEL, testing 8594 register REG. LABEL is the operand number of the label; REG is the 8595 operand number of the reg. OP is the conditional expression. The mode 8596 of REG says what kind of comparison we made. 8597 8598 DEST is the destination insn (i.e. the label), INSN is the source. 8599 8600 REVERSED is nonzero if we should reverse the sense of the comparison. 8601 8602 ANNUL is nonzero if we should generate an annulling branch. */ 8603 8604 const char * 8605 output_v9branch (rtx op, rtx dest, int reg, int label, int reversed, 8606 int annul, rtx_insn *insn) 8607 { 8608 static char string[64]; 8609 enum rtx_code code = GET_CODE (op); 8610 machine_mode mode = GET_MODE (XEXP (op, 0)); 8611 rtx note; 8612 int far; 8613 char *p; 8614 8615 /* branch on register are limited to +-128KB. If it is too far away, 8616 change 8617 8618 brnz,pt %g1, .LC30 8619 8620 to 8621 8622 brz,pn %g1, .+12 8623 nop 8624 ba,pt %xcc, .LC30 8625 8626 and 8627 8628 brgez,a,pn %o1, .LC29 8629 8630 to 8631 8632 brlz,pt %o1, .+16 8633 nop 8634 ba,pt %xcc, .LC29 */ 8635 8636 far = get_attr_length (insn) >= 3; 8637 8638 /* If not floating-point or if EQ or NE, we can just reverse the code. */ 8639 if (reversed ^ far) 8640 code = reverse_condition (code); 8641 8642 /* Only 64-bit versions of these instructions exist. */ 8643 gcc_assert (mode == DImode); 8644 8645 /* Start by writing the branch condition. */ 8646 8647 switch (code) 8648 { 8649 case NE: 8650 strcpy (string, "brnz"); 8651 break; 8652 8653 case EQ: 8654 strcpy (string, "brz"); 8655 break; 8656 8657 case GE: 8658 strcpy (string, "brgez"); 8659 break; 8660 8661 case LT: 8662 strcpy (string, "brlz"); 8663 break; 8664 8665 case LE: 8666 strcpy (string, "brlez"); 8667 break; 8668 8669 case GT: 8670 strcpy (string, "brgz"); 8671 break; 8672 8673 default: 8674 gcc_unreachable (); 8675 } 8676 8677 p = strchr (string, '\0'); 8678 8679 /* Now add the annulling, reg, label, and nop. */ 8680 if (annul && ! far) 8681 { 8682 strcpy (p, ",a"); 8683 p += 2; 8684 } 8685 8686 if (insn && (note = find_reg_note (insn, REG_BR_PROB, NULL_RTX))) 8687 { 8688 strcpy (p, 8689 ((XINT (note, 0) >= REG_BR_PROB_BASE / 2) ^ far) 8690 ? ",pt" : ",pn"); 8691 p += 3; 8692 } 8693 8694 *p = p < string + 8 ? '\t' : ' '; 8695 p++; 8696 *p++ = '%'; 8697 *p++ = '0' + reg; 8698 *p++ = ','; 8699 *p++ = ' '; 8700 if (far) 8701 { 8702 int veryfar = 1, delta; 8703 8704 if (INSN_ADDRESSES_SET_P ()) 8705 { 8706 delta = (INSN_ADDRESSES (INSN_UID (dest)) 8707 - INSN_ADDRESSES (INSN_UID (insn))); 8708 /* Leave some instructions for "slop". */ 8709 if (delta >= -260000 && delta < 260000) 8710 veryfar = 0; 8711 } 8712 8713 strcpy (p, ".+12\n\t nop\n\t"); 8714 /* Skip the next insn if requested or 8715 if we know that it will be a nop. */ 8716 if (annul || ! final_sequence) 8717 p[3] = '6'; 8718 p += 12; 8719 if (veryfar) 8720 { 8721 strcpy (p, "b\t"); 8722 p += 2; 8723 } 8724 else 8725 { 8726 strcpy (p, "ba,pt\t%%xcc, "); 8727 p += 13; 8728 } 8729 } 8730 *p++ = '%'; 8731 *p++ = 'l'; 8732 *p++ = '0' + label; 8733 *p++ = '%'; 8734 *p++ = '#'; 8735 *p = '\0'; 8736 8737 return string; 8738 } 8739 8740 /* Return 1, if any of the registers of the instruction are %l[0-7] or %o[0-7]. 8741 Such instructions cannot be used in the delay slot of return insn on v9. 8742 If TEST is 0, also rename all %i[0-7] registers to their %o[0-7] counterparts. 8743 */ 8744 8745 static int 8746 epilogue_renumber (register rtx *where, int test) 8747 { 8748 register const char *fmt; 8749 register int i; 8750 register enum rtx_code code; 8751 8752 if (*where == 0) 8753 return 0; 8754 8755 code = GET_CODE (*where); 8756 8757 switch (code) 8758 { 8759 case REG: 8760 if (REGNO (*where) >= 8 && REGNO (*where) < 24) /* oX or lX */ 8761 return 1; 8762 if (! test && REGNO (*where) >= 24 && REGNO (*where) < 32) 8763 *where = gen_rtx_REG (GET_MODE (*where), OUTGOING_REGNO (REGNO(*where))); 8764 /* fallthrough */ 8765 case SCRATCH: 8766 case CC0: 8767 case PC: 8768 case CONST_INT: 8769 case CONST_WIDE_INT: 8770 case CONST_DOUBLE: 8771 return 0; 8772 8773 /* Do not replace the frame pointer with the stack pointer because 8774 it can cause the delayed instruction to load below the stack. 8775 This occurs when instructions like: 8776 8777 (set (reg/i:SI 24 %i0) 8778 (mem/f:SI (plus:SI (reg/f:SI 30 %fp) 8779 (const_int -20 [0xffffffec])) 0)) 8780 8781 are in the return delayed slot. */ 8782 case PLUS: 8783 if (GET_CODE (XEXP (*where, 0)) == REG 8784 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM 8785 && (GET_CODE (XEXP (*where, 1)) != CONST_INT 8786 || INTVAL (XEXP (*where, 1)) < SPARC_STACK_BIAS)) 8787 return 1; 8788 break; 8789 8790 case MEM: 8791 if (SPARC_STACK_BIAS 8792 && GET_CODE (XEXP (*where, 0)) == REG 8793 && REGNO (XEXP (*where, 0)) == HARD_FRAME_POINTER_REGNUM) 8794 return 1; 8795 break; 8796 8797 default: 8798 break; 8799 } 8800 8801 fmt = GET_RTX_FORMAT (code); 8802 8803 for (i = GET_RTX_LENGTH (code) - 1; i >= 0; i--) 8804 { 8805 if (fmt[i] == 'E') 8806 { 8807 register int j; 8808 for (j = XVECLEN (*where, i) - 1; j >= 0; j--) 8809 if (epilogue_renumber (&(XVECEXP (*where, i, j)), test)) 8810 return 1; 8811 } 8812 else if (fmt[i] == 'e' 8813 && epilogue_renumber (&(XEXP (*where, i)), test)) 8814 return 1; 8815 } 8816 return 0; 8817 } 8818 8819 /* Leaf functions and non-leaf functions have different needs. */ 8820 8821 static const int 8822 reg_leaf_alloc_order[] = REG_LEAF_ALLOC_ORDER; 8823 8824 static const int 8825 reg_nonleaf_alloc_order[] = REG_ALLOC_ORDER; 8826 8827 static const int *const reg_alloc_orders[] = { 8828 reg_leaf_alloc_order, 8829 reg_nonleaf_alloc_order}; 8830 8831 void 8832 order_regs_for_local_alloc (void) 8833 { 8834 static int last_order_nonleaf = 1; 8835 8836 if (df_regs_ever_live_p (15) != last_order_nonleaf) 8837 { 8838 last_order_nonleaf = !last_order_nonleaf; 8839 memcpy ((char *) reg_alloc_order, 8840 (const char *) reg_alloc_orders[last_order_nonleaf], 8841 FIRST_PSEUDO_REGISTER * sizeof (int)); 8842 } 8843 } 8844 8845 /* Return 1 if REG and MEM are legitimate enough to allow the various 8846 MEM<-->REG splits to be run. */ 8847 8848 int 8849 sparc_split_reg_mem_legitimate (rtx reg, rtx mem) 8850 { 8851 /* Punt if we are here by mistake. */ 8852 gcc_assert (reload_completed); 8853 8854 /* We must have an offsettable memory reference. */ 8855 if (!offsettable_memref_p (mem)) 8856 return 0; 8857 8858 /* If we have legitimate args for ldd/std, we do not want 8859 the split to happen. */ 8860 if ((REGNO (reg) % 2) == 0 && mem_min_alignment (mem, 8)) 8861 return 0; 8862 8863 /* Success. */ 8864 return 1; 8865 } 8866 8867 /* Split a REG <-- MEM move into a pair of moves in MODE. */ 8868 8869 void 8870 sparc_split_reg_mem (rtx dest, rtx src, machine_mode mode) 8871 { 8872 rtx high_part = gen_highpart (mode, dest); 8873 rtx low_part = gen_lowpart (mode, dest); 8874 rtx word0 = adjust_address (src, mode, 0); 8875 rtx word1 = adjust_address (src, mode, 4); 8876 8877 if (reg_overlap_mentioned_p (high_part, word1)) 8878 { 8879 emit_move_insn_1 (low_part, word1); 8880 emit_move_insn_1 (high_part, word0); 8881 } 8882 else 8883 { 8884 emit_move_insn_1 (high_part, word0); 8885 emit_move_insn_1 (low_part, word1); 8886 } 8887 } 8888 8889 /* Split a MEM <-- REG move into a pair of moves in MODE. */ 8890 8891 void 8892 sparc_split_mem_reg (rtx dest, rtx src, machine_mode mode) 8893 { 8894 rtx word0 = adjust_address (dest, mode, 0); 8895 rtx word1 = adjust_address (dest, mode, 4); 8896 rtx high_part = gen_highpart (mode, src); 8897 rtx low_part = gen_lowpart (mode, src); 8898 8899 emit_move_insn_1 (word0, high_part); 8900 emit_move_insn_1 (word1, low_part); 8901 } 8902 8903 /* Like sparc_split_reg_mem_legitimate but for REG <--> REG moves. */ 8904 8905 int 8906 sparc_split_reg_reg_legitimate (rtx reg1, rtx reg2) 8907 { 8908 /* Punt if we are here by mistake. */ 8909 gcc_assert (reload_completed); 8910 8911 if (GET_CODE (reg1) == SUBREG) 8912 reg1 = SUBREG_REG (reg1); 8913 if (GET_CODE (reg1) != REG) 8914 return 0; 8915 const int regno1 = REGNO (reg1); 8916 8917 if (GET_CODE (reg2) == SUBREG) 8918 reg2 = SUBREG_REG (reg2); 8919 if (GET_CODE (reg2) != REG) 8920 return 0; 8921 const int regno2 = REGNO (reg2); 8922 8923 if (SPARC_INT_REG_P (regno1) && SPARC_INT_REG_P (regno2)) 8924 return 1; 8925 8926 if (TARGET_VIS3) 8927 { 8928 if ((SPARC_INT_REG_P (regno1) && SPARC_FP_REG_P (regno2)) 8929 || (SPARC_FP_REG_P (regno1) && SPARC_INT_REG_P (regno2))) 8930 return 1; 8931 } 8932 8933 return 0; 8934 } 8935 8936 /* Split a REG <--> REG move into a pair of moves in MODE. */ 8937 8938 void 8939 sparc_split_reg_reg (rtx dest, rtx src, machine_mode mode) 8940 { 8941 rtx dest1 = gen_highpart (mode, dest); 8942 rtx dest2 = gen_lowpart (mode, dest); 8943 rtx src1 = gen_highpart (mode, src); 8944 rtx src2 = gen_lowpart (mode, src); 8945 8946 /* Now emit using the real source and destination we found, swapping 8947 the order if we detect overlap. */ 8948 if (reg_overlap_mentioned_p (dest1, src2)) 8949 { 8950 emit_move_insn_1 (dest2, src2); 8951 emit_move_insn_1 (dest1, src1); 8952 } 8953 else 8954 { 8955 emit_move_insn_1 (dest1, src1); 8956 emit_move_insn_1 (dest2, src2); 8957 } 8958 } 8959 8960 /* Return 1 if REGNO (reg1) is even and REGNO (reg1) == REGNO (reg2) - 1. 8961 This makes them candidates for using ldd and std insns. 8962 8963 Note reg1 and reg2 *must* be hard registers. */ 8964 8965 int 8966 registers_ok_for_ldd_peep (rtx reg1, rtx reg2) 8967 { 8968 /* We might have been passed a SUBREG. */ 8969 if (GET_CODE (reg1) != REG || GET_CODE (reg2) != REG) 8970 return 0; 8971 8972 if (REGNO (reg1) % 2 != 0) 8973 return 0; 8974 8975 /* Integer ldd is deprecated in SPARC V9 */ 8976 if (TARGET_V9 && SPARC_INT_REG_P (REGNO (reg1))) 8977 return 0; 8978 8979 return (REGNO (reg1) == REGNO (reg2) - 1); 8980 } 8981 8982 /* Return 1 if the addresses in mem1 and mem2 are suitable for use in 8983 an ldd or std insn. 8984 8985 This can only happen when addr1 and addr2, the addresses in mem1 8986 and mem2, are consecutive memory locations (addr1 + 4 == addr2). 8987 addr1 must also be aligned on a 64-bit boundary. 8988 8989 Also iff dependent_reg_rtx is not null it should not be used to 8990 compute the address for mem1, i.e. we cannot optimize a sequence 8991 like: 8992 ld [%o0], %o0 8993 ld [%o0 + 4], %o1 8994 to 8995 ldd [%o0], %o0 8996 nor: 8997 ld [%g3 + 4], %g3 8998 ld [%g3], %g2 8999 to 9000 ldd [%g3], %g2 9001 9002 But, note that the transformation from: 9003 ld [%g2 + 4], %g3 9004 ld [%g2], %g2 9005 to 9006 ldd [%g2], %g2 9007 is perfectly fine. Thus, the peephole2 patterns always pass us 9008 the destination register of the first load, never the second one. 9009 9010 For stores we don't have a similar problem, so dependent_reg_rtx is 9011 NULL_RTX. */ 9012 9013 int 9014 mems_ok_for_ldd_peep (rtx mem1, rtx mem2, rtx dependent_reg_rtx) 9015 { 9016 rtx addr1, addr2; 9017 unsigned int reg1; 9018 HOST_WIDE_INT offset1; 9019 9020 /* The mems cannot be volatile. */ 9021 if (MEM_VOLATILE_P (mem1) || MEM_VOLATILE_P (mem2)) 9022 return 0; 9023 9024 /* MEM1 should be aligned on a 64-bit boundary. */ 9025 if (MEM_ALIGN (mem1) < 64) 9026 return 0; 9027 9028 addr1 = XEXP (mem1, 0); 9029 addr2 = XEXP (mem2, 0); 9030 9031 /* Extract a register number and offset (if used) from the first addr. */ 9032 if (GET_CODE (addr1) == PLUS) 9033 { 9034 /* If not a REG, return zero. */ 9035 if (GET_CODE (XEXP (addr1, 0)) != REG) 9036 return 0; 9037 else 9038 { 9039 reg1 = REGNO (XEXP (addr1, 0)); 9040 /* The offset must be constant! */ 9041 if (GET_CODE (XEXP (addr1, 1)) != CONST_INT) 9042 return 0; 9043 offset1 = INTVAL (XEXP (addr1, 1)); 9044 } 9045 } 9046 else if (GET_CODE (addr1) != REG) 9047 return 0; 9048 else 9049 { 9050 reg1 = REGNO (addr1); 9051 /* This was a simple (mem (reg)) expression. Offset is 0. */ 9052 offset1 = 0; 9053 } 9054 9055 /* Make sure the second address is a (mem (plus (reg) (const_int). */ 9056 if (GET_CODE (addr2) != PLUS) 9057 return 0; 9058 9059 if (GET_CODE (XEXP (addr2, 0)) != REG 9060 || GET_CODE (XEXP (addr2, 1)) != CONST_INT) 9061 return 0; 9062 9063 if (reg1 != REGNO (XEXP (addr2, 0))) 9064 return 0; 9065 9066 if (dependent_reg_rtx != NULL_RTX && reg1 == REGNO (dependent_reg_rtx)) 9067 return 0; 9068 9069 /* The first offset must be evenly divisible by 8 to ensure the 9070 address is 64-bit aligned. */ 9071 if (offset1 % 8 != 0) 9072 return 0; 9073 9074 /* The offset for the second addr must be 4 more than the first addr. */ 9075 if (INTVAL (XEXP (addr2, 1)) != offset1 + 4) 9076 return 0; 9077 9078 /* All the tests passed. addr1 and addr2 are valid for ldd and std 9079 instructions. */ 9080 return 1; 9081 } 9082 9083 /* Return the widened memory access made of MEM1 and MEM2 in MODE. */ 9084 9085 rtx 9086 widen_mem_for_ldd_peep (rtx mem1, rtx mem2, machine_mode mode) 9087 { 9088 rtx x = widen_memory_access (mem1, mode, 0); 9089 MEM_NOTRAP_P (x) = MEM_NOTRAP_P (mem1) && MEM_NOTRAP_P (mem2); 9090 return x; 9091 } 9092 9093 /* Return 1 if reg is a pseudo, or is the first register in 9094 a hard register pair. This makes it suitable for use in 9095 ldd and std insns. */ 9096 9097 int 9098 register_ok_for_ldd (rtx reg) 9099 { 9100 /* We might have been passed a SUBREG. */ 9101 if (!REG_P (reg)) 9102 return 0; 9103 9104 if (REGNO (reg) < FIRST_PSEUDO_REGISTER) 9105 return (REGNO (reg) % 2 == 0); 9106 9107 return 1; 9108 } 9109 9110 /* Return 1 if OP, a MEM, has an address which is known to be 9111 aligned to an 8-byte boundary. */ 9112 9113 int 9114 memory_ok_for_ldd (rtx op) 9115 { 9116 /* In 64-bit mode, we assume that the address is word-aligned. */ 9117 if (TARGET_ARCH32 && !mem_min_alignment (op, 8)) 9118 return 0; 9119 9120 if (! can_create_pseudo_p () 9121 && !strict_memory_address_p (Pmode, XEXP (op, 0))) 9122 return 0; 9123 9124 return 1; 9125 } 9126 9127 /* Implement TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ 9128 9129 static bool 9130 sparc_print_operand_punct_valid_p (unsigned char code) 9131 { 9132 if (code == '#' 9133 || code == '*' 9134 || code == '(' 9135 || code == ')' 9136 || code == '_' 9137 || code == '&') 9138 return true; 9139 9140 return false; 9141 } 9142 9143 /* Implement TARGET_PRINT_OPERAND. 9144 Print operand X (an rtx) in assembler syntax to file FILE. 9145 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 9146 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 9147 9148 static void 9149 sparc_print_operand (FILE *file, rtx x, int code) 9150 { 9151 const char *s; 9152 9153 switch (code) 9154 { 9155 case '#': 9156 /* Output an insn in a delay slot. */ 9157 if (final_sequence) 9158 sparc_indent_opcode = 1; 9159 else 9160 fputs ("\n\t nop", file); 9161 return; 9162 case '*': 9163 /* Output an annul flag if there's nothing for the delay slot and we 9164 are optimizing. This is always used with '(' below. 9165 Sun OS 4.1.1 dbx can't handle an annulled unconditional branch; 9166 this is a dbx bug. So, we only do this when optimizing. 9167 On UltraSPARC, a branch in a delay slot causes a pipeline flush. 9168 Always emit a nop in case the next instruction is a branch. */ 9169 if (! final_sequence && (optimize && (int)sparc_cpu < PROCESSOR_V9)) 9170 fputs (",a", file); 9171 return; 9172 case '(': 9173 /* Output a 'nop' if there's nothing for the delay slot and we are 9174 not optimizing. This is always used with '*' above. */ 9175 if (! final_sequence && ! (optimize && (int)sparc_cpu < PROCESSOR_V9)) 9176 fputs ("\n\t nop", file); 9177 else if (final_sequence) 9178 sparc_indent_opcode = 1; 9179 return; 9180 case ')': 9181 /* Output the right displacement from the saved PC on function return. 9182 The caller may have placed an "unimp" insn immediately after the call 9183 so we have to account for it. This insn is used in the 32-bit ABI 9184 when calling a function that returns a non zero-sized structure. The 9185 64-bit ABI doesn't have it. Be careful to have this test be the same 9186 as that for the call. The exception is when sparc_std_struct_return 9187 is enabled, the psABI is followed exactly and the adjustment is made 9188 by the code in sparc_struct_value_rtx. The call emitted is the same 9189 when sparc_std_struct_return is enabled. */ 9190 if (!TARGET_ARCH64 9191 && cfun->returns_struct 9192 && !sparc_std_struct_return 9193 && DECL_SIZE (DECL_RESULT (current_function_decl)) 9194 && TREE_CODE (DECL_SIZE (DECL_RESULT (current_function_decl))) 9195 == INTEGER_CST 9196 && !integer_zerop (DECL_SIZE (DECL_RESULT (current_function_decl)))) 9197 fputs ("12", file); 9198 else 9199 fputc ('8', file); 9200 return; 9201 case '_': 9202 /* Output the Embedded Medium/Anywhere code model base register. */ 9203 fputs (EMBMEDANY_BASE_REG, file); 9204 return; 9205 case '&': 9206 /* Print some local dynamic TLS name. */ 9207 if (const char *name = get_some_local_dynamic_name ()) 9208 assemble_name (file, name); 9209 else 9210 output_operand_lossage ("'%%&' used without any " 9211 "local dynamic TLS references"); 9212 return; 9213 9214 case 'Y': 9215 /* Adjust the operand to take into account a RESTORE operation. */ 9216 if (GET_CODE (x) == CONST_INT) 9217 break; 9218 else if (GET_CODE (x) != REG) 9219 output_operand_lossage ("invalid %%Y operand"); 9220 else if (REGNO (x) < 8) 9221 fputs (reg_names[REGNO (x)], file); 9222 else if (REGNO (x) >= 24 && REGNO (x) < 32) 9223 fputs (reg_names[REGNO (x)-16], file); 9224 else 9225 output_operand_lossage ("invalid %%Y operand"); 9226 return; 9227 case 'L': 9228 /* Print out the low order register name of a register pair. */ 9229 if (WORDS_BIG_ENDIAN) 9230 fputs (reg_names[REGNO (x)+1], file); 9231 else 9232 fputs (reg_names[REGNO (x)], file); 9233 return; 9234 case 'H': 9235 /* Print out the high order register name of a register pair. */ 9236 if (WORDS_BIG_ENDIAN) 9237 fputs (reg_names[REGNO (x)], file); 9238 else 9239 fputs (reg_names[REGNO (x)+1], file); 9240 return; 9241 case 'R': 9242 /* Print out the second register name of a register pair or quad. 9243 I.e., R (%o0) => %o1. */ 9244 fputs (reg_names[REGNO (x)+1], file); 9245 return; 9246 case 'S': 9247 /* Print out the third register name of a register quad. 9248 I.e., S (%o0) => %o2. */ 9249 fputs (reg_names[REGNO (x)+2], file); 9250 return; 9251 case 'T': 9252 /* Print out the fourth register name of a register quad. 9253 I.e., T (%o0) => %o3. */ 9254 fputs (reg_names[REGNO (x)+3], file); 9255 return; 9256 case 'x': 9257 /* Print a condition code register. */ 9258 if (REGNO (x) == SPARC_ICC_REG) 9259 { 9260 switch (GET_MODE (x)) 9261 { 9262 case CCmode: 9263 case CCNZmode: 9264 case CCCmode: 9265 case CCVmode: 9266 s = "%icc"; 9267 break; 9268 case CCXmode: 9269 case CCXNZmode: 9270 case CCXCmode: 9271 case CCXVmode: 9272 s = "%xcc"; 9273 break; 9274 default: 9275 gcc_unreachable (); 9276 } 9277 fputs (s, file); 9278 } 9279 else 9280 /* %fccN register */ 9281 fputs (reg_names[REGNO (x)], file); 9282 return; 9283 case 'm': 9284 /* Print the operand's address only. */ 9285 output_address (GET_MODE (x), XEXP (x, 0)); 9286 return; 9287 case 'r': 9288 /* In this case we need a register. Use %g0 if the 9289 operand is const0_rtx. */ 9290 if (x == const0_rtx 9291 || (GET_MODE (x) != VOIDmode && x == CONST0_RTX (GET_MODE (x)))) 9292 { 9293 fputs ("%g0", file); 9294 return; 9295 } 9296 else 9297 break; 9298 9299 case 'A': 9300 switch (GET_CODE (x)) 9301 { 9302 case IOR: 9303 s = "or"; 9304 break; 9305 case AND: 9306 s = "and"; 9307 break; 9308 case XOR: 9309 s = "xor"; 9310 break; 9311 default: 9312 output_operand_lossage ("invalid %%A operand"); 9313 s = ""; 9314 break; 9315 } 9316 fputs (s, file); 9317 return; 9318 9319 case 'B': 9320 switch (GET_CODE (x)) 9321 { 9322 case IOR: 9323 s = "orn"; 9324 break; 9325 case AND: 9326 s = "andn"; 9327 break; 9328 case XOR: 9329 s = "xnor"; 9330 break; 9331 default: 9332 output_operand_lossage ("invalid %%B operand"); 9333 s = ""; 9334 break; 9335 } 9336 fputs (s, file); 9337 return; 9338 9339 /* This is used by the conditional move instructions. */ 9340 case 'C': 9341 { 9342 machine_mode mode = GET_MODE (XEXP (x, 0)); 9343 switch (GET_CODE (x)) 9344 { 9345 case NE: 9346 if (mode == CCVmode || mode == CCXVmode) 9347 s = "vs"; 9348 else 9349 s = "ne"; 9350 break; 9351 case EQ: 9352 if (mode == CCVmode || mode == CCXVmode) 9353 s = "vc"; 9354 else 9355 s = "e"; 9356 break; 9357 case GE: 9358 if (mode == CCNZmode || mode == CCXNZmode) 9359 s = "pos"; 9360 else 9361 s = "ge"; 9362 break; 9363 case GT: 9364 s = "g"; 9365 break; 9366 case LE: 9367 s = "le"; 9368 break; 9369 case LT: 9370 if (mode == CCNZmode || mode == CCXNZmode) 9371 s = "neg"; 9372 else 9373 s = "l"; 9374 break; 9375 case GEU: 9376 s = "geu"; 9377 break; 9378 case GTU: 9379 s = "gu"; 9380 break; 9381 case LEU: 9382 s = "leu"; 9383 break; 9384 case LTU: 9385 s = "lu"; 9386 break; 9387 case LTGT: 9388 s = "lg"; 9389 break; 9390 case UNORDERED: 9391 s = "u"; 9392 break; 9393 case ORDERED: 9394 s = "o"; 9395 break; 9396 case UNLT: 9397 s = "ul"; 9398 break; 9399 case UNLE: 9400 s = "ule"; 9401 break; 9402 case UNGT: 9403 s = "ug"; 9404 break; 9405 case UNGE: 9406 s = "uge" 9407 ; break; 9408 case UNEQ: 9409 s = "ue"; 9410 break; 9411 default: 9412 output_operand_lossage ("invalid %%C operand"); 9413 s = ""; 9414 break; 9415 } 9416 fputs (s, file); 9417 return; 9418 } 9419 9420 /* This are used by the movr instruction pattern. */ 9421 case 'D': 9422 { 9423 switch (GET_CODE (x)) 9424 { 9425 case NE: 9426 s = "ne"; 9427 break; 9428 case EQ: 9429 s = "e"; 9430 break; 9431 case GE: 9432 s = "gez"; 9433 break; 9434 case LT: 9435 s = "lz"; 9436 break; 9437 case LE: 9438 s = "lez"; 9439 break; 9440 case GT: 9441 s = "gz"; 9442 break; 9443 default: 9444 output_operand_lossage ("invalid %%D operand"); 9445 s = ""; 9446 break; 9447 } 9448 fputs (s, file); 9449 return; 9450 } 9451 9452 case 'b': 9453 { 9454 /* Print a sign-extended character. */ 9455 int i = trunc_int_for_mode (INTVAL (x), QImode); 9456 fprintf (file, "%d", i); 9457 return; 9458 } 9459 9460 case 'f': 9461 /* Operand must be a MEM; write its address. */ 9462 if (GET_CODE (x) != MEM) 9463 output_operand_lossage ("invalid %%f operand"); 9464 output_address (GET_MODE (x), XEXP (x, 0)); 9465 return; 9466 9467 case 's': 9468 { 9469 /* Print a sign-extended 32-bit value. */ 9470 HOST_WIDE_INT i; 9471 if (GET_CODE(x) == CONST_INT) 9472 i = INTVAL (x); 9473 else 9474 { 9475 output_operand_lossage ("invalid %%s operand"); 9476 return; 9477 } 9478 i = trunc_int_for_mode (i, SImode); 9479 fprintf (file, HOST_WIDE_INT_PRINT_DEC, i); 9480 return; 9481 } 9482 9483 case 0: 9484 /* Do nothing special. */ 9485 break; 9486 9487 default: 9488 /* Undocumented flag. */ 9489 output_operand_lossage ("invalid operand output code"); 9490 } 9491 9492 if (GET_CODE (x) == REG) 9493 fputs (reg_names[REGNO (x)], file); 9494 else if (GET_CODE (x) == MEM) 9495 { 9496 fputc ('[', file); 9497 /* Poor Sun assembler doesn't understand absolute addressing. */ 9498 if (CONSTANT_P (XEXP (x, 0))) 9499 fputs ("%g0+", file); 9500 output_address (GET_MODE (x), XEXP (x, 0)); 9501 fputc (']', file); 9502 } 9503 else if (GET_CODE (x) == HIGH) 9504 { 9505 fputs ("%hi(", file); 9506 output_addr_const (file, XEXP (x, 0)); 9507 fputc (')', file); 9508 } 9509 else if (GET_CODE (x) == LO_SUM) 9510 { 9511 sparc_print_operand (file, XEXP (x, 0), 0); 9512 if (TARGET_CM_MEDMID) 9513 fputs ("+%l44(", file); 9514 else 9515 fputs ("+%lo(", file); 9516 output_addr_const (file, XEXP (x, 1)); 9517 fputc (')', file); 9518 } 9519 else if (GET_CODE (x) == CONST_DOUBLE) 9520 output_operand_lossage ("floating-point constant not a valid immediate operand"); 9521 else 9522 output_addr_const (file, x); 9523 } 9524 9525 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ 9526 9527 static void 9528 sparc_print_operand_address (FILE *file, machine_mode /*mode*/, rtx x) 9529 { 9530 register rtx base, index = 0; 9531 int offset = 0; 9532 register rtx addr = x; 9533 9534 if (REG_P (addr)) 9535 fputs (reg_names[REGNO (addr)], file); 9536 else if (GET_CODE (addr) == PLUS) 9537 { 9538 if (CONST_INT_P (XEXP (addr, 0))) 9539 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); 9540 else if (CONST_INT_P (XEXP (addr, 1))) 9541 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); 9542 else 9543 base = XEXP (addr, 0), index = XEXP (addr, 1); 9544 if (GET_CODE (base) == LO_SUM) 9545 { 9546 gcc_assert (USE_AS_OFFSETABLE_LO10 9547 && TARGET_ARCH64 9548 && ! TARGET_CM_MEDMID); 9549 output_operand (XEXP (base, 0), 0); 9550 fputs ("+%lo(", file); 9551 output_address (VOIDmode, XEXP (base, 1)); 9552 fprintf (file, ")+%d", offset); 9553 } 9554 else 9555 { 9556 fputs (reg_names[REGNO (base)], file); 9557 if (index == 0) 9558 fprintf (file, "%+d", offset); 9559 else if (REG_P (index)) 9560 fprintf (file, "+%s", reg_names[REGNO (index)]); 9561 else if (GET_CODE (index) == SYMBOL_REF 9562 || GET_CODE (index) == LABEL_REF 9563 || GET_CODE (index) == CONST) 9564 fputc ('+', file), output_addr_const (file, index); 9565 else gcc_unreachable (); 9566 } 9567 } 9568 else if (GET_CODE (addr) == MINUS 9569 && GET_CODE (XEXP (addr, 1)) == LABEL_REF) 9570 { 9571 output_addr_const (file, XEXP (addr, 0)); 9572 fputs ("-(", file); 9573 output_addr_const (file, XEXP (addr, 1)); 9574 fputs ("-.)", file); 9575 } 9576 else if (GET_CODE (addr) == LO_SUM) 9577 { 9578 output_operand (XEXP (addr, 0), 0); 9579 if (TARGET_CM_MEDMID) 9580 fputs ("+%l44(", file); 9581 else 9582 fputs ("+%lo(", file); 9583 output_address (VOIDmode, XEXP (addr, 1)); 9584 fputc (')', file); 9585 } 9586 else if (flag_pic 9587 && GET_CODE (addr) == CONST 9588 && GET_CODE (XEXP (addr, 0)) == MINUS 9589 && GET_CODE (XEXP (XEXP (addr, 0), 1)) == CONST 9590 && GET_CODE (XEXP (XEXP (XEXP (addr, 0), 1), 0)) == MINUS 9591 && XEXP (XEXP (XEXP (XEXP (addr, 0), 1), 0), 1) == pc_rtx) 9592 { 9593 addr = XEXP (addr, 0); 9594 output_addr_const (file, XEXP (addr, 0)); 9595 /* Group the args of the second CONST in parenthesis. */ 9596 fputs ("-(", file); 9597 /* Skip past the second CONST--it does nothing for us. */ 9598 output_addr_const (file, XEXP (XEXP (addr, 1), 0)); 9599 /* Close the parenthesis. */ 9600 fputc (')', file); 9601 } 9602 else 9603 { 9604 output_addr_const (file, addr); 9605 } 9606 } 9607 9608 /* Target hook for assembling integer objects. The sparc version has 9609 special handling for aligned DI-mode objects. */ 9610 9611 static bool 9612 sparc_assemble_integer (rtx x, unsigned int size, int aligned_p) 9613 { 9614 /* ??? We only output .xword's for symbols and only then in environments 9615 where the assembler can handle them. */ 9616 if (aligned_p && size == 8 && GET_CODE (x) != CONST_INT) 9617 { 9618 if (TARGET_V9) 9619 { 9620 assemble_integer_with_op ("\t.xword\t", x); 9621 return true; 9622 } 9623 else 9624 { 9625 assemble_aligned_integer (4, const0_rtx); 9626 assemble_aligned_integer (4, x); 9627 return true; 9628 } 9629 } 9630 return default_assemble_integer (x, size, aligned_p); 9631 } 9632 9633 /* Return the value of a code used in the .proc pseudo-op that says 9634 what kind of result this function returns. For non-C types, we pick 9635 the closest C type. */ 9636 9637 #ifndef SHORT_TYPE_SIZE 9638 #define SHORT_TYPE_SIZE (BITS_PER_UNIT * 2) 9639 #endif 9640 9641 #ifndef INT_TYPE_SIZE 9642 #define INT_TYPE_SIZE BITS_PER_WORD 9643 #endif 9644 9645 #ifndef LONG_TYPE_SIZE 9646 #define LONG_TYPE_SIZE BITS_PER_WORD 9647 #endif 9648 9649 #ifndef LONG_LONG_TYPE_SIZE 9650 #define LONG_LONG_TYPE_SIZE (BITS_PER_WORD * 2) 9651 #endif 9652 9653 #ifndef FLOAT_TYPE_SIZE 9654 #define FLOAT_TYPE_SIZE BITS_PER_WORD 9655 #endif 9656 9657 #ifndef DOUBLE_TYPE_SIZE 9658 #define DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 9659 #endif 9660 9661 #ifndef LONG_DOUBLE_TYPE_SIZE 9662 #define LONG_DOUBLE_TYPE_SIZE (BITS_PER_WORD * 2) 9663 #endif 9664 9665 unsigned long 9666 sparc_type_code (register tree type) 9667 { 9668 register unsigned long qualifiers = 0; 9669 register unsigned shift; 9670 9671 /* Only the first 30 bits of the qualifier are valid. We must refrain from 9672 setting more, since some assemblers will give an error for this. Also, 9673 we must be careful to avoid shifts of 32 bits or more to avoid getting 9674 unpredictable results. */ 9675 9676 for (shift = 6; shift < 30; shift += 2, type = TREE_TYPE (type)) 9677 { 9678 switch (TREE_CODE (type)) 9679 { 9680 case ERROR_MARK: 9681 return qualifiers; 9682 9683 case ARRAY_TYPE: 9684 qualifiers |= (3 << shift); 9685 break; 9686 9687 case FUNCTION_TYPE: 9688 case METHOD_TYPE: 9689 qualifiers |= (2 << shift); 9690 break; 9691 9692 case POINTER_TYPE: 9693 case REFERENCE_TYPE: 9694 case OFFSET_TYPE: 9695 qualifiers |= (1 << shift); 9696 break; 9697 9698 case RECORD_TYPE: 9699 return (qualifiers | 8); 9700 9701 case UNION_TYPE: 9702 case QUAL_UNION_TYPE: 9703 return (qualifiers | 9); 9704 9705 case ENUMERAL_TYPE: 9706 return (qualifiers | 10); 9707 9708 case VOID_TYPE: 9709 return (qualifiers | 16); 9710 9711 case INTEGER_TYPE: 9712 /* If this is a range type, consider it to be the underlying 9713 type. */ 9714 if (TREE_TYPE (type) != 0) 9715 break; 9716 9717 /* Carefully distinguish all the standard types of C, 9718 without messing up if the language is not C. We do this by 9719 testing TYPE_PRECISION and TYPE_UNSIGNED. The old code used to 9720 look at both the names and the above fields, but that's redundant. 9721 Any type whose size is between two C types will be considered 9722 to be the wider of the two types. Also, we do not have a 9723 special code to use for "long long", so anything wider than 9724 long is treated the same. Note that we can't distinguish 9725 between "int" and "long" in this code if they are the same 9726 size, but that's fine, since neither can the assembler. */ 9727 9728 if (TYPE_PRECISION (type) <= CHAR_TYPE_SIZE) 9729 return (qualifiers | (TYPE_UNSIGNED (type) ? 12 : 2)); 9730 9731 else if (TYPE_PRECISION (type) <= SHORT_TYPE_SIZE) 9732 return (qualifiers | (TYPE_UNSIGNED (type) ? 13 : 3)); 9733 9734 else if (TYPE_PRECISION (type) <= INT_TYPE_SIZE) 9735 return (qualifiers | (TYPE_UNSIGNED (type) ? 14 : 4)); 9736 9737 else 9738 return (qualifiers | (TYPE_UNSIGNED (type) ? 15 : 5)); 9739 9740 case REAL_TYPE: 9741 /* If this is a range type, consider it to be the underlying 9742 type. */ 9743 if (TREE_TYPE (type) != 0) 9744 break; 9745 9746 /* Carefully distinguish all the standard types of C, 9747 without messing up if the language is not C. */ 9748 9749 if (TYPE_PRECISION (type) == FLOAT_TYPE_SIZE) 9750 return (qualifiers | 6); 9751 9752 else 9753 return (qualifiers | 7); 9754 9755 case COMPLEX_TYPE: /* GNU Fortran COMPLEX type. */ 9756 /* ??? We need to distinguish between double and float complex types, 9757 but I don't know how yet because I can't reach this code from 9758 existing front-ends. */ 9759 return (qualifiers | 7); /* Who knows? */ 9760 9761 case VECTOR_TYPE: 9762 case BOOLEAN_TYPE: /* Boolean truth value type. */ 9763 case LANG_TYPE: 9764 case NULLPTR_TYPE: 9765 return qualifiers; 9766 9767 default: 9768 gcc_unreachable (); /* Not a type! */ 9769 } 9770 } 9771 9772 return qualifiers; 9773 } 9774 9775 /* Nested function support. */ 9776 9777 /* Emit RTL insns to initialize the variable parts of a trampoline. 9778 FNADDR is an RTX for the address of the function's pure code. 9779 CXT is an RTX for the static chain value for the function. 9780 9781 This takes 16 insns: 2 shifts & 2 ands (to split up addresses), 4 sethi 9782 (to load in opcodes), 4 iors (to merge address and opcodes), and 4 writes 9783 (to store insns). This is a bit excessive. Perhaps a different 9784 mechanism would be better here. 9785 9786 Emit enough FLUSH insns to synchronize the data and instruction caches. */ 9787 9788 static void 9789 sparc32_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) 9790 { 9791 /* SPARC 32-bit trampoline: 9792 9793 sethi %hi(fn), %g1 9794 sethi %hi(static), %g2 9795 jmp %g1+%lo(fn) 9796 or %g2, %lo(static), %g2 9797 9798 SETHI i,r = 00rr rrr1 00ii iiii iiii iiii iiii iiii 9799 JMPL r+i,d = 10dd ddd1 1100 0rrr rr1i iiii iiii iiii 9800 */ 9801 9802 emit_move_insn 9803 (adjust_address (m_tramp, SImode, 0), 9804 expand_binop (SImode, ior_optab, 9805 expand_shift (RSHIFT_EXPR, SImode, fnaddr, 10, 0, 1), 9806 GEN_INT (trunc_int_for_mode (0x03000000, SImode)), 9807 NULL_RTX, 1, OPTAB_DIRECT)); 9808 9809 emit_move_insn 9810 (adjust_address (m_tramp, SImode, 4), 9811 expand_binop (SImode, ior_optab, 9812 expand_shift (RSHIFT_EXPR, SImode, cxt, 10, 0, 1), 9813 GEN_INT (trunc_int_for_mode (0x05000000, SImode)), 9814 NULL_RTX, 1, OPTAB_DIRECT)); 9815 9816 emit_move_insn 9817 (adjust_address (m_tramp, SImode, 8), 9818 expand_binop (SImode, ior_optab, 9819 expand_and (SImode, fnaddr, GEN_INT (0x3ff), NULL_RTX), 9820 GEN_INT (trunc_int_for_mode (0x81c06000, SImode)), 9821 NULL_RTX, 1, OPTAB_DIRECT)); 9822 9823 emit_move_insn 9824 (adjust_address (m_tramp, SImode, 12), 9825 expand_binop (SImode, ior_optab, 9826 expand_and (SImode, cxt, GEN_INT (0x3ff), NULL_RTX), 9827 GEN_INT (trunc_int_for_mode (0x8410a000, SImode)), 9828 NULL_RTX, 1, OPTAB_DIRECT)); 9829 9830 /* On UltraSPARC a flush flushes an entire cache line. The trampoline is 9831 aligned on a 16 byte boundary so one flush clears it all. */ 9832 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 0)))); 9833 if (sparc_cpu != PROCESSOR_ULTRASPARC 9834 && sparc_cpu != PROCESSOR_ULTRASPARC3 9835 && sparc_cpu != PROCESSOR_NIAGARA 9836 && sparc_cpu != PROCESSOR_NIAGARA2 9837 && sparc_cpu != PROCESSOR_NIAGARA3 9838 && sparc_cpu != PROCESSOR_NIAGARA4 9839 && sparc_cpu != PROCESSOR_NIAGARA7 9840 && sparc_cpu != PROCESSOR_M8) 9841 emit_insn (gen_flushsi (validize_mem (adjust_address (m_tramp, SImode, 8)))); 9842 9843 /* Call __enable_execute_stack after writing onto the stack to make sure 9844 the stack address is accessible. */ 9845 #ifdef HAVE_ENABLE_EXECUTE_STACK 9846 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), 9847 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode); 9848 #endif 9849 9850 } 9851 9852 /* The 64-bit version is simpler because it makes more sense to load the 9853 values as "immediate" data out of the trampoline. It's also easier since 9854 we can read the PC without clobbering a register. */ 9855 9856 static void 9857 sparc64_initialize_trampoline (rtx m_tramp, rtx fnaddr, rtx cxt) 9858 { 9859 /* SPARC 64-bit trampoline: 9860 9861 rd %pc, %g1 9862 ldx [%g1+24], %g5 9863 jmp %g5 9864 ldx [%g1+16], %g5 9865 +16 bytes data 9866 */ 9867 9868 emit_move_insn (adjust_address (m_tramp, SImode, 0), 9869 GEN_INT (trunc_int_for_mode (0x83414000, SImode))); 9870 emit_move_insn (adjust_address (m_tramp, SImode, 4), 9871 GEN_INT (trunc_int_for_mode (0xca586018, SImode))); 9872 emit_move_insn (adjust_address (m_tramp, SImode, 8), 9873 GEN_INT (trunc_int_for_mode (0x81c14000, SImode))); 9874 emit_move_insn (adjust_address (m_tramp, SImode, 12), 9875 GEN_INT (trunc_int_for_mode (0xca586010, SImode))); 9876 emit_move_insn (adjust_address (m_tramp, DImode, 16), cxt); 9877 emit_move_insn (adjust_address (m_tramp, DImode, 24), fnaddr); 9878 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 0)))); 9879 9880 if (sparc_cpu != PROCESSOR_ULTRASPARC 9881 && sparc_cpu != PROCESSOR_ULTRASPARC3 9882 && sparc_cpu != PROCESSOR_NIAGARA 9883 && sparc_cpu != PROCESSOR_NIAGARA2 9884 && sparc_cpu != PROCESSOR_NIAGARA3 9885 && sparc_cpu != PROCESSOR_NIAGARA4 9886 && sparc_cpu != PROCESSOR_NIAGARA7 9887 && sparc_cpu != PROCESSOR_M8) 9888 emit_insn (gen_flushdi (validize_mem (adjust_address (m_tramp, DImode, 8)))); 9889 9890 /* Call __enable_execute_stack after writing onto the stack to make sure 9891 the stack address is accessible. */ 9892 #ifdef HAVE_ENABLE_EXECUTE_STACK 9893 emit_library_call (gen_rtx_SYMBOL_REF (Pmode, "__enable_execute_stack"), 9894 LCT_NORMAL, VOIDmode, 1, XEXP (m_tramp, 0), Pmode); 9895 #endif 9896 } 9897 9898 /* Worker for TARGET_TRAMPOLINE_INIT. */ 9899 9900 static void 9901 sparc_trampoline_init (rtx m_tramp, tree fndecl, rtx cxt) 9902 { 9903 rtx fnaddr = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0)); 9904 cxt = force_reg (Pmode, cxt); 9905 if (TARGET_ARCH64) 9906 sparc64_initialize_trampoline (m_tramp, fnaddr, cxt); 9907 else 9908 sparc32_initialize_trampoline (m_tramp, fnaddr, cxt); 9909 } 9910 9911 /* Adjust the cost of a scheduling dependency. Return the new cost of 9912 a dependency LINK or INSN on DEP_INSN. COST is the current cost. */ 9913 9914 static int 9915 supersparc_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep_insn, 9916 int cost) 9917 { 9918 enum attr_type insn_type; 9919 9920 if (recog_memoized (insn) < 0) 9921 return cost; 9922 9923 insn_type = get_attr_type (insn); 9924 9925 if (dep_type == 0) 9926 { 9927 /* Data dependency; DEP_INSN writes a register that INSN reads some 9928 cycles later. */ 9929 9930 /* if a load, then the dependence must be on the memory address; 9931 add an extra "cycle". Note that the cost could be two cycles 9932 if the reg was written late in an instruction group; we ca not tell 9933 here. */ 9934 if (insn_type == TYPE_LOAD || insn_type == TYPE_FPLOAD) 9935 return cost + 3; 9936 9937 /* Get the delay only if the address of the store is the dependence. */ 9938 if (insn_type == TYPE_STORE || insn_type == TYPE_FPSTORE) 9939 { 9940 rtx pat = PATTERN(insn); 9941 rtx dep_pat = PATTERN (dep_insn); 9942 9943 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 9944 return cost; /* This should not happen! */ 9945 9946 /* The dependency between the two instructions was on the data that 9947 is being stored. Assume that this implies that the address of the 9948 store is not dependent. */ 9949 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 9950 return cost; 9951 9952 return cost + 3; /* An approximation. */ 9953 } 9954 9955 /* A shift instruction cannot receive its data from an instruction 9956 in the same cycle; add a one cycle penalty. */ 9957 if (insn_type == TYPE_SHIFT) 9958 return cost + 3; /* Split before cascade into shift. */ 9959 } 9960 else 9961 { 9962 /* Anti- or output- dependency; DEP_INSN reads/writes a register that 9963 INSN writes some cycles later. */ 9964 9965 /* These are only significant for the fpu unit; writing a fp reg before 9966 the fpu has finished with it stalls the processor. */ 9967 9968 /* Reusing an integer register causes no problems. */ 9969 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 9970 return 0; 9971 } 9972 9973 return cost; 9974 } 9975 9976 static int 9977 hypersparc_adjust_cost (rtx_insn *insn, int dtype, rtx_insn *dep_insn, 9978 int cost) 9979 { 9980 enum attr_type insn_type, dep_type; 9981 rtx pat = PATTERN(insn); 9982 rtx dep_pat = PATTERN (dep_insn); 9983 9984 if (recog_memoized (insn) < 0 || recog_memoized (dep_insn) < 0) 9985 return cost; 9986 9987 insn_type = get_attr_type (insn); 9988 dep_type = get_attr_type (dep_insn); 9989 9990 switch (dtype) 9991 { 9992 case 0: 9993 /* Data dependency; DEP_INSN writes a register that INSN reads some 9994 cycles later. */ 9995 9996 switch (insn_type) 9997 { 9998 case TYPE_STORE: 9999 case TYPE_FPSTORE: 10000 /* Get the delay iff the address of the store is the dependence. */ 10001 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET) 10002 return cost; 10003 10004 if (rtx_equal_p (SET_DEST (dep_pat), SET_SRC (pat))) 10005 return cost; 10006 return cost + 3; 10007 10008 case TYPE_LOAD: 10009 case TYPE_SLOAD: 10010 case TYPE_FPLOAD: 10011 /* If a load, then the dependence must be on the memory address. If 10012 the addresses aren't equal, then it might be a false dependency */ 10013 if (dep_type == TYPE_STORE || dep_type == TYPE_FPSTORE) 10014 { 10015 if (GET_CODE (pat) != SET || GET_CODE (dep_pat) != SET 10016 || GET_CODE (SET_DEST (dep_pat)) != MEM 10017 || GET_CODE (SET_SRC (pat)) != MEM 10018 || ! rtx_equal_p (XEXP (SET_DEST (dep_pat), 0), 10019 XEXP (SET_SRC (pat), 0))) 10020 return cost + 2; 10021 10022 return cost + 8; 10023 } 10024 break; 10025 10026 case TYPE_BRANCH: 10027 /* Compare to branch latency is 0. There is no benefit from 10028 separating compare and branch. */ 10029 if (dep_type == TYPE_COMPARE) 10030 return 0; 10031 /* Floating point compare to branch latency is less than 10032 compare to conditional move. */ 10033 if (dep_type == TYPE_FPCMP) 10034 return cost - 1; 10035 break; 10036 default: 10037 break; 10038 } 10039 break; 10040 10041 case REG_DEP_ANTI: 10042 /* Anti-dependencies only penalize the fpu unit. */ 10043 if (insn_type == TYPE_IALU || insn_type == TYPE_SHIFT) 10044 return 0; 10045 break; 10046 10047 default: 10048 break; 10049 } 10050 10051 return cost; 10052 } 10053 10054 static int 10055 sparc_adjust_cost (rtx_insn *insn, int dep_type, rtx_insn *dep, int cost, 10056 unsigned int) 10057 { 10058 switch (sparc_cpu) 10059 { 10060 case PROCESSOR_SUPERSPARC: 10061 cost = supersparc_adjust_cost (insn, dep_type, dep, cost); 10062 break; 10063 case PROCESSOR_HYPERSPARC: 10064 case PROCESSOR_SPARCLITE86X: 10065 cost = hypersparc_adjust_cost (insn, dep_type, dep, cost); 10066 break; 10067 default: 10068 break; 10069 } 10070 return cost; 10071 } 10072 10073 static void 10074 sparc_sched_init (FILE *dump ATTRIBUTE_UNUSED, 10075 int sched_verbose ATTRIBUTE_UNUSED, 10076 int max_ready ATTRIBUTE_UNUSED) 10077 {} 10078 10079 static int 10080 sparc_use_sched_lookahead (void) 10081 { 10082 if (sparc_cpu == PROCESSOR_NIAGARA 10083 || sparc_cpu == PROCESSOR_NIAGARA2 10084 || sparc_cpu == PROCESSOR_NIAGARA3) 10085 return 0; 10086 if (sparc_cpu == PROCESSOR_NIAGARA4 10087 || sparc_cpu == PROCESSOR_NIAGARA7 10088 || sparc_cpu == PROCESSOR_M8) 10089 return 2; 10090 if (sparc_cpu == PROCESSOR_ULTRASPARC 10091 || sparc_cpu == PROCESSOR_ULTRASPARC3) 10092 return 4; 10093 if ((1 << sparc_cpu) & 10094 ((1 << PROCESSOR_SUPERSPARC) | (1 << PROCESSOR_HYPERSPARC) | 10095 (1 << PROCESSOR_SPARCLITE86X))) 10096 return 3; 10097 return 0; 10098 } 10099 10100 static int 10101 sparc_issue_rate (void) 10102 { 10103 switch (sparc_cpu) 10104 { 10105 case PROCESSOR_NIAGARA: 10106 case PROCESSOR_NIAGARA2: 10107 case PROCESSOR_NIAGARA3: 10108 default: 10109 return 1; 10110 case PROCESSOR_NIAGARA4: 10111 case PROCESSOR_NIAGARA7: 10112 case PROCESSOR_V9: 10113 /* Assume V9 processors are capable of at least dual-issue. */ 10114 return 2; 10115 case PROCESSOR_SUPERSPARC: 10116 return 3; 10117 case PROCESSOR_HYPERSPARC: 10118 case PROCESSOR_SPARCLITE86X: 10119 return 2; 10120 case PROCESSOR_ULTRASPARC: 10121 case PROCESSOR_ULTRASPARC3: 10122 case PROCESSOR_M8: 10123 return 4; 10124 } 10125 } 10126 10127 static int 10128 set_extends (rtx_insn *insn) 10129 { 10130 register rtx pat = PATTERN (insn); 10131 10132 switch (GET_CODE (SET_SRC (pat))) 10133 { 10134 /* Load and some shift instructions zero extend. */ 10135 case MEM: 10136 case ZERO_EXTEND: 10137 /* sethi clears the high bits */ 10138 case HIGH: 10139 /* LO_SUM is used with sethi. sethi cleared the high 10140 bits and the values used with lo_sum are positive */ 10141 case LO_SUM: 10142 /* Store flag stores 0 or 1 */ 10143 case LT: case LTU: 10144 case GT: case GTU: 10145 case LE: case LEU: 10146 case GE: case GEU: 10147 case EQ: 10148 case NE: 10149 return 1; 10150 case AND: 10151 { 10152 rtx op0 = XEXP (SET_SRC (pat), 0); 10153 rtx op1 = XEXP (SET_SRC (pat), 1); 10154 if (GET_CODE (op1) == CONST_INT) 10155 return INTVAL (op1) >= 0; 10156 if (GET_CODE (op0) != REG) 10157 return 0; 10158 if (sparc_check_64 (op0, insn) == 1) 10159 return 1; 10160 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 10161 } 10162 case IOR: 10163 case XOR: 10164 { 10165 rtx op0 = XEXP (SET_SRC (pat), 0); 10166 rtx op1 = XEXP (SET_SRC (pat), 1); 10167 if (GET_CODE (op0) != REG || sparc_check_64 (op0, insn) <= 0) 10168 return 0; 10169 if (GET_CODE (op1) == CONST_INT) 10170 return INTVAL (op1) >= 0; 10171 return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1); 10172 } 10173 case LSHIFTRT: 10174 return GET_MODE (SET_SRC (pat)) == SImode; 10175 /* Positive integers leave the high bits zero. */ 10176 case CONST_INT: 10177 return !(INTVAL (SET_SRC (pat)) & 0x80000000); 10178 case ASHIFTRT: 10179 case SIGN_EXTEND: 10180 return - (GET_MODE (SET_SRC (pat)) == SImode); 10181 case REG: 10182 return sparc_check_64 (SET_SRC (pat), insn); 10183 default: 10184 return 0; 10185 } 10186 } 10187 10188 /* We _ought_ to have only one kind per function, but... */ 10189 static GTY(()) rtx sparc_addr_diff_list; 10190 static GTY(()) rtx sparc_addr_list; 10191 10192 void 10193 sparc_defer_case_vector (rtx lab, rtx vec, int diff) 10194 { 10195 vec = gen_rtx_EXPR_LIST (VOIDmode, lab, vec); 10196 if (diff) 10197 sparc_addr_diff_list 10198 = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_diff_list); 10199 else 10200 sparc_addr_list = gen_rtx_EXPR_LIST (VOIDmode, vec, sparc_addr_list); 10201 } 10202 10203 static void 10204 sparc_output_addr_vec (rtx vec) 10205 { 10206 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 10207 int idx, vlen = XVECLEN (body, 0); 10208 10209 #ifdef ASM_OUTPUT_ADDR_VEC_START 10210 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 10211 #endif 10212 10213 #ifdef ASM_OUTPUT_CASE_LABEL 10214 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 10215 NEXT_INSN (lab)); 10216 #else 10217 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 10218 #endif 10219 10220 for (idx = 0; idx < vlen; idx++) 10221 { 10222 ASM_OUTPUT_ADDR_VEC_ELT 10223 (asm_out_file, CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 0, idx), 0))); 10224 } 10225 10226 #ifdef ASM_OUTPUT_ADDR_VEC_END 10227 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 10228 #endif 10229 } 10230 10231 static void 10232 sparc_output_addr_diff_vec (rtx vec) 10233 { 10234 rtx lab = XEXP (vec, 0), body = XEXP (vec, 1); 10235 rtx base = XEXP (XEXP (body, 0), 0); 10236 int idx, vlen = XVECLEN (body, 1); 10237 10238 #ifdef ASM_OUTPUT_ADDR_VEC_START 10239 ASM_OUTPUT_ADDR_VEC_START (asm_out_file); 10240 #endif 10241 10242 #ifdef ASM_OUTPUT_CASE_LABEL 10243 ASM_OUTPUT_CASE_LABEL (asm_out_file, "L", CODE_LABEL_NUMBER (lab), 10244 NEXT_INSN (lab)); 10245 #else 10246 (*targetm.asm_out.internal_label) (asm_out_file, "L", CODE_LABEL_NUMBER (lab)); 10247 #endif 10248 10249 for (idx = 0; idx < vlen; idx++) 10250 { 10251 ASM_OUTPUT_ADDR_DIFF_ELT 10252 (asm_out_file, 10253 body, 10254 CODE_LABEL_NUMBER (XEXP (XVECEXP (body, 1, idx), 0)), 10255 CODE_LABEL_NUMBER (base)); 10256 } 10257 10258 #ifdef ASM_OUTPUT_ADDR_VEC_END 10259 ASM_OUTPUT_ADDR_VEC_END (asm_out_file); 10260 #endif 10261 } 10262 10263 static void 10264 sparc_output_deferred_case_vectors (void) 10265 { 10266 rtx t; 10267 int align; 10268 10269 if (sparc_addr_list == NULL_RTX 10270 && sparc_addr_diff_list == NULL_RTX) 10271 return; 10272 10273 /* Align to cache line in the function's code section. */ 10274 switch_to_section (current_function_section ()); 10275 10276 align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 10277 if (align > 0) 10278 ASM_OUTPUT_ALIGN (asm_out_file, align); 10279 10280 for (t = sparc_addr_list; t ; t = XEXP (t, 1)) 10281 sparc_output_addr_vec (XEXP (t, 0)); 10282 for (t = sparc_addr_diff_list; t ; t = XEXP (t, 1)) 10283 sparc_output_addr_diff_vec (XEXP (t, 0)); 10284 10285 sparc_addr_list = sparc_addr_diff_list = NULL_RTX; 10286 } 10287 10288 /* Return 0 if the high 32 bits of X (the low word of X, if DImode) are 10289 unknown. Return 1 if the high bits are zero, -1 if the register is 10290 sign extended. */ 10291 int 10292 sparc_check_64 (rtx x, rtx_insn *insn) 10293 { 10294 /* If a register is set only once it is safe to ignore insns this 10295 code does not know how to handle. The loop will either recognize 10296 the single set and return the correct value or fail to recognize 10297 it and return 0. */ 10298 int set_once = 0; 10299 rtx y = x; 10300 10301 gcc_assert (GET_CODE (x) == REG); 10302 10303 if (GET_MODE (x) == DImode) 10304 y = gen_rtx_REG (SImode, REGNO (x) + WORDS_BIG_ENDIAN); 10305 10306 if (flag_expensive_optimizations 10307 && df && DF_REG_DEF_COUNT (REGNO (y)) == 1) 10308 set_once = 1; 10309 10310 if (insn == 0) 10311 { 10312 if (set_once) 10313 insn = get_last_insn_anywhere (); 10314 else 10315 return 0; 10316 } 10317 10318 while ((insn = PREV_INSN (insn))) 10319 { 10320 switch (GET_CODE (insn)) 10321 { 10322 case JUMP_INSN: 10323 case NOTE: 10324 break; 10325 case CODE_LABEL: 10326 case CALL_INSN: 10327 default: 10328 if (! set_once) 10329 return 0; 10330 break; 10331 case INSN: 10332 { 10333 rtx pat = PATTERN (insn); 10334 if (GET_CODE (pat) != SET) 10335 return 0; 10336 if (rtx_equal_p (x, SET_DEST (pat))) 10337 return set_extends (insn); 10338 if (y && rtx_equal_p (y, SET_DEST (pat))) 10339 return set_extends (insn); 10340 if (reg_overlap_mentioned_p (SET_DEST (pat), y)) 10341 return 0; 10342 } 10343 } 10344 } 10345 return 0; 10346 } 10347 10348 /* Output a wide shift instruction in V8+ mode. INSN is the instruction, 10349 OPERANDS are its operands and OPCODE is the mnemonic to be used. */ 10350 10351 const char * 10352 output_v8plus_shift (rtx_insn *insn, rtx *operands, const char *opcode) 10353 { 10354 static char asm_code[60]; 10355 10356 /* The scratch register is only required when the destination 10357 register is not a 64-bit global or out register. */ 10358 if (which_alternative != 2) 10359 operands[3] = operands[0]; 10360 10361 /* We can only shift by constants <= 63. */ 10362 if (GET_CODE (operands[2]) == CONST_INT) 10363 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 10364 10365 if (GET_CODE (operands[1]) == CONST_INT) 10366 { 10367 output_asm_insn ("mov\t%1, %3", operands); 10368 } 10369 else 10370 { 10371 output_asm_insn ("sllx\t%H1, 32, %3", operands); 10372 if (sparc_check_64 (operands[1], insn) <= 0) 10373 output_asm_insn ("srl\t%L1, 0, %L1", operands); 10374 output_asm_insn ("or\t%L1, %3, %3", operands); 10375 } 10376 10377 strcpy (asm_code, opcode); 10378 10379 if (which_alternative != 2) 10380 return strcat (asm_code, "\t%0, %2, %L0\n\tsrlx\t%L0, 32, %H0"); 10381 else 10382 return 10383 strcat (asm_code, "\t%3, %2, %3\n\tsrlx\t%3, 32, %H0\n\tmov\t%3, %L0"); 10384 } 10385 10386 /* Output rtl to increment the profiler label LABELNO 10387 for profiling a function entry. */ 10388 10389 void 10390 sparc_profile_hook (int labelno) 10391 { 10392 char buf[32]; 10393 rtx lab, fun; 10394 10395 fun = gen_rtx_SYMBOL_REF (Pmode, MCOUNT_FUNCTION); 10396 if (NO_PROFILE_COUNTERS) 10397 { 10398 emit_library_call (fun, LCT_NORMAL, VOIDmode, 0); 10399 } 10400 else 10401 { 10402 ASM_GENERATE_INTERNAL_LABEL (buf, "LP", labelno); 10403 lab = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 10404 emit_library_call (fun, LCT_NORMAL, VOIDmode, 1, lab, Pmode); 10405 } 10406 } 10407 10408 #ifdef TARGET_SOLARIS 10409 /* Solaris implementation of TARGET_ASM_NAMED_SECTION. */ 10410 10411 static void 10412 sparc_solaris_elf_asm_named_section (const char *name, unsigned int flags, 10413 tree decl ATTRIBUTE_UNUSED) 10414 { 10415 if (HAVE_COMDAT_GROUP && flags & SECTION_LINKONCE) 10416 { 10417 solaris_elf_asm_comdat_section (name, flags, decl); 10418 return; 10419 } 10420 10421 fprintf (asm_out_file, "\t.section\t\"%s\"", name); 10422 10423 if (!(flags & SECTION_DEBUG)) 10424 fputs (",#alloc", asm_out_file); 10425 if (flags & SECTION_WRITE) 10426 fputs (",#write", asm_out_file); 10427 if (flags & SECTION_TLS) 10428 fputs (",#tls", asm_out_file); 10429 if (flags & SECTION_CODE) 10430 fputs (",#execinstr", asm_out_file); 10431 10432 if (flags & SECTION_NOTYPE) 10433 ; 10434 else if (flags & SECTION_BSS) 10435 fputs (",#nobits", asm_out_file); 10436 else 10437 fputs (",#progbits", asm_out_file); 10438 10439 fputc ('\n', asm_out_file); 10440 } 10441 #endif /* TARGET_SOLARIS */ 10442 10443 /* We do not allow indirect calls to be optimized into sibling calls. 10444 10445 We cannot use sibling calls when delayed branches are disabled 10446 because they will likely require the call delay slot to be filled. 10447 10448 Also, on SPARC 32-bit we cannot emit a sibling call when the 10449 current function returns a structure. This is because the "unimp 10450 after call" convention would cause the callee to return to the 10451 wrong place. The generic code already disallows cases where the 10452 function being called returns a structure. 10453 10454 It may seem strange how this last case could occur. Usually there 10455 is code after the call which jumps to epilogue code which dumps the 10456 return value into the struct return area. That ought to invalidate 10457 the sibling call right? Well, in the C++ case we can end up passing 10458 the pointer to the struct return area to a constructor (which returns 10459 void) and then nothing else happens. Such a sibling call would look 10460 valid without the added check here. 10461 10462 VxWorks PIC PLT entries require the global pointer to be initialized 10463 on entry. We therefore can't emit sibling calls to them. */ 10464 static bool 10465 sparc_function_ok_for_sibcall (tree decl, tree exp ATTRIBUTE_UNUSED) 10466 { 10467 return (decl 10468 && flag_delayed_branch 10469 && (TARGET_ARCH64 || ! cfun->returns_struct) 10470 && !(TARGET_VXWORKS_RTP 10471 && flag_pic 10472 && !targetm.binds_local_p (decl))); 10473 } 10474 10475 /* libfunc renaming. */ 10476 10477 static void 10478 sparc_init_libfuncs (void) 10479 { 10480 if (TARGET_ARCH32) 10481 { 10482 /* Use the subroutines that Sun's library provides for integer 10483 multiply and divide. The `*' prevents an underscore from 10484 being prepended by the compiler. .umul is a little faster 10485 than .mul. */ 10486 set_optab_libfunc (smul_optab, SImode, "*.umul"); 10487 set_optab_libfunc (sdiv_optab, SImode, "*.div"); 10488 set_optab_libfunc (udiv_optab, SImode, "*.udiv"); 10489 set_optab_libfunc (smod_optab, SImode, "*.rem"); 10490 set_optab_libfunc (umod_optab, SImode, "*.urem"); 10491 10492 /* TFmode arithmetic. These names are part of the SPARC 32bit ABI. */ 10493 set_optab_libfunc (add_optab, TFmode, "_Q_add"); 10494 set_optab_libfunc (sub_optab, TFmode, "_Q_sub"); 10495 set_optab_libfunc (neg_optab, TFmode, "_Q_neg"); 10496 set_optab_libfunc (smul_optab, TFmode, "_Q_mul"); 10497 set_optab_libfunc (sdiv_optab, TFmode, "_Q_div"); 10498 10499 /* We can define the TFmode sqrt optab only if TARGET_FPU. This 10500 is because with soft-float, the SFmode and DFmode sqrt 10501 instructions will be absent, and the compiler will notice and 10502 try to use the TFmode sqrt instruction for calls to the 10503 builtin function sqrt, but this fails. */ 10504 if (TARGET_FPU) 10505 set_optab_libfunc (sqrt_optab, TFmode, "_Q_sqrt"); 10506 10507 set_optab_libfunc (eq_optab, TFmode, "_Q_feq"); 10508 set_optab_libfunc (ne_optab, TFmode, "_Q_fne"); 10509 set_optab_libfunc (gt_optab, TFmode, "_Q_fgt"); 10510 set_optab_libfunc (ge_optab, TFmode, "_Q_fge"); 10511 set_optab_libfunc (lt_optab, TFmode, "_Q_flt"); 10512 set_optab_libfunc (le_optab, TFmode, "_Q_fle"); 10513 10514 set_conv_libfunc (sext_optab, TFmode, SFmode, "_Q_stoq"); 10515 set_conv_libfunc (sext_optab, TFmode, DFmode, "_Q_dtoq"); 10516 set_conv_libfunc (trunc_optab, SFmode, TFmode, "_Q_qtos"); 10517 set_conv_libfunc (trunc_optab, DFmode, TFmode, "_Q_qtod"); 10518 10519 set_conv_libfunc (sfix_optab, SImode, TFmode, "_Q_qtoi"); 10520 set_conv_libfunc (ufix_optab, SImode, TFmode, "_Q_qtou"); 10521 set_conv_libfunc (sfloat_optab, TFmode, SImode, "_Q_itoq"); 10522 set_conv_libfunc (ufloat_optab, TFmode, SImode, "_Q_utoq"); 10523 10524 if (DITF_CONVERSION_LIBFUNCS) 10525 { 10526 set_conv_libfunc (sfix_optab, DImode, TFmode, "_Q_qtoll"); 10527 set_conv_libfunc (ufix_optab, DImode, TFmode, "_Q_qtoull"); 10528 set_conv_libfunc (sfloat_optab, TFmode, DImode, "_Q_lltoq"); 10529 set_conv_libfunc (ufloat_optab, TFmode, DImode, "_Q_ulltoq"); 10530 } 10531 10532 if (SUN_CONVERSION_LIBFUNCS) 10533 { 10534 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftoll"); 10535 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoull"); 10536 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtoll"); 10537 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoull"); 10538 } 10539 } 10540 if (TARGET_ARCH64) 10541 { 10542 /* In the SPARC 64bit ABI, SImode multiply and divide functions 10543 do not exist in the library. Make sure the compiler does not 10544 emit calls to them by accident. (It should always use the 10545 hardware instructions.) */ 10546 set_optab_libfunc (smul_optab, SImode, 0); 10547 set_optab_libfunc (sdiv_optab, SImode, 0); 10548 set_optab_libfunc (udiv_optab, SImode, 0); 10549 set_optab_libfunc (smod_optab, SImode, 0); 10550 set_optab_libfunc (umod_optab, SImode, 0); 10551 10552 if (SUN_INTEGER_MULTIPLY_64) 10553 { 10554 set_optab_libfunc (smul_optab, DImode, "__mul64"); 10555 set_optab_libfunc (sdiv_optab, DImode, "__div64"); 10556 set_optab_libfunc (udiv_optab, DImode, "__udiv64"); 10557 set_optab_libfunc (smod_optab, DImode, "__rem64"); 10558 set_optab_libfunc (umod_optab, DImode, "__urem64"); 10559 } 10560 10561 if (SUN_CONVERSION_LIBFUNCS) 10562 { 10563 set_conv_libfunc (sfix_optab, DImode, SFmode, "__ftol"); 10564 set_conv_libfunc (ufix_optab, DImode, SFmode, "__ftoul"); 10565 set_conv_libfunc (sfix_optab, DImode, DFmode, "__dtol"); 10566 set_conv_libfunc (ufix_optab, DImode, DFmode, "__dtoul"); 10567 } 10568 } 10569 } 10570 10571 /* SPARC builtins. */ 10572 enum sparc_builtins 10573 { 10574 /* FPU builtins. */ 10575 SPARC_BUILTIN_LDFSR, 10576 SPARC_BUILTIN_STFSR, 10577 10578 /* VIS 1.0 builtins. */ 10579 SPARC_BUILTIN_FPACK16, 10580 SPARC_BUILTIN_FPACK32, 10581 SPARC_BUILTIN_FPACKFIX, 10582 SPARC_BUILTIN_FEXPAND, 10583 SPARC_BUILTIN_FPMERGE, 10584 SPARC_BUILTIN_FMUL8X16, 10585 SPARC_BUILTIN_FMUL8X16AU, 10586 SPARC_BUILTIN_FMUL8X16AL, 10587 SPARC_BUILTIN_FMUL8SUX16, 10588 SPARC_BUILTIN_FMUL8ULX16, 10589 SPARC_BUILTIN_FMULD8SUX16, 10590 SPARC_BUILTIN_FMULD8ULX16, 10591 SPARC_BUILTIN_FALIGNDATAV4HI, 10592 SPARC_BUILTIN_FALIGNDATAV8QI, 10593 SPARC_BUILTIN_FALIGNDATAV2SI, 10594 SPARC_BUILTIN_FALIGNDATADI, 10595 SPARC_BUILTIN_WRGSR, 10596 SPARC_BUILTIN_RDGSR, 10597 SPARC_BUILTIN_ALIGNADDR, 10598 SPARC_BUILTIN_ALIGNADDRL, 10599 SPARC_BUILTIN_PDIST, 10600 SPARC_BUILTIN_EDGE8, 10601 SPARC_BUILTIN_EDGE8L, 10602 SPARC_BUILTIN_EDGE16, 10603 SPARC_BUILTIN_EDGE16L, 10604 SPARC_BUILTIN_EDGE32, 10605 SPARC_BUILTIN_EDGE32L, 10606 SPARC_BUILTIN_FCMPLE16, 10607 SPARC_BUILTIN_FCMPLE32, 10608 SPARC_BUILTIN_FCMPNE16, 10609 SPARC_BUILTIN_FCMPNE32, 10610 SPARC_BUILTIN_FCMPGT16, 10611 SPARC_BUILTIN_FCMPGT32, 10612 SPARC_BUILTIN_FCMPEQ16, 10613 SPARC_BUILTIN_FCMPEQ32, 10614 SPARC_BUILTIN_FPADD16, 10615 SPARC_BUILTIN_FPADD16S, 10616 SPARC_BUILTIN_FPADD32, 10617 SPARC_BUILTIN_FPADD32S, 10618 SPARC_BUILTIN_FPSUB16, 10619 SPARC_BUILTIN_FPSUB16S, 10620 SPARC_BUILTIN_FPSUB32, 10621 SPARC_BUILTIN_FPSUB32S, 10622 SPARC_BUILTIN_ARRAY8, 10623 SPARC_BUILTIN_ARRAY16, 10624 SPARC_BUILTIN_ARRAY32, 10625 10626 /* VIS 2.0 builtins. */ 10627 SPARC_BUILTIN_EDGE8N, 10628 SPARC_BUILTIN_EDGE8LN, 10629 SPARC_BUILTIN_EDGE16N, 10630 SPARC_BUILTIN_EDGE16LN, 10631 SPARC_BUILTIN_EDGE32N, 10632 SPARC_BUILTIN_EDGE32LN, 10633 SPARC_BUILTIN_BMASK, 10634 SPARC_BUILTIN_BSHUFFLEV4HI, 10635 SPARC_BUILTIN_BSHUFFLEV8QI, 10636 SPARC_BUILTIN_BSHUFFLEV2SI, 10637 SPARC_BUILTIN_BSHUFFLEDI, 10638 10639 /* VIS 3.0 builtins. */ 10640 SPARC_BUILTIN_CMASK8, 10641 SPARC_BUILTIN_CMASK16, 10642 SPARC_BUILTIN_CMASK32, 10643 SPARC_BUILTIN_FCHKSM16, 10644 SPARC_BUILTIN_FSLL16, 10645 SPARC_BUILTIN_FSLAS16, 10646 SPARC_BUILTIN_FSRL16, 10647 SPARC_BUILTIN_FSRA16, 10648 SPARC_BUILTIN_FSLL32, 10649 SPARC_BUILTIN_FSLAS32, 10650 SPARC_BUILTIN_FSRL32, 10651 SPARC_BUILTIN_FSRA32, 10652 SPARC_BUILTIN_PDISTN, 10653 SPARC_BUILTIN_FMEAN16, 10654 SPARC_BUILTIN_FPADD64, 10655 SPARC_BUILTIN_FPSUB64, 10656 SPARC_BUILTIN_FPADDS16, 10657 SPARC_BUILTIN_FPADDS16S, 10658 SPARC_BUILTIN_FPSUBS16, 10659 SPARC_BUILTIN_FPSUBS16S, 10660 SPARC_BUILTIN_FPADDS32, 10661 SPARC_BUILTIN_FPADDS32S, 10662 SPARC_BUILTIN_FPSUBS32, 10663 SPARC_BUILTIN_FPSUBS32S, 10664 SPARC_BUILTIN_FUCMPLE8, 10665 SPARC_BUILTIN_FUCMPNE8, 10666 SPARC_BUILTIN_FUCMPGT8, 10667 SPARC_BUILTIN_FUCMPEQ8, 10668 SPARC_BUILTIN_FHADDS, 10669 SPARC_BUILTIN_FHADDD, 10670 SPARC_BUILTIN_FHSUBS, 10671 SPARC_BUILTIN_FHSUBD, 10672 SPARC_BUILTIN_FNHADDS, 10673 SPARC_BUILTIN_FNHADDD, 10674 SPARC_BUILTIN_UMULXHI, 10675 SPARC_BUILTIN_XMULX, 10676 SPARC_BUILTIN_XMULXHI, 10677 10678 /* VIS 4.0 builtins. */ 10679 SPARC_BUILTIN_FPADD8, 10680 SPARC_BUILTIN_FPADDS8, 10681 SPARC_BUILTIN_FPADDUS8, 10682 SPARC_BUILTIN_FPADDUS16, 10683 SPARC_BUILTIN_FPCMPLE8, 10684 SPARC_BUILTIN_FPCMPGT8, 10685 SPARC_BUILTIN_FPCMPULE16, 10686 SPARC_BUILTIN_FPCMPUGT16, 10687 SPARC_BUILTIN_FPCMPULE32, 10688 SPARC_BUILTIN_FPCMPUGT32, 10689 SPARC_BUILTIN_FPMAX8, 10690 SPARC_BUILTIN_FPMAX16, 10691 SPARC_BUILTIN_FPMAX32, 10692 SPARC_BUILTIN_FPMAXU8, 10693 SPARC_BUILTIN_FPMAXU16, 10694 SPARC_BUILTIN_FPMAXU32, 10695 SPARC_BUILTIN_FPMIN8, 10696 SPARC_BUILTIN_FPMIN16, 10697 SPARC_BUILTIN_FPMIN32, 10698 SPARC_BUILTIN_FPMINU8, 10699 SPARC_BUILTIN_FPMINU16, 10700 SPARC_BUILTIN_FPMINU32, 10701 SPARC_BUILTIN_FPSUB8, 10702 SPARC_BUILTIN_FPSUBS8, 10703 SPARC_BUILTIN_FPSUBUS8, 10704 SPARC_BUILTIN_FPSUBUS16, 10705 10706 /* VIS 4.0B builtins. */ 10707 10708 /* Note that all the DICTUNPACK* entries should be kept 10709 contiguous. */ 10710 SPARC_BUILTIN_FIRST_DICTUNPACK, 10711 SPARC_BUILTIN_DICTUNPACK8 = SPARC_BUILTIN_FIRST_DICTUNPACK, 10712 SPARC_BUILTIN_DICTUNPACK16, 10713 SPARC_BUILTIN_DICTUNPACK32, 10714 SPARC_BUILTIN_LAST_DICTUNPACK = SPARC_BUILTIN_DICTUNPACK32, 10715 10716 /* Note that all the FPCMP*SHL entries should be kept 10717 contiguous. */ 10718 SPARC_BUILTIN_FIRST_FPCMPSHL, 10719 SPARC_BUILTIN_FPCMPLE8SHL = SPARC_BUILTIN_FIRST_FPCMPSHL, 10720 SPARC_BUILTIN_FPCMPGT8SHL, 10721 SPARC_BUILTIN_FPCMPEQ8SHL, 10722 SPARC_BUILTIN_FPCMPNE8SHL, 10723 SPARC_BUILTIN_FPCMPLE16SHL, 10724 SPARC_BUILTIN_FPCMPGT16SHL, 10725 SPARC_BUILTIN_FPCMPEQ16SHL, 10726 SPARC_BUILTIN_FPCMPNE16SHL, 10727 SPARC_BUILTIN_FPCMPLE32SHL, 10728 SPARC_BUILTIN_FPCMPGT32SHL, 10729 SPARC_BUILTIN_FPCMPEQ32SHL, 10730 SPARC_BUILTIN_FPCMPNE32SHL, 10731 SPARC_BUILTIN_FPCMPULE8SHL, 10732 SPARC_BUILTIN_FPCMPUGT8SHL, 10733 SPARC_BUILTIN_FPCMPULE16SHL, 10734 SPARC_BUILTIN_FPCMPUGT16SHL, 10735 SPARC_BUILTIN_FPCMPULE32SHL, 10736 SPARC_BUILTIN_FPCMPUGT32SHL, 10737 SPARC_BUILTIN_FPCMPDE8SHL, 10738 SPARC_BUILTIN_FPCMPDE16SHL, 10739 SPARC_BUILTIN_FPCMPDE32SHL, 10740 SPARC_BUILTIN_FPCMPUR8SHL, 10741 SPARC_BUILTIN_FPCMPUR16SHL, 10742 SPARC_BUILTIN_FPCMPUR32SHL, 10743 SPARC_BUILTIN_LAST_FPCMPSHL = SPARC_BUILTIN_FPCMPUR32SHL, 10744 10745 SPARC_BUILTIN_MAX 10746 }; 10747 10748 static GTY (()) tree sparc_builtins[(int) SPARC_BUILTIN_MAX]; 10749 static enum insn_code sparc_builtins_icode[(int) SPARC_BUILTIN_MAX]; 10750 10751 /* Return true if OPVAL can be used for operand OPNUM of instruction ICODE. 10752 The instruction should require a constant operand of some sort. The 10753 function prints an error if OPVAL is not valid. */ 10754 10755 static int 10756 check_constant_argument (enum insn_code icode, int opnum, rtx opval) 10757 { 10758 if (GET_CODE (opval) != CONST_INT) 10759 { 10760 error ("%qs expects a constant argument", insn_data[icode].name); 10761 return false; 10762 } 10763 10764 if (!(*insn_data[icode].operand[opnum].predicate) (opval, VOIDmode)) 10765 { 10766 error ("constant argument out of range for %qs", insn_data[icode].name); 10767 return false; 10768 } 10769 return true; 10770 } 10771 10772 /* Add a SPARC builtin function with NAME, ICODE, CODE and TYPE. Return the 10773 function decl or NULL_TREE if the builtin was not added. */ 10774 10775 static tree 10776 def_builtin (const char *name, enum insn_code icode, enum sparc_builtins code, 10777 tree type) 10778 { 10779 tree t 10780 = add_builtin_function (name, type, code, BUILT_IN_MD, NULL, NULL_TREE); 10781 10782 if (t) 10783 { 10784 sparc_builtins[code] = t; 10785 sparc_builtins_icode[code] = icode; 10786 } 10787 10788 return t; 10789 } 10790 10791 /* Likewise, but also marks the function as "const". */ 10792 10793 static tree 10794 def_builtin_const (const char *name, enum insn_code icode, 10795 enum sparc_builtins code, tree type) 10796 { 10797 tree t = def_builtin (name, icode, code, type); 10798 10799 if (t) 10800 TREE_READONLY (t) = 1; 10801 10802 return t; 10803 } 10804 10805 /* Implement the TARGET_INIT_BUILTINS target hook. 10806 Create builtin functions for special SPARC instructions. */ 10807 10808 static void 10809 sparc_init_builtins (void) 10810 { 10811 if (TARGET_FPU) 10812 sparc_fpu_init_builtins (); 10813 10814 if (TARGET_VIS) 10815 sparc_vis_init_builtins (); 10816 } 10817 10818 /* Create builtin functions for FPU instructions. */ 10819 10820 static void 10821 sparc_fpu_init_builtins (void) 10822 { 10823 tree ftype 10824 = build_function_type_list (void_type_node, 10825 build_pointer_type (unsigned_type_node), 0); 10826 def_builtin ("__builtin_load_fsr", CODE_FOR_ldfsr, 10827 SPARC_BUILTIN_LDFSR, ftype); 10828 def_builtin ("__builtin_store_fsr", CODE_FOR_stfsr, 10829 SPARC_BUILTIN_STFSR, ftype); 10830 } 10831 10832 /* Create builtin functions for VIS instructions. */ 10833 10834 static void 10835 sparc_vis_init_builtins (void) 10836 { 10837 tree v4qi = build_vector_type (unsigned_intQI_type_node, 4); 10838 tree v8qi = build_vector_type (unsigned_intQI_type_node, 8); 10839 tree v4hi = build_vector_type (intHI_type_node, 4); 10840 tree v2hi = build_vector_type (intHI_type_node, 2); 10841 tree v2si = build_vector_type (intSI_type_node, 2); 10842 tree v1si = build_vector_type (intSI_type_node, 1); 10843 10844 tree v4qi_ftype_v4hi = build_function_type_list (v4qi, v4hi, 0); 10845 tree v8qi_ftype_v2si_v8qi = build_function_type_list (v8qi, v2si, v8qi, 0); 10846 tree v2hi_ftype_v2si = build_function_type_list (v2hi, v2si, 0); 10847 tree v4hi_ftype_v4qi = build_function_type_list (v4hi, v4qi, 0); 10848 tree v8qi_ftype_v4qi_v4qi = build_function_type_list (v8qi, v4qi, v4qi, 0); 10849 tree v4hi_ftype_v4qi_v4hi = build_function_type_list (v4hi, v4qi, v4hi, 0); 10850 tree v4hi_ftype_v4qi_v2hi = build_function_type_list (v4hi, v4qi, v2hi, 0); 10851 tree v2si_ftype_v4qi_v2hi = build_function_type_list (v2si, v4qi, v2hi, 0); 10852 tree v4hi_ftype_v8qi_v4hi = build_function_type_list (v4hi, v8qi, v4hi, 0); 10853 tree v4hi_ftype_v4hi_v4hi = build_function_type_list (v4hi, v4hi, v4hi, 0); 10854 tree v2si_ftype_v2si_v2si = build_function_type_list (v2si, v2si, v2si, 0); 10855 tree v8qi_ftype_v8qi_v8qi = build_function_type_list (v8qi, v8qi, v8qi, 0); 10856 tree v2hi_ftype_v2hi_v2hi = build_function_type_list (v2hi, v2hi, v2hi, 0); 10857 tree v1si_ftype_v1si_v1si = build_function_type_list (v1si, v1si, v1si, 0); 10858 tree di_ftype_v8qi_v8qi_di = build_function_type_list (intDI_type_node, 10859 v8qi, v8qi, 10860 intDI_type_node, 0); 10861 tree di_ftype_v8qi_v8qi = build_function_type_list (intDI_type_node, 10862 v8qi, v8qi, 0); 10863 tree si_ftype_v8qi_v8qi = build_function_type_list (intSI_type_node, 10864 v8qi, v8qi, 0); 10865 tree v8qi_ftype_df_si = build_function_type_list (v8qi, double_type_node, 10866 intSI_type_node, 0); 10867 tree v4hi_ftype_df_si = build_function_type_list (v4hi, double_type_node, 10868 intSI_type_node, 0); 10869 tree v2si_ftype_df_si = build_function_type_list (v2si, double_type_node, 10870 intDI_type_node, 0); 10871 tree di_ftype_di_di = build_function_type_list (intDI_type_node, 10872 intDI_type_node, 10873 intDI_type_node, 0); 10874 tree si_ftype_si_si = build_function_type_list (intSI_type_node, 10875 intSI_type_node, 10876 intSI_type_node, 0); 10877 tree ptr_ftype_ptr_si = build_function_type_list (ptr_type_node, 10878 ptr_type_node, 10879 intSI_type_node, 0); 10880 tree ptr_ftype_ptr_di = build_function_type_list (ptr_type_node, 10881 ptr_type_node, 10882 intDI_type_node, 0); 10883 tree si_ftype_ptr_ptr = build_function_type_list (intSI_type_node, 10884 ptr_type_node, 10885 ptr_type_node, 0); 10886 tree di_ftype_ptr_ptr = build_function_type_list (intDI_type_node, 10887 ptr_type_node, 10888 ptr_type_node, 0); 10889 tree si_ftype_v4hi_v4hi = build_function_type_list (intSI_type_node, 10890 v4hi, v4hi, 0); 10891 tree si_ftype_v2si_v2si = build_function_type_list (intSI_type_node, 10892 v2si, v2si, 0); 10893 tree di_ftype_v4hi_v4hi = build_function_type_list (intDI_type_node, 10894 v4hi, v4hi, 0); 10895 tree di_ftype_v2si_v2si = build_function_type_list (intDI_type_node, 10896 v2si, v2si, 0); 10897 tree void_ftype_di = build_function_type_list (void_type_node, 10898 intDI_type_node, 0); 10899 tree di_ftype_void = build_function_type_list (intDI_type_node, 10900 void_type_node, 0); 10901 tree void_ftype_si = build_function_type_list (void_type_node, 10902 intSI_type_node, 0); 10903 tree sf_ftype_sf_sf = build_function_type_list (float_type_node, 10904 float_type_node, 10905 float_type_node, 0); 10906 tree df_ftype_df_df = build_function_type_list (double_type_node, 10907 double_type_node, 10908 double_type_node, 0); 10909 10910 /* Packing and expanding vectors. */ 10911 def_builtin ("__builtin_vis_fpack16", CODE_FOR_fpack16_vis, 10912 SPARC_BUILTIN_FPACK16, v4qi_ftype_v4hi); 10913 def_builtin ("__builtin_vis_fpack32", CODE_FOR_fpack32_vis, 10914 SPARC_BUILTIN_FPACK32, v8qi_ftype_v2si_v8qi); 10915 def_builtin ("__builtin_vis_fpackfix", CODE_FOR_fpackfix_vis, 10916 SPARC_BUILTIN_FPACKFIX, v2hi_ftype_v2si); 10917 def_builtin_const ("__builtin_vis_fexpand", CODE_FOR_fexpand_vis, 10918 SPARC_BUILTIN_FEXPAND, v4hi_ftype_v4qi); 10919 def_builtin_const ("__builtin_vis_fpmerge", CODE_FOR_fpmerge_vis, 10920 SPARC_BUILTIN_FPMERGE, v8qi_ftype_v4qi_v4qi); 10921 10922 /* Multiplications. */ 10923 def_builtin_const ("__builtin_vis_fmul8x16", CODE_FOR_fmul8x16_vis, 10924 SPARC_BUILTIN_FMUL8X16, v4hi_ftype_v4qi_v4hi); 10925 def_builtin_const ("__builtin_vis_fmul8x16au", CODE_FOR_fmul8x16au_vis, 10926 SPARC_BUILTIN_FMUL8X16AU, v4hi_ftype_v4qi_v2hi); 10927 def_builtin_const ("__builtin_vis_fmul8x16al", CODE_FOR_fmul8x16al_vis, 10928 SPARC_BUILTIN_FMUL8X16AL, v4hi_ftype_v4qi_v2hi); 10929 def_builtin_const ("__builtin_vis_fmul8sux16", CODE_FOR_fmul8sux16_vis, 10930 SPARC_BUILTIN_FMUL8SUX16, v4hi_ftype_v8qi_v4hi); 10931 def_builtin_const ("__builtin_vis_fmul8ulx16", CODE_FOR_fmul8ulx16_vis, 10932 SPARC_BUILTIN_FMUL8ULX16, v4hi_ftype_v8qi_v4hi); 10933 def_builtin_const ("__builtin_vis_fmuld8sux16", CODE_FOR_fmuld8sux16_vis, 10934 SPARC_BUILTIN_FMULD8SUX16, v2si_ftype_v4qi_v2hi); 10935 def_builtin_const ("__builtin_vis_fmuld8ulx16", CODE_FOR_fmuld8ulx16_vis, 10936 SPARC_BUILTIN_FMULD8ULX16, v2si_ftype_v4qi_v2hi); 10937 10938 /* Data aligning. */ 10939 def_builtin ("__builtin_vis_faligndatav4hi", CODE_FOR_faligndatav4hi_vis, 10940 SPARC_BUILTIN_FALIGNDATAV4HI, v4hi_ftype_v4hi_v4hi); 10941 def_builtin ("__builtin_vis_faligndatav8qi", CODE_FOR_faligndatav8qi_vis, 10942 SPARC_BUILTIN_FALIGNDATAV8QI, v8qi_ftype_v8qi_v8qi); 10943 def_builtin ("__builtin_vis_faligndatav2si", CODE_FOR_faligndatav2si_vis, 10944 SPARC_BUILTIN_FALIGNDATAV2SI, v2si_ftype_v2si_v2si); 10945 def_builtin ("__builtin_vis_faligndatadi", CODE_FOR_faligndatav1di_vis, 10946 SPARC_BUILTIN_FALIGNDATADI, di_ftype_di_di); 10947 10948 def_builtin ("__builtin_vis_write_gsr", CODE_FOR_wrgsr_vis, 10949 SPARC_BUILTIN_WRGSR, void_ftype_di); 10950 def_builtin ("__builtin_vis_read_gsr", CODE_FOR_rdgsr_vis, 10951 SPARC_BUILTIN_RDGSR, di_ftype_void); 10952 10953 if (TARGET_ARCH64) 10954 { 10955 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrdi_vis, 10956 SPARC_BUILTIN_ALIGNADDR, ptr_ftype_ptr_di); 10957 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrldi_vis, 10958 SPARC_BUILTIN_ALIGNADDRL, ptr_ftype_ptr_di); 10959 } 10960 else 10961 { 10962 def_builtin ("__builtin_vis_alignaddr", CODE_FOR_alignaddrsi_vis, 10963 SPARC_BUILTIN_ALIGNADDR, ptr_ftype_ptr_si); 10964 def_builtin ("__builtin_vis_alignaddrl", CODE_FOR_alignaddrlsi_vis, 10965 SPARC_BUILTIN_ALIGNADDRL, ptr_ftype_ptr_si); 10966 } 10967 10968 /* Pixel distance. */ 10969 def_builtin_const ("__builtin_vis_pdist", CODE_FOR_pdist_vis, 10970 SPARC_BUILTIN_PDIST, di_ftype_v8qi_v8qi_di); 10971 10972 /* Edge handling. */ 10973 if (TARGET_ARCH64) 10974 { 10975 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8di_vis, 10976 SPARC_BUILTIN_EDGE8, di_ftype_ptr_ptr); 10977 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8ldi_vis, 10978 SPARC_BUILTIN_EDGE8L, di_ftype_ptr_ptr); 10979 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16di_vis, 10980 SPARC_BUILTIN_EDGE16, di_ftype_ptr_ptr); 10981 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16ldi_vis, 10982 SPARC_BUILTIN_EDGE16L, di_ftype_ptr_ptr); 10983 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32di_vis, 10984 SPARC_BUILTIN_EDGE32, di_ftype_ptr_ptr); 10985 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32ldi_vis, 10986 SPARC_BUILTIN_EDGE32L, di_ftype_ptr_ptr); 10987 } 10988 else 10989 { 10990 def_builtin_const ("__builtin_vis_edge8", CODE_FOR_edge8si_vis, 10991 SPARC_BUILTIN_EDGE8, si_ftype_ptr_ptr); 10992 def_builtin_const ("__builtin_vis_edge8l", CODE_FOR_edge8lsi_vis, 10993 SPARC_BUILTIN_EDGE8L, si_ftype_ptr_ptr); 10994 def_builtin_const ("__builtin_vis_edge16", CODE_FOR_edge16si_vis, 10995 SPARC_BUILTIN_EDGE16, si_ftype_ptr_ptr); 10996 def_builtin_const ("__builtin_vis_edge16l", CODE_FOR_edge16lsi_vis, 10997 SPARC_BUILTIN_EDGE16L, si_ftype_ptr_ptr); 10998 def_builtin_const ("__builtin_vis_edge32", CODE_FOR_edge32si_vis, 10999 SPARC_BUILTIN_EDGE32, si_ftype_ptr_ptr); 11000 def_builtin_const ("__builtin_vis_edge32l", CODE_FOR_edge32lsi_vis, 11001 SPARC_BUILTIN_EDGE32L, si_ftype_ptr_ptr); 11002 } 11003 11004 /* Pixel compare. */ 11005 if (TARGET_ARCH64) 11006 { 11007 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16di_vis, 11008 SPARC_BUILTIN_FCMPLE16, di_ftype_v4hi_v4hi); 11009 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32di_vis, 11010 SPARC_BUILTIN_FCMPLE32, di_ftype_v2si_v2si); 11011 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16di_vis, 11012 SPARC_BUILTIN_FCMPNE16, di_ftype_v4hi_v4hi); 11013 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32di_vis, 11014 SPARC_BUILTIN_FCMPNE32, di_ftype_v2si_v2si); 11015 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16di_vis, 11016 SPARC_BUILTIN_FCMPGT16, di_ftype_v4hi_v4hi); 11017 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32di_vis, 11018 SPARC_BUILTIN_FCMPGT32, di_ftype_v2si_v2si); 11019 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16di_vis, 11020 SPARC_BUILTIN_FCMPEQ16, di_ftype_v4hi_v4hi); 11021 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32di_vis, 11022 SPARC_BUILTIN_FCMPEQ32, di_ftype_v2si_v2si); 11023 } 11024 else 11025 { 11026 def_builtin_const ("__builtin_vis_fcmple16", CODE_FOR_fcmple16si_vis, 11027 SPARC_BUILTIN_FCMPLE16, si_ftype_v4hi_v4hi); 11028 def_builtin_const ("__builtin_vis_fcmple32", CODE_FOR_fcmple32si_vis, 11029 SPARC_BUILTIN_FCMPLE32, si_ftype_v2si_v2si); 11030 def_builtin_const ("__builtin_vis_fcmpne16", CODE_FOR_fcmpne16si_vis, 11031 SPARC_BUILTIN_FCMPNE16, si_ftype_v4hi_v4hi); 11032 def_builtin_const ("__builtin_vis_fcmpne32", CODE_FOR_fcmpne32si_vis, 11033 SPARC_BUILTIN_FCMPNE32, si_ftype_v2si_v2si); 11034 def_builtin_const ("__builtin_vis_fcmpgt16", CODE_FOR_fcmpgt16si_vis, 11035 SPARC_BUILTIN_FCMPGT16, si_ftype_v4hi_v4hi); 11036 def_builtin_const ("__builtin_vis_fcmpgt32", CODE_FOR_fcmpgt32si_vis, 11037 SPARC_BUILTIN_FCMPGT32, si_ftype_v2si_v2si); 11038 def_builtin_const ("__builtin_vis_fcmpeq16", CODE_FOR_fcmpeq16si_vis, 11039 SPARC_BUILTIN_FCMPEQ16, si_ftype_v4hi_v4hi); 11040 def_builtin_const ("__builtin_vis_fcmpeq32", CODE_FOR_fcmpeq32si_vis, 11041 SPARC_BUILTIN_FCMPEQ32, si_ftype_v2si_v2si); 11042 } 11043 11044 /* Addition and subtraction. */ 11045 def_builtin_const ("__builtin_vis_fpadd16", CODE_FOR_addv4hi3, 11046 SPARC_BUILTIN_FPADD16, v4hi_ftype_v4hi_v4hi); 11047 def_builtin_const ("__builtin_vis_fpadd16s", CODE_FOR_addv2hi3, 11048 SPARC_BUILTIN_FPADD16S, v2hi_ftype_v2hi_v2hi); 11049 def_builtin_const ("__builtin_vis_fpadd32", CODE_FOR_addv2si3, 11050 SPARC_BUILTIN_FPADD32, v2si_ftype_v2si_v2si); 11051 def_builtin_const ("__builtin_vis_fpadd32s", CODE_FOR_addv1si3, 11052 SPARC_BUILTIN_FPADD32S, v1si_ftype_v1si_v1si); 11053 def_builtin_const ("__builtin_vis_fpsub16", CODE_FOR_subv4hi3, 11054 SPARC_BUILTIN_FPSUB16, v4hi_ftype_v4hi_v4hi); 11055 def_builtin_const ("__builtin_vis_fpsub16s", CODE_FOR_subv2hi3, 11056 SPARC_BUILTIN_FPSUB16S, v2hi_ftype_v2hi_v2hi); 11057 def_builtin_const ("__builtin_vis_fpsub32", CODE_FOR_subv2si3, 11058 SPARC_BUILTIN_FPSUB32, v2si_ftype_v2si_v2si); 11059 def_builtin_const ("__builtin_vis_fpsub32s", CODE_FOR_subv1si3, 11060 SPARC_BUILTIN_FPSUB32S, v1si_ftype_v1si_v1si); 11061 11062 /* Three-dimensional array addressing. */ 11063 if (TARGET_ARCH64) 11064 { 11065 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8di_vis, 11066 SPARC_BUILTIN_ARRAY8, di_ftype_di_di); 11067 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16di_vis, 11068 SPARC_BUILTIN_ARRAY16, di_ftype_di_di); 11069 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32di_vis, 11070 SPARC_BUILTIN_ARRAY32, di_ftype_di_di); 11071 } 11072 else 11073 { 11074 def_builtin_const ("__builtin_vis_array8", CODE_FOR_array8si_vis, 11075 SPARC_BUILTIN_ARRAY8, si_ftype_si_si); 11076 def_builtin_const ("__builtin_vis_array16", CODE_FOR_array16si_vis, 11077 SPARC_BUILTIN_ARRAY16, si_ftype_si_si); 11078 def_builtin_const ("__builtin_vis_array32", CODE_FOR_array32si_vis, 11079 SPARC_BUILTIN_ARRAY32, si_ftype_si_si); 11080 } 11081 11082 if (TARGET_VIS2) 11083 { 11084 /* Edge handling. */ 11085 if (TARGET_ARCH64) 11086 { 11087 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8ndi_vis, 11088 SPARC_BUILTIN_EDGE8N, di_ftype_ptr_ptr); 11089 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lndi_vis, 11090 SPARC_BUILTIN_EDGE8LN, di_ftype_ptr_ptr); 11091 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16ndi_vis, 11092 SPARC_BUILTIN_EDGE16N, di_ftype_ptr_ptr); 11093 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lndi_vis, 11094 SPARC_BUILTIN_EDGE16LN, di_ftype_ptr_ptr); 11095 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32ndi_vis, 11096 SPARC_BUILTIN_EDGE32N, di_ftype_ptr_ptr); 11097 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lndi_vis, 11098 SPARC_BUILTIN_EDGE32LN, di_ftype_ptr_ptr); 11099 } 11100 else 11101 { 11102 def_builtin_const ("__builtin_vis_edge8n", CODE_FOR_edge8nsi_vis, 11103 SPARC_BUILTIN_EDGE8N, si_ftype_ptr_ptr); 11104 def_builtin_const ("__builtin_vis_edge8ln", CODE_FOR_edge8lnsi_vis, 11105 SPARC_BUILTIN_EDGE8LN, si_ftype_ptr_ptr); 11106 def_builtin_const ("__builtin_vis_edge16n", CODE_FOR_edge16nsi_vis, 11107 SPARC_BUILTIN_EDGE16N, si_ftype_ptr_ptr); 11108 def_builtin_const ("__builtin_vis_edge16ln", CODE_FOR_edge16lnsi_vis, 11109 SPARC_BUILTIN_EDGE16LN, si_ftype_ptr_ptr); 11110 def_builtin_const ("__builtin_vis_edge32n", CODE_FOR_edge32nsi_vis, 11111 SPARC_BUILTIN_EDGE32N, si_ftype_ptr_ptr); 11112 def_builtin_const ("__builtin_vis_edge32ln", CODE_FOR_edge32lnsi_vis, 11113 SPARC_BUILTIN_EDGE32LN, si_ftype_ptr_ptr); 11114 } 11115 11116 /* Byte mask and shuffle. */ 11117 if (TARGET_ARCH64) 11118 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmaskdi_vis, 11119 SPARC_BUILTIN_BMASK, di_ftype_di_di); 11120 else 11121 def_builtin ("__builtin_vis_bmask", CODE_FOR_bmasksi_vis, 11122 SPARC_BUILTIN_BMASK, si_ftype_si_si); 11123 def_builtin ("__builtin_vis_bshufflev4hi", CODE_FOR_bshufflev4hi_vis, 11124 SPARC_BUILTIN_BSHUFFLEV4HI, v4hi_ftype_v4hi_v4hi); 11125 def_builtin ("__builtin_vis_bshufflev8qi", CODE_FOR_bshufflev8qi_vis, 11126 SPARC_BUILTIN_BSHUFFLEV8QI, v8qi_ftype_v8qi_v8qi); 11127 def_builtin ("__builtin_vis_bshufflev2si", CODE_FOR_bshufflev2si_vis, 11128 SPARC_BUILTIN_BSHUFFLEV2SI, v2si_ftype_v2si_v2si); 11129 def_builtin ("__builtin_vis_bshuffledi", CODE_FOR_bshufflev1di_vis, 11130 SPARC_BUILTIN_BSHUFFLEDI, di_ftype_di_di); 11131 } 11132 11133 if (TARGET_VIS3) 11134 { 11135 if (TARGET_ARCH64) 11136 { 11137 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8di_vis, 11138 SPARC_BUILTIN_CMASK8, void_ftype_di); 11139 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16di_vis, 11140 SPARC_BUILTIN_CMASK16, void_ftype_di); 11141 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32di_vis, 11142 SPARC_BUILTIN_CMASK32, void_ftype_di); 11143 } 11144 else 11145 { 11146 def_builtin ("__builtin_vis_cmask8", CODE_FOR_cmask8si_vis, 11147 SPARC_BUILTIN_CMASK8, void_ftype_si); 11148 def_builtin ("__builtin_vis_cmask16", CODE_FOR_cmask16si_vis, 11149 SPARC_BUILTIN_CMASK16, void_ftype_si); 11150 def_builtin ("__builtin_vis_cmask32", CODE_FOR_cmask32si_vis, 11151 SPARC_BUILTIN_CMASK32, void_ftype_si); 11152 } 11153 11154 def_builtin_const ("__builtin_vis_fchksm16", CODE_FOR_fchksm16_vis, 11155 SPARC_BUILTIN_FCHKSM16, v4hi_ftype_v4hi_v4hi); 11156 11157 def_builtin_const ("__builtin_vis_fsll16", CODE_FOR_vashlv4hi3, 11158 SPARC_BUILTIN_FSLL16, v4hi_ftype_v4hi_v4hi); 11159 def_builtin_const ("__builtin_vis_fslas16", CODE_FOR_vssashlv4hi3, 11160 SPARC_BUILTIN_FSLAS16, v4hi_ftype_v4hi_v4hi); 11161 def_builtin_const ("__builtin_vis_fsrl16", CODE_FOR_vlshrv4hi3, 11162 SPARC_BUILTIN_FSRL16, v4hi_ftype_v4hi_v4hi); 11163 def_builtin_const ("__builtin_vis_fsra16", CODE_FOR_vashrv4hi3, 11164 SPARC_BUILTIN_FSRA16, v4hi_ftype_v4hi_v4hi); 11165 def_builtin_const ("__builtin_vis_fsll32", CODE_FOR_vashlv2si3, 11166 SPARC_BUILTIN_FSLL32, v2si_ftype_v2si_v2si); 11167 def_builtin_const ("__builtin_vis_fslas32", CODE_FOR_vssashlv2si3, 11168 SPARC_BUILTIN_FSLAS32, v2si_ftype_v2si_v2si); 11169 def_builtin_const ("__builtin_vis_fsrl32", CODE_FOR_vlshrv2si3, 11170 SPARC_BUILTIN_FSRL32, v2si_ftype_v2si_v2si); 11171 def_builtin_const ("__builtin_vis_fsra32", CODE_FOR_vashrv2si3, 11172 SPARC_BUILTIN_FSRA32, v2si_ftype_v2si_v2si); 11173 11174 if (TARGET_ARCH64) 11175 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistndi_vis, 11176 SPARC_BUILTIN_PDISTN, di_ftype_v8qi_v8qi); 11177 else 11178 def_builtin_const ("__builtin_vis_pdistn", CODE_FOR_pdistnsi_vis, 11179 SPARC_BUILTIN_PDISTN, si_ftype_v8qi_v8qi); 11180 11181 def_builtin_const ("__builtin_vis_fmean16", CODE_FOR_fmean16_vis, 11182 SPARC_BUILTIN_FMEAN16, v4hi_ftype_v4hi_v4hi); 11183 def_builtin_const ("__builtin_vis_fpadd64", CODE_FOR_fpadd64_vis, 11184 SPARC_BUILTIN_FPADD64, di_ftype_di_di); 11185 def_builtin_const ("__builtin_vis_fpsub64", CODE_FOR_fpsub64_vis, 11186 SPARC_BUILTIN_FPSUB64, di_ftype_di_di); 11187 11188 def_builtin_const ("__builtin_vis_fpadds16", CODE_FOR_ssaddv4hi3, 11189 SPARC_BUILTIN_FPADDS16, v4hi_ftype_v4hi_v4hi); 11190 def_builtin_const ("__builtin_vis_fpadds16s", CODE_FOR_ssaddv2hi3, 11191 SPARC_BUILTIN_FPADDS16S, v2hi_ftype_v2hi_v2hi); 11192 def_builtin_const ("__builtin_vis_fpsubs16", CODE_FOR_sssubv4hi3, 11193 SPARC_BUILTIN_FPSUBS16, v4hi_ftype_v4hi_v4hi); 11194 def_builtin_const ("__builtin_vis_fpsubs16s", CODE_FOR_sssubv2hi3, 11195 SPARC_BUILTIN_FPSUBS16S, v2hi_ftype_v2hi_v2hi); 11196 def_builtin_const ("__builtin_vis_fpadds32", CODE_FOR_ssaddv2si3, 11197 SPARC_BUILTIN_FPADDS32, v2si_ftype_v2si_v2si); 11198 def_builtin_const ("__builtin_vis_fpadds32s", CODE_FOR_ssaddv1si3, 11199 SPARC_BUILTIN_FPADDS32S, v1si_ftype_v1si_v1si); 11200 def_builtin_const ("__builtin_vis_fpsubs32", CODE_FOR_sssubv2si3, 11201 SPARC_BUILTIN_FPSUBS32, v2si_ftype_v2si_v2si); 11202 def_builtin_const ("__builtin_vis_fpsubs32s", CODE_FOR_sssubv1si3, 11203 SPARC_BUILTIN_FPSUBS32S, v1si_ftype_v1si_v1si); 11204 11205 if (TARGET_ARCH64) 11206 { 11207 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8di_vis, 11208 SPARC_BUILTIN_FUCMPLE8, di_ftype_v8qi_v8qi); 11209 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8di_vis, 11210 SPARC_BUILTIN_FUCMPNE8, di_ftype_v8qi_v8qi); 11211 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8di_vis, 11212 SPARC_BUILTIN_FUCMPGT8, di_ftype_v8qi_v8qi); 11213 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8di_vis, 11214 SPARC_BUILTIN_FUCMPEQ8, di_ftype_v8qi_v8qi); 11215 } 11216 else 11217 { 11218 def_builtin_const ("__builtin_vis_fucmple8", CODE_FOR_fucmple8si_vis, 11219 SPARC_BUILTIN_FUCMPLE8, si_ftype_v8qi_v8qi); 11220 def_builtin_const ("__builtin_vis_fucmpne8", CODE_FOR_fucmpne8si_vis, 11221 SPARC_BUILTIN_FUCMPNE8, si_ftype_v8qi_v8qi); 11222 def_builtin_const ("__builtin_vis_fucmpgt8", CODE_FOR_fucmpgt8si_vis, 11223 SPARC_BUILTIN_FUCMPGT8, si_ftype_v8qi_v8qi); 11224 def_builtin_const ("__builtin_vis_fucmpeq8", CODE_FOR_fucmpeq8si_vis, 11225 SPARC_BUILTIN_FUCMPEQ8, si_ftype_v8qi_v8qi); 11226 } 11227 11228 def_builtin_const ("__builtin_vis_fhadds", CODE_FOR_fhaddsf_vis, 11229 SPARC_BUILTIN_FHADDS, sf_ftype_sf_sf); 11230 def_builtin_const ("__builtin_vis_fhaddd", CODE_FOR_fhadddf_vis, 11231 SPARC_BUILTIN_FHADDD, df_ftype_df_df); 11232 def_builtin_const ("__builtin_vis_fhsubs", CODE_FOR_fhsubsf_vis, 11233 SPARC_BUILTIN_FHSUBS, sf_ftype_sf_sf); 11234 def_builtin_const ("__builtin_vis_fhsubd", CODE_FOR_fhsubdf_vis, 11235 SPARC_BUILTIN_FHSUBD, df_ftype_df_df); 11236 def_builtin_const ("__builtin_vis_fnhadds", CODE_FOR_fnhaddsf_vis, 11237 SPARC_BUILTIN_FNHADDS, sf_ftype_sf_sf); 11238 def_builtin_const ("__builtin_vis_fnhaddd", CODE_FOR_fnhadddf_vis, 11239 SPARC_BUILTIN_FNHADDD, df_ftype_df_df); 11240 11241 def_builtin_const ("__builtin_vis_umulxhi", CODE_FOR_umulxhi_vis, 11242 SPARC_BUILTIN_UMULXHI, di_ftype_di_di); 11243 def_builtin_const ("__builtin_vis_xmulx", CODE_FOR_xmulx_vis, 11244 SPARC_BUILTIN_XMULX, di_ftype_di_di); 11245 def_builtin_const ("__builtin_vis_xmulxhi", CODE_FOR_xmulxhi_vis, 11246 SPARC_BUILTIN_XMULXHI, di_ftype_di_di); 11247 } 11248 11249 if (TARGET_VIS4) 11250 { 11251 def_builtin_const ("__builtin_vis_fpadd8", CODE_FOR_addv8qi3, 11252 SPARC_BUILTIN_FPADD8, v8qi_ftype_v8qi_v8qi); 11253 def_builtin_const ("__builtin_vis_fpadds8", CODE_FOR_ssaddv8qi3, 11254 SPARC_BUILTIN_FPADDS8, v8qi_ftype_v8qi_v8qi); 11255 def_builtin_const ("__builtin_vis_fpaddus8", CODE_FOR_usaddv8qi3, 11256 SPARC_BUILTIN_FPADDUS8, v8qi_ftype_v8qi_v8qi); 11257 def_builtin_const ("__builtin_vis_fpaddus16", CODE_FOR_usaddv4hi3, 11258 SPARC_BUILTIN_FPADDUS16, v4hi_ftype_v4hi_v4hi); 11259 11260 11261 if (TARGET_ARCH64) 11262 { 11263 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8di_vis, 11264 SPARC_BUILTIN_FPCMPLE8, di_ftype_v8qi_v8qi); 11265 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8di_vis, 11266 SPARC_BUILTIN_FPCMPGT8, di_ftype_v8qi_v8qi); 11267 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16di_vis, 11268 SPARC_BUILTIN_FPCMPULE16, di_ftype_v4hi_v4hi); 11269 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16di_vis, 11270 SPARC_BUILTIN_FPCMPUGT16, di_ftype_v4hi_v4hi); 11271 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32di_vis, 11272 SPARC_BUILTIN_FPCMPULE32, di_ftype_v2si_v2si); 11273 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32di_vis, 11274 SPARC_BUILTIN_FPCMPUGT32, di_ftype_v2si_v2si); 11275 } 11276 else 11277 { 11278 def_builtin_const ("__builtin_vis_fpcmple8", CODE_FOR_fpcmple8si_vis, 11279 SPARC_BUILTIN_FPCMPLE8, si_ftype_v8qi_v8qi); 11280 def_builtin_const ("__builtin_vis_fpcmpgt8", CODE_FOR_fpcmpgt8si_vis, 11281 SPARC_BUILTIN_FPCMPGT8, si_ftype_v8qi_v8qi); 11282 def_builtin_const ("__builtin_vis_fpcmpule16", CODE_FOR_fpcmpule16si_vis, 11283 SPARC_BUILTIN_FPCMPULE16, si_ftype_v4hi_v4hi); 11284 def_builtin_const ("__builtin_vis_fpcmpugt16", CODE_FOR_fpcmpugt16si_vis, 11285 SPARC_BUILTIN_FPCMPUGT16, si_ftype_v4hi_v4hi); 11286 def_builtin_const ("__builtin_vis_fpcmpule32", CODE_FOR_fpcmpule32si_vis, 11287 SPARC_BUILTIN_FPCMPULE32, di_ftype_v2si_v2si); 11288 def_builtin_const ("__builtin_vis_fpcmpugt32", CODE_FOR_fpcmpugt32si_vis, 11289 SPARC_BUILTIN_FPCMPUGT32, di_ftype_v2si_v2si); 11290 } 11291 11292 def_builtin_const ("__builtin_vis_fpmax8", CODE_FOR_maxv8qi3, 11293 SPARC_BUILTIN_FPMAX8, v8qi_ftype_v8qi_v8qi); 11294 def_builtin_const ("__builtin_vis_fpmax16", CODE_FOR_maxv4hi3, 11295 SPARC_BUILTIN_FPMAX16, v4hi_ftype_v4hi_v4hi); 11296 def_builtin_const ("__builtin_vis_fpmax32", CODE_FOR_maxv2si3, 11297 SPARC_BUILTIN_FPMAX32, v2si_ftype_v2si_v2si); 11298 def_builtin_const ("__builtin_vis_fpmaxu8", CODE_FOR_maxuv8qi3, 11299 SPARC_BUILTIN_FPMAXU8, v8qi_ftype_v8qi_v8qi); 11300 def_builtin_const ("__builtin_vis_fpmaxu16", CODE_FOR_maxuv4hi3, 11301 SPARC_BUILTIN_FPMAXU16, v4hi_ftype_v4hi_v4hi); 11302 def_builtin_const ("__builtin_vis_fpmaxu32", CODE_FOR_maxuv2si3, 11303 SPARC_BUILTIN_FPMAXU32, v2si_ftype_v2si_v2si); 11304 def_builtin_const ("__builtin_vis_fpmin8", CODE_FOR_minv8qi3, 11305 SPARC_BUILTIN_FPMIN8, v8qi_ftype_v8qi_v8qi); 11306 def_builtin_const ("__builtin_vis_fpmin16", CODE_FOR_minv4hi3, 11307 SPARC_BUILTIN_FPMIN16, v4hi_ftype_v4hi_v4hi); 11308 def_builtin_const ("__builtin_vis_fpmin32", CODE_FOR_minv2si3, 11309 SPARC_BUILTIN_FPMIN32, v2si_ftype_v2si_v2si); 11310 def_builtin_const ("__builtin_vis_fpminu8", CODE_FOR_minuv8qi3, 11311 SPARC_BUILTIN_FPMINU8, v8qi_ftype_v8qi_v8qi); 11312 def_builtin_const ("__builtin_vis_fpminu16", CODE_FOR_minuv4hi3, 11313 SPARC_BUILTIN_FPMINU16, v4hi_ftype_v4hi_v4hi); 11314 def_builtin_const ("__builtin_vis_fpminu32", CODE_FOR_minuv2si3, 11315 SPARC_BUILTIN_FPMINU32, v2si_ftype_v2si_v2si); 11316 def_builtin_const ("__builtin_vis_fpsub8", CODE_FOR_subv8qi3, 11317 SPARC_BUILTIN_FPSUB8, v8qi_ftype_v8qi_v8qi); 11318 def_builtin_const ("__builtin_vis_fpsubs8", CODE_FOR_sssubv8qi3, 11319 SPARC_BUILTIN_FPSUBS8, v8qi_ftype_v8qi_v8qi); 11320 def_builtin_const ("__builtin_vis_fpsubus8", CODE_FOR_ussubv8qi3, 11321 SPARC_BUILTIN_FPSUBUS8, v8qi_ftype_v8qi_v8qi); 11322 def_builtin_const ("__builtin_vis_fpsubus16", CODE_FOR_ussubv4hi3, 11323 SPARC_BUILTIN_FPSUBUS16, v4hi_ftype_v4hi_v4hi); 11324 } 11325 11326 if (TARGET_VIS4B) 11327 { 11328 def_builtin_const ("__builtin_vis_dictunpack8", CODE_FOR_dictunpack8, 11329 SPARC_BUILTIN_DICTUNPACK8, v8qi_ftype_df_si); 11330 def_builtin_const ("__builtin_vis_dictunpack16", CODE_FOR_dictunpack16, 11331 SPARC_BUILTIN_DICTUNPACK16, v4hi_ftype_df_si); 11332 def_builtin_const ("__builtin_vis_dictunpack32", CODE_FOR_dictunpack32, 11333 SPARC_BUILTIN_DICTUNPACK32, v2si_ftype_df_si); 11334 11335 if (TARGET_ARCH64) 11336 { 11337 tree di_ftype_v8qi_v8qi_si = build_function_type_list (intDI_type_node, 11338 v8qi, v8qi, 11339 intSI_type_node, 0); 11340 tree di_ftype_v4hi_v4hi_si = build_function_type_list (intDI_type_node, 11341 v4hi, v4hi, 11342 intSI_type_node, 0); 11343 tree di_ftype_v2si_v2si_si = build_function_type_list (intDI_type_node, 11344 v2si, v2si, 11345 intSI_type_node, 0); 11346 11347 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8dishl, 11348 SPARC_BUILTIN_FPCMPLE8SHL, di_ftype_v8qi_v8qi_si); 11349 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8dishl, 11350 SPARC_BUILTIN_FPCMPGT8SHL, di_ftype_v8qi_v8qi_si); 11351 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8dishl, 11352 SPARC_BUILTIN_FPCMPEQ8SHL, di_ftype_v8qi_v8qi_si); 11353 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8dishl, 11354 SPARC_BUILTIN_FPCMPNE8SHL, di_ftype_v8qi_v8qi_si); 11355 11356 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16dishl, 11357 SPARC_BUILTIN_FPCMPLE16SHL, di_ftype_v4hi_v4hi_si); 11358 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16dishl, 11359 SPARC_BUILTIN_FPCMPGT16SHL, di_ftype_v4hi_v4hi_si); 11360 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16dishl, 11361 SPARC_BUILTIN_FPCMPEQ16SHL, di_ftype_v4hi_v4hi_si); 11362 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16dishl, 11363 SPARC_BUILTIN_FPCMPNE16SHL, di_ftype_v4hi_v4hi_si); 11364 11365 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32dishl, 11366 SPARC_BUILTIN_FPCMPLE32SHL, di_ftype_v2si_v2si_si); 11367 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32dishl, 11368 SPARC_BUILTIN_FPCMPGT32SHL, di_ftype_v2si_v2si_si); 11369 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32dishl, 11370 SPARC_BUILTIN_FPCMPEQ32SHL, di_ftype_v2si_v2si_si); 11371 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32dishl, 11372 SPARC_BUILTIN_FPCMPNE32SHL, di_ftype_v2si_v2si_si); 11373 11374 11375 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8dishl, 11376 SPARC_BUILTIN_FPCMPULE8SHL, di_ftype_v8qi_v8qi_si); 11377 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8dishl, 11378 SPARC_BUILTIN_FPCMPUGT8SHL, di_ftype_v8qi_v8qi_si); 11379 11380 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16dishl, 11381 SPARC_BUILTIN_FPCMPULE16SHL, di_ftype_v4hi_v4hi_si); 11382 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16dishl, 11383 SPARC_BUILTIN_FPCMPUGT16SHL, di_ftype_v4hi_v4hi_si); 11384 11385 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32dishl, 11386 SPARC_BUILTIN_FPCMPULE32SHL, di_ftype_v2si_v2si_si); 11387 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32dishl, 11388 SPARC_BUILTIN_FPCMPUGT32SHL, di_ftype_v2si_v2si_si); 11389 11390 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8dishl, 11391 SPARC_BUILTIN_FPCMPDE8SHL, di_ftype_v8qi_v8qi_si); 11392 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16dishl, 11393 SPARC_BUILTIN_FPCMPDE16SHL, di_ftype_v4hi_v4hi_si); 11394 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32dishl, 11395 SPARC_BUILTIN_FPCMPDE32SHL, di_ftype_v2si_v2si_si); 11396 11397 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8dishl, 11398 SPARC_BUILTIN_FPCMPUR8SHL, di_ftype_v8qi_v8qi_si); 11399 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16dishl, 11400 SPARC_BUILTIN_FPCMPUR16SHL, di_ftype_v4hi_v4hi_si); 11401 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32dishl, 11402 SPARC_BUILTIN_FPCMPUR32SHL, di_ftype_v2si_v2si_si); 11403 11404 } 11405 else 11406 { 11407 tree si_ftype_v8qi_v8qi_si = build_function_type_list (intSI_type_node, 11408 v8qi, v8qi, 11409 intSI_type_node, 0); 11410 tree si_ftype_v4hi_v4hi_si = build_function_type_list (intSI_type_node, 11411 v4hi, v4hi, 11412 intSI_type_node, 0); 11413 tree si_ftype_v2si_v2si_si = build_function_type_list (intSI_type_node, 11414 v2si, v2si, 11415 intSI_type_node, 0); 11416 11417 def_builtin_const ("__builtin_vis_fpcmple8shl", CODE_FOR_fpcmple8sishl, 11418 SPARC_BUILTIN_FPCMPLE8SHL, si_ftype_v8qi_v8qi_si); 11419 def_builtin_const ("__builtin_vis_fpcmpgt8shl", CODE_FOR_fpcmpgt8sishl, 11420 SPARC_BUILTIN_FPCMPGT8SHL, si_ftype_v8qi_v8qi_si); 11421 def_builtin_const ("__builtin_vis_fpcmpeq8shl", CODE_FOR_fpcmpeq8sishl, 11422 SPARC_BUILTIN_FPCMPEQ8SHL, si_ftype_v8qi_v8qi_si); 11423 def_builtin_const ("__builtin_vis_fpcmpne8shl", CODE_FOR_fpcmpne8sishl, 11424 SPARC_BUILTIN_FPCMPNE8SHL, si_ftype_v8qi_v8qi_si); 11425 11426 def_builtin_const ("__builtin_vis_fpcmple16shl", CODE_FOR_fpcmple16sishl, 11427 SPARC_BUILTIN_FPCMPLE16SHL, si_ftype_v4hi_v4hi_si); 11428 def_builtin_const ("__builtin_vis_fpcmpgt16shl", CODE_FOR_fpcmpgt16sishl, 11429 SPARC_BUILTIN_FPCMPGT16SHL, si_ftype_v4hi_v4hi_si); 11430 def_builtin_const ("__builtin_vis_fpcmpeq16shl", CODE_FOR_fpcmpeq16sishl, 11431 SPARC_BUILTIN_FPCMPEQ16SHL, si_ftype_v4hi_v4hi_si); 11432 def_builtin_const ("__builtin_vis_fpcmpne16shl", CODE_FOR_fpcmpne16sishl, 11433 SPARC_BUILTIN_FPCMPNE16SHL, si_ftype_v4hi_v4hi_si); 11434 11435 def_builtin_const ("__builtin_vis_fpcmple32shl", CODE_FOR_fpcmple32sishl, 11436 SPARC_BUILTIN_FPCMPLE32SHL, si_ftype_v2si_v2si_si); 11437 def_builtin_const ("__builtin_vis_fpcmpgt32shl", CODE_FOR_fpcmpgt32sishl, 11438 SPARC_BUILTIN_FPCMPGT32SHL, si_ftype_v2si_v2si_si); 11439 def_builtin_const ("__builtin_vis_fpcmpeq32shl", CODE_FOR_fpcmpeq32sishl, 11440 SPARC_BUILTIN_FPCMPEQ32SHL, si_ftype_v2si_v2si_si); 11441 def_builtin_const ("__builtin_vis_fpcmpne32shl", CODE_FOR_fpcmpne32sishl, 11442 SPARC_BUILTIN_FPCMPNE32SHL, si_ftype_v2si_v2si_si); 11443 11444 11445 def_builtin_const ("__builtin_vis_fpcmpule8shl", CODE_FOR_fpcmpule8sishl, 11446 SPARC_BUILTIN_FPCMPULE8SHL, si_ftype_v8qi_v8qi_si); 11447 def_builtin_const ("__builtin_vis_fpcmpugt8shl", CODE_FOR_fpcmpugt8sishl, 11448 SPARC_BUILTIN_FPCMPUGT8SHL, si_ftype_v8qi_v8qi_si); 11449 11450 def_builtin_const ("__builtin_vis_fpcmpule16shl", CODE_FOR_fpcmpule16sishl, 11451 SPARC_BUILTIN_FPCMPULE16SHL, si_ftype_v4hi_v4hi_si); 11452 def_builtin_const ("__builtin_vis_fpcmpugt16shl", CODE_FOR_fpcmpugt16sishl, 11453 SPARC_BUILTIN_FPCMPUGT16SHL, si_ftype_v4hi_v4hi_si); 11454 11455 def_builtin_const ("__builtin_vis_fpcmpule32shl", CODE_FOR_fpcmpule32sishl, 11456 SPARC_BUILTIN_FPCMPULE32SHL, si_ftype_v2si_v2si_si); 11457 def_builtin_const ("__builtin_vis_fpcmpugt32shl", CODE_FOR_fpcmpugt32sishl, 11458 SPARC_BUILTIN_FPCMPUGT32SHL, si_ftype_v2si_v2si_si); 11459 11460 def_builtin_const ("__builtin_vis_fpcmpde8shl", CODE_FOR_fpcmpde8sishl, 11461 SPARC_BUILTIN_FPCMPDE8SHL, si_ftype_v8qi_v8qi_si); 11462 def_builtin_const ("__builtin_vis_fpcmpde16shl", CODE_FOR_fpcmpde16sishl, 11463 SPARC_BUILTIN_FPCMPDE16SHL, si_ftype_v4hi_v4hi_si); 11464 def_builtin_const ("__builtin_vis_fpcmpde32shl", CODE_FOR_fpcmpde32sishl, 11465 SPARC_BUILTIN_FPCMPDE32SHL, si_ftype_v2si_v2si_si); 11466 11467 def_builtin_const ("__builtin_vis_fpcmpur8shl", CODE_FOR_fpcmpur8sishl, 11468 SPARC_BUILTIN_FPCMPUR8SHL, si_ftype_v8qi_v8qi_si); 11469 def_builtin_const ("__builtin_vis_fpcmpur16shl", CODE_FOR_fpcmpur16sishl, 11470 SPARC_BUILTIN_FPCMPUR16SHL, si_ftype_v4hi_v4hi_si); 11471 def_builtin_const ("__builtin_vis_fpcmpur32shl", CODE_FOR_fpcmpur32sishl, 11472 SPARC_BUILTIN_FPCMPUR32SHL, si_ftype_v2si_v2si_si); 11473 } 11474 } 11475 } 11476 11477 /* Implement TARGET_BUILTIN_DECL hook. */ 11478 11479 static tree 11480 sparc_builtin_decl (unsigned code, bool initialize_p ATTRIBUTE_UNUSED) 11481 { 11482 if (code >= SPARC_BUILTIN_MAX) 11483 return error_mark_node; 11484 11485 return sparc_builtins[code]; 11486 } 11487 11488 /* Implemented TARGET_EXPAND_BUILTIN hook. */ 11489 11490 static rtx 11491 sparc_expand_builtin (tree exp, rtx target, 11492 rtx subtarget ATTRIBUTE_UNUSED, 11493 machine_mode tmode ATTRIBUTE_UNUSED, 11494 int ignore ATTRIBUTE_UNUSED) 11495 { 11496 tree fndecl = TREE_OPERAND (CALL_EXPR_FN (exp), 0); 11497 enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl); 11498 enum insn_code icode = sparc_builtins_icode[code]; 11499 bool nonvoid = TREE_TYPE (TREE_TYPE (fndecl)) != void_type_node; 11500 call_expr_arg_iterator iter; 11501 int arg_count = 0; 11502 rtx pat, op[4]; 11503 tree arg; 11504 11505 if (nonvoid) 11506 { 11507 machine_mode tmode = insn_data[icode].operand[0].mode; 11508 if (!target 11509 || GET_MODE (target) != tmode 11510 || ! (*insn_data[icode].operand[0].predicate) (target, tmode)) 11511 op[0] = gen_reg_rtx (tmode); 11512 else 11513 op[0] = target; 11514 } 11515 11516 FOR_EACH_CALL_EXPR_ARG (arg, iter, exp) 11517 { 11518 const struct insn_operand_data *insn_op; 11519 int idx; 11520 11521 if (arg == error_mark_node) 11522 return NULL_RTX; 11523 11524 arg_count++; 11525 idx = arg_count - !nonvoid; 11526 insn_op = &insn_data[icode].operand[idx]; 11527 op[arg_count] = expand_normal (arg); 11528 11529 /* Some of the builtins require constant arguments. We check 11530 for this here. */ 11531 if ((code >= SPARC_BUILTIN_FIRST_FPCMPSHL 11532 && code <= SPARC_BUILTIN_LAST_FPCMPSHL 11533 && arg_count == 3) 11534 || (code >= SPARC_BUILTIN_FIRST_DICTUNPACK 11535 && code <= SPARC_BUILTIN_LAST_DICTUNPACK 11536 && arg_count == 2)) 11537 { 11538 if (!check_constant_argument (icode, idx, op[arg_count])) 11539 return const0_rtx; 11540 } 11541 11542 if (code == SPARC_BUILTIN_LDFSR || code == SPARC_BUILTIN_STFSR) 11543 { 11544 if (!address_operand (op[arg_count], SImode)) 11545 { 11546 op[arg_count] = convert_memory_address (Pmode, op[arg_count]); 11547 op[arg_count] = copy_addr_to_reg (op[arg_count]); 11548 } 11549 op[arg_count] = gen_rtx_MEM (SImode, op[arg_count]); 11550 } 11551 11552 else if (insn_op->mode == V1DImode 11553 && GET_MODE (op[arg_count]) == DImode) 11554 op[arg_count] = gen_lowpart (V1DImode, op[arg_count]); 11555 11556 else if (insn_op->mode == V1SImode 11557 && GET_MODE (op[arg_count]) == SImode) 11558 op[arg_count] = gen_lowpart (V1SImode, op[arg_count]); 11559 11560 if (! (*insn_data[icode].operand[idx].predicate) (op[arg_count], 11561 insn_op->mode)) 11562 op[arg_count] = copy_to_mode_reg (insn_op->mode, op[arg_count]); 11563 } 11564 11565 switch (arg_count) 11566 { 11567 case 0: 11568 pat = GEN_FCN (icode) (op[0]); 11569 break; 11570 case 1: 11571 if (nonvoid) 11572 pat = GEN_FCN (icode) (op[0], op[1]); 11573 else 11574 pat = GEN_FCN (icode) (op[1]); 11575 break; 11576 case 2: 11577 pat = GEN_FCN (icode) (op[0], op[1], op[2]); 11578 break; 11579 case 3: 11580 pat = GEN_FCN (icode) (op[0], op[1], op[2], op[3]); 11581 break; 11582 default: 11583 gcc_unreachable (); 11584 } 11585 11586 if (!pat) 11587 return NULL_RTX; 11588 11589 emit_insn (pat); 11590 11591 return (nonvoid ? op[0] : const0_rtx); 11592 } 11593 11594 /* Return the upper 16 bits of the 8x16 multiplication. */ 11595 11596 static int 11597 sparc_vis_mul8x16 (int e8, int e16) 11598 { 11599 return (e8 * e16 + 128) / 256; 11600 } 11601 11602 /* Multiply the VECTOR_CSTs CST0 and CST1 as specified by FNCODE and put 11603 the result into the array N_ELTS, whose elements are of INNER_TYPE. */ 11604 11605 static void 11606 sparc_handle_vis_mul8x16 (tree *n_elts, enum sparc_builtins fncode, 11607 tree inner_type, tree cst0, tree cst1) 11608 { 11609 unsigned i, num = VECTOR_CST_NELTS (cst0); 11610 int scale; 11611 11612 switch (fncode) 11613 { 11614 case SPARC_BUILTIN_FMUL8X16: 11615 for (i = 0; i < num; ++i) 11616 { 11617 int val 11618 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)), 11619 TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, i))); 11620 n_elts[i] = build_int_cst (inner_type, val); 11621 } 11622 break; 11623 11624 case SPARC_BUILTIN_FMUL8X16AU: 11625 scale = TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, 0)); 11626 11627 for (i = 0; i < num; ++i) 11628 { 11629 int val 11630 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)), 11631 scale); 11632 n_elts[i] = build_int_cst (inner_type, val); 11633 } 11634 break; 11635 11636 case SPARC_BUILTIN_FMUL8X16AL: 11637 scale = TREE_INT_CST_LOW (VECTOR_CST_ELT (cst1, 1)); 11638 11639 for (i = 0; i < num; ++i) 11640 { 11641 int val 11642 = sparc_vis_mul8x16 (TREE_INT_CST_LOW (VECTOR_CST_ELT (cst0, i)), 11643 scale); 11644 n_elts[i] = build_int_cst (inner_type, val); 11645 } 11646 break; 11647 11648 default: 11649 gcc_unreachable (); 11650 } 11651 } 11652 11653 /* Implement TARGET_FOLD_BUILTIN hook. 11654 11655 Fold builtin functions for SPARC intrinsics. If IGNORE is true the 11656 result of the function call is ignored. NULL_TREE is returned if the 11657 function could not be folded. */ 11658 11659 static tree 11660 sparc_fold_builtin (tree fndecl, int n_args ATTRIBUTE_UNUSED, 11661 tree *args, bool ignore) 11662 { 11663 enum sparc_builtins code = (enum sparc_builtins) DECL_FUNCTION_CODE (fndecl); 11664 tree rtype = TREE_TYPE (TREE_TYPE (fndecl)); 11665 tree arg0, arg1, arg2; 11666 11667 if (ignore) 11668 switch (code) 11669 { 11670 case SPARC_BUILTIN_LDFSR: 11671 case SPARC_BUILTIN_STFSR: 11672 case SPARC_BUILTIN_ALIGNADDR: 11673 case SPARC_BUILTIN_WRGSR: 11674 case SPARC_BUILTIN_BMASK: 11675 case SPARC_BUILTIN_CMASK8: 11676 case SPARC_BUILTIN_CMASK16: 11677 case SPARC_BUILTIN_CMASK32: 11678 break; 11679 11680 default: 11681 return build_zero_cst (rtype); 11682 } 11683 11684 switch (code) 11685 { 11686 case SPARC_BUILTIN_FEXPAND: 11687 arg0 = args[0]; 11688 STRIP_NOPS (arg0); 11689 11690 if (TREE_CODE (arg0) == VECTOR_CST) 11691 { 11692 tree inner_type = TREE_TYPE (rtype); 11693 tree *n_elts; 11694 unsigned i; 11695 11696 n_elts = XALLOCAVEC (tree, VECTOR_CST_NELTS (arg0)); 11697 for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i) 11698 n_elts[i] = build_int_cst (inner_type, 11699 TREE_INT_CST_LOW 11700 (VECTOR_CST_ELT (arg0, i)) << 4); 11701 return build_vector (rtype, n_elts); 11702 } 11703 break; 11704 11705 case SPARC_BUILTIN_FMUL8X16: 11706 case SPARC_BUILTIN_FMUL8X16AU: 11707 case SPARC_BUILTIN_FMUL8X16AL: 11708 arg0 = args[0]; 11709 arg1 = args[1]; 11710 STRIP_NOPS (arg0); 11711 STRIP_NOPS (arg1); 11712 11713 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST) 11714 { 11715 tree inner_type = TREE_TYPE (rtype); 11716 tree *n_elts = XALLOCAVEC (tree, VECTOR_CST_NELTS (arg0)); 11717 sparc_handle_vis_mul8x16 (n_elts, code, inner_type, arg0, arg1); 11718 return build_vector (rtype, n_elts); 11719 } 11720 break; 11721 11722 case SPARC_BUILTIN_FPMERGE: 11723 arg0 = args[0]; 11724 arg1 = args[1]; 11725 STRIP_NOPS (arg0); 11726 STRIP_NOPS (arg1); 11727 11728 if (TREE_CODE (arg0) == VECTOR_CST && TREE_CODE (arg1) == VECTOR_CST) 11729 { 11730 tree *n_elts = XALLOCAVEC (tree, 2 * VECTOR_CST_NELTS (arg0)); 11731 unsigned i; 11732 for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i) 11733 { 11734 n_elts[2*i] = VECTOR_CST_ELT (arg0, i); 11735 n_elts[2*i+1] = VECTOR_CST_ELT (arg1, i); 11736 } 11737 11738 return build_vector (rtype, n_elts); 11739 } 11740 break; 11741 11742 case SPARC_BUILTIN_PDIST: 11743 case SPARC_BUILTIN_PDISTN: 11744 arg0 = args[0]; 11745 arg1 = args[1]; 11746 STRIP_NOPS (arg0); 11747 STRIP_NOPS (arg1); 11748 if (code == SPARC_BUILTIN_PDIST) 11749 { 11750 arg2 = args[2]; 11751 STRIP_NOPS (arg2); 11752 } 11753 else 11754 arg2 = integer_zero_node; 11755 11756 if (TREE_CODE (arg0) == VECTOR_CST 11757 && TREE_CODE (arg1) == VECTOR_CST 11758 && TREE_CODE (arg2) == INTEGER_CST) 11759 { 11760 bool overflow = false; 11761 widest_int result = wi::to_widest (arg2); 11762 widest_int tmp; 11763 unsigned i; 11764 11765 for (i = 0; i < VECTOR_CST_NELTS (arg0); ++i) 11766 { 11767 tree e0 = VECTOR_CST_ELT (arg0, i); 11768 tree e1 = VECTOR_CST_ELT (arg1, i); 11769 11770 bool neg1_ovf, neg2_ovf, add1_ovf, add2_ovf; 11771 11772 tmp = wi::neg (wi::to_widest (e1), &neg1_ovf); 11773 tmp = wi::add (wi::to_widest (e0), tmp, SIGNED, &add1_ovf); 11774 if (wi::neg_p (tmp)) 11775 tmp = wi::neg (tmp, &neg2_ovf); 11776 else 11777 neg2_ovf = false; 11778 result = wi::add (result, tmp, SIGNED, &add2_ovf); 11779 overflow |= neg1_ovf | neg2_ovf | add1_ovf | add2_ovf; 11780 } 11781 11782 gcc_assert (!overflow); 11783 11784 return wide_int_to_tree (rtype, result); 11785 } 11786 11787 default: 11788 break; 11789 } 11790 11791 return NULL_TREE; 11792 } 11793 11794 /* ??? This duplicates information provided to the compiler by the 11795 ??? scheduler description. Some day, teach genautomata to output 11796 ??? the latencies and then CSE will just use that. */ 11797 11798 static bool 11799 sparc_rtx_costs (rtx x, machine_mode mode, int outer_code, 11800 int opno ATTRIBUTE_UNUSED, 11801 int *total, bool speed ATTRIBUTE_UNUSED) 11802 { 11803 int code = GET_CODE (x); 11804 bool float_mode_p = FLOAT_MODE_P (mode); 11805 11806 switch (code) 11807 { 11808 case CONST_INT: 11809 if (SMALL_INT (x)) 11810 *total = 0; 11811 else 11812 *total = 2; 11813 return true; 11814 11815 case CONST_WIDE_INT: 11816 *total = 0; 11817 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x, 0))) 11818 *total += 2; 11819 if (!SPARC_SIMM13_P (CONST_WIDE_INT_ELT (x, 1))) 11820 *total += 2; 11821 return true; 11822 11823 case HIGH: 11824 *total = 2; 11825 return true; 11826 11827 case CONST: 11828 case LABEL_REF: 11829 case SYMBOL_REF: 11830 *total = 4; 11831 return true; 11832 11833 case CONST_DOUBLE: 11834 *total = 8; 11835 return true; 11836 11837 case MEM: 11838 /* If outer-code was a sign or zero extension, a cost 11839 of COSTS_N_INSNS (1) was already added in. This is 11840 why we are subtracting it back out. */ 11841 if (outer_code == ZERO_EXTEND) 11842 { 11843 *total = sparc_costs->int_zload - COSTS_N_INSNS (1); 11844 } 11845 else if (outer_code == SIGN_EXTEND) 11846 { 11847 *total = sparc_costs->int_sload - COSTS_N_INSNS (1); 11848 } 11849 else if (float_mode_p) 11850 { 11851 *total = sparc_costs->float_load; 11852 } 11853 else 11854 { 11855 *total = sparc_costs->int_load; 11856 } 11857 11858 return true; 11859 11860 case PLUS: 11861 case MINUS: 11862 if (float_mode_p) 11863 *total = sparc_costs->float_plusminus; 11864 else 11865 *total = COSTS_N_INSNS (1); 11866 return false; 11867 11868 case FMA: 11869 { 11870 rtx sub; 11871 11872 gcc_assert (float_mode_p); 11873 *total = sparc_costs->float_mul; 11874 11875 sub = XEXP (x, 0); 11876 if (GET_CODE (sub) == NEG) 11877 sub = XEXP (sub, 0); 11878 *total += rtx_cost (sub, mode, FMA, 0, speed); 11879 11880 sub = XEXP (x, 2); 11881 if (GET_CODE (sub) == NEG) 11882 sub = XEXP (sub, 0); 11883 *total += rtx_cost (sub, mode, FMA, 2, speed); 11884 return true; 11885 } 11886 11887 case MULT: 11888 if (float_mode_p) 11889 *total = sparc_costs->float_mul; 11890 else if (TARGET_ARCH32 && !TARGET_HARD_MUL) 11891 *total = COSTS_N_INSNS (25); 11892 else 11893 { 11894 int bit_cost; 11895 11896 bit_cost = 0; 11897 if (sparc_costs->int_mul_bit_factor) 11898 { 11899 int nbits; 11900 11901 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 11902 { 11903 unsigned HOST_WIDE_INT value = INTVAL (XEXP (x, 1)); 11904 for (nbits = 0; value != 0; value &= value - 1) 11905 nbits++; 11906 } 11907 else 11908 nbits = 7; 11909 11910 if (nbits < 3) 11911 nbits = 3; 11912 bit_cost = (nbits - 3) / sparc_costs->int_mul_bit_factor; 11913 bit_cost = COSTS_N_INSNS (bit_cost); 11914 } 11915 11916 if (mode == DImode || !TARGET_HARD_MUL) 11917 *total = sparc_costs->int_mulX + bit_cost; 11918 else 11919 *total = sparc_costs->int_mul + bit_cost; 11920 } 11921 return false; 11922 11923 case ASHIFT: 11924 case ASHIFTRT: 11925 case LSHIFTRT: 11926 *total = COSTS_N_INSNS (1) + sparc_costs->shift_penalty; 11927 return false; 11928 11929 case DIV: 11930 case UDIV: 11931 case MOD: 11932 case UMOD: 11933 if (float_mode_p) 11934 { 11935 if (mode == DFmode) 11936 *total = sparc_costs->float_div_df; 11937 else 11938 *total = sparc_costs->float_div_sf; 11939 } 11940 else 11941 { 11942 if (mode == DImode) 11943 *total = sparc_costs->int_divX; 11944 else 11945 *total = sparc_costs->int_div; 11946 } 11947 return false; 11948 11949 case NEG: 11950 if (! float_mode_p) 11951 { 11952 *total = COSTS_N_INSNS (1); 11953 return false; 11954 } 11955 /* FALLTHRU */ 11956 11957 case ABS: 11958 case FLOAT: 11959 case UNSIGNED_FLOAT: 11960 case FIX: 11961 case UNSIGNED_FIX: 11962 case FLOAT_EXTEND: 11963 case FLOAT_TRUNCATE: 11964 *total = sparc_costs->float_move; 11965 return false; 11966 11967 case SQRT: 11968 if (mode == DFmode) 11969 *total = sparc_costs->float_sqrt_df; 11970 else 11971 *total = sparc_costs->float_sqrt_sf; 11972 return false; 11973 11974 case COMPARE: 11975 if (float_mode_p) 11976 *total = sparc_costs->float_cmp; 11977 else 11978 *total = COSTS_N_INSNS (1); 11979 return false; 11980 11981 case IF_THEN_ELSE: 11982 if (float_mode_p) 11983 *total = sparc_costs->float_cmove; 11984 else 11985 *total = sparc_costs->int_cmove; 11986 return false; 11987 11988 case IOR: 11989 /* Handle the NAND vector patterns. */ 11990 if (sparc_vector_mode_supported_p (mode) 11991 && GET_CODE (XEXP (x, 0)) == NOT 11992 && GET_CODE (XEXP (x, 1)) == NOT) 11993 { 11994 *total = COSTS_N_INSNS (1); 11995 return true; 11996 } 11997 else 11998 return false; 11999 12000 default: 12001 return false; 12002 } 12003 } 12004 12005 /* Return true if CLASS is either GENERAL_REGS or I64_REGS. */ 12006 12007 static inline bool 12008 general_or_i64_p (reg_class_t rclass) 12009 { 12010 return (rclass == GENERAL_REGS || rclass == I64_REGS); 12011 } 12012 12013 /* Implement TARGET_REGISTER_MOVE_COST. */ 12014 12015 static int 12016 sparc_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 12017 reg_class_t from, reg_class_t to) 12018 { 12019 bool need_memory = false; 12020 12021 /* This helps postreload CSE to eliminate redundant comparisons. */ 12022 if (from == NO_REGS || to == NO_REGS) 12023 return 100; 12024 12025 if (from == FPCC_REGS || to == FPCC_REGS) 12026 need_memory = true; 12027 else if ((FP_REG_CLASS_P (from) && general_or_i64_p (to)) 12028 || (general_or_i64_p (from) && FP_REG_CLASS_P (to))) 12029 { 12030 if (TARGET_VIS3) 12031 { 12032 int size = GET_MODE_SIZE (mode); 12033 if (size == 8 || size == 4) 12034 { 12035 if (! TARGET_ARCH32 || size == 4) 12036 return 4; 12037 else 12038 return 6; 12039 } 12040 } 12041 need_memory = true; 12042 } 12043 12044 if (need_memory) 12045 { 12046 if (sparc_cpu == PROCESSOR_ULTRASPARC 12047 || sparc_cpu == PROCESSOR_ULTRASPARC3 12048 || sparc_cpu == PROCESSOR_NIAGARA 12049 || sparc_cpu == PROCESSOR_NIAGARA2 12050 || sparc_cpu == PROCESSOR_NIAGARA3 12051 || sparc_cpu == PROCESSOR_NIAGARA4 12052 || sparc_cpu == PROCESSOR_NIAGARA7 12053 || sparc_cpu == PROCESSOR_M8) 12054 return 12; 12055 12056 return 6; 12057 } 12058 12059 return 2; 12060 } 12061 12062 /* Emit the sequence of insns SEQ while preserving the registers REG and REG2. 12063 This is achieved by means of a manual dynamic stack space allocation in 12064 the current frame. We make the assumption that SEQ doesn't contain any 12065 function calls, with the possible exception of calls to the GOT helper. */ 12066 12067 static void 12068 emit_and_preserve (rtx seq, rtx reg, rtx reg2) 12069 { 12070 /* We must preserve the lowest 16 words for the register save area. */ 12071 HOST_WIDE_INT offset = 16*UNITS_PER_WORD; 12072 /* We really need only 2 words of fresh stack space. */ 12073 HOST_WIDE_INT size = SPARC_STACK_ALIGN (offset + 2*UNITS_PER_WORD); 12074 12075 rtx slot 12076 = gen_rtx_MEM (word_mode, plus_constant (Pmode, stack_pointer_rtx, 12077 SPARC_STACK_BIAS + offset)); 12078 12079 emit_insn (gen_stack_pointer_inc (GEN_INT (-size))); 12080 emit_insn (gen_rtx_SET (slot, reg)); 12081 if (reg2) 12082 emit_insn (gen_rtx_SET (adjust_address (slot, word_mode, UNITS_PER_WORD), 12083 reg2)); 12084 emit_insn (seq); 12085 if (reg2) 12086 emit_insn (gen_rtx_SET (reg2, 12087 adjust_address (slot, word_mode, UNITS_PER_WORD))); 12088 emit_insn (gen_rtx_SET (reg, slot)); 12089 emit_insn (gen_stack_pointer_inc (GEN_INT (size))); 12090 } 12091 12092 /* Output the assembler code for a thunk function. THUNK_DECL is the 12093 declaration for the thunk function itself, FUNCTION is the decl for 12094 the target function. DELTA is an immediate constant offset to be 12095 added to THIS. If VCALL_OFFSET is nonzero, the word at address 12096 (*THIS + VCALL_OFFSET) should be additionally added to THIS. */ 12097 12098 static void 12099 sparc_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 12100 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 12101 tree function) 12102 { 12103 rtx this_rtx, funexp; 12104 rtx_insn *insn; 12105 unsigned int int_arg_first; 12106 12107 reload_completed = 1; 12108 epilogue_completed = 1; 12109 12110 emit_note (NOTE_INSN_PROLOGUE_END); 12111 12112 if (TARGET_FLAT) 12113 { 12114 sparc_leaf_function_p = 1; 12115 12116 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST; 12117 } 12118 else if (flag_delayed_branch) 12119 { 12120 /* We will emit a regular sibcall below, so we need to instruct 12121 output_sibcall that we are in a leaf function. */ 12122 sparc_leaf_function_p = crtl->uses_only_leaf_regs = 1; 12123 12124 /* This will cause final.c to invoke leaf_renumber_regs so we 12125 must behave as if we were in a not-yet-leafified function. */ 12126 int_arg_first = SPARC_INCOMING_INT_ARG_FIRST; 12127 } 12128 else 12129 { 12130 /* We will emit the sibcall manually below, so we will need to 12131 manually spill non-leaf registers. */ 12132 sparc_leaf_function_p = crtl->uses_only_leaf_regs = 0; 12133 12134 /* We really are in a leaf function. */ 12135 int_arg_first = SPARC_OUTGOING_INT_ARG_FIRST; 12136 } 12137 12138 /* Find the "this" pointer. Normally in %o0, but in ARCH64 if the function 12139 returns a structure, the structure return pointer is there instead. */ 12140 if (TARGET_ARCH64 12141 && aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 12142 this_rtx = gen_rtx_REG (Pmode, int_arg_first + 1); 12143 else 12144 this_rtx = gen_rtx_REG (Pmode, int_arg_first); 12145 12146 /* Add DELTA. When possible use a plain add, otherwise load it into 12147 a register first. */ 12148 if (delta) 12149 { 12150 rtx delta_rtx = GEN_INT (delta); 12151 12152 if (! SPARC_SIMM13_P (delta)) 12153 { 12154 rtx scratch = gen_rtx_REG (Pmode, 1); 12155 emit_move_insn (scratch, delta_rtx); 12156 delta_rtx = scratch; 12157 } 12158 12159 /* THIS_RTX += DELTA. */ 12160 emit_insn (gen_add2_insn (this_rtx, delta_rtx)); 12161 } 12162 12163 /* Add the word at address (*THIS_RTX + VCALL_OFFSET). */ 12164 if (vcall_offset) 12165 { 12166 rtx vcall_offset_rtx = GEN_INT (vcall_offset); 12167 rtx scratch = gen_rtx_REG (Pmode, 1); 12168 12169 gcc_assert (vcall_offset < 0); 12170 12171 /* SCRATCH = *THIS_RTX. */ 12172 emit_move_insn (scratch, gen_rtx_MEM (Pmode, this_rtx)); 12173 12174 /* Prepare for adding VCALL_OFFSET. The difficulty is that we 12175 may not have any available scratch register at this point. */ 12176 if (SPARC_SIMM13_P (vcall_offset)) 12177 ; 12178 /* This is the case if ARCH64 (unless -ffixed-g5 is passed). */ 12179 else if (! fixed_regs[5] 12180 /* The below sequence is made up of at least 2 insns, 12181 while the default method may need only one. */ 12182 && vcall_offset < -8192) 12183 { 12184 rtx scratch2 = gen_rtx_REG (Pmode, 5); 12185 emit_move_insn (scratch2, vcall_offset_rtx); 12186 vcall_offset_rtx = scratch2; 12187 } 12188 else 12189 { 12190 rtx increment = GEN_INT (-4096); 12191 12192 /* VCALL_OFFSET is a negative number whose typical range can be 12193 estimated as -32768..0 in 32-bit mode. In almost all cases 12194 it is therefore cheaper to emit multiple add insns than 12195 spilling and loading the constant into a register (at least 12196 6 insns). */ 12197 while (! SPARC_SIMM13_P (vcall_offset)) 12198 { 12199 emit_insn (gen_add2_insn (scratch, increment)); 12200 vcall_offset += 4096; 12201 } 12202 vcall_offset_rtx = GEN_INT (vcall_offset); /* cannot be 0 */ 12203 } 12204 12205 /* SCRATCH = *(*THIS_RTX + VCALL_OFFSET). */ 12206 emit_move_insn (scratch, gen_rtx_MEM (Pmode, 12207 gen_rtx_PLUS (Pmode, 12208 scratch, 12209 vcall_offset_rtx))); 12210 12211 /* THIS_RTX += *(*THIS_RTX + VCALL_OFFSET). */ 12212 emit_insn (gen_add2_insn (this_rtx, scratch)); 12213 } 12214 12215 /* Generate a tail call to the target function. */ 12216 if (! TREE_USED (function)) 12217 { 12218 assemble_external (function); 12219 TREE_USED (function) = 1; 12220 } 12221 funexp = XEXP (DECL_RTL (function), 0); 12222 12223 if (flag_delayed_branch) 12224 { 12225 funexp = gen_rtx_MEM (FUNCTION_MODE, funexp); 12226 insn = emit_call_insn (gen_sibcall (funexp)); 12227 SIBLING_CALL_P (insn) = 1; 12228 } 12229 else 12230 { 12231 /* The hoops we have to jump through in order to generate a sibcall 12232 without using delay slots... */ 12233 rtx spill_reg, seq, scratch = gen_rtx_REG (Pmode, 1); 12234 12235 if (flag_pic) 12236 { 12237 spill_reg = gen_rtx_REG (word_mode, 15); /* %o7 */ 12238 start_sequence (); 12239 load_got_register (); /* clobbers %o7 */ 12240 scratch = sparc_legitimize_pic_address (funexp, scratch); 12241 seq = get_insns (); 12242 end_sequence (); 12243 emit_and_preserve (seq, spill_reg, pic_offset_table_rtx); 12244 } 12245 else if (TARGET_ARCH32) 12246 { 12247 emit_insn (gen_rtx_SET (scratch, 12248 gen_rtx_HIGH (SImode, funexp))); 12249 emit_insn (gen_rtx_SET (scratch, 12250 gen_rtx_LO_SUM (SImode, scratch, funexp))); 12251 } 12252 else /* TARGET_ARCH64 */ 12253 { 12254 switch (sparc_cmodel) 12255 { 12256 case CM_MEDLOW: 12257 case CM_MEDMID: 12258 /* The destination can serve as a temporary. */ 12259 sparc_emit_set_symbolic_const64 (scratch, funexp, scratch); 12260 break; 12261 12262 case CM_MEDANY: 12263 case CM_EMBMEDANY: 12264 /* The destination cannot serve as a temporary. */ 12265 spill_reg = gen_rtx_REG (DImode, 15); /* %o7 */ 12266 start_sequence (); 12267 sparc_emit_set_symbolic_const64 (scratch, funexp, spill_reg); 12268 seq = get_insns (); 12269 end_sequence (); 12270 emit_and_preserve (seq, spill_reg, 0); 12271 break; 12272 12273 default: 12274 gcc_unreachable (); 12275 } 12276 } 12277 12278 emit_jump_insn (gen_indirect_jump (scratch)); 12279 } 12280 12281 emit_barrier (); 12282 12283 /* Run just enough of rest_of_compilation to get the insns emitted. 12284 There's not really enough bulk here to make other passes such as 12285 instruction scheduling worth while. Note that use_thunk calls 12286 assemble_start_function and assemble_end_function. */ 12287 insn = get_insns (); 12288 shorten_branches (insn); 12289 final_start_function (insn, file, 1); 12290 final (insn, file, 1); 12291 final_end_function (); 12292 12293 reload_completed = 0; 12294 epilogue_completed = 0; 12295 } 12296 12297 /* Return true if sparc_output_mi_thunk would be able to output the 12298 assembler code for the thunk function specified by the arguments 12299 it is passed, and false otherwise. */ 12300 static bool 12301 sparc_can_output_mi_thunk (const_tree thunk_fndecl ATTRIBUTE_UNUSED, 12302 HOST_WIDE_INT delta ATTRIBUTE_UNUSED, 12303 HOST_WIDE_INT vcall_offset, 12304 const_tree function ATTRIBUTE_UNUSED) 12305 { 12306 /* Bound the loop used in the default method above. */ 12307 return (vcall_offset >= -32768 || ! fixed_regs[5]); 12308 } 12309 12310 /* How to allocate a 'struct machine_function'. */ 12311 12312 static struct machine_function * 12313 sparc_init_machine_status (void) 12314 { 12315 return ggc_cleared_alloc<machine_function> (); 12316 } 12317 12318 /* This is called from dwarf2out.c via TARGET_ASM_OUTPUT_DWARF_DTPREL. 12319 We need to emit DTP-relative relocations. */ 12320 12321 static void 12322 sparc_output_dwarf_dtprel (FILE *file, int size, rtx x) 12323 { 12324 switch (size) 12325 { 12326 case 4: 12327 fputs ("\t.word\t%r_tls_dtpoff32(", file); 12328 break; 12329 case 8: 12330 fputs ("\t.xword\t%r_tls_dtpoff64(", file); 12331 break; 12332 default: 12333 gcc_unreachable (); 12334 } 12335 output_addr_const (file, x); 12336 fputs (")", file); 12337 } 12338 12339 /* Do whatever processing is required at the end of a file. */ 12340 12341 static void 12342 sparc_file_end (void) 12343 { 12344 /* If we need to emit the special GOT helper function, do so now. */ 12345 if (got_helper_rtx) 12346 { 12347 const char *name = XSTR (got_helper_rtx, 0); 12348 const char *reg_name = reg_names[GLOBAL_OFFSET_TABLE_REGNUM]; 12349 #ifdef DWARF2_UNWIND_INFO 12350 bool do_cfi; 12351 #endif 12352 12353 if (USE_HIDDEN_LINKONCE) 12354 { 12355 tree decl = build_decl (BUILTINS_LOCATION, FUNCTION_DECL, 12356 get_identifier (name), 12357 build_function_type_list (void_type_node, 12358 NULL_TREE)); 12359 DECL_RESULT (decl) = build_decl (BUILTINS_LOCATION, RESULT_DECL, 12360 NULL_TREE, void_type_node); 12361 TREE_PUBLIC (decl) = 1; 12362 TREE_STATIC (decl) = 1; 12363 make_decl_one_only (decl, DECL_ASSEMBLER_NAME (decl)); 12364 DECL_VISIBILITY (decl) = VISIBILITY_HIDDEN; 12365 DECL_VISIBILITY_SPECIFIED (decl) = 1; 12366 resolve_unique_section (decl, 0, flag_function_sections); 12367 allocate_struct_function (decl, true); 12368 cfun->is_thunk = 1; 12369 current_function_decl = decl; 12370 init_varasm_status (); 12371 assemble_start_function (decl, name); 12372 } 12373 else 12374 { 12375 const int align = floor_log2 (FUNCTION_BOUNDARY / BITS_PER_UNIT); 12376 switch_to_section (text_section); 12377 if (align > 0) 12378 ASM_OUTPUT_ALIGN (asm_out_file, align); 12379 ASM_OUTPUT_LABEL (asm_out_file, name); 12380 } 12381 12382 #ifdef DWARF2_UNWIND_INFO 12383 do_cfi = dwarf2out_do_cfi_asm (); 12384 if (do_cfi) 12385 fprintf (asm_out_file, "\t.cfi_startproc\n"); 12386 #endif 12387 if (flag_delayed_branch) 12388 fprintf (asm_out_file, "\tjmp\t%%o7+8\n\t add\t%%o7, %s, %s\n", 12389 reg_name, reg_name); 12390 else 12391 fprintf (asm_out_file, "\tadd\t%%o7, %s, %s\n\tjmp\t%%o7+8\n\t nop\n", 12392 reg_name, reg_name); 12393 #ifdef DWARF2_UNWIND_INFO 12394 if (do_cfi) 12395 fprintf (asm_out_file, "\t.cfi_endproc\n"); 12396 #endif 12397 } 12398 12399 if (NEED_INDICATE_EXEC_STACK) 12400 file_end_indicate_exec_stack (); 12401 12402 #ifdef TARGET_SOLARIS 12403 solaris_file_end (); 12404 #endif 12405 } 12406 12407 #ifdef TARGET_ALTERNATE_LONG_DOUBLE_MANGLING 12408 /* Implement TARGET_MANGLE_TYPE. */ 12409 12410 static const char * 12411 sparc_mangle_type (const_tree type) 12412 { 12413 if (TARGET_ARCH32 12414 && TYPE_MAIN_VARIANT (type) == long_double_type_node 12415 && TARGET_LONG_DOUBLE_128) 12416 return "g"; 12417 12418 /* For all other types, use normal C++ mangling. */ 12419 return NULL; 12420 } 12421 #endif 12422 12423 /* Expand a membar instruction for various use cases. Both the LOAD_STORE 12424 and BEFORE_AFTER arguments of the form X_Y. They are two-bit masks where 12425 bit 0 indicates that X is true, and bit 1 indicates Y is true. */ 12426 12427 void 12428 sparc_emit_membar_for_model (enum memmodel model, 12429 int load_store, int before_after) 12430 { 12431 /* Bits for the MEMBAR mmask field. */ 12432 const int LoadLoad = 1; 12433 const int StoreLoad = 2; 12434 const int LoadStore = 4; 12435 const int StoreStore = 8; 12436 12437 int mm = 0, implied = 0; 12438 12439 switch (sparc_memory_model) 12440 { 12441 case SMM_SC: 12442 /* Sequential Consistency. All memory transactions are immediately 12443 visible in sequential execution order. No barriers needed. */ 12444 implied = LoadLoad | StoreLoad | LoadStore | StoreStore; 12445 break; 12446 12447 case SMM_TSO: 12448 /* Total Store Ordering: all memory transactions with store semantics 12449 are followed by an implied StoreStore. */ 12450 implied |= StoreStore; 12451 12452 /* If we're not looking for a raw barrer (before+after), then atomic 12453 operations get the benefit of being both load and store. */ 12454 if (load_store == 3 && before_after == 1) 12455 implied |= StoreLoad; 12456 /* FALLTHRU */ 12457 12458 case SMM_PSO: 12459 /* Partial Store Ordering: all memory transactions with load semantics 12460 are followed by an implied LoadLoad | LoadStore. */ 12461 implied |= LoadLoad | LoadStore; 12462 12463 /* If we're not looking for a raw barrer (before+after), then atomic 12464 operations get the benefit of being both load and store. */ 12465 if (load_store == 3 && before_after == 2) 12466 implied |= StoreLoad | StoreStore; 12467 /* FALLTHRU */ 12468 12469 case SMM_RMO: 12470 /* Relaxed Memory Ordering: no implicit bits. */ 12471 break; 12472 12473 default: 12474 gcc_unreachable (); 12475 } 12476 12477 if (before_after & 1) 12478 { 12479 if (is_mm_release (model) || is_mm_acq_rel (model) 12480 || is_mm_seq_cst (model)) 12481 { 12482 if (load_store & 1) 12483 mm |= LoadLoad | StoreLoad; 12484 if (load_store & 2) 12485 mm |= LoadStore | StoreStore; 12486 } 12487 } 12488 if (before_after & 2) 12489 { 12490 if (is_mm_acquire (model) || is_mm_acq_rel (model) 12491 || is_mm_seq_cst (model)) 12492 { 12493 if (load_store & 1) 12494 mm |= LoadLoad | LoadStore; 12495 if (load_store & 2) 12496 mm |= StoreLoad | StoreStore; 12497 } 12498 } 12499 12500 /* Remove the bits implied by the system memory model. */ 12501 mm &= ~implied; 12502 12503 /* For raw barriers (before+after), always emit a barrier. 12504 This will become a compile-time barrier if needed. */ 12505 if (mm || before_after == 3) 12506 emit_insn (gen_membar (GEN_INT (mm))); 12507 } 12508 12509 /* Expand code to perform a 8 or 16-bit compare and swap by doing 32-bit 12510 compare and swap on the word containing the byte or half-word. */ 12511 12512 static void 12513 sparc_expand_compare_and_swap_12 (rtx bool_result, rtx result, rtx mem, 12514 rtx oldval, rtx newval) 12515 { 12516 rtx addr1 = force_reg (Pmode, XEXP (mem, 0)); 12517 rtx addr = gen_reg_rtx (Pmode); 12518 rtx off = gen_reg_rtx (SImode); 12519 rtx oldv = gen_reg_rtx (SImode); 12520 rtx newv = gen_reg_rtx (SImode); 12521 rtx oldvalue = gen_reg_rtx (SImode); 12522 rtx newvalue = gen_reg_rtx (SImode); 12523 rtx res = gen_reg_rtx (SImode); 12524 rtx resv = gen_reg_rtx (SImode); 12525 rtx memsi, val, mask, cc; 12526 12527 emit_insn (gen_rtx_SET (addr, gen_rtx_AND (Pmode, addr1, GEN_INT (-4)))); 12528 12529 if (Pmode != SImode) 12530 addr1 = gen_lowpart (SImode, addr1); 12531 emit_insn (gen_rtx_SET (off, gen_rtx_AND (SImode, addr1, GEN_INT (3)))); 12532 12533 memsi = gen_rtx_MEM (SImode, addr); 12534 set_mem_alias_set (memsi, ALIAS_SET_MEMORY_BARRIER); 12535 MEM_VOLATILE_P (memsi) = MEM_VOLATILE_P (mem); 12536 12537 val = copy_to_reg (memsi); 12538 12539 emit_insn (gen_rtx_SET (off, 12540 gen_rtx_XOR (SImode, off, 12541 GEN_INT (GET_MODE (mem) == QImode 12542 ? 3 : 2)))); 12543 12544 emit_insn (gen_rtx_SET (off, gen_rtx_ASHIFT (SImode, off, GEN_INT (3)))); 12545 12546 if (GET_MODE (mem) == QImode) 12547 mask = force_reg (SImode, GEN_INT (0xff)); 12548 else 12549 mask = force_reg (SImode, GEN_INT (0xffff)); 12550 12551 emit_insn (gen_rtx_SET (mask, gen_rtx_ASHIFT (SImode, mask, off))); 12552 12553 emit_insn (gen_rtx_SET (val, 12554 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), 12555 val))); 12556 12557 oldval = gen_lowpart (SImode, oldval); 12558 emit_insn (gen_rtx_SET (oldv, gen_rtx_ASHIFT (SImode, oldval, off))); 12559 12560 newval = gen_lowpart_common (SImode, newval); 12561 emit_insn (gen_rtx_SET (newv, gen_rtx_ASHIFT (SImode, newval, off))); 12562 12563 emit_insn (gen_rtx_SET (oldv, gen_rtx_AND (SImode, oldv, mask))); 12564 12565 emit_insn (gen_rtx_SET (newv, gen_rtx_AND (SImode, newv, mask))); 12566 12567 rtx_code_label *end_label = gen_label_rtx (); 12568 rtx_code_label *loop_label = gen_label_rtx (); 12569 emit_label (loop_label); 12570 12571 emit_insn (gen_rtx_SET (oldvalue, gen_rtx_IOR (SImode, oldv, val))); 12572 12573 emit_insn (gen_rtx_SET (newvalue, gen_rtx_IOR (SImode, newv, val))); 12574 12575 emit_move_insn (bool_result, const1_rtx); 12576 12577 emit_insn (gen_atomic_compare_and_swapsi_1 (res, memsi, oldvalue, newvalue)); 12578 12579 emit_cmp_and_jump_insns (res, oldvalue, EQ, NULL, SImode, 0, end_label); 12580 12581 emit_insn (gen_rtx_SET (resv, 12582 gen_rtx_AND (SImode, gen_rtx_NOT (SImode, mask), 12583 res))); 12584 12585 emit_move_insn (bool_result, const0_rtx); 12586 12587 cc = gen_compare_reg_1 (NE, resv, val); 12588 emit_insn (gen_rtx_SET (val, resv)); 12589 12590 /* Use cbranchcc4 to separate the compare and branch! */ 12591 emit_jump_insn (gen_cbranchcc4 (gen_rtx_NE (VOIDmode, cc, const0_rtx), 12592 cc, const0_rtx, loop_label)); 12593 12594 emit_label (end_label); 12595 12596 emit_insn (gen_rtx_SET (res, gen_rtx_AND (SImode, res, mask))); 12597 12598 emit_insn (gen_rtx_SET (res, gen_rtx_LSHIFTRT (SImode, res, off))); 12599 12600 emit_move_insn (result, gen_lowpart (GET_MODE (result), res)); 12601 } 12602 12603 /* Expand code to perform a compare-and-swap. */ 12604 12605 void 12606 sparc_expand_compare_and_swap (rtx operands[]) 12607 { 12608 rtx bval, retval, mem, oldval, newval; 12609 machine_mode mode; 12610 enum memmodel model; 12611 12612 bval = operands[0]; 12613 retval = operands[1]; 12614 mem = operands[2]; 12615 oldval = operands[3]; 12616 newval = operands[4]; 12617 model = (enum memmodel) INTVAL (operands[6]); 12618 mode = GET_MODE (mem); 12619 12620 sparc_emit_membar_for_model (model, 3, 1); 12621 12622 if (reg_overlap_mentioned_p (retval, oldval)) 12623 oldval = copy_to_reg (oldval); 12624 12625 if (mode == QImode || mode == HImode) 12626 sparc_expand_compare_and_swap_12 (bval, retval, mem, oldval, newval); 12627 else 12628 { 12629 rtx (*gen) (rtx, rtx, rtx, rtx); 12630 rtx x; 12631 12632 if (mode == SImode) 12633 gen = gen_atomic_compare_and_swapsi_1; 12634 else 12635 gen = gen_atomic_compare_and_swapdi_1; 12636 emit_insn (gen (retval, mem, oldval, newval)); 12637 12638 x = emit_store_flag (bval, EQ, retval, oldval, mode, 1, 1); 12639 if (x != bval) 12640 convert_move (bval, x, 1); 12641 } 12642 12643 sparc_emit_membar_for_model (model, 3, 2); 12644 } 12645 12646 void 12647 sparc_expand_vec_perm_bmask (machine_mode vmode, rtx sel) 12648 { 12649 rtx t_1, t_2, t_3; 12650 12651 sel = gen_lowpart (DImode, sel); 12652 switch (vmode) 12653 { 12654 case V2SImode: 12655 /* inp = xxxxxxxAxxxxxxxB */ 12656 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16), 12657 NULL_RTX, 1, OPTAB_DIRECT); 12658 /* t_1 = ....xxxxxxxAxxx. */ 12659 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel), 12660 GEN_INT (3), NULL_RTX, 1, OPTAB_DIRECT); 12661 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1), 12662 GEN_INT (0x30000), NULL_RTX, 1, OPTAB_DIRECT); 12663 /* sel = .......B */ 12664 /* t_1 = ...A.... */ 12665 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT); 12666 /* sel = ...A...B */ 12667 sel = expand_mult (SImode, sel, GEN_INT (0x4444), sel, 1); 12668 /* sel = AAAABBBB * 4 */ 12669 t_1 = force_reg (SImode, GEN_INT (0x01230123)); 12670 /* sel = { A*4, A*4+1, A*4+2, ... } */ 12671 break; 12672 12673 case V4HImode: 12674 /* inp = xxxAxxxBxxxCxxxD */ 12675 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8), 12676 NULL_RTX, 1, OPTAB_DIRECT); 12677 t_2 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16), 12678 NULL_RTX, 1, OPTAB_DIRECT); 12679 t_3 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (24), 12680 NULL_RTX, 1, OPTAB_DIRECT); 12681 /* t_1 = ..xxxAxxxBxxxCxx */ 12682 /* t_2 = ....xxxAxxxBxxxC */ 12683 /* t_3 = ......xxxAxxxBxx */ 12684 sel = expand_simple_binop (SImode, AND, gen_lowpart (SImode, sel), 12685 GEN_INT (0x07), 12686 NULL_RTX, 1, OPTAB_DIRECT); 12687 t_1 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_1), 12688 GEN_INT (0x0700), 12689 NULL_RTX, 1, OPTAB_DIRECT); 12690 t_2 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_2), 12691 GEN_INT (0x070000), 12692 NULL_RTX, 1, OPTAB_DIRECT); 12693 t_3 = expand_simple_binop (SImode, AND, gen_lowpart (SImode, t_3), 12694 GEN_INT (0x07000000), 12695 NULL_RTX, 1, OPTAB_DIRECT); 12696 /* sel = .......D */ 12697 /* t_1 = .....C.. */ 12698 /* t_2 = ...B.... */ 12699 /* t_3 = .A...... */ 12700 sel = expand_simple_binop (SImode, IOR, sel, t_1, sel, 1, OPTAB_DIRECT); 12701 t_2 = expand_simple_binop (SImode, IOR, t_2, t_3, t_2, 1, OPTAB_DIRECT); 12702 sel = expand_simple_binop (SImode, IOR, sel, t_2, sel, 1, OPTAB_DIRECT); 12703 /* sel = .A.B.C.D */ 12704 sel = expand_mult (SImode, sel, GEN_INT (0x22), sel, 1); 12705 /* sel = AABBCCDD * 2 */ 12706 t_1 = force_reg (SImode, GEN_INT (0x01010101)); 12707 /* sel = { A*2, A*2+1, B*2, B*2+1, ... } */ 12708 break; 12709 12710 case V8QImode: 12711 /* input = xAxBxCxDxExFxGxH */ 12712 sel = expand_simple_binop (DImode, AND, sel, 12713 GEN_INT ((HOST_WIDE_INT)0x0f0f0f0f << 32 12714 | 0x0f0f0f0f), 12715 NULL_RTX, 1, OPTAB_DIRECT); 12716 /* sel = .A.B.C.D.E.F.G.H */ 12717 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (4), 12718 NULL_RTX, 1, OPTAB_DIRECT); 12719 /* t_1 = ..A.B.C.D.E.F.G. */ 12720 sel = expand_simple_binop (DImode, IOR, sel, t_1, 12721 NULL_RTX, 1, OPTAB_DIRECT); 12722 /* sel = .AABBCCDDEEFFGGH */ 12723 sel = expand_simple_binop (DImode, AND, sel, 12724 GEN_INT ((HOST_WIDE_INT)0xff00ff << 32 12725 | 0xff00ff), 12726 NULL_RTX, 1, OPTAB_DIRECT); 12727 /* sel = ..AB..CD..EF..GH */ 12728 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (8), 12729 NULL_RTX, 1, OPTAB_DIRECT); 12730 /* t_1 = ....AB..CD..EF.. */ 12731 sel = expand_simple_binop (DImode, IOR, sel, t_1, 12732 NULL_RTX, 1, OPTAB_DIRECT); 12733 /* sel = ..ABABCDCDEFEFGH */ 12734 sel = expand_simple_binop (DImode, AND, sel, 12735 GEN_INT ((HOST_WIDE_INT)0xffff << 32 | 0xffff), 12736 NULL_RTX, 1, OPTAB_DIRECT); 12737 /* sel = ....ABCD....EFGH */ 12738 t_1 = expand_simple_binop (DImode, LSHIFTRT, sel, GEN_INT (16), 12739 NULL_RTX, 1, OPTAB_DIRECT); 12740 /* t_1 = ........ABCD.... */ 12741 sel = gen_lowpart (SImode, sel); 12742 t_1 = gen_lowpart (SImode, t_1); 12743 break; 12744 12745 default: 12746 gcc_unreachable (); 12747 } 12748 12749 /* Always perform the final addition/merge within the bmask insn. */ 12750 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, t_1)); 12751 } 12752 12753 /* Implement TARGET_FRAME_POINTER_REQUIRED. */ 12754 12755 static bool 12756 sparc_frame_pointer_required (void) 12757 { 12758 /* If the stack pointer is dynamically modified in the function, it cannot 12759 serve as the frame pointer. */ 12760 if (cfun->calls_alloca) 12761 return true; 12762 12763 /* If the function receives nonlocal gotos, it needs to save the frame 12764 pointer in the nonlocal_goto_save_area object. */ 12765 if (cfun->has_nonlocal_label) 12766 return true; 12767 12768 /* In flat mode, that's it. */ 12769 if (TARGET_FLAT) 12770 return false; 12771 12772 /* Otherwise, the frame pointer is required if the function isn't leaf, but 12773 we cannot use sparc_leaf_function_p since it hasn't been computed yet. */ 12774 return !(optimize > 0 && crtl->is_leaf && only_leaf_regs_used ()); 12775 } 12776 12777 /* The way this is structured, we can't eliminate SFP in favor of SP 12778 if the frame pointer is required: we want to use the SFP->HFP elimination 12779 in that case. But the test in update_eliminables doesn't know we are 12780 assuming below that we only do the former elimination. */ 12781 12782 static bool 12783 sparc_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 12784 { 12785 return to == HARD_FRAME_POINTER_REGNUM || !sparc_frame_pointer_required (); 12786 } 12787 12788 /* Return the hard frame pointer directly to bypass the stack bias. */ 12789 12790 static rtx 12791 sparc_builtin_setjmp_frame_value (void) 12792 { 12793 return hard_frame_pointer_rtx; 12794 } 12795 12796 /* If !TARGET_FPU, then make the fp registers and fp cc regs fixed so that 12797 they won't be allocated. */ 12798 12799 static void 12800 sparc_conditional_register_usage (void) 12801 { 12802 if (PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) 12803 { 12804 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; 12805 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; 12806 } 12807 /* If the user has passed -f{fixed,call-{used,saved}}-g5 */ 12808 /* then honor it. */ 12809 if (TARGET_ARCH32 && fixed_regs[5]) 12810 fixed_regs[5] = 1; 12811 else if (TARGET_ARCH64 && fixed_regs[5] == 2) 12812 fixed_regs[5] = 0; 12813 if (! TARGET_V9) 12814 { 12815 int regno; 12816 for (regno = SPARC_FIRST_V9_FP_REG; 12817 regno <= SPARC_LAST_V9_FP_REG; 12818 regno++) 12819 fixed_regs[regno] = 1; 12820 /* %fcc0 is used by v8 and v9. */ 12821 for (regno = SPARC_FIRST_V9_FCC_REG + 1; 12822 regno <= SPARC_LAST_V9_FCC_REG; 12823 regno++) 12824 fixed_regs[regno] = 1; 12825 } 12826 if (! TARGET_FPU) 12827 { 12828 int regno; 12829 for (regno = 32; regno < SPARC_LAST_V9_FCC_REG; regno++) 12830 fixed_regs[regno] = 1; 12831 } 12832 /* If the user has passed -f{fixed,call-{used,saved}}-g2 */ 12833 /* then honor it. Likewise with g3 and g4. */ 12834 if (fixed_regs[2] == 2) 12835 fixed_regs[2] = ! TARGET_APP_REGS; 12836 if (fixed_regs[3] == 2) 12837 fixed_regs[3] = ! TARGET_APP_REGS; 12838 if (TARGET_ARCH32 && fixed_regs[4] == 2) 12839 fixed_regs[4] = ! TARGET_APP_REGS; 12840 else if (TARGET_CM_EMBMEDANY) 12841 fixed_regs[4] = 1; 12842 else if (fixed_regs[4] == 2) 12843 fixed_regs[4] = 0; 12844 if (TARGET_FLAT) 12845 { 12846 int regno; 12847 /* Disable leaf functions. */ 12848 memset (sparc_leaf_regs, 0, FIRST_PSEUDO_REGISTER); 12849 for (regno = 0; regno < FIRST_PSEUDO_REGISTER; regno++) 12850 leaf_reg_remap [regno] = regno; 12851 } 12852 if (TARGET_VIS) 12853 global_regs[SPARC_GSR_REG] = 1; 12854 } 12855 12856 /* Implement TARGET_PREFERRED_RELOAD_CLASS: 12857 12858 - We can't load constants into FP registers. 12859 - We can't load FP constants into integer registers when soft-float, 12860 because there is no soft-float pattern with a r/F constraint. 12861 - We can't load FP constants into integer registers for TFmode unless 12862 it is 0.0L, because there is no movtf pattern with a r/F constraint. 12863 - Try and reload integer constants (symbolic or otherwise) back into 12864 registers directly, rather than having them dumped to memory. */ 12865 12866 static reg_class_t 12867 sparc_preferred_reload_class (rtx x, reg_class_t rclass) 12868 { 12869 machine_mode mode = GET_MODE (x); 12870 if (CONSTANT_P (x)) 12871 { 12872 if (FP_REG_CLASS_P (rclass) 12873 || rclass == GENERAL_OR_FP_REGS 12874 || rclass == GENERAL_OR_EXTRA_FP_REGS 12875 || (GET_MODE_CLASS (mode) == MODE_FLOAT && ! TARGET_FPU) 12876 || (mode == TFmode && ! const_zero_operand (x, mode))) 12877 return NO_REGS; 12878 12879 if (GET_MODE_CLASS (mode) == MODE_INT) 12880 return GENERAL_REGS; 12881 12882 if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) 12883 { 12884 if (! FP_REG_CLASS_P (rclass) 12885 || !(const_zero_operand (x, mode) 12886 || const_all_ones_operand (x, mode))) 12887 return NO_REGS; 12888 } 12889 } 12890 12891 if (TARGET_VIS3 12892 && ! TARGET_ARCH64 12893 && (rclass == EXTRA_FP_REGS 12894 || rclass == GENERAL_OR_EXTRA_FP_REGS)) 12895 { 12896 int regno = true_regnum (x); 12897 12898 if (SPARC_INT_REG_P (regno)) 12899 return (rclass == EXTRA_FP_REGS 12900 ? FP_REGS : GENERAL_OR_FP_REGS); 12901 } 12902 12903 return rclass; 12904 } 12905 12906 /* Return true if we use LRA instead of reload pass. */ 12907 12908 static bool 12909 sparc_lra_p (void) 12910 { 12911 return TARGET_LRA; 12912 } 12913 12914 /* Output a wide multiply instruction in V8+ mode. INSN is the instruction, 12915 OPERANDS are its operands and OPCODE is the mnemonic to be used. */ 12916 12917 const char * 12918 output_v8plus_mult (rtx_insn *insn, rtx *operands, const char *opcode) 12919 { 12920 char mulstr[32]; 12921 12922 gcc_assert (! TARGET_ARCH64); 12923 12924 if (sparc_check_64 (operands[1], insn) <= 0) 12925 output_asm_insn ("srl\t%L1, 0, %L1", operands); 12926 if (which_alternative == 1) 12927 output_asm_insn ("sllx\t%H1, 32, %H1", operands); 12928 if (GET_CODE (operands[2]) == CONST_INT) 12929 { 12930 if (which_alternative == 1) 12931 { 12932 output_asm_insn ("or\t%L1, %H1, %H1", operands); 12933 sprintf (mulstr, "%s\t%%H1, %%2, %%L0", opcode); 12934 output_asm_insn (mulstr, operands); 12935 return "srlx\t%L0, 32, %H0"; 12936 } 12937 else 12938 { 12939 output_asm_insn ("sllx\t%H1, 32, %3", operands); 12940 output_asm_insn ("or\t%L1, %3, %3", operands); 12941 sprintf (mulstr, "%s\t%%3, %%2, %%3", opcode); 12942 output_asm_insn (mulstr, operands); 12943 output_asm_insn ("srlx\t%3, 32, %H0", operands); 12944 return "mov\t%3, %L0"; 12945 } 12946 } 12947 else if (rtx_equal_p (operands[1], operands[2])) 12948 { 12949 if (which_alternative == 1) 12950 { 12951 output_asm_insn ("or\t%L1, %H1, %H1", operands); 12952 sprintf (mulstr, "%s\t%%H1, %%H1, %%L0", opcode); 12953 output_asm_insn (mulstr, operands); 12954 return "srlx\t%L0, 32, %H0"; 12955 } 12956 else 12957 { 12958 output_asm_insn ("sllx\t%H1, 32, %3", operands); 12959 output_asm_insn ("or\t%L1, %3, %3", operands); 12960 sprintf (mulstr, "%s\t%%3, %%3, %%3", opcode); 12961 output_asm_insn (mulstr, operands); 12962 output_asm_insn ("srlx\t%3, 32, %H0", operands); 12963 return "mov\t%3, %L0"; 12964 } 12965 } 12966 if (sparc_check_64 (operands[2], insn) <= 0) 12967 output_asm_insn ("srl\t%L2, 0, %L2", operands); 12968 if (which_alternative == 1) 12969 { 12970 output_asm_insn ("or\t%L1, %H1, %H1", operands); 12971 output_asm_insn ("sllx\t%H2, 32, %L1", operands); 12972 output_asm_insn ("or\t%L2, %L1, %L1", operands); 12973 sprintf (mulstr, "%s\t%%H1, %%L1, %%L0", opcode); 12974 output_asm_insn (mulstr, operands); 12975 return "srlx\t%L0, 32, %H0"; 12976 } 12977 else 12978 { 12979 output_asm_insn ("sllx\t%H1, 32, %3", operands); 12980 output_asm_insn ("sllx\t%H2, 32, %4", operands); 12981 output_asm_insn ("or\t%L1, %3, %3", operands); 12982 output_asm_insn ("or\t%L2, %4, %4", operands); 12983 sprintf (mulstr, "%s\t%%3, %%4, %%3", opcode); 12984 output_asm_insn (mulstr, operands); 12985 output_asm_insn ("srlx\t%3, 32, %H0", operands); 12986 return "mov\t%3, %L0"; 12987 } 12988 } 12989 12990 /* Subroutine of sparc_expand_vector_init. Emit code to initialize 12991 all fields of TARGET to ELT by means of VIS2 BSHUFFLE insn. MODE 12992 and INNER_MODE are the modes describing TARGET. */ 12993 12994 static void 12995 vector_init_bshuffle (rtx target, rtx elt, machine_mode mode, 12996 machine_mode inner_mode) 12997 { 12998 rtx t1, final_insn, sel; 12999 int bmask; 13000 13001 t1 = gen_reg_rtx (mode); 13002 13003 elt = convert_modes (SImode, inner_mode, elt, true); 13004 emit_move_insn (gen_lowpart(SImode, t1), elt); 13005 13006 switch (mode) 13007 { 13008 case V2SImode: 13009 final_insn = gen_bshufflev2si_vis (target, t1, t1); 13010 bmask = 0x45674567; 13011 break; 13012 case V4HImode: 13013 final_insn = gen_bshufflev4hi_vis (target, t1, t1); 13014 bmask = 0x67676767; 13015 break; 13016 case V8QImode: 13017 final_insn = gen_bshufflev8qi_vis (target, t1, t1); 13018 bmask = 0x77777777; 13019 break; 13020 default: 13021 gcc_unreachable (); 13022 } 13023 13024 sel = force_reg (SImode, GEN_INT (bmask)); 13025 emit_insn (gen_bmasksi_vis (gen_reg_rtx (SImode), sel, const0_rtx)); 13026 emit_insn (final_insn); 13027 } 13028 13029 /* Subroutine of sparc_expand_vector_init. Emit code to initialize 13030 all fields of TARGET to ELT in V8QI by means of VIS FPMERGE insn. */ 13031 13032 static void 13033 vector_init_fpmerge (rtx target, rtx elt) 13034 { 13035 rtx t1, t2, t2_low, t3, t3_low; 13036 13037 t1 = gen_reg_rtx (V4QImode); 13038 elt = convert_modes (SImode, QImode, elt, true); 13039 emit_move_insn (gen_lowpart (SImode, t1), elt); 13040 13041 t2 = gen_reg_rtx (V8QImode); 13042 t2_low = gen_lowpart (V4QImode, t2); 13043 emit_insn (gen_fpmerge_vis (t2, t1, t1)); 13044 13045 t3 = gen_reg_rtx (V8QImode); 13046 t3_low = gen_lowpart (V4QImode, t3); 13047 emit_insn (gen_fpmerge_vis (t3, t2_low, t2_low)); 13048 13049 emit_insn (gen_fpmerge_vis (target, t3_low, t3_low)); 13050 } 13051 13052 /* Subroutine of sparc_expand_vector_init. Emit code to initialize 13053 all fields of TARGET to ELT in V4HI by means of VIS FALIGNDATA insn. */ 13054 13055 static void 13056 vector_init_faligndata (rtx target, rtx elt) 13057 { 13058 rtx t1 = gen_reg_rtx (V4HImode); 13059 int i; 13060 13061 elt = convert_modes (SImode, HImode, elt, true); 13062 emit_move_insn (gen_lowpart (SImode, t1), elt); 13063 13064 emit_insn (gen_alignaddrsi_vis (gen_reg_rtx (SImode), 13065 force_reg (SImode, GEN_INT (6)), 13066 const0_rtx)); 13067 13068 for (i = 0; i < 4; i++) 13069 emit_insn (gen_faligndatav4hi_vis (target, t1, target)); 13070 } 13071 13072 /* Emit code to initialize TARGET to values for individual fields VALS. */ 13073 13074 void 13075 sparc_expand_vector_init (rtx target, rtx vals) 13076 { 13077 const machine_mode mode = GET_MODE (target); 13078 const machine_mode inner_mode = GET_MODE_INNER (mode); 13079 const int n_elts = GET_MODE_NUNITS (mode); 13080 int i, n_var = 0; 13081 bool all_same = true; 13082 rtx mem; 13083 13084 for (i = 0; i < n_elts; i++) 13085 { 13086 rtx x = XVECEXP (vals, 0, i); 13087 if (!(CONST_SCALAR_INT_P (x) || CONST_DOUBLE_P (x) || CONST_FIXED_P (x))) 13088 n_var++; 13089 13090 if (i > 0 && !rtx_equal_p (x, XVECEXP (vals, 0, 0))) 13091 all_same = false; 13092 } 13093 13094 if (n_var == 0) 13095 { 13096 emit_move_insn (target, gen_rtx_CONST_VECTOR (mode, XVEC (vals, 0))); 13097 return; 13098 } 13099 13100 if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (mode)) 13101 { 13102 if (GET_MODE_SIZE (inner_mode) == 4) 13103 { 13104 emit_move_insn (gen_lowpart (SImode, target), 13105 gen_lowpart (SImode, XVECEXP (vals, 0, 0))); 13106 return; 13107 } 13108 else if (GET_MODE_SIZE (inner_mode) == 8) 13109 { 13110 emit_move_insn (gen_lowpart (DImode, target), 13111 gen_lowpart (DImode, XVECEXP (vals, 0, 0))); 13112 return; 13113 } 13114 } 13115 else if (GET_MODE_SIZE (inner_mode) == GET_MODE_SIZE (word_mode) 13116 && GET_MODE_SIZE (mode) == 2 * GET_MODE_SIZE (word_mode)) 13117 { 13118 emit_move_insn (gen_highpart (word_mode, target), 13119 gen_lowpart (word_mode, XVECEXP (vals, 0, 0))); 13120 emit_move_insn (gen_lowpart (word_mode, target), 13121 gen_lowpart (word_mode, XVECEXP (vals, 0, 1))); 13122 return; 13123 } 13124 13125 if (all_same && GET_MODE_SIZE (mode) == 8) 13126 { 13127 if (TARGET_VIS2) 13128 { 13129 vector_init_bshuffle (target, XVECEXP (vals, 0, 0), mode, inner_mode); 13130 return; 13131 } 13132 if (mode == V8QImode) 13133 { 13134 vector_init_fpmerge (target, XVECEXP (vals, 0, 0)); 13135 return; 13136 } 13137 if (mode == V4HImode) 13138 { 13139 vector_init_faligndata (target, XVECEXP (vals, 0, 0)); 13140 return; 13141 } 13142 } 13143 13144 mem = assign_stack_temp (mode, GET_MODE_SIZE (mode)); 13145 for (i = 0; i < n_elts; i++) 13146 emit_move_insn (adjust_address_nv (mem, inner_mode, 13147 i * GET_MODE_SIZE (inner_mode)), 13148 XVECEXP (vals, 0, i)); 13149 emit_move_insn (target, mem); 13150 } 13151 13152 /* Implement TARGET_SECONDARY_RELOAD. */ 13153 13154 static reg_class_t 13155 sparc_secondary_reload (bool in_p, rtx x, reg_class_t rclass_i, 13156 machine_mode mode, secondary_reload_info *sri) 13157 { 13158 enum reg_class rclass = (enum reg_class) rclass_i; 13159 13160 sri->icode = CODE_FOR_nothing; 13161 sri->extra_cost = 0; 13162 13163 /* We need a temporary when loading/storing a HImode/QImode value 13164 between memory and the FPU registers. This can happen when combine puts 13165 a paradoxical subreg in a float/fix conversion insn. */ 13166 if (FP_REG_CLASS_P (rclass) 13167 && (mode == HImode || mode == QImode) 13168 && (GET_CODE (x) == MEM 13169 || ((GET_CODE (x) == REG || GET_CODE (x) == SUBREG) 13170 && true_regnum (x) == -1))) 13171 return GENERAL_REGS; 13172 13173 /* On 32-bit we need a temporary when loading/storing a DFmode value 13174 between unaligned memory and the upper FPU registers. */ 13175 if (TARGET_ARCH32 13176 && rclass == EXTRA_FP_REGS 13177 && mode == DFmode 13178 && GET_CODE (x) == MEM 13179 && ! mem_min_alignment (x, 8)) 13180 return FP_REGS; 13181 13182 if (((TARGET_CM_MEDANY 13183 && symbolic_operand (x, mode)) 13184 || (TARGET_CM_EMBMEDANY 13185 && text_segment_operand (x, mode))) 13186 && ! flag_pic) 13187 { 13188 if (in_p) 13189 sri->icode = direct_optab_handler (reload_in_optab, mode); 13190 else 13191 sri->icode = direct_optab_handler (reload_out_optab, mode); 13192 return NO_REGS; 13193 } 13194 13195 if (TARGET_VIS3 && TARGET_ARCH32) 13196 { 13197 int regno = true_regnum (x); 13198 13199 /* When using VIS3 fp<-->int register moves, on 32-bit we have 13200 to move 8-byte values in 4-byte pieces. This only works via 13201 FP_REGS, and not via EXTRA_FP_REGS. Therefore if we try to 13202 move between EXTRA_FP_REGS and GENERAL_REGS, we will need 13203 an FP_REGS intermediate move. */ 13204 if ((rclass == EXTRA_FP_REGS && SPARC_INT_REG_P (regno)) 13205 || ((general_or_i64_p (rclass) 13206 || rclass == GENERAL_OR_FP_REGS) 13207 && SPARC_FP_REG_P (regno))) 13208 { 13209 sri->extra_cost = 2; 13210 return FP_REGS; 13211 } 13212 } 13213 13214 return NO_REGS; 13215 } 13216 13217 /* Emit code to conditionally move either OPERANDS[2] or OPERANDS[3] into 13218 OPERANDS[0] in MODE. OPERANDS[1] is the operator of the condition. */ 13219 13220 bool 13221 sparc_expand_conditional_move (machine_mode mode, rtx *operands) 13222 { 13223 enum rtx_code rc = GET_CODE (operands[1]); 13224 machine_mode cmp_mode; 13225 rtx cc_reg, dst, cmp; 13226 13227 cmp = operands[1]; 13228 if (GET_MODE (XEXP (cmp, 0)) == DImode && !TARGET_ARCH64) 13229 return false; 13230 13231 if (GET_MODE (XEXP (cmp, 0)) == TFmode && !TARGET_HARD_QUAD) 13232 cmp = sparc_emit_float_lib_cmp (XEXP (cmp, 0), XEXP (cmp, 1), rc); 13233 13234 cmp_mode = GET_MODE (XEXP (cmp, 0)); 13235 rc = GET_CODE (cmp); 13236 13237 dst = operands[0]; 13238 if (! rtx_equal_p (operands[2], dst) 13239 && ! rtx_equal_p (operands[3], dst)) 13240 { 13241 if (reg_overlap_mentioned_p (dst, cmp)) 13242 dst = gen_reg_rtx (mode); 13243 13244 emit_move_insn (dst, operands[3]); 13245 } 13246 else if (operands[2] == dst) 13247 { 13248 operands[2] = operands[3]; 13249 13250 if (GET_MODE_CLASS (cmp_mode) == MODE_FLOAT) 13251 rc = reverse_condition_maybe_unordered (rc); 13252 else 13253 rc = reverse_condition (rc); 13254 } 13255 13256 if (XEXP (cmp, 1) == const0_rtx 13257 && GET_CODE (XEXP (cmp, 0)) == REG 13258 && cmp_mode == DImode 13259 && v9_regcmp_p (rc)) 13260 cc_reg = XEXP (cmp, 0); 13261 else 13262 cc_reg = gen_compare_reg_1 (rc, XEXP (cmp, 0), XEXP (cmp, 1)); 13263 13264 cmp = gen_rtx_fmt_ee (rc, GET_MODE (cc_reg), cc_reg, const0_rtx); 13265 13266 emit_insn (gen_rtx_SET (dst, 13267 gen_rtx_IF_THEN_ELSE (mode, cmp, operands[2], dst))); 13268 13269 if (dst != operands[0]) 13270 emit_move_insn (operands[0], dst); 13271 13272 return true; 13273 } 13274 13275 /* Emit code to conditionally move a combination of OPERANDS[1] and OPERANDS[2] 13276 into OPERANDS[0] in MODE, depending on the outcome of the comparison of 13277 OPERANDS[4] and OPERANDS[5]. OPERANDS[3] is the operator of the condition. 13278 FCODE is the machine code to be used for OPERANDS[3] and CCODE the machine 13279 code to be used for the condition mask. */ 13280 13281 void 13282 sparc_expand_vcond (machine_mode mode, rtx *operands, int ccode, int fcode) 13283 { 13284 rtx mask, cop0, cop1, fcmp, cmask, bshuf, gsr; 13285 enum rtx_code code = GET_CODE (operands[3]); 13286 13287 mask = gen_reg_rtx (Pmode); 13288 cop0 = operands[4]; 13289 cop1 = operands[5]; 13290 if (code == LT || code == GE) 13291 { 13292 rtx t; 13293 13294 code = swap_condition (code); 13295 t = cop0; cop0 = cop1; cop1 = t; 13296 } 13297 13298 gsr = gen_rtx_REG (DImode, SPARC_GSR_REG); 13299 13300 fcmp = gen_rtx_UNSPEC (Pmode, 13301 gen_rtvec (1, gen_rtx_fmt_ee (code, mode, cop0, cop1)), 13302 fcode); 13303 13304 cmask = gen_rtx_UNSPEC (DImode, 13305 gen_rtvec (2, mask, gsr), 13306 ccode); 13307 13308 bshuf = gen_rtx_UNSPEC (mode, 13309 gen_rtvec (3, operands[1], operands[2], gsr), 13310 UNSPEC_BSHUFFLE); 13311 13312 emit_insn (gen_rtx_SET (mask, fcmp)); 13313 emit_insn (gen_rtx_SET (gsr, cmask)); 13314 13315 emit_insn (gen_rtx_SET (operands[0], bshuf)); 13316 } 13317 13318 /* On sparc, any mode which naturally allocates into the float 13319 registers should return 4 here. */ 13320 13321 unsigned int 13322 sparc_regmode_natural_size (machine_mode mode) 13323 { 13324 int size = UNITS_PER_WORD; 13325 13326 if (TARGET_ARCH64) 13327 { 13328 enum mode_class mclass = GET_MODE_CLASS (mode); 13329 13330 if (mclass == MODE_FLOAT || mclass == MODE_VECTOR_INT) 13331 size = 4; 13332 } 13333 13334 return size; 13335 } 13336 13337 /* Return TRUE if it is a good idea to tie two pseudo registers 13338 when one has mode MODE1 and one has mode MODE2. 13339 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 13340 for any hard reg, then this must be FALSE for correct output. 13341 13342 For V9 we have to deal with the fact that only the lower 32 floating 13343 point registers are 32-bit addressable. */ 13344 13345 bool 13346 sparc_modes_tieable_p (machine_mode mode1, machine_mode mode2) 13347 { 13348 enum mode_class mclass1, mclass2; 13349 unsigned short size1, size2; 13350 13351 if (mode1 == mode2) 13352 return true; 13353 13354 mclass1 = GET_MODE_CLASS (mode1); 13355 mclass2 = GET_MODE_CLASS (mode2); 13356 if (mclass1 != mclass2) 13357 return false; 13358 13359 if (! TARGET_V9) 13360 return true; 13361 13362 /* Classes are the same and we are V9 so we have to deal with upper 13363 vs. lower floating point registers. If one of the modes is a 13364 4-byte mode, and the other is not, we have to mark them as not 13365 tieable because only the lower 32 floating point register are 13366 addressable 32-bits at a time. 13367 13368 We can't just test explicitly for SFmode, otherwise we won't 13369 cover the vector mode cases properly. */ 13370 13371 if (mclass1 != MODE_FLOAT && mclass1 != MODE_VECTOR_INT) 13372 return true; 13373 13374 size1 = GET_MODE_SIZE (mode1); 13375 size2 = GET_MODE_SIZE (mode2); 13376 if ((size1 > 4 && size2 == 4) 13377 || (size2 > 4 && size1 == 4)) 13378 return false; 13379 13380 return true; 13381 } 13382 13383 /* Implement TARGET_CSTORE_MODE. */ 13384 13385 static machine_mode 13386 sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED) 13387 { 13388 return (TARGET_ARCH64 ? DImode : SImode); 13389 } 13390 13391 /* Return the compound expression made of T1 and T2. */ 13392 13393 static inline tree 13394 compound_expr (tree t1, tree t2) 13395 { 13396 return build2 (COMPOUND_EXPR, void_type_node, t1, t2); 13397 } 13398 13399 /* Implement TARGET_ATOMIC_ASSIGN_EXPAND_FENV hook. */ 13400 13401 static void 13402 sparc_atomic_assign_expand_fenv (tree *hold, tree *clear, tree *update) 13403 { 13404 if (!TARGET_FPU) 13405 return; 13406 13407 const unsigned HOST_WIDE_INT accrued_exception_mask = 0x1f << 5; 13408 const unsigned HOST_WIDE_INT trap_enable_mask = 0x1f << 23; 13409 13410 /* We generate the equivalent of feholdexcept (&fenv_var): 13411 13412 unsigned int fenv_var; 13413 __builtin_store_fsr (&fenv_var); 13414 13415 unsigned int tmp1_var; 13416 tmp1_var = fenv_var & ~(accrued_exception_mask | trap_enable_mask); 13417 13418 __builtin_load_fsr (&tmp1_var); */ 13419 13420 tree fenv_var = create_tmp_var_raw (unsigned_type_node); 13421 TREE_ADDRESSABLE (fenv_var) = 1; 13422 tree fenv_addr = build_fold_addr_expr (fenv_var); 13423 tree stfsr = sparc_builtins[SPARC_BUILTIN_STFSR]; 13424 tree hold_stfsr 13425 = build4 (TARGET_EXPR, unsigned_type_node, fenv_var, 13426 build_call_expr (stfsr, 1, fenv_addr), NULL_TREE, NULL_TREE); 13427 13428 tree tmp1_var = create_tmp_var_raw (unsigned_type_node); 13429 TREE_ADDRESSABLE (tmp1_var) = 1; 13430 tree masked_fenv_var 13431 = build2 (BIT_AND_EXPR, unsigned_type_node, fenv_var, 13432 build_int_cst (unsigned_type_node, 13433 ~(accrued_exception_mask | trap_enable_mask))); 13434 tree hold_mask 13435 = build4 (TARGET_EXPR, unsigned_type_node, tmp1_var, masked_fenv_var, 13436 NULL_TREE, NULL_TREE); 13437 13438 tree tmp1_addr = build_fold_addr_expr (tmp1_var); 13439 tree ldfsr = sparc_builtins[SPARC_BUILTIN_LDFSR]; 13440 tree hold_ldfsr = build_call_expr (ldfsr, 1, tmp1_addr); 13441 13442 *hold = compound_expr (compound_expr (hold_stfsr, hold_mask), hold_ldfsr); 13443 13444 /* We reload the value of tmp1_var to clear the exceptions: 13445 13446 __builtin_load_fsr (&tmp1_var); */ 13447 13448 *clear = build_call_expr (ldfsr, 1, tmp1_addr); 13449 13450 /* We generate the equivalent of feupdateenv (&fenv_var): 13451 13452 unsigned int tmp2_var; 13453 __builtin_store_fsr (&tmp2_var); 13454 13455 __builtin_load_fsr (&fenv_var); 13456 13457 if (SPARC_LOW_FE_EXCEPT_VALUES) 13458 tmp2_var >>= 5; 13459 __atomic_feraiseexcept ((int) tmp2_var); */ 13460 13461 tree tmp2_var = create_tmp_var_raw (unsigned_type_node); 13462 TREE_ADDRESSABLE (tmp2_var) = 1; 13463 tree tmp2_addr = build_fold_addr_expr (tmp2_var); 13464 tree update_stfsr 13465 = build4 (TARGET_EXPR, unsigned_type_node, tmp2_var, 13466 build_call_expr (stfsr, 1, tmp2_addr), NULL_TREE, NULL_TREE); 13467 13468 tree update_ldfsr = build_call_expr (ldfsr, 1, fenv_addr); 13469 13470 tree atomic_feraiseexcept 13471 = builtin_decl_implicit (BUILT_IN_ATOMIC_FERAISEEXCEPT); 13472 tree update_call 13473 = build_call_expr (atomic_feraiseexcept, 1, 13474 fold_convert (integer_type_node, tmp2_var)); 13475 13476 if (SPARC_LOW_FE_EXCEPT_VALUES) 13477 { 13478 tree shifted_tmp2_var 13479 = build2 (RSHIFT_EXPR, unsigned_type_node, tmp2_var, 13480 build_int_cst (unsigned_type_node, 5)); 13481 tree update_shift 13482 = build2 (MODIFY_EXPR, void_type_node, tmp2_var, shifted_tmp2_var); 13483 update_call = compound_expr (update_shift, update_call); 13484 } 13485 13486 *update 13487 = compound_expr (compound_expr (update_stfsr, update_ldfsr), update_call); 13488 } 13489 13490 #include "gt-sparc.h" 13491