1;; Scheduling description for Renesas SH4a 2;; Copyright (C) 2003-2019 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GNU CC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GNU CC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; The following description models the SH4A pipeline 21;; using the DFA based scheduler. 22(define_automaton "sh4a") 23 24(define_cpu_unit "sh4a_ex" "sh4a") 25(define_cpu_unit "sh4a_ls" "sh4a") 26(define_cpu_unit "sh4a_fex" "sh4a") 27(define_cpu_unit "sh4a_fls" "sh4a") 28(define_cpu_unit "sh4a_mult" "sh4a") 29(define_cpu_unit "sh4a_fdiv" "sh4a") 30 31;; Decoding is done on the integer pipeline like the 32;; sh4. Define issue to be the | of the two pipelines 33;; to control how often instructions are issued. 34(define_reservation "ID_or" "sh4a_ex|sh4a_ls") 35(define_reservation "ID_and" "sh4a_ex+sh4a_ls") 36 37;; ======================================================= 38;; Locking Descriptions 39 40;; Sh4a_Memory access on the LS pipeline. 41(define_cpu_unit "sh4a_memory" "sh4a") 42 43;; Other access on the LS pipeline. 44(define_cpu_unit "sh4a_load_store" "sh4a") 45 46;; The address calculator used for branch instructions. 47;; This will be reserved after "issue" of branch instructions 48;; and this is to make sure that no two branch instructions 49;; can be issued in parallel. 50(define_reservation "sh4a_addrcalc" "sh4a_ex") 51 52;; ======================================================= 53;; Reservations 54 55;; Branch (BF,BF/S,BT,BT/S,BRA,BSR) 56;; Group: BR 57;; Latency when taken: 2 58(define_insn_reservation "sh4a_branch" 2 59 (and (eq_attr "cpu" "sh4a") 60 (eq_attr "type" "cbranch,jump")) 61 "ID_or+sh4a_addrcalc") 62 63;; Jump (JSR,JMP,RTS) 64;; Group: BR 65;; Latency: 3 66(define_insn_reservation "sh4a_jump" 3 67 (and (eq_attr "cpu" "sh4a") 68 (eq_attr "type" "return,jump_ind")) 69 "ID_or+sh4a_addrcalc") 70 71;; RTE 72;; Group: CO 73;; Latency: 3 74(define_insn_reservation "sh4a_rte" 3 75 (and (eq_attr "cpu" "sh4a") 76 (eq_attr "type" "rte")) 77 "ID_and*4") 78 79;; EX Group Single 80;; Group: EX 81;; Latency: 0 82(define_insn_reservation "sh4a_ex" 0 83 (and (eq_attr "cpu" "sh4a") 84 (eq_attr "insn_class" "ex_group")) 85 "sh4a_ex") 86 87;; MOVA 88;; Group: LS 89;; Latency: 1 90(define_insn_reservation "sh4a_mova" 1 91 (and (eq_attr "cpu" "sh4a") 92 (eq_attr "type" "mova")) 93 "sh4a_ls+sh4a_load_store") 94 95;; MOV 96;; Group: MT 97;; Latency: 0 98;; ??? not sure if movi8 belongs here, but that's where it was 99;; effectively before. 100(define_insn_reservation "sh4a_mov" 0 101 (and (eq_attr "cpu" "sh4a") 102 (eq_attr "type" "move,movi8,gp_mac")) 103 "ID_or") 104 105;; Load 106;; Group: LS 107;; Latency: 3 108(define_insn_reservation "sh4a_load" 3 109 (and (eq_attr "cpu" "sh4a") 110 (eq_attr "type" "load,pcload,mem_mac")) 111 "sh4a_ls+sh4a_memory") 112 113(define_insn_reservation "sh4a_load_si" 3 114 (and (eq_attr "cpu" "sh4a") 115 (eq_attr "type" "load_si,pcload_si")) 116 "sh4a_ls+sh4a_memory") 117 118;; Store 119;; Group: LS 120;; Latency: 0 121(define_insn_reservation "sh4a_store" 0 122 (and (eq_attr "cpu" "sh4a") 123 (eq_attr "type" "store,fstore,mac_mem")) 124 "sh4a_ls+sh4a_memory") 125 126;; CWB TYPE 127 128;; MOVUA 129;; Group: LS 130;; Latency: 3 131(define_insn_reservation "sh4a_movua" 3 132 (and (eq_attr "cpu" "sh4a") 133 (eq_attr "type" "movua")) 134 "sh4a_ls+sh4a_memory*2") 135 136;; Fixed point multiplication (single) 137;; Group: CO 138;; Latency: 2 139(define_insn_reservation "sh4a_smult" 2 140 (and (eq_attr "cpu" "sh4a") 141 (eq_attr "type" "smpy")) 142 "ID_or+sh4a_mult") 143 144;; Fixed point multiplication (double) 145;; Group: CO 146;; Latency: 3 147(define_insn_reservation "sh4a_dmult" 3 148 (and (eq_attr "cpu" "sh4a") 149 (eq_attr "type" "dmpy")) 150 "ID_or+sh4a_mult") 151 152(define_insn_reservation "sh4a_mac_gp" 3 153 (and (eq_attr "cpu" "sh4a") 154 (eq_attr "type" "mac_gp")) 155 "ID_and") 156 157;; Other MT group instructions(1 step operations) 158;; Group: MT 159;; Latency: 1 160(define_insn_reservation "sh4a_mt" 1 161 (and (eq_attr "cpu" "sh4a") 162 (eq_attr "type" "mt_group")) 163 "ID_or") 164 165;; Floating point reg move 166;; Group: LS 167;; Latency: 2 168(define_insn_reservation "sh4a_freg_mov" 2 169 (and (eq_attr "cpu" "sh4a") 170 (eq_attr "type" "fmove")) 171 "sh4a_ls,sh4a_fls") 172 173;; Single precision floating point computation FCMP/EQ, 174;; FCMP/GT, FADD, FLOAT, FMAC, FMUL, FSUB, FTRC, FRVHG, FSCHG 175;; Group: FE 176;; Latency: 3 177(define_insn_reservation "sh4a_fp_arith" 3 178 (and (eq_attr "cpu" "sh4a") 179 (eq_attr "type" "fp,fp_cmp,fpscr_toggle")) 180 "ID_or,sh4a_fex") 181 182(define_insn_reservation "sh4a_fp_arith_ftrc" 3 183 (and (eq_attr "cpu" "sh4a") 184 (eq_attr "type" "ftrc_s")) 185 "ID_or,sh4a_fex") 186 187;; Single-precision FDIV/FSQRT 188;; Group: FE 189;; Latency: 20 190(define_insn_reservation "sh4a_fdiv" 20 191 (and (eq_attr "cpu" "sh4a") 192 (eq_attr "type" "fdiv")) 193 "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex") 194 195;; Double Precision floating point computation 196;; (FCNVDS, FCNVSD, FLOAT, FTRC) 197;; Group: FE 198;; Latency: 3 199(define_insn_reservation "sh4a_dp_float" 3 200 (and (eq_attr "cpu" "sh4a") 201 (eq_attr "type" "dfp_conv")) 202 "ID_or,sh4a_fex") 203 204;; Double-precision floating-point (FADD,FMUL,FSUB) 205;; Group: FE 206;; Latency: 5 207(define_insn_reservation "sh4a_fp_double_arith" 5 208 (and (eq_attr "cpu" "sh4a") 209 (eq_attr "type" "dfp_arith,dfp_mul")) 210 "ID_or,sh4a_fex*3") 211 212;; Double precision FDIV/SQRT 213;; Group: FE 214;; Latency: 36 215(define_insn_reservation "sh4a_dp_div" 36 216 (and (eq_attr "cpu" "sh4a") 217 (eq_attr "type" "dfdiv")) 218 "ID_or,sh4a_fex+sh4a_fdiv,sh4a_fex*2") 219 220;; FSRRA 221;; Group: FE 222;; Latency: 5 223(define_insn_reservation "sh4a_fsrra" 5 224 (and (eq_attr "cpu" "sh4a") 225 (eq_attr "type" "fsrra")) 226 "ID_or,sh4a_fex") 227 228;; FSCA 229;; Group: FE 230;; Latency: 7 231(define_insn_reservation "sh4a_fsca" 7 232 (and (eq_attr "cpu" "sh4a") 233 (eq_attr "type" "fsca")) 234 "ID_or,sh4a_fex*3") 235