1;; Constraint definitions for Renesas / SuperH SH. 2;; Copyright (C) 2007-2015 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Overview of uppercase letter constraints: 21;; Axx: atomic memory operand constraints 22;; Ara: Same as Sra but disallows r15 23;; Add: Same as Sdd but disallows r15 24;; Bxx: miscellaneous constraints 25;; Bsc: SCRATCH - for the scratch register in movsi_ie in the 26;; fldi0 / fldi0 cases 27;; Cxx: Constants other than only CONST_INT 28;; Css: signed 16-bit constant, literal or symbolic 29;; Csu: unsigned 16-bit constant, literal or symbolic 30;; Csy: label or symbol 31;; Cpg: non-explicit constants that can be directly loaded into a general 32;; purpose register in PIC code. Like 's' except we don't allow 33;; PIC_ADDR_P 34;; IJKLMNOP: CONT_INT constants 35;; Ixx: signed xx bit 36;; J16: 0xffffffff00000000 | 0x00000000ffffffff 37;; Jmb: 0x000000FF 38;; Jmw: 0x0000FFFF 39;; Jhb: 0x80000000 40;; Kxx: unsigned xx bit 41;; M: 1 42;; N: 0 43;; P27: 1 | 2 | 8 | 16 44;; Pso: 1 | 2 | 4 | 8 | 16 | 32 | 64 | 128 45;; Psz: ~1 | ~2 | ~4 | ~8 | ~16 | ~32 | ~64 | ~128 46;; G: Floating point 0 47;; H: Floating point 1 48;; Q: pc relative load operand 49;; Rxx: reserved for exotic register classes. 50;; Sxx: extra memory constraints 51;; Sua: unaligned memory address 52;; Sbv: QImode address without displacement 53;; Sbw: QImode address with 12 bit displacement 54;; Snd: address without displacement 55;; Sdd: address with displacement 56;; Sra: simple register address 57;; W: vector 58;; Z: zero in any mode 59;; 60;; unused CONST_INT constraint letters: LO 61;; unused "extra" constraint letters: D T U Y 62 63;; Register constraints 64(define_register_constraint "a" "ALL_REGS" 65 "@internal") 66 67(define_register_constraint "b" "TARGET_REGS" 68 "Branch target registers.") 69 70(define_register_constraint "c" "FPSCR_REGS" 71 "Floating-point status register.") 72 73(define_register_constraint "d" "DF_REGS" 74 "Double precision floating-point register.") 75 76(define_register_constraint "e" "TARGET_FMOVD ? NO_REGS : FP_REGS" 77 "Floating-point register.") 78 79(define_register_constraint "f" "FP_REGS" 80 "Floating-point register.") 81 82(define_register_constraint "k" "SIBCALL_REGS" 83 "@internal") 84 85(define_register_constraint "l" "PR_REGS" 86 "PR register.") 87 88(define_register_constraint "t" "T_REGS" 89 "T register.") 90 91(define_register_constraint "u" "NON_SP_REGS" 92 "Non-stack-pointer register.") 93 94(define_register_constraint "w" "FP0_REGS" 95 "Floating-point register 0.") 96 97(define_register_constraint "x" "MAC_REGS" 98 "MACH and MACL registers.") 99 100(define_register_constraint "y" "FPUL_REGS" 101 "FPUL register.") 102 103(define_register_constraint "z" "R0_REGS" 104 "R0 register.") 105 106;; Integer constraints 107(define_constraint "I06" 108 "A signed 6-bit constant, as used in SHmedia beqi, bnei and xori." 109 (and (match_code "const_int") 110 (match_test "ival >= -32 && ival <= 31"))) 111 112(define_constraint "I08" 113 "A signed 8-bit constant, as used in add, sub, etc." 114 (and (match_code "const_int") 115 (match_test "ival >= -128 && ival <= 127"))) 116 117(define_constraint "I10" 118 "A signed 10-bit constant, as used in SHmedia andi, ori." 119 (and (match_code "const_int") 120 (match_test "ival >= -512 && ival <= 511"))) 121 122(define_constraint "I16" 123 "A signed 16-bit constant, as used in SHmedia movi." 124 (and (match_code "const_int") 125 (match_test "ival >= -32768 && ival <= 32767"))) 126 127(define_constraint "I20" 128 "A signed 20-bit constant, as used in SH2A movi20." 129 (and (match_code "const_int") 130 (match_test "ival >= -524288 && ival <= 524287") 131 (match_test "TARGET_SH2A"))) 132 133(define_constraint "I28" 134 "A signed 28-bit constant, as used in SH2A movi20s." 135 (and (match_code "const_int") 136 (match_test "ival >= -134217728 && ival <= 134217727") 137 (match_test "(ival & 255) == 0") 138 (match_test "TARGET_SH2A"))) 139 140(define_constraint "J16" 141 "0xffffffff00000000 or 0x00000000ffffffff." 142 (and (match_code "const_int") 143 (match_test "CONST_OK_FOR_J16 (ival)"))) 144 145(define_constraint "Jmb" 146 "Low byte mask constant 0x000000FF" 147 (and (match_code "const_int") 148 (match_test "ival == 0xFF"))) 149 150(define_constraint "Jmw" 151 "Low word mask constant 0x0000FFFF" 152 (and (match_code "const_int") 153 (match_test "ival == 0xFFFF"))) 154 155(define_constraint "Jhb" 156 "Highest bit constant" 157 (and (match_code "const_int") 158 (match_test "(ival & 0xFFFFFFFF) == 0x80000000"))) 159 160(define_constraint "K03" 161 "An unsigned 3-bit constant, as used in SH2A bclr, bset, etc." 162 (and (match_code "const_int") 163 (match_test "ival >= 0 && ival <= 7"))) 164 165(define_constraint "K04" 166 "An unsigned 4-bit constant, as used in mov.b displacement addressing." 167 (and (match_code "const_int") 168 (match_test "ival >= 0 && ival <= 15"))) 169 170(define_constraint "K05" 171 "An unsigned 5-bit constant, as used in mov.w displacement addressing." 172 (and (match_code "const_int") 173 (match_test "ival >= 0 && ival <= 31"))) 174 175(define_constraint "K08" 176 "An unsigned 8-bit constant, as used in and, or, etc." 177 (and (match_code "const_int") 178 (match_test "ival >= 0 && ival <= 255"))) 179 180(define_constraint "K12" 181 "An unsigned 12-bit constant, as used in SH2A 12-bit mov.b displacement 182 addressing." 183 (and (match_code "const_int") 184 (match_test "ival >= 0 && ival <= 4095"))) 185 186(define_constraint "K13" 187 "An unsigned 13-bit constant, as used in SH2A 12-bit mov.w displacement 188 addressing." 189 (and (match_code "const_int") 190 (match_test "ival >= 0 && ival <= 8191"))) 191 192(define_constraint "K16" 193 "An unsigned 16-bit constant, as used in SHmedia shori." 194 (and (match_code "const_int") 195 (match_test "ival >= 0 && ival <= 65535"))) 196 197(define_constraint "P27" 198 "A constant for shift operand 1,2,8 or 16." 199 (and (match_code "const_int") 200 (match_test "ival == 1 || ival == 2 || ival == 8 || ival == 16"))) 201 202(define_constraint "M" 203 "Integer constant 1." 204 (and (match_code "const_int") 205 (match_test "ival == 1"))) 206 207(define_constraint "N" 208 "Integer constant 0." 209 (and (match_code "const_int") 210 (match_test "ival == 0"))) 211 212;; Floating-point constraints 213(define_constraint "G" 214 "Double constant 0." 215 (and (match_code "const_double") 216 (match_test "fp_zero_operand (op)"))) 217 218(define_constraint "H" 219 "Double constant 1." 220 (and (match_code "const_double") 221 (match_test "fp_one_operand (op)"))) 222 223;; Extra constraints 224(define_constraint "Q" 225 "A pc relative load operand." 226 (and (match_code "mem") 227 (match_test "GET_MODE (op) != QImode") 228 (match_test "IS_PC_RELATIVE_LOAD_ADDR_P (XEXP (op, 0))"))) 229 230(define_constraint "Bsc" 231 "Constraint for selecting FLDI0 or FLDI1 instruction. If the clobber 232 operand is not SCRATCH (i.e. REG) then R0 is probably being used, 233 hence mova is being used, hence do not select this pattern." 234 (match_code "scratch")) 235 236(define_constraint "Css" 237 "A signed 16-bit constant, literal or symbolic." 238 (and (match_code "const") 239 (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") 240 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_EXTRACT_S16"))) 241 242(define_constraint "Csu" 243 "An unsigned 16-bit constant, literal or symbolic." 244 (and (match_code "const") 245 (match_test "GET_CODE (XEXP (op, 0)) == UNSPEC") 246 (match_test "XINT (XEXP (op, 0), 1) == UNSPEC_EXTRACT_U16"))) 247 248(define_constraint "Csy" 249 "A label or a symbol." 250 (ior (match_test "NON_PIC_REFERENCE_P (op)") 251 (match_test "PIC_ADDR_P (op)"))) 252 253(define_constraint "Z" 254 "A zero in any shape or form." 255 (match_test "op == CONST0_RTX (GET_MODE (op))")) 256 257(define_constraint "W" 258 "Any vector constant we can handle." 259 (and (match_code "const_vector") 260 (ior (match_test "sh_rep_vec (op, VOIDmode)") 261 (match_test "HOST_BITS_PER_WIDE_INT >= 64 262 ? sh_const_vec (op, VOIDmode) 263 : sh_1el_vec (op, VOIDmode)")))) 264 265(define_constraint "Cpg" 266 "A non-explicit constant that can be loaded directly into a general 267 purpose register. This is like 's' except we don't allow 268 PIC_ADDR_P." 269 (match_test "IS_NON_EXPLICIT_CONSTANT_P (op)")) 270 271(define_constraint "Pso" 272 "Integer constant with a single bit set in its lower 8-bit." 273 (and (match_code "const_int") 274 (ior (match_test "ival == 1") 275 (match_test "ival == 2") 276 (match_test "ival == 4") 277 (match_test "ival == 8") 278 (match_test "ival == 16") 279 (match_test "ival == 32") 280 (match_test "ival == 64") 281 (match_test "ival == 128")))) 282 283(define_constraint "Psz" 284 "Integer constant with a single zero bit in the lower 8-bit." 285 (and (match_code "const_int") 286 (ior (match_test "~ival == 1") 287 (match_test "~ival == 2") 288 (match_test "~ival == 4") 289 (match_test "~ival == 8") 290 (match_test "~ival == 16") 291 (match_test "~ival == 32") 292 (match_test "~ival == 64") 293 (match_test "~ival == 128")))) 294 295(define_memory_constraint "Sua" 296 "@internal" 297 (and (match_test "memory_operand (op, GET_MODE (op))") 298 (match_test "GET_CODE (XEXP (op, 0)) != PLUS"))) 299 300(define_memory_constraint "Sdd" 301 "A memory reference that uses displacement addressing." 302 (and (match_code "mem") 303 (match_code "plus" "0") 304 (match_code "reg" "00") 305 (match_code "const_int" "01"))) 306 307(define_memory_constraint "Snd" 308 "A memory reference that excludes displacement addressing." 309 (and (match_code "mem") 310 (match_test "! satisfies_constraint_Sdd (op)"))) 311 312(define_memory_constraint "Sbv" 313 "A memory reference, as used in SH2A bclr.b, bset.b, etc." 314 (and (match_test "MEM_P (op) && GET_MODE (op) == QImode") 315 (match_test "REG_P (XEXP (op, 0))"))) 316 317(define_memory_constraint "Sbw" 318 "A memory reference, as used in SH2A bclr.b, bset.b, etc." 319 (and (match_test "satisfies_constraint_Sdd (op)") 320 (match_test "GET_MODE (op) == QImode") 321 (match_test "satisfies_constraint_K12 (XEXP (XEXP (op, 0), 1))"))) 322 323(define_memory_constraint "Sra" 324 "A memory reference that uses simple register addressing." 325 (and (match_code "mem") 326 (match_code "reg" "0"))) 327 328(define_memory_constraint "Ara" 329 "A memory reference that uses simple register addressing suitable for 330 gusa atomic operations." 331 (and (match_code "mem") 332 (match_code "reg" "0") 333 (match_test "REGNO (XEXP (op, 0)) != SP_REG"))) 334 335(define_memory_constraint "Add" 336 "A memory reference that uses displacement addressing suitable for 337 gusa atomic operations." 338 (and (match_code "mem") 339 (match_test "GET_MODE (op) == SImode") 340 (match_code "plus" "0") 341 (match_code "reg" "00") 342 (match_code "const_int" "01") 343 (match_test "REGNO (XEXP (XEXP (op, 0), 0)) != SP_REG"))) 344