1;;- Machine description for GNU compiler -- S/390 / zSeries version. 2;; Copyright (C) 1999-2015 Free Software Foundation, Inc. 3;; Contributed by Hartmut Penner (hpenner@de.ibm.com) and 4;; Ulrich Weigand (uweigand@de.ibm.com) and 5;; Andreas Krebbel (Andreas.Krebbel@de.ibm.com) 6 7;; This file is part of GCC. 8 9;; GCC is free software; you can redistribute it and/or modify it under 10;; the terms of the GNU General Public License as published by the Free 11;; Software Foundation; either version 3, or (at your option) any later 12;; version. 13 14;; GCC is distributed in the hope that it will be useful, but WITHOUT ANY 15;; WARRANTY; without even the implied warranty of MERCHANTABILITY or 16;; FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 17;; for more details. 18 19;; You should have received a copy of the GNU General Public License 20;; along with GCC; see the file COPYING3. If not see 21;; <http://www.gnu.org/licenses/>. 22 23;; 24;; See constraints.md for a description of constraints specific to s390. 25;; 26 27;; Special formats used for outputting 390 instructions. 28;; 29;; %C: print opcode suffix for branch condition. 30;; %D: print opcode suffix for inverse branch condition. 31;; %J: print tls_load/tls_gdcall/tls_ldcall suffix 32;; %G: print the size of the operand in bytes. 33;; %O: print only the displacement of a memory reference. 34;; %R: print only the base register of a memory reference. 35;; %S: print S-type memory reference (base+displacement). 36;; %N: print the second word of a DImode operand. 37;; %M: print the second word of a TImode operand. 38;; %Y: print shift count operand. 39;; 40;; %b: print integer X as if it's an unsigned byte. 41;; %c: print integer X as if it's an signed byte. 42;; %x: print integer X as if it's an unsigned halfword. 43;; %h: print integer X as if it's a signed halfword. 44;; %i: print the first nonzero HImode part of X. 45;; %j: print the first HImode part unequal to -1 of X. 46;; %k: print the first nonzero SImode part of X. 47;; %m: print the first SImode part unequal to -1 of X. 48;; %o: print integer X as if it's an unsigned 32bit word. 49;; 50;; We have a special constraint for pattern matching. 51;; 52;; s_operand -- Matches a valid S operand in a RS, SI or SS type instruction. 53;; 54 55;; 56;; UNSPEC usage 57;; 58 59(define_c_enum "unspec" [ 60 ; Miscellaneous 61 UNSPEC_ROUND 62 UNSPEC_ICM 63 UNSPEC_TIE 64 65 ; Convert CC into a str comparison result and copy it into an 66 ; integer register 67 ; cc0->0, cc1->1, cc2->-1, (cc3->-1) 68 UNSPEC_STRCMPCC_TO_INT 69 70 ; Copy CC as is into the lower 2 bits of an integer register 71 UNSPEC_CC_TO_INT 72 73 ; GOT/PLT and lt-relative accesses 74 UNSPEC_LTREL_OFFSET 75 UNSPEC_LTREL_BASE 76 UNSPEC_POOL_OFFSET 77 UNSPEC_GOTENT 78 UNSPEC_GOT 79 UNSPEC_GOTOFF 80 UNSPEC_PLT 81 UNSPEC_PLTOFF 82 83 ; Literal pool 84 UNSPEC_RELOAD_BASE 85 UNSPEC_MAIN_BASE 86 UNSPEC_LTREF 87 UNSPEC_INSN 88 UNSPEC_EXECUTE 89 90 ; Atomic Support 91 UNSPEC_MB 92 UNSPEC_MOVA 93 94 ; TLS relocation specifiers 95 UNSPEC_TLSGD 96 UNSPEC_TLSLDM 97 UNSPEC_NTPOFF 98 UNSPEC_DTPOFF 99 UNSPEC_GOTNTPOFF 100 UNSPEC_INDNTPOFF 101 102 ; TLS support 103 UNSPEC_TLSLDM_NTPOFF 104 UNSPEC_TLS_LOAD 105 106 ; String Functions 107 UNSPEC_SRST 108 UNSPEC_MVST 109 110 ; Stack Smashing Protector 111 UNSPEC_SP_SET 112 UNSPEC_SP_TEST 113 114 ; Test Data Class (TDC) 115 UNSPEC_TDC_INSN 116 117 ; Population Count 118 UNSPEC_POPCNT 119 UNSPEC_COPYSIGN 120 121 ; Load FP Integer 122 UNSPEC_FPINT_FLOOR 123 UNSPEC_FPINT_BTRUNC 124 UNSPEC_FPINT_ROUND 125 UNSPEC_FPINT_CEIL 126 UNSPEC_FPINT_NEARBYINT 127 UNSPEC_FPINT_RINT 128 129 UNSPEC_LCBB 130 131 ; Vector 132 UNSPEC_VEC_SMULT_HI 133 UNSPEC_VEC_UMULT_HI 134 UNSPEC_VEC_SMULT_LO 135 UNSPEC_VEC_SMULT_EVEN 136 UNSPEC_VEC_UMULT_EVEN 137 UNSPEC_VEC_SMULT_ODD 138 UNSPEC_VEC_UMULT_ODD 139 140 UNSPEC_VEC_VMAL 141 UNSPEC_VEC_VMAH 142 UNSPEC_VEC_VMALH 143 UNSPEC_VEC_VMAE 144 UNSPEC_VEC_VMALE 145 UNSPEC_VEC_VMAO 146 UNSPEC_VEC_VMALO 147 148 UNSPEC_VEC_GATHER 149 UNSPEC_VEC_EXTRACT 150 UNSPEC_VEC_INSERT_AND_ZERO 151 UNSPEC_VEC_LOAD_BNDRY 152 UNSPEC_VEC_LOAD_LEN 153 UNSPEC_VEC_MERGEH 154 UNSPEC_VEC_MERGEL 155 UNSPEC_VEC_PACK 156 UNSPEC_VEC_PACK_SATURATE 157 UNSPEC_VEC_PACK_SATURATE_CC 158 UNSPEC_VEC_PACK_SATURATE_GENCC 159 UNSPEC_VEC_PACK_UNSIGNED_SATURATE 160 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_CC 161 UNSPEC_VEC_PACK_UNSIGNED_SATURATE_GENCC 162 UNSPEC_VEC_PERM 163 UNSPEC_VEC_PERMI 164 UNSPEC_VEC_EXTEND 165 UNSPEC_VEC_STORE_LEN 166 UNSPEC_VEC_UNPACKH 167 UNSPEC_VEC_UNPACKH_L 168 UNSPEC_VEC_UNPACKL 169 UNSPEC_VEC_UNPACKL_L 170 UNSPEC_VEC_ADDC 171 UNSPEC_VEC_ADDC_U128 172 UNSPEC_VEC_ADDE_U128 173 UNSPEC_VEC_ADDEC_U128 174 UNSPEC_VEC_AVG 175 UNSPEC_VEC_AVGU 176 UNSPEC_VEC_CHECKSUM 177 UNSPEC_VEC_GFMSUM 178 UNSPEC_VEC_GFMSUM_128 179 UNSPEC_VEC_GFMSUM_ACCUM 180 UNSPEC_VEC_GFMSUM_ACCUM_128 181 UNSPEC_VEC_SET 182 183 UNSPEC_VEC_VSUMG 184 UNSPEC_VEC_VSUMQ 185 UNSPEC_VEC_VSUM 186 UNSPEC_VEC_RL_MASK 187 UNSPEC_VEC_SLL 188 UNSPEC_VEC_SLB 189 UNSPEC_VEC_SLDB 190 UNSPEC_VEC_SRAL 191 UNSPEC_VEC_SRAB 192 UNSPEC_VEC_SRL 193 UNSPEC_VEC_SRLB 194 195 UNSPEC_VEC_SUB_U128 196 UNSPEC_VEC_SUBC 197 UNSPEC_VEC_SUBC_U128 198 UNSPEC_VEC_SUBE_U128 199 UNSPEC_VEC_SUBEC_U128 200 201 UNSPEC_VEC_TEST_MASK 202 203 UNSPEC_VEC_VFAE 204 UNSPEC_VEC_VFAECC 205 206 UNSPEC_VEC_VFEE 207 UNSPEC_VEC_VFEECC 208 UNSPEC_VEC_VFENE 209 UNSPEC_VEC_VFENECC 210 211 UNSPEC_VEC_VISTR 212 UNSPEC_VEC_VISTRCC 213 214 UNSPEC_VEC_VSTRC 215 UNSPEC_VEC_VSTRCCC 216 217 UNSPEC_VEC_VCDGB 218 UNSPEC_VEC_VCDLGB 219 220 UNSPEC_VEC_VCGDB 221 UNSPEC_VEC_VCLGDB 222 223 UNSPEC_VEC_VFIDB 224 225 UNSPEC_VEC_VLDEB 226 UNSPEC_VEC_VLEDB 227 228 UNSPEC_VEC_VFTCIDB 229 UNSPEC_VEC_VFTCIDBCC 230]) 231 232;; 233;; UNSPEC_VOLATILE usage 234;; 235 236(define_c_enum "unspecv" [ 237 ; Blockage 238 UNSPECV_BLOCKAGE 239 240 ; TPF Support 241 UNSPECV_TPF_PROLOGUE 242 UNSPECV_TPF_EPILOGUE 243 244 ; Literal pool 245 UNSPECV_POOL 246 UNSPECV_POOL_SECTION 247 UNSPECV_POOL_ALIGN 248 UNSPECV_POOL_ENTRY 249 UNSPECV_MAIN_POOL 250 251 ; TLS support 252 UNSPECV_SET_TP 253 254 ; Atomic Support 255 UNSPECV_CAS 256 UNSPECV_ATOMIC_OP 257 258 ; Hotpatching (unremovable NOPs) 259 UNSPECV_NOP_2_BYTE 260 UNSPECV_NOP_4_BYTE 261 UNSPECV_NOP_6_BYTE 262 263 ; Transactional Execution support 264 UNSPECV_TBEGIN 265 UNSPECV_TBEGIN_TDB 266 UNSPECV_TBEGINC 267 UNSPECV_TEND 268 UNSPECV_TABORT 269 UNSPECV_ETND 270 UNSPECV_NTSTG 271 UNSPECV_PPA 272 273 ; Set and get floating point control register 274 UNSPECV_SFPC 275 UNSPECV_EFPC 276 ]) 277 278;; 279;; Registers 280;; 281 282; Registers with special meaning 283 284(define_constants 285 [ 286 ; Sibling call register. 287 (SIBCALL_REGNUM 1) 288 ; Literal pool base register. 289 (BASE_REGNUM 13) 290 ; Return address register. 291 (RETURN_REGNUM 14) 292 ; Stack pointer register. 293 (STACK_REGNUM 15) 294 ; Condition code register. 295 (CC_REGNUM 33) 296 ; Thread local storage pointer register. 297 (TP_REGNUM 36) 298 ]) 299 300; Hardware register names 301 302(define_constants 303 [ 304 ; General purpose registers 305 (GPR0_REGNUM 0) 306 (GPR1_REGNUM 1) 307 (GPR2_REGNUM 2) 308 (GPR6_REGNUM 6) 309 ; Floating point registers. 310 (FPR0_REGNUM 16) 311 (FPR1_REGNUM 20) 312 (FPR2_REGNUM 17) 313 (FPR3_REGNUM 21) 314 (FPR4_REGNUM 18) 315 (FPR5_REGNUM 22) 316 (FPR6_REGNUM 19) 317 (FPR7_REGNUM 23) 318 (FPR8_REGNUM 24) 319 (FPR9_REGNUM 28) 320 (FPR10_REGNUM 25) 321 (FPR11_REGNUM 29) 322 (FPR12_REGNUM 26) 323 (FPR13_REGNUM 30) 324 (FPR14_REGNUM 27) 325 (FPR15_REGNUM 31) 326 (VR0_REGNUM 16) 327 (VR16_REGNUM 38) 328 (VR23_REGNUM 45) 329 (VR24_REGNUM 46) 330 (VR31_REGNUM 53) 331 ]) 332 333;; 334;; PFPO GPR0 argument format 335;; 336 337(define_constants 338 [ 339 ; PFPO operation type 340 (PFPO_CONVERT 0x1000000) 341 ; PFPO operand types 342 (PFPO_OP_TYPE_SF 0x5) 343 (PFPO_OP_TYPE_DF 0x6) 344 (PFPO_OP_TYPE_TF 0x7) 345 (PFPO_OP_TYPE_SD 0x8) 346 (PFPO_OP_TYPE_DD 0x9) 347 (PFPO_OP_TYPE_TD 0xa) 348 ; Bitposition of operand types 349 (PFPO_OP0_TYPE_SHIFT 16) 350 (PFPO_OP1_TYPE_SHIFT 8) 351 ]) 352 353; Immediate operands for tbegin and tbeginc 354(define_constants [(TBEGIN_MASK 65292)]) ; 0xff0c 355(define_constants [(TBEGINC_MASK 65288)]) ; 0xff08 356 357;; Instruction operand type as used in the Principles of Operation. 358;; Used to determine defaults for length and other attribute values. 359 360(define_attr "op_type" 361 "NN,E,RR,RRE,RX,RS,RSI,RI,SI,S,SS,SSE,RXE,RSE,RIL,RIE,RXY,RSY,SIY,RRF,RRR,SIL,RRS,RIS,VRI,VRR,VRS,VRV,VRX" 362 (const_string "NN")) 363 364;; Instruction type attribute used for scheduling. 365 366(define_attr "type" "none,integer,load,lr,la,larl,lm,stm, 367 cs,vs,store,sem,idiv, 368 imulhi,imulsi,imuldi, 369 branch,jsr,fsimptf,fsimpdf,fsimpsf,fhex, 370 floadtf,floaddf,floadsf,fstoredf,fstoresf, 371 fmultf,fmuldf,fmulsf,fdivtf,fdivdf,fdivsf, 372 ftoi,fsqrttf,fsqrtdf,fsqrtsf, 373 fmadddf,fmaddsf, 374 ftrunctf,ftruncdf, ftruncsd, ftruncdd, 375 itoftf, itofdf, itofsf, itofdd, itoftd, 376 fdivdd, fdivtd, floaddd, floadsd, fmuldd, fmultd, 377 fsimpdd, fsimpsd, fsimptd, fstoredd, fstoresd, 378 ftoidfp, other" 379 (cond [(eq_attr "op_type" "NN") (const_string "other") 380 (eq_attr "op_type" "SS") (const_string "cs")] 381 (const_string "integer"))) 382 383;; Another attribute used for scheduling purposes: 384;; agen: Instruction uses the address generation unit 385;; reg: Instruction does not use the agen unit 386 387(define_attr "atype" "agen,reg" 388 (if_then_else (eq_attr "op_type" "E,RR,RI,RRE,RSI,RIL,RIE,RRF,RRR") 389 (const_string "reg") 390 (const_string "agen"))) 391 392;; Properties concerning Z10 execution grouping and value forwarding. 393;; z10_super: instruction is superscalar. 394;; z10_super_c: instruction is superscalar and meets the condition of z10_c. 395;; z10_fwd: The instruction reads the value of an operand and stores it into a 396;; target register. It can forward this value to a second instruction that reads 397;; the same register if that second instruction is issued in the same group. 398;; z10_rec: The instruction is in the T pipeline and reads a register. If the 399;; instruction in the S pipe writes to the register, then the T instruction 400;; can immediately read the new value. 401;; z10_fr: union of Z10_fwd and z10_rec. 402;; z10_c: second operand of instruction is a register and read with complemented bits. 403;; 404;; An additional suffix A1, A3, or E1 indicates the respective AGI bypass. 405 406 407(define_attr "z10prop" "none, 408 z10_super, z10_super_E1, z10_super_A1, z10_super_c, z10_super_c_E1, 409 z10_fwd, z10_fwd_A1, z10_fwd_A3, z10_fwd_E1, 410 z10_rec, 411 z10_fr, z10_fr_A3, z10_fr_E1, 412 z10_c" 413 (const_string "none")) 414 415;; Properties concerning Z196 decoding 416;; z196_alone: must group alone 417;; z196_end: ends a group 418;; z196_cracked: instruction is cracked or expanded 419(define_attr "z196prop" "none, 420 z196_alone, z196_ends, 421 z196_cracked" 422 (const_string "none")) 423 424(define_attr "mnemonic" "bcr_flush,unknown" (const_string "unknown")) 425 426;; Length in bytes. 427 428(define_attr "length" "" 429 (cond [(eq_attr "op_type" "E,RR") (const_int 2) 430 (eq_attr "op_type" "RX,RI,RRE,RS,RSI,S,SI,RRF,RRR") (const_int 4)] 431 (const_int 6))) 432 433 434;; Processor type. This attribute must exactly match the processor_type 435;; enumeration in s390.h. The current machine description does not 436;; distinguish between g5 and g6, but there are differences between the two 437;; CPUs could in theory be modeled. 438 439(define_attr "cpu" "g5,g6,z900,z990,z9_109,z9_ec,z10,z196,zEC12,z13" 440 (const (symbol_ref "s390_tune_attr"))) 441 442(define_attr "cpu_facility" 443 "standard,ieee,zarch,cpu_zarch,longdisp,extimm,dfp,z10,z196,zEC12,vec" 444 (const_string "standard")) 445 446(define_attr "enabled" "" 447 (cond [(eq_attr "cpu_facility" "standard") 448 (const_int 1) 449 450 (and (eq_attr "cpu_facility" "ieee") 451 (match_test "TARGET_CPU_IEEE_FLOAT")) 452 (const_int 1) 453 454 (and (eq_attr "cpu_facility" "zarch") 455 (match_test "TARGET_ZARCH")) 456 (const_int 1) 457 458 (and (eq_attr "cpu_facility" "longdisp") 459 (match_test "TARGET_LONG_DISPLACEMENT")) 460 (const_int 1) 461 462 (and (eq_attr "cpu_facility" "extimm") 463 (match_test "TARGET_EXTIMM")) 464 (const_int 1) 465 466 (and (eq_attr "cpu_facility" "dfp") 467 (match_test "TARGET_DFP")) 468 (const_int 1) 469 470 (and (eq_attr "cpu_facility" "cpu_zarch") 471 (match_test "TARGET_CPU_ZARCH")) 472 (const_int 1) 473 474 (and (eq_attr "cpu_facility" "z10") 475 (match_test "TARGET_Z10")) 476 (const_int 1) 477 478 (and (eq_attr "cpu_facility" "z196") 479 (match_test "TARGET_Z196")) 480 (const_int 1) 481 482 (and (eq_attr "cpu_facility" "zEC12") 483 (match_test "TARGET_ZEC12")) 484 (const_int 1) 485 486 (and (eq_attr "cpu_facility" "vec") 487 (match_test "TARGET_VX")) 488 (const_int 1)] 489 (const_int 0))) 490 491;; Pipeline description for z900. For lack of anything better, 492;; this description is also used for the g5 and g6. 493(include "2064.md") 494 495;; Pipeline description for z990, z9-109 and z9-ec. 496(include "2084.md") 497 498;; Pipeline description for z10 499(include "2097.md") 500 501;; Pipeline description for z196 502(include "2817.md") 503 504;; Pipeline description for zEC12 505(include "2827.md") 506 507;; Pipeline description for z13 508(include "2964.md") 509 510;; Predicates 511(include "predicates.md") 512 513;; Constraint definitions 514(include "constraints.md") 515 516;; Other includes 517(include "tpf.md") 518 519;; Iterators 520 521(define_mode_iterator ALL [TI DI SI HI QI TF DF SF TD DD SD V1QI V2QI V4QI V8QI V16QI V1HI V2HI V4HI V8HI V1SI V2SI V4SI V1DI V2DI V1SF V2SF V4SF V1TI V1DF V2DF V1TF]) 522 523;; These mode iterators allow floating point patterns to be generated from the 524;; same template. 525(define_mode_iterator FP_ALL [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP") 526 (SD "TARGET_HARD_DFP")]) 527(define_mode_iterator FP [TF DF SF (TD "TARGET_HARD_DFP") (DD "TARGET_HARD_DFP")]) 528(define_mode_iterator BFP [TF DF SF]) 529(define_mode_iterator DFP [TD DD]) 530(define_mode_iterator DFP_ALL [TD DD SD]) 531(define_mode_iterator DSF [DF SF]) 532(define_mode_iterator SD_SF [SF SD]) 533(define_mode_iterator DD_DF [DF DD]) 534(define_mode_iterator TD_TF [TF TD]) 535 536;; These mode iterators allow 31-bit and 64-bit GPR patterns to be generated 537;; from the same template. 538(define_mode_iterator GPR [(DI "TARGET_ZARCH") SI]) 539(define_mode_iterator DGPR [(TI "TARGET_ZARCH") DI SI]) 540(define_mode_iterator DSI [DI SI]) 541(define_mode_iterator TDI [TI DI]) 542 543;; These mode iterators allow :P to be used for patterns that operate on 544;; pointer-sized quantities. Exactly one of the two alternatives will match. 545(define_mode_iterator P [(DI "TARGET_64BIT") (SI "!TARGET_64BIT")]) 546 547;; These macros refer to the actual word_mode of the configuration. 548;; This is equal to Pmode except on 31-bit machines in zarch mode. 549(define_mode_iterator DW [(TI "TARGET_ZARCH") (DI "!TARGET_ZARCH")]) 550(define_mode_iterator W [(DI "TARGET_ZARCH") (SI "!TARGET_ZARCH")]) 551 552;; Used by the umul pattern to express modes having half the size. 553(define_mode_attr DWH [(TI "DI") (DI "SI")]) 554(define_mode_attr dwh [(TI "di") (DI "si")]) 555 556;; This mode iterator allows the QI and HI patterns to be defined from 557;; the same template. 558(define_mode_iterator HQI [HI QI]) 559 560;; This mode iterator allows the integer patterns to be defined from the 561;; same template. 562(define_mode_iterator INT [(DI "TARGET_ZARCH") SI HI QI]) 563(define_mode_iterator DINT [(TI "TARGET_ZARCH") DI SI HI QI]) 564 565;; This iterator allows some 'ashift' and 'lshiftrt' pattern to be defined from 566;; the same template. 567(define_code_iterator SHIFT [ashift lshiftrt]) 568 569;; This iterator allows r[ox]sbg to be defined with the same template 570(define_code_iterator IXOR [ior xor]) 571 572;; This iterator is used to expand the patterns for the nearest 573;; integer functions. 574(define_int_iterator FPINT [UNSPEC_FPINT_FLOOR UNSPEC_FPINT_BTRUNC 575 UNSPEC_FPINT_ROUND UNSPEC_FPINT_CEIL 576 UNSPEC_FPINT_NEARBYINT]) 577(define_int_attr fpint_name [(UNSPEC_FPINT_FLOOR "floor") 578 (UNSPEC_FPINT_BTRUNC "btrunc") 579 (UNSPEC_FPINT_ROUND "round") 580 (UNSPEC_FPINT_CEIL "ceil") 581 (UNSPEC_FPINT_NEARBYINT "nearbyint")]) 582(define_int_attr fpint_roundingmode [(UNSPEC_FPINT_FLOOR "7") 583 (UNSPEC_FPINT_BTRUNC "5") 584 (UNSPEC_FPINT_ROUND "1") 585 (UNSPEC_FPINT_CEIL "6") 586 (UNSPEC_FPINT_NEARBYINT "0")]) 587 588;; This iterator and attribute allow to combine most atomic operations. 589(define_code_iterator ATOMIC [and ior xor plus minus mult]) 590(define_code_iterator ATOMIC_Z196 [and ior xor plus]) 591(define_code_attr atomic [(and "and") (ior "or") (xor "xor") 592 (plus "add") (minus "sub") (mult "nand")]) 593(define_code_attr noxa [(and "n") (ior "o") (xor "x") (plus "a")]) 594 595;; In FP templates, a string like "lt<de>br" will expand to "ltxbr" in 596;; TF/TDmode, "ltdbr" in DF/DDmode, and "ltebr" in SF/SDmode. 597(define_mode_attr xde [(TF "x") (DF "d") (SF "e") (TD "x") (DD "d") (SD "e")]) 598 599;; In FP templates, a <dee> in "m<dee><bt>r" will expand to "mx<bt>r" in 600;; TF/TDmode, "md<bt>r" in DF/DDmode, "mee<bt>r" in SFmode and "me<bt>r in 601;; SDmode. 602(define_mode_attr xdee [(TF "x") (DF "d") (SF "ee") (TD "x") (DD "d") (SD "e")]) 603 604;; In FP templates, "<RRe>" will expand to "RRE" in TFmode and "RR" otherwise. 605;; Likewise for "<RXe>". 606(define_mode_attr RRe [(TF "RRE") (DF "RR") (SF "RR")]) 607(define_mode_attr RXe [(TF "RXE") (DF "RX") (SF "RX")]) 608 609;; The decimal floating point variants of add, sub, div and mul support 3 610;; fp register operands. The following attributes allow to merge the bfp and 611;; dfp variants in a single insn definition. 612 613;; This attribute is used to set op_type accordingly. 614(define_mode_attr RRer [(TF "RRE") (DF "RRE") (SF "RRE") (TD "RRR") 615 (DD "RRR") (SD "RRR")]) 616 617;; This attribute is used in the operand constraint list in order to have the 618;; first and the second operand match for bfp modes. 619(define_mode_attr f0 [(TF "0") (DF "0") (SF "0") (TD "f") (DD "f") (DD "f")]) 620 621;; This attribute is used to merge the scalar vector instructions into 622;; the FP patterns. For non-supported modes (all but DF) it expands 623;; to constraints which are supposed to be matched by an earlier 624;; variant. 625(define_mode_attr v0 [(TF "0") (DF "v") (SF "0") (TD "0") (DD "0") (DD "0") (TI "0") (DI "v") (SI "0")]) 626(define_mode_attr vf [(TF "f") (DF "v") (SF "f") (TD "f") (DD "f") (DD "f") (TI "f") (DI "v") (SI "f")]) 627(define_mode_attr vd [(TF "d") (DF "v") (SF "d") (TD "d") (DD "d") (DD "d") (TI "d") (DI "v") (SI "d")]) 628 629;; This attribute is used in the operand list of the instruction to have an 630;; additional operand for the dfp instructions. 631(define_mode_attr op1 [(TF "") (DF "") (SF "") 632 (TD "%1,") (DD "%1,") (SD "%1,")]) 633 634 635;; This attribute is used in the operand constraint list 636;; for instructions dealing with the sign bit of 32 or 64bit fp values. 637;; TFmode values are represented by a fp register pair. Since the 638;; sign bit instructions only handle single source and target fp registers 639;; these instructions can only be used for TFmode values if the source and 640;; target operand uses the same fp register. 641(define_mode_attr fT0 [(TF "0") (DF "f") (SF "f")]) 642 643;; In FP templates, "<Rf>" will expand to "f" in TFmode and "R" otherwise. 644;; This is used to disable the memory alternative in TFmode patterns. 645(define_mode_attr Rf [(TF "f") (DF "R") (SF "R") (TD "f") (DD "f") (SD "f")]) 646 647;; This attribute adds b for bfp instructions and t for dfp instructions and is used 648;; within instruction mnemonics. 649(define_mode_attr bt [(TF "b") (DF "b") (SF "b") (TD "t") (DD "t") (SD "t")]) 650 651;; This attribute is used within instruction mnemonics. It evaluates to d for dfp 652;; modes and to an empty string for bfp modes. 653(define_mode_attr _d [(TF "") (DF "") (SF "") (TD "d") (DD "d") (SD "d")]) 654 655;; In GPR and P templates, a constraint like "<d0>" will expand to "d" in DImode 656;; and "0" in SImode. This allows to combine instructions of which the 31bit 657;; version only operates on one register. 658(define_mode_attr d0 [(DI "d") (SI "0")]) 659 660;; In combination with d0 this allows to combine instructions of which the 31bit 661;; version only operates on one register. The DImode version needs an additional 662;; register for the assembler output. 663(define_mode_attr 1 [(DI "%1,") (SI "")]) 664 665;; In SHIFT templates, a string like "s<lr>dl" will expand to "sldl" in 666;; 'ashift' and "srdl" in 'lshiftrt'. 667(define_code_attr lr [(ashift "l") (lshiftrt "r")]) 668 669;; In SHIFT templates, this attribute holds the correct standard name for the 670;; pattern itself and the corresponding function calls. 671(define_code_attr shift [(ashift "ashl") (lshiftrt "lshr")]) 672 673;; This attribute handles differences in the instruction 'type' and will result 674;; in "RRE" for DImode and "RR" for SImode. 675(define_mode_attr E [(DI "E") (SI "")]) 676 677;; This attribute handles differences in the instruction 'type' and makes RX<Y> 678;; to result in "RXY" for DImode and "RX" for SImode. 679(define_mode_attr Y [(DI "Y") (SI "")]) 680 681;; This attribute handles differences in the instruction 'type' and will result 682;; in "RSE" for TImode and "RS" for DImode. 683(define_mode_attr TE [(TI "E") (DI "")]) 684 685;; In GPR templates, a string like "lc<g>r" will expand to "lcgr" in DImode 686;; and "lcr" in SImode. 687(define_mode_attr g [(DI "g") (SI "")]) 688 689;; In GPR templates, a string like "sl<y>" will expand to "slg" in DImode 690;; and "sly" in SImode. This is useful because on 64bit the ..g instructions 691;; were enhanced with long displacements whereas 31bit instructions got a ..y 692;; variant for long displacements. 693(define_mode_attr y [(DI "g") (SI "y")]) 694 695;; In DW templates, a string like "cds<g>" will expand to "cdsg" in TImode 696;; and "cds" in DImode. 697(define_mode_attr tg [(TI "g") (DI "")]) 698 699;; In TDI templates, a string like "c<d>sg". 700(define_mode_attr td [(TI "d") (DI "")]) 701 702;; In GPR templates, a string like "c<gf>dbr" will expand to "cgdbr" in DImode 703;; and "cfdbr" in SImode. 704(define_mode_attr gf [(DI "g") (SI "f")]) 705 706;; In GPR templates, a string like sll<gk> will expand to sllg for DI 707;; and sllk for SI. This way it is possible to merge the new z196 SI 708;; 3 operands shift instructions into the existing patterns. 709(define_mode_attr gk [(DI "g") (SI "k")]) 710 711;; ICM mask required to load MODE value into the lowest subreg 712;; of a SImode register. 713(define_mode_attr icm_lo [(HI "3") (QI "1")]) 714 715;; In HQI templates, a string like "llg<hc>" will expand to "llgh" in 716;; HImode and "llgc" in QImode. 717(define_mode_attr hc [(HI "h") (QI "c")]) 718 719;; In P templates, the mode <DBL> will expand to "TI" in DImode and "DI" 720;; in SImode. 721(define_mode_attr DBL [(DI "TI") (SI "DI")]) 722 723;; This attribute expands to DF for TFmode and to DD for TDmode . It is 724;; used for Txmode splitters splitting a Txmode copy into 2 Dxmode copies. 725(define_mode_attr HALF_TMODE [(TF "DF") (TD "DD")]) 726 727;; Maximum unsigned integer that fits in MODE. 728(define_mode_attr max_uint [(HI "65535") (QI "255")]) 729 730;; Start and end field computations for RISBG et al. 731(define_mode_attr bfstart [(DI "s") (SI "t")]) 732(define_mode_attr bfend [(DI "e") (SI "f")]) 733 734;; In place of GET_MODE_BITSIZE (<MODE>mode) 735(define_mode_attr bitsize [(DI "64") (SI "32") (HI "16") (QI "8")]) 736 737;; Allow return and simple_return to be defined from a single template. 738(define_code_iterator ANY_RETURN [return simple_return]) 739 740 741 742; Condition code modes generated by vector fp comparisons. These will 743; be used also in single element mode. 744(define_mode_iterator VFCMP [CCVEQ CCVFH CCVFHE]) 745; Used with VFCMP to expand part of the mnemonic 746; For fp we have a mismatch: eq in the insn name - e in asm 747(define_mode_attr asm_fcmp [(CCVEQ "e") (CCVFH "h") (CCVFHE "he")]) 748(define_mode_attr insn_cmp [(CCVEQ "eq") (CCVH "h") (CCVHU "hl") (CCVFH "h") (CCVFHE "he")]) 749 750 751(include "vector.md") 752 753;; 754;;- Compare instructions. 755;; 756 757; Test-under-Mask instructions 758 759(define_insn "*tmqi_mem" 760 [(set (reg CC_REGNUM) 761 (compare (and:QI (match_operand:QI 0 "memory_operand" "Q,S") 762 (match_operand:QI 1 "immediate_operand" "n,n")) 763 (match_operand:QI 2 "immediate_operand" "n,n")))] 764 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], false))" 765 "@ 766 tm\t%S0,%b1 767 tmy\t%S0,%b1" 768 [(set_attr "op_type" "SI,SIY") 769 (set_attr "z10prop" "z10_super,z10_super")]) 770 771(define_insn "*tmdi_reg" 772 [(set (reg CC_REGNUM) 773 (compare (and:DI (match_operand:DI 0 "nonimmediate_operand" "d,d,d,d") 774 (match_operand:DI 1 "immediate_operand" 775 "N0HD0,N1HD0,N2HD0,N3HD0")) 776 (match_operand:DI 2 "immediate_operand" "n,n,n,n")))] 777 "TARGET_ZARCH 778 && s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) 779 && s390_single_part (operands[1], DImode, HImode, 0) >= 0" 780 "@ 781 tmhh\t%0,%i1 782 tmhl\t%0,%i1 783 tmlh\t%0,%i1 784 tmll\t%0,%i1" 785 [(set_attr "op_type" "RI") 786 (set_attr "z10prop" "z10_super,z10_super,z10_super,z10_super")]) 787 788(define_insn "*tmsi_reg" 789 [(set (reg CC_REGNUM) 790 (compare (and:SI (match_operand:SI 0 "nonimmediate_operand" "d,d") 791 (match_operand:SI 1 "immediate_operand" "N0HS0,N1HS0")) 792 (match_operand:SI 2 "immediate_operand" "n,n")))] 793 "s390_match_ccmode (insn, s390_tm_ccmode (operands[1], operands[2], true)) 794 && s390_single_part (operands[1], SImode, HImode, 0) >= 0" 795 "@ 796 tmh\t%0,%i1 797 tml\t%0,%i1" 798 [(set_attr "op_type" "RI") 799 (set_attr "z10prop" "z10_super,z10_super")]) 800 801(define_insn "*tm<mode>_full" 802 [(set (reg CC_REGNUM) 803 (compare (match_operand:HQI 0 "register_operand" "d") 804 (match_operand:HQI 1 "immediate_operand" "n")))] 805 "s390_match_ccmode (insn, s390_tm_ccmode (constm1_rtx, operands[1], true))" 806 "tml\t%0,<max_uint>" 807 [(set_attr "op_type" "RI") 808 (set_attr "z10prop" "z10_super")]) 809 810 811; 812; Load-and-Test instructions 813; 814 815; tst(di|si) instruction pattern(s). 816 817(define_insn "*tstdi_sign" 818 [(set (reg CC_REGNUM) 819 (compare 820 (ashiftrt:DI 821 (ashift:DI 822 (subreg:DI (match_operand:SI 0 "nonimmediate_operand" "d,RT") 0) 823 (const_int 32)) (const_int 32)) 824 (match_operand:DI 1 "const0_operand" ""))) 825 (set (match_operand:DI 2 "register_operand" "=d,d") 826 (sign_extend:DI (match_dup 0)))] 827 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH" 828 "ltgfr\t%2,%0 829 ltgf\t%2,%0" 830 [(set_attr "op_type" "RRE,RXY") 831 (set_attr "cpu_facility" "*,z10") 832 (set_attr "z10prop" "z10_super_E1,z10_super_E1") ]) 833 834; ltr, lt, ltgr, ltg 835(define_insn "*tst<mode>_extimm" 836 [(set (reg CC_REGNUM) 837 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") 838 (match_operand:GPR 1 "const0_operand" ""))) 839 (set (match_operand:GPR 2 "register_operand" "=d,d") 840 (match_dup 0))] 841 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" 842 "@ 843 lt<g>r\t%2,%0 844 lt<g>\t%2,%0" 845 [(set_attr "op_type" "RR<E>,RXY") 846 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3") ]) 847 848; ltr, lt, ltgr, ltg 849(define_insn "*tst<mode>_cconly_extimm" 850 [(set (reg CC_REGNUM) 851 (compare (match_operand:GPR 0 "nonimmediate_operand" "d,RT") 852 (match_operand:GPR 1 "const0_operand" ""))) 853 (clobber (match_scratch:GPR 2 "=X,d"))] 854 "s390_match_ccmode(insn, CCSmode) && TARGET_EXTIMM" 855 "@ 856 lt<g>r\t%0,%0 857 lt<g>\t%2,%0" 858 [(set_attr "op_type" "RR<E>,RXY") 859 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3")]) 860 861(define_insn "*tstdi" 862 [(set (reg CC_REGNUM) 863 (compare (match_operand:DI 0 "register_operand" "d") 864 (match_operand:DI 1 "const0_operand" ""))) 865 (set (match_operand:DI 2 "register_operand" "=d") 866 (match_dup 0))] 867 "s390_match_ccmode(insn, CCSmode) && TARGET_ZARCH && !TARGET_EXTIMM" 868 "ltgr\t%2,%0" 869 [(set_attr "op_type" "RRE") 870 (set_attr "z10prop" "z10_fr_E1")]) 871 872(define_insn "*tstsi" 873 [(set (reg CC_REGNUM) 874 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") 875 (match_operand:SI 1 "const0_operand" ""))) 876 (set (match_operand:SI 2 "register_operand" "=d,d,d") 877 (match_dup 0))] 878 "s390_match_ccmode(insn, CCSmode) && !TARGET_EXTIMM" 879 "@ 880 ltr\t%2,%0 881 icm\t%2,15,%S0 882 icmy\t%2,15,%S0" 883 [(set_attr "op_type" "RR,RS,RSY") 884 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) 885 886(define_insn "*tstsi_cconly" 887 [(set (reg CC_REGNUM) 888 (compare (match_operand:SI 0 "nonimmediate_operand" "d,Q,S") 889 (match_operand:SI 1 "const0_operand" ""))) 890 (clobber (match_scratch:SI 2 "=X,d,d"))] 891 "s390_match_ccmode(insn, CCSmode)" 892 "@ 893 ltr\t%0,%0 894 icm\t%2,15,%S0 895 icmy\t%2,15,%S0" 896 [(set_attr "op_type" "RR,RS,RSY") 897 (set_attr "z10prop" "z10_fr_E1,z10_super_E1,z10_super_E1")]) 898 899(define_insn "*tstdi_cconly_31" 900 [(set (reg CC_REGNUM) 901 (compare (match_operand:DI 0 "register_operand" "d") 902 (match_operand:DI 1 "const0_operand" "")))] 903 "s390_match_ccmode(insn, CCSmode) && !TARGET_ZARCH" 904 "srda\t%0,0" 905 [(set_attr "op_type" "RS") 906 (set_attr "atype" "reg")]) 907 908; ltr, ltgr 909(define_insn "*tst<mode>_cconly2" 910 [(set (reg CC_REGNUM) 911 (compare (match_operand:GPR 0 "register_operand" "d") 912 (match_operand:GPR 1 "const0_operand" "")))] 913 "s390_match_ccmode(insn, CCSmode)" 914 "lt<g>r\t%0,%0" 915 [(set_attr "op_type" "RR<E>") 916 (set_attr "z10prop" "z10_fr_E1")]) 917 918; tst(hi|qi) instruction pattern(s). 919 920(define_insn "*tst<mode>CCT" 921 [(set (reg CC_REGNUM) 922 (compare (match_operand:HQI 0 "nonimmediate_operand" "?Q,?S,d") 923 (match_operand:HQI 1 "const0_operand" ""))) 924 (set (match_operand:HQI 2 "register_operand" "=d,d,0") 925 (match_dup 0))] 926 "s390_match_ccmode(insn, CCTmode)" 927 "@ 928 icm\t%2,<icm_lo>,%S0 929 icmy\t%2,<icm_lo>,%S0 930 tml\t%0,<max_uint>" 931 [(set_attr "op_type" "RS,RSY,RI") 932 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) 933 934(define_insn "*tsthiCCT_cconly" 935 [(set (reg CC_REGNUM) 936 (compare (match_operand:HI 0 "nonimmediate_operand" "Q,S,d") 937 (match_operand:HI 1 "const0_operand" ""))) 938 (clobber (match_scratch:HI 2 "=d,d,X"))] 939 "s390_match_ccmode(insn, CCTmode)" 940 "@ 941 icm\t%2,3,%S0 942 icmy\t%2,3,%S0 943 tml\t%0,65535" 944 [(set_attr "op_type" "RS,RSY,RI") 945 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super")]) 946 947(define_insn "*tstqiCCT_cconly" 948 [(set (reg CC_REGNUM) 949 (compare (match_operand:QI 0 "nonimmediate_operand" "?Q,?S,d") 950 (match_operand:QI 1 "const0_operand" "")))] 951 "s390_match_ccmode(insn, CCTmode)" 952 "@ 953 cli\t%S0,0 954 cliy\t%S0,0 955 tml\t%0,255" 956 [(set_attr "op_type" "SI,SIY,RI") 957 (set_attr "z10prop" "z10_super,z10_super,z10_super")]) 958 959(define_insn "*tst<mode>" 960 [(set (reg CC_REGNUM) 961 (compare (match_operand:HQI 0 "s_operand" "Q,S") 962 (match_operand:HQI 1 "const0_operand" ""))) 963 (set (match_operand:HQI 2 "register_operand" "=d,d") 964 (match_dup 0))] 965 "s390_match_ccmode(insn, CCSmode)" 966 "@ 967 icm\t%2,<icm_lo>,%S0 968 icmy\t%2,<icm_lo>,%S0" 969 [(set_attr "op_type" "RS,RSY") 970 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 971 972(define_insn "*tst<mode>_cconly" 973 [(set (reg CC_REGNUM) 974 (compare (match_operand:HQI 0 "s_operand" "Q,S") 975 (match_operand:HQI 1 "const0_operand" ""))) 976 (clobber (match_scratch:HQI 2 "=d,d"))] 977 "s390_match_ccmode(insn, CCSmode)" 978 "@ 979 icm\t%2,<icm_lo>,%S0 980 icmy\t%2,<icm_lo>,%S0" 981 [(set_attr "op_type" "RS,RSY") 982 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 983 984 985; Compare (equality) instructions 986 987(define_insn "*cmpdi_cct" 988 [(set (reg CC_REGNUM) 989 (compare (match_operand:DI 0 "nonimmediate_operand" "%d,d,d,d,Q") 990 (match_operand:DI 1 "general_operand" "d,K,Os,RT,BQ")))] 991 "s390_match_ccmode (insn, CCTmode) && TARGET_ZARCH" 992 "@ 993 cgr\t%0,%1 994 cghi\t%0,%h1 995 cgfi\t%0,%1 996 cg\t%0,%1 997 #" 998 [(set_attr "op_type" "RRE,RI,RIL,RXY,SS") 999 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,*")]) 1000 1001(define_insn "*cmpsi_cct" 1002 [(set (reg CC_REGNUM) 1003 (compare (match_operand:SI 0 "nonimmediate_operand" "%d,d,d,d,d,Q") 1004 (match_operand:SI 1 "general_operand" "d,K,Os,R,T,BQ")))] 1005 "s390_match_ccmode (insn, CCTmode)" 1006 "@ 1007 cr\t%0,%1 1008 chi\t%0,%h1 1009 cfi\t%0,%1 1010 c\t%0,%1 1011 cy\t%0,%1 1012 #" 1013 [(set_attr "op_type" "RR,RI,RIL,RX,RXY,SS") 1014 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*")]) 1015 1016; Compare (signed) instructions 1017 1018(define_insn "*cmpdi_ccs_sign" 1019 [(set (reg CC_REGNUM) 1020 (compare (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" 1021 "d,RT,b")) 1022 (match_operand:DI 0 "register_operand" "d, d,d")))] 1023 "s390_match_ccmode(insn, CCSRmode) && TARGET_ZARCH" 1024 "@ 1025 cgfr\t%0,%1 1026 cgf\t%0,%1 1027 cgfrl\t%0,%1" 1028 [(set_attr "op_type" "RRE,RXY,RIL") 1029 (set_attr "z10prop" "z10_c,*,*") 1030 (set_attr "type" "*,*,larl")]) 1031 1032 1033 1034(define_insn "*cmpsi_ccs_sign" 1035 [(set (reg CC_REGNUM) 1036 (compare (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T,b")) 1037 (match_operand:SI 0 "register_operand" "d,d,d")))] 1038 "s390_match_ccmode(insn, CCSRmode)" 1039 "@ 1040 ch\t%0,%1 1041 chy\t%0,%1 1042 chrl\t%0,%1" 1043 [(set_attr "op_type" "RX,RXY,RIL") 1044 (set_attr "cpu_facility" "*,*,z10") 1045 (set_attr "type" "*,*,larl") 1046 (set_attr "z196prop" "z196_cracked,z196_cracked,z196_cracked")]) 1047 1048(define_insn "*cmphi_ccs_z10" 1049 [(set (reg CC_REGNUM) 1050 (compare (match_operand:HI 0 "s_operand" "Q") 1051 (match_operand:HI 1 "immediate_operand" "K")))] 1052 "s390_match_ccmode(insn, CCSmode) && TARGET_Z10" 1053 "chhsi\t%0,%1" 1054 [(set_attr "op_type" "SIL") 1055 (set_attr "z196prop" "z196_cracked")]) 1056 1057(define_insn "*cmpdi_ccs_signhi_rl" 1058 [(set (reg CC_REGNUM) 1059 (compare (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT,b")) 1060 (match_operand:GPR 0 "register_operand" "d,d")))] 1061 "s390_match_ccmode(insn, CCSRmode) && TARGET_Z10" 1062 "@ 1063 cgh\t%0,%1 1064 cghrl\t%0,%1" 1065 [(set_attr "op_type" "RXY,RIL") 1066 (set_attr "type" "*,larl")]) 1067 1068; cr, chi, cfi, c, cy, cgr, cghi, cgfi, cg, chsi, cghsi, crl, cgrl 1069(define_insn "*cmp<mode>_ccs" 1070 [(set (reg CC_REGNUM) 1071 (compare (match_operand:GPR 0 "nonimmediate_operand" 1072 "d,d,Q, d,d,d,d") 1073 (match_operand:GPR 1 "general_operand" 1074 "d,K,K,Os,R,T,b")))] 1075 "s390_match_ccmode(insn, CCSmode)" 1076 "@ 1077 c<g>r\t%0,%1 1078 c<g>hi\t%0,%h1 1079 c<g>hsi\t%0,%h1 1080 c<g>fi\t%0,%1 1081 c<g>\t%0,%1 1082 c<y>\t%0,%1 1083 c<g>rl\t%0,%1" 1084 [(set_attr "op_type" "RR<E>,RI,SIL,RIL,RX<Y>,RXY,RIL") 1085 (set_attr "cpu_facility" "*,*,z10,extimm,*,*,z10") 1086 (set_attr "type" "*,*,*,*,*,*,larl") 1087 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,z10_super")]) 1088 1089 1090; Compare (unsigned) instructions 1091 1092(define_insn "*cmpsi_ccu_zerohi_rlsi" 1093 [(set (reg CC_REGNUM) 1094 (compare (zero_extend:SI (mem:HI (match_operand:SI 1 1095 "larl_operand" "X"))) 1096 (match_operand:SI 0 "register_operand" "d")))] 1097 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" 1098 "clhrl\t%0,%1" 1099 [(set_attr "op_type" "RIL") 1100 (set_attr "type" "larl") 1101 (set_attr "z10prop" "z10_super")]) 1102 1103; clhrl, clghrl 1104(define_insn "*cmp<GPR:mode>_ccu_zerohi_rldi" 1105 [(set (reg CC_REGNUM) 1106 (compare (zero_extend:GPR (mem:HI (match_operand:DI 1 1107 "larl_operand" "X"))) 1108 (match_operand:GPR 0 "register_operand" "d")))] 1109 "s390_match_ccmode(insn, CCURmode) && TARGET_Z10" 1110 "cl<g>hrl\t%0,%1" 1111 [(set_attr "op_type" "RIL") 1112 (set_attr "type" "larl") 1113 (set_attr "z10prop" "z10_super")]) 1114 1115(define_insn "*cmpdi_ccu_zero" 1116 [(set (reg CC_REGNUM) 1117 (compare (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" 1118 "d,RT,b")) 1119 (match_operand:DI 0 "register_operand" "d, d,d")))] 1120 "s390_match_ccmode (insn, CCURmode) && TARGET_ZARCH" 1121 "@ 1122 clgfr\t%0,%1 1123 clgf\t%0,%1 1124 clgfrl\t%0,%1" 1125 [(set_attr "op_type" "RRE,RXY,RIL") 1126 (set_attr "cpu_facility" "*,*,z10") 1127 (set_attr "type" "*,*,larl") 1128 (set_attr "z10prop" "z10_super_c,z10_super_E1,z10_super")]) 1129 1130(define_insn "*cmpdi_ccu" 1131 [(set (reg CC_REGNUM) 1132 (compare (match_operand:DI 0 "nonimmediate_operand" 1133 "d, d,d,Q, d, Q,BQ") 1134 (match_operand:DI 1 "general_operand" 1135 "d,Op,b,D,RT,BQ,Q")))] 1136 "s390_match_ccmode (insn, CCUmode) && TARGET_ZARCH" 1137 "@ 1138 clgr\t%0,%1 1139 clgfi\t%0,%1 1140 clgrl\t%0,%1 1141 clghsi\t%0,%x1 1142 clg\t%0,%1 1143 # 1144 #" 1145 [(set_attr "op_type" "RRE,RIL,RIL,SIL,RXY,SS,SS") 1146 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*") 1147 (set_attr "type" "*,*,larl,*,*,*,*") 1148 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,*,*")]) 1149 1150(define_insn "*cmpsi_ccu" 1151 [(set (reg CC_REGNUM) 1152 (compare (match_operand:SI 0 "nonimmediate_operand" "d, d,d,Q,d,d, Q,BQ") 1153 (match_operand:SI 1 "general_operand" "d,Os,b,D,R,T,BQ, Q")))] 1154 "s390_match_ccmode (insn, CCUmode)" 1155 "@ 1156 clr\t%0,%1 1157 clfi\t%0,%o1 1158 clrl\t%0,%1 1159 clfhsi\t%0,%x1 1160 cl\t%0,%1 1161 cly\t%0,%1 1162 # 1163 #" 1164 [(set_attr "op_type" "RR,RIL,RIL,SIL,RX,RXY,SS,SS") 1165 (set_attr "cpu_facility" "*,extimm,z10,z10,*,*,*,*") 1166 (set_attr "type" "*,*,larl,*,*,*,*,*") 1167 (set_attr "z10prop" "z10_super_c,z10_super,z10_super,z10_super,z10_super,z10_super,*,*")]) 1168 1169(define_insn "*cmphi_ccu" 1170 [(set (reg CC_REGNUM) 1171 (compare (match_operand:HI 0 "nonimmediate_operand" "d,d,Q,Q,BQ") 1172 (match_operand:HI 1 "general_operand" "Q,S,D,BQ,Q")))] 1173 "s390_match_ccmode (insn, CCUmode) 1174 && !register_operand (operands[1], HImode)" 1175 "@ 1176 clm\t%0,3,%S1 1177 clmy\t%0,3,%S1 1178 clhhsi\t%0,%1 1179 # 1180 #" 1181 [(set_attr "op_type" "RS,RSY,SIL,SS,SS") 1182 (set_attr "cpu_facility" "*,*,z10,*,*") 1183 (set_attr "z10prop" "*,*,z10_super,*,*")]) 1184 1185(define_insn "*cmpqi_ccu" 1186 [(set (reg CC_REGNUM) 1187 (compare (match_operand:QI 0 "nonimmediate_operand" "d,d,Q,S,Q,BQ") 1188 (match_operand:QI 1 "general_operand" "Q,S,n,n,BQ,Q")))] 1189 "s390_match_ccmode (insn, CCUmode) 1190 && !register_operand (operands[1], QImode)" 1191 "@ 1192 clm\t%0,1,%S1 1193 clmy\t%0,1,%S1 1194 cli\t%S0,%b1 1195 cliy\t%S0,%b1 1196 # 1197 #" 1198 [(set_attr "op_type" "RS,RSY,SI,SIY,SS,SS") 1199 (set_attr "z10prop" "*,*,z10_super,z10_super,*,*")]) 1200 1201 1202; Block compare (CLC) instruction patterns. 1203 1204(define_insn "*clc" 1205 [(set (reg CC_REGNUM) 1206 (compare (match_operand:BLK 0 "memory_operand" "Q") 1207 (match_operand:BLK 1 "memory_operand" "Q"))) 1208 (use (match_operand 2 "const_int_operand" "n"))] 1209 "s390_match_ccmode (insn, CCUmode) 1210 && INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 1211 "clc\t%O0(%2,%R0),%S1" 1212 [(set_attr "op_type" "SS")]) 1213 1214(define_split 1215 [(set (reg CC_REGNUM) 1216 (compare (match_operand 0 "memory_operand" "") 1217 (match_operand 1 "memory_operand" "")))] 1218 "reload_completed 1219 && s390_match_ccmode (insn, CCUmode) 1220 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 1221 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 1222 [(parallel 1223 [(set (match_dup 0) (match_dup 1)) 1224 (use (match_dup 2))])] 1225{ 1226 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 1227 operands[0] = adjust_address (operands[0], BLKmode, 0); 1228 operands[1] = adjust_address (operands[1], BLKmode, 0); 1229 1230 operands[1] = gen_rtx_COMPARE (GET_MODE (SET_DEST (PATTERN (curr_insn))), 1231 operands[0], operands[1]); 1232 operands[0] = SET_DEST (PATTERN (curr_insn)); 1233}) 1234 1235 1236; (TF|DF|SF|TD|DD|SD) instructions 1237 1238; ltxbr, ltdbr, ltebr, ltxtr, ltdtr 1239(define_insn "*cmp<mode>_ccs_0" 1240 [(set (reg CC_REGNUM) 1241 (compare (match_operand:FP 0 "register_operand" "f") 1242 (match_operand:FP 1 "const0_operand" "")))] 1243 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" 1244 "lt<xde><bt>r\t%0,%0" 1245 [(set_attr "op_type" "RRE") 1246 (set_attr "type" "fsimp<mode>")]) 1247 1248; cxtr, cxbr, cdtr, cdbr, cebr, cdb, ceb 1249(define_insn "*cmp<mode>_ccs" 1250 [(set (reg CC_REGNUM) 1251 (compare (match_operand:FP 0 "register_operand" "f,f") 1252 (match_operand:FP 1 "general_operand" "f,<Rf>")))] 1253 "s390_match_ccmode(insn, CCSmode) && TARGET_HARD_FLOAT" 1254 "@ 1255 c<xde><bt>r\t%0,%1 1256 c<xde>b\t%0,%1" 1257 [(set_attr "op_type" "RRE,RXE") 1258 (set_attr "type" "fsimp<mode>")]) 1259 1260; wfcedbs, wfchdbs, wfchedbs 1261(define_insn "*vec_cmp<insn_cmp>df_cconly" 1262 [(set (reg:VFCMP CC_REGNUM) 1263 (compare:VFCMP (match_operand:DF 0 "register_operand" "v") 1264 (match_operand:DF 1 "register_operand" "v"))) 1265 (clobber (match_scratch:V2DI 2 "=v"))] 1266 "TARGET_VX && TARGET_HARD_FLOAT" 1267 "wfc<asm_fcmp>dbs\t%v2,%v0,%v1" 1268 [(set_attr "op_type" "VRR")]) 1269 1270; Compare and Branch instructions 1271 1272; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr 1273; The following instructions do a complementary access of their second 1274; operand (z01 only): crj_c, cgrjc, cr, cgr 1275(define_insn "*cmp_and_br_signed_<mode>" 1276 [(set (pc) 1277 (if_then_else (match_operator 0 "s390_signed_integer_comparison" 1278 [(match_operand:GPR 1 "register_operand" "d,d") 1279 (match_operand:GPR 2 "nonmemory_operand" "d,C")]) 1280 (label_ref (match_operand 3 "" "")) 1281 (pc))) 1282 (clobber (reg:CC CC_REGNUM))] 1283 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1284{ 1285 if (get_attr_length (insn) == 6) 1286 return which_alternative ? 1287 "c<g>ij%C0\t%1,%c2,%l3" : "c<g>rj%C0\t%1,%2,%l3"; 1288 else 1289 return which_alternative ? 1290 "c<g>fi\t%1,%c2\;jg%C0\t%l3" : "c<g>r\t%1,%2\;jg%C0\t%l3"; 1291} 1292 [(set_attr "op_type" "RIE") 1293 (set_attr "type" "branch") 1294 (set_attr "z10prop" "z10_super_c,z10_super") 1295 (set (attr "length") 1296 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1297 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg 1298 ; 10 byte for cgr/jg 1299 1300; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr 1301; The following instructions do a complementary access of their second 1302; operand (z10 only): clrj, clgrj, clr, clgr 1303(define_insn "*cmp_and_br_unsigned_<mode>" 1304 [(set (pc) 1305 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" 1306 [(match_operand:GPR 1 "register_operand" "d,d") 1307 (match_operand:GPR 2 "nonmemory_operand" "d,I")]) 1308 (label_ref (match_operand 3 "" "")) 1309 (pc))) 1310 (clobber (reg:CC CC_REGNUM))] 1311 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1312{ 1313 if (get_attr_length (insn) == 6) 1314 return which_alternative ? 1315 "cl<g>ij%C0\t%1,%b2,%l3" : "cl<g>rj%C0\t%1,%2,%l3"; 1316 else 1317 return which_alternative ? 1318 "cl<g>fi\t%1,%b2\;jg%C0\t%l3" : "cl<g>r\t%1,%2\;jg%C0\t%l3"; 1319} 1320 [(set_attr "op_type" "RIE") 1321 (set_attr "type" "branch") 1322 (set_attr "z10prop" "z10_super_c,z10_super") 1323 (set (attr "length") 1324 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1325 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg 1326 ; 10 byte for clgr/jg 1327 1328; And now the same two patterns as above but with a negated CC mask. 1329 1330; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr 1331; The following instructions do a complementary access of their second 1332; operand (z01 only): crj_c, cgrjc, cr, cgr 1333(define_insn "*icmp_and_br_signed_<mode>" 1334 [(set (pc) 1335 (if_then_else (match_operator 0 "s390_signed_integer_comparison" 1336 [(match_operand:GPR 1 "register_operand" "d,d") 1337 (match_operand:GPR 2 "nonmemory_operand" "d,C")]) 1338 (pc) 1339 (label_ref (match_operand 3 "" "")))) 1340 (clobber (reg:CC CC_REGNUM))] 1341 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1342{ 1343 if (get_attr_length (insn) == 6) 1344 return which_alternative ? 1345 "c<g>ij%D0\t%1,%c2,%l3" : "c<g>rj%D0\t%1,%2,%l3"; 1346 else 1347 return which_alternative ? 1348 "c<g>fi\t%1,%c2\;jg%D0\t%l3" : "c<g>r\t%1,%2\;jg%D0\t%l3"; 1349} 1350 [(set_attr "op_type" "RIE") 1351 (set_attr "type" "branch") 1352 (set_attr "z10prop" "z10_super_c,z10_super") 1353 (set (attr "length") 1354 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1355 (const_int 6) (const_int 12)))]) ; 8 byte for cr/jg 1356 ; 10 byte for cgr/jg 1357 1358; clij, clgij, clrj, clgrj, clfi, clgfi, clr, clgr 1359; The following instructions do a complementary access of their second 1360; operand (z10 only): clrj, clgrj, clr, clgr 1361(define_insn "*icmp_and_br_unsigned_<mode>" 1362 [(set (pc) 1363 (if_then_else (match_operator 0 "s390_unsigned_integer_comparison" 1364 [(match_operand:GPR 1 "register_operand" "d,d") 1365 (match_operand:GPR 2 "nonmemory_operand" "d,I")]) 1366 (pc) 1367 (label_ref (match_operand 3 "" "")))) 1368 (clobber (reg:CC CC_REGNUM))] 1369 "TARGET_Z10 && !TARGET_AVOID_CMP_AND_BRANCH" 1370{ 1371 if (get_attr_length (insn) == 6) 1372 return which_alternative ? 1373 "cl<g>ij%D0\t%1,%b2,%l3" : "cl<g>rj%D0\t%1,%2,%l3"; 1374 else 1375 return which_alternative ? 1376 "cl<g>fi\t%1,%b2\;jg%D0\t%l3" : "cl<g>r\t%1,%2\;jg%D0\t%l3"; 1377} 1378 [(set_attr "op_type" "RIE") 1379 (set_attr "type" "branch") 1380 (set_attr "z10prop" "z10_super_c,z10_super") 1381 (set (attr "length") 1382 (if_then_else (lt (abs (minus (pc) (match_dup 3))) (const_int 60000)) 1383 (const_int 6) (const_int 12)))]) ; 8 byte for clr/jg 1384 ; 10 byte for clgr/jg 1385 1386;; 1387;;- Move instructions. 1388;; 1389 1390; 1391; movti instruction pattern(s). 1392; 1393 1394; FIXME: More constants are possible by enabling jxx, jyy constraints 1395; for TImode (use double-int for the calculations) 1396(define_insn "movti" 1397 [(set (match_operand:TI 0 "nonimmediate_operand" "=d,QS,v, v, v,v,d, v,QR, d,o") 1398 (match_operand:TI 1 "general_operand" "QS, d,v,j00,jm1,d,v,QR, v,dPRT,d"))] 1399 "TARGET_ZARCH" 1400 "@ 1401 lmg\t%0,%N0,%S1 1402 stmg\t%1,%N1,%S0 1403 vlr\t%v0,%v1 1404 vzero\t%v0 1405 vone\t%v0 1406 vlvgp\t%v0,%1,%N1 1407 # 1408 vl\t%v0,%1 1409 vst\t%v1,%0 1410 # 1411 #" 1412 [(set_attr "op_type" "RSY,RSY,VRR,VRI,VRI,VRR,*,VRX,VRX,*,*") 1413 (set_attr "type" "lm,stm,*,*,*,*,*,*,*,*,*") 1414 (set_attr "cpu_facility" "*,*,vec,vec,vec,vec,vec,vec,vec,*,*")]) 1415 1416(define_split 1417 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1418 (match_operand:TI 1 "general_operand" ""))] 1419 "TARGET_ZARCH && reload_completed 1420 && s390_split_ok_p (operands[0], operands[1], TImode, 0)" 1421 [(set (match_dup 2) (match_dup 4)) 1422 (set (match_dup 3) (match_dup 5))] 1423{ 1424 operands[2] = operand_subword (operands[0], 0, 0, TImode); 1425 operands[3] = operand_subword (operands[0], 1, 0, TImode); 1426 operands[4] = operand_subword (operands[1], 0, 0, TImode); 1427 operands[5] = operand_subword (operands[1], 1, 0, TImode); 1428}) 1429 1430(define_split 1431 [(set (match_operand:TI 0 "nonimmediate_operand" "") 1432 (match_operand:TI 1 "general_operand" ""))] 1433 "TARGET_ZARCH && reload_completed 1434 && s390_split_ok_p (operands[0], operands[1], TImode, 1)" 1435 [(set (match_dup 2) (match_dup 4)) 1436 (set (match_dup 3) (match_dup 5))] 1437{ 1438 operands[2] = operand_subword (operands[0], 1, 0, TImode); 1439 operands[3] = operand_subword (operands[0], 0, 0, TImode); 1440 operands[4] = operand_subword (operands[1], 1, 0, TImode); 1441 operands[5] = operand_subword (operands[1], 0, 0, TImode); 1442}) 1443 1444; Use part of the TImode target reg to perform the address 1445; calculation. If the TImode value is supposed to be copied into a VR 1446; this splitter is not necessary. 1447(define_split 1448 [(set (match_operand:TI 0 "register_operand" "") 1449 (match_operand:TI 1 "memory_operand" ""))] 1450 "TARGET_ZARCH && reload_completed 1451 && !VECTOR_REG_P (operands[0]) 1452 && !s_operand (operands[1], VOIDmode)" 1453 [(set (match_dup 0) (match_dup 1))] 1454{ 1455 rtx addr = operand_subword (operands[0], 1, 0, TImode); 1456 addr = gen_lowpart (Pmode, addr); 1457 s390_load_address (addr, XEXP (operands[1], 0)); 1458 operands[1] = replace_equiv_address (operands[1], addr); 1459}) 1460 1461 1462; Split a VR -> GPR TImode move into 2 vector load GR from VR element. 1463; For the higher order bits we do simply a DImode move while the 1464; second part is done via vec extract. Both will end up as vlgvg. 1465(define_split 1466 [(set (match_operand:TI 0 "register_operand" "") 1467 (match_operand:TI 1 "register_operand" ""))] 1468 "TARGET_VX && reload_completed 1469 && GENERAL_REG_P (operands[0]) 1470 && VECTOR_REG_P (operands[1])" 1471 [(set (match_dup 2) (match_dup 4)) 1472 (set (match_dup 3) (unspec:DI [(match_dup 5) (const_int 1)] 1473 UNSPEC_VEC_EXTRACT))] 1474{ 1475 operands[2] = operand_subword (operands[0], 0, 0, TImode); 1476 operands[3] = operand_subword (operands[0], 1, 0, TImode); 1477 operands[4] = gen_rtx_REG (DImode, REGNO (operands[1])); 1478 operands[5] = gen_rtx_REG (V2DImode, REGNO (operands[1])); 1479}) 1480 1481; 1482; Patterns used for secondary reloads 1483; 1484 1485; z10 provides move instructions accepting larl memory operands. 1486; Unfortunately there is no such variant for QI, TI and FP mode moves. 1487; These patterns are also used for unaligned SI and DI accesses. 1488 1489(define_expand "reload<ALL:mode><P:mode>_tomem_z10" 1490 [(parallel [(match_operand:ALL 0 "memory_operand" "") 1491 (match_operand:ALL 1 "register_operand" "=d") 1492 (match_operand:P 2 "register_operand" "=&a")])] 1493 "TARGET_Z10" 1494{ 1495 s390_reload_symref_address (operands[1], operands[0], operands[2], 1); 1496 DONE; 1497}) 1498 1499(define_expand "reload<ALL:mode><P:mode>_toreg_z10" 1500 [(parallel [(match_operand:ALL 0 "register_operand" "=d") 1501 (match_operand:ALL 1 "memory_operand" "") 1502 (match_operand:P 2 "register_operand" "=a")])] 1503 "TARGET_Z10" 1504{ 1505 s390_reload_symref_address (operands[0], operands[1], operands[2], 0); 1506 DONE; 1507}) 1508 1509(define_expand "reload<P:mode>_larl_odd_addend_z10" 1510 [(parallel [(match_operand:P 0 "register_operand" "=d") 1511 (match_operand:P 1 "larl_operand" "") 1512 (match_operand:P 2 "register_operand" "=a")])] 1513 "TARGET_Z10" 1514{ 1515 s390_reload_larl_operand (operands[0], operands[1], operands[2]); 1516 DONE; 1517}) 1518 1519; Handles loading a PLUS (load address) expression 1520 1521(define_expand "reload<mode>_plus" 1522 [(parallel [(match_operand:P 0 "register_operand" "=a") 1523 (match_operand:P 1 "s390_plus_operand" "") 1524 (match_operand:P 2 "register_operand" "=&a")])] 1525 "" 1526{ 1527 s390_expand_plus_operand (operands[0], operands[1], operands[2]); 1528 DONE; 1529}) 1530 1531; Not all the indirect memory access instructions support the full 1532; format (long disp + index + base). So whenever a move from/to such 1533; an address is required and the instruction cannot deal with it we do 1534; a load address into a scratch register first and use this as the new 1535; base register. 1536; This in particular is used for: 1537; - non-offsetable memory accesses for multiword moves 1538; - full vector reg moves with long displacements 1539 1540(define_expand "reload<mode>_la_in" 1541 [(parallel [(match_operand 0 "register_operand" "") 1542 (match_operand 1 "" "") 1543 (match_operand:P 2 "register_operand" "=&a")])] 1544 "" 1545{ 1546 gcc_assert (MEM_P (operands[1])); 1547 s390_load_address (operands[2], find_replacement (&XEXP (operands[1], 0))); 1548 operands[1] = replace_equiv_address (operands[1], operands[2]); 1549 emit_move_insn (operands[0], operands[1]); 1550 DONE; 1551}) 1552 1553(define_expand "reload<mode>_la_out" 1554 [(parallel [(match_operand 0 "" "") 1555 (match_operand 1 "register_operand" "") 1556 (match_operand:P 2 "register_operand" "=&a")])] 1557 "" 1558{ 1559 gcc_assert (MEM_P (operands[0])); 1560 s390_load_address (operands[2], find_replacement (&XEXP (operands[0], 0))); 1561 operands[0] = replace_equiv_address (operands[0], operands[2]); 1562 emit_move_insn (operands[0], operands[1]); 1563 DONE; 1564}) 1565 1566(define_expand "reload<mode>_PIC_addr" 1567 [(parallel [(match_operand 0 "register_operand" "=d") 1568 (match_operand 1 "larl_operand" "") 1569 (match_operand:P 2 "register_operand" "=a")])] 1570 "" 1571{ 1572 rtx new_rtx = legitimize_pic_address (operands[1], operands[2]); 1573 emit_move_insn (operands[0], new_rtx); 1574}) 1575 1576; 1577; movdi instruction pattern(s). 1578; 1579 1580(define_expand "movdi" 1581 [(set (match_operand:DI 0 "general_operand" "") 1582 (match_operand:DI 1 "general_operand" ""))] 1583 "" 1584{ 1585 /* Handle symbolic constants. */ 1586 if (TARGET_64BIT 1587 && (SYMBOLIC_CONST (operands[1]) 1588 || (GET_CODE (operands[1]) == PLUS 1589 && XEXP (operands[1], 0) == pic_offset_table_rtx 1590 && SYMBOLIC_CONST (XEXP (operands[1], 1))))) 1591 emit_symbolic_move (operands); 1592}) 1593 1594(define_insn "*movdi_larl" 1595 [(set (match_operand:DI 0 "register_operand" "=d") 1596 (match_operand:DI 1 "larl_operand" "X"))] 1597 "TARGET_64BIT 1598 && !FP_REG_P (operands[0])" 1599 "larl\t%0,%1" 1600 [(set_attr "op_type" "RIL") 1601 (set_attr "type" "larl") 1602 (set_attr "z10prop" "z10_super_A1")]) 1603 1604(define_insn "*movdi_64" 1605 [(set (match_operand:DI 0 "nonimmediate_operand" 1606 "=d, d, d, d, d, d, d, d,f,d,d,d,d, d,RT,!*f,!*f,!*f,!R,!T,b,Q,d,t,Q,t,v,v,v,d, v,QR") 1607 (match_operand:DI 1 "general_operand" 1608 " K,N0HD0,N1HD0,N2HD0,N3HD0,Os,N0SD0,N1SD0,d,f,L,b,d,RT, d, *f, R, T,*f,*f,d,K,t,d,t,Q,K,v,d,v,QR, v"))] 1609 "TARGET_ZARCH" 1610 "@ 1611 lghi\t%0,%h1 1612 llihh\t%0,%i1 1613 llihl\t%0,%i1 1614 llilh\t%0,%i1 1615 llill\t%0,%i1 1616 lgfi\t%0,%1 1617 llihf\t%0,%k1 1618 llilf\t%0,%k1 1619 ldgr\t%0,%1 1620 lgdr\t%0,%1 1621 lay\t%0,%a1 1622 lgrl\t%0,%1 1623 lgr\t%0,%1 1624 lg\t%0,%1 1625 stg\t%1,%0 1626 ldr\t%0,%1 1627 ld\t%0,%1 1628 ldy\t%0,%1 1629 std\t%1,%0 1630 stdy\t%1,%0 1631 stgrl\t%1,%0 1632 mvghi\t%0,%1 1633 # 1634 # 1635 stam\t%1,%N1,%S0 1636 lam\t%0,%N0,%S1 1637 vleig\t%v0,%h1,0 1638 vlr\t%v0,%v1 1639 vlvgg\t%v0,%1,0 1640 vlgvg\t%0,%v1,0 1641 vleg\t%v0,%1,0 1642 vsteg\t%v1,%0,0" 1643 [(set_attr "op_type" "RI,RI,RI,RI,RI,RIL,RIL,RIL,RRE,RRE,RXY,RIL,RRE,RXY, 1644 RXY,RR,RX,RXY,RX,RXY,RIL,SIL,*,*,RS,RS,VRI,VRR,VRS,VRS,VRX,VRX") 1645 (set_attr "type" "*,*,*,*,*,*,*,*,floaddf,floaddf,la,larl,lr,load,store, 1646 floaddf,floaddf,floaddf,fstoredf,fstoredf,larl,*,*,*,*, 1647 *,*,*,*,*,*,*") 1648 (set_attr "cpu_facility" "*,*,*,*,*,extimm,extimm,extimm,dfp,dfp,longdisp, 1649 z10,*,*,*,*,*,longdisp,*,longdisp, 1650 z10,z10,*,*,*,*,vec,vec,vec,vec,vec,vec") 1651 (set_attr "z10prop" "z10_fwd_A1, 1652 z10_fwd_E1, 1653 z10_fwd_E1, 1654 z10_fwd_E1, 1655 z10_fwd_E1, 1656 z10_fwd_A1, 1657 z10_fwd_E1, 1658 z10_fwd_E1, 1659 *, 1660 *, 1661 z10_fwd_A1, 1662 z10_fwd_A3, 1663 z10_fr_E1, 1664 z10_fwd_A3, 1665 z10_rec, 1666 *, 1667 *, 1668 *, 1669 *, 1670 *, 1671 z10_rec, 1672 z10_super, 1673 *, 1674 *, 1675 *, 1676 *,*,*,*,*,*,*") 1677]) 1678 1679(define_split 1680 [(set (match_operand:DI 0 "register_operand" "") 1681 (match_operand:DI 1 "register_operand" ""))] 1682 "TARGET_ZARCH && ACCESS_REG_P (operands[1])" 1683 [(set (match_dup 2) (match_dup 3)) 1684 (set (match_dup 0) (ashift:DI (match_dup 0) (const_int 32))) 1685 (set (strict_low_part (match_dup 2)) (match_dup 4))] 1686 "operands[2] = gen_lowpart (SImode, operands[0]); 1687 s390_split_access_reg (operands[1], &operands[4], &operands[3]);") 1688 1689(define_split 1690 [(set (match_operand:DI 0 "register_operand" "") 1691 (match_operand:DI 1 "register_operand" ""))] 1692 "TARGET_ZARCH && ACCESS_REG_P (operands[0]) 1693 && dead_or_set_p (insn, operands[1])" 1694 [(set (match_dup 3) (match_dup 2)) 1695 (set (match_dup 1) (lshiftrt:DI (match_dup 1) (const_int 32))) 1696 (set (match_dup 4) (match_dup 2))] 1697 "operands[2] = gen_lowpart (SImode, operands[1]); 1698 s390_split_access_reg (operands[0], &operands[3], &operands[4]);") 1699 1700(define_split 1701 [(set (match_operand:DI 0 "register_operand" "") 1702 (match_operand:DI 1 "register_operand" ""))] 1703 "TARGET_ZARCH && ACCESS_REG_P (operands[0]) 1704 && !dead_or_set_p (insn, operands[1])" 1705 [(set (match_dup 3) (match_dup 2)) 1706 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32))) 1707 (set (match_dup 4) (match_dup 2)) 1708 (set (match_dup 1) (rotate:DI (match_dup 1) (const_int 32)))] 1709 "operands[2] = gen_lowpart (SImode, operands[1]); 1710 s390_split_access_reg (operands[0], &operands[3], &operands[4]);") 1711 1712(define_insn "*movdi_31" 1713 [(set (match_operand:DI 0 "nonimmediate_operand" 1714 "=d,d,Q,S,d ,o,!*f,!*f,!*f,!R,!T,d") 1715 (match_operand:DI 1 "general_operand" 1716 " Q,S,d,d,dPRT,d, *f, R, T,*f,*f,b"))] 1717 "!TARGET_ZARCH" 1718 "@ 1719 lm\t%0,%N0,%S1 1720 lmy\t%0,%N0,%S1 1721 stm\t%1,%N1,%S0 1722 stmy\t%1,%N1,%S0 1723 # 1724 # 1725 ldr\t%0,%1 1726 ld\t%0,%1 1727 ldy\t%0,%1 1728 std\t%1,%0 1729 stdy\t%1,%0 1730 #" 1731 [(set_attr "op_type" "RS,RSY,RS,RSY,*,*,RR,RX,RXY,RX,RXY,*") 1732 (set_attr "type" "lm,lm,stm,stm,*,*,floaddf,floaddf,floaddf,fstoredf,fstoredf,*") 1733 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,*,*,z10")]) 1734 1735; For a load from a symbol ref we can use one of the target registers 1736; together with larl to load the address. 1737(define_split 1738 [(set (match_operand:DI 0 "register_operand" "") 1739 (match_operand:DI 1 "memory_operand" ""))] 1740 "!TARGET_ZARCH && reload_completed && TARGET_Z10 1741 && larl_operand (XEXP (operands[1], 0), SImode)" 1742 [(set (match_dup 2) (match_dup 3)) 1743 (set (match_dup 0) (match_dup 1))] 1744{ 1745 operands[2] = operand_subword (operands[0], 1, 0, DImode); 1746 operands[3] = XEXP (operands[1], 0); 1747 operands[1] = replace_equiv_address (operands[1], operands[2]); 1748}) 1749 1750(define_split 1751 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1752 (match_operand:DI 1 "general_operand" ""))] 1753 "!TARGET_ZARCH && reload_completed 1754 && s390_split_ok_p (operands[0], operands[1], DImode, 0)" 1755 [(set (match_dup 2) (match_dup 4)) 1756 (set (match_dup 3) (match_dup 5))] 1757{ 1758 operands[2] = operand_subword (operands[0], 0, 0, DImode); 1759 operands[3] = operand_subword (operands[0], 1, 0, DImode); 1760 operands[4] = operand_subword (operands[1], 0, 0, DImode); 1761 operands[5] = operand_subword (operands[1], 1, 0, DImode); 1762}) 1763 1764(define_split 1765 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1766 (match_operand:DI 1 "general_operand" ""))] 1767 "!TARGET_ZARCH && reload_completed 1768 && s390_split_ok_p (operands[0], operands[1], DImode, 1)" 1769 [(set (match_dup 2) (match_dup 4)) 1770 (set (match_dup 3) (match_dup 5))] 1771{ 1772 operands[2] = operand_subword (operands[0], 1, 0, DImode); 1773 operands[3] = operand_subword (operands[0], 0, 0, DImode); 1774 operands[4] = operand_subword (operands[1], 1, 0, DImode); 1775 operands[5] = operand_subword (operands[1], 0, 0, DImode); 1776}) 1777 1778(define_split 1779 [(set (match_operand:DI 0 "register_operand" "") 1780 (match_operand:DI 1 "memory_operand" ""))] 1781 "!TARGET_ZARCH && reload_completed 1782 && !FP_REG_P (operands[0]) 1783 && !s_operand (operands[1], VOIDmode)" 1784 [(set (match_dup 0) (match_dup 1))] 1785{ 1786 rtx addr = operand_subword (operands[0], 1, 0, DImode); 1787 s390_load_address (addr, XEXP (operands[1], 0)); 1788 operands[1] = replace_equiv_address (operands[1], addr); 1789}) 1790 1791(define_peephole2 1792 [(set (match_operand:DI 0 "register_operand" "") 1793 (mem:DI (match_operand 1 "address_operand" "")))] 1794 "TARGET_ZARCH 1795 && !FP_REG_P (operands[0]) 1796 && GET_CODE (operands[1]) == SYMBOL_REF 1797 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1798 && get_pool_mode (operands[1]) == DImode 1799 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 1800 [(set (match_dup 0) (match_dup 2))] 1801 "operands[2] = get_pool_constant (operands[1]);") 1802 1803(define_insn "*la_64" 1804 [(set (match_operand:DI 0 "register_operand" "=d,d") 1805 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] 1806 "TARGET_64BIT" 1807 "@ 1808 la\t%0,%a1 1809 lay\t%0,%a1" 1810 [(set_attr "op_type" "RX,RXY") 1811 (set_attr "type" "la") 1812 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 1813 1814(define_peephole2 1815 [(parallel 1816 [(set (match_operand:DI 0 "register_operand" "") 1817 (match_operand:QI 1 "address_operand" "")) 1818 (clobber (reg:CC CC_REGNUM))])] 1819 "TARGET_64BIT 1820 && preferred_la_operand_p (operands[1], const0_rtx)" 1821 [(set (match_dup 0) (match_dup 1))] 1822 "") 1823 1824(define_peephole2 1825 [(set (match_operand:DI 0 "register_operand" "") 1826 (match_operand:DI 1 "register_operand" "")) 1827 (parallel 1828 [(set (match_dup 0) 1829 (plus:DI (match_dup 0) 1830 (match_operand:DI 2 "nonmemory_operand" ""))) 1831 (clobber (reg:CC CC_REGNUM))])] 1832 "TARGET_64BIT 1833 && !reg_overlap_mentioned_p (operands[0], operands[2]) 1834 && preferred_la_operand_p (operands[1], operands[2])" 1835 [(set (match_dup 0) (plus:DI (match_dup 1) (match_dup 2)))] 1836 "") 1837 1838; 1839; movsi instruction pattern(s). 1840; 1841 1842(define_expand "movsi" 1843 [(set (match_operand:SI 0 "general_operand" "") 1844 (match_operand:SI 1 "general_operand" ""))] 1845 "" 1846{ 1847 /* Handle symbolic constants. */ 1848 if (!TARGET_64BIT 1849 && (SYMBOLIC_CONST (operands[1]) 1850 || (GET_CODE (operands[1]) == PLUS 1851 && XEXP (operands[1], 0) == pic_offset_table_rtx 1852 && SYMBOLIC_CONST (XEXP(operands[1], 1))))) 1853 emit_symbolic_move (operands); 1854}) 1855 1856(define_insn "*movsi_larl" 1857 [(set (match_operand:SI 0 "register_operand" "=d") 1858 (match_operand:SI 1 "larl_operand" "X"))] 1859 "!TARGET_64BIT && TARGET_CPU_ZARCH 1860 && !FP_REG_P (operands[0])" 1861 "larl\t%0,%1" 1862 [(set_attr "op_type" "RIL") 1863 (set_attr "type" "larl") 1864 (set_attr "z10prop" "z10_fwd_A1")]) 1865 1866(define_insn "*movsi_zarch" 1867 [(set (match_operand:SI 0 "nonimmediate_operand" 1868 "=d, d, d, d,d,d,d,d,d,R,T,!*f,!*f,!*f,!*f,!*f,!R,!T,d,t,Q,b,Q,t,v,v,v,d, v,QR") 1869 (match_operand:SI 1 "general_operand" 1870 " K,N0HS0,N1HS0,Os,L,b,d,R,T,d,d, *f, *f, R, R, T,*f,*f,t,d,t,d,K,Q,K,v,d,v,QR, v"))] 1871 "TARGET_ZARCH" 1872 "@ 1873 lhi\t%0,%h1 1874 llilh\t%0,%i1 1875 llill\t%0,%i1 1876 iilf\t%0,%o1 1877 lay\t%0,%a1 1878 lrl\t%0,%1 1879 lr\t%0,%1 1880 l\t%0,%1 1881 ly\t%0,%1 1882 st\t%1,%0 1883 sty\t%1,%0 1884 lder\t%0,%1 1885 ler\t%0,%1 1886 lde\t%0,%1 1887 le\t%0,%1 1888 ley\t%0,%1 1889 ste\t%1,%0 1890 stey\t%1,%0 1891 ear\t%0,%1 1892 sar\t%0,%1 1893 stam\t%1,%1,%S0 1894 strl\t%1,%0 1895 mvhi\t%0,%1 1896 lam\t%0,%0,%S1 1897 vleif\t%v0,%h1,0 1898 vlr\t%v0,%v1 1899 vlvgf\t%v0,%1,0 1900 vlgvf\t%0,%v1,0 1901 vlef\t%v0,%1,0 1902 vstef\t%v1,%0,0" 1903 [(set_attr "op_type" "RI,RI,RI,RIL,RXY,RIL,RR,RX,RXY,RX,RXY, 1904 RRE,RR,RXE,RX,RXY,RX,RXY,RRE,RRE,RS,RIL,SIL,RS,VRI,VRR,VRS,VRS,VRX,VRX") 1905 (set_attr "type" "*, 1906 *, 1907 *, 1908 *, 1909 la, 1910 larl, 1911 lr, 1912 load, 1913 load, 1914 store, 1915 store, 1916 floadsf, 1917 floadsf, 1918 floadsf, 1919 floadsf, 1920 floadsf, 1921 fstoresf, 1922 fstoresf, 1923 *, 1924 *, 1925 *, 1926 larl, 1927 *, 1928 *,*,*,*,*,*,*") 1929 (set_attr "cpu_facility" "*,*,*,extimm,longdisp,z10,*,*,longdisp,*,longdisp, 1930 vec,*,vec,*,longdisp,*,longdisp,*,*,*,z10,z10,*,vec,vec,vec,vec,vec,vec") 1931 (set_attr "z10prop" "z10_fwd_A1, 1932 z10_fwd_E1, 1933 z10_fwd_E1, 1934 z10_fwd_A1, 1935 z10_fwd_A1, 1936 z10_fwd_A3, 1937 z10_fr_E1, 1938 z10_fwd_A3, 1939 z10_fwd_A3, 1940 z10_rec, 1941 z10_rec, 1942 *, 1943 *, 1944 *, 1945 *, 1946 *, 1947 *, 1948 *, 1949 z10_super_E1, 1950 z10_super, 1951 *, 1952 z10_rec, 1953 z10_super, 1954 *,*,*,*,*,*,*")]) 1955 1956(define_insn "*movsi_esa" 1957 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,R,!*f,!*f,!*f,!*f,!R,d,t,Q,t") 1958 (match_operand:SI 1 "general_operand" "K,d,R,d, *f, *f, R, R,*f,t,d,t,Q"))] 1959 "!TARGET_ZARCH" 1960 "@ 1961 lhi\t%0,%h1 1962 lr\t%0,%1 1963 l\t%0,%1 1964 st\t%1,%0 1965 lder\t%0,%1 1966 ler\t%0,%1 1967 lde\t%0,%1 1968 le\t%0,%1 1969 ste\t%1,%0 1970 ear\t%0,%1 1971 sar\t%0,%1 1972 stam\t%1,%1,%S0 1973 lam\t%0,%0,%S1" 1974 [(set_attr "op_type" "RI,RR,RX,RX,RRE,RR,RXE,RX,RX,RRE,RRE,RS,RS") 1975 (set_attr "type" "*,lr,load,store,floadsf,floadsf,floadsf,floadsf,fstoresf,*,*,*,*") 1976 (set_attr "z10prop" "z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_rec,*,*,*,*,*,z10_super_E1, 1977 z10_super,*,*") 1978 (set_attr "cpu_facility" "*,*,*,*,vec,*,vec,*,*,*,*,*,*") 1979]) 1980 1981(define_peephole2 1982 [(set (match_operand:SI 0 "register_operand" "") 1983 (mem:SI (match_operand 1 "address_operand" "")))] 1984 "!FP_REG_P (operands[0]) 1985 && GET_CODE (operands[1]) == SYMBOL_REF 1986 && CONSTANT_POOL_ADDRESS_P (operands[1]) 1987 && get_pool_mode (operands[1]) == SImode 1988 && legitimate_reload_constant_p (get_pool_constant (operands[1]))" 1989 [(set (match_dup 0) (match_dup 2))] 1990 "operands[2] = get_pool_constant (operands[1]);") 1991 1992(define_insn "*la_31" 1993 [(set (match_operand:SI 0 "register_operand" "=d,d") 1994 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT"))] 1995 "!TARGET_64BIT && legitimate_la_operand_p (operands[1])" 1996 "@ 1997 la\t%0,%a1 1998 lay\t%0,%a1" 1999 [(set_attr "op_type" "RX,RXY") 2000 (set_attr "type" "la") 2001 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2002 2003(define_peephole2 2004 [(parallel 2005 [(set (match_operand:SI 0 "register_operand" "") 2006 (match_operand:QI 1 "address_operand" "")) 2007 (clobber (reg:CC CC_REGNUM))])] 2008 "!TARGET_64BIT 2009 && preferred_la_operand_p (operands[1], const0_rtx)" 2010 [(set (match_dup 0) (match_dup 1))] 2011 "") 2012 2013(define_peephole2 2014 [(set (match_operand:SI 0 "register_operand" "") 2015 (match_operand:SI 1 "register_operand" "")) 2016 (parallel 2017 [(set (match_dup 0) 2018 (plus:SI (match_dup 0) 2019 (match_operand:SI 2 "nonmemory_operand" ""))) 2020 (clobber (reg:CC CC_REGNUM))])] 2021 "!TARGET_64BIT 2022 && !reg_overlap_mentioned_p (operands[0], operands[2]) 2023 && preferred_la_operand_p (operands[1], operands[2])" 2024 [(set (match_dup 0) (plus:SI (match_dup 1) (match_dup 2)))] 2025 "") 2026 2027(define_insn "*la_31_and" 2028 [(set (match_operand:SI 0 "register_operand" "=d,d") 2029 (and:SI (match_operand:QI 1 "address_operand" "ZQZR,ZSZT") 2030 (const_int 2147483647)))] 2031 "!TARGET_64BIT" 2032 "@ 2033 la\t%0,%a1 2034 lay\t%0,%a1" 2035 [(set_attr "op_type" "RX,RXY") 2036 (set_attr "type" "la") 2037 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2038 2039(define_insn_and_split "*la_31_and_cc" 2040 [(set (match_operand:SI 0 "register_operand" "=d") 2041 (and:SI (match_operand:QI 1 "address_operand" "p") 2042 (const_int 2147483647))) 2043 (clobber (reg:CC CC_REGNUM))] 2044 "!TARGET_64BIT" 2045 "#" 2046 "&& reload_completed" 2047 [(set (match_dup 0) 2048 (and:SI (match_dup 1) (const_int 2147483647)))] 2049 "" 2050 [(set_attr "op_type" "RX") 2051 (set_attr "type" "la")]) 2052 2053(define_insn "force_la_31" 2054 [(set (match_operand:SI 0 "register_operand" "=d,d") 2055 (match_operand:QI 1 "address_operand" "ZQZR,ZSZT")) 2056 (use (const_int 0))] 2057 "!TARGET_64BIT" 2058 "@ 2059 la\t%0,%a1 2060 lay\t%0,%a1" 2061 [(set_attr "op_type" "RX") 2062 (set_attr "type" "la") 2063 (set_attr "z10prop" "z10_fwd_A1,z10_fwd_A1")]) 2064 2065; 2066; movhi instruction pattern(s). 2067; 2068 2069(define_expand "movhi" 2070 [(set (match_operand:HI 0 "nonimmediate_operand" "") 2071 (match_operand:HI 1 "general_operand" ""))] 2072 "" 2073{ 2074 /* Make it explicit that loading a register from memory 2075 always sign-extends (at least) to SImode. */ 2076 if (optimize && can_create_pseudo_p () 2077 && register_operand (operands[0], VOIDmode) 2078 && GET_CODE (operands[1]) == MEM) 2079 { 2080 rtx tmp = gen_reg_rtx (SImode); 2081 rtx ext = gen_rtx_SIGN_EXTEND (SImode, operands[1]); 2082 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); 2083 operands[1] = gen_lowpart (HImode, tmp); 2084 } 2085}) 2086 2087(define_insn "*movhi" 2088 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d,d,d,R,T,b,Q,v,v,v,d, v,QR") 2089 (match_operand:HI 1 "general_operand" " d,n,R,T,b,d,d,d,K,K,v,d,v,QR, v"))] 2090 "" 2091 "@ 2092 lr\t%0,%1 2093 lhi\t%0,%h1 2094 lh\t%0,%1 2095 lhy\t%0,%1 2096 lhrl\t%0,%1 2097 sth\t%1,%0 2098 sthy\t%1,%0 2099 sthrl\t%1,%0 2100 mvhhi\t%0,%1 2101 vleih\t%v0,%h1,0 2102 vlr\t%v0,%v1 2103 vlvgh\t%v0,%1,0 2104 vlgvh\t%0,%v1,0 2105 vleh\t%v0,%1,0 2106 vsteh\t%v1,%0,0" 2107 [(set_attr "op_type" "RR,RI,RX,RXY,RIL,RX,RXY,RIL,SIL,VRI,VRR,VRS,VRS,VRX,VRX") 2108 (set_attr "type" "lr,*,*,*,larl,store,store,store,*,*,*,*,*,*,*") 2109 (set_attr "cpu_facility" "*,*,*,*,z10,*,*,z10,z10,vec,vec,vec,vec,vec,vec") 2110 (set_attr "z10prop" "z10_fr_E1, 2111 z10_fwd_A1, 2112 z10_super_E1, 2113 z10_super_E1, 2114 z10_super_E1, 2115 z10_rec, 2116 z10_rec, 2117 z10_rec, 2118 z10_super,*,*,*,*,*,*")]) 2119 2120(define_peephole2 2121 [(set (match_operand:HI 0 "register_operand" "") 2122 (mem:HI (match_operand 1 "address_operand" "")))] 2123 "GET_CODE (operands[1]) == SYMBOL_REF 2124 && CONSTANT_POOL_ADDRESS_P (operands[1]) 2125 && get_pool_mode (operands[1]) == HImode 2126 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 2127 [(set (match_dup 0) (match_dup 2))] 2128 "operands[2] = get_pool_constant (operands[1]);") 2129 2130; 2131; movqi instruction pattern(s). 2132; 2133 2134(define_expand "movqi" 2135 [(set (match_operand:QI 0 "nonimmediate_operand" "") 2136 (match_operand:QI 1 "general_operand" ""))] 2137 "" 2138{ 2139 /* On z/Architecture, zero-extending from memory to register 2140 is just as fast as a QImode load. */ 2141 if (TARGET_ZARCH && optimize && can_create_pseudo_p () 2142 && register_operand (operands[0], VOIDmode) 2143 && GET_CODE (operands[1]) == MEM) 2144 { 2145 rtx tmp = gen_reg_rtx (DImode); 2146 rtx ext = gen_rtx_ZERO_EXTEND (DImode, operands[1]); 2147 emit_insn (gen_rtx_SET (VOIDmode, tmp, ext)); 2148 operands[1] = gen_lowpart (QImode, tmp); 2149 } 2150}) 2151 2152(define_insn "*movqi" 2153 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,d,R,T,Q,S,?Q,v,v,v,d, v,QR") 2154 (match_operand:QI 1 "general_operand" " d,n,R,T,d,d,n,n,?Q,K,v,d,v,QR, v"))] 2155 "" 2156 "@ 2157 lr\t%0,%1 2158 lhi\t%0,%b1 2159 ic\t%0,%1 2160 icy\t%0,%1 2161 stc\t%1,%0 2162 stcy\t%1,%0 2163 mvi\t%S0,%b1 2164 mviy\t%S0,%b1 2165 # 2166 vleib\t%v0,%b1,0 2167 vlr\t%v0,%v1 2168 vlvgb\t%v0,%1,0 2169 vlgvb\t%0,%v1,0 2170 vleb\t%v0,%1,0 2171 vsteb\t%v1,%0,0" 2172 [(set_attr "op_type" "RR,RI,RX,RXY,RX,RXY,SI,SIY,SS,VRI,VRR,VRS,VRS,VRX,VRX") 2173 (set_attr "type" "lr,*,*,*,store,store,store,store,*,*,*,*,*,*,*") 2174 (set_attr "cpu_facility" "*,*,*,*,*,*,*,*,*,vec,vec,vec,vec,vec,vec") 2175 (set_attr "z10prop" "z10_fr_E1, 2176 z10_fwd_A1, 2177 z10_super_E1, 2178 z10_super_E1, 2179 z10_rec, 2180 z10_rec, 2181 z10_super, 2182 z10_super, 2183 *,*,*,*,*,*,*")]) 2184 2185(define_peephole2 2186 [(set (match_operand:QI 0 "nonimmediate_operand" "") 2187 (mem:QI (match_operand 1 "address_operand" "")))] 2188 "GET_CODE (operands[1]) == SYMBOL_REF 2189 && CONSTANT_POOL_ADDRESS_P (operands[1]) 2190 && get_pool_mode (operands[1]) == QImode 2191 && GET_CODE (get_pool_constant (operands[1])) == CONST_INT" 2192 [(set (match_dup 0) (match_dup 2))] 2193 "operands[2] = get_pool_constant (operands[1]);") 2194 2195; 2196; movstrictqi instruction pattern(s). 2197; 2198 2199(define_insn "*movstrictqi" 2200 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d,d")) 2201 (match_operand:QI 1 "memory_operand" "R,T"))] 2202 "" 2203 "@ 2204 ic\t%0,%1 2205 icy\t%0,%1" 2206 [(set_attr "op_type" "RX,RXY") 2207 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 2208 2209; 2210; movstricthi instruction pattern(s). 2211; 2212 2213(define_insn "*movstricthi" 2214 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d,d")) 2215 (match_operand:HI 1 "memory_operand" "Q,S")) 2216 (clobber (reg:CC CC_REGNUM))] 2217 "" 2218 "@ 2219 icm\t%0,3,%S1 2220 icmy\t%0,3,%S1" 2221 [(set_attr "op_type" "RS,RSY") 2222 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 2223 2224; 2225; movstrictsi instruction pattern(s). 2226; 2227 2228(define_insn "movstrictsi" 2229 [(set (strict_low_part (match_operand:SI 0 "register_operand" "+d,d,d,d")) 2230 (match_operand:SI 1 "general_operand" "d,R,T,t"))] 2231 "TARGET_ZARCH" 2232 "@ 2233 lr\t%0,%1 2234 l\t%0,%1 2235 ly\t%0,%1 2236 ear\t%0,%1" 2237 [(set_attr "op_type" "RR,RX,RXY,RRE") 2238 (set_attr "type" "lr,load,load,*") 2239 (set_attr "z10prop" "z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_super_E1")]) 2240 2241; 2242; mov(tf|td) instruction pattern(s). 2243; 2244 2245(define_expand "mov<mode>" 2246 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 2247 (match_operand:TD_TF 1 "general_operand" ""))] 2248 "" 2249 "") 2250 2251(define_insn "*mov<mode>_64" 2252 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o, d,QS, d,o") 2253 (match_operand:TD_TF 1 "general_operand" " G,f,o,f,QS, d,dRT,d"))] 2254 "TARGET_ZARCH" 2255 "@ 2256 lzxr\t%0 2257 lxr\t%0,%1 2258 # 2259 # 2260 lmg\t%0,%N0,%S1 2261 stmg\t%1,%N1,%S0 2262 # 2263 #" 2264 [(set_attr "op_type" "RRE,RRE,*,*,RSY,RSY,*,*") 2265 (set_attr "type" "fsimptf,fsimptf,*,*,lm,stm,*,*") 2266 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*")]) 2267 2268(define_insn "*mov<mode>_31" 2269 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "=f,f,f,o") 2270 (match_operand:TD_TF 1 "general_operand" " G,f,o,f"))] 2271 "!TARGET_ZARCH" 2272 "@ 2273 lzxr\t%0 2274 lxr\t%0,%1 2275 # 2276 #" 2277 [(set_attr "op_type" "RRE,RRE,*,*") 2278 (set_attr "type" "fsimptf,fsimptf,*,*") 2279 (set_attr "cpu_facility" "z196,*,*,*")]) 2280 2281; TFmode in GPRs splitters 2282 2283(define_split 2284 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 2285 (match_operand:TD_TF 1 "general_operand" ""))] 2286 "TARGET_ZARCH && reload_completed 2287 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" 2288 [(set (match_dup 2) (match_dup 4)) 2289 (set (match_dup 3) (match_dup 5))] 2290{ 2291 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 2292 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); 2293 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); 2294 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); 2295}) 2296 2297(define_split 2298 [(set (match_operand:TD_TF 0 "nonimmediate_operand" "") 2299 (match_operand:TD_TF 1 "general_operand" ""))] 2300 "TARGET_ZARCH && reload_completed 2301 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" 2302 [(set (match_dup 2) (match_dup 4)) 2303 (set (match_dup 3) (match_dup 5))] 2304{ 2305 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); 2306 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); 2307 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); 2308 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); 2309}) 2310 2311(define_split 2312 [(set (match_operand:TD_TF 0 "register_operand" "") 2313 (match_operand:TD_TF 1 "memory_operand" ""))] 2314 "TARGET_ZARCH && reload_completed 2315 && GENERAL_REG_P (operands[0]) 2316 && !s_operand (operands[1], VOIDmode)" 2317 [(set (match_dup 0) (match_dup 1))] 2318{ 2319 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); 2320 addr = gen_lowpart (Pmode, addr); 2321 s390_load_address (addr, XEXP (operands[1], 0)); 2322 operands[1] = replace_equiv_address (operands[1], addr); 2323}) 2324 2325; TFmode in BFPs splitters 2326 2327(define_split 2328 [(set (match_operand:TD_TF 0 "register_operand" "") 2329 (match_operand:TD_TF 1 "memory_operand" ""))] 2330 "reload_completed && offsettable_memref_p (operands[1]) 2331 && FP_REG_P (operands[0])" 2332 [(set (match_dup 2) (match_dup 4)) 2333 (set (match_dup 3) (match_dup 5))] 2334{ 2335 operands[2] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], 2336 <MODE>mode, 0); 2337 operands[3] = simplify_gen_subreg (<HALF_TMODE>mode, operands[0], 2338 <MODE>mode, 8); 2339 operands[4] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 0); 2340 operands[5] = adjust_address_nv (operands[1], <HALF_TMODE>mode, 8); 2341}) 2342 2343(define_split 2344 [(set (match_operand:TD_TF 0 "memory_operand" "") 2345 (match_operand:TD_TF 1 "register_operand" ""))] 2346 "reload_completed && offsettable_memref_p (operands[0]) 2347 && FP_REG_P (operands[1])" 2348 [(set (match_dup 2) (match_dup 4)) 2349 (set (match_dup 3) (match_dup 5))] 2350{ 2351 operands[2] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 0); 2352 operands[3] = adjust_address_nv (operands[0], <HALF_TMODE>mode, 8); 2353 operands[4] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], 2354 <MODE>mode, 0); 2355 operands[5] = simplify_gen_subreg (<HALF_TMODE>mode, operands[1], 2356 <MODE>mode, 8); 2357}) 2358 2359; 2360; mov(df|dd) instruction pattern(s). 2361; 2362 2363(define_expand "mov<mode>" 2364 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2365 (match_operand:DD_DF 1 "general_operand" ""))] 2366 "" 2367 "") 2368 2369(define_insn "*mov<mode>_64dfp" 2370 [(set (match_operand:DD_DF 0 "nonimmediate_operand" 2371 "=f,f,f,d,f,f,R,T,d,d,d, d,b,RT,v,v,d,v,QR") 2372 (match_operand:DD_DF 1 "general_operand" 2373 " G,f,d,f,R,T,f,f,G,d,b,RT,d, d,v,d,v,QR,v"))] 2374 "TARGET_DFP" 2375 "@ 2376 lzdr\t%0 2377 ldr\t%0,%1 2378 ldgr\t%0,%1 2379 lgdr\t%0,%1 2380 ld\t%0,%1 2381 ldy\t%0,%1 2382 std\t%1,%0 2383 stdy\t%1,%0 2384 lghi\t%0,0 2385 lgr\t%0,%1 2386 lgrl\t%0,%1 2387 lg\t%0,%1 2388 stgrl\t%1,%0 2389 stg\t%1,%0 2390 vlr\t%v0,%v1 2391 vlvgg\t%v0,%1,0 2392 vlgvg\t%0,%v1,0 2393 vleg\t%0,%1,0 2394 vsteg\t%1,%0,0" 2395 [(set_attr "op_type" "RRE,RR,RRE,RRE,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRS,VRS,VRX,VRX") 2396 (set_attr "type" "fsimpdf,floaddf,floaddf,floaddf,floaddf,floaddf, 2397 fstoredf,fstoredf,*,lr,load,load,store,store,*,*,*,load,store") 2398 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*,*,*") 2399 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec,vec,vec")]) 2400 2401(define_insn "*mov<mode>_64" 2402 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "=f,f,f,f,R,T,d,d,d, d,b,RT,v,v,QR") 2403 (match_operand:DD_DF 1 "general_operand" " G,f,R,T,f,f,G,d,b,RT,d, d,v,QR,v"))] 2404 "TARGET_ZARCH" 2405 "@ 2406 lzdr\t%0 2407 ldr\t%0,%1 2408 ld\t%0,%1 2409 ldy\t%0,%1 2410 std\t%1,%0 2411 stdy\t%1,%0 2412 lghi\t%0,0 2413 lgr\t%0,%1 2414 lgrl\t%0,%1 2415 lg\t%0,%1 2416 stgrl\t%1,%0 2417 stg\t%1,%0 2418 vlr\t%v0,%v1 2419 vleg\t%v0,%1,0 2420 vsteg\t%v1,%0,0" 2421 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RI,RRE,RIL,RXY,RIL,RXY,VRR,VRX,VRX") 2422 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, 2423 fstore<mode>,fstore<mode>,*,lr,load,load,store,store,*,load,store") 2424 (set_attr "z10prop" "*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,*,*,*") 2425 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,z10,*,z10,*,vec,vec,vec")]) 2426 2427(define_insn "*mov<mode>_31" 2428 [(set (match_operand:DD_DF 0 "nonimmediate_operand" 2429 "=f,f,f,f,R,T,d,d,Q,S, d,o") 2430 (match_operand:DD_DF 1 "general_operand" 2431 " G,f,R,T,f,f,Q,S,d,d,dPRT,d"))] 2432 "!TARGET_ZARCH" 2433 "@ 2434 lzdr\t%0 2435 ldr\t%0,%1 2436 ld\t%0,%1 2437 ldy\t%0,%1 2438 std\t%1,%0 2439 stdy\t%1,%0 2440 lm\t%0,%N0,%S1 2441 lmy\t%0,%N0,%S1 2442 stm\t%1,%N1,%S0 2443 stmy\t%1,%N1,%S0 2444 # 2445 #" 2446 [(set_attr "op_type" "RRE,RR,RX,RXY,RX,RXY,RS,RSY,RS,RSY,*,*") 2447 (set_attr "type" "fsimpdf,fload<mode>,fload<mode>,fload<mode>, 2448 fstore<mode>,fstore<mode>,lm,lm,stm,stm,*,*") 2449 (set_attr "cpu_facility" "z196,*,*,*,*,*,*,*,*,*,*,*")]) 2450 2451(define_split 2452 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2453 (match_operand:DD_DF 1 "general_operand" ""))] 2454 "!TARGET_ZARCH && reload_completed 2455 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 0)" 2456 [(set (match_dup 2) (match_dup 4)) 2457 (set (match_dup 3) (match_dup 5))] 2458{ 2459 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 2460 operands[3] = operand_subword (operands[0], 1, 0, <MODE>mode); 2461 operands[4] = operand_subword (operands[1], 0, 0, <MODE>mode); 2462 operands[5] = operand_subword (operands[1], 1, 0, <MODE>mode); 2463}) 2464 2465(define_split 2466 [(set (match_operand:DD_DF 0 "nonimmediate_operand" "") 2467 (match_operand:DD_DF 1 "general_operand" ""))] 2468 "!TARGET_ZARCH && reload_completed 2469 && s390_split_ok_p (operands[0], operands[1], <MODE>mode, 1)" 2470 [(set (match_dup 2) (match_dup 4)) 2471 (set (match_dup 3) (match_dup 5))] 2472{ 2473 operands[2] = operand_subword (operands[0], 1, 0, <MODE>mode); 2474 operands[3] = operand_subword (operands[0], 0, 0, <MODE>mode); 2475 operands[4] = operand_subword (operands[1], 1, 0, <MODE>mode); 2476 operands[5] = operand_subword (operands[1], 0, 0, <MODE>mode); 2477}) 2478 2479(define_split 2480 [(set (match_operand:DD_DF 0 "register_operand" "") 2481 (match_operand:DD_DF 1 "memory_operand" ""))] 2482 "!TARGET_ZARCH && reload_completed 2483 && !FP_REG_P (operands[0]) 2484 && !s_operand (operands[1], VOIDmode)" 2485 [(set (match_dup 0) (match_dup 1))] 2486{ 2487 rtx addr = operand_subword (operands[0], 1, 0, <MODE>mode); 2488 s390_load_address (addr, XEXP (operands[1], 0)); 2489 operands[1] = replace_equiv_address (operands[1], addr); 2490}) 2491 2492; 2493; mov(sf|sd) instruction pattern(s). 2494; 2495 2496(define_insn "mov<mode>" 2497 [(set (match_operand:SD_SF 0 "nonimmediate_operand" 2498 "=f,f,f,f,f,f,R,T,d,d,d,d,d,b,R,T,v,v,v,d,v,QR") 2499 (match_operand:SD_SF 1 "general_operand" 2500 " G,f,f,R,R,T,f,f,G,d,b,R,T,d,d,d,v,G,d,v,QR,v"))] 2501 "" 2502 "@ 2503 lzer\t%0 2504 lder\t%0,%1 2505 ler\t%0,%1 2506 lde\t%0,%1 2507 le\t%0,%1 2508 ley\t%0,%1 2509 ste\t%1,%0 2510 stey\t%1,%0 2511 lhi\t%0,0 2512 lr\t%0,%1 2513 lrl\t%0,%1 2514 l\t%0,%1 2515 ly\t%0,%1 2516 strl\t%1,%0 2517 st\t%1,%0 2518 sty\t%1,%0 2519 vlr\t%v0,%v1 2520 vleif\t%v0,0 2521 vlvgf\t%v0,%1,0 2522 vlgvf\t%0,%v1,0 2523 vleg\t%0,%1,0 2524 vsteg\t%1,%0,0" 2525 [(set_attr "op_type" "RRE,RRE,RR,RXE,RX,RXY,RX,RXY,RI,RR,RIL,RX,RXY,RIL,RX,RXY,VRR,VRI,VRS,VRS,VRX,VRX") 2526 (set_attr "type" "fsimpsf,fsimpsf,fload<mode>,fload<mode>,fload<mode>,fload<mode>, 2527 fstore<mode>,fstore<mode>,*,lr,load,load,load,store,store,store,*,*,*,*,load,store") 2528 (set_attr "z10prop" "*,*,*,*,*,*,*,*,z10_fwd_A1,z10_fr_E1,z10_fr_E1,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec,z10_rec,*,*,*,*,*,*") 2529 (set_attr "cpu_facility" "z196,vec,*,vec,*,*,*,*,*,*,z10,*,*,z10,*,*,vec,vec,vec,vec,vec,vec")]) 2530 2531; 2532; movcc instruction pattern 2533; 2534 2535(define_insn "movcc" 2536 [(set (match_operand:CC 0 "nonimmediate_operand" "=d,c,d,d,d,R,T") 2537 (match_operand:CC 1 "nonimmediate_operand" " d,d,c,R,T,d,d"))] 2538 "" 2539 "@ 2540 lr\t%0,%1 2541 tmh\t%1,12288 2542 ipm\t%0 2543 l\t%0,%1 2544 ly\t%0,%1 2545 st\t%1,%0 2546 sty\t%1,%0" 2547 [(set_attr "op_type" "RR,RI,RRE,RX,RXY,RX,RXY") 2548 (set_attr "type" "lr,*,*,load,load,store,store") 2549 (set_attr "z10prop" "z10_fr_E1,z10_super,*,z10_fwd_A3,z10_fwd_A3,z10_rec,z10_rec") 2550 (set_attr "z196prop" "*,*,z196_ends,*,*,*,*")]) 2551 2552; 2553; Block move (MVC) patterns. 2554; 2555 2556(define_insn "*mvc" 2557 [(set (match_operand:BLK 0 "memory_operand" "=Q") 2558 (match_operand:BLK 1 "memory_operand" "Q")) 2559 (use (match_operand 2 "const_int_operand" "n"))] 2560 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 2561 "mvc\t%O0(%2,%R0),%S1" 2562 [(set_attr "op_type" "SS")]) 2563 2564; This splitter converts a QI to QI mode copy into a BLK mode copy in 2565; order to have it implemented with mvc. 2566 2567(define_split 2568 [(set (match_operand:QI 0 "memory_operand" "") 2569 (match_operand:QI 1 "memory_operand" ""))] 2570 "reload_completed" 2571 [(parallel 2572 [(set (match_dup 0) (match_dup 1)) 2573 (use (const_int 1))])] 2574{ 2575 operands[0] = adjust_address (operands[0], BLKmode, 0); 2576 operands[1] = adjust_address (operands[1], BLKmode, 0); 2577}) 2578 2579 2580(define_peephole2 2581 [(parallel 2582 [(set (match_operand:BLK 0 "memory_operand" "") 2583 (match_operand:BLK 1 "memory_operand" "")) 2584 (use (match_operand 2 "const_int_operand" ""))]) 2585 (parallel 2586 [(set (match_operand:BLK 3 "memory_operand" "") 2587 (match_operand:BLK 4 "memory_operand" "")) 2588 (use (match_operand 5 "const_int_operand" ""))])] 2589 "s390_offset_p (operands[0], operands[3], operands[2]) 2590 && s390_offset_p (operands[1], operands[4], operands[2]) 2591 && !s390_overlap_p (operands[0], operands[1], 2592 INTVAL (operands[2]) + INTVAL (operands[5])) 2593 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 2594 [(parallel 2595 [(set (match_dup 6) (match_dup 7)) 2596 (use (match_dup 8))])] 2597 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 2598 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 2599 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 2600 2601 2602; 2603; load_multiple pattern(s). 2604; 2605; ??? Due to reload problems with replacing registers inside match_parallel 2606; we currently support load_multiple/store_multiple only after reload. 2607; 2608 2609(define_expand "load_multiple" 2610 [(match_par_dup 3 [(set (match_operand 0 "" "") 2611 (match_operand 1 "" "")) 2612 (use (match_operand 2 "" ""))])] 2613 "reload_completed" 2614{ 2615 machine_mode mode; 2616 int regno; 2617 int count; 2618 rtx from; 2619 int i, off; 2620 2621 /* Support only loading a constant number of fixed-point registers from 2622 memory and only bother with this if more than two */ 2623 if (GET_CODE (operands[2]) != CONST_INT 2624 || INTVAL (operands[2]) < 2 2625 || INTVAL (operands[2]) > 16 2626 || GET_CODE (operands[1]) != MEM 2627 || GET_CODE (operands[0]) != REG 2628 || REGNO (operands[0]) >= 16) 2629 FAIL; 2630 2631 count = INTVAL (operands[2]); 2632 regno = REGNO (operands[0]); 2633 mode = GET_MODE (operands[0]); 2634 if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) 2635 FAIL; 2636 2637 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 2638 if (!can_create_pseudo_p ()) 2639 { 2640 if (GET_CODE (XEXP (operands[1], 0)) == REG) 2641 { 2642 from = XEXP (operands[1], 0); 2643 off = 0; 2644 } 2645 else if (GET_CODE (XEXP (operands[1], 0)) == PLUS 2646 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == REG 2647 && GET_CODE (XEXP (XEXP (operands[1], 0), 1)) == CONST_INT) 2648 { 2649 from = XEXP (XEXP (operands[1], 0), 0); 2650 off = INTVAL (XEXP (XEXP (operands[1], 0), 1)); 2651 } 2652 else 2653 FAIL; 2654 } 2655 else 2656 { 2657 from = force_reg (Pmode, XEXP (operands[1], 0)); 2658 off = 0; 2659 } 2660 2661 for (i = 0; i < count; i++) 2662 XVECEXP (operands[3], 0, i) 2663 = gen_rtx_SET (VOIDmode, gen_rtx_REG (mode, regno + i), 2664 change_address (operands[1], mode, 2665 plus_constant (Pmode, from, 2666 off + i * GET_MODE_SIZE (mode)))); 2667}) 2668 2669(define_insn "*load_multiple_di" 2670 [(match_parallel 0 "load_multiple_operation" 2671 [(set (match_operand:DI 1 "register_operand" "=r") 2672 (match_operand:DI 2 "s_operand" "QS"))])] 2673 "reload_completed && TARGET_ZARCH" 2674{ 2675 int words = XVECLEN (operands[0], 0); 2676 operands[0] = gen_rtx_REG (DImode, REGNO (operands[1]) + words - 1); 2677 return "lmg\t%1,%0,%S2"; 2678} 2679 [(set_attr "op_type" "RSY") 2680 (set_attr "type" "lm")]) 2681 2682(define_insn "*load_multiple_si" 2683 [(match_parallel 0 "load_multiple_operation" 2684 [(set (match_operand:SI 1 "register_operand" "=r,r") 2685 (match_operand:SI 2 "s_operand" "Q,S"))])] 2686 "reload_completed" 2687{ 2688 int words = XVECLEN (operands[0], 0); 2689 operands[0] = gen_rtx_REG (SImode, REGNO (operands[1]) + words - 1); 2690 return which_alternative == 0 ? "lm\t%1,%0,%S2" : "lmy\t%1,%0,%S2"; 2691} 2692 [(set_attr "op_type" "RS,RSY") 2693 (set_attr "type" "lm")]) 2694 2695; 2696; store multiple pattern(s). 2697; 2698 2699(define_expand "store_multiple" 2700 [(match_par_dup 3 [(set (match_operand 0 "" "") 2701 (match_operand 1 "" "")) 2702 (use (match_operand 2 "" ""))])] 2703 "reload_completed" 2704{ 2705 machine_mode mode; 2706 int regno; 2707 int count; 2708 rtx to; 2709 int i, off; 2710 2711 /* Support only storing a constant number of fixed-point registers to 2712 memory and only bother with this if more than two. */ 2713 if (GET_CODE (operands[2]) != CONST_INT 2714 || INTVAL (operands[2]) < 2 2715 || INTVAL (operands[2]) > 16 2716 || GET_CODE (operands[0]) != MEM 2717 || GET_CODE (operands[1]) != REG 2718 || REGNO (operands[1]) >= 16) 2719 FAIL; 2720 2721 count = INTVAL (operands[2]); 2722 regno = REGNO (operands[1]); 2723 mode = GET_MODE (operands[1]); 2724 if (mode != SImode && (!TARGET_ZARCH || mode != DImode)) 2725 FAIL; 2726 2727 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 2728 2729 if (!can_create_pseudo_p ()) 2730 { 2731 if (GET_CODE (XEXP (operands[0], 0)) == REG) 2732 { 2733 to = XEXP (operands[0], 0); 2734 off = 0; 2735 } 2736 else if (GET_CODE (XEXP (operands[0], 0)) == PLUS 2737 && GET_CODE (XEXP (XEXP (operands[0], 0), 0)) == REG 2738 && GET_CODE (XEXP (XEXP (operands[0], 0), 1)) == CONST_INT) 2739 { 2740 to = XEXP (XEXP (operands[0], 0), 0); 2741 off = INTVAL (XEXP (XEXP (operands[0], 0), 1)); 2742 } 2743 else 2744 FAIL; 2745 } 2746 else 2747 { 2748 to = force_reg (Pmode, XEXP (operands[0], 0)); 2749 off = 0; 2750 } 2751 2752 for (i = 0; i < count; i++) 2753 XVECEXP (operands[3], 0, i) 2754 = gen_rtx_SET (VOIDmode, 2755 change_address (operands[0], mode, 2756 plus_constant (Pmode, to, 2757 off + i * GET_MODE_SIZE (mode))), 2758 gen_rtx_REG (mode, regno + i)); 2759}) 2760 2761(define_insn "*store_multiple_di" 2762 [(match_parallel 0 "store_multiple_operation" 2763 [(set (match_operand:DI 1 "s_operand" "=QS") 2764 (match_operand:DI 2 "register_operand" "r"))])] 2765 "reload_completed && TARGET_ZARCH" 2766{ 2767 int words = XVECLEN (operands[0], 0); 2768 operands[0] = gen_rtx_REG (DImode, REGNO (operands[2]) + words - 1); 2769 return "stmg\t%2,%0,%S1"; 2770} 2771 [(set_attr "op_type" "RSY") 2772 (set_attr "type" "stm")]) 2773 2774 2775(define_insn "*store_multiple_si" 2776 [(match_parallel 0 "store_multiple_operation" 2777 [(set (match_operand:SI 1 "s_operand" "=Q,S") 2778 (match_operand:SI 2 "register_operand" "r,r"))])] 2779 "reload_completed" 2780{ 2781 int words = XVECLEN (operands[0], 0); 2782 operands[0] = gen_rtx_REG (SImode, REGNO (operands[2]) + words - 1); 2783 return which_alternative == 0 ? "stm\t%2,%0,%S1" : "stmy\t%2,%0,%S1"; 2784} 2785 [(set_attr "op_type" "RS,RSY") 2786 (set_attr "type" "stm")]) 2787 2788;; 2789;; String instructions. 2790;; 2791 2792(define_insn "*execute_rl" 2793 [(match_parallel 0 "execute_operation" 2794 [(unspec [(match_operand 1 "register_operand" "a") 2795 (match_operand 2 "" "") 2796 (match_operand:SI 3 "larl_operand" "X")] UNSPEC_EXECUTE)])] 2797 "TARGET_Z10 && GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT 2798 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" 2799 "exrl\t%1,%3" 2800 [(set_attr "op_type" "RIL") 2801 (set_attr "type" "cs")]) 2802 2803(define_insn "*execute" 2804 [(match_parallel 0 "execute_operation" 2805 [(unspec [(match_operand 1 "register_operand" "a") 2806 (match_operand:BLK 2 "memory_operand" "R") 2807 (match_operand 3 "" "")] UNSPEC_EXECUTE)])] 2808 "GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT 2809 && GET_MODE_SIZE (GET_MODE (operands[1])) <= UNITS_PER_WORD" 2810 "ex\t%1,%2" 2811 [(set_attr "op_type" "RX") 2812 (set_attr "type" "cs")]) 2813 2814 2815; 2816; strlenM instruction pattern(s). 2817; 2818 2819(define_expand "strlen<mode>" 2820 [(match_operand:P 0 "register_operand" "") ; result 2821 (match_operand:BLK 1 "memory_operand" "") ; input string 2822 (match_operand:SI 2 "immediate_operand" "") ; search character 2823 (match_operand:SI 3 "immediate_operand" "")] ; known alignment 2824 "" 2825{ 2826 if (!TARGET_VX || operands[2] != const0_rtx) 2827 emit_insn (gen_strlen_srst<mode> (operands[0], operands[1], 2828 operands[2], operands[3])); 2829 else 2830 s390_expand_vec_strlen (operands[0], operands[1], operands[3]); 2831 2832 DONE; 2833}) 2834 2835(define_expand "strlen_srst<mode>" 2836 [(set (reg:SI 0) (match_operand:SI 2 "immediate_operand" "")) 2837 (parallel 2838 [(set (match_dup 4) 2839 (unspec:P [(const_int 0) 2840 (match_operand:BLK 1 "memory_operand" "") 2841 (reg:SI 0) 2842 (match_operand 3 "immediate_operand" "")] UNSPEC_SRST)) 2843 (clobber (scratch:P)) 2844 (clobber (reg:CC CC_REGNUM))]) 2845 (parallel 2846 [(set (match_operand:P 0 "register_operand" "") 2847 (minus:P (match_dup 4) (match_dup 5))) 2848 (clobber (reg:CC CC_REGNUM))])] 2849 "" 2850{ 2851 operands[4] = gen_reg_rtx (Pmode); 2852 operands[5] = gen_reg_rtx (Pmode); 2853 emit_move_insn (operands[5], force_operand (XEXP (operands[1], 0), NULL_RTX)); 2854 operands[1] = replace_equiv_address (operands[1], operands[5]); 2855}) 2856 2857(define_insn "*strlen<mode>" 2858 [(set (match_operand:P 0 "register_operand" "=a") 2859 (unspec:P [(match_operand:P 2 "general_operand" "0") 2860 (mem:BLK (match_operand:P 3 "register_operand" "1")) 2861 (reg:SI 0) 2862 (match_operand 4 "immediate_operand" "")] UNSPEC_SRST)) 2863 (clobber (match_scratch:P 1 "=a")) 2864 (clobber (reg:CC CC_REGNUM))] 2865 "" 2866 "srst\t%0,%1\;jo\t.-4" 2867 [(set_attr "length" "8") 2868 (set_attr "type" "vs")]) 2869 2870; 2871; cmpstrM instruction pattern(s). 2872; 2873 2874(define_expand "cmpstrsi" 2875 [(set (reg:SI 0) (const_int 0)) 2876 (parallel 2877 [(clobber (match_operand 3 "" "")) 2878 (clobber (match_dup 4)) 2879 (set (reg:CCU CC_REGNUM) 2880 (compare:CCU (match_operand:BLK 1 "memory_operand" "") 2881 (match_operand:BLK 2 "memory_operand" ""))) 2882 (use (reg:SI 0))]) 2883 (parallel 2884 [(set (match_operand:SI 0 "register_operand" "=d") 2885 (unspec:SI [(reg:CCU CC_REGNUM)] UNSPEC_STRCMPCC_TO_INT)) 2886 (clobber (reg:CC CC_REGNUM))])] 2887 "" 2888{ 2889 /* As the result of CMPINT is inverted compared to what we need, 2890 we have to swap the operands. */ 2891 rtx op1 = operands[2]; 2892 rtx op2 = operands[1]; 2893 rtx addr1 = gen_reg_rtx (Pmode); 2894 rtx addr2 = gen_reg_rtx (Pmode); 2895 2896 emit_move_insn (addr1, force_operand (XEXP (op1, 0), NULL_RTX)); 2897 emit_move_insn (addr2, force_operand (XEXP (op2, 0), NULL_RTX)); 2898 operands[1] = replace_equiv_address_nv (op1, addr1); 2899 operands[2] = replace_equiv_address_nv (op2, addr2); 2900 operands[3] = addr1; 2901 operands[4] = addr2; 2902}) 2903 2904(define_insn "*cmpstr<mode>" 2905 [(clobber (match_operand:P 0 "register_operand" "=d")) 2906 (clobber (match_operand:P 1 "register_operand" "=d")) 2907 (set (reg:CCU CC_REGNUM) 2908 (compare:CCU (mem:BLK (match_operand:P 2 "register_operand" "0")) 2909 (mem:BLK (match_operand:P 3 "register_operand" "1")))) 2910 (use (reg:SI 0))] 2911 "" 2912 "clst\t%0,%1\;jo\t.-4" 2913 [(set_attr "length" "8") 2914 (set_attr "type" "vs")]) 2915 2916; 2917; movstr instruction pattern. 2918; 2919 2920(define_expand "movstr" 2921 [(set (reg:SI 0) (const_int 0)) 2922 (parallel 2923 [(clobber (match_dup 3)) 2924 (set (match_operand:BLK 1 "memory_operand" "") 2925 (match_operand:BLK 2 "memory_operand" "")) 2926 (set (match_operand 0 "register_operand" "") 2927 (unspec [(match_dup 1) 2928 (match_dup 2) 2929 (reg:SI 0)] UNSPEC_MVST)) 2930 (clobber (reg:CC CC_REGNUM))])] 2931 "" 2932{ 2933 rtx addr1, addr2; 2934 2935 if (TARGET_VX && optimize_function_for_speed_p (cfun)) 2936 { 2937 s390_expand_vec_movstr (operands[0], operands[1], operands[2]); 2938 DONE; 2939 } 2940 2941 addr1 = gen_reg_rtx (Pmode); 2942 addr2 = gen_reg_rtx (Pmode); 2943 2944 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 2945 emit_move_insn (addr2, force_operand (XEXP (operands[2], 0), NULL_RTX)); 2946 operands[1] = replace_equiv_address_nv (operands[1], addr1); 2947 operands[2] = replace_equiv_address_nv (operands[2], addr2); 2948 operands[3] = addr2; 2949}) 2950 2951(define_insn "*movstr" 2952 [(clobber (match_operand:P 2 "register_operand" "=d")) 2953 (set (mem:BLK (match_operand:P 1 "register_operand" "0")) 2954 (mem:BLK (match_operand:P 3 "register_operand" "2"))) 2955 (set (match_operand:P 0 "register_operand" "=d") 2956 (unspec [(mem:BLK (match_dup 1)) 2957 (mem:BLK (match_dup 3)) 2958 (reg:SI 0)] UNSPEC_MVST)) 2959 (clobber (reg:CC CC_REGNUM))] 2960 "" 2961 "mvst\t%1,%2\;jo\t.-4" 2962 [(set_attr "length" "8") 2963 (set_attr "type" "vs")]) 2964 2965 2966; 2967; movmemM instruction pattern(s). 2968; 2969 2970(define_expand "movmem<mode>" 2971 [(set (match_operand:BLK 0 "memory_operand" "") ; destination 2972 (match_operand:BLK 1 "memory_operand" "")) ; source 2973 (use (match_operand:GPR 2 "general_operand" "")) ; count 2974 (match_operand 3 "" "")] 2975 "" 2976{ 2977 if (s390_expand_movmem (operands[0], operands[1], operands[2])) 2978 DONE; 2979 else 2980 FAIL; 2981}) 2982 2983; Move a block that is up to 256 bytes in length. 2984; The block length is taken as (operands[2] % 256) + 1. 2985 2986(define_expand "movmem_short" 2987 [(parallel 2988 [(set (match_operand:BLK 0 "memory_operand" "") 2989 (match_operand:BLK 1 "memory_operand" "")) 2990 (use (match_operand 2 "nonmemory_operand" "")) 2991 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 2992 (clobber (match_dup 3))])] 2993 "" 2994 "operands[3] = gen_rtx_SCRATCH (Pmode);") 2995 2996(define_insn "*movmem_short" 2997 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") 2998 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q")) 2999 (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) 3000 (use (match_operand 3 "immediate_operand" "X,R,X,X")) 3001 (clobber (match_scratch:P 4 "=X,X,X,&a"))] 3002 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" 3003 "#" 3004 [(set_attr "type" "cs") 3005 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) 3006 3007(define_split 3008 [(set (match_operand:BLK 0 "memory_operand" "") 3009 (match_operand:BLK 1 "memory_operand" "")) 3010 (use (match_operand 2 "const_int_operand" "")) 3011 (use (match_operand 3 "immediate_operand" "")) 3012 (clobber (scratch))] 3013 "reload_completed" 3014 [(parallel 3015 [(set (match_dup 0) (match_dup 1)) 3016 (use (match_dup 2))])] 3017 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") 3018 3019(define_split 3020 [(set (match_operand:BLK 0 "memory_operand" "") 3021 (match_operand:BLK 1 "memory_operand" "")) 3022 (use (match_operand 2 "register_operand" "")) 3023 (use (match_operand 3 "memory_operand" "")) 3024 (clobber (scratch))] 3025 "reload_completed" 3026 [(parallel 3027 [(unspec [(match_dup 2) (match_dup 3) 3028 (const_int 0)] UNSPEC_EXECUTE) 3029 (set (match_dup 0) (match_dup 1)) 3030 (use (const_int 1))])] 3031 "") 3032 3033(define_split 3034 [(set (match_operand:BLK 0 "memory_operand" "") 3035 (match_operand:BLK 1 "memory_operand" "")) 3036 (use (match_operand 2 "register_operand" "")) 3037 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3038 (clobber (scratch))] 3039 "TARGET_Z10 && reload_completed" 3040 [(parallel 3041 [(unspec [(match_dup 2) (const_int 0) 3042 (label_ref (match_dup 3))] UNSPEC_EXECUTE) 3043 (set (match_dup 0) (match_dup 1)) 3044 (use (const_int 1))])] 3045 "operands[3] = gen_label_rtx ();") 3046 3047(define_split 3048 [(set (match_operand:BLK 0 "memory_operand" "") 3049 (match_operand:BLK 1 "memory_operand" "")) 3050 (use (match_operand 2 "register_operand" "")) 3051 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3052 (clobber (match_operand 3 "register_operand" ""))] 3053 "reload_completed && TARGET_CPU_ZARCH" 3054 [(set (match_dup 3) (label_ref (match_dup 4))) 3055 (parallel 3056 [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) 3057 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3058 (set (match_dup 0) (match_dup 1)) 3059 (use (const_int 1))])] 3060 "operands[4] = gen_label_rtx ();") 3061 3062; Move a block of arbitrary length. 3063 3064(define_expand "movmem_long" 3065 [(parallel 3066 [(clobber (match_dup 2)) 3067 (clobber (match_dup 3)) 3068 (set (match_operand:BLK 0 "memory_operand" "") 3069 (match_operand:BLK 1 "memory_operand" "")) 3070 (use (match_operand 2 "general_operand" "")) 3071 (use (match_dup 3)) 3072 (clobber (reg:CC CC_REGNUM))])] 3073 "" 3074{ 3075 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; 3076 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; 3077 rtx reg0 = gen_reg_rtx (dreg_mode); 3078 rtx reg1 = gen_reg_rtx (dreg_mode); 3079 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); 3080 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); 3081 rtx len0 = gen_lowpart (Pmode, reg0); 3082 rtx len1 = gen_lowpart (Pmode, reg1); 3083 3084 emit_clobber (reg0); 3085 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3086 emit_move_insn (len0, operands[2]); 3087 3088 emit_clobber (reg1); 3089 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 3090 emit_move_insn (len1, operands[2]); 3091 3092 operands[0] = replace_equiv_address_nv (operands[0], addr0); 3093 operands[1] = replace_equiv_address_nv (operands[1], addr1); 3094 operands[2] = reg0; 3095 operands[3] = reg1; 3096}) 3097 3098(define_insn "*movmem_long" 3099 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3100 (clobber (match_operand:<DBL> 1 "register_operand" "=d")) 3101 (set (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) 3102 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0))) 3103 (use (match_dup 2)) 3104 (use (match_dup 3)) 3105 (clobber (reg:CC CC_REGNUM))] 3106 "TARGET_64BIT || !TARGET_ZARCH" 3107 "mvcle\t%0,%1,0\;jo\t.-4" 3108 [(set_attr "length" "8") 3109 (set_attr "type" "vs")]) 3110 3111(define_insn "*movmem_long_31z" 3112 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3113 (clobber (match_operand:TI 1 "register_operand" "=d")) 3114 (set (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) 3115 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4))) 3116 (use (match_dup 2)) 3117 (use (match_dup 3)) 3118 (clobber (reg:CC CC_REGNUM))] 3119 "!TARGET_64BIT && TARGET_ZARCH" 3120 "mvcle\t%0,%1,0\;jo\t.-4" 3121 [(set_attr "length" "8") 3122 (set_attr "type" "vs")]) 3123 3124 3125; 3126; Test data class. 3127; 3128 3129(define_expand "signbit<mode>2" 3130 [(set (reg:CCZ CC_REGNUM) 3131 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") 3132 (match_dup 2)] 3133 UNSPEC_TDC_INSN)) 3134 (set (match_operand:SI 0 "register_operand" "=d") 3135 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] 3136 "TARGET_HARD_FLOAT" 3137{ 3138 operands[2] = GEN_INT (S390_TDC_SIGNBIT_SET); 3139}) 3140 3141(define_expand "isinf<mode>2" 3142 [(set (reg:CCZ CC_REGNUM) 3143 (unspec:CCZ [(match_operand:FP_ALL 1 "register_operand" "f") 3144 (match_dup 2)] 3145 UNSPEC_TDC_INSN)) 3146 (set (match_operand:SI 0 "register_operand" "=d") 3147 (unspec:SI [(reg:CCZ CC_REGNUM)] UNSPEC_CC_TO_INT))] 3148 "TARGET_HARD_FLOAT" 3149{ 3150 operands[2] = GEN_INT (S390_TDC_INFINITY); 3151}) 3152 3153; This extracts CC into a GPR properly shifted. The actual IPM 3154; instruction will be issued by reload. The constraint of operand 1 3155; forces reload to use a GPR. So reload will issue a movcc insn for 3156; copying CC into a GPR first. 3157(define_insn_and_split "*cc_to_int" 3158 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3159 (unspec:SI [(match_operand 1 "register_operand" "0")] 3160 UNSPEC_CC_TO_INT))] 3161 "operands != NULL" 3162 "#" 3163 "reload_completed" 3164 [(set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 28)))]) 3165 3166; This insn is used to generate all variants of the Test Data Class 3167; instruction, namely tcxb, tcdb, and tceb. The insn's first operand 3168; is the register to be tested and the second one is the bit mask 3169; specifying the required test(s). 3170; 3171; tcxb, tcdb, tceb, tdcxt, tdcdt, tdcet 3172(define_insn "*TDC_insn_<mode>" 3173 [(set (reg:CCZ CC_REGNUM) 3174 (unspec:CCZ [(match_operand:FP_ALL 0 "register_operand" "f") 3175 (match_operand:SI 1 "const_int_operand")] UNSPEC_TDC_INSN))] 3176 "TARGET_HARD_FLOAT" 3177 "t<_d>c<xde><bt>\t%0,%1" 3178 [(set_attr "op_type" "RXE") 3179 (set_attr "type" "fsimp<mode>")]) 3180 3181 3182 3183; 3184; setmemM instruction pattern(s). 3185; 3186 3187(define_expand "setmem<mode>" 3188 [(set (match_operand:BLK 0 "memory_operand" "") 3189 (match_operand:QI 2 "general_operand" "")) 3190 (use (match_operand:GPR 1 "general_operand" "")) 3191 (match_operand 3 "" "")] 3192 "" 3193 "s390_expand_setmem (operands[0], operands[1], operands[2]); DONE;") 3194 3195; Clear a block that is up to 256 bytes in length. 3196; The block length is taken as (operands[1] % 256) + 1. 3197 3198(define_expand "clrmem_short" 3199 [(parallel 3200 [(set (match_operand:BLK 0 "memory_operand" "") 3201 (const_int 0)) 3202 (use (match_operand 1 "nonmemory_operand" "")) 3203 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3204 (clobber (match_dup 2)) 3205 (clobber (reg:CC CC_REGNUM))])] 3206 "" 3207 "operands[2] = gen_rtx_SCRATCH (Pmode);") 3208 3209(define_insn "*clrmem_short" 3210 [(set (match_operand:BLK 0 "memory_operand" "=Q,Q,Q,Q") 3211 (const_int 0)) 3212 (use (match_operand 1 "nonmemory_operand" "n,a,a,a")) 3213 (use (match_operand 2 "immediate_operand" "X,R,X,X")) 3214 (clobber (match_scratch:P 3 "=X,X,X,&a")) 3215 (clobber (reg:CC CC_REGNUM))] 3216 "(GET_MODE (operands[1]) == Pmode || GET_MODE (operands[1]) == VOIDmode)" 3217 "#" 3218 [(set_attr "type" "cs") 3219 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) 3220 3221(define_split 3222 [(set (match_operand:BLK 0 "memory_operand" "") 3223 (const_int 0)) 3224 (use (match_operand 1 "const_int_operand" "")) 3225 (use (match_operand 2 "immediate_operand" "")) 3226 (clobber (scratch)) 3227 (clobber (reg:CC CC_REGNUM))] 3228 "reload_completed" 3229 [(parallel 3230 [(set (match_dup 0) (const_int 0)) 3231 (use (match_dup 1)) 3232 (clobber (reg:CC CC_REGNUM))])] 3233 "operands[1] = GEN_INT ((INTVAL (operands[1]) & 0xff) + 1);") 3234 3235(define_split 3236 [(set (match_operand:BLK 0 "memory_operand" "") 3237 (const_int 0)) 3238 (use (match_operand 1 "register_operand" "")) 3239 (use (match_operand 2 "memory_operand" "")) 3240 (clobber (scratch)) 3241 (clobber (reg:CC CC_REGNUM))] 3242 "reload_completed" 3243 [(parallel 3244 [(unspec [(match_dup 1) (match_dup 2) 3245 (const_int 0)] UNSPEC_EXECUTE) 3246 (set (match_dup 0) (const_int 0)) 3247 (use (const_int 1)) 3248 (clobber (reg:CC CC_REGNUM))])] 3249 "") 3250 3251(define_split 3252 [(set (match_operand:BLK 0 "memory_operand" "") 3253 (const_int 0)) 3254 (use (match_operand 1 "register_operand" "")) 3255 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3256 (clobber (scratch)) 3257 (clobber (reg:CC CC_REGNUM))] 3258 "TARGET_Z10 && reload_completed" 3259 [(parallel 3260 [(unspec [(match_dup 1) (const_int 0) 3261 (label_ref (match_dup 3))] UNSPEC_EXECUTE) 3262 (set (match_dup 0) (const_int 0)) 3263 (use (const_int 1)) 3264 (clobber (reg:CC CC_REGNUM))])] 3265 "operands[3] = gen_label_rtx ();") 3266 3267(define_split 3268 [(set (match_operand:BLK 0 "memory_operand" "") 3269 (const_int 0)) 3270 (use (match_operand 1 "register_operand" "")) 3271 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3272 (clobber (match_operand 2 "register_operand" "")) 3273 (clobber (reg:CC CC_REGNUM))] 3274 "reload_completed && TARGET_CPU_ZARCH" 3275 [(set (match_dup 2) (label_ref (match_dup 3))) 3276 (parallel 3277 [(unspec [(match_dup 1) (mem:BLK (match_dup 2)) 3278 (label_ref (match_dup 3))] UNSPEC_EXECUTE) 3279 (set (match_dup 0) (const_int 0)) 3280 (use (const_int 1)) 3281 (clobber (reg:CC CC_REGNUM))])] 3282 "operands[3] = gen_label_rtx ();") 3283 3284; Initialize a block of arbitrary length with (operands[2] % 256). 3285 3286(define_expand "setmem_long" 3287 [(parallel 3288 [(clobber (match_dup 1)) 3289 (set (match_operand:BLK 0 "memory_operand" "") 3290 (match_operand 2 "shift_count_or_setmem_operand" "")) 3291 (use (match_operand 1 "general_operand" "")) 3292 (use (match_dup 3)) 3293 (clobber (reg:CC CC_REGNUM))])] 3294 "" 3295{ 3296 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; 3297 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; 3298 rtx reg0 = gen_reg_rtx (dreg_mode); 3299 rtx reg1 = gen_reg_rtx (dreg_mode); 3300 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); 3301 rtx len0 = gen_lowpart (Pmode, reg0); 3302 3303 emit_clobber (reg0); 3304 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3305 emit_move_insn (len0, operands[1]); 3306 3307 emit_move_insn (reg1, const0_rtx); 3308 3309 operands[0] = replace_equiv_address_nv (operands[0], addr0); 3310 operands[1] = reg0; 3311 operands[3] = reg1; 3312}) 3313 3314(define_insn "*setmem_long" 3315 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3316 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) 3317 (match_operand 2 "shift_count_or_setmem_operand" "Y")) 3318 (use (match_dup 3)) 3319 (use (match_operand:<DBL> 1 "register_operand" "d")) 3320 (clobber (reg:CC CC_REGNUM))] 3321 "TARGET_64BIT || !TARGET_ZARCH" 3322 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3323 [(set_attr "length" "8") 3324 (set_attr "type" "vs")]) 3325 3326(define_insn "*setmem_long_and" 3327 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3328 (set (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "0") 0)) 3329 (and (match_operand 2 "shift_count_or_setmem_operand" "Y") 3330 (match_operand 4 "const_int_operand" "n"))) 3331 (use (match_dup 3)) 3332 (use (match_operand:<DBL> 1 "register_operand" "d")) 3333 (clobber (reg:CC CC_REGNUM))] 3334 "(TARGET_64BIT || !TARGET_ZARCH) && 3335 (INTVAL (operands[4]) & 255) == 255" 3336 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3337 [(set_attr "length" "8") 3338 (set_attr "type" "vs")]) 3339 3340(define_insn "*setmem_long_31z" 3341 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3342 (set (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "0") 4)) 3343 (match_operand 2 "shift_count_or_setmem_operand" "Y")) 3344 (use (match_dup 3)) 3345 (use (match_operand:TI 1 "register_operand" "d")) 3346 (clobber (reg:CC CC_REGNUM))] 3347 "!TARGET_64BIT && TARGET_ZARCH" 3348 "mvcle\t%0,%1,%Y2\;jo\t.-4" 3349 [(set_attr "length" "8") 3350 (set_attr "type" "vs")]) 3351 3352; 3353; cmpmemM instruction pattern(s). 3354; 3355 3356(define_expand "cmpmemsi" 3357 [(set (match_operand:SI 0 "register_operand" "") 3358 (compare:SI (match_operand:BLK 1 "memory_operand" "") 3359 (match_operand:BLK 2 "memory_operand" "") ) ) 3360 (use (match_operand:SI 3 "general_operand" "")) 3361 (use (match_operand:SI 4 "" ""))] 3362 "" 3363{ 3364 if (s390_expand_cmpmem (operands[0], operands[1], 3365 operands[2], operands[3])) 3366 DONE; 3367 else 3368 FAIL; 3369}) 3370 3371; Compare a block that is up to 256 bytes in length. 3372; The block length is taken as (operands[2] % 256) + 1. 3373 3374(define_expand "cmpmem_short" 3375 [(parallel 3376 [(set (reg:CCU CC_REGNUM) 3377 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3378 (match_operand:BLK 1 "memory_operand" ""))) 3379 (use (match_operand 2 "nonmemory_operand" "")) 3380 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3381 (clobber (match_dup 3))])] 3382 "" 3383 "operands[3] = gen_rtx_SCRATCH (Pmode);") 3384 3385(define_insn "*cmpmem_short" 3386 [(set (reg:CCU CC_REGNUM) 3387 (compare:CCU (match_operand:BLK 0 "memory_operand" "Q,Q,Q,Q") 3388 (match_operand:BLK 1 "memory_operand" "Q,Q,Q,Q"))) 3389 (use (match_operand 2 "nonmemory_operand" "n,a,a,a")) 3390 (use (match_operand 3 "immediate_operand" "X,R,X,X")) 3391 (clobber (match_scratch:P 4 "=X,X,X,&a"))] 3392 "(GET_MODE (operands[2]) == Pmode || GET_MODE (operands[2]) == VOIDmode)" 3393 "#" 3394 [(set_attr "type" "cs") 3395 (set_attr "cpu_facility" "*,*,z10,cpu_zarch")]) 3396 3397(define_split 3398 [(set (reg:CCU CC_REGNUM) 3399 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3400 (match_operand:BLK 1 "memory_operand" ""))) 3401 (use (match_operand 2 "const_int_operand" "")) 3402 (use (match_operand 3 "immediate_operand" "")) 3403 (clobber (scratch))] 3404 "reload_completed" 3405 [(parallel 3406 [(set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3407 (use (match_dup 2))])] 3408 "operands[2] = GEN_INT ((INTVAL (operands[2]) & 0xff) + 1);") 3409 3410(define_split 3411 [(set (reg:CCU CC_REGNUM) 3412 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3413 (match_operand:BLK 1 "memory_operand" ""))) 3414 (use (match_operand 2 "register_operand" "")) 3415 (use (match_operand 3 "memory_operand" "")) 3416 (clobber (scratch))] 3417 "reload_completed" 3418 [(parallel 3419 [(unspec [(match_dup 2) (match_dup 3) 3420 (const_int 0)] UNSPEC_EXECUTE) 3421 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3422 (use (const_int 1))])] 3423 "") 3424 3425(define_split 3426 [(set (reg:CCU CC_REGNUM) 3427 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3428 (match_operand:BLK 1 "memory_operand" ""))) 3429 (use (match_operand 2 "register_operand" "")) 3430 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3431 (clobber (scratch))] 3432 "TARGET_Z10 && reload_completed" 3433 [(parallel 3434 [(unspec [(match_dup 2) (const_int 0) 3435 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3436 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3437 (use (const_int 1))])] 3438 "operands[4] = gen_label_rtx ();") 3439 3440(define_split 3441 [(set (reg:CCU CC_REGNUM) 3442 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3443 (match_operand:BLK 1 "memory_operand" ""))) 3444 (use (match_operand 2 "register_operand" "")) 3445 (use (const:BLK (unspec:BLK [(const_int 0)] UNSPEC_INSN))) 3446 (clobber (match_operand 3 "register_operand" ""))] 3447 "reload_completed && TARGET_CPU_ZARCH" 3448 [(set (match_dup 3) (label_ref (match_dup 4))) 3449 (parallel 3450 [(unspec [(match_dup 2) (mem:BLK (match_dup 3)) 3451 (label_ref (match_dup 4))] UNSPEC_EXECUTE) 3452 (set (reg:CCU CC_REGNUM) (compare:CCU (match_dup 0) (match_dup 1))) 3453 (use (const_int 1))])] 3454 "operands[4] = gen_label_rtx ();") 3455 3456; Compare a block of arbitrary length. 3457 3458(define_expand "cmpmem_long" 3459 [(parallel 3460 [(clobber (match_dup 2)) 3461 (clobber (match_dup 3)) 3462 (set (reg:CCU CC_REGNUM) 3463 (compare:CCU (match_operand:BLK 0 "memory_operand" "") 3464 (match_operand:BLK 1 "memory_operand" ""))) 3465 (use (match_operand 2 "general_operand" "")) 3466 (use (match_dup 3))])] 3467 "" 3468{ 3469 machine_mode sreg_mode = TARGET_ZARCH ? DImode : SImode; 3470 machine_mode dreg_mode = TARGET_ZARCH ? TImode : DImode; 3471 rtx reg0 = gen_reg_rtx (dreg_mode); 3472 rtx reg1 = gen_reg_rtx (dreg_mode); 3473 rtx addr0 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg0)); 3474 rtx addr1 = gen_lowpart (Pmode, gen_highpart (sreg_mode, reg1)); 3475 rtx len0 = gen_lowpart (Pmode, reg0); 3476 rtx len1 = gen_lowpart (Pmode, reg1); 3477 3478 emit_clobber (reg0); 3479 emit_move_insn (addr0, force_operand (XEXP (operands[0], 0), NULL_RTX)); 3480 emit_move_insn (len0, operands[2]); 3481 3482 emit_clobber (reg1); 3483 emit_move_insn (addr1, force_operand (XEXP (operands[1], 0), NULL_RTX)); 3484 emit_move_insn (len1, operands[2]); 3485 3486 operands[0] = replace_equiv_address_nv (operands[0], addr0); 3487 operands[1] = replace_equiv_address_nv (operands[1], addr1); 3488 operands[2] = reg0; 3489 operands[3] = reg1; 3490}) 3491 3492(define_insn "*cmpmem_long" 3493 [(clobber (match_operand:<DBL> 0 "register_operand" "=d")) 3494 (clobber (match_operand:<DBL> 1 "register_operand" "=d")) 3495 (set (reg:CCU CC_REGNUM) 3496 (compare:CCU (mem:BLK (subreg:P (match_operand:<DBL> 2 "register_operand" "0") 0)) 3497 (mem:BLK (subreg:P (match_operand:<DBL> 3 "register_operand" "1") 0)))) 3498 (use (match_dup 2)) 3499 (use (match_dup 3))] 3500 "TARGET_64BIT || !TARGET_ZARCH" 3501 "clcle\t%0,%1,0\;jo\t.-4" 3502 [(set_attr "length" "8") 3503 (set_attr "type" "vs")]) 3504 3505(define_insn "*cmpmem_long_31z" 3506 [(clobber (match_operand:TI 0 "register_operand" "=d")) 3507 (clobber (match_operand:TI 1 "register_operand" "=d")) 3508 (set (reg:CCU CC_REGNUM) 3509 (compare:CCU (mem:BLK (subreg:SI (match_operand:TI 2 "register_operand" "0") 4)) 3510 (mem:BLK (subreg:SI (match_operand:TI 3 "register_operand" "1") 4)))) 3511 (use (match_dup 2)) 3512 (use (match_dup 3))] 3513 "!TARGET_64BIT && TARGET_ZARCH" 3514 "clcle\t%0,%1,0\;jo\t.-4" 3515 [(set_attr "op_type" "NN") 3516 (set_attr "type" "vs") 3517 (set_attr "length" "8")]) 3518 3519; Convert CCUmode condition code to integer. 3520; Result is zero if EQ, positive if LTU, negative if GTU. 3521 3522(define_insn_and_split "cmpint" 3523 [(set (match_operand:SI 0 "register_operand" "=d") 3524 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3525 UNSPEC_STRCMPCC_TO_INT)) 3526 (clobber (reg:CC CC_REGNUM))] 3527 "" 3528 "#" 3529 "reload_completed" 3530 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) 3531 (parallel 3532 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30))) 3533 (clobber (reg:CC CC_REGNUM))])]) 3534 3535(define_insn_and_split "*cmpint_cc" 3536 [(set (reg CC_REGNUM) 3537 (compare (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3538 UNSPEC_STRCMPCC_TO_INT) 3539 (const_int 0))) 3540 (set (match_operand:SI 0 "register_operand" "=d") 3541 (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT))] 3542 "s390_match_ccmode (insn, CCSmode)" 3543 "#" 3544 "&& reload_completed" 3545 [(set (match_dup 0) (ashift:SI (match_dup 0) (const_int 2))) 3546 (parallel 3547 [(set (match_dup 2) (match_dup 3)) 3548 (set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 30)))])] 3549{ 3550 rtx result = gen_rtx_ASHIFTRT (SImode, operands[0], GEN_INT (30)); 3551 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); 3552 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); 3553}) 3554 3555(define_insn_and_split "*cmpint_sign" 3556 [(set (match_operand:DI 0 "register_operand" "=d") 3557 (sign_extend:DI (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3558 UNSPEC_STRCMPCC_TO_INT))) 3559 (clobber (reg:CC CC_REGNUM))] 3560 "TARGET_ZARCH" 3561 "#" 3562 "&& reload_completed" 3563 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) 3564 (parallel 3565 [(set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62))) 3566 (clobber (reg:CC CC_REGNUM))])]) 3567 3568(define_insn_and_split "*cmpint_sign_cc" 3569 [(set (reg CC_REGNUM) 3570 (compare (ashiftrt:DI (ashift:DI (subreg:DI 3571 (unspec:SI [(match_operand:CCU 1 "register_operand" "0")] 3572 UNSPEC_STRCMPCC_TO_INT) 0) 3573 (const_int 32)) (const_int 32)) 3574 (const_int 0))) 3575 (set (match_operand:DI 0 "register_operand" "=d") 3576 (sign_extend:DI (unspec:SI [(match_dup 1)] UNSPEC_STRCMPCC_TO_INT)))] 3577 "s390_match_ccmode (insn, CCSmode) && TARGET_ZARCH" 3578 "#" 3579 "&& reload_completed" 3580 [(set (match_dup 0) (ashift:DI (match_dup 0) (const_int 34))) 3581 (parallel 3582 [(set (match_dup 2) (match_dup 3)) 3583 (set (match_dup 0) (ashiftrt:DI (match_dup 0) (const_int 62)))])] 3584{ 3585 rtx result = gen_rtx_ASHIFTRT (DImode, operands[0], GEN_INT (62)); 3586 operands[2] = SET_DEST (XVECEXP (PATTERN (curr_insn), 0, 0)); 3587 operands[3] = gen_rtx_COMPARE (GET_MODE (operands[2]), result, const0_rtx); 3588}) 3589 3590 3591;; 3592;;- Conversion instructions. 3593;; 3594 3595(define_insn "*sethighpartsi" 3596 [(set (match_operand:SI 0 "register_operand" "=d,d") 3597 (unspec:SI [(match_operand:BLK 1 "s_operand" "Q,S") 3598 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) 3599 (clobber (reg:CC CC_REGNUM))] 3600 "" 3601 "@ 3602 icm\t%0,%2,%S1 3603 icmy\t%0,%2,%S1" 3604 [(set_attr "op_type" "RS,RSY") 3605 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 3606 3607(define_insn "*sethighpartdi_64" 3608 [(set (match_operand:DI 0 "register_operand" "=d") 3609 (unspec:DI [(match_operand:BLK 1 "s_operand" "QS") 3610 (match_operand 2 "const_int_operand" "n")] UNSPEC_ICM)) 3611 (clobber (reg:CC CC_REGNUM))] 3612 "TARGET_ZARCH" 3613 "icmh\t%0,%2,%S1" 3614 [(set_attr "op_type" "RSY") 3615 (set_attr "z10prop" "z10_super")]) 3616 3617(define_insn "*sethighpartdi_31" 3618 [(set (match_operand:DI 0 "register_operand" "=d,d") 3619 (unspec:DI [(match_operand:BLK 1 "s_operand" "Q,S") 3620 (match_operand 2 "const_int_operand" "n,n")] UNSPEC_ICM)) 3621 (clobber (reg:CC CC_REGNUM))] 3622 "!TARGET_ZARCH" 3623 "@ 3624 icm\t%0,%2,%S1 3625 icmy\t%0,%2,%S1" 3626 [(set_attr "op_type" "RS,RSY") 3627 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 3628 3629; 3630; extv instruction patterns 3631; 3632 3633; FIXME: This expander needs to be converted from DI to GPR as well 3634; after resolving some issues with it. 3635 3636(define_expand "extzv" 3637 [(parallel 3638 [(set (match_operand:DI 0 "register_operand" "=d") 3639 (zero_extract:DI 3640 (match_operand:DI 1 "register_operand" "d") 3641 (match_operand 2 "const_int_operand" "") ; size 3642 (match_operand 3 "const_int_operand" ""))) ; start 3643 (clobber (reg:CC CC_REGNUM))])] 3644 "TARGET_Z10" 3645{ 3646 /* Starting with zEC12 there is risbgn not clobbering CC. */ 3647 if (TARGET_ZEC12) 3648 { 3649 emit_move_insn (operands[0], 3650 gen_rtx_ZERO_EXTRACT (DImode, 3651 operands[1], 3652 operands[2], 3653 operands[3])); 3654 DONE; 3655 } 3656}) 3657 3658(define_insn "*extzv<mode>_zEC12" 3659 [(set (match_operand:GPR 0 "register_operand" "=d") 3660 (zero_extract:GPR 3661 (match_operand:GPR 1 "register_operand" "d") 3662 (match_operand 2 "const_int_operand" "") ; size 3663 (match_operand 3 "const_int_operand" "")))] ; start] 3664 "TARGET_ZEC12" 3665 "risbgn\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift 3666 [(set_attr "op_type" "RIE")]) 3667 3668(define_insn "*extzv<mode>_z10" 3669 [(set (match_operand:GPR 0 "register_operand" "=d") 3670 (zero_extract:GPR 3671 (match_operand:GPR 1 "register_operand" "d") 3672 (match_operand 2 "const_int_operand" "") ; size 3673 (match_operand 3 "const_int_operand" ""))) ; start 3674 (clobber (reg:CC CC_REGNUM))] 3675 "TARGET_Z10" 3676 "risbg\t%0,%1,64-%2,128+63,<bitsize>+%3+%2" ; dst, src, start, end, shift 3677 [(set_attr "op_type" "RIE") 3678 (set_attr "z10prop" "z10_super_E1")]) 3679 3680(define_insn_and_split "*pre_z10_extzv<mode>" 3681 [(set (match_operand:GPR 0 "register_operand" "=d") 3682 (zero_extract:GPR (match_operand:QI 1 "s_operand" "QS") 3683 (match_operand 2 "nonzero_shift_count_operand" "") 3684 (const_int 0))) 3685 (clobber (reg:CC CC_REGNUM))] 3686 "!TARGET_Z10" 3687 "#" 3688 "&& reload_completed" 3689 [(parallel 3690 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) 3691 (clobber (reg:CC CC_REGNUM))]) 3692 (set (match_dup 0) (lshiftrt:GPR (match_dup 0) (match_dup 2)))] 3693{ 3694 int bitsize = INTVAL (operands[2]); 3695 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ 3696 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); 3697 3698 operands[1] = adjust_address (operands[1], BLKmode, 0); 3699 set_mem_size (operands[1], size); 3700 operands[2] = GEN_INT (<GPR:bitsize> - bitsize); 3701 operands[3] = GEN_INT (mask); 3702}) 3703 3704(define_insn_and_split "*pre_z10_extv<mode>" 3705 [(set (match_operand:GPR 0 "register_operand" "=d") 3706 (sign_extract:GPR (match_operand:QI 1 "s_operand" "QS") 3707 (match_operand 2 "nonzero_shift_count_operand" "") 3708 (const_int 0))) 3709 (clobber (reg:CC CC_REGNUM))] 3710 "" 3711 "#" 3712 "&& reload_completed" 3713 [(parallel 3714 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (match_dup 3)] UNSPEC_ICM)) 3715 (clobber (reg:CC CC_REGNUM))]) 3716 (parallel 3717 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) 3718 (clobber (reg:CC CC_REGNUM))])] 3719{ 3720 int bitsize = INTVAL (operands[2]); 3721 int size = (bitsize - 1) / BITS_PER_UNIT + 1; /* round up */ 3722 int mask = ((1ul << size) - 1) << (GET_MODE_SIZE (SImode) - size); 3723 3724 operands[1] = adjust_address (operands[1], BLKmode, 0); 3725 set_mem_size (operands[1], size); 3726 operands[2] = GEN_INT (<GPR:bitsize> - bitsize); 3727 operands[3] = GEN_INT (mask); 3728}) 3729 3730; 3731; insv instruction patterns 3732; 3733 3734(define_expand "insv" 3735 [(set (zero_extract (match_operand 0 "nonimmediate_operand" "") 3736 (match_operand 1 "const_int_operand" "") 3737 (match_operand 2 "const_int_operand" "")) 3738 (match_operand 3 "general_operand" ""))] 3739 "" 3740{ 3741 if (s390_expand_insv (operands[0], operands[1], operands[2], operands[3])) 3742 DONE; 3743 FAIL; 3744}) 3745 3746 3747; The normal RTL expansion will never generate a zero_extract where 3748; the location operand isn't word mode. However, we do this in the 3749; back-end when generating atomic operations. See s390_two_part_insv. 3750(define_insn "*insv<mode>_zEC12" 3751 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") 3752 (match_operand 1 "const_int_operand" "I") ; size 3753 (match_operand 2 "const_int_operand" "I")) ; pos 3754 (match_operand:GPR 3 "nonimmediate_operand" "d"))] 3755 "TARGET_ZEC12 3756 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" 3757 "risbgn\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" 3758 [(set_attr "op_type" "RIE")]) 3759 3760(define_insn "*insv<mode>_z10" 3761 [(set (zero_extract:GPR (match_operand:GPR 0 "nonimmediate_operand" "+d") 3762 (match_operand 1 "const_int_operand" "I") ; size 3763 (match_operand 2 "const_int_operand" "I")) ; pos 3764 (match_operand:GPR 3 "nonimmediate_operand" "d")) 3765 (clobber (reg:CC CC_REGNUM))] 3766 "TARGET_Z10 3767 && (INTVAL (operands[1]) + INTVAL (operands[2])) <= <bitsize>" 3768 "risbg\t%0,%3,64-<bitsize>+%2,64-<bitsize>+%2+%1-1,<bitsize>-%2-%1" 3769 [(set_attr "op_type" "RIE") 3770 (set_attr "z10prop" "z10_super_E1")]) 3771 3772; and op1 with a mask being 1 for the selected bits and 0 for the rest 3773; and op3=op0 with a mask being 0 for the selected bits and 1 for the rest 3774(define_insn "*insv<mode>_zEC12_noshift" 3775 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 3776 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") 3777 (match_operand:GPR 2 "contiguous_bitmask_operand" "")) 3778 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") 3779 (match_operand:GPR 4 "const_int_operand" ""))))] 3780 "TARGET_ZEC12 && INTVAL (operands[2]) == ~INTVAL (operands[4])" 3781 "risbgn\t%0,%1,%<bfstart>2,%<bfend>2,0" 3782 [(set_attr "op_type" "RIE")]) 3783 3784(define_insn "*insv<mode>_z10_noshift" 3785 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 3786 (ior:GPR (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") 3787 (match_operand:GPR 2 "contiguous_bitmask_operand" "")) 3788 (and:GPR (match_operand:GPR 3 "nonimmediate_operand" "0") 3789 (match_operand:GPR 4 "const_int_operand" "")))) 3790 (clobber (reg:CC CC_REGNUM))] 3791 "TARGET_Z10 && INTVAL (operands[2]) == ~INTVAL (operands[4])" 3792 "risbg\t%0,%1,%<bfstart>2,%<bfend>2,0" 3793 [(set_attr "op_type" "RIE") 3794 (set_attr "z10prop" "z10_super_E1")]) 3795 3796(define_insn "*r<noxa>sbg_<mode>_noshift" 3797 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 3798 (IXOR:GPR 3799 (and:GPR (match_operand:GPR 1 "nonimmediate_operand" "d") 3800 (match_operand:GPR 2 "contiguous_bitmask_operand" "")) 3801 (match_operand:GPR 3 "nonimmediate_operand" "0"))) 3802 (clobber (reg:CC CC_REGNUM))] 3803 "TARGET_Z10" 3804 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,0" 3805 [(set_attr "op_type" "RIE")]) 3806 3807(define_insn "*r<noxa>sbg_di_rotl" 3808 [(set (match_operand:DI 0 "nonimmediate_operand" "=d") 3809 (IXOR:DI 3810 (and:DI 3811 (rotate:DI 3812 (match_operand:DI 1 "nonimmediate_operand" "d") 3813 (match_operand:DI 3 "const_int_operand" "")) 3814 (match_operand:DI 2 "contiguous_bitmask_operand" "")) 3815 (match_operand:DI 4 "nonimmediate_operand" "0"))) 3816 (clobber (reg:CC CC_REGNUM))] 3817 "TARGET_Z10" 3818 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%b3" 3819 [(set_attr "op_type" "RIE")]) 3820 3821(define_insn "*r<noxa>sbg_<mode>_srl" 3822 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 3823 (IXOR:GPR 3824 (and:GPR 3825 (lshiftrt:GPR 3826 (match_operand:GPR 1 "nonimmediate_operand" "d") 3827 (match_operand:GPR 3 "nonzero_shift_count_operand" "")) 3828 (match_operand:GPR 2 "contiguous_bitmask_operand" "")) 3829 (match_operand:GPR 4 "nonimmediate_operand" "0"))) 3830 (clobber (reg:CC CC_REGNUM))] 3831 "TARGET_Z10 3832 && s390_extzv_shift_ok (<bitsize>, 64 - INTVAL (operands[3]), 3833 INTVAL (operands[2]))" 3834 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,64-%3" 3835 [(set_attr "op_type" "RIE")]) 3836 3837(define_insn "*r<noxa>sbg_<mode>_sll" 3838 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d") 3839 (IXOR:GPR 3840 (and:GPR 3841 (ashift:GPR 3842 (match_operand:GPR 1 "nonimmediate_operand" "d") 3843 (match_operand:GPR 3 "nonzero_shift_count_operand" "")) 3844 (match_operand:GPR 2 "contiguous_bitmask_operand" "")) 3845 (match_operand:GPR 4 "nonimmediate_operand" "0"))) 3846 (clobber (reg:CC CC_REGNUM))] 3847 "TARGET_Z10 3848 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[3]), 3849 INTVAL (operands[2]))" 3850 "r<noxa>sbg\t%0,%1,%<bfstart>2,%<bfend>2,%3" 3851 [(set_attr "op_type" "RIE")]) 3852 3853;; These two are generated by combine for s.bf &= val. 3854;; ??? For bitfields smaller than 32-bits, we wind up with SImode 3855;; shifts and ands, which results in some truly awful patterns 3856;; including subregs of operations. Rather unnecessisarily, IMO. 3857;; Instead of 3858;; 3859;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) 3860;; (const_int 24 [0x18]) 3861;; (const_int 0 [0])) 3862;; (subreg:DI (and:SI (subreg:SI (lshiftrt:DI (reg/v:DI 50 [ s ]) 3863;; (const_int 40 [0x28])) 4) 3864;; (reg:SI 4 %r4 [ y+4 ])) 0)) 3865;; 3866;; we should instead generate 3867;; 3868;; (set (zero_extract:DI (reg/v:DI 50 [ s ]) 3869;; (const_int 24 [0x18]) 3870;; (const_int 0 [0])) 3871;; (and:DI (lshiftrt:DI (reg/v:DI 50 [ s ]) 3872;; (const_int 40 [0x28])) 3873;; (subreg:DI (reg:SI 4 %r4 [ y+4 ]) 0))) 3874;; 3875;; by noticing that we can push down the outer paradoxical subreg 3876;; into the operation. 3877 3878(define_insn "*insv_rnsbg_noshift" 3879 [(set (zero_extract:DI 3880 (match_operand:DI 0 "nonimmediate_operand" "+d") 3881 (match_operand 1 "const_int_operand" "") 3882 (match_operand 2 "const_int_operand" "")) 3883 (and:DI 3884 (match_dup 0) 3885 (match_operand:DI 3 "nonimmediate_operand" "d"))) 3886 (clobber (reg:CC CC_REGNUM))] 3887 "TARGET_Z10 3888 && INTVAL (operands[1]) + INTVAL (operands[2]) == 64" 3889 "rnsbg\t%0,%3,%2,63,0" 3890 [(set_attr "op_type" "RIE")]) 3891 3892(define_insn "*insv_rnsbg_srl" 3893 [(set (zero_extract:DI 3894 (match_operand:DI 0 "nonimmediate_operand" "+d") 3895 (match_operand 1 "const_int_operand" "") 3896 (match_operand 2 "const_int_operand" "")) 3897 (and:DI 3898 (lshiftrt:DI 3899 (match_dup 0) 3900 (match_operand 3 "const_int_operand" "")) 3901 (match_operand:DI 4 "nonimmediate_operand" "d"))) 3902 (clobber (reg:CC CC_REGNUM))] 3903 "TARGET_Z10 3904 && INTVAL (operands[3]) == 64 - INTVAL (operands[1]) - INTVAL (operands[2])" 3905 "rnsbg\t%0,%4,%2,%2+%1-1,%3" 3906 [(set_attr "op_type" "RIE")]) 3907 3908(define_insn "*insv<mode>_mem_reg" 3909 [(set (zero_extract:W (match_operand:QI 0 "memory_operand" "+Q,S") 3910 (match_operand 1 "const_int_operand" "n,n") 3911 (const_int 0)) 3912 (match_operand:W 2 "register_operand" "d,d"))] 3913 "INTVAL (operands[1]) > 0 3914 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) 3915 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" 3916{ 3917 int size = INTVAL (operands[1]) / BITS_PER_UNIT; 3918 3919 operands[1] = GEN_INT ((1ul << size) - 1); 3920 return (which_alternative == 0) ? "stcm\t%2,%1,%S0" 3921 : "stcmy\t%2,%1,%S0"; 3922} 3923 [(set_attr "op_type" "RS,RSY") 3924 (set_attr "z10prop" "z10_super,z10_super")]) 3925 3926(define_insn "*insvdi_mem_reghigh" 3927 [(set (zero_extract:DI (match_operand:QI 0 "memory_operand" "+QS") 3928 (match_operand 1 "const_int_operand" "n") 3929 (const_int 0)) 3930 (lshiftrt:DI (match_operand:DI 2 "register_operand" "d") 3931 (const_int 32)))] 3932 "TARGET_ZARCH 3933 && INTVAL (operands[1]) > 0 3934 && INTVAL (operands[1]) <= GET_MODE_BITSIZE (SImode) 3935 && INTVAL (operands[1]) % BITS_PER_UNIT == 0" 3936{ 3937 int size = INTVAL (operands[1]) / BITS_PER_UNIT; 3938 3939 operands[1] = GEN_INT ((1ul << size) - 1); 3940 return "stcmh\t%2,%1,%S0"; 3941} 3942[(set_attr "op_type" "RSY") 3943 (set_attr "z10prop" "z10_super")]) 3944 3945(define_insn "*insvdi_reg_imm" 3946 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 3947 (const_int 16) 3948 (match_operand 1 "const_int_operand" "n")) 3949 (match_operand:DI 2 "const_int_operand" "n"))] 3950 "TARGET_ZARCH 3951 && INTVAL (operands[1]) >= 0 3952 && INTVAL (operands[1]) < BITS_PER_WORD 3953 && INTVAL (operands[1]) % 16 == 0" 3954{ 3955 switch (BITS_PER_WORD - INTVAL (operands[1])) 3956 { 3957 case 64: return "iihh\t%0,%x2"; break; 3958 case 48: return "iihl\t%0,%x2"; break; 3959 case 32: return "iilh\t%0,%x2"; break; 3960 case 16: return "iill\t%0,%x2"; break; 3961 default: gcc_unreachable(); 3962 } 3963} 3964 [(set_attr "op_type" "RI") 3965 (set_attr "z10prop" "z10_super_E1")]) 3966 3967; Update the left-most 32 bit of a DI. 3968(define_insn "*insv_h_di_reg_extimm" 3969 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 3970 (const_int 32) 3971 (const_int 0)) 3972 (match_operand:DI 1 "const_int_operand" "n"))] 3973 "TARGET_EXTIMM" 3974 "iihf\t%0,%o1" 3975 [(set_attr "op_type" "RIL") 3976 (set_attr "z10prop" "z10_fwd_E1")]) 3977 3978; Update the right-most 32 bit of a DI. 3979(define_insn "*insv_l_di_reg_extimm" 3980 [(set (zero_extract:DI (match_operand:DI 0 "register_operand" "+d") 3981 (const_int 32) 3982 (const_int 32)) 3983 (match_operand:DI 1 "const_int_operand" "n"))] 3984 "TARGET_EXTIMM" 3985 "iilf\t%0,%o1" 3986 [(set_attr "op_type" "RIL") 3987 (set_attr "z10prop" "z10_fwd_A1")]) 3988 3989; 3990; extendsidi2 instruction pattern(s). 3991; 3992 3993(define_expand "extendsidi2" 3994 [(set (match_operand:DI 0 "register_operand" "") 3995 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 3996 "" 3997{ 3998 if (!TARGET_ZARCH) 3999 { 4000 emit_clobber (operands[0]); 4001 emit_move_insn (gen_highpart (SImode, operands[0]), operands[1]); 4002 emit_move_insn (gen_lowpart (SImode, operands[0]), const0_rtx); 4003 emit_insn (gen_ashrdi3 (operands[0], operands[0], GEN_INT (32))); 4004 DONE; 4005 } 4006}) 4007 4008(define_insn "*extendsidi2" 4009 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4010 (sign_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] 4011 "TARGET_ZARCH" 4012 "@ 4013 lgfr\t%0,%1 4014 lgf\t%0,%1 4015 lgfrl\t%0,%1" 4016 [(set_attr "op_type" "RRE,RXY,RIL") 4017 (set_attr "type" "*,*,larl") 4018 (set_attr "cpu_facility" "*,*,z10") 4019 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) 4020 4021; 4022; extend(hi|qi)(si|di)2 instruction pattern(s). 4023; 4024 4025(define_expand "extend<HQI:mode><DSI:mode>2" 4026 [(set (match_operand:DSI 0 "register_operand" "") 4027 (sign_extend:DSI (match_operand:HQI 1 "nonimmediate_operand" "")))] 4028 "" 4029{ 4030 if (<DSI:MODE>mode == DImode && !TARGET_ZARCH) 4031 { 4032 rtx tmp = gen_reg_rtx (SImode); 4033 emit_insn (gen_extend<HQI:mode>si2 (tmp, operands[1])); 4034 emit_insn (gen_extendsidi2 (operands[0], tmp)); 4035 DONE; 4036 } 4037 else if (!TARGET_EXTIMM) 4038 { 4039 rtx bitcount = GEN_INT (<DSI:bitsize> - <HQI:bitsize>); 4040 4041 operands[1] = gen_lowpart (<DSI:MODE>mode, operands[1]); 4042 emit_insn (gen_ashl<DSI:mode>3 (operands[0], operands[1], bitcount)); 4043 emit_insn (gen_ashr<DSI:mode>3 (operands[0], operands[0], bitcount)); 4044 DONE; 4045 } 4046}) 4047 4048; 4049; extendhidi2 instruction pattern(s). 4050; 4051 4052(define_insn "*extendhidi2_extimm" 4053 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4054 (sign_extend:DI (match_operand:HI 1 "general_operand" "d,RT,b")))] 4055 "TARGET_ZARCH && TARGET_EXTIMM" 4056 "@ 4057 lghr\t%0,%1 4058 lgh\t%0,%1 4059 lghrl\t%0,%1" 4060 [(set_attr "op_type" "RRE,RXY,RIL") 4061 (set_attr "type" "*,*,larl") 4062 (set_attr "cpu_facility" "extimm,extimm,z10") 4063 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1")]) 4064 4065(define_insn "*extendhidi2" 4066 [(set (match_operand:DI 0 "register_operand" "=d") 4067 (sign_extend:DI (match_operand:HI 1 "memory_operand" "RT")))] 4068 "TARGET_ZARCH" 4069 "lgh\t%0,%1" 4070 [(set_attr "op_type" "RXY") 4071 (set_attr "z10prop" "z10_super_E1")]) 4072 4073; 4074; extendhisi2 instruction pattern(s). 4075; 4076 4077(define_insn "*extendhisi2_extimm" 4078 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d") 4079 (sign_extend:SI (match_operand:HI 1 "nonimmediate_operand" " d,R,T,b")))] 4080 "TARGET_EXTIMM" 4081 "@ 4082 lhr\t%0,%1 4083 lh\t%0,%1 4084 lhy\t%0,%1 4085 lhrl\t%0,%1" 4086 [(set_attr "op_type" "RRE,RX,RXY,RIL") 4087 (set_attr "type" "*,*,*,larl") 4088 (set_attr "cpu_facility" "extimm,extimm,extimm,z10") 4089 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1,z10_super_E1")]) 4090 4091(define_insn "*extendhisi2" 4092 [(set (match_operand:SI 0 "register_operand" "=d,d") 4093 (sign_extend:SI (match_operand:HI 1 "memory_operand" "R,T")))] 4094 "!TARGET_EXTIMM" 4095 "@ 4096 lh\t%0,%1 4097 lhy\t%0,%1" 4098 [(set_attr "op_type" "RX,RXY") 4099 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4100 4101; 4102; extendqi(si|di)2 instruction pattern(s). 4103; 4104 4105; lbr, lgbr, lb, lgb 4106(define_insn "*extendqi<mode>2_extimm" 4107 [(set (match_operand:GPR 0 "register_operand" "=d,d") 4108 (sign_extend:GPR (match_operand:QI 1 "nonimmediate_operand" "d,RT")))] 4109 "TARGET_EXTIMM" 4110 "@ 4111 l<g>br\t%0,%1 4112 l<g>b\t%0,%1" 4113 [(set_attr "op_type" "RRE,RXY") 4114 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4115 4116; lb, lgb 4117(define_insn "*extendqi<mode>2" 4118 [(set (match_operand:GPR 0 "register_operand" "=d") 4119 (sign_extend:GPR (match_operand:QI 1 "memory_operand" "RT")))] 4120 "!TARGET_EXTIMM && TARGET_LONG_DISPLACEMENT" 4121 "l<g>b\t%0,%1" 4122 [(set_attr "op_type" "RXY") 4123 (set_attr "z10prop" "z10_super_E1")]) 4124 4125(define_insn_and_split "*extendqi<mode>2_short_displ" 4126 [(set (match_operand:GPR 0 "register_operand" "=d") 4127 (sign_extend:GPR (match_operand:QI 1 "s_operand" "Q"))) 4128 (clobber (reg:CC CC_REGNUM))] 4129 "!TARGET_EXTIMM && !TARGET_LONG_DISPLACEMENT" 4130 "#" 4131 "&& reload_completed" 4132 [(parallel 4133 [(set (match_dup 0) (unspec:GPR [(match_dup 1) (const_int 8)] UNSPEC_ICM)) 4134 (clobber (reg:CC CC_REGNUM))]) 4135 (parallel 4136 [(set (match_dup 0) (ashiftrt:GPR (match_dup 0) (match_dup 2))) 4137 (clobber (reg:CC CC_REGNUM))])] 4138{ 4139 operands[1] = adjust_address (operands[1], BLKmode, 0); 4140 set_mem_size (operands[1], GET_MODE_SIZE (QImode)); 4141 operands[2] = GEN_INT (<GPR:bitsize> - BITS_PER_UNIT); 4142}) 4143 4144; 4145; zero_extendsidi2 instruction pattern(s). 4146; 4147 4148(define_expand "zero_extendsidi2" 4149 [(set (match_operand:DI 0 "register_operand" "") 4150 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "")))] 4151 "" 4152{ 4153 if (!TARGET_ZARCH) 4154 { 4155 emit_clobber (operands[0]); 4156 emit_move_insn (gen_lowpart (SImode, operands[0]), operands[1]); 4157 emit_move_insn (gen_highpart (SImode, operands[0]), const0_rtx); 4158 DONE; 4159 } 4160}) 4161 4162(define_insn "*zero_extendsidi2" 4163 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 4164 (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "d,RT,b")))] 4165 "TARGET_ZARCH" 4166 "@ 4167 llgfr\t%0,%1 4168 llgf\t%0,%1 4169 llgfrl\t%0,%1" 4170 [(set_attr "op_type" "RRE,RXY,RIL") 4171 (set_attr "type" "*,*,larl") 4172 (set_attr "cpu_facility" "*,*,z10") 4173 (set_attr "z10prop" "z10_fwd_E1,z10_fwd_A3,z10_fwd_A3")]) 4174 4175; 4176; LLGT-type instructions (zero-extend from 31 bit to 64 bit). 4177; 4178 4179(define_insn "*llgt_sidi" 4180 [(set (match_operand:DI 0 "register_operand" "=d") 4181 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) 4182 (const_int 2147483647)))] 4183 "TARGET_ZARCH" 4184 "llgt\t%0,%1" 4185 [(set_attr "op_type" "RXE") 4186 (set_attr "z10prop" "z10_super_E1")]) 4187 4188(define_insn_and_split "*llgt_sidi_split" 4189 [(set (match_operand:DI 0 "register_operand" "=d") 4190 (and:DI (subreg:DI (match_operand:SI 1 "memory_operand" "RT") 0) 4191 (const_int 2147483647))) 4192 (clobber (reg:CC CC_REGNUM))] 4193 "TARGET_ZARCH" 4194 "#" 4195 "&& reload_completed" 4196 [(set (match_dup 0) 4197 (and:DI (subreg:DI (match_dup 1) 0) 4198 (const_int 2147483647)))] 4199 "") 4200 4201(define_insn "*llgt_sisi" 4202 [(set (match_operand:SI 0 "register_operand" "=d,d") 4203 (and:SI (match_operand:SI 1 "nonimmediate_operand" "d,RT") 4204 (const_int 2147483647)))] 4205 "TARGET_ZARCH" 4206 "@ 4207 llgtr\t%0,%1 4208 llgt\t%0,%1" 4209 [(set_attr "op_type" "RRE,RXE") 4210 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4211 4212(define_insn "*llgt_didi" 4213 [(set (match_operand:DI 0 "register_operand" "=d,d") 4214 (and:DI (match_operand:DI 1 "nonimmediate_operand" "d,o") 4215 (const_int 2147483647)))] 4216 "TARGET_ZARCH" 4217 "@ 4218 llgtr\t%0,%1 4219 llgt\t%0,%N1" 4220 [(set_attr "op_type" "RRE,RXE") 4221 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 4222 4223(define_split 4224 [(set (match_operand:DSI 0 "register_operand" "") 4225 (and:DSI (match_operand:DSI 1 "nonimmediate_operand" "") 4226 (const_int 2147483647))) 4227 (clobber (reg:CC CC_REGNUM))] 4228 "TARGET_ZARCH && reload_completed" 4229 [(set (match_dup 0) 4230 (and:DSI (match_dup 1) 4231 (const_int 2147483647)))] 4232 "") 4233 4234; 4235; zero_extend(hi|qi)(si|di)2 instruction pattern(s). 4236; 4237 4238(define_expand "zero_extend<mode>di2" 4239 [(set (match_operand:DI 0 "register_operand" "") 4240 (zero_extend:DI (match_operand:HQI 1 "nonimmediate_operand" "")))] 4241 "" 4242{ 4243 if (!TARGET_ZARCH) 4244 { 4245 rtx tmp = gen_reg_rtx (SImode); 4246 emit_insn (gen_zero_extend<mode>si2 (tmp, operands[1])); 4247 emit_insn (gen_zero_extendsidi2 (operands[0], tmp)); 4248 DONE; 4249 } 4250 else if (!TARGET_EXTIMM) 4251 { 4252 rtx bitcount = GEN_INT (64 - <HQI:bitsize>); 4253 operands[1] = gen_lowpart (DImode, operands[1]); 4254 emit_insn (gen_ashldi3 (operands[0], operands[1], bitcount)); 4255 emit_insn (gen_lshrdi3 (operands[0], operands[0], bitcount)); 4256 DONE; 4257 } 4258}) 4259 4260(define_expand "zero_extend<mode>si2" 4261 [(set (match_operand:SI 0 "register_operand" "") 4262 (zero_extend:SI (match_operand:HQI 1 "nonimmediate_operand" "")))] 4263 "" 4264{ 4265 if (!TARGET_EXTIMM) 4266 { 4267 operands[1] = gen_lowpart (SImode, operands[1]); 4268 emit_insn (gen_andsi3 (operands[0], operands[1], 4269 GEN_INT ((1 << <HQI:bitsize>) - 1))); 4270 DONE; 4271 } 4272}) 4273 4274; llhrl, llghrl 4275(define_insn "*zero_extendhi<mode>2_z10" 4276 [(set (match_operand:GPR 0 "register_operand" "=d,d,d") 4277 (zero_extend:GPR (match_operand:HI 1 "nonimmediate_operand" "d,RT,b")))] 4278 "TARGET_Z10" 4279 "@ 4280 ll<g>hr\t%0,%1 4281 ll<g>h\t%0,%1 4282 ll<g>hrl\t%0,%1" 4283 [(set_attr "op_type" "RXY,RRE,RIL") 4284 (set_attr "type" "*,*,larl") 4285 (set_attr "cpu_facility" "*,*,z10") 4286 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3,z10_fwd_A3")]) 4287 4288; llhr, llcr, llghr, llgcr, llh, llc, llgh, llgc 4289(define_insn "*zero_extend<HQI:mode><GPR:mode>2_extimm" 4290 [(set (match_operand:GPR 0 "register_operand" "=d,d") 4291 (zero_extend:GPR (match_operand:HQI 1 "nonimmediate_operand" "d,RT")))] 4292 "TARGET_EXTIMM" 4293 "@ 4294 ll<g><hc>r\t%0,%1 4295 ll<g><hc>\t%0,%1" 4296 [(set_attr "op_type" "RRE,RXY") 4297 (set_attr "z10prop" "z10_super_E1,z10_fwd_A3")]) 4298 4299; llgh, llgc 4300(define_insn "*zero_extend<HQI:mode><GPR:mode>2" 4301 [(set (match_operand:GPR 0 "register_operand" "=d") 4302 (zero_extend:GPR (match_operand:HQI 1 "memory_operand" "RT")))] 4303 "TARGET_ZARCH && !TARGET_EXTIMM" 4304 "llg<hc>\t%0,%1" 4305 [(set_attr "op_type" "RXY") 4306 (set_attr "z10prop" "z10_fwd_A3")]) 4307 4308(define_insn_and_split "*zero_extendhisi2_31" 4309 [(set (match_operand:SI 0 "register_operand" "=&d") 4310 (zero_extend:SI (match_operand:HI 1 "s_operand" "QS"))) 4311 (clobber (reg:CC CC_REGNUM))] 4312 "!TARGET_ZARCH" 4313 "#" 4314 "&& reload_completed" 4315 [(set (match_dup 0) (const_int 0)) 4316 (parallel 4317 [(set (strict_low_part (match_dup 2)) (match_dup 1)) 4318 (clobber (reg:CC CC_REGNUM))])] 4319 "operands[2] = gen_lowpart (HImode, operands[0]);") 4320 4321(define_insn_and_split "*zero_extendqisi2_31" 4322 [(set (match_operand:SI 0 "register_operand" "=&d") 4323 (zero_extend:SI (match_operand:QI 1 "memory_operand" "RT")))] 4324 "!TARGET_ZARCH" 4325 "#" 4326 "&& reload_completed" 4327 [(set (match_dup 0) (const_int 0)) 4328 (set (strict_low_part (match_dup 2)) (match_dup 1))] 4329 "operands[2] = gen_lowpart (QImode, operands[0]);") 4330 4331; 4332; zero_extendqihi2 instruction pattern(s). 4333; 4334 4335(define_expand "zero_extendqihi2" 4336 [(set (match_operand:HI 0 "register_operand" "") 4337 (zero_extend:HI (match_operand:QI 1 "register_operand" "")))] 4338 "TARGET_ZARCH && !TARGET_EXTIMM" 4339{ 4340 operands[1] = gen_lowpart (HImode, operands[1]); 4341 emit_insn (gen_andhi3 (operands[0], operands[1], GEN_INT (0xff))); 4342 DONE; 4343}) 4344 4345(define_insn "*zero_extendqihi2_64" 4346 [(set (match_operand:HI 0 "register_operand" "=d") 4347 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] 4348 "TARGET_ZARCH && !TARGET_EXTIMM" 4349 "llgc\t%0,%1" 4350 [(set_attr "op_type" "RXY") 4351 (set_attr "z10prop" "z10_fwd_A3")]) 4352 4353(define_insn_and_split "*zero_extendqihi2_31" 4354 [(set (match_operand:HI 0 "register_operand" "=&d") 4355 (zero_extend:HI (match_operand:QI 1 "memory_operand" "RT")))] 4356 "!TARGET_ZARCH" 4357 "#" 4358 "&& reload_completed" 4359 [(set (match_dup 0) (const_int 0)) 4360 (set (strict_low_part (match_dup 2)) (match_dup 1))] 4361 "operands[2] = gen_lowpart (QImode, operands[0]);") 4362 4363; 4364; fixuns_trunc(dd|td)di2 instruction pattern(s). 4365; 4366 4367(define_expand "fixuns_truncdddi2" 4368 [(parallel 4369 [(set (match_operand:DI 0 "register_operand" "") 4370 (unsigned_fix:DI (match_operand:DD 1 "register_operand" ""))) 4371 (unspec:DI [(const_int 5)] UNSPEC_ROUND) 4372 (clobber (reg:CC CC_REGNUM))])] 4373 4374 "TARGET_HARD_DFP" 4375{ 4376 if (!TARGET_Z196) 4377 { 4378 rtx_code_label *label1 = gen_label_rtx (); 4379 rtx_code_label *label2 = gen_label_rtx (); 4380 rtx temp = gen_reg_rtx (TDmode); 4381 REAL_VALUE_TYPE cmp, sub; 4382 4383 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ 4384 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ 4385 4386 /* 2^63 can't be represented as 64bit DFP number with full precision. The 4387 solution is doing the check and the subtraction in TD mode and using a 4388 TD -> DI convert afterwards. */ 4389 emit_insn (gen_extendddtd2 (temp, operands[1])); 4390 temp = force_reg (TDmode, temp); 4391 emit_cmp_and_jump_insns (temp, 4392 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), 4393 LT, NULL_RTX, VOIDmode, 0, label1); 4394 emit_insn (gen_subtd3 (temp, temp, 4395 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); 4396 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); 4397 emit_jump (label2); 4398 4399 emit_label (label1); 4400 emit_insn (gen_fix_truncdddi2_dfp (operands[0], operands[1], GEN_INT (9))); 4401 emit_label (label2); 4402 DONE; 4403 } 4404}) 4405 4406(define_expand "fixuns_trunctddi2" 4407 [(parallel 4408 [(set (match_operand:DI 0 "register_operand" "") 4409 (unsigned_fix:DI (match_operand:TD 1 "register_operand" ""))) 4410 (unspec:DI [(const_int 5)] UNSPEC_ROUND) 4411 (clobber (reg:CC CC_REGNUM))])] 4412 4413 "TARGET_HARD_DFP" 4414{ 4415 if (!TARGET_Z196) 4416 { 4417 rtx_code_label *label1 = gen_label_rtx (); 4418 rtx_code_label *label2 = gen_label_rtx (); 4419 rtx temp = gen_reg_rtx (TDmode); 4420 REAL_VALUE_TYPE cmp, sub; 4421 4422 operands[1] = force_reg (TDmode, operands[1]); 4423 decimal_real_from_string (&cmp, "9223372036854775808.0"); /* 2^63 */ 4424 decimal_real_from_string (&sub, "18446744073709551616.0"); /* 2^64 */ 4425 4426 emit_cmp_and_jump_insns (operands[1], 4427 CONST_DOUBLE_FROM_REAL_VALUE (cmp, TDmode), 4428 LT, NULL_RTX, VOIDmode, 0, label1); 4429 emit_insn (gen_subtd3 (temp, operands[1], 4430 CONST_DOUBLE_FROM_REAL_VALUE (sub, TDmode))); 4431 emit_insn (gen_fix_trunctddi2_dfp (operands[0], temp, GEN_INT (11))); 4432 emit_jump (label2); 4433 4434 emit_label (label1); 4435 emit_insn (gen_fix_trunctddi2_dfp (operands[0], operands[1], GEN_INT (9))); 4436 emit_label (label2); 4437 DONE; 4438 } 4439}) 4440 4441; 4442; fixuns_trunc(sf|df|tf)(si|di)2 and fix_trunc(sf|df|tf)(si|di)2 4443; instruction pattern(s). 4444; 4445 4446(define_expand "fixuns_trunc<BFP:mode><GPR:mode>2" 4447 [(parallel 4448 [(set (match_operand:GPR 0 "register_operand" "") 4449 (unsigned_fix:GPR (match_operand:BFP 1 "register_operand" ""))) 4450 (unspec:GPR [(const_int 5)] UNSPEC_ROUND) 4451 (clobber (reg:CC CC_REGNUM))])] 4452 "TARGET_HARD_FLOAT" 4453{ 4454 if (!TARGET_Z196) 4455 { 4456 rtx_code_label *label1 = gen_label_rtx (); 4457 rtx_code_label *label2 = gen_label_rtx (); 4458 rtx temp = gen_reg_rtx (<BFP:MODE>mode); 4459 REAL_VALUE_TYPE cmp, sub; 4460 4461 operands[1] = force_reg (<BFP:MODE>mode, operands[1]); 4462 real_2expN (&cmp, <GPR:bitsize> - 1, <BFP:MODE>mode); 4463 real_2expN (&sub, <GPR:bitsize>, <BFP:MODE>mode); 4464 4465 emit_cmp_and_jump_insns (operands[1], 4466 CONST_DOUBLE_FROM_REAL_VALUE (cmp, <BFP:MODE>mode), 4467 LT, NULL_RTX, VOIDmode, 0, label1); 4468 emit_insn (gen_sub<BFP:mode>3 (temp, operands[1], 4469 CONST_DOUBLE_FROM_REAL_VALUE (sub, <BFP:MODE>mode))); 4470 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], temp, 4471 GEN_INT (7))); 4472 emit_jump (label2); 4473 4474 emit_label (label1); 4475 emit_insn (gen_fix_trunc<BFP:mode><GPR:mode>2_bfp (operands[0], 4476 operands[1], GEN_INT (5))); 4477 emit_label (label2); 4478 DONE; 4479 } 4480}) 4481 4482; fixuns_trunc(td|dd)si2 expander 4483(define_expand "fixuns_trunc<mode>si2" 4484 [(parallel 4485 [(set (match_operand:SI 0 "register_operand" "") 4486 (unsigned_fix:SI (match_operand:DFP 1 "register_operand" ""))) 4487 (unspec:SI [(const_int 5)] UNSPEC_ROUND) 4488 (clobber (reg:CC CC_REGNUM))])] 4489 "TARGET_Z196 && TARGET_HARD_DFP" 4490 "") 4491 4492; fixuns_trunc(tf|df|sf|td|dd)(di|si)2 instruction patterns. 4493 4494(define_insn "*fixuns_truncdfdi2_z13" 4495 [(set (match_operand:DI 0 "register_operand" "=d,v") 4496 (unsigned_fix:DI (match_operand:DF 1 "register_operand" "f,v"))) 4497 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) 4498 (clobber (reg:CC CC_REGNUM))] 4499 "TARGET_VX && TARGET_HARD_FLOAT" 4500 "@ 4501 clgdbr\t%0,%h2,%1,0 4502 wclgdb\t%v0,%v1,0,%h2" 4503 [(set_attr "op_type" "RRF,VRR") 4504 (set_attr "type" "ftoi")]) 4505 4506; clfebr, clfdbr, clfxbr, clgebr, clgdbr, clgxbr 4507; clfdtr, clfxtr, clgdtr, clgxtr 4508(define_insn "*fixuns_trunc<FP:mode><GPR:mode>2_z196" 4509 [(set (match_operand:GPR 0 "register_operand" "=d") 4510 (unsigned_fix:GPR (match_operand:FP 1 "register_operand" "f"))) 4511 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) 4512 (clobber (reg:CC CC_REGNUM))] 4513 "TARGET_Z196 && TARGET_HARD_FLOAT 4514 && (!TARGET_VX || <GPR:MODE>mode != DImode || <FP:MODE>mode != DFmode)" 4515 "cl<GPR:gf><FP:xde><FP:bt>r\t%0,%h2,%1,0" 4516 [(set_attr "op_type" "RRF") 4517 (set_attr "type" "ftoi")]) 4518 4519(define_expand "fix_trunc<DSF:mode><GPR:mode>2" 4520 [(set (match_operand:GPR 0 "register_operand" "") 4521 (fix:GPR (match_operand:DSF 1 "register_operand" "")))] 4522 "TARGET_HARD_FLOAT" 4523{ 4524 emit_insn (gen_fix_trunc<DSF:mode><GPR:mode>2_bfp (operands[0], operands[1], 4525 GEN_INT (5))); 4526 DONE; 4527}) 4528 4529(define_insn "*fix_truncdfdi2_bfp_z13" 4530 [(set (match_operand:DI 0 "register_operand" "=d,v") 4531 (fix:DI (match_operand:DF 1 "register_operand" "f,v"))) 4532 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K,K")] UNSPEC_ROUND) 4533 (clobber (reg:CC CC_REGNUM))] 4534 "TARGET_VX && TARGET_HARD_FLOAT" 4535 "@ 4536 cgdbr\t%0,%h2,%1 4537 wcgdb\t%v0,%v1,0,%h2" 4538 [(set_attr "op_type" "RRE,VRR") 4539 (set_attr "type" "ftoi")]) 4540 4541; cgxbr, cgdbr, cgebr, cfxbr, cfdbr, cfebr 4542(define_insn "*fix_trunc<BFP:mode><GPR:mode>2_bfp" 4543 [(set (match_operand:GPR 0 "register_operand" "=d") 4544 (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) 4545 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) 4546 (clobber (reg:CC CC_REGNUM))] 4547 "TARGET_HARD_FLOAT 4548 && (!TARGET_VX || <GPR:MODE>mode != DImode || <BFP:MODE>mode != DFmode)" 4549 "c<GPR:gf><BFP:xde>br\t%0,%h2,%1" 4550 [(set_attr "op_type" "RRE") 4551 (set_attr "type" "ftoi")]) 4552 4553(define_expand "fix_trunc<BFP:mode><GPR:mode>2_bfp" 4554 [(parallel 4555 [(set (match_operand:GPR 0 "register_operand" "=d") 4556 (fix:GPR (match_operand:BFP 1 "register_operand" "f"))) 4557 (unspec:GPR [(match_operand:GPR 2 "immediate_operand" "K")] UNSPEC_ROUND) 4558 (clobber (reg:CC CC_REGNUM))])] 4559 "TARGET_HARD_FLOAT") 4560; 4561; fix_trunc(td|dd)di2 instruction pattern(s). 4562; 4563 4564(define_expand "fix_trunc<mode>di2" 4565 [(set (match_operand:DI 0 "register_operand" "") 4566 (fix:DI (match_operand:DFP 1 "nonimmediate_operand" "")))] 4567 "TARGET_ZARCH && TARGET_HARD_DFP" 4568{ 4569 operands[1] = force_reg (<MODE>mode, operands[1]); 4570 emit_insn (gen_fix_trunc<mode>di2_dfp (operands[0], operands[1], 4571 GEN_INT (9))); 4572 DONE; 4573}) 4574 4575; cgxtr, cgdtr 4576(define_insn "fix_trunc<DFP:mode>di2_dfp" 4577 [(set (match_operand:DI 0 "register_operand" "=d") 4578 (fix:DI (match_operand:DFP 1 "register_operand" "f"))) 4579 (unspec:DI [(match_operand:DI 2 "immediate_operand" "K")] UNSPEC_ROUND) 4580 (clobber (reg:CC CC_REGNUM))] 4581 "TARGET_ZARCH && TARGET_HARD_DFP" 4582 "cg<DFP:xde>tr\t%0,%h2,%1" 4583 [(set_attr "op_type" "RRF") 4584 (set_attr "type" "ftoidfp")]) 4585 4586 4587; 4588; fix_trunctf(si|di)2 instruction pattern(s). 4589; 4590 4591(define_expand "fix_trunctf<mode>2" 4592 [(parallel [(set (match_operand:GPR 0 "register_operand" "") 4593 (fix:GPR (match_operand:TF 1 "register_operand" ""))) 4594 (unspec:GPR [(const_int 5)] UNSPEC_ROUND) 4595 (clobber (reg:CC CC_REGNUM))])] 4596 "TARGET_HARD_FLOAT" 4597 "") 4598 4599 4600; 4601; float(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). 4602; 4603 4604; cxgbr, cdgbr, cegbr, cxgtr, cdgtr 4605(define_insn "floatdi<mode>2" 4606 [(set (match_operand:FP 0 "register_operand" "=f,<vf>") 4607 (float:FP (match_operand:DI 1 "register_operand" "d,<vd>")))] 4608 "TARGET_ZARCH && TARGET_HARD_FLOAT" 4609 "@ 4610 c<xde>g<bt>r\t%0,%1 4611 wcdgb\t%v0,%v1,0,0" 4612 [(set_attr "op_type" "RRE,VRR") 4613 (set_attr "type" "itof<mode>" ) 4614 (set_attr "cpu_facility" "*,vec")]) 4615 4616; cxfbr, cdfbr, cefbr 4617(define_insn "floatsi<mode>2" 4618 [(set (match_operand:BFP 0 "register_operand" "=f") 4619 (float:BFP (match_operand:SI 1 "register_operand" "d")))] 4620 "TARGET_HARD_FLOAT" 4621 "c<xde>fbr\t%0,%1" 4622 [(set_attr "op_type" "RRE") 4623 (set_attr "type" "itof<mode>" )]) 4624 4625; cxftr, cdftr 4626(define_insn "floatsi<mode>2" 4627 [(set (match_operand:DFP 0 "register_operand" "=f") 4628 (float:DFP (match_operand:SI 1 "register_operand" "d")))] 4629 "TARGET_Z196 && TARGET_HARD_FLOAT" 4630 "c<xde>ftr\t%0,0,%1,0" 4631 [(set_attr "op_type" "RRE") 4632 (set_attr "type" "itof<mode>" )]) 4633 4634; 4635; floatuns(si|di)(tf|df|sf|td|dd)2 instruction pattern(s). 4636; 4637 4638(define_insn "*floatunsdidf2_z13" 4639 [(set (match_operand:DF 0 "register_operand" "=f,v") 4640 (unsigned_float:DF (match_operand:DI 1 "register_operand" "d,v")))] 4641 "TARGET_VX && TARGET_HARD_FLOAT" 4642 "@ 4643 cdlgbr\t%0,0,%1,0 4644 wcdlgb\t%v0,%v1,0,0" 4645 [(set_attr "op_type" "RRE,VRR") 4646 (set_attr "type" "itofdf")]) 4647 4648; cxlgbr, cdlgbr, celgbr, cxlgtr, cdlgtr 4649; cxlfbr, cdlfbr, celfbr, cxlftr, cdlftr 4650(define_insn "*floatuns<GPR:mode><FP:mode>2" 4651 [(set (match_operand:FP 0 "register_operand" "=f") 4652 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "d")))] 4653 "TARGET_Z196 && TARGET_HARD_FLOAT 4654 && (!TARGET_VX || <FP:MODE>mode != DFmode || <GPR:MODE>mode != DImode)" 4655 "c<FP:xde>l<GPR:gf><FP:bt>r\t%0,0,%1,0" 4656 [(set_attr "op_type" "RRE") 4657 (set_attr "type" "itof<FP:mode>")]) 4658 4659(define_expand "floatuns<GPR:mode><FP:mode>2" 4660 [(set (match_operand:FP 0 "register_operand" "") 4661 (unsigned_float:FP (match_operand:GPR 1 "register_operand" "")))] 4662 "TARGET_Z196 && TARGET_HARD_FLOAT") 4663 4664; 4665; truncdfsf2 instruction pattern(s). 4666; 4667 4668(define_insn "truncdfsf2" 4669 [(set (match_operand:SF 0 "register_operand" "=f,v") 4670 (float_truncate:SF (match_operand:DF 1 "register_operand" "f,v")))] 4671 "TARGET_HARD_FLOAT" 4672 "@ 4673 ledbr\t%0,%1 4674 wledb\t%v0,%v1,0,0" ; IEEE inexact exception not suppressed 4675 ; According to BFP rounding mode 4676 [(set_attr "op_type" "RRE,VRR") 4677 (set_attr "type" "ftruncdf") 4678 (set_attr "cpu_facility" "*,vec")]) 4679 4680; 4681; trunctf(df|sf)2 instruction pattern(s). 4682; 4683 4684; ldxbr, lexbr 4685(define_insn "trunctf<mode>2" 4686 [(set (match_operand:DSF 0 "register_operand" "=f") 4687 (float_truncate:DSF (match_operand:TF 1 "register_operand" "f"))) 4688 (clobber (match_scratch:TF 2 "=f"))] 4689 "TARGET_HARD_FLOAT" 4690 "l<xde>xbr\t%2,%1\;l<xde>r\t%0,%2" 4691 [(set_attr "length" "6") 4692 (set_attr "type" "ftrunctf")]) 4693 4694; 4695; trunctddd2 and truncddsd2 instruction pattern(s). 4696; 4697 4698(define_insn "trunctddd2" 4699 [(set (match_operand:DD 0 "register_operand" "=f") 4700 (float_truncate:DD (match_operand:TD 1 "register_operand" "f"))) 4701 (clobber (match_scratch:TD 2 "=f"))] 4702 "TARGET_HARD_DFP" 4703 "ldxtr\t%2,0,%1,0\;ldr\t%0,%2" 4704 [(set_attr "length" "6") 4705 (set_attr "type" "ftruncdd")]) 4706 4707(define_insn "truncddsd2" 4708 [(set (match_operand:SD 0 "register_operand" "=f") 4709 (float_truncate:SD (match_operand:DD 1 "register_operand" "f")))] 4710 "TARGET_HARD_DFP" 4711 "ledtr\t%0,0,%1,0" 4712 [(set_attr "op_type" "RRF") 4713 (set_attr "type" "ftruncsd")]) 4714 4715(define_expand "trunctdsd2" 4716 [(parallel 4717 [(set (match_dup 3) 4718 (float_truncate:DD (match_operand:TD 1 "register_operand" ""))) 4719 (clobber (match_scratch:TD 2 ""))]) 4720 (set (match_operand:SD 0 "register_operand" "") 4721 (float_truncate:SD (match_dup 3)))] 4722 "TARGET_HARD_DFP" 4723{ 4724 operands[3] = gen_reg_rtx (DDmode); 4725}) 4726 4727; 4728; extend(sf|df)(df|tf)2 instruction pattern(s). 4729; 4730 4731(define_insn "*extendsfdf2_z13" 4732 [(set (match_operand:DF 0 "register_operand" "=f,f,v") 4733 (float_extend:DF (match_operand:SF 1 "nonimmediate_operand" "f,R,v")))] 4734 "TARGET_VX && TARGET_HARD_FLOAT" 4735 "@ 4736 ldebr\t%0,%1 4737 ldeb\t%0,%1 4738 wldeb\t%v0,%v1" 4739 [(set_attr "op_type" "RRE,RXE,VRR") 4740 (set_attr "type" "fsimpdf, floaddf,fsimpdf")]) 4741 4742; ldebr, ldeb, lxdbr, lxdb, lxebr, lxeb 4743(define_insn "*extend<DSF:mode><BFP:mode>2" 4744 [(set (match_operand:BFP 0 "register_operand" "=f,f") 4745 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "f,R")))] 4746 "TARGET_HARD_FLOAT 4747 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode) 4748 && (!TARGET_VX || <BFP:MODE>mode != DFmode || <DSF:MODE>mode != SFmode)" 4749 "@ 4750 l<BFP:xde><DSF:xde>br\t%0,%1 4751 l<BFP:xde><DSF:xde>b\t%0,%1" 4752 [(set_attr "op_type" "RRE,RXE") 4753 (set_attr "type" "fsimp<BFP:mode>, fload<BFP:mode>")]) 4754 4755(define_expand "extend<DSF:mode><BFP:mode>2" 4756 [(set (match_operand:BFP 0 "register_operand" "") 4757 (float_extend:BFP (match_operand:DSF 1 "nonimmediate_operand" "")))] 4758 "TARGET_HARD_FLOAT 4759 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DSF:MODE>mode)") 4760 4761; 4762; extendddtd2 and extendsddd2 instruction pattern(s). 4763; 4764 4765(define_insn "extendddtd2" 4766 [(set (match_operand:TD 0 "register_operand" "=f") 4767 (float_extend:TD (match_operand:DD 1 "register_operand" "f")))] 4768 "TARGET_HARD_DFP" 4769 "lxdtr\t%0,%1,0" 4770 [(set_attr "op_type" "RRF") 4771 (set_attr "type" "fsimptf")]) 4772 4773(define_insn "extendsddd2" 4774 [(set (match_operand:DD 0 "register_operand" "=f") 4775 (float_extend:DD (match_operand:SD 1 "register_operand" "f")))] 4776 "TARGET_HARD_DFP" 4777 "ldetr\t%0,%1,0" 4778 [(set_attr "op_type" "RRF") 4779 (set_attr "type" "fsimptf")]) 4780 4781(define_expand "extendsdtd2" 4782 [(set (match_dup 2) 4783 (float_extend:DD (match_operand:SD 1 "register_operand" ""))) 4784 (set (match_operand:TD 0 "register_operand" "") 4785 (float_extend:TD (match_dup 2)))] 4786 "TARGET_HARD_DFP" 4787{ 4788 operands[2] = gen_reg_rtx (DDmode); 4789}) 4790 4791; Binary Floating Point - load fp integer 4792 4793; Expanders for: floor, btrunc, round, ceil, and nearbyint 4794; For all of them the inexact exceptions are suppressed. 4795 4796; fiebra, fidbra, fixbra 4797(define_insn "<FPINT:fpint_name><BFP:mode>2" 4798 [(set (match_operand:BFP 0 "register_operand" "=f") 4799 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] 4800 FPINT))] 4801 "TARGET_Z196" 4802 "fi<BFP:xde>bra\t%0,<FPINT:fpint_roundingmode>,%1,4" 4803 [(set_attr "op_type" "RRF") 4804 (set_attr "type" "fsimp<BFP:mode>")]) 4805 4806; rint is supposed to raise an inexact exception so we can use the 4807; older instructions. 4808 4809; fiebr, fidbr, fixbr 4810(define_insn "rint<BFP:mode>2" 4811 [(set (match_operand:BFP 0 "register_operand" "=f") 4812 (unspec:BFP [(match_operand:BFP 1 "register_operand" "f")] 4813 UNSPEC_FPINT_RINT))] 4814 "" 4815 "fi<BFP:xde>br\t%0,0,%1" 4816 [(set_attr "op_type" "RRF") 4817 (set_attr "type" "fsimp<BFP:mode>")]) 4818 4819 4820; Decimal Floating Point - load fp integer 4821 4822; fidtr, fixtr 4823(define_insn "<FPINT:fpint_name><DFP:mode>2" 4824 [(set (match_operand:DFP 0 "register_operand" "=f") 4825 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] 4826 FPINT))] 4827 "TARGET_HARD_DFP" 4828 "fi<DFP:xde>tr\t%0,<FPINT:fpint_roundingmode>,%1,4" 4829 [(set_attr "op_type" "RRF") 4830 (set_attr "type" "fsimp<DFP:mode>")]) 4831 4832; fidtr, fixtr 4833(define_insn "rint<DFP:mode>2" 4834 [(set (match_operand:DFP 0 "register_operand" "=f") 4835 (unspec:DFP [(match_operand:DFP 1 "register_operand" "f")] 4836 UNSPEC_FPINT_RINT))] 4837 "TARGET_HARD_DFP" 4838 "fi<DFP:xde>tr\t%0,0,%1,0" 4839 [(set_attr "op_type" "RRF") 4840 (set_attr "type" "fsimp<DFP:mode>")]) 4841 4842; 4843; Binary <-> Decimal floating point trunc patterns 4844; 4845 4846(define_insn "*trunc<BFP:mode><DFP_ALL:mode>2" 4847 [(set (reg:DFP_ALL FPR0_REGNUM) 4848 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) 4849 (use (reg:SI GPR0_REGNUM)) 4850 (clobber (reg:CC CC_REGNUM)) 4851 (clobber (reg:SI GPR1_REGNUM))] 4852 "TARGET_HARD_DFP" 4853 "pfpo") 4854 4855(define_insn "*trunc<DFP_ALL:mode><BFP:mode>2" 4856 [(set (reg:BFP FPR0_REGNUM) 4857 (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) 4858 (use (reg:SI GPR0_REGNUM)) 4859 (clobber (reg:CC CC_REGNUM)) 4860 (clobber (reg:SI GPR1_REGNUM))] 4861 "TARGET_HARD_DFP" 4862 "pfpo") 4863 4864(define_expand "trunc<BFP:mode><DFP_ALL:mode>2" 4865 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) 4866 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 4867 (parallel 4868 [(set (reg:DFP_ALL FPR0_REGNUM) 4869 (float_truncate:DFP_ALL (reg:BFP FPR4_REGNUM))) 4870 (use (reg:SI GPR0_REGNUM)) 4871 (clobber (reg:CC CC_REGNUM)) 4872 (clobber (reg:SI GPR1_REGNUM))]) 4873 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") 4874 (reg:DFP_ALL FPR0_REGNUM))] 4875 "TARGET_HARD_DFP 4876 && GET_MODE_SIZE (<BFP:MODE>mode) > GET_MODE_SIZE (<DFP_ALL:MODE>mode)" 4877{ 4878 HOST_WIDE_INT flags; 4879 4880 flags = (PFPO_CONVERT | 4881 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | 4882 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); 4883 4884 operands[2] = GEN_INT (flags); 4885}) 4886 4887(define_expand "trunc<DFP_ALL:mode><BFP:mode>2" 4888 [(set (reg:DFP_ALL FPR4_REGNUM) 4889 (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) 4890 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 4891 (parallel 4892 [(set (reg:BFP FPR0_REGNUM) (float_truncate:BFP (reg:DFP_ALL FPR4_REGNUM))) 4893 (use (reg:SI GPR0_REGNUM)) 4894 (clobber (reg:CC CC_REGNUM)) 4895 (clobber (reg:SI GPR1_REGNUM))]) 4896 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] 4897 "TARGET_HARD_DFP 4898 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) >= GET_MODE_SIZE (<BFP:MODE>mode)" 4899{ 4900 HOST_WIDE_INT flags; 4901 4902 flags = (PFPO_CONVERT | 4903 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | 4904 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); 4905 4906 operands[2] = GEN_INT (flags); 4907}) 4908 4909; 4910; Binary <-> Decimal floating point extend patterns 4911; 4912 4913(define_insn "*extend<BFP:mode><DFP_ALL:mode>2" 4914 [(set (reg:DFP_ALL FPR0_REGNUM) (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) 4915 (use (reg:SI GPR0_REGNUM)) 4916 (clobber (reg:CC CC_REGNUM)) 4917 (clobber (reg:SI GPR1_REGNUM))] 4918 "TARGET_HARD_DFP" 4919 "pfpo") 4920 4921(define_insn "*extend<DFP_ALL:mode><BFP:mode>2" 4922 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) 4923 (use (reg:SI GPR0_REGNUM)) 4924 (clobber (reg:CC CC_REGNUM)) 4925 (clobber (reg:SI GPR1_REGNUM))] 4926 "TARGET_HARD_DFP" 4927 "pfpo") 4928 4929(define_expand "extend<BFP:mode><DFP_ALL:mode>2" 4930 [(set (reg:BFP FPR4_REGNUM) (match_operand:BFP 1 "nonimmediate_operand" "")) 4931 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 4932 (parallel 4933 [(set (reg:DFP_ALL FPR0_REGNUM) 4934 (float_extend:DFP_ALL (reg:BFP FPR4_REGNUM))) 4935 (use (reg:SI GPR0_REGNUM)) 4936 (clobber (reg:CC CC_REGNUM)) 4937 (clobber (reg:SI GPR1_REGNUM))]) 4938 (set (match_operand:DFP_ALL 0 "nonimmediate_operand" "") 4939 (reg:DFP_ALL FPR0_REGNUM))] 4940 "TARGET_HARD_DFP 4941 && GET_MODE_SIZE (<BFP:MODE>mode) <= GET_MODE_SIZE (<DFP_ALL:MODE>mode)" 4942{ 4943 HOST_WIDE_INT flags; 4944 4945 flags = (PFPO_CONVERT | 4946 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP0_TYPE_SHIFT | 4947 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP1_TYPE_SHIFT); 4948 4949 operands[2] = GEN_INT (flags); 4950}) 4951 4952(define_expand "extend<DFP_ALL:mode><BFP:mode>2" 4953 [(set (reg:DFP_ALL FPR4_REGNUM) 4954 (match_operand:DFP_ALL 1 "nonimmediate_operand" "")) 4955 (set (reg:SI GPR0_REGNUM) (match_dup 2)) 4956 (parallel 4957 [(set (reg:BFP FPR0_REGNUM) (float_extend:BFP (reg:DFP_ALL FPR4_REGNUM))) 4958 (use (reg:SI GPR0_REGNUM)) 4959 (clobber (reg:CC CC_REGNUM)) 4960 (clobber (reg:SI GPR1_REGNUM))]) 4961 (set (match_operand:BFP 0 "nonimmediate_operand" "") (reg:BFP FPR0_REGNUM))] 4962 "TARGET_HARD_DFP 4963 && GET_MODE_SIZE (<DFP_ALL:MODE>mode) < GET_MODE_SIZE (<BFP:MODE>mode)" 4964{ 4965 HOST_WIDE_INT flags; 4966 4967 flags = (PFPO_CONVERT | 4968 PFPO_OP_TYPE_<BFP:MODE> << PFPO_OP0_TYPE_SHIFT | 4969 PFPO_OP_TYPE_<DFP_ALL:MODE> << PFPO_OP1_TYPE_SHIFT); 4970 4971 operands[2] = GEN_INT (flags); 4972}) 4973 4974 4975;; 4976;; ARITHMETIC OPERATIONS 4977;; 4978; arithmetic operations set the ConditionCode, 4979; because of unpredictable Bits in Register for Halfword and Byte 4980; the ConditionCode can be set wrong in operations for Halfword and Byte 4981 4982;; 4983;;- Add instructions. 4984;; 4985 4986; 4987; addti3 instruction pattern(s). 4988; 4989 4990(define_expand "addti3" 4991 [(parallel 4992 [(set (match_operand:TI 0 "register_operand" "") 4993 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "") 4994 (match_operand:TI 2 "general_operand" "") ) ) 4995 (clobber (reg:CC CC_REGNUM))])] 4996 "TARGET_ZARCH" 4997{ 4998 /* For z13 we have vaq which doesn't set CC. */ 4999 if (TARGET_VX) 5000 { 5001 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 5002 gen_rtx_PLUS (TImode, 5003 copy_to_mode_reg (TImode, operands[1]), 5004 copy_to_mode_reg (TImode, operands[2])))); 5005 DONE; 5006 } 5007}) 5008 5009(define_insn_and_split "*addti3" 5010 [(set (match_operand:TI 0 "register_operand" "=&d") 5011 (plus:TI (match_operand:TI 1 "nonimmediate_operand" "%0") 5012 (match_operand:TI 2 "general_operand" "do") ) ) 5013 (clobber (reg:CC CC_REGNUM))] 5014 "TARGET_ZARCH" 5015 "#" 5016 "&& reload_completed" 5017 [(parallel 5018 [(set (reg:CCL1 CC_REGNUM) 5019 (compare:CCL1 (plus:DI (match_dup 7) (match_dup 8)) 5020 (match_dup 7))) 5021 (set (match_dup 6) (plus:DI (match_dup 7) (match_dup 8)))]) 5022 (parallel 5023 [(set (match_dup 3) (plus:DI 5024 (plus:DI (ltu:DI (reg:CCL1 CC_REGNUM) (const_int 0)) 5025 (match_dup 4)) (match_dup 5))) 5026 (clobber (reg:CC CC_REGNUM))])] 5027 "operands[3] = operand_subword (operands[0], 0, 0, TImode); 5028 operands[4] = operand_subword (operands[1], 0, 0, TImode); 5029 operands[5] = operand_subword (operands[2], 0, 0, TImode); 5030 operands[6] = operand_subword (operands[0], 1, 0, TImode); 5031 operands[7] = operand_subword (operands[1], 1, 0, TImode); 5032 operands[8] = operand_subword (operands[2], 1, 0, TImode);" 5033 [(set_attr "op_type" "*") 5034 (set_attr "cpu_facility" "*")]) 5035 5036; 5037; adddi3 instruction pattern(s). 5038; 5039 5040(define_expand "adddi3" 5041 [(parallel 5042 [(set (match_operand:DI 0 "nonimmediate_operand" "") 5043 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "") 5044 (match_operand:DI 2 "general_operand" ""))) 5045 (clobber (reg:CC CC_REGNUM))])] 5046 "" 5047 "") 5048 5049(define_insn "*adddi3_sign" 5050 [(set (match_operand:DI 0 "register_operand" "=d,d") 5051 (plus:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 5052 (match_operand:DI 1 "register_operand" "0,0"))) 5053 (clobber (reg:CC CC_REGNUM))] 5054 "TARGET_ZARCH" 5055 "@ 5056 agfr\t%0,%2 5057 agf\t%0,%2" 5058 [(set_attr "op_type" "RRE,RXY") 5059 (set_attr "z196prop" "z196_cracked,z196_cracked")]) 5060 5061(define_insn "*adddi3_zero_cc" 5062 [(set (reg CC_REGNUM) 5063 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 5064 (match_operand:DI 1 "register_operand" "0,0")) 5065 (const_int 0))) 5066 (set (match_operand:DI 0 "register_operand" "=d,d") 5067 (plus:DI (zero_extend:DI (match_dup 2)) (match_dup 1)))] 5068 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 5069 "@ 5070 algfr\t%0,%2 5071 algf\t%0,%2" 5072 [(set_attr "op_type" "RRE,RXY") 5073 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5074 5075(define_insn "*adddi3_zero_cconly" 5076 [(set (reg CC_REGNUM) 5077 (compare (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 5078 (match_operand:DI 1 "register_operand" "0,0")) 5079 (const_int 0))) 5080 (clobber (match_scratch:DI 0 "=d,d"))] 5081 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 5082 "@ 5083 algfr\t%0,%2 5084 algf\t%0,%2" 5085 [(set_attr "op_type" "RRE,RXY") 5086 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5087 5088(define_insn "*adddi3_zero" 5089 [(set (match_operand:DI 0 "register_operand" "=d,d") 5090 (plus:DI (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 5091 (match_operand:DI 1 "register_operand" "0,0"))) 5092 (clobber (reg:CC CC_REGNUM))] 5093 "TARGET_ZARCH" 5094 "@ 5095 algfr\t%0,%2 5096 algf\t%0,%2" 5097 [(set_attr "op_type" "RRE,RXY") 5098 (set_attr "z10prop" "z10_super_E1,z10_super_E1")]) 5099 5100(define_insn_and_split "*adddi3_31z" 5101 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") 5102 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 5103 (match_operand:DI 2 "general_operand" "do") ) ) 5104 (clobber (reg:CC CC_REGNUM))] 5105 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 5106 "#" 5107 "&& reload_completed" 5108 [(parallel 5109 [(set (reg:CCL1 CC_REGNUM) 5110 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) 5111 (match_dup 7))) 5112 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) 5113 (parallel 5114 [(set (match_dup 3) (plus:SI 5115 (plus:SI (ltu:SI (reg:CCL1 CC_REGNUM) (const_int 0)) 5116 (match_dup 4)) (match_dup 5))) 5117 (clobber (reg:CC CC_REGNUM))])] 5118 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 5119 operands[4] = operand_subword (operands[1], 0, 0, DImode); 5120 operands[5] = operand_subword (operands[2], 0, 0, DImode); 5121 operands[6] = operand_subword (operands[0], 1, 0, DImode); 5122 operands[7] = operand_subword (operands[1], 1, 0, DImode); 5123 operands[8] = operand_subword (operands[2], 1, 0, DImode);") 5124 5125(define_insn_and_split "*adddi3_31" 5126 [(set (match_operand:DI 0 "nonimmediate_operand" "=&d") 5127 (plus:DI (match_operand:DI 1 "nonimmediate_operand" "%0") 5128 (match_operand:DI 2 "general_operand" "do") ) ) 5129 (clobber (reg:CC CC_REGNUM))] 5130 "!TARGET_CPU_ZARCH" 5131 "#" 5132 "&& reload_completed" 5133 [(parallel 5134 [(set (match_dup 3) (plus:SI (match_dup 4) (match_dup 5))) 5135 (clobber (reg:CC CC_REGNUM))]) 5136 (parallel 5137 [(set (reg:CCL1 CC_REGNUM) 5138 (compare:CCL1 (plus:SI (match_dup 7) (match_dup 8)) 5139 (match_dup 7))) 5140 (set (match_dup 6) (plus:SI (match_dup 7) (match_dup 8)))]) 5141 (set (pc) 5142 (if_then_else (ltu (reg:CCL1 CC_REGNUM) (const_int 0)) 5143 (pc) 5144 (label_ref (match_dup 9)))) 5145 (parallel 5146 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int 1))) 5147 (clobber (reg:CC CC_REGNUM))]) 5148 (match_dup 9)] 5149 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 5150 operands[4] = operand_subword (operands[1], 0, 0, DImode); 5151 operands[5] = operand_subword (operands[2], 0, 0, DImode); 5152 operands[6] = operand_subword (operands[0], 1, 0, DImode); 5153 operands[7] = operand_subword (operands[1], 1, 0, DImode); 5154 operands[8] = operand_subword (operands[2], 1, 0, DImode); 5155 operands[9] = gen_label_rtx ();") 5156 5157; 5158; addsi3 instruction pattern(s). 5159; 5160 5161(define_expand "addsi3" 5162 [(parallel 5163 [(set (match_operand:SI 0 "nonimmediate_operand" "") 5164 (plus:SI (match_operand:SI 1 "nonimmediate_operand" "") 5165 (match_operand:SI 2 "general_operand" ""))) 5166 (clobber (reg:CC CC_REGNUM))])] 5167 "" 5168 "") 5169 5170(define_insn "*addsi3_sign" 5171 [(set (match_operand:SI 0 "register_operand" "=d,d") 5172 (plus:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) 5173 (match_operand:SI 1 "register_operand" "0,0"))) 5174 (clobber (reg:CC CC_REGNUM))] 5175 "" 5176 "@ 5177 ah\t%0,%2 5178 ahy\t%0,%2" 5179 [(set_attr "op_type" "RX,RXY") 5180 (set_attr "z196prop" "z196_cracked,z196_cracked")]) 5181 5182; 5183; add(di|si)3 instruction pattern(s). 5184; 5185 5186; ark, agrk, ar, ahi, ahik, aghik, alfi, slfi, a, ay, agr, aghi, algfi, slgfi, ag, asi, agsi 5187(define_insn "*add<mode>3" 5188 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d,d,d, d, d,d,d,QS") 5189 (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,d, 0, 0,0,0, 0") 5190 (match_operand:GPR 2 "general_operand" " d,d,K,K,Op,On,R,T, C") ) ) 5191 (clobber (reg:CC CC_REGNUM))] 5192 "" 5193 "@ 5194 a<g>r\t%0,%2 5195 a<g>rk\t%0,%1,%2 5196 a<g>hi\t%0,%h2 5197 a<g>hik\t%0,%1,%h2 5198 al<g>fi\t%0,%2 5199 sl<g>fi\t%0,%n2 5200 a<g>\t%0,%2 5201 a<y>\t%0,%2 5202 a<g>si\t%0,%c2" 5203 [(set_attr "op_type" "RR<E>,RRF,RI,RIE,RIL,RIL,RX<Y>,RXY,SIY") 5204 (set_attr "cpu_facility" "*,z196,*,z196,extimm,extimm,*,*,z10") 5205 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,z10_super_E1,z10_super_E1, 5206 z10_super_E1,z10_super_E1,z10_super_E1")]) 5207 5208; alr, alfi, slfi, al, aly, alrk, alhsik, algr, algfi, slgfi, alg, alsi, algsi, algrk, alghsik 5209(define_insn "*add<mode>3_carry1_cc" 5210 [(set (reg CC_REGNUM) 5211 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0,0") 5212 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T,C")) 5213 (match_dup 1))) 5214 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,d") 5215 (plus:GPR (match_dup 1) (match_dup 2)))] 5216 "s390_match_ccmode (insn, CCL1mode)" 5217 "@ 5218 al<g>r\t%0,%2 5219 al<g>rk\t%0,%1,%2 5220 al<g>fi\t%0,%2 5221 sl<g>fi\t%0,%n2 5222 al<g>hsik\t%0,%1,%h2 5223 al<g>\t%0,%2 5224 al<y>\t%0,%2 5225 al<g>si\t%0,%c2" 5226 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") 5227 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") 5228 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, 5229 z10_super_E1,z10_super_E1,z10_super_E1")]) 5230 5231; alr, al, aly, algr, alg, alrk, algrk 5232(define_insn "*add<mode>3_carry1_cconly" 5233 [(set (reg CC_REGNUM) 5234 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 5235 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5236 (match_dup 1))) 5237 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5238 "s390_match_ccmode (insn, CCL1mode)" 5239 "@ 5240 al<g>r\t%0,%2 5241 al<g>rk\t%0,%1,%2 5242 al<g>\t%0,%2 5243 al<y>\t%0,%2" 5244 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5245 (set_attr "cpu_facility" "*,z196,*,*") 5246 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5247 5248; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik 5249(define_insn "*add<mode>3_carry2_cc" 5250 [(set (reg CC_REGNUM) 5251 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") 5252 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) 5253 (match_dup 2))) 5254 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") 5255 (plus:GPR (match_dup 1) (match_dup 2)))] 5256 "s390_match_ccmode (insn, CCL1mode)" 5257 "@ 5258 al<g>r\t%0,%2 5259 al<g>rk\t%0,%1,%2 5260 al<g>fi\t%0,%2 5261 sl<g>fi\t%0,%n2 5262 al<g>hsik\t%0,%1,%h2 5263 al<g>\t%0,%2 5264 al<y>\t%0,%2 5265 al<g>si\t%0,%c2" 5266 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") 5267 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") 5268 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1,*, 5269 z10_super_E1,z10_super_E1,z10_super_E1")]) 5270 5271; alr, al, aly, algr, alg, alrk, algrk 5272(define_insn "*add<mode>3_carry2_cconly" 5273 [(set (reg CC_REGNUM) 5274 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 5275 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5276 (match_dup 2))) 5277 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5278 "s390_match_ccmode (insn, CCL1mode)" 5279 "@ 5280 al<g>r\t%0,%2 5281 al<g>rk\t%0,%1,%2 5282 al<g>\t%0,%2 5283 al<y>\t%0,%2" 5284 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5285 (set_attr "cpu_facility" "*,z196,*,*") 5286 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5287 5288; alr, alfi, slfi, al, aly, algr, algfi, slgfi, alg, alsi, algsi, alrk, algrk, alhsik, alghsik 5289(define_insn "*add<mode>3_cc" 5290 [(set (reg CC_REGNUM) 5291 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d, 0, 0,d,0,0, 0") 5292 (match_operand:GPR 2 "general_operand" " d,d,Op,On,K,R,T, C")) 5293 (const_int 0))) 5294 (set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,d,d,d,RS") 5295 (plus:GPR (match_dup 1) (match_dup 2)))] 5296 "s390_match_ccmode (insn, CCLmode)" 5297 "@ 5298 al<g>r\t%0,%2 5299 al<g>rk\t%0,%1,%2 5300 al<g>fi\t%0,%2 5301 sl<g>fi\t%0,%n2 5302 al<g>hsik\t%0,%1,%h2 5303 al<g>\t%0,%2 5304 al<y>\t%0,%2 5305 al<g>si\t%0,%c2" 5306 [(set_attr "op_type" "RR<E>,RRF,RIL,RIL,RIE,RX<Y>,RXY,SIY") 5307 (set_attr "cpu_facility" "*,z196,extimm,extimm,z196,*,*,z10") 5308 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1, 5309 *,z10_super_E1,z10_super_E1,z10_super_E1")]) 5310 5311; alr, al, aly, algr, alg, alrk, algrk 5312(define_insn "*add<mode>3_cconly" 5313 [(set (reg CC_REGNUM) 5314 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 5315 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5316 (const_int 0))) 5317 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5318 "s390_match_ccmode (insn, CCLmode)" 5319 "@ 5320 al<g>r\t%0,%2 5321 al<g>rk\t%0,%1,%2 5322 al<g>\t%0,%2 5323 al<y>\t%0,%2" 5324 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5325 (set_attr "cpu_facility" "*,z196,*,*") 5326 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5327 5328; alr, al, aly, algr, alg, alrk, algrk 5329(define_insn "*add<mode>3_cconly2" 5330 [(set (reg CC_REGNUM) 5331 (compare (match_operand:GPR 1 "nonimmediate_operand" "%0,d,0,0") 5332 (neg:GPR (match_operand:GPR 2 "general_operand" "d,d,R,T")))) 5333 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5334 "s390_match_ccmode(insn, CCLmode)" 5335 "@ 5336 al<g>r\t%0,%2 5337 al<g>rk\t%0,%1,%2 5338 al<g>\t%0,%2 5339 al<y>\t%0,%2" 5340 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5341 (set_attr "cpu_facility" "*,z196,*,*") 5342 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5343 5344; ahi, afi, aghi, agfi, asi, agsi 5345(define_insn "*add<mode>3_imm_cc" 5346 [(set (reg CC_REGNUM) 5347 (compare (plus:GPR (match_operand:GPR 1 "nonimmediate_operand" " 0, d,0, 0") 5348 (match_operand:GPR 2 "const_int_operand" " K, K,Os, C")) 5349 (const_int 0))) 5350 (set (match_operand:GPR 0 "nonimmediate_operand" "=d, d,d,QS") 5351 (plus:GPR (match_dup 1) (match_dup 2)))] 5352 "s390_match_ccmode (insn, CCAmode) 5353 && (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'K', \"K\") 5354 || (CONST_OK_FOR_CONSTRAINT_P (INTVAL (operands[2]), 'O', \"Os\") 5355 /* Avoid INT32_MIN on 32 bit. */ 5356 && (!TARGET_ZARCH || INTVAL (operands[2]) != -0x7fffffff - 1)))" 5357 "@ 5358 a<g>hi\t%0,%h2 5359 a<g>hik\t%0,%1,%h2 5360 a<g>fi\t%0,%2 5361 a<g>si\t%0,%c2" 5362 [(set_attr "op_type" "RI,RIE,RIL,SIY") 5363 (set_attr "cpu_facility" "*,z196,extimm,z10") 5364 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 5365 5366; 5367; add(tf|df|sf|td|dd)3 instruction pattern(s). 5368; 5369 5370; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr 5371; FIXME: wfadb does not clobber cc 5372(define_insn "add<mode>3" 5373 [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") 5374 (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>") 5375 (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>"))) 5376 (clobber (reg:CC CC_REGNUM))] 5377 "TARGET_HARD_FLOAT" 5378 "@ 5379 a<xde><bt>r\t%0,<op1>%2 5380 a<xde>b\t%0,%2 5381 wfadb\t%v0,%v1,%v2" 5382 [(set_attr "op_type" "<RRer>,RXE,VRR") 5383 (set_attr "type" "fsimp<mode>") 5384 (set_attr "cpu_facility" "*,*,vec")]) 5385 5386; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr 5387(define_insn "*add<mode>3_cc" 5388 [(set (reg CC_REGNUM) 5389 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") 5390 (match_operand:FP 2 "general_operand" " f,<Rf>")) 5391 (match_operand:FP 3 "const0_operand" ""))) 5392 (set (match_operand:FP 0 "register_operand" "=f,f") 5393 (plus:FP (match_dup 1) (match_dup 2)))] 5394 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 5395 "@ 5396 a<xde><bt>r\t%0,<op1>%2 5397 a<xde>b\t%0,%2" 5398 [(set_attr "op_type" "<RRer>,RXE") 5399 (set_attr "type" "fsimp<mode>")]) 5400 5401; axbr, adbr, aebr, axb, adb, aeb, adtr, axtr 5402(define_insn "*add<mode>3_cconly" 5403 [(set (reg CC_REGNUM) 5404 (compare (plus:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>,0") 5405 (match_operand:FP 2 "general_operand" " f,<Rf>")) 5406 (match_operand:FP 3 "const0_operand" ""))) 5407 (clobber (match_scratch:FP 0 "=f,f"))] 5408 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 5409 "@ 5410 a<xde><bt>r\t%0,<op1>%2 5411 a<xde>b\t%0,%2" 5412 [(set_attr "op_type" "<RRer>,RXE") 5413 (set_attr "type" "fsimp<mode>")]) 5414 5415; 5416; Pointer add instruction patterns 5417; 5418 5419; This will match "*la_64" 5420(define_expand "addptrdi3" 5421 [(set (match_operand:DI 0 "register_operand" "") 5422 (plus:DI (match_operand:DI 1 "register_operand" "") 5423 (match_operand:DI 2 "nonmemory_operand" "")))] 5424 "TARGET_64BIT" 5425{ 5426 if (GET_CODE (operands[2]) == CONST_INT) 5427 { 5428 HOST_WIDE_INT c = INTVAL (operands[2]); 5429 5430 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") 5431 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) 5432 { 5433 operands[2] = force_const_mem (DImode, operands[2]); 5434 operands[2] = force_reg (DImode, operands[2]); 5435 } 5436 else if (!DISP_IN_RANGE (INTVAL (operands[2]))) 5437 operands[2] = force_reg (DImode, operands[2]); 5438 } 5439}) 5440 5441; For 31 bit we have to prevent the generated pattern from matching 5442; normal ADDs since la only does a 31 bit add. This is supposed to 5443; match "force_la_31". 5444(define_expand "addptrsi3" 5445 [(parallel 5446 [(set (match_operand:SI 0 "register_operand" "") 5447 (plus:SI (match_operand:SI 1 "register_operand" "") 5448 (match_operand:SI 2 "nonmemory_operand" ""))) 5449 (use (const_int 0))])] 5450 "!TARGET_64BIT" 5451{ 5452 if (GET_CODE (operands[2]) == CONST_INT) 5453 { 5454 HOST_WIDE_INT c = INTVAL (operands[2]); 5455 5456 if (!CONST_OK_FOR_CONSTRAINT_P (c, 'K', "K") 5457 && !CONST_OK_FOR_CONSTRAINT_P (c, 'O', "Os")) 5458 { 5459 operands[2] = force_const_mem (SImode, operands[2]); 5460 operands[2] = force_reg (SImode, operands[2]); 5461 } 5462 else if (!DISP_IN_RANGE (INTVAL (operands[2]))) 5463 operands[2] = force_reg (SImode, operands[2]); 5464 } 5465}) 5466 5467;; 5468;;- Subtract instructions. 5469;; 5470 5471; 5472; subti3 instruction pattern(s). 5473; 5474 5475(define_expand "subti3" 5476 [(parallel 5477 [(set (match_operand:TI 0 "register_operand" "") 5478 (minus:TI (match_operand:TI 1 "register_operand" "") 5479 (match_operand:TI 2 "general_operand" "") ) ) 5480 (clobber (reg:CC CC_REGNUM))])] 5481 "TARGET_ZARCH" 5482{ 5483 /* For z13 we have vaq which doesn't set CC. */ 5484 if (TARGET_VX) 5485 { 5486 emit_insn (gen_rtx_SET (VOIDmode, operands[0], 5487 gen_rtx_MINUS (TImode, 5488 operands[1], 5489 copy_to_mode_reg (TImode, operands[2])))); 5490 DONE; 5491 } 5492}) 5493 5494(define_insn_and_split "*subti3" 5495 [(set (match_operand:TI 0 "register_operand" "=&d") 5496 (minus:TI (match_operand:TI 1 "register_operand" "0") 5497 (match_operand:TI 2 "general_operand" "do") ) ) 5498 (clobber (reg:CC CC_REGNUM))] 5499 "TARGET_ZARCH" 5500 "#" 5501 "&& reload_completed" 5502 [(parallel 5503 [(set (reg:CCL2 CC_REGNUM) 5504 (compare:CCL2 (minus:DI (match_dup 7) (match_dup 8)) 5505 (match_dup 7))) 5506 (set (match_dup 6) (minus:DI (match_dup 7) (match_dup 8)))]) 5507 (parallel 5508 [(set (match_dup 3) (minus:DI (minus:DI (match_dup 4) (match_dup 5)) 5509 (gtu:DI (reg:CCL2 CC_REGNUM) (const_int 0)))) 5510 (clobber (reg:CC CC_REGNUM))])] 5511 "operands[3] = operand_subword (operands[0], 0, 0, TImode); 5512 operands[4] = operand_subword (operands[1], 0, 0, TImode); 5513 operands[5] = operand_subword (operands[2], 0, 0, TImode); 5514 operands[6] = operand_subword (operands[0], 1, 0, TImode); 5515 operands[7] = operand_subword (operands[1], 1, 0, TImode); 5516 operands[8] = operand_subword (operands[2], 1, 0, TImode);" 5517 [(set_attr "op_type" "*") 5518 (set_attr "cpu_facility" "*")]) 5519 5520; 5521; subdi3 instruction pattern(s). 5522; 5523 5524(define_expand "subdi3" 5525 [(parallel 5526 [(set (match_operand:DI 0 "register_operand" "") 5527 (minus:DI (match_operand:DI 1 "register_operand" "") 5528 (match_operand:DI 2 "general_operand" ""))) 5529 (clobber (reg:CC CC_REGNUM))])] 5530 "" 5531 "") 5532 5533(define_insn "*subdi3_sign" 5534 [(set (match_operand:DI 0 "register_operand" "=d,d") 5535 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 5536 (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) 5537 (clobber (reg:CC CC_REGNUM))] 5538 "TARGET_ZARCH" 5539 "@ 5540 sgfr\t%0,%2 5541 sgf\t%0,%2" 5542 [(set_attr "op_type" "RRE,RXY") 5543 (set_attr "z10prop" "z10_c,*") 5544 (set_attr "z196prop" "z196_cracked")]) 5545 5546(define_insn "*subdi3_zero_cc" 5547 [(set (reg CC_REGNUM) 5548 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 5549 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) 5550 (const_int 0))) 5551 (set (match_operand:DI 0 "register_operand" "=d,d") 5552 (minus:DI (match_dup 1) (zero_extend:DI (match_dup 2))))] 5553 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 5554 "@ 5555 slgfr\t%0,%2 5556 slgf\t%0,%2" 5557 [(set_attr "op_type" "RRE,RXY") 5558 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 5559 5560(define_insn "*subdi3_zero_cconly" 5561 [(set (reg CC_REGNUM) 5562 (compare (minus:DI (match_operand:DI 1 "register_operand" "0,0") 5563 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT"))) 5564 (const_int 0))) 5565 (clobber (match_scratch:DI 0 "=d,d"))] 5566 "s390_match_ccmode (insn, CCLmode) && TARGET_ZARCH" 5567 "@ 5568 slgfr\t%0,%2 5569 slgf\t%0,%2" 5570 [(set_attr "op_type" "RRE,RXY") 5571 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 5572 5573(define_insn "*subdi3_zero" 5574 [(set (match_operand:DI 0 "register_operand" "=d,d") 5575 (minus:DI (match_operand:DI 1 "register_operand" "0,0") 5576 (zero_extend:DI (match_operand:SI 2 "general_operand" "d,RT")))) 5577 (clobber (reg:CC CC_REGNUM))] 5578 "TARGET_ZARCH" 5579 "@ 5580 slgfr\t%0,%2 5581 slgf\t%0,%2" 5582 [(set_attr "op_type" "RRE,RXY") 5583 (set_attr "z10prop" "z10_super_c_E1,z10_super_E1")]) 5584 5585(define_insn_and_split "*subdi3_31z" 5586 [(set (match_operand:DI 0 "register_operand" "=&d") 5587 (minus:DI (match_operand:DI 1 "register_operand" "0") 5588 (match_operand:DI 2 "general_operand" "do") ) ) 5589 (clobber (reg:CC CC_REGNUM))] 5590 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 5591 "#" 5592 "&& reload_completed" 5593 [(parallel 5594 [(set (reg:CCL2 CC_REGNUM) 5595 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) 5596 (match_dup 7))) 5597 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) 5598 (parallel 5599 [(set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) 5600 (gtu:SI (reg:CCL2 CC_REGNUM) (const_int 0)))) 5601 (clobber (reg:CC CC_REGNUM))])] 5602 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 5603 operands[4] = operand_subword (operands[1], 0, 0, DImode); 5604 operands[5] = operand_subword (operands[2], 0, 0, DImode); 5605 operands[6] = operand_subword (operands[0], 1, 0, DImode); 5606 operands[7] = operand_subword (operands[1], 1, 0, DImode); 5607 operands[8] = operand_subword (operands[2], 1, 0, DImode);") 5608 5609(define_insn_and_split "*subdi3_31" 5610 [(set (match_operand:DI 0 "register_operand" "=&d") 5611 (minus:DI (match_operand:DI 1 "register_operand" "0") 5612 (match_operand:DI 2 "general_operand" "do") ) ) 5613 (clobber (reg:CC CC_REGNUM))] 5614 "!TARGET_CPU_ZARCH" 5615 "#" 5616 "&& reload_completed" 5617 [(parallel 5618 [(set (match_dup 3) (minus:SI (match_dup 4) (match_dup 5))) 5619 (clobber (reg:CC CC_REGNUM))]) 5620 (parallel 5621 [(set (reg:CCL2 CC_REGNUM) 5622 (compare:CCL2 (minus:SI (match_dup 7) (match_dup 8)) 5623 (match_dup 7))) 5624 (set (match_dup 6) (minus:SI (match_dup 7) (match_dup 8)))]) 5625 (set (pc) 5626 (if_then_else (gtu (reg:CCL2 CC_REGNUM) (const_int 0)) 5627 (pc) 5628 (label_ref (match_dup 9)))) 5629 (parallel 5630 [(set (match_dup 3) (plus:SI (match_dup 3) (const_int -1))) 5631 (clobber (reg:CC CC_REGNUM))]) 5632 (match_dup 9)] 5633 "operands[3] = operand_subword (operands[0], 0, 0, DImode); 5634 operands[4] = operand_subword (operands[1], 0, 0, DImode); 5635 operands[5] = operand_subword (operands[2], 0, 0, DImode); 5636 operands[6] = operand_subword (operands[0], 1, 0, DImode); 5637 operands[7] = operand_subword (operands[1], 1, 0, DImode); 5638 operands[8] = operand_subword (operands[2], 1, 0, DImode); 5639 operands[9] = gen_label_rtx ();") 5640 5641; 5642; subsi3 instruction pattern(s). 5643; 5644 5645(define_expand "subsi3" 5646 [(parallel 5647 [(set (match_operand:SI 0 "register_operand" "") 5648 (minus:SI (match_operand:SI 1 "register_operand" "") 5649 (match_operand:SI 2 "general_operand" ""))) 5650 (clobber (reg:CC CC_REGNUM))])] 5651 "" 5652 "") 5653 5654(define_insn "*subsi3_sign" 5655 [(set (match_operand:SI 0 "register_operand" "=d,d") 5656 (minus:SI (match_operand:SI 1 "register_operand" "0,0") 5657 (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")))) 5658 (clobber (reg:CC CC_REGNUM))] 5659 "" 5660 "@ 5661 sh\t%0,%2 5662 shy\t%0,%2" 5663 [(set_attr "op_type" "RX,RXY") 5664 (set_attr "z196prop" "z196_cracked,z196_cracked")]) 5665 5666; 5667; sub(di|si)3 instruction pattern(s). 5668; 5669 5670; sr, s, sy, sgr, sg, srk, sgrk 5671(define_insn "*sub<mode>3" 5672 [(set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 5673 (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 5674 (match_operand:GPR 2 "general_operand" "d,d,R,T") ) ) 5675 (clobber (reg:CC CC_REGNUM))] 5676 "" 5677 "@ 5678 s<g>r\t%0,%2 5679 s<g>rk\t%0,%1,%2 5680 s<g>\t%0,%2 5681 s<y>\t%0,%2" 5682 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5683 (set_attr "cpu_facility" "*,z196,*,*") 5684 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 5685 5686; slr, sl, sly, slgr, slg, slrk, slgrk 5687(define_insn "*sub<mode>3_borrow_cc" 5688 [(set (reg CC_REGNUM) 5689 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 5690 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5691 (match_dup 1))) 5692 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 5693 (minus:GPR (match_dup 1) (match_dup 2)))] 5694 "s390_match_ccmode (insn, CCL2mode)" 5695 "@ 5696 sl<g>r\t%0,%2 5697 sl<g>rk\t%0,%1,%2 5698 sl<g>\t%0,%2 5699 sl<y>\t%0,%2" 5700 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5701 (set_attr "cpu_facility" "*,z196,*,*") 5702 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 5703 5704; slr, sl, sly, slgr, slg, slrk, slgrk 5705(define_insn "*sub<mode>3_borrow_cconly" 5706 [(set (reg CC_REGNUM) 5707 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 5708 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5709 (match_dup 1))) 5710 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5711 "s390_match_ccmode (insn, CCL2mode)" 5712 "@ 5713 sl<g>r\t%0,%2 5714 sl<g>rk\t%0,%1,%2 5715 sl<g>\t%0,%2 5716 sl<y>\t%0,%2" 5717 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5718 (set_attr "cpu_facility" "*,z196,*,*") 5719 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 5720 5721; slr, sl, sly, slgr, slg, slrk, slgrk 5722(define_insn "*sub<mode>3_cc" 5723 [(set (reg CC_REGNUM) 5724 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 5725 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5726 (const_int 0))) 5727 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 5728 (minus:GPR (match_dup 1) (match_dup 2)))] 5729 "s390_match_ccmode (insn, CCLmode)" 5730 "@ 5731 sl<g>r\t%0,%2 5732 sl<g>rk\t%0,%1,%2 5733 sl<g>\t%0,%2 5734 sl<y>\t%0,%2" 5735 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5736 (set_attr "cpu_facility" "*,z196,*,*") 5737 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 5738 5739; slr, sl, sly, slgr, slg, slrk, slgrk 5740(define_insn "*sub<mode>3_cc2" 5741 [(set (reg CC_REGNUM) 5742 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") 5743 (match_operand:GPR 2 "general_operand" "d,d,R,T"))) 5744 (set (match_operand:GPR 0 "register_operand" "=d,d,d,d") 5745 (minus:GPR (match_dup 1) (match_dup 2)))] 5746 "s390_match_ccmode (insn, CCL3mode)" 5747 "@ 5748 sl<g>r\t%0,%2 5749 sl<g>rk\t%0,%1,%2 5750 sl<g>\t%0,%2 5751 sl<y>\t%0,%2" 5752 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5753 (set_attr "cpu_facility" "*,z196,*,*") 5754 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 5755 5756; slr, sl, sly, slgr, slg, slrk, slgrk 5757(define_insn "*sub<mode>3_cconly" 5758 [(set (reg CC_REGNUM) 5759 (compare (minus:GPR (match_operand:GPR 1 "register_operand" "0,d,0,0") 5760 (match_operand:GPR 2 "general_operand" "d,d,R,T")) 5761 (const_int 0))) 5762 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5763 "s390_match_ccmode (insn, CCLmode)" 5764 "@ 5765 sl<g>r\t%0,%2 5766 sl<g>rk\t%0,%1,%2 5767 sl<g>\t%0,%2 5768 sl<y>\t%0,%2" 5769 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5770 (set_attr "cpu_facility" "*,z196,*,*") 5771 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 5772 5773 5774; slr, sl, sly, slgr, slg, slrk, slgrk 5775(define_insn "*sub<mode>3_cconly2" 5776 [(set (reg CC_REGNUM) 5777 (compare (match_operand:GPR 1 "register_operand" "0,d,0,0") 5778 (match_operand:GPR 2 "general_operand" "d,d,R,T"))) 5779 (clobber (match_scratch:GPR 0 "=d,d,d,d"))] 5780 "s390_match_ccmode (insn, CCL3mode)" 5781 "@ 5782 sl<g>r\t%0,%2 5783 sl<g>rk\t%0,%1,%2 5784 sl<g>\t%0,%2 5785 sl<y>\t%0,%2" 5786 [(set_attr "op_type" "RR<E>,RRF,RX<Y>,RXY") 5787 (set_attr "cpu_facility" "*,z196,*,*") 5788 (set_attr "z10prop" "z10_super_c_E1,*,z10_super_E1,z10_super_E1")]) 5789 5790 5791; 5792; sub(tf|df|sf|td|dd)3 instruction pattern(s). 5793; 5794 5795; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr 5796(define_insn "sub<mode>3" 5797 [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") 5798 (minus:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>") 5799 (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>"))) 5800 (clobber (reg:CC CC_REGNUM))] 5801 "TARGET_HARD_FLOAT" 5802 "@ 5803 s<xde><bt>r\t%0,<op1>%2 5804 s<xde>b\t%0,%2 5805 wfsdb\t%v0,%v1,%v2" 5806 [(set_attr "op_type" "<RRer>,RXE,VRR") 5807 (set_attr "type" "fsimp<mode>") 5808 (set_attr "cpu_facility" "*,*,vec")]) 5809 5810; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr 5811(define_insn "*sub<mode>3_cc" 5812 [(set (reg CC_REGNUM) 5813 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") 5814 (match_operand:FP 2 "general_operand" "f,<Rf>")) 5815 (match_operand:FP 3 "const0_operand" ""))) 5816 (set (match_operand:FP 0 "register_operand" "=f,f") 5817 (minus:FP (match_dup 1) (match_dup 2)))] 5818 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 5819 "@ 5820 s<xde><bt>r\t%0,<op1>%2 5821 s<xde>b\t%0,%2" 5822 [(set_attr "op_type" "<RRer>,RXE") 5823 (set_attr "type" "fsimp<mode>")]) 5824 5825; sxbr, sdbr, sebr, sdb, seb, sxtr, sdtr 5826(define_insn "*sub<mode>3_cconly" 5827 [(set (reg CC_REGNUM) 5828 (compare (minus:FP (match_operand:FP 1 "nonimmediate_operand" "<f0>,0") 5829 (match_operand:FP 2 "general_operand" "f,<Rf>")) 5830 (match_operand:FP 3 "const0_operand" ""))) 5831 (clobber (match_scratch:FP 0 "=f,f"))] 5832 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 5833 "@ 5834 s<xde><bt>r\t%0,<op1>%2 5835 s<xde>b\t%0,%2" 5836 [(set_attr "op_type" "<RRer>,RXE") 5837 (set_attr "type" "fsimp<mode>")]) 5838 5839 5840;; 5841;;- Conditional add/subtract instructions. 5842;; 5843 5844; 5845; add(di|si)cc instruction pattern(s). 5846; 5847 5848; the following 4 patterns are used when the result of an add with 5849; carry is checked for an overflow condition 5850 5851; op1 + op2 + c < op1 5852 5853; alcr, alc, alcgr, alcg 5854(define_insn "*add<mode>3_alc_carry1_cc" 5855 [(set (reg CC_REGNUM) 5856 (compare 5857 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 5858 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 5859 (match_operand:GPR 2 "general_operand" "d,RT")) 5860 (match_dup 1))) 5861 (set (match_operand:GPR 0 "register_operand" "=d,d") 5862 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] 5863 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" 5864 "@ 5865 alc<g>r\t%0,%2 5866 alc<g>\t%0,%2" 5867 [(set_attr "op_type" "RRE,RXY") 5868 (set_attr "z196prop" "z196_alone,z196_alone")]) 5869 5870; alcr, alc, alcgr, alcg 5871(define_insn "*add<mode>3_alc_carry1_cconly" 5872 [(set (reg CC_REGNUM) 5873 (compare 5874 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 5875 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 5876 (match_operand:GPR 2 "general_operand" "d,RT")) 5877 (match_dup 1))) 5878 (clobber (match_scratch:GPR 0 "=d,d"))] 5879 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" 5880 "@ 5881 alc<g>r\t%0,%2 5882 alc<g>\t%0,%2" 5883 [(set_attr "op_type" "RRE,RXY") 5884 (set_attr "z196prop" "z196_alone,z196_alone")]) 5885 5886; op1 + op2 + c < op2 5887 5888; alcr, alc, alcgr, alcg 5889(define_insn "*add<mode>3_alc_carry2_cc" 5890 [(set (reg CC_REGNUM) 5891 (compare 5892 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 5893 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 5894 (match_operand:GPR 2 "general_operand" "d,RT")) 5895 (match_dup 2))) 5896 (set (match_operand:GPR 0 "register_operand" "=d,d") 5897 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] 5898 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" 5899 "@ 5900 alc<g>r\t%0,%2 5901 alc<g>\t%0,%2" 5902 [(set_attr "op_type" "RRE,RXY")]) 5903 5904; alcr, alc, alcgr, alcg 5905(define_insn "*add<mode>3_alc_carry2_cconly" 5906 [(set (reg CC_REGNUM) 5907 (compare 5908 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 5909 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 5910 (match_operand:GPR 2 "general_operand" "d,RT")) 5911 (match_dup 2))) 5912 (clobber (match_scratch:GPR 0 "=d,d"))] 5913 "s390_match_ccmode (insn, CCL1mode) && TARGET_CPU_ZARCH" 5914 "@ 5915 alc<g>r\t%0,%2 5916 alc<g>\t%0,%2" 5917 [(set_attr "op_type" "RRE,RXY")]) 5918 5919; alcr, alc, alcgr, alcg 5920(define_insn "*add<mode>3_alc_cc" 5921 [(set (reg CC_REGNUM) 5922 (compare 5923 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 5924 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 5925 (match_operand:GPR 2 "general_operand" "d,RT")) 5926 (const_int 0))) 5927 (set (match_operand:GPR 0 "register_operand" "=d,d") 5928 (plus:GPR (plus:GPR (match_dup 3) (match_dup 1)) (match_dup 2)))] 5929 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" 5930 "@ 5931 alc<g>r\t%0,%2 5932 alc<g>\t%0,%2" 5933 [(set_attr "op_type" "RRE,RXY")]) 5934 5935; alcr, alc, alcgr, alcg 5936(define_insn "*add<mode>3_alc" 5937 [(set (match_operand:GPR 0 "register_operand" "=d,d") 5938 (plus:GPR (plus:GPR (match_operand:GPR 3 "s390_alc_comparison" "") 5939 (match_operand:GPR 1 "nonimmediate_operand" "%0,0")) 5940 (match_operand:GPR 2 "general_operand" "d,RT"))) 5941 (clobber (reg:CC CC_REGNUM))] 5942 "TARGET_CPU_ZARCH" 5943 "@ 5944 alc<g>r\t%0,%2 5945 alc<g>\t%0,%2" 5946 [(set_attr "op_type" "RRE,RXY")]) 5947 5948; slbr, slb, slbgr, slbg 5949(define_insn "*sub<mode>3_slb_cc" 5950 [(set (reg CC_REGNUM) 5951 (compare 5952 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") 5953 (match_operand:GPR 2 "general_operand" "d,RT")) 5954 (match_operand:GPR 3 "s390_slb_comparison" "")) 5955 (const_int 0))) 5956 (set (match_operand:GPR 0 "register_operand" "=d,d") 5957 (minus:GPR (minus:GPR (match_dup 1) (match_dup 2)) (match_dup 3)))] 5958 "s390_match_ccmode (insn, CCLmode) && TARGET_CPU_ZARCH" 5959 "@ 5960 slb<g>r\t%0,%2 5961 slb<g>\t%0,%2" 5962 [(set_attr "op_type" "RRE,RXY") 5963 (set_attr "z10prop" "z10_c,*")]) 5964 5965; slbr, slb, slbgr, slbg 5966(define_insn "*sub<mode>3_slb" 5967 [(set (match_operand:GPR 0 "register_operand" "=d,d") 5968 (minus:GPR (minus:GPR (match_operand:GPR 1 "nonimmediate_operand" "0,0") 5969 (match_operand:GPR 2 "general_operand" "d,RT")) 5970 (match_operand:GPR 3 "s390_slb_comparison" ""))) 5971 (clobber (reg:CC CC_REGNUM))] 5972 "TARGET_CPU_ZARCH" 5973 "@ 5974 slb<g>r\t%0,%2 5975 slb<g>\t%0,%2" 5976 [(set_attr "op_type" "RRE,RXY") 5977 (set_attr "z10prop" "z10_c,*")]) 5978 5979(define_expand "add<mode>cc" 5980 [(match_operand:GPR 0 "register_operand" "") 5981 (match_operand 1 "comparison_operator" "") 5982 (match_operand:GPR 2 "register_operand" "") 5983 (match_operand:GPR 3 "const_int_operand" "")] 5984 "TARGET_CPU_ZARCH" 5985 "if (!s390_expand_addcc (GET_CODE (operands[1]), 5986 XEXP (operands[1], 0), XEXP (operands[1], 1), 5987 operands[0], operands[2], 5988 operands[3])) FAIL; DONE;") 5989 5990; 5991; scond instruction pattern(s). 5992; 5993 5994(define_insn_and_split "*scond<mode>" 5995 [(set (match_operand:GPR 0 "register_operand" "=&d") 5996 (match_operand:GPR 1 "s390_alc_comparison" "")) 5997 (clobber (reg:CC CC_REGNUM))] 5998 "TARGET_CPU_ZARCH" 5999 "#" 6000 "&& reload_completed" 6001 [(set (match_dup 0) (const_int 0)) 6002 (parallel 6003 [(set (match_dup 0) (plus:GPR (plus:GPR (match_dup 1) (match_dup 0)) 6004 (match_dup 0))) 6005 (clobber (reg:CC CC_REGNUM))])] 6006 "") 6007 6008(define_insn_and_split "*scond<mode>_neg" 6009 [(set (match_operand:GPR 0 "register_operand" "=&d") 6010 (match_operand:GPR 1 "s390_slb_comparison" "")) 6011 (clobber (reg:CC CC_REGNUM))] 6012 "TARGET_CPU_ZARCH" 6013 "#" 6014 "&& reload_completed" 6015 [(set (match_dup 0) (const_int 0)) 6016 (parallel 6017 [(set (match_dup 0) (minus:GPR (minus:GPR (match_dup 0) (match_dup 0)) 6018 (match_dup 1))) 6019 (clobber (reg:CC CC_REGNUM))]) 6020 (parallel 6021 [(set (match_dup 0) (neg:GPR (match_dup 0))) 6022 (clobber (reg:CC CC_REGNUM))])] 6023 "") 6024 6025 6026(define_expand "cstore<mode>4" 6027 [(set (match_operand:SI 0 "register_operand" "") 6028 (match_operator:SI 1 "s390_scond_operator" 6029 [(match_operand:GPR 2 "register_operand" "") 6030 (match_operand:GPR 3 "general_operand" "")]))] 6031 "TARGET_CPU_ZARCH" 6032 "if (!s390_expand_addcc (GET_CODE (operands[1]), operands[2], operands[3], 6033 operands[0], const0_rtx, const1_rtx)) FAIL; DONE;") 6034 6035(define_expand "cstorecc4" 6036 [(parallel 6037 [(set (match_operand:SI 0 "register_operand" "") 6038 (match_operator:SI 1 "s390_eqne_operator" 6039 [(match_operand:CCZ1 2 "register_operand") 6040 (match_operand 3 "const0_operand")])) 6041 (clobber (reg:CC CC_REGNUM))])] 6042 "" 6043 "emit_insn (gen_sne (operands[0], operands[2])); 6044 if (GET_CODE (operands[1]) == EQ) 6045 emit_insn (gen_xorsi3 (operands[0], operands[0], const1_rtx)); 6046 DONE;") 6047 6048(define_insn_and_split "sne" 6049 [(set (match_operand:SI 0 "register_operand" "=d") 6050 (ne:SI (match_operand:CCZ1 1 "register_operand" "0") 6051 (const_int 0))) 6052 (clobber (reg:CC CC_REGNUM))] 6053 "" 6054 "#" 6055 "reload_completed" 6056 [(parallel 6057 [(set (match_dup 0) (ashiftrt:SI (match_dup 0) (const_int 28))) 6058 (clobber (reg:CC CC_REGNUM))])]) 6059 6060 6061;; 6062;; - Conditional move instructions (introduced with z196) 6063;; 6064 6065(define_expand "mov<mode>cc" 6066 [(set (match_operand:GPR 0 "nonimmediate_operand" "") 6067 (if_then_else:GPR (match_operand 1 "comparison_operator" "") 6068 (match_operand:GPR 2 "nonimmediate_operand" "") 6069 (match_operand:GPR 3 "nonimmediate_operand" "")))] 6070 "TARGET_Z196" 6071{ 6072 /* Emit the comparison insn in case we do not already have a comparison result. */ 6073 if (!s390_comparison (operands[1], VOIDmode)) 6074 operands[1] = s390_emit_compare (GET_CODE (operands[1]), 6075 XEXP (operands[1], 0), 6076 XEXP (operands[1], 1)); 6077}) 6078 6079; locr, loc, stoc, locgr, locg, stocg 6080(define_insn_and_split "*mov<mode>cc" 6081 [(set (match_operand:GPR 0 "nonimmediate_operand" "=d,d, d, d,QS,QS,&d") 6082 (if_then_else:GPR 6083 (match_operator 1 "s390_comparison" 6084 [(match_operand 2 "cc_reg_operand" " c,c, c, c, c, c, c") 6085 (match_operand 5 "const_int_operand" "")]) 6086 (match_operand:GPR 3 "nonimmediate_operand" " d,0,QS, 0, d, 0,QS") 6087 (match_operand:GPR 4 "nonimmediate_operand" " 0,d, 0,QS, 0, d,QS")))] 6088 "TARGET_Z196" 6089 "@ 6090 loc<g>r%C1\t%0,%3 6091 loc<g>r%D1\t%0,%4 6092 loc<g>%C1\t%0,%3 6093 loc<g>%D1\t%0,%4 6094 stoc<g>%C1\t%3,%0 6095 stoc<g>%D1\t%4,%0 6096 #" 6097 "&& reload_completed 6098 && MEM_P (operands[3]) && MEM_P (operands[4])" 6099 [(set (match_dup 0) 6100 (if_then_else:GPR 6101 (match_op_dup 1 [(match_dup 2) (const_int 0)]) 6102 (match_dup 3) 6103 (match_dup 0))) 6104 (set (match_dup 0) 6105 (if_then_else:GPR 6106 (match_op_dup 1 [(match_dup 2) (const_int 0)]) 6107 (match_dup 0) 6108 (match_dup 4)))] 6109 "" 6110 [(set_attr "op_type" "RRF,RRF,RSY,RSY,RSY,RSY,*")]) 6111 6112;; 6113;;- Multiply instructions. 6114;; 6115 6116; 6117; muldi3 instruction pattern(s). 6118; 6119 6120(define_insn "*muldi3_sign" 6121 [(set (match_operand:DI 0 "register_operand" "=d,d") 6122 (mult:DI (sign_extend:DI (match_operand:SI 2 "general_operand" "d,RT")) 6123 (match_operand:DI 1 "register_operand" "0,0")))] 6124 "TARGET_ZARCH" 6125 "@ 6126 msgfr\t%0,%2 6127 msgf\t%0,%2" 6128 [(set_attr "op_type" "RRE,RXY") 6129 (set_attr "type" "imuldi")]) 6130 6131(define_insn "muldi3" 6132 [(set (match_operand:DI 0 "register_operand" "=d,d,d,d") 6133 (mult:DI (match_operand:DI 1 "nonimmediate_operand" "%0,0,0,0") 6134 (match_operand:DI 2 "general_operand" "d,K,RT,Os")))] 6135 "TARGET_ZARCH" 6136 "@ 6137 msgr\t%0,%2 6138 mghi\t%0,%h2 6139 msg\t%0,%2 6140 msgfi\t%0,%2" 6141 [(set_attr "op_type" "RRE,RI,RXY,RIL") 6142 (set_attr "type" "imuldi") 6143 (set_attr "cpu_facility" "*,*,*,z10")]) 6144 6145; 6146; mulsi3 instruction pattern(s). 6147; 6148 6149(define_insn "*mulsi3_sign" 6150 [(set (match_operand:SI 0 "register_operand" "=d,d") 6151 (mult:SI (sign_extend:SI (match_operand:HI 2 "memory_operand" "R,T")) 6152 (match_operand:SI 1 "register_operand" "0,0")))] 6153 "" 6154 "@ 6155 mh\t%0,%2 6156 mhy\t%0,%2" 6157 [(set_attr "op_type" "RX,RXY") 6158 (set_attr "type" "imulhi") 6159 (set_attr "cpu_facility" "*,z10")]) 6160 6161(define_insn "mulsi3" 6162 [(set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") 6163 (mult:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0,0") 6164 (match_operand:SI 2 "general_operand" "d,K,R,T,Os")))] 6165 "" 6166 "@ 6167 msr\t%0,%2 6168 mhi\t%0,%h2 6169 ms\t%0,%2 6170 msy\t%0,%2 6171 msfi\t%0,%2" 6172 [(set_attr "op_type" "RRE,RI,RX,RXY,RIL") 6173 (set_attr "type" "imulsi,imulhi,imulsi,imulsi,imulsi") 6174 (set_attr "cpu_facility" "*,*,*,*,z10")]) 6175 6176; 6177; mulsidi3 instruction pattern(s). 6178; 6179 6180(define_insn "mulsidi3" 6181 [(set (match_operand:DI 0 "register_operand" "=d,d,d") 6182 (mult:DI (sign_extend:DI 6183 (match_operand:SI 1 "register_operand" "%0,0,0")) 6184 (sign_extend:DI 6185 (match_operand:SI 2 "nonimmediate_operand" "d,R,T"))))] 6186 "!TARGET_ZARCH" 6187 "@ 6188 mr\t%0,%2 6189 m\t%0,%2 6190 mfy\t%0,%2" 6191 [(set_attr "op_type" "RR,RX,RXY") 6192 (set_attr "type" "imulsi") 6193 (set_attr "cpu_facility" "*,*,z10")]) 6194 6195; 6196; umul instruction pattern(s). 6197; 6198 6199; mlr, ml, mlgr, mlg 6200(define_insn "umul<dwh><mode>3" 6201 [(set (match_operand:DW 0 "register_operand" "=d, d") 6202 (mult:DW (zero_extend:DW 6203 (match_operand:<DWH> 1 "register_operand" "%0, 0")) 6204 (zero_extend:DW 6205 (match_operand:<DWH> 2 "nonimmediate_operand" " d,RT"))))] 6206 "TARGET_CPU_ZARCH" 6207 "@ 6208 ml<tg>r\t%0,%2 6209 ml<tg>\t%0,%2" 6210 [(set_attr "op_type" "RRE,RXY") 6211 (set_attr "type" "imul<dwh>")]) 6212 6213; 6214; mul(tf|df|sf|td|dd)3 instruction pattern(s). 6215; 6216 6217; mxbr, mdbr, meebr, mxb, mxb, meeb, mdtr, mxtr 6218(define_insn "mul<mode>3" 6219 [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") 6220 (mult:FP (match_operand:FP 1 "nonimmediate_operand" "%<f0>, 0,<v0>") 6221 (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))] 6222 "TARGET_HARD_FLOAT" 6223 "@ 6224 m<xdee><bt>r\t%0,<op1>%2 6225 m<xdee>b\t%0,%2 6226 wfmdb\t%v0,%v1,%v2" 6227 [(set_attr "op_type" "<RRer>,RXE,VRR") 6228 (set_attr "type" "fmul<mode>") 6229 (set_attr "cpu_facility" "*,*,vec")]) 6230 6231; madbr, maebr, maxb, madb, maeb 6232(define_insn "fma<mode>4" 6233 [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>") 6234 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>") 6235 (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>") 6236 (match_operand:DSF 3 "register_operand" "0,0,<v0>")))] 6237 "TARGET_HARD_FLOAT" 6238 "@ 6239 ma<xde>br\t%0,%1,%2 6240 ma<xde>b\t%0,%1,%2 6241 wfmadb\t%v0,%v1,%v2,%v3" 6242 [(set_attr "op_type" "RRE,RXE,VRR") 6243 (set_attr "type" "fmadd<mode>") 6244 (set_attr "cpu_facility" "*,*,vec")]) 6245 6246; msxbr, msdbr, msebr, msxb, msdb, mseb 6247(define_insn "fms<mode>4" 6248 [(set (match_operand:DSF 0 "register_operand" "=f,f,<vf>") 6249 (fma:DSF (match_operand:DSF 1 "nonimmediate_operand" "%f,f,<vf>") 6250 (match_operand:DSF 2 "nonimmediate_operand" "f,R,<vf>") 6251 (neg:DSF (match_operand:DSF 3 "register_operand" "0,0,<v0>"))))] 6252 "TARGET_HARD_FLOAT" 6253 "@ 6254 ms<xde>br\t%0,%1,%2 6255 ms<xde>b\t%0,%1,%2 6256 wfmsdb\t%v0,%v1,%v2,%v3" 6257 [(set_attr "op_type" "RRE,RXE,VRR") 6258 (set_attr "type" "fmadd<mode>") 6259 (set_attr "cpu_facility" "*,*,vec")]) 6260 6261;; 6262;;- Divide and modulo instructions. 6263;; 6264 6265; 6266; divmoddi4 instruction pattern(s). 6267; 6268 6269(define_expand "divmoddi4" 6270 [(parallel [(set (match_operand:DI 0 "general_operand" "") 6271 (div:DI (match_operand:DI 1 "register_operand" "") 6272 (match_operand:DI 2 "general_operand" ""))) 6273 (set (match_operand:DI 3 "general_operand" "") 6274 (mod:DI (match_dup 1) (match_dup 2)))]) 6275 (clobber (match_dup 4))] 6276 "TARGET_ZARCH" 6277{ 6278 rtx insn, div_equal, mod_equal; 6279 6280 div_equal = gen_rtx_DIV (DImode, operands[1], operands[2]); 6281 mod_equal = gen_rtx_MOD (DImode, operands[1], operands[2]); 6282 6283 operands[4] = gen_reg_rtx(TImode); 6284 emit_insn (gen_divmodtidi3 (operands[4], operands[1], operands[2])); 6285 6286 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 6287 set_unique_reg_note (insn, REG_EQUAL, div_equal); 6288 6289 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 6290 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 6291 6292 DONE; 6293}) 6294 6295(define_insn "divmodtidi3" 6296 [(set (match_operand:TI 0 "register_operand" "=d,d") 6297 (ior:TI 6298 (ashift:TI 6299 (zero_extend:TI 6300 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 6301 (match_operand:DI 2 "general_operand" "d,RT"))) 6302 (const_int 64)) 6303 (zero_extend:TI (div:DI (match_dup 1) (match_dup 2)))))] 6304 "TARGET_ZARCH" 6305 "@ 6306 dsgr\t%0,%2 6307 dsg\t%0,%2" 6308 [(set_attr "op_type" "RRE,RXY") 6309 (set_attr "type" "idiv")]) 6310 6311(define_insn "divmodtisi3" 6312 [(set (match_operand:TI 0 "register_operand" "=d,d") 6313 (ior:TI 6314 (ashift:TI 6315 (zero_extend:TI 6316 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 6317 (sign_extend:DI 6318 (match_operand:SI 2 "nonimmediate_operand" "d,RT")))) 6319 (const_int 64)) 6320 (zero_extend:TI 6321 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2))))))] 6322 "TARGET_ZARCH" 6323 "@ 6324 dsgfr\t%0,%2 6325 dsgf\t%0,%2" 6326 [(set_attr "op_type" "RRE,RXY") 6327 (set_attr "type" "idiv")]) 6328 6329; 6330; udivmoddi4 instruction pattern(s). 6331; 6332 6333(define_expand "udivmoddi4" 6334 [(parallel [(set (match_operand:DI 0 "general_operand" "") 6335 (udiv:DI (match_operand:DI 1 "general_operand" "") 6336 (match_operand:DI 2 "nonimmediate_operand" ""))) 6337 (set (match_operand:DI 3 "general_operand" "") 6338 (umod:DI (match_dup 1) (match_dup 2)))]) 6339 (clobber (match_dup 4))] 6340 "TARGET_ZARCH" 6341{ 6342 rtx insn, div_equal, mod_equal, equal; 6343 6344 div_equal = gen_rtx_UDIV (DImode, operands[1], operands[2]); 6345 mod_equal = gen_rtx_UMOD (DImode, operands[1], operands[2]); 6346 equal = gen_rtx_IOR (TImode, 6347 gen_rtx_ASHIFT (TImode, 6348 gen_rtx_ZERO_EXTEND (TImode, mod_equal), 6349 GEN_INT (64)), 6350 gen_rtx_ZERO_EXTEND (TImode, div_equal)); 6351 6352 operands[4] = gen_reg_rtx(TImode); 6353 emit_clobber (operands[4]); 6354 emit_move_insn (gen_lowpart (DImode, operands[4]), operands[1]); 6355 emit_move_insn (gen_highpart (DImode, operands[4]), const0_rtx); 6356 6357 insn = emit_insn (gen_udivmodtidi3 (operands[4], operands[4], operands[2])); 6358 set_unique_reg_note (insn, REG_EQUAL, equal); 6359 6360 insn = emit_move_insn (operands[0], gen_lowpart (DImode, operands[4])); 6361 set_unique_reg_note (insn, REG_EQUAL, div_equal); 6362 6363 insn = emit_move_insn (operands[3], gen_highpart (DImode, operands[4])); 6364 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 6365 6366 DONE; 6367}) 6368 6369(define_insn "udivmodtidi3" 6370 [(set (match_operand:TI 0 "register_operand" "=d,d") 6371 (ior:TI 6372 (ashift:TI 6373 (zero_extend:TI 6374 (truncate:DI 6375 (umod:TI (match_operand:TI 1 "register_operand" "0,0") 6376 (zero_extend:TI 6377 (match_operand:DI 2 "nonimmediate_operand" "d,RT"))))) 6378 (const_int 64)) 6379 (zero_extend:TI 6380 (truncate:DI 6381 (udiv:TI (match_dup 1) (zero_extend:TI (match_dup 2)))))))] 6382 "TARGET_ZARCH" 6383 "@ 6384 dlgr\t%0,%2 6385 dlg\t%0,%2" 6386 [(set_attr "op_type" "RRE,RXY") 6387 (set_attr "type" "idiv")]) 6388 6389; 6390; divmodsi4 instruction pattern(s). 6391; 6392 6393(define_expand "divmodsi4" 6394 [(parallel [(set (match_operand:SI 0 "general_operand" "") 6395 (div:SI (match_operand:SI 1 "general_operand" "") 6396 (match_operand:SI 2 "nonimmediate_operand" ""))) 6397 (set (match_operand:SI 3 "general_operand" "") 6398 (mod:SI (match_dup 1) (match_dup 2)))]) 6399 (clobber (match_dup 4))] 6400 "!TARGET_ZARCH" 6401{ 6402 rtx insn, div_equal, mod_equal, equal; 6403 6404 div_equal = gen_rtx_DIV (SImode, operands[1], operands[2]); 6405 mod_equal = gen_rtx_MOD (SImode, operands[1], operands[2]); 6406 equal = gen_rtx_IOR (DImode, 6407 gen_rtx_ASHIFT (DImode, 6408 gen_rtx_ZERO_EXTEND (DImode, mod_equal), 6409 GEN_INT (32)), 6410 gen_rtx_ZERO_EXTEND (DImode, div_equal)); 6411 6412 operands[4] = gen_reg_rtx(DImode); 6413 emit_insn (gen_extendsidi2 (operands[4], operands[1])); 6414 6415 insn = emit_insn (gen_divmoddisi3 (operands[4], operands[4], operands[2])); 6416 set_unique_reg_note (insn, REG_EQUAL, equal); 6417 6418 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); 6419 set_unique_reg_note (insn, REG_EQUAL, div_equal); 6420 6421 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); 6422 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 6423 6424 DONE; 6425}) 6426 6427(define_insn "divmoddisi3" 6428 [(set (match_operand:DI 0 "register_operand" "=d,d") 6429 (ior:DI 6430 (ashift:DI 6431 (zero_extend:DI 6432 (truncate:SI 6433 (mod:DI (match_operand:DI 1 "register_operand" "0,0") 6434 (sign_extend:DI 6435 (match_operand:SI 2 "nonimmediate_operand" "d,R"))))) 6436 (const_int 32)) 6437 (zero_extend:DI 6438 (truncate:SI 6439 (div:DI (match_dup 1) (sign_extend:DI (match_dup 2)))))))] 6440 "!TARGET_ZARCH" 6441 "@ 6442 dr\t%0,%2 6443 d\t%0,%2" 6444 [(set_attr "op_type" "RR,RX") 6445 (set_attr "type" "idiv")]) 6446 6447; 6448; udivsi3 and umodsi3 instruction pattern(s). 6449; 6450 6451(define_expand "udivmodsi4" 6452 [(parallel [(set (match_operand:SI 0 "general_operand" "") 6453 (udiv:SI (match_operand:SI 1 "general_operand" "") 6454 (match_operand:SI 2 "nonimmediate_operand" ""))) 6455 (set (match_operand:SI 3 "general_operand" "") 6456 (umod:SI (match_dup 1) (match_dup 2)))]) 6457 (clobber (match_dup 4))] 6458 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 6459{ 6460 rtx insn, div_equal, mod_equal, equal; 6461 6462 div_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 6463 mod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 6464 equal = gen_rtx_IOR (DImode, 6465 gen_rtx_ASHIFT (DImode, 6466 gen_rtx_ZERO_EXTEND (DImode, mod_equal), 6467 GEN_INT (32)), 6468 gen_rtx_ZERO_EXTEND (DImode, div_equal)); 6469 6470 operands[4] = gen_reg_rtx(DImode); 6471 emit_clobber (operands[4]); 6472 emit_move_insn (gen_lowpart (SImode, operands[4]), operands[1]); 6473 emit_move_insn (gen_highpart (SImode, operands[4]), const0_rtx); 6474 6475 insn = emit_insn (gen_udivmoddisi3 (operands[4], operands[4], operands[2])); 6476 set_unique_reg_note (insn, REG_EQUAL, equal); 6477 6478 insn = emit_move_insn (operands[0], gen_lowpart (SImode, operands[4])); 6479 set_unique_reg_note (insn, REG_EQUAL, div_equal); 6480 6481 insn = emit_move_insn (operands[3], gen_highpart (SImode, operands[4])); 6482 set_unique_reg_note (insn, REG_EQUAL, mod_equal); 6483 6484 DONE; 6485}) 6486 6487(define_insn "udivmoddisi3" 6488 [(set (match_operand:DI 0 "register_operand" "=d,d") 6489 (ior:DI 6490 (ashift:DI 6491 (zero_extend:DI 6492 (truncate:SI 6493 (umod:DI (match_operand:DI 1 "register_operand" "0,0") 6494 (zero_extend:DI 6495 (match_operand:SI 2 "nonimmediate_operand" "d,RT"))))) 6496 (const_int 32)) 6497 (zero_extend:DI 6498 (truncate:SI 6499 (udiv:DI (match_dup 1) (zero_extend:DI (match_dup 2)))))))] 6500 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 6501 "@ 6502 dlr\t%0,%2 6503 dl\t%0,%2" 6504 [(set_attr "op_type" "RRE,RXY") 6505 (set_attr "type" "idiv")]) 6506 6507(define_expand "udivsi3" 6508 [(set (match_operand:SI 0 "register_operand" "=d") 6509 (udiv:SI (match_operand:SI 1 "general_operand" "") 6510 (match_operand:SI 2 "general_operand" ""))) 6511 (clobber (match_dup 3))] 6512 "!TARGET_ZARCH && !TARGET_CPU_ZARCH" 6513{ 6514 rtx insn, udiv_equal, umod_equal, equal; 6515 6516 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 6517 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 6518 equal = gen_rtx_IOR (DImode, 6519 gen_rtx_ASHIFT (DImode, 6520 gen_rtx_ZERO_EXTEND (DImode, umod_equal), 6521 GEN_INT (32)), 6522 gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); 6523 6524 operands[3] = gen_reg_rtx (DImode); 6525 6526 if (CONSTANT_P (operands[2])) 6527 { 6528 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) < 0) 6529 { 6530 rtx_code_label *label1 = gen_label_rtx (); 6531 6532 operands[1] = make_safe_from (operands[1], operands[0]); 6533 emit_move_insn (operands[0], const0_rtx); 6534 emit_cmp_and_jump_insns (operands[1], operands[2], LT, NULL_RTX, 6535 SImode, 1, label1); 6536 emit_move_insn (operands[0], const1_rtx); 6537 emit_label (label1); 6538 } 6539 else 6540 { 6541 operands[2] = force_reg (SImode, operands[2]); 6542 operands[2] = make_safe_from (operands[2], operands[0]); 6543 6544 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 6545 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 6546 operands[2])); 6547 set_unique_reg_note (insn, REG_EQUAL, equal); 6548 6549 insn = emit_move_insn (operands[0], 6550 gen_lowpart (SImode, operands[3])); 6551 set_unique_reg_note (insn, REG_EQUAL, udiv_equal); 6552 } 6553 } 6554 else 6555 { 6556 rtx_code_label *label1 = gen_label_rtx (); 6557 rtx_code_label *label2 = gen_label_rtx (); 6558 rtx_code_label *label3 = gen_label_rtx (); 6559 6560 operands[1] = force_reg (SImode, operands[1]); 6561 operands[1] = make_safe_from (operands[1], operands[0]); 6562 operands[2] = force_reg (SImode, operands[2]); 6563 operands[2] = make_safe_from (operands[2], operands[0]); 6564 6565 emit_move_insn (operands[0], const0_rtx); 6566 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, 6567 SImode, 1, label3); 6568 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, 6569 SImode, 0, label2); 6570 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, 6571 SImode, 0, label1); 6572 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 6573 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 6574 operands[2])); 6575 set_unique_reg_note (insn, REG_EQUAL, equal); 6576 6577 insn = emit_move_insn (operands[0], 6578 gen_lowpart (SImode, operands[3])); 6579 set_unique_reg_note (insn, REG_EQUAL, udiv_equal); 6580 6581 emit_jump (label3); 6582 emit_label (label1); 6583 emit_move_insn (operands[0], operands[1]); 6584 emit_jump (label3); 6585 emit_label (label2); 6586 emit_move_insn (operands[0], const1_rtx); 6587 emit_label (label3); 6588 } 6589 emit_move_insn (operands[0], operands[0]); 6590 DONE; 6591}) 6592 6593(define_expand "umodsi3" 6594 [(set (match_operand:SI 0 "register_operand" "=d") 6595 (umod:SI (match_operand:SI 1 "nonimmediate_operand" "") 6596 (match_operand:SI 2 "nonimmediate_operand" ""))) 6597 (clobber (match_dup 3))] 6598 "!TARGET_ZARCH && !TARGET_CPU_ZARCH" 6599{ 6600 rtx insn, udiv_equal, umod_equal, equal; 6601 6602 udiv_equal = gen_rtx_UDIV (SImode, operands[1], operands[2]); 6603 umod_equal = gen_rtx_UMOD (SImode, operands[1], operands[2]); 6604 equal = gen_rtx_IOR (DImode, 6605 gen_rtx_ASHIFT (DImode, 6606 gen_rtx_ZERO_EXTEND (DImode, umod_equal), 6607 GEN_INT (32)), 6608 gen_rtx_ZERO_EXTEND (DImode, udiv_equal)); 6609 6610 operands[3] = gen_reg_rtx (DImode); 6611 6612 if (CONSTANT_P (operands[2])) 6613 { 6614 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) <= 0) 6615 { 6616 rtx_code_label *label1 = gen_label_rtx (); 6617 6618 operands[1] = make_safe_from (operands[1], operands[0]); 6619 emit_move_insn (operands[0], operands[1]); 6620 emit_cmp_and_jump_insns (operands[0], operands[2], LT, NULL_RTX, 6621 SImode, 1, label1); 6622 emit_insn (gen_abssi2 (operands[0], operands[2])); 6623 emit_insn (gen_addsi3 (operands[0], operands[0], operands[1])); 6624 emit_label (label1); 6625 } 6626 else 6627 { 6628 operands[2] = force_reg (SImode, operands[2]); 6629 operands[2] = make_safe_from (operands[2], operands[0]); 6630 6631 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 6632 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 6633 operands[2])); 6634 set_unique_reg_note (insn, REG_EQUAL, equal); 6635 6636 insn = emit_move_insn (operands[0], 6637 gen_highpart (SImode, operands[3])); 6638 set_unique_reg_note (insn, REG_EQUAL, umod_equal); 6639 } 6640 } 6641 else 6642 { 6643 rtx_code_label *label1 = gen_label_rtx (); 6644 rtx_code_label *label2 = gen_label_rtx (); 6645 rtx_code_label *label3 = gen_label_rtx (); 6646 6647 operands[1] = force_reg (SImode, operands[1]); 6648 operands[1] = make_safe_from (operands[1], operands[0]); 6649 operands[2] = force_reg (SImode, operands[2]); 6650 operands[2] = make_safe_from (operands[2], operands[0]); 6651 6652 emit_move_insn(operands[0], operands[1]); 6653 emit_cmp_and_jump_insns (operands[2], operands[1], GT, NULL_RTX, 6654 SImode, 1, label3); 6655 emit_cmp_and_jump_insns (operands[2], const0_rtx, LT, NULL_RTX, 6656 SImode, 0, label2); 6657 emit_cmp_and_jump_insns (operands[2], const1_rtx, EQ, NULL_RTX, 6658 SImode, 0, label1); 6659 emit_insn (gen_zero_extendsidi2 (operands[3], operands[1])); 6660 insn = emit_insn (gen_divmoddisi3 (operands[3], operands[3], 6661 operands[2])); 6662 set_unique_reg_note (insn, REG_EQUAL, equal); 6663 6664 insn = emit_move_insn (operands[0], 6665 gen_highpart (SImode, operands[3])); 6666 set_unique_reg_note (insn, REG_EQUAL, umod_equal); 6667 6668 emit_jump (label3); 6669 emit_label (label1); 6670 emit_move_insn (operands[0], const0_rtx); 6671 emit_jump (label3); 6672 emit_label (label2); 6673 emit_insn (gen_subsi3 (operands[0], operands[0], operands[2])); 6674 emit_label (label3); 6675 } 6676 DONE; 6677}) 6678 6679; 6680; div(df|sf)3 instruction pattern(s). 6681; 6682 6683; dxbr, ddbr, debr, dxb, ddb, deb, ddtr, dxtr 6684(define_insn "div<mode>3" 6685 [(set (match_operand:FP 0 "register_operand" "=f, f,<vf>") 6686 (div:FP (match_operand:FP 1 "register_operand" "<f0>, 0,<v0>") 6687 (match_operand:FP 2 "general_operand" "f,<Rf>,<vf>")))] 6688 "TARGET_HARD_FLOAT" 6689 "@ 6690 d<xde><bt>r\t%0,<op1>%2 6691 d<xde>b\t%0,%2 6692 wfddb\t%v0,%v1,%v2" 6693 [(set_attr "op_type" "<RRer>,RXE,VRR") 6694 (set_attr "type" "fdiv<mode>") 6695 (set_attr "cpu_facility" "*,*,vec")]) 6696 6697 6698;; 6699;;- And instructions. 6700;; 6701 6702(define_expand "and<mode>3" 6703 [(set (match_operand:INT 0 "nonimmediate_operand" "") 6704 (and:INT (match_operand:INT 1 "nonimmediate_operand" "") 6705 (match_operand:INT 2 "general_operand" ""))) 6706 (clobber (reg:CC CC_REGNUM))] 6707 "" 6708 "s390_expand_logical_operator (AND, <MODE>mode, operands); DONE;") 6709 6710; 6711; anddi3 instruction pattern(s). 6712; 6713 6714(define_insn "*anddi3_cc" 6715 [(set (reg CC_REGNUM) 6716 (compare 6717 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") 6718 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) 6719 (const_int 0))) 6720 (set (match_operand:DI 0 "register_operand" "=d,d, d, d") 6721 (and:DI (match_dup 1) (match_dup 2)))] 6722 "TARGET_ZARCH && s390_match_ccmode(insn, CCTmode)" 6723 "@ 6724 ngr\t%0,%2 6725 ngrk\t%0,%1,%2 6726 ng\t%0,%2 6727 risbg\t%0,%1,%s2,128+%e2,0" 6728 [(set_attr "op_type" "RRE,RRF,RXY,RIE") 6729 (set_attr "cpu_facility" "*,z196,*,z10") 6730 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 6731 6732(define_insn "*anddi3_cconly" 6733 [(set (reg CC_REGNUM) 6734 (compare 6735 (and:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0, d") 6736 (match_operand:DI 2 "general_operand" " d,d,RT,NxxDq")) 6737 (const_int 0))) 6738 (clobber (match_scratch:DI 0 "=d,d, d, d"))] 6739 "TARGET_ZARCH 6740 && s390_match_ccmode(insn, CCTmode) 6741 /* Do not steal TM patterns. */ 6742 && s390_single_part (operands[2], DImode, HImode, 0) < 0" 6743 "@ 6744 ngr\t%0,%2 6745 ngrk\t%0,%1,%2 6746 ng\t%0,%2 6747 risbg\t%0,%1,%s2,128+%e2,0" 6748 [(set_attr "op_type" "RRE,RRF,RXY,RIE") 6749 (set_attr "cpu_facility" "*,z196,*,z10") 6750 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super_E1")]) 6751 6752(define_insn "*anddi3" 6753 [(set (match_operand:DI 0 "nonimmediate_operand" 6754 "=d,d, d, d, d, d, d, d,d,d, d, d, AQ,Q") 6755 (and:DI 6756 (match_operand:DI 1 "nonimmediate_operand" 6757 "%d,o, 0, 0, 0, 0, 0, 0,0,d, 0, d, 0,0") 6758 (match_operand:DI 2 "general_operand" 6759 "M, M,N0HDF,N1HDF,N2HDF,N3HDF,N0SDF,N1SDF,d,d,RT,NxxDq,NxQDF,Q"))) 6760 (clobber (reg:CC CC_REGNUM))] 6761 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 6762 "@ 6763 # 6764 # 6765 nihh\t%0,%j2 6766 nihl\t%0,%j2 6767 nilh\t%0,%j2 6768 nill\t%0,%j2 6769 nihf\t%0,%m2 6770 nilf\t%0,%m2 6771 ngr\t%0,%2 6772 ngrk\t%0,%1,%2 6773 ng\t%0,%2 6774 risbg\t%0,%1,%s2,128+%e2,0 6775 # 6776 #" 6777 [(set_attr "op_type" "RRE,RXE,RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,RIE,SI,SS") 6778 (set_attr "cpu_facility" "*,*,*,*,*,*,extimm,extimm,*,z196,*,z10,*,*") 6779 (set_attr "z10prop" "*, 6780 *, 6781 z10_super_E1, 6782 z10_super_E1, 6783 z10_super_E1, 6784 z10_super_E1, 6785 z10_super_E1, 6786 z10_super_E1, 6787 z10_super_E1, 6788 *, 6789 z10_super_E1, 6790 z10_super_E1, 6791 *, 6792 *")]) 6793 6794(define_split 6795 [(set (match_operand:DI 0 "s_operand" "") 6796 (and:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) 6797 (clobber (reg:CC CC_REGNUM))] 6798 "reload_completed" 6799 [(parallel 6800 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 6801 (clobber (reg:CC CC_REGNUM))])] 6802 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") 6803 6804;; These two are what combine generates for (ashift (zero_extract)). 6805(define_insn "*extzv_<mode>_srl" 6806 [(set (match_operand:GPR 0 "register_operand" "=d") 6807 (and:GPR (lshiftrt:GPR 6808 (match_operand:GPR 1 "register_operand" "d") 6809 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 6810 (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) 6811 (clobber (reg:CC CC_REGNUM))] 6812 "TARGET_Z10 6813 /* Note that even for the SImode pattern, the rotate is always DImode. */ 6814 && s390_extzv_shift_ok (<bitsize>, -INTVAL (operands[2]), 6815 INTVAL (operands[3]))" 6816 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,64-%2" 6817 [(set_attr "op_type" "RIE") 6818 (set_attr "z10prop" "z10_super_E1")]) 6819 6820(define_insn "*extzv_<mode>_sll" 6821 [(set (match_operand:GPR 0 "register_operand" "=d") 6822 (and:GPR (ashift:GPR 6823 (match_operand:GPR 1 "register_operand" "d") 6824 (match_operand:GPR 2 "nonzero_shift_count_operand" "")) 6825 (match_operand:GPR 3 "contiguous_bitmask_operand" ""))) 6826 (clobber (reg:CC CC_REGNUM))] 6827 "TARGET_Z10 6828 && s390_extzv_shift_ok (<bitsize>, INTVAL (operands[2]), 6829 INTVAL (operands[3]))" 6830 "risbg\t%0,%1,%<bfstart>3,128+%<bfend>3,%2" 6831 [(set_attr "op_type" "RIE") 6832 (set_attr "z10prop" "z10_super_E1")]) 6833 6834 6835; 6836; andsi3 instruction pattern(s). 6837; 6838 6839(define_insn "*andsi3_cc" 6840 [(set (reg CC_REGNUM) 6841 (compare 6842 (and:SI 6843 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") 6844 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) 6845 (const_int 0))) 6846 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d, d") 6847 (and:SI (match_dup 1) (match_dup 2)))] 6848 "s390_match_ccmode(insn, CCTmode)" 6849 "@ 6850 nilf\t%0,%o2 6851 nr\t%0,%2 6852 nrk\t%0,%1,%2 6853 n\t%0,%2 6854 ny\t%0,%2 6855 risbg\t%0,%1,%t2,128+%f2,0" 6856 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") 6857 (set_attr "cpu_facility" "*,*,z196,*,*,z10") 6858 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 6859 z10_super_E1,z10_super_E1,z10_super_E1")]) 6860 6861(define_insn "*andsi3_cconly" 6862 [(set (reg CC_REGNUM) 6863 (compare 6864 (and:SI 6865 (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, d") 6866 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxxSq")) 6867 (const_int 0))) 6868 (clobber (match_scratch:SI 0 "=d,d,d,d,d, d"))] 6869 "s390_match_ccmode(insn, CCTmode) 6870 /* Do not steal TM patterns. */ 6871 && s390_single_part (operands[2], SImode, HImode, 0) < 0" 6872 "@ 6873 nilf\t%0,%o2 6874 nr\t%0,%2 6875 nrk\t%0,%1,%2 6876 n\t%0,%2 6877 ny\t%0,%2 6878 risbg\t%0,%1,%t2,128+%f2,0" 6879 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,RIE") 6880 (set_attr "cpu_facility" "*,*,z196,*,*,z10") 6881 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 6882 z10_super_E1,z10_super_E1,z10_super_E1")]) 6883 6884(define_insn "*andsi3_zarch" 6885 [(set (match_operand:SI 0 "nonimmediate_operand" 6886 "=d,d, d, d, d,d,d,d,d, d, AQ,Q") 6887 (and:SI (match_operand:SI 1 "nonimmediate_operand" 6888 "%d,o, 0, 0, 0,0,d,0,0, d, 0,0") 6889 (match_operand:SI 2 "general_operand" 6890 " M,M,N0HSF,N1HSF,Os,d,d,R,T,NxxSq,NxQSF,Q"))) 6891 (clobber (reg:CC CC_REGNUM))] 6892 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 6893 "@ 6894 # 6895 # 6896 nilh\t%0,%j2 6897 nill\t%0,%j2 6898 nilf\t%0,%o2 6899 nr\t%0,%2 6900 nrk\t%0,%1,%2 6901 n\t%0,%2 6902 ny\t%0,%2 6903 risbg\t%0,%1,%t2,128+%f2,0 6904 # 6905 #" 6906 [(set_attr "op_type" "RRE,RXE,RI,RI,RIL,RR,RRF,RX,RXY,RIE,SI,SS") 6907 (set_attr "cpu_facility" "*,*,*,*,*,*,z196,*,*,z10,*,*") 6908 (set_attr "z10prop" "*, 6909 *, 6910 z10_super_E1, 6911 z10_super_E1, 6912 z10_super_E1, 6913 z10_super_E1, 6914 *, 6915 z10_super_E1, 6916 z10_super_E1, 6917 z10_super_E1, 6918 *, 6919 *")]) 6920 6921(define_insn "*andsi3_esa" 6922 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d, AQ,Q") 6923 (and:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0, 0,0") 6924 (match_operand:SI 2 "general_operand" " d,R,NxQSF,Q"))) 6925 (clobber (reg:CC CC_REGNUM))] 6926 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 6927 "@ 6928 nr\t%0,%2 6929 n\t%0,%2 6930 # 6931 #" 6932 [(set_attr "op_type" "RR,RX,SI,SS") 6933 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) 6934 6935 6936(define_split 6937 [(set (match_operand:SI 0 "s_operand" "") 6938 (and:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) 6939 (clobber (reg:CC CC_REGNUM))] 6940 "reload_completed" 6941 [(parallel 6942 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 6943 (clobber (reg:CC CC_REGNUM))])] 6944 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") 6945 6946; 6947; andhi3 instruction pattern(s). 6948; 6949 6950(define_insn "*andhi3_zarch" 6951 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") 6952 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") 6953 (match_operand:HI 2 "general_operand" " d,d,n,NxQHF,Q"))) 6954 (clobber (reg:CC CC_REGNUM))] 6955 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 6956 "@ 6957 nr\t%0,%2 6958 nrk\t%0,%1,%2 6959 nill\t%0,%x2 6960 # 6961 #" 6962 [(set_attr "op_type" "RR,RRF,RI,SI,SS") 6963 (set_attr "cpu_facility" "*,z196,*,*,*") 6964 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*") 6965]) 6966 6967(define_insn "*andhi3_esa" 6968 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") 6969 (and:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") 6970 (match_operand:HI 2 "general_operand" "d,NxQHF,Q"))) 6971 (clobber (reg:CC CC_REGNUM))] 6972 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 6973 "@ 6974 nr\t%0,%2 6975 # 6976 #" 6977 [(set_attr "op_type" "RR,SI,SS") 6978 (set_attr "z10prop" "z10_super_E1,*,*") 6979]) 6980 6981(define_split 6982 [(set (match_operand:HI 0 "s_operand" "") 6983 (and:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) 6984 (clobber (reg:CC CC_REGNUM))] 6985 "reload_completed" 6986 [(parallel 6987 [(set (match_dup 0) (and:QI (match_dup 0) (match_dup 1))) 6988 (clobber (reg:CC CC_REGNUM))])] 6989 "s390_narrow_logical_operator (AND, &operands[0], &operands[1]);") 6990 6991; 6992; andqi3 instruction pattern(s). 6993; 6994 6995(define_insn "*andqi3_zarch" 6996 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") 6997 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 6998 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) 6999 (clobber (reg:CC CC_REGNUM))] 7000 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7001 "@ 7002 nr\t%0,%2 7003 nrk\t%0,%1,%2 7004 nill\t%0,%b2 7005 ni\t%S0,%b2 7006 niy\t%S0,%b2 7007 #" 7008 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") 7009 (set_attr "cpu_facility" "*,z196,*,*,*,*") 7010 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,z10_super,z10_super,*")]) 7011 7012(define_insn "*andqi3_esa" 7013 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") 7014 (and:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 7015 (match_operand:QI 2 "general_operand" "d,n,Q"))) 7016 (clobber (reg:CC CC_REGNUM))] 7017 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7018 "@ 7019 nr\t%0,%2 7020 ni\t%S0,%b2 7021 #" 7022 [(set_attr "op_type" "RR,SI,SS") 7023 (set_attr "z10prop" "z10_super_E1,z10_super,*")]) 7024 7025; 7026; Block and (NC) patterns. 7027; 7028 7029(define_insn "*nc" 7030 [(set (match_operand:BLK 0 "memory_operand" "=Q") 7031 (and:BLK (match_dup 0) 7032 (match_operand:BLK 1 "memory_operand" "Q"))) 7033 (use (match_operand 2 "const_int_operand" "n")) 7034 (clobber (reg:CC CC_REGNUM))] 7035 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 7036 "nc\t%O0(%2,%R0),%S1" 7037 [(set_attr "op_type" "SS") 7038 (set_attr "z196prop" "z196_cracked")]) 7039 7040(define_split 7041 [(set (match_operand 0 "memory_operand" "") 7042 (and (match_dup 0) 7043 (match_operand 1 "memory_operand" ""))) 7044 (clobber (reg:CC CC_REGNUM))] 7045 "reload_completed 7046 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 7047 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 7048 [(parallel 7049 [(set (match_dup 0) (and:BLK (match_dup 0) (match_dup 1))) 7050 (use (match_dup 2)) 7051 (clobber (reg:CC CC_REGNUM))])] 7052{ 7053 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 7054 operands[0] = adjust_address (operands[0], BLKmode, 0); 7055 operands[1] = adjust_address (operands[1], BLKmode, 0); 7056}) 7057 7058(define_peephole2 7059 [(parallel 7060 [(set (match_operand:BLK 0 "memory_operand" "") 7061 (and:BLK (match_dup 0) 7062 (match_operand:BLK 1 "memory_operand" ""))) 7063 (use (match_operand 2 "const_int_operand" "")) 7064 (clobber (reg:CC CC_REGNUM))]) 7065 (parallel 7066 [(set (match_operand:BLK 3 "memory_operand" "") 7067 (and:BLK (match_dup 3) 7068 (match_operand:BLK 4 "memory_operand" ""))) 7069 (use (match_operand 5 "const_int_operand" "")) 7070 (clobber (reg:CC CC_REGNUM))])] 7071 "s390_offset_p (operands[0], operands[3], operands[2]) 7072 && s390_offset_p (operands[1], operands[4], operands[2]) 7073 && !s390_overlap_p (operands[0], operands[1], 7074 INTVAL (operands[2]) + INTVAL (operands[5])) 7075 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 7076 [(parallel 7077 [(set (match_dup 6) (and:BLK (match_dup 6) (match_dup 7))) 7078 (use (match_dup 8)) 7079 (clobber (reg:CC CC_REGNUM))])] 7080 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 7081 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 7082 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 7083 7084 7085;; 7086;;- Bit set (inclusive or) instructions. 7087;; 7088 7089(define_expand "ior<mode>3" 7090 [(set (match_operand:INT 0 "nonimmediate_operand" "") 7091 (ior:INT (match_operand:INT 1 "nonimmediate_operand" "") 7092 (match_operand:INT 2 "general_operand" ""))) 7093 (clobber (reg:CC CC_REGNUM))] 7094 "" 7095 "s390_expand_logical_operator (IOR, <MODE>mode, operands); DONE;") 7096 7097; 7098; iordi3 instruction pattern(s). 7099; 7100 7101(define_insn "*iordi3_cc" 7102 [(set (reg CC_REGNUM) 7103 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") 7104 (match_operand:DI 2 "general_operand" " d,d,RT")) 7105 (const_int 0))) 7106 (set (match_operand:DI 0 "register_operand" "=d,d, d") 7107 (ior:DI (match_dup 1) (match_dup 2)))] 7108 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 7109 "@ 7110 ogr\t%0,%2 7111 ogrk\t%0,%1,%2 7112 og\t%0,%2" 7113 [(set_attr "op_type" "RRE,RRF,RXY") 7114 (set_attr "cpu_facility" "*,z196,*") 7115 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 7116 7117(define_insn "*iordi3_cconly" 7118 [(set (reg CC_REGNUM) 7119 (compare (ior:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d,0") 7120 (match_operand:DI 2 "general_operand" " d,d,RT")) 7121 (const_int 0))) 7122 (clobber (match_scratch:DI 0 "=d,d,d"))] 7123 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 7124 "@ 7125 ogr\t%0,%2 7126 ogrk\t%0,%1,%2 7127 og\t%0,%2" 7128 [(set_attr "op_type" "RRE,RRF,RXY") 7129 (set_attr "cpu_facility" "*,z196,*") 7130 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 7131 7132(define_insn "*iordi3" 7133 [(set (match_operand:DI 0 "nonimmediate_operand" 7134 "=d, d, d, d, d, d,d,d, d, AQ,Q") 7135 (ior:DI (match_operand:DI 1 "nonimmediate_operand" 7136 " %0, 0, 0, 0, 0, 0,0,d, 0, 0,0") 7137 (match_operand:DI 2 "general_operand" 7138 "N0HD0,N1HD0,N2HD0,N3HD0,N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) 7139 (clobber (reg:CC CC_REGNUM))] 7140 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7141 "@ 7142 oihh\t%0,%i2 7143 oihl\t%0,%i2 7144 oilh\t%0,%i2 7145 oill\t%0,%i2 7146 oihf\t%0,%k2 7147 oilf\t%0,%k2 7148 ogr\t%0,%2 7149 ogrk\t%0,%1,%2 7150 og\t%0,%2 7151 # 7152 #" 7153 [(set_attr "op_type" "RI,RI,RI,RI,RIL,RIL,RRE,RRF,RXY,SI,SS") 7154 (set_attr "cpu_facility" "*,*,*,*,extimm,extimm,*,z196,*,*,*") 7155 (set_attr "z10prop" "z10_super_E1, 7156 z10_super_E1, 7157 z10_super_E1, 7158 z10_super_E1, 7159 z10_super_E1, 7160 z10_super_E1, 7161 z10_super_E1, 7162 *, 7163 z10_super_E1, 7164 *, 7165 *")]) 7166 7167(define_split 7168 [(set (match_operand:DI 0 "s_operand" "") 7169 (ior:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) 7170 (clobber (reg:CC CC_REGNUM))] 7171 "reload_completed" 7172 [(parallel 7173 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) 7174 (clobber (reg:CC CC_REGNUM))])] 7175 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") 7176 7177; 7178; iorsi3 instruction pattern(s). 7179; 7180 7181(define_insn "*iorsi3_cc" 7182 [(set (reg CC_REGNUM) 7183 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 7184 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 7185 (const_int 0))) 7186 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") 7187 (ior:SI (match_dup 1) (match_dup 2)))] 7188 "s390_match_ccmode(insn, CCTmode)" 7189 "@ 7190 oilf\t%0,%o2 7191 or\t%0,%2 7192 ork\t%0,%1,%2 7193 o\t%0,%2 7194 oy\t%0,%2" 7195 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 7196 (set_attr "cpu_facility" "*,*,z196,*,*") 7197 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) 7198 7199(define_insn "*iorsi3_cconly" 7200 [(set (reg CC_REGNUM) 7201 (compare (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 7202 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 7203 (const_int 0))) 7204 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] 7205 "s390_match_ccmode(insn, CCTmode)" 7206 "@ 7207 oilf\t%0,%o2 7208 or\t%0,%2 7209 ork\t%0,%1,%2 7210 o\t%0,%2 7211 oy\t%0,%2" 7212 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 7213 (set_attr "cpu_facility" "*,*,z196,*,*") 7214 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super_E1,z10_super_E1")]) 7215 7216(define_insn "*iorsi3_zarch" 7217 [(set (match_operand:SI 0 "nonimmediate_operand" "=d, d, d,d,d,d,d, AQ,Q") 7218 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0, 0, 0,0,d,0,0, 0,0") 7219 (match_operand:SI 2 "general_operand" "N0HS0,N1HS0,Os,d,d,R,T,NxQS0,Q"))) 7220 (clobber (reg:CC CC_REGNUM))] 7221 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7222 "@ 7223 oilh\t%0,%i2 7224 oill\t%0,%i2 7225 oilf\t%0,%o2 7226 or\t%0,%2 7227 ork\t%0,%1,%2 7228 o\t%0,%2 7229 oy\t%0,%2 7230 # 7231 #" 7232 [(set_attr "op_type" "RI,RI,RIL,RR,RRF,RX,RXY,SI,SS") 7233 (set_attr "cpu_facility" "*,*,*,*,z196,*,*,*,*") 7234 (set_attr "z10prop" "z10_super_E1, 7235 z10_super_E1, 7236 z10_super_E1, 7237 z10_super_E1, 7238 *, 7239 z10_super_E1, 7240 z10_super_E1, 7241 *, 7242 *")]) 7243 7244(define_insn "*iorsi3_esa" 7245 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,AQ,Q") 7246 (ior:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,0,0") 7247 (match_operand:SI 2 "general_operand" "d,R,NxQS0,Q"))) 7248 (clobber (reg:CC CC_REGNUM))] 7249 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7250 "@ 7251 or\t%0,%2 7252 o\t%0,%2 7253 # 7254 #" 7255 [(set_attr "op_type" "RR,RX,SI,SS") 7256 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*")]) 7257 7258(define_split 7259 [(set (match_operand:SI 0 "s_operand" "") 7260 (ior:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) 7261 (clobber (reg:CC CC_REGNUM))] 7262 "reload_completed" 7263 [(parallel 7264 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) 7265 (clobber (reg:CC CC_REGNUM))])] 7266 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") 7267 7268; 7269; iorhi3 instruction pattern(s). 7270; 7271 7272(define_insn "*iorhi3_zarch" 7273 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") 7274 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,d,0, 0,0") 7275 (match_operand:HI 2 "general_operand" " d,d,n,NxQH0,Q"))) 7276 (clobber (reg:CC CC_REGNUM))] 7277 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7278 "@ 7279 or\t%0,%2 7280 ork\t%0,%1,%2 7281 oill\t%0,%x2 7282 # 7283 #" 7284 [(set_attr "op_type" "RR,RRF,RI,SI,SS") 7285 (set_attr "cpu_facility" "*,z196,*,*,*") 7286 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1,*,*")]) 7287 7288(define_insn "*iorhi3_esa" 7289 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,AQ,Q") 7290 (ior:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,0") 7291 (match_operand:HI 2 "general_operand" "d,NxQH0,Q"))) 7292 (clobber (reg:CC CC_REGNUM))] 7293 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7294 "@ 7295 or\t%0,%2 7296 # 7297 #" 7298 [(set_attr "op_type" "RR,SI,SS") 7299 (set_attr "z10prop" "z10_super_E1,*,*")]) 7300 7301(define_split 7302 [(set (match_operand:HI 0 "s_operand" "") 7303 (ior:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) 7304 (clobber (reg:CC CC_REGNUM))] 7305 "reload_completed" 7306 [(parallel 7307 [(set (match_dup 0) (ior:QI (match_dup 0) (match_dup 1))) 7308 (clobber (reg:CC CC_REGNUM))])] 7309 "s390_narrow_logical_operator (IOR, &operands[0], &operands[1]);") 7310 7311; 7312; iorqi3 instruction pattern(s). 7313; 7314 7315(define_insn "*iorqi3_zarch" 7316 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") 7317 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,d,0,0,0,0") 7318 (match_operand:QI 2 "general_operand" " d,d,n,n,n,Q"))) 7319 (clobber (reg:CC CC_REGNUM))] 7320 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7321 "@ 7322 or\t%0,%2 7323 ork\t%0,%1,%2 7324 oill\t%0,%b2 7325 oi\t%S0,%b2 7326 oiy\t%S0,%b2 7327 #" 7328 [(set_attr "op_type" "RR,RRF,RI,SI,SIY,SS") 7329 (set_attr "cpu_facility" "*,z196,*,*,*,*") 7330 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1, 7331 z10_super,z10_super,*")]) 7332 7333(define_insn "*iorqi3_esa" 7334 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,Q,Q") 7335 (ior:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,0") 7336 (match_operand:QI 2 "general_operand" "d,n,Q"))) 7337 (clobber (reg:CC CC_REGNUM))] 7338 "!TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7339 "@ 7340 or\t%0,%2 7341 oi\t%S0,%b2 7342 #" 7343 [(set_attr "op_type" "RR,SI,SS") 7344 (set_attr "z10prop" "z10_super_E1,z10_super,*")]) 7345 7346; 7347; Block inclusive or (OC) patterns. 7348; 7349 7350(define_insn "*oc" 7351 [(set (match_operand:BLK 0 "memory_operand" "=Q") 7352 (ior:BLK (match_dup 0) 7353 (match_operand:BLK 1 "memory_operand" "Q"))) 7354 (use (match_operand 2 "const_int_operand" "n")) 7355 (clobber (reg:CC CC_REGNUM))] 7356 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 7357 "oc\t%O0(%2,%R0),%S1" 7358 [(set_attr "op_type" "SS") 7359 (set_attr "z196prop" "z196_cracked")]) 7360 7361(define_split 7362 [(set (match_operand 0 "memory_operand" "") 7363 (ior (match_dup 0) 7364 (match_operand 1 "memory_operand" ""))) 7365 (clobber (reg:CC CC_REGNUM))] 7366 "reload_completed 7367 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 7368 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 7369 [(parallel 7370 [(set (match_dup 0) (ior:BLK (match_dup 0) (match_dup 1))) 7371 (use (match_dup 2)) 7372 (clobber (reg:CC CC_REGNUM))])] 7373{ 7374 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 7375 operands[0] = adjust_address (operands[0], BLKmode, 0); 7376 operands[1] = adjust_address (operands[1], BLKmode, 0); 7377}) 7378 7379(define_peephole2 7380 [(parallel 7381 [(set (match_operand:BLK 0 "memory_operand" "") 7382 (ior:BLK (match_dup 0) 7383 (match_operand:BLK 1 "memory_operand" ""))) 7384 (use (match_operand 2 "const_int_operand" "")) 7385 (clobber (reg:CC CC_REGNUM))]) 7386 (parallel 7387 [(set (match_operand:BLK 3 "memory_operand" "") 7388 (ior:BLK (match_dup 3) 7389 (match_operand:BLK 4 "memory_operand" ""))) 7390 (use (match_operand 5 "const_int_operand" "")) 7391 (clobber (reg:CC CC_REGNUM))])] 7392 "s390_offset_p (operands[0], operands[3], operands[2]) 7393 && s390_offset_p (operands[1], operands[4], operands[2]) 7394 && !s390_overlap_p (operands[0], operands[1], 7395 INTVAL (operands[2]) + INTVAL (operands[5])) 7396 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 7397 [(parallel 7398 [(set (match_dup 6) (ior:BLK (match_dup 6) (match_dup 7))) 7399 (use (match_dup 8)) 7400 (clobber (reg:CC CC_REGNUM))])] 7401 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 7402 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 7403 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 7404 7405 7406;; 7407;;- Xor instructions. 7408;; 7409 7410(define_expand "xor<mode>3" 7411 [(set (match_operand:INT 0 "nonimmediate_operand" "") 7412 (xor:INT (match_operand:INT 1 "nonimmediate_operand" "") 7413 (match_operand:INT 2 "general_operand" ""))) 7414 (clobber (reg:CC CC_REGNUM))] 7415 "" 7416 "s390_expand_logical_operator (XOR, <MODE>mode, operands); DONE;") 7417 7418; Combine replaces (xor (x) (const_int -1)) with (not (x)) when doing 7419; simplifications. So its better to have something matching. 7420(define_split 7421 [(set (match_operand:INT 0 "nonimmediate_operand" "") 7422 (not:INT (match_operand:INT 1 "nonimmediate_operand" "")))] 7423 "" 7424 [(parallel 7425 [(set (match_dup 0) (xor:INT (match_dup 1) (match_dup 2))) 7426 (clobber (reg:CC CC_REGNUM))])] 7427{ 7428 operands[2] = constm1_rtx; 7429 if (!s390_logical_operator_ok_p (operands)) 7430 FAIL; 7431}) 7432 7433; 7434; xordi3 instruction pattern(s). 7435; 7436 7437(define_insn "*xordi3_cc" 7438 [(set (reg CC_REGNUM) 7439 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") 7440 (match_operand:DI 2 "general_operand" " d,d,RT")) 7441 (const_int 0))) 7442 (set (match_operand:DI 0 "register_operand" "=d,d, d") 7443 (xor:DI (match_dup 1) (match_dup 2)))] 7444 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 7445 "@ 7446 xgr\t%0,%2 7447 xgrk\t%0,%1,%2 7448 xg\t%0,%2" 7449 [(set_attr "op_type" "RRE,RRF,RXY") 7450 (set_attr "cpu_facility" "*,z196,*") 7451 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 7452 7453(define_insn "*xordi3_cconly" 7454 [(set (reg CC_REGNUM) 7455 (compare (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0,d, 0") 7456 (match_operand:DI 2 "general_operand" " d,d,RT")) 7457 (const_int 0))) 7458 (clobber (match_scratch:DI 0 "=d,d, d"))] 7459 "s390_match_ccmode(insn, CCTmode) && TARGET_ZARCH" 7460 "@ 7461 xgr\t%0,%2 7462 xgrk\t%0,%1,%2 7463 xg\t%0,%2" 7464 [(set_attr "op_type" "RRE,RRF,RXY") 7465 (set_attr "cpu_facility" "*,z196,*") 7466 (set_attr "z10prop" "z10_super_E1,*,z10_super_E1")]) 7467 7468(define_insn "*xordi3" 7469 [(set (match_operand:DI 0 "nonimmediate_operand" "=d, d,d,d, d, AQ,Q") 7470 (xor:DI (match_operand:DI 1 "nonimmediate_operand" "%0, 0,0,d, 0, 0,0") 7471 (match_operand:DI 2 "general_operand" "N0SD0,N1SD0,d,d,RT,NxQD0,Q"))) 7472 (clobber (reg:CC CC_REGNUM))] 7473 "TARGET_ZARCH && s390_logical_operator_ok_p (operands)" 7474 "@ 7475 xihf\t%0,%k2 7476 xilf\t%0,%k2 7477 xgr\t%0,%2 7478 xgrk\t%0,%1,%2 7479 xg\t%0,%2 7480 # 7481 #" 7482 [(set_attr "op_type" "RIL,RIL,RRE,RRF,RXY,SI,SS") 7483 (set_attr "cpu_facility" "extimm,extimm,*,z196,*,*,*") 7484 (set_attr "z10prop" "z10_super_E1,z10_super_E1,z10_super_E1, 7485 *,z10_super_E1,*,*")]) 7486 7487(define_split 7488 [(set (match_operand:DI 0 "s_operand" "") 7489 (xor:DI (match_dup 0) (match_operand:DI 1 "immediate_operand" ""))) 7490 (clobber (reg:CC CC_REGNUM))] 7491 "reload_completed" 7492 [(parallel 7493 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 7494 (clobber (reg:CC CC_REGNUM))])] 7495 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") 7496 7497; 7498; xorsi3 instruction pattern(s). 7499; 7500 7501(define_insn "*xorsi3_cc" 7502 [(set (reg CC_REGNUM) 7503 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 7504 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 7505 (const_int 0))) 7506 (set (match_operand:SI 0 "register_operand" "=d,d,d,d,d") 7507 (xor:SI (match_dup 1) (match_dup 2)))] 7508 "s390_match_ccmode(insn, CCTmode)" 7509 "@ 7510 xilf\t%0,%o2 7511 xr\t%0,%2 7512 xrk\t%0,%1,%2 7513 x\t%0,%2 7514 xy\t%0,%2" 7515 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 7516 (set_attr "cpu_facility" "*,*,z196,*,*") 7517 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 7518 z10_super_E1,z10_super_E1")]) 7519 7520(define_insn "*xorsi3_cconly" 7521 [(set (reg CC_REGNUM) 7522 (compare (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0") 7523 (match_operand:SI 2 "general_operand" "Os,d,d,R,T")) 7524 (const_int 0))) 7525 (clobber (match_scratch:SI 0 "=d,d,d,d,d"))] 7526 "s390_match_ccmode(insn, CCTmode)" 7527 "@ 7528 xilf\t%0,%o2 7529 xr\t%0,%2 7530 xrk\t%0,%1,%2 7531 x\t%0,%2 7532 xy\t%0,%2" 7533 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY") 7534 (set_attr "cpu_facility" "*,*,z196,*,*") 7535 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 7536 z10_super_E1,z10_super_E1")]) 7537 7538(define_insn "*xorsi3" 7539 [(set (match_operand:SI 0 "nonimmediate_operand" "=d,d,d,d,d, AQ,Q") 7540 (xor:SI (match_operand:SI 1 "nonimmediate_operand" "%0,0,d,0,0, 0,0") 7541 (match_operand:SI 2 "general_operand" "Os,d,d,R,T,NxQS0,Q"))) 7542 (clobber (reg:CC CC_REGNUM))] 7543 "s390_logical_operator_ok_p (operands)" 7544 "@ 7545 xilf\t%0,%o2 7546 xr\t%0,%2 7547 xrk\t%0,%1,%2 7548 x\t%0,%2 7549 xy\t%0,%2 7550 # 7551 #" 7552 [(set_attr "op_type" "RIL,RR,RRF,RX,RXY,SI,SS") 7553 (set_attr "cpu_facility" "*,*,z196,*,*,*,*") 7554 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*, 7555 z10_super_E1,z10_super_E1,*,*")]) 7556 7557(define_split 7558 [(set (match_operand:SI 0 "s_operand" "") 7559 (xor:SI (match_dup 0) (match_operand:SI 1 "immediate_operand" ""))) 7560 (clobber (reg:CC CC_REGNUM))] 7561 "reload_completed" 7562 [(parallel 7563 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 7564 (clobber (reg:CC CC_REGNUM))])] 7565 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") 7566 7567; 7568; xorhi3 instruction pattern(s). 7569; 7570 7571(define_insn "*xorhi3" 7572 [(set (match_operand:HI 0 "nonimmediate_operand" "=d,d,d, AQ,Q") 7573 (xor:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,d, 0,0") 7574 (match_operand:HI 2 "general_operand" "Os,d,d,NxQH0,Q"))) 7575 (clobber (reg:CC CC_REGNUM))] 7576 "s390_logical_operator_ok_p (operands)" 7577 "@ 7578 xilf\t%0,%x2 7579 xr\t%0,%2 7580 xrk\t%0,%1,%2 7581 # 7582 #" 7583 [(set_attr "op_type" "RIL,RR,RRF,SI,SS") 7584 (set_attr "cpu_facility" "*,*,z196,*,*") 7585 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,*,*")]) 7586 7587(define_split 7588 [(set (match_operand:HI 0 "s_operand" "") 7589 (xor:HI (match_dup 0) (match_operand:HI 1 "immediate_operand" ""))) 7590 (clobber (reg:CC CC_REGNUM))] 7591 "reload_completed" 7592 [(parallel 7593 [(set (match_dup 0) (xor:QI (match_dup 0) (match_dup 1))) 7594 (clobber (reg:CC CC_REGNUM))])] 7595 "s390_narrow_logical_operator (XOR, &operands[0], &operands[1]);") 7596 7597; 7598; xorqi3 instruction pattern(s). 7599; 7600 7601(define_insn "*xorqi3" 7602 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d,d,Q,S,Q") 7603 (xor:QI (match_operand:QI 1 "nonimmediate_operand" "%0,0,d,0,0,0") 7604 (match_operand:QI 2 "general_operand" "Os,d,d,n,n,Q"))) 7605 (clobber (reg:CC CC_REGNUM))] 7606 "s390_logical_operator_ok_p (operands)" 7607 "@ 7608 xilf\t%0,%b2 7609 xr\t%0,%2 7610 xrk\t%0,%1,%2 7611 xi\t%S0,%b2 7612 xiy\t%S0,%b2 7613 #" 7614 [(set_attr "op_type" "RIL,RR,RRF,SI,SIY,SS") 7615 (set_attr "cpu_facility" "*,*,z196,*,*,*") 7616 (set_attr "z10prop" "z10_super_E1,z10_super_E1,*,z10_super,z10_super,*")]) 7617 7618 7619; 7620; Block exclusive or (XC) patterns. 7621; 7622 7623(define_insn "*xc" 7624 [(set (match_operand:BLK 0 "memory_operand" "=Q") 7625 (xor:BLK (match_dup 0) 7626 (match_operand:BLK 1 "memory_operand" "Q"))) 7627 (use (match_operand 2 "const_int_operand" "n")) 7628 (clobber (reg:CC CC_REGNUM))] 7629 "INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 256" 7630 "xc\t%O0(%2,%R0),%S1" 7631 [(set_attr "op_type" "SS")]) 7632 7633(define_split 7634 [(set (match_operand 0 "memory_operand" "") 7635 (xor (match_dup 0) 7636 (match_operand 1 "memory_operand" ""))) 7637 (clobber (reg:CC CC_REGNUM))] 7638 "reload_completed 7639 && GET_MODE (operands[0]) == GET_MODE (operands[1]) 7640 && GET_MODE_SIZE (GET_MODE (operands[0])) > 0" 7641 [(parallel 7642 [(set (match_dup 0) (xor:BLK (match_dup 0) (match_dup 1))) 7643 (use (match_dup 2)) 7644 (clobber (reg:CC CC_REGNUM))])] 7645{ 7646 operands[2] = GEN_INT (GET_MODE_SIZE (GET_MODE (operands[0]))); 7647 operands[0] = adjust_address (operands[0], BLKmode, 0); 7648 operands[1] = adjust_address (operands[1], BLKmode, 0); 7649}) 7650 7651(define_peephole2 7652 [(parallel 7653 [(set (match_operand:BLK 0 "memory_operand" "") 7654 (xor:BLK (match_dup 0) 7655 (match_operand:BLK 1 "memory_operand" ""))) 7656 (use (match_operand 2 "const_int_operand" "")) 7657 (clobber (reg:CC CC_REGNUM))]) 7658 (parallel 7659 [(set (match_operand:BLK 3 "memory_operand" "") 7660 (xor:BLK (match_dup 3) 7661 (match_operand:BLK 4 "memory_operand" ""))) 7662 (use (match_operand 5 "const_int_operand" "")) 7663 (clobber (reg:CC CC_REGNUM))])] 7664 "s390_offset_p (operands[0], operands[3], operands[2]) 7665 && s390_offset_p (operands[1], operands[4], operands[2]) 7666 && !s390_overlap_p (operands[0], operands[1], 7667 INTVAL (operands[2]) + INTVAL (operands[5])) 7668 && INTVAL (operands[2]) + INTVAL (operands[5]) <= 256" 7669 [(parallel 7670 [(set (match_dup 6) (xor:BLK (match_dup 6) (match_dup 7))) 7671 (use (match_dup 8)) 7672 (clobber (reg:CC CC_REGNUM))])] 7673 "operands[6] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 7674 operands[7] = gen_rtx_MEM (BLKmode, XEXP (operands[1], 0)); 7675 operands[8] = GEN_INT (INTVAL (operands[2]) + INTVAL (operands[5]));") 7676 7677; 7678; Block xor (XC) patterns with src == dest. 7679; 7680 7681(define_insn "*xc_zero" 7682 [(set (match_operand:BLK 0 "memory_operand" "=Q") 7683 (const_int 0)) 7684 (use (match_operand 1 "const_int_operand" "n")) 7685 (clobber (reg:CC CC_REGNUM))] 7686 "INTVAL (operands[1]) >= 1 && INTVAL (operands[1]) <= 256" 7687 "xc\t%O0(%1,%R0),%S0" 7688 [(set_attr "op_type" "SS") 7689 (set_attr "z196prop" "z196_cracked")]) 7690 7691(define_peephole2 7692 [(parallel 7693 [(set (match_operand:BLK 0 "memory_operand" "") 7694 (const_int 0)) 7695 (use (match_operand 1 "const_int_operand" "")) 7696 (clobber (reg:CC CC_REGNUM))]) 7697 (parallel 7698 [(set (match_operand:BLK 2 "memory_operand" "") 7699 (const_int 0)) 7700 (use (match_operand 3 "const_int_operand" "")) 7701 (clobber (reg:CC CC_REGNUM))])] 7702 "s390_offset_p (operands[0], operands[2], operands[1]) 7703 && INTVAL (operands[1]) + INTVAL (operands[3]) <= 256" 7704 [(parallel 7705 [(set (match_dup 4) (const_int 0)) 7706 (use (match_dup 5)) 7707 (clobber (reg:CC CC_REGNUM))])] 7708 "operands[4] = gen_rtx_MEM (BLKmode, XEXP (operands[0], 0)); 7709 operands[5] = GEN_INT (INTVAL (operands[1]) + INTVAL (operands[3]));") 7710 7711 7712;; 7713;;- Negate instructions. 7714;; 7715 7716; 7717; neg(di|si)2 instruction pattern(s). 7718; 7719 7720(define_expand "neg<mode>2" 7721 [(parallel 7722 [(set (match_operand:DSI 0 "register_operand" "=d") 7723 (neg:DSI (match_operand:DSI 1 "register_operand" "d"))) 7724 (clobber (reg:CC CC_REGNUM))])] 7725 "" 7726 "") 7727 7728(define_insn "*negdi2_sign_cc" 7729 [(set (reg CC_REGNUM) 7730 (compare (neg:DI (ashiftrt:DI (ashift:DI (subreg:DI 7731 (match_operand:SI 1 "register_operand" "d") 0) 7732 (const_int 32)) (const_int 32))) 7733 (const_int 0))) 7734 (set (match_operand:DI 0 "register_operand" "=d") 7735 (neg:DI (sign_extend:DI (match_dup 1))))] 7736 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" 7737 "lcgfr\t%0,%1" 7738 [(set_attr "op_type" "RRE") 7739 (set_attr "z10prop" "z10_c")]) 7740 7741(define_insn "*negdi2_sign" 7742 [(set (match_operand:DI 0 "register_operand" "=d") 7743 (neg:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) 7744 (clobber (reg:CC CC_REGNUM))] 7745 "TARGET_ZARCH" 7746 "lcgfr\t%0,%1" 7747 [(set_attr "op_type" "RRE") 7748 (set_attr "z10prop" "z10_c")]) 7749 7750; lcr, lcgr 7751(define_insn "*neg<mode>2_cc" 7752 [(set (reg CC_REGNUM) 7753 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) 7754 (const_int 0))) 7755 (set (match_operand:GPR 0 "register_operand" "=d") 7756 (neg:GPR (match_dup 1)))] 7757 "s390_match_ccmode (insn, CCAmode)" 7758 "lc<g>r\t%0,%1" 7759 [(set_attr "op_type" "RR<E>") 7760 (set_attr "z10prop" "z10_super_c_E1")]) 7761 7762; lcr, lcgr 7763(define_insn "*neg<mode>2_cconly" 7764 [(set (reg CC_REGNUM) 7765 (compare (neg:GPR (match_operand:GPR 1 "register_operand" "d")) 7766 (const_int 0))) 7767 (clobber (match_scratch:GPR 0 "=d"))] 7768 "s390_match_ccmode (insn, CCAmode)" 7769 "lc<g>r\t%0,%1" 7770 [(set_attr "op_type" "RR<E>") 7771 (set_attr "z10prop" "z10_super_c_E1")]) 7772 7773; lcr, lcgr 7774(define_insn "*neg<mode>2" 7775 [(set (match_operand:GPR 0 "register_operand" "=d") 7776 (neg:GPR (match_operand:GPR 1 "register_operand" "d"))) 7777 (clobber (reg:CC CC_REGNUM))] 7778 "" 7779 "lc<g>r\t%0,%1" 7780 [(set_attr "op_type" "RR<E>") 7781 (set_attr "z10prop" "z10_super_c_E1")]) 7782 7783(define_insn "*negdi2_31" 7784 [(set (match_operand:DI 0 "register_operand" "=d") 7785 (neg:DI (match_operand:DI 1 "register_operand" "d"))) 7786 (clobber (reg:CC CC_REGNUM))] 7787 "!TARGET_ZARCH" 7788 "#") 7789 7790; Split a DImode NEG on 31bit into 2 SImode NEGs 7791 7792; Doing the twos complement separately on the SImode parts does an 7793; unwanted +1 on the high part which needs to be subtracted afterwards 7794; ... unless the +1 on the low part created an overflow. 7795 7796(define_split 7797 [(set (match_operand:DI 0 "register_operand" "") 7798 (neg:DI (match_operand:DI 1 "register_operand" ""))) 7799 (clobber (reg:CC CC_REGNUM))] 7800 "!TARGET_ZARCH 7801 && (REGNO (operands[0]) == REGNO (operands[1]) 7802 || s390_split_ok_p (operands[0], operands[1], DImode, 0)) 7803 && reload_completed" 7804 [(parallel 7805 [(set (match_dup 2) (neg:SI (match_dup 3))) 7806 (clobber (reg:CC CC_REGNUM))]) 7807 (parallel 7808 [(set (reg:CCAP CC_REGNUM) 7809 (compare:CCAP (neg:SI (match_dup 5)) (const_int 0))) 7810 (set (match_dup 4) (neg:SI (match_dup 5)))]) 7811 (set (pc) 7812 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) 7813 (pc) 7814 (label_ref (match_dup 6)))) 7815 (parallel 7816 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) 7817 (clobber (reg:CC CC_REGNUM))]) 7818 (match_dup 6)] 7819 "operands[2] = operand_subword (operands[0], 0, 0, DImode); 7820 operands[3] = operand_subword (operands[1], 0, 0, DImode); 7821 operands[4] = operand_subword (operands[0], 1, 0, DImode); 7822 operands[5] = operand_subword (operands[1], 1, 0, DImode); 7823 operands[6] = gen_label_rtx ();") 7824 7825; Like above but first make a copy of the low part of the src operand 7826; since it might overlap with the high part of the destination. 7827 7828(define_split 7829 [(set (match_operand:DI 0 "register_operand" "") 7830 (neg:DI (match_operand:DI 1 "register_operand" ""))) 7831 (clobber (reg:CC CC_REGNUM))] 7832 "!TARGET_ZARCH 7833 && s390_split_ok_p (operands[0], operands[1], DImode, 1) 7834 && reload_completed" 7835 [; Make a backup of op5 first 7836 (set (match_dup 4) (match_dup 5)) 7837 ; Setting op2 here might clobber op5 7838 (parallel 7839 [(set (match_dup 2) (neg:SI (match_dup 3))) 7840 (clobber (reg:CC CC_REGNUM))]) 7841 (parallel 7842 [(set (reg:CCAP CC_REGNUM) 7843 (compare:CCAP (neg:SI (match_dup 4)) (const_int 0))) 7844 (set (match_dup 4) (neg:SI (match_dup 4)))]) 7845 (set (pc) 7846 (if_then_else (ne (reg:CCAP CC_REGNUM) (const_int 0)) 7847 (pc) 7848 (label_ref (match_dup 6)))) 7849 (parallel 7850 [(set (match_dup 2) (plus:SI (match_dup 2) (const_int -1))) 7851 (clobber (reg:CC CC_REGNUM))]) 7852 (match_dup 6)] 7853 "operands[2] = operand_subword (operands[0], 0, 0, DImode); 7854 operands[3] = operand_subword (operands[1], 0, 0, DImode); 7855 operands[4] = operand_subword (operands[0], 1, 0, DImode); 7856 operands[5] = operand_subword (operands[1], 1, 0, DImode); 7857 operands[6] = gen_label_rtx ();") 7858 7859; 7860; neg(df|sf)2 instruction pattern(s). 7861; 7862 7863(define_expand "neg<mode>2" 7864 [(parallel 7865 [(set (match_operand:BFP 0 "register_operand" "=f") 7866 (neg:BFP (match_operand:BFP 1 "register_operand" "f"))) 7867 (clobber (reg:CC CC_REGNUM))])] 7868 "TARGET_HARD_FLOAT" 7869 "") 7870 7871; lcxbr, lcdbr, lcebr 7872(define_insn "*neg<mode>2_cc" 7873 [(set (reg CC_REGNUM) 7874 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) 7875 (match_operand:BFP 2 "const0_operand" ""))) 7876 (set (match_operand:BFP 0 "register_operand" "=f") 7877 (neg:BFP (match_dup 1)))] 7878 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 7879 "lc<xde>br\t%0,%1" 7880 [(set_attr "op_type" "RRE") 7881 (set_attr "type" "fsimp<mode>")]) 7882 7883; lcxbr, lcdbr, lcebr 7884(define_insn "*neg<mode>2_cconly" 7885 [(set (reg CC_REGNUM) 7886 (compare (neg:BFP (match_operand:BFP 1 "register_operand" "f")) 7887 (match_operand:BFP 2 "const0_operand" ""))) 7888 (clobber (match_scratch:BFP 0 "=f"))] 7889 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 7890 "lc<xde>br\t%0,%1" 7891 [(set_attr "op_type" "RRE") 7892 (set_attr "type" "fsimp<mode>")]) 7893 7894; lcdfr 7895(define_insn "*neg<mode>2_nocc" 7896 [(set (match_operand:FP 0 "register_operand" "=f") 7897 (neg:FP (match_operand:FP 1 "register_operand" "<fT0>")))] 7898 "TARGET_DFP" 7899 "lcdfr\t%0,%1" 7900 [(set_attr "op_type" "RRE") 7901 (set_attr "type" "fsimp<mode>")]) 7902 7903; lcxbr, lcdbr, lcebr 7904; FIXME: wflcdb does not clobber cc 7905(define_insn "*neg<mode>2" 7906 [(set (match_operand:BFP 0 "register_operand" "=f,<vf>") 7907 (neg:BFP (match_operand:BFP 1 "register_operand" "f,<vf>"))) 7908 (clobber (reg:CC CC_REGNUM))] 7909 "TARGET_HARD_FLOAT" 7910 "@ 7911 lc<xde>br\t%0,%1 7912 wflcdb\t%0,%1" 7913 [(set_attr "op_type" "RRE,VRR") 7914 (set_attr "cpu_facility" "*,vec") 7915 (set_attr "type" "fsimp<mode>,*")]) 7916 7917 7918;; 7919;;- Absolute value instructions. 7920;; 7921 7922; 7923; abs(di|si)2 instruction pattern(s). 7924; 7925 7926(define_insn "*absdi2_sign_cc" 7927 [(set (reg CC_REGNUM) 7928 (compare (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI 7929 (match_operand:SI 1 "register_operand" "d") 0) 7930 (const_int 32)) (const_int 32))) 7931 (const_int 0))) 7932 (set (match_operand:DI 0 "register_operand" "=d") 7933 (abs:DI (sign_extend:DI (match_dup 1))))] 7934 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" 7935 "lpgfr\t%0,%1" 7936 [(set_attr "op_type" "RRE") 7937 (set_attr "z10prop" "z10_c")]) 7938 7939(define_insn "*absdi2_sign" 7940 [(set (match_operand:DI 0 "register_operand" "=d") 7941 (abs:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "d")))) 7942 (clobber (reg:CC CC_REGNUM))] 7943 "TARGET_ZARCH" 7944 "lpgfr\t%0,%1" 7945 [(set_attr "op_type" "RRE") 7946 (set_attr "z10prop" "z10_c")]) 7947 7948; lpr, lpgr 7949(define_insn "*abs<mode>2_cc" 7950 [(set (reg CC_REGNUM) 7951 (compare (abs:GPR (match_operand:DI 1 "register_operand" "d")) 7952 (const_int 0))) 7953 (set (match_operand:GPR 0 "register_operand" "=d") 7954 (abs:GPR (match_dup 1)))] 7955 "s390_match_ccmode (insn, CCAmode)" 7956 "lp<g>r\t%0,%1" 7957 [(set_attr "op_type" "RR<E>") 7958 (set_attr "z10prop" "z10_c")]) 7959 7960; lpr, lpgr 7961(define_insn "*abs<mode>2_cconly" 7962 [(set (reg CC_REGNUM) 7963 (compare (abs:GPR (match_operand:GPR 1 "register_operand" "d")) 7964 (const_int 0))) 7965 (clobber (match_scratch:GPR 0 "=d"))] 7966 "s390_match_ccmode (insn, CCAmode)" 7967 "lp<g>r\t%0,%1" 7968 [(set_attr "op_type" "RR<E>") 7969 (set_attr "z10prop" "z10_c")]) 7970 7971; lpr, lpgr 7972(define_insn "abs<mode>2" 7973 [(set (match_operand:GPR 0 "register_operand" "=d") 7974 (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) 7975 (clobber (reg:CC CC_REGNUM))] 7976 "" 7977 "lp<g>r\t%0,%1" 7978 [(set_attr "op_type" "RR<E>") 7979 (set_attr "z10prop" "z10_c")]) 7980 7981; 7982; abs(df|sf)2 instruction pattern(s). 7983; 7984 7985(define_expand "abs<mode>2" 7986 [(parallel 7987 [(set (match_operand:BFP 0 "register_operand" "=f") 7988 (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) 7989 (clobber (reg:CC CC_REGNUM))])] 7990 "TARGET_HARD_FLOAT" 7991 "") 7992 7993; lpxbr, lpdbr, lpebr 7994(define_insn "*abs<mode>2_cc" 7995 [(set (reg CC_REGNUM) 7996 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) 7997 (match_operand:BFP 2 "const0_operand" ""))) 7998 (set (match_operand:BFP 0 "register_operand" "=f") 7999 (abs:BFP (match_dup 1)))] 8000 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8001 "lp<xde>br\t%0,%1" 8002 [(set_attr "op_type" "RRE") 8003 (set_attr "type" "fsimp<mode>")]) 8004 8005; lpxbr, lpdbr, lpebr 8006(define_insn "*abs<mode>2_cconly" 8007 [(set (reg CC_REGNUM) 8008 (compare (abs:BFP (match_operand:BFP 1 "register_operand" "f")) 8009 (match_operand:BFP 2 "const0_operand" ""))) 8010 (clobber (match_scratch:BFP 0 "=f"))] 8011 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8012 "lp<xde>br\t%0,%1" 8013 [(set_attr "op_type" "RRE") 8014 (set_attr "type" "fsimp<mode>")]) 8015 8016; lpdfr 8017(define_insn "*abs<mode>2_nocc" 8018 [(set (match_operand:FP 0 "register_operand" "=f") 8019 (abs:FP (match_operand:FP 1 "register_operand" "<fT0>")))] 8020 "TARGET_DFP" 8021 "lpdfr\t%0,%1" 8022 [(set_attr "op_type" "RRE") 8023 (set_attr "type" "fsimp<mode>")]) 8024 8025; lpxbr, lpdbr, lpebr 8026; FIXME: wflpdb does not clobber cc 8027(define_insn "*abs<mode>2" 8028 [(set (match_operand:BFP 0 "register_operand" "=f,<vf>") 8029 (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>"))) 8030 (clobber (reg:CC CC_REGNUM))] 8031 "TARGET_HARD_FLOAT" 8032 "@ 8033 lp<xde>br\t%0,%1 8034 wflpdb\t%0,%1" 8035 [(set_attr "op_type" "RRE,VRR") 8036 (set_attr "cpu_facility" "*,vec") 8037 (set_attr "type" "fsimp<mode>,*")]) 8038 8039 8040;; 8041;;- Negated absolute value instructions 8042;; 8043 8044; 8045; Integer 8046; 8047 8048(define_insn "*negabsdi2_sign_cc" 8049 [(set (reg CC_REGNUM) 8050 (compare (neg:DI (abs:DI (ashiftrt:DI (ashift:DI (subreg:DI 8051 (match_operand:SI 1 "register_operand" "d") 0) 8052 (const_int 32)) (const_int 32)))) 8053 (const_int 0))) 8054 (set (match_operand:DI 0 "register_operand" "=d") 8055 (neg:DI (abs:DI (sign_extend:DI (match_dup 1)))))] 8056 "TARGET_ZARCH && s390_match_ccmode (insn, CCAmode)" 8057 "lngfr\t%0,%1" 8058 [(set_attr "op_type" "RRE") 8059 (set_attr "z10prop" "z10_c")]) 8060 8061(define_insn "*negabsdi2_sign" 8062 [(set (match_operand:DI 0 "register_operand" "=d") 8063 (neg:DI (abs:DI (sign_extend:DI 8064 (match_operand:SI 1 "register_operand" "d"))))) 8065 (clobber (reg:CC CC_REGNUM))] 8066 "TARGET_ZARCH" 8067 "lngfr\t%0,%1" 8068 [(set_attr "op_type" "RRE") 8069 (set_attr "z10prop" "z10_c")]) 8070 8071; lnr, lngr 8072(define_insn "*negabs<mode>2_cc" 8073 [(set (reg CC_REGNUM) 8074 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) 8075 (const_int 0))) 8076 (set (match_operand:GPR 0 "register_operand" "=d") 8077 (neg:GPR (abs:GPR (match_dup 1))))] 8078 "s390_match_ccmode (insn, CCAmode)" 8079 "ln<g>r\t%0,%1" 8080 [(set_attr "op_type" "RR<E>") 8081 (set_attr "z10prop" "z10_c")]) 8082 8083; lnr, lngr 8084(define_insn "*negabs<mode>2_cconly" 8085 [(set (reg CC_REGNUM) 8086 (compare (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d"))) 8087 (const_int 0))) 8088 (clobber (match_scratch:GPR 0 "=d"))] 8089 "s390_match_ccmode (insn, CCAmode)" 8090 "ln<g>r\t%0,%1" 8091 [(set_attr "op_type" "RR<E>") 8092 (set_attr "z10prop" "z10_c")]) 8093 8094; lnr, lngr 8095(define_insn "*negabs<mode>2" 8096 [(set (match_operand:GPR 0 "register_operand" "=d") 8097 (neg:GPR (abs:GPR (match_operand:GPR 1 "register_operand" "d")))) 8098 (clobber (reg:CC CC_REGNUM))] 8099 "" 8100 "ln<g>r\t%0,%1" 8101 [(set_attr "op_type" "RR<E>") 8102 (set_attr "z10prop" "z10_c")]) 8103 8104; 8105; Floating point 8106; 8107 8108; lnxbr, lndbr, lnebr 8109(define_insn "*negabs<mode>2_cc" 8110 [(set (reg CC_REGNUM) 8111 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) 8112 (match_operand:BFP 2 "const0_operand" ""))) 8113 (set (match_operand:BFP 0 "register_operand" "=f") 8114 (neg:BFP (abs:BFP (match_dup 1))))] 8115 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8116 "ln<xde>br\t%0,%1" 8117 [(set_attr "op_type" "RRE") 8118 (set_attr "type" "fsimp<mode>")]) 8119 8120; lnxbr, lndbr, lnebr 8121(define_insn "*negabs<mode>2_cconly" 8122 [(set (reg CC_REGNUM) 8123 (compare (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f"))) 8124 (match_operand:BFP 2 "const0_operand" ""))) 8125 (clobber (match_scratch:BFP 0 "=f"))] 8126 "s390_match_ccmode (insn, CCSmode) && TARGET_HARD_FLOAT" 8127 "ln<xde>br\t%0,%1" 8128 [(set_attr "op_type" "RRE") 8129 (set_attr "type" "fsimp<mode>")]) 8130 8131; lndfr 8132(define_insn "*negabs<mode>2_nocc" 8133 [(set (match_operand:FP 0 "register_operand" "=f") 8134 (neg:FP (abs:FP (match_operand:BFP 1 "register_operand" "<fT0>"))))] 8135 "TARGET_DFP" 8136 "lndfr\t%0,%1" 8137 [(set_attr "op_type" "RRE") 8138 (set_attr "type" "fsimp<mode>")]) 8139 8140; lnxbr, lndbr, lnebr 8141; FIXME: wflndb does not clobber cc 8142(define_insn "*negabs<mode>2" 8143 [(set (match_operand:BFP 0 "register_operand" "=f,<vf>") 8144 (neg:BFP (abs:BFP (match_operand:BFP 1 "register_operand" "f,<vf>")))) 8145 (clobber (reg:CC CC_REGNUM))] 8146 "TARGET_HARD_FLOAT" 8147 "@ 8148 ln<xde>br\t%0,%1 8149 wflndb\t%0,%1" 8150 [(set_attr "op_type" "RRE,VRR") 8151 (set_attr "cpu_facility" "*,vec") 8152 (set_attr "type" "fsimp<mode>,*")]) 8153 8154;; 8155;;- Square root instructions. 8156;; 8157 8158; 8159; sqrt(df|sf)2 instruction pattern(s). 8160; 8161 8162; sqxbr, sqdbr, sqebr, sqdb, sqeb 8163(define_insn "sqrt<mode>2" 8164 [(set (match_operand:BFP 0 "register_operand" "=f, f,<vf>") 8165 (sqrt:BFP (match_operand:BFP 1 "general_operand" "f,<Rf>,<vf>")))] 8166 "TARGET_HARD_FLOAT" 8167 "@ 8168 sq<xde>br\t%0,%1 8169 sq<xde>b\t%0,%1 8170 wfsqdb\t%v0,%v1" 8171 [(set_attr "op_type" "RRE,RXE,VRR") 8172 (set_attr "type" "fsqrt<mode>") 8173 (set_attr "cpu_facility" "*,*,vec")]) 8174 8175 8176;; 8177;;- One complement instructions. 8178;; 8179 8180; 8181; one_cmpl(di|si|hi|qi)2 instruction pattern(s). 8182; 8183 8184(define_expand "one_cmpl<mode>2" 8185 [(parallel 8186 [(set (match_operand:INT 0 "register_operand" "") 8187 (xor:INT (match_operand:INT 1 "register_operand" "") 8188 (const_int -1))) 8189 (clobber (reg:CC CC_REGNUM))])] 8190 "" 8191 "") 8192 8193 8194;; 8195;; Find leftmost bit instructions. 8196;; 8197 8198(define_expand "clzdi2" 8199 [(set (match_operand:DI 0 "register_operand" "=d") 8200 (clz:DI (match_operand:DI 1 "register_operand" "d")))] 8201 "TARGET_EXTIMM && TARGET_ZARCH" 8202{ 8203 rtx insn, clz_equal; 8204 rtx wide_reg = gen_reg_rtx (TImode); 8205 rtx msb = gen_rtx_CONST_INT (DImode, (unsigned HOST_WIDE_INT) 1 << 63); 8206 8207 clz_equal = gen_rtx_CLZ (DImode, operands[1]); 8208 8209 emit_insn (gen_clztidi2 (wide_reg, operands[1], msb)); 8210 8211 insn = emit_move_insn (operands[0], gen_highpart (DImode, wide_reg)); 8212 set_unique_reg_note (insn, REG_EQUAL, clz_equal); 8213 8214 DONE; 8215}) 8216 8217(define_insn "clztidi2" 8218 [(set (match_operand:TI 0 "register_operand" "=d") 8219 (ior:TI 8220 (ashift:TI 8221 (zero_extend:TI 8222 (xor:DI (match_operand:DI 1 "register_operand" "d") 8223 (lshiftrt (match_operand:DI 2 "const_int_operand" "") 8224 (subreg:SI (clz:DI (match_dup 1)) 4)))) 8225 8226 (const_int 64)) 8227 (zero_extend:TI (clz:DI (match_dup 1))))) 8228 (clobber (reg:CC CC_REGNUM))] 8229 "(unsigned HOST_WIDE_INT) INTVAL (operands[2]) 8230 == (unsigned HOST_WIDE_INT) 1 << 63 8231 && TARGET_EXTIMM && TARGET_ZARCH" 8232 "flogr\t%0,%1" 8233 [(set_attr "op_type" "RRE")]) 8234 8235 8236;; 8237;;- Rotate instructions. 8238;; 8239 8240; 8241; rotl(di|si)3 instruction pattern(s). 8242; 8243 8244; rll, rllg 8245(define_insn "rotl<mode>3" 8246 [(set (match_operand:GPR 0 "register_operand" "=d") 8247 (rotate:GPR (match_operand:GPR 1 "register_operand" "d") 8248 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] 8249 "TARGET_CPU_ZARCH" 8250 "rll<g>\t%0,%1,%Y2" 8251 [(set_attr "op_type" "RSE") 8252 (set_attr "atype" "reg") 8253 (set_attr "z10prop" "z10_super_E1")]) 8254 8255; rll, rllg 8256(define_insn "*rotl<mode>3_and" 8257 [(set (match_operand:GPR 0 "register_operand" "=d") 8258 (rotate:GPR (match_operand:GPR 1 "register_operand" "d") 8259 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") 8260 (match_operand:SI 3 "const_int_operand" "n"))))] 8261 "TARGET_CPU_ZARCH && (INTVAL (operands[3]) & 63) == 63" 8262 "rll<g>\t%0,%1,%Y2" 8263 [(set_attr "op_type" "RSE") 8264 (set_attr "atype" "reg") 8265 (set_attr "z10prop" "z10_super_E1")]) 8266 8267 8268;; 8269;;- Shift instructions. 8270;; 8271 8272; 8273; (ashl|lshr)(di|si)3 instruction pattern(s). 8274; Left shifts and logical right shifts 8275 8276(define_expand "<shift><mode>3" 8277 [(set (match_operand:DSI 0 "register_operand" "") 8278 (SHIFT:DSI (match_operand:DSI 1 "register_operand" "") 8279 (match_operand:SI 2 "shift_count_or_setmem_operand" "")))] 8280 "" 8281 "") 8282 8283; sldl, srdl 8284(define_insn "*<shift>di3_31" 8285 [(set (match_operand:DI 0 "register_operand" "=d") 8286 (SHIFT:DI (match_operand:DI 1 "register_operand" "0") 8287 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")))] 8288 "!TARGET_ZARCH" 8289 "s<lr>dl\t%0,%Y2" 8290 [(set_attr "op_type" "RS") 8291 (set_attr "atype" "reg") 8292 (set_attr "z196prop" "z196_cracked")]) 8293 8294; sll, srl, sllg, srlg, sllk, srlk 8295(define_insn "*<shift><mode>3" 8296 [(set (match_operand:GPR 0 "register_operand" "=d,d") 8297 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") 8298 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")))] 8299 "" 8300 "@ 8301 s<lr>l<g>\t%0,<1>%Y2 8302 s<lr>l<gk>\t%0,%1,%Y2" 8303 [(set_attr "op_type" "RS<E>,RSY") 8304 (set_attr "atype" "reg,reg") 8305 (set_attr "cpu_facility" "*,z196") 8306 (set_attr "z10prop" "z10_super_E1,*")]) 8307 8308; sldl, srdl 8309(define_insn "*<shift>di3_31_and" 8310 [(set (match_operand:DI 0 "register_operand" "=d") 8311 (SHIFT:DI (match_operand:DI 1 "register_operand" "0") 8312 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") 8313 (match_operand:SI 3 "const_int_operand" "n"))))] 8314 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" 8315 "s<lr>dl\t%0,%Y2" 8316 [(set_attr "op_type" "RS") 8317 (set_attr "atype" "reg")]) 8318 8319; sll, srl, sllg, srlg, sllk, srlk 8320(define_insn "*<shift><mode>3_and" 8321 [(set (match_operand:GPR 0 "register_operand" "=d,d") 8322 (SHIFT:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") 8323 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") 8324 (match_operand:SI 3 "const_int_operand" "n,n"))))] 8325 "(INTVAL (operands[3]) & 63) == 63" 8326 "@ 8327 s<lr>l<g>\t%0,<1>%Y2 8328 s<lr>l<gk>\t%0,%1,%Y2" 8329 [(set_attr "op_type" "RS<E>,RSY") 8330 (set_attr "atype" "reg,reg") 8331 (set_attr "cpu_facility" "*,z196") 8332 (set_attr "z10prop" "z10_super_E1,*")]) 8333 8334; 8335; ashr(di|si)3 instruction pattern(s). 8336; Arithmetic right shifts 8337 8338(define_expand "ashr<mode>3" 8339 [(parallel 8340 [(set (match_operand:DSI 0 "register_operand" "") 8341 (ashiftrt:DSI (match_operand:DSI 1 "register_operand" "") 8342 (match_operand:SI 2 "shift_count_or_setmem_operand" ""))) 8343 (clobber (reg:CC CC_REGNUM))])] 8344 "" 8345 "") 8346 8347(define_insn "*ashrdi3_cc_31" 8348 [(set (reg CC_REGNUM) 8349 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 8350 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) 8351 (const_int 0))) 8352 (set (match_operand:DI 0 "register_operand" "=d") 8353 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 8354 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" 8355 "srda\t%0,%Y2" 8356 [(set_attr "op_type" "RS") 8357 (set_attr "atype" "reg")]) 8358 8359(define_insn "*ashrdi3_cconly_31" 8360 [(set (reg CC_REGNUM) 8361 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 8362 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y")) 8363 (const_int 0))) 8364 (clobber (match_scratch:DI 0 "=d"))] 8365 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode)" 8366 "srda\t%0,%Y2" 8367 [(set_attr "op_type" "RS") 8368 (set_attr "atype" "reg")]) 8369 8370(define_insn "*ashrdi3_31" 8371 [(set (match_operand:DI 0 "register_operand" "=d") 8372 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 8373 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y"))) 8374 (clobber (reg:CC CC_REGNUM))] 8375 "!TARGET_ZARCH" 8376 "srda\t%0,%Y2" 8377 [(set_attr "op_type" "RS") 8378 (set_attr "atype" "reg")]) 8379 8380; sra, srag, srak 8381(define_insn "*ashr<mode>3_cc" 8382 [(set (reg CC_REGNUM) 8383 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") 8384 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) 8385 (const_int 0))) 8386 (set (match_operand:GPR 0 "register_operand" "=d,d") 8387 (ashiftrt:GPR (match_dup 1) (match_dup 2)))] 8388 "s390_match_ccmode(insn, CCSmode)" 8389 "@ 8390 sra<g>\t%0,<1>%Y2 8391 sra<gk>\t%0,%1,%Y2" 8392 [(set_attr "op_type" "RS<E>,RSY") 8393 (set_attr "atype" "reg,reg") 8394 (set_attr "cpu_facility" "*,z196") 8395 (set_attr "z10prop" "z10_super_E1,*")]) 8396 8397; sra, srag, srak 8398(define_insn "*ashr<mode>3_cconly" 8399 [(set (reg CC_REGNUM) 8400 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") 8401 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y")) 8402 (const_int 0))) 8403 (clobber (match_scratch:GPR 0 "=d,d"))] 8404 "s390_match_ccmode(insn, CCSmode)" 8405 "@ 8406 sra<g>\t%0,<1>%Y2 8407 sra<gk>\t%0,%1,%Y2" 8408 [(set_attr "op_type" "RS<E>,RSY") 8409 (set_attr "atype" "reg,reg") 8410 (set_attr "cpu_facility" "*,z196") 8411 (set_attr "z10prop" "z10_super_E1,*")]) 8412 8413; sra, srag 8414(define_insn "*ashr<mode>3" 8415 [(set (match_operand:GPR 0 "register_operand" "=d,d") 8416 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") 8417 (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y"))) 8418 (clobber (reg:CC CC_REGNUM))] 8419 "" 8420 "@ 8421 sra<g>\t%0,<1>%Y2 8422 sra<gk>\t%0,%1,%Y2" 8423 [(set_attr "op_type" "RS<E>,RSY") 8424 (set_attr "atype" "reg,reg") 8425 (set_attr "cpu_facility" "*,z196") 8426 (set_attr "z10prop" "z10_super_E1,*")]) 8427 8428 8429; shift pattern with implicit ANDs 8430 8431(define_insn "*ashrdi3_cc_31_and" 8432 [(set (reg CC_REGNUM) 8433 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 8434 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") 8435 (match_operand:SI 3 "const_int_operand" "n"))) 8436 (const_int 0))) 8437 (set (match_operand:DI 0 "register_operand" "=d") 8438 (ashiftrt:DI (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] 8439 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) 8440 && (INTVAL (operands[3]) & 63) == 63" 8441 "srda\t%0,%Y2" 8442 [(set_attr "op_type" "RS") 8443 (set_attr "atype" "reg")]) 8444 8445(define_insn "*ashrdi3_cconly_31_and" 8446 [(set (reg CC_REGNUM) 8447 (compare (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 8448 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") 8449 (match_operand:SI 3 "const_int_operand" "n"))) 8450 (const_int 0))) 8451 (clobber (match_scratch:DI 0 "=d"))] 8452 "!TARGET_ZARCH && s390_match_ccmode(insn, CCSmode) 8453 && (INTVAL (operands[3]) & 63) == 63" 8454 "srda\t%0,%Y2" 8455 [(set_attr "op_type" "RS") 8456 (set_attr "atype" "reg")]) 8457 8458(define_insn "*ashrdi3_31_and" 8459 [(set (match_operand:DI 0 "register_operand" "=d") 8460 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 8461 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y") 8462 (match_operand:SI 3 "const_int_operand" "n")))) 8463 (clobber (reg:CC CC_REGNUM))] 8464 "!TARGET_ZARCH && (INTVAL (operands[3]) & 63) == 63" 8465 "srda\t%0,%Y2" 8466 [(set_attr "op_type" "RS") 8467 (set_attr "atype" "reg")]) 8468 8469; sra, srag, srak 8470(define_insn "*ashr<mode>3_cc_and" 8471 [(set (reg CC_REGNUM) 8472 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") 8473 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") 8474 (match_operand:SI 3 "const_int_operand" "n,n"))) 8475 (const_int 0))) 8476 (set (match_operand:GPR 0 "register_operand" "=d,d") 8477 (ashiftrt:GPR (match_dup 1) (and:SI (match_dup 2) (match_dup 3))))] 8478 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" 8479 "@ 8480 sra<g>\t%0,<1>%Y2 8481 sra<gk>\t%0,%1,%Y2" 8482 [(set_attr "op_type" "RS<E>,RSY") 8483 (set_attr "atype" "reg,reg") 8484 (set_attr "cpu_facility" "*,z196") 8485 (set_attr "z10prop" "z10_super_E1,*")]) 8486 8487; sra, srag, srak 8488(define_insn "*ashr<mode>3_cconly_and" 8489 [(set (reg CC_REGNUM) 8490 (compare (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") 8491 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") 8492 (match_operand:SI 3 "const_int_operand" "n,n"))) 8493 (const_int 0))) 8494 (clobber (match_scratch:GPR 0 "=d,d"))] 8495 "s390_match_ccmode(insn, CCSmode) && (INTVAL (operands[3]) & 63) == 63" 8496 "@ 8497 sra<g>\t%0,<1>%Y2 8498 sra<gk>\t%0,%1,%Y2" 8499 [(set_attr "op_type" "RS<E>,RSY") 8500 (set_attr "atype" "reg,reg") 8501 (set_attr "cpu_facility" "*,z196") 8502 (set_attr "z10prop" "z10_super_E1,*")]) 8503 8504; sra, srag, srak 8505(define_insn "*ashr<mode>3_and" 8506 [(set (match_operand:GPR 0 "register_operand" "=d,d") 8507 (ashiftrt:GPR (match_operand:GPR 1 "register_operand" "<d0>,d") 8508 (and:SI (match_operand:SI 2 "shift_count_or_setmem_operand" "Y,Y") 8509 (match_operand:SI 3 "const_int_operand" "n,n")))) 8510 (clobber (reg:CC CC_REGNUM))] 8511 "(INTVAL (operands[3]) & 63) == 63" 8512 "@ 8513 sra<g>\t%0,<1>%Y2 8514 sra<gk>\t%0,%1,%Y2" 8515 [(set_attr "op_type" "RS<E>,RSY") 8516 (set_attr "atype" "reg,reg") 8517 (set_attr "cpu_facility" "*,z196") 8518 (set_attr "z10prop" "z10_super_E1,*")]) 8519 8520 8521;; 8522;; Branch instruction patterns. 8523;; 8524 8525(define_expand "cbranch<mode>4" 8526 [(set (pc) 8527 (if_then_else (match_operator 0 "comparison_operator" 8528 [(match_operand:GPR 1 "register_operand" "") 8529 (match_operand:GPR 2 "general_operand" "")]) 8530 (label_ref (match_operand 3 "" "")) 8531 (pc)))] 8532 "" 8533 "s390_emit_jump (operands[3], 8534 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); 8535 DONE;") 8536 8537(define_expand "cbranch<mode>4" 8538 [(set (pc) 8539 (if_then_else (match_operator 0 "comparison_operator" 8540 [(match_operand:FP 1 "register_operand" "") 8541 (match_operand:FP 2 "general_operand" "")]) 8542 (label_ref (match_operand 3 "" "")) 8543 (pc)))] 8544 "TARGET_HARD_FLOAT" 8545 "s390_emit_jump (operands[3], 8546 s390_emit_compare (GET_CODE (operands[0]), operands[1], operands[2])); 8547 DONE;") 8548 8549(define_expand "cbranchcc4" 8550 [(set (pc) 8551 (if_then_else (match_operator 0 "s390_comparison" 8552 [(match_operand 1 "cc_reg_operand" "") 8553 (match_operand 2 "const_int_operand" "")]) 8554 (label_ref (match_operand 3 "" "")) 8555 (pc)))] 8556 "" 8557 "") 8558 8559 8560;; 8561;;- Conditional jump instructions. 8562;; 8563 8564(define_insn "*cjump_64" 8565 [(set (pc) 8566 (if_then_else 8567 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) 8568 (match_operand 2 "const_int_operand" "")]) 8569 (label_ref (match_operand 0 "" "")) 8570 (pc)))] 8571 "TARGET_CPU_ZARCH" 8572{ 8573 if (get_attr_length (insn) == 4) 8574 return "j%C1\t%l0"; 8575 else 8576 return "jg%C1\t%l0"; 8577} 8578 [(set_attr "op_type" "RI") 8579 (set_attr "type" "branch") 8580 (set (attr "length") 8581 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 8582 (const_int 4) (const_int 6)))]) 8583 8584(define_insn "*cjump_31" 8585 [(set (pc) 8586 (if_then_else 8587 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) 8588 (match_operand 2 "const_int_operand" "")]) 8589 (label_ref (match_operand 0 "" "")) 8590 (pc)))] 8591 "!TARGET_CPU_ZARCH" 8592{ 8593 gcc_assert (get_attr_length (insn) == 4); 8594 return "j%C1\t%l0"; 8595} 8596 [(set_attr "op_type" "RI") 8597 (set_attr "type" "branch") 8598 (set (attr "length") 8599 (if_then_else (not (match_test "flag_pic")) 8600 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 8601 (const_int 4) (const_int 6)) 8602 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 8603 (const_int 4) (const_int 8))))]) 8604 8605(define_insn "*cjump_long" 8606 [(set (pc) 8607 (if_then_else 8608 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 8609 (match_operand 0 "address_operand" "ZQZR") 8610 (pc)))] 8611 "" 8612{ 8613 if (get_attr_op_type (insn) == OP_TYPE_RR) 8614 return "b%C1r\t%0"; 8615 else 8616 return "b%C1\t%a0"; 8617} 8618 [(set (attr "op_type") 8619 (if_then_else (match_operand 0 "register_operand" "") 8620 (const_string "RR") (const_string "RX"))) 8621 (set_attr "type" "branch") 8622 (set_attr "atype" "agen")]) 8623 8624;; A conditional return instruction. 8625(define_insn "*c<code>" 8626 [(set (pc) 8627 (if_then_else 8628 (match_operator 0 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 8629 (ANY_RETURN) 8630 (pc)))] 8631 "s390_can_use_<code>_insn ()" 8632 "b%C0r\t%%r14" 8633 [(set_attr "op_type" "RR") 8634 (set_attr "type" "jsr") 8635 (set_attr "atype" "agen")]) 8636 8637;; 8638;;- Negated conditional jump instructions. 8639;; 8640 8641(define_insn "*icjump_64" 8642 [(set (pc) 8643 (if_then_else 8644 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 8645 (pc) 8646 (label_ref (match_operand 0 "" ""))))] 8647 "TARGET_CPU_ZARCH" 8648{ 8649 if (get_attr_length (insn) == 4) 8650 return "j%D1\t%l0"; 8651 else 8652 return "jg%D1\t%l0"; 8653} 8654 [(set_attr "op_type" "RI") 8655 (set_attr "type" "branch") 8656 (set (attr "length") 8657 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 8658 (const_int 4) (const_int 6)))]) 8659 8660(define_insn "*icjump_31" 8661 [(set (pc) 8662 (if_then_else 8663 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 8664 (pc) 8665 (label_ref (match_operand 0 "" ""))))] 8666 "!TARGET_CPU_ZARCH" 8667{ 8668 gcc_assert (get_attr_length (insn) == 4); 8669 return "j%D1\t%l0"; 8670} 8671 [(set_attr "op_type" "RI") 8672 (set_attr "type" "branch") 8673 (set (attr "length") 8674 (if_then_else (not (match_test "flag_pic")) 8675 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 8676 (const_int 4) (const_int 6)) 8677 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 8678 (const_int 4) (const_int 8))))]) 8679 8680(define_insn "*icjump_long" 8681 [(set (pc) 8682 (if_then_else 8683 (match_operator 1 "s390_comparison" [(reg CC_REGNUM) (const_int 0)]) 8684 (pc) 8685 (match_operand 0 "address_operand" "ZQZR")))] 8686 "" 8687{ 8688 if (get_attr_op_type (insn) == OP_TYPE_RR) 8689 return "b%D1r\t%0"; 8690 else 8691 return "b%D1\t%a0"; 8692} 8693 [(set (attr "op_type") 8694 (if_then_else (match_operand 0 "register_operand" "") 8695 (const_string "RR") (const_string "RX"))) 8696 (set_attr "type" "branch") 8697 (set_attr "atype" "agen")]) 8698 8699;; 8700;;- Trap instructions. 8701;; 8702 8703(define_insn "trap" 8704 [(trap_if (const_int 1) (const_int 0))] 8705 "" 8706 "j\t.+2" 8707 [(set_attr "op_type" "RI") 8708 (set_attr "type" "branch")]) 8709 8710(define_expand "ctrap<mode>4" 8711 [(trap_if (match_operator 0 "comparison_operator" 8712 [(match_operand:GPR 1 "register_operand" "") 8713 (match_operand:GPR 2 "general_operand" "")]) 8714 (match_operand 3 "const0_operand" ""))] 8715 "" 8716 { 8717 rtx cond = s390_emit_compare (GET_CODE (operands[0]), 8718 operands[1], operands[2]); 8719 emit_insn (gen_condtrap (cond, XEXP (cond, 0))); 8720 DONE; 8721 }) 8722 8723(define_expand "ctrap<mode>4" 8724 [(trap_if (match_operator 0 "comparison_operator" 8725 [(match_operand:FP 1 "register_operand" "") 8726 (match_operand:FP 2 "general_operand" "")]) 8727 (match_operand 3 "const0_operand" ""))] 8728 "" 8729 { 8730 rtx cond = s390_emit_compare (GET_CODE (operands[0]), 8731 operands[1], operands[2]); 8732 emit_insn (gen_condtrap (cond, XEXP (cond, 0))); 8733 DONE; 8734 }) 8735 8736(define_insn "condtrap" 8737 [(trap_if (match_operator 0 "s390_comparison" 8738 [(match_operand 1 "cc_reg_operand" "c") 8739 (const_int 0)]) 8740 (const_int 0))] 8741 "" 8742 "j%C0\t.+2"; 8743 [(set_attr "op_type" "RI") 8744 (set_attr "type" "branch")]) 8745 8746; crt, cgrt, cit, cgit 8747(define_insn "*cmp_and_trap_signed_int<mode>" 8748 [(trap_if (match_operator 0 "s390_signed_integer_comparison" 8749 [(match_operand:GPR 1 "register_operand" "d,d") 8750 (match_operand:GPR 2 "nonmemory_operand" "d,K")]) 8751 (const_int 0))] 8752 "TARGET_Z10" 8753 "@ 8754 c<g>rt%C0\t%1,%2 8755 c<g>it%C0\t%1,%h2" 8756 [(set_attr "op_type" "RRF,RIE") 8757 (set_attr "type" "branch") 8758 (set_attr "z10prop" "z10_super_c,z10_super")]) 8759 8760; clrt, clgrt, clfit, clgit, clt, clgt 8761(define_insn "*cmp_and_trap_unsigned_int<mode>" 8762 [(trap_if (match_operator 0 "s390_unsigned_integer_comparison" 8763 [(match_operand:GPR 1 "register_operand" "d,d, d") 8764 (match_operand:GPR 2 "general_operand" "d,D,RT")]) 8765 (const_int 0))] 8766 "TARGET_Z10" 8767 "@ 8768 cl<g>rt%C0\t%1,%2 8769 cl<gf>it%C0\t%1,%x2 8770 cl<g>t%C0\t%1,%2" 8771 [(set_attr "op_type" "RRF,RIE,RSY") 8772 (set_attr "type" "branch") 8773 (set_attr "z10prop" "z10_super_c,z10_super,*") 8774 (set_attr "cpu_facility" "z10,z10,zEC12")]) 8775 8776; lat, lgat 8777(define_insn "*load_and_trap<mode>" 8778 [(trap_if (eq (match_operand:GPR 0 "memory_operand" "RT") 8779 (const_int 0)) 8780 (const_int 0)) 8781 (set (match_operand:GPR 1 "register_operand" "=d") 8782 (match_dup 0))] 8783 "TARGET_ZEC12" 8784 "l<g>at\t%1,%0" 8785 [(set_attr "op_type" "RXY")]) 8786 8787 8788;; 8789;;- Loop instructions. 8790;; 8791;; This is all complicated by the fact that since this is a jump insn 8792;; we must handle our own output reloads. 8793 8794;; branch on index 8795 8796; This splitter will be matched by combine and has to add the 2 moves 8797; necessary to load the compare and the increment values into a 8798; register pair as needed by brxle. 8799 8800(define_insn_and_split "*brx_stage1_<GPR:mode>" 8801 [(set (pc) 8802 (if_then_else 8803 (match_operator 6 "s390_brx_operator" 8804 [(plus:GPR (match_operand:GPR 1 "register_operand" "") 8805 (match_operand:GPR 2 "general_operand" "")) 8806 (match_operand:GPR 3 "register_operand" "")]) 8807 (label_ref (match_operand 0 "" "")) 8808 (pc))) 8809 (set (match_operand:GPR 4 "nonimmediate_operand" "") 8810 (plus:GPR (match_dup 1) (match_dup 2))) 8811 (clobber (match_scratch:GPR 5 ""))] 8812 "TARGET_CPU_ZARCH" 8813 "#" 8814 "!reload_completed && !reload_in_progress" 8815 [(set (match_dup 7) (match_dup 2)) ; the increment 8816 (set (match_dup 8) (match_dup 3)) ; the comparison value 8817 (parallel [(set (pc) 8818 (if_then_else 8819 (match_op_dup 6 8820 [(plus:GPR (match_dup 1) (match_dup 7)) 8821 (match_dup 8)]) 8822 (label_ref (match_dup 0)) 8823 (pc))) 8824 (set (match_dup 4) 8825 (plus:GPR (match_dup 1) (match_dup 7))) 8826 (clobber (match_dup 5)) 8827 (clobber (reg:CC CC_REGNUM))])] 8828 { 8829 rtx dreg = gen_reg_rtx (word_mode == DImode ? TImode : DImode); 8830 operands[7] = gen_lowpart (<GPR:MODE>mode, 8831 gen_highpart (word_mode, dreg)); 8832 operands[8] = gen_lowpart (<GPR:MODE>mode, 8833 gen_lowpart (word_mode, dreg)); 8834 }) 8835 8836; brxlg, brxhg 8837 8838(define_insn_and_split "*brxg_64bit" 8839 [(set (pc) 8840 (if_then_else 8841 (match_operator 5 "s390_brx_operator" 8842 [(plus:DI (match_operand:DI 1 "register_operand" "d,d,d") 8843 (subreg:DI (match_operand:TI 2 "register_operand" "d,d,d") 0)) 8844 (subreg:DI (match_dup 2) 8)]) 8845 (label_ref (match_operand 0 "" "")) 8846 (pc))) 8847 (set (match_operand:DI 3 "nonimmediate_operand" "=1,?X,?X") 8848 (plus:DI (match_dup 1) 8849 (subreg:DI (match_dup 2) 0))) 8850 (clobber (match_scratch:DI 4 "=X,&1,&?d")) 8851 (clobber (reg:CC CC_REGNUM))] 8852 "TARGET_ZARCH" 8853{ 8854 if (which_alternative != 0) 8855 return "#"; 8856 else if (get_attr_length (insn) == 6) 8857 return "brx%E5g\t%1,%2,%l0"; 8858 else 8859 return "agr\t%1,%2\;cgr\t%1,%M2\;jg%C5\t%l0"; 8860} 8861 "&& reload_completed 8862 && (!REG_P (operands[3]) 8863 || !rtx_equal_p (operands[1], operands[3]))" 8864 [(set (match_dup 4) (match_dup 1)) 8865 (parallel [(set (match_dup 4) (plus:DI (match_dup 4) (subreg:DI (match_dup 2) 0))) 8866 (clobber (reg:CC CC_REGNUM))]) 8867 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:DI (match_dup 2) 8))) 8868 (set (match_dup 3) (match_dup 4)) 8869 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) 8870 (label_ref (match_dup 0)) 8871 (pc)))] 8872 "" 8873 [(set_attr "op_type" "RIE") 8874 (set_attr "type" "branch") 8875 (set (attr "length") 8876 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 8877 (const_int 6) (const_int 16)))]) 8878 8879; brxle, brxh 8880 8881(define_insn_and_split "*brx_64bit" 8882 [(set (pc) 8883 (if_then_else 8884 (match_operator 5 "s390_brx_operator" 8885 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") 8886 (subreg:SI (match_operand:TI 2 "register_operand" "d,d,d") 4)) 8887 (subreg:SI (match_dup 2) 12)]) 8888 (label_ref (match_operand 0 "" "")) 8889 (pc))) 8890 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") 8891 (plus:SI (match_dup 1) 8892 (subreg:SI (match_dup 2) 4))) 8893 (clobber (match_scratch:SI 4 "=X,&1,&?d")) 8894 (clobber (reg:CC CC_REGNUM))] 8895 "TARGET_ZARCH" 8896{ 8897 if (which_alternative != 0) 8898 return "#"; 8899 else if (get_attr_length (insn) == 6) 8900 return "brx%C5\t%1,%2,%l0"; 8901 else 8902 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; 8903} 8904 "&& reload_completed 8905 && (!REG_P (operands[3]) 8906 || !rtx_equal_p (operands[1], operands[3]))" 8907 [(set (match_dup 4) (match_dup 1)) 8908 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 4))) 8909 (clobber (reg:CC CC_REGNUM))]) 8910 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 12))) 8911 (set (match_dup 3) (match_dup 4)) 8912 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) 8913 (label_ref (match_dup 0)) 8914 (pc)))] 8915 "" 8916 [(set_attr "op_type" "RSI") 8917 (set_attr "type" "branch") 8918 (set (attr "length") 8919 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 8920 (const_int 6) (const_int 14)))]) 8921 8922; brxle, brxh 8923 8924(define_insn_and_split "*brx_31bit" 8925 [(set (pc) 8926 (if_then_else 8927 (match_operator 5 "s390_brx_operator" 8928 [(plus:SI (match_operand:SI 1 "register_operand" "d,d,d") 8929 (subreg:SI (match_operand:DI 2 "register_operand" "d,d,d") 0)) 8930 (subreg:SI (match_dup 2) 4)]) 8931 (label_ref (match_operand 0 "" "")) 8932 (pc))) 8933 (set (match_operand:SI 3 "nonimmediate_operand" "=1,?X,?X") 8934 (plus:SI (match_dup 1) 8935 (subreg:SI (match_dup 2) 0))) 8936 (clobber (match_scratch:SI 4 "=X,&1,&?d")) 8937 (clobber (reg:CC CC_REGNUM))] 8938 "!TARGET_ZARCH && TARGET_CPU_ZARCH" 8939{ 8940 if (which_alternative != 0) 8941 return "#"; 8942 else if (get_attr_length (insn) == 6) 8943 return "brx%C5\t%1,%2,%l0"; 8944 else 8945 return "ar\t%1,%2\;cr\t%1,%M2\;jg%C5\t%l0"; 8946} 8947 "&& reload_completed 8948 && (!REG_P (operands[3]) 8949 || !rtx_equal_p (operands[1], operands[3]))" 8950 [(set (match_dup 4) (match_dup 1)) 8951 (parallel [(set (match_dup 4) (plus:SI (match_dup 4) (subreg:SI (match_dup 2) 0))) 8952 (clobber (reg:CC CC_REGNUM))]) 8953 (set (reg:CCS CC_REGNUM) (compare:CCS (match_dup 4) (subreg:SI (match_dup 2) 4))) 8954 (set (match_dup 3) (match_dup 4)) 8955 (set (pc) (if_then_else (match_op_dup 5 [(reg:CCS CC_REGNUM) (const_int 0)]) 8956 (label_ref (match_dup 0)) 8957 (pc)))] 8958 "" 8959 [(set_attr "op_type" "RSI") 8960 (set_attr "type" "branch") 8961 (set (attr "length") 8962 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 8963 (const_int 6) (const_int 14)))]) 8964 8965 8966;; branch on count 8967 8968(define_expand "doloop_end" 8969 [(use (match_operand 0 "" "")) ; loop pseudo 8970 (use (match_operand 1 "" ""))] ; label 8971 "" 8972{ 8973 if (GET_MODE (operands[0]) == SImode && !TARGET_CPU_ZARCH) 8974 emit_jump_insn (gen_doloop_si31 (operands[1], operands[0], operands[0])); 8975 else if (GET_MODE (operands[0]) == SImode && TARGET_CPU_ZARCH) 8976 emit_jump_insn (gen_doloop_si64 (operands[1], operands[0], operands[0])); 8977 else if (GET_MODE (operands[0]) == DImode && TARGET_ZARCH) 8978 emit_jump_insn (gen_doloop_di (operands[1], operands[0], operands[0])); 8979 else 8980 FAIL; 8981 8982 DONE; 8983}) 8984 8985(define_insn_and_split "doloop_si64" 8986 [(set (pc) 8987 (if_then_else 8988 (ne (match_operand:SI 1 "register_operand" "d,d,d") 8989 (const_int 1)) 8990 (label_ref (match_operand 0 "" "")) 8991 (pc))) 8992 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") 8993 (plus:SI (match_dup 1) (const_int -1))) 8994 (clobber (match_scratch:SI 3 "=X,&1,&?d")) 8995 (clobber (reg:CC CC_REGNUM))] 8996 "TARGET_CPU_ZARCH" 8997{ 8998 if (which_alternative != 0) 8999 return "#"; 9000 else if (get_attr_length (insn) == 4) 9001 return "brct\t%1,%l0"; 9002 else 9003 return "ahi\t%1,-1\;jgne\t%l0"; 9004} 9005 "&& reload_completed 9006 && (! REG_P (operands[2]) 9007 || ! rtx_equal_p (operands[1], operands[2]))" 9008 [(set (match_dup 3) (match_dup 1)) 9009 (parallel [(set (reg:CCAN CC_REGNUM) 9010 (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) 9011 (const_int 0))) 9012 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) 9013 (set (match_dup 2) (match_dup 3)) 9014 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) 9015 (label_ref (match_dup 0)) 9016 (pc)))] 9017 "" 9018 [(set_attr "op_type" "RI") 9019 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not 9020 ; hurt us in the (rare) case of ahi. 9021 (set_attr "z10prop" "z10_super_E1") 9022 (set_attr "type" "branch") 9023 (set (attr "length") 9024 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9025 (const_int 4) (const_int 10)))]) 9026 9027(define_insn_and_split "doloop_si31" 9028 [(set (pc) 9029 (if_then_else 9030 (ne (match_operand:SI 1 "register_operand" "d,d,d") 9031 (const_int 1)) 9032 (label_ref (match_operand 0 "" "")) 9033 (pc))) 9034 (set (match_operand:SI 2 "nonimmediate_operand" "=1,?X,?X") 9035 (plus:SI (match_dup 1) (const_int -1))) 9036 (clobber (match_scratch:SI 3 "=X,&1,&?d")) 9037 (clobber (reg:CC CC_REGNUM))] 9038 "!TARGET_CPU_ZARCH" 9039{ 9040 if (which_alternative != 0) 9041 return "#"; 9042 else if (get_attr_length (insn) == 4) 9043 return "brct\t%1,%l0"; 9044 else 9045 gcc_unreachable (); 9046} 9047 "&& reload_completed 9048 && (! REG_P (operands[2]) 9049 || ! rtx_equal_p (operands[1], operands[2]))" 9050 [(set (match_dup 3) (match_dup 1)) 9051 (parallel [(set (reg:CCAN CC_REGNUM) 9052 (compare:CCAN (plus:SI (match_dup 3) (const_int -1)) 9053 (const_int 0))) 9054 (set (match_dup 3) (plus:SI (match_dup 3) (const_int -1)))]) 9055 (set (match_dup 2) (match_dup 3)) 9056 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) 9057 (label_ref (match_dup 0)) 9058 (pc)))] 9059 "" 9060 [(set_attr "op_type" "RI") 9061 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not 9062 ; hurt us in the (rare) case of ahi. 9063 (set_attr "z10prop" "z10_super_E1") 9064 (set_attr "type" "branch") 9065 (set (attr "length") 9066 (if_then_else (not (match_test "flag_pic")) 9067 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9068 (const_int 4) (const_int 6)) 9069 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9070 (const_int 4) (const_int 8))))]) 9071 9072(define_insn "*doloop_si_long" 9073 [(set (pc) 9074 (if_then_else 9075 (ne (match_operand:SI 1 "register_operand" "d") 9076 (const_int 1)) 9077 (match_operand 0 "address_operand" "ZQZR") 9078 (pc))) 9079 (set (match_operand:SI 2 "register_operand" "=1") 9080 (plus:SI (match_dup 1) (const_int -1))) 9081 (clobber (match_scratch:SI 3 "=X")) 9082 (clobber (reg:CC CC_REGNUM))] 9083 "!TARGET_CPU_ZARCH" 9084{ 9085 if (get_attr_op_type (insn) == OP_TYPE_RR) 9086 return "bctr\t%1,%0"; 9087 else 9088 return "bct\t%1,%a0"; 9089} 9090 [(set (attr "op_type") 9091 (if_then_else (match_operand 0 "register_operand" "") 9092 (const_string "RR") (const_string "RX"))) 9093 (set_attr "type" "branch") 9094 (set_attr "atype" "agen") 9095 (set_attr "z10prop" "z10_c") 9096 (set_attr "z196prop" "z196_cracked")]) 9097 9098(define_insn_and_split "doloop_di" 9099 [(set (pc) 9100 (if_then_else 9101 (ne (match_operand:DI 1 "register_operand" "d,d,d") 9102 (const_int 1)) 9103 (label_ref (match_operand 0 "" "")) 9104 (pc))) 9105 (set (match_operand:DI 2 "nonimmediate_operand" "=1,?X,?X") 9106 (plus:DI (match_dup 1) (const_int -1))) 9107 (clobber (match_scratch:DI 3 "=X,&1,&?d")) 9108 (clobber (reg:CC CC_REGNUM))] 9109 "TARGET_ZARCH" 9110{ 9111 if (which_alternative != 0) 9112 return "#"; 9113 else if (get_attr_length (insn) == 4) 9114 return "brctg\t%1,%l0"; 9115 else 9116 return "aghi\t%1,-1\;jgne\t%l0"; 9117} 9118 "&& reload_completed 9119 && (! REG_P (operands[2]) 9120 || ! rtx_equal_p (operands[1], operands[2]))" 9121 [(set (match_dup 3) (match_dup 1)) 9122 (parallel [(set (reg:CCAN CC_REGNUM) 9123 (compare:CCAN (plus:DI (match_dup 3) (const_int -1)) 9124 (const_int 0))) 9125 (set (match_dup 3) (plus:DI (match_dup 3) (const_int -1)))]) 9126 (set (match_dup 2) (match_dup 3)) 9127 (set (pc) (if_then_else (ne (reg:CCAN CC_REGNUM) (const_int 0)) 9128 (label_ref (match_dup 0)) 9129 (pc)))] 9130 "" 9131 [(set_attr "op_type" "RI") 9132 ; Strictly speaking, the z10 properties are valid for brct only, however, it does not 9133 ; hurt us in the (rare) case of ahi. 9134 (set_attr "z10prop" "z10_super_E1") 9135 (set_attr "type" "branch") 9136 (set (attr "length") 9137 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9138 (const_int 4) (const_int 10)))]) 9139 9140;; 9141;;- Unconditional jump instructions. 9142;; 9143 9144; 9145; jump instruction pattern(s). 9146; 9147 9148(define_expand "jump" 9149 [(match_operand 0 "" "")] 9150 "" 9151 "s390_emit_jump (operands[0], NULL_RTX); DONE;") 9152 9153(define_insn "*jump64" 9154 [(set (pc) (label_ref (match_operand 0 "" "")))] 9155 "TARGET_CPU_ZARCH" 9156{ 9157 if (get_attr_length (insn) == 4) 9158 return "j\t%l0"; 9159 else 9160 return "jg\t%l0"; 9161} 9162 [(set_attr "op_type" "RI") 9163 (set_attr "type" "branch") 9164 (set (attr "length") 9165 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9166 (const_int 4) (const_int 6)))]) 9167 9168(define_insn "*jump31" 9169 [(set (pc) (label_ref (match_operand 0 "" "")))] 9170 "!TARGET_CPU_ZARCH" 9171{ 9172 gcc_assert (get_attr_length (insn) == 4); 9173 return "j\t%l0"; 9174} 9175 [(set_attr "op_type" "RI") 9176 (set_attr "type" "branch") 9177 (set (attr "length") 9178 (if_then_else (not (match_test "flag_pic")) 9179 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9180 (const_int 4) (const_int 6)) 9181 (if_then_else (lt (abs (minus (pc) (match_dup 0))) (const_int 60000)) 9182 (const_int 4) (const_int 8))))]) 9183 9184; 9185; indirect-jump instruction pattern(s). 9186; 9187 9188(define_insn "indirect_jump" 9189 [(set (pc) (match_operand 0 "address_operand" "ZQZR"))] 9190 "" 9191{ 9192 if (get_attr_op_type (insn) == OP_TYPE_RR) 9193 return "br\t%0"; 9194 else 9195 return "b\t%a0"; 9196} 9197 [(set (attr "op_type") 9198 (if_then_else (match_operand 0 "register_operand" "") 9199 (const_string "RR") (const_string "RX"))) 9200 (set_attr "type" "branch") 9201 (set_attr "atype" "agen")]) 9202 9203; 9204; casesi instruction pattern(s). 9205; 9206 9207(define_insn "casesi_jump" 9208 [(set (pc) (match_operand 0 "address_operand" "ZQZR")) 9209 (use (label_ref (match_operand 1 "" "")))] 9210 "" 9211{ 9212 if (get_attr_op_type (insn) == OP_TYPE_RR) 9213 return "br\t%0"; 9214 else 9215 return "b\t%a0"; 9216} 9217 [(set (attr "op_type") 9218 (if_then_else (match_operand 0 "register_operand" "") 9219 (const_string "RR") (const_string "RX"))) 9220 (set_attr "type" "branch") 9221 (set_attr "atype" "agen")]) 9222 9223(define_expand "casesi" 9224 [(match_operand:SI 0 "general_operand" "") 9225 (match_operand:SI 1 "general_operand" "") 9226 (match_operand:SI 2 "general_operand" "") 9227 (label_ref (match_operand 3 "" "")) 9228 (label_ref (match_operand 4 "" ""))] 9229 "" 9230{ 9231 rtx index = gen_reg_rtx (SImode); 9232 rtx base = gen_reg_rtx (Pmode); 9233 rtx target = gen_reg_rtx (Pmode); 9234 9235 emit_move_insn (index, operands[0]); 9236 emit_insn (gen_subsi3 (index, index, operands[1])); 9237 emit_cmp_and_jump_insns (index, operands[2], GTU, NULL_RTX, SImode, 1, 9238 operands[4]); 9239 9240 if (Pmode != SImode) 9241 index = convert_to_mode (Pmode, index, 1); 9242 if (GET_CODE (index) != REG) 9243 index = copy_to_mode_reg (Pmode, index); 9244 9245 if (TARGET_64BIT) 9246 emit_insn (gen_ashldi3 (index, index, GEN_INT (3))); 9247 else 9248 emit_insn (gen_ashlsi3 (index, index, const2_rtx)); 9249 9250 emit_move_insn (base, gen_rtx_LABEL_REF (Pmode, operands[3])); 9251 9252 index = gen_const_mem (Pmode, gen_rtx_PLUS (Pmode, base, index)); 9253 emit_move_insn (target, index); 9254 9255 if (flag_pic) 9256 target = gen_rtx_PLUS (Pmode, base, target); 9257 emit_jump_insn (gen_casesi_jump (target, operands[3])); 9258 9259 DONE; 9260}) 9261 9262 9263;; 9264;;- Jump to subroutine. 9265;; 9266;; 9267 9268; 9269; untyped call instruction pattern(s). 9270; 9271 9272;; Call subroutine returning any type. 9273(define_expand "untyped_call" 9274 [(parallel [(call (match_operand 0 "" "") 9275 (const_int 0)) 9276 (match_operand 1 "" "") 9277 (match_operand 2 "" "")])] 9278 "" 9279{ 9280 int i; 9281 9282 emit_call_insn (gen_call (operands[0], const0_rtx, const0_rtx)); 9283 9284 for (i = 0; i < XVECLEN (operands[2], 0); i++) 9285 { 9286 rtx set = XVECEXP (operands[2], 0, i); 9287 emit_move_insn (SET_DEST (set), SET_SRC (set)); 9288 } 9289 9290 /* The optimizer does not know that the call sets the function value 9291 registers we stored in the result block. We avoid problems by 9292 claiming that all hard registers are used and clobbered at this 9293 point. */ 9294 emit_insn (gen_blockage ()); 9295 9296 DONE; 9297}) 9298 9299;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 9300;; all of memory. This blocks insns from being moved across this point. 9301 9302(define_insn "blockage" 9303 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 9304 "" 9305 "" 9306 [(set_attr "type" "none") 9307 (set_attr "length" "0")]) 9308 9309; 9310; sibcall patterns 9311; 9312 9313(define_expand "sibcall" 9314 [(call (match_operand 0 "" "") 9315 (match_operand 1 "" ""))] 9316 "" 9317{ 9318 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, NULL_RTX); 9319 DONE; 9320}) 9321 9322(define_insn "*sibcall_br" 9323 [(call (mem:QI (reg SIBCALL_REGNUM)) 9324 (match_operand 0 "const_int_operand" "n"))] 9325 "SIBLING_CALL_P (insn) 9326 && GET_MODE (XEXP (XEXP (PATTERN (insn), 0), 0)) == Pmode" 9327 "br\t%%r1" 9328 [(set_attr "op_type" "RR") 9329 (set_attr "type" "branch") 9330 (set_attr "atype" "agen")]) 9331 9332(define_insn "*sibcall_brc" 9333 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 9334 (match_operand 1 "const_int_operand" "n"))] 9335 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" 9336 "j\t%0" 9337 [(set_attr "op_type" "RI") 9338 (set_attr "type" "branch")]) 9339 9340(define_insn "*sibcall_brcl" 9341 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 9342 (match_operand 1 "const_int_operand" "n"))] 9343 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" 9344 "jg\t%0" 9345 [(set_attr "op_type" "RIL") 9346 (set_attr "type" "branch")]) 9347 9348; 9349; sibcall_value patterns 9350; 9351 9352(define_expand "sibcall_value" 9353 [(set (match_operand 0 "" "") 9354 (call (match_operand 1 "" "") 9355 (match_operand 2 "" "")))] 9356 "" 9357{ 9358 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], NULL_RTX); 9359 DONE; 9360}) 9361 9362(define_insn "*sibcall_value_br" 9363 [(set (match_operand 0 "" "") 9364 (call (mem:QI (reg SIBCALL_REGNUM)) 9365 (match_operand 1 "const_int_operand" "n")))] 9366 "SIBLING_CALL_P (insn) 9367 && GET_MODE (XEXP (XEXP (XEXP (PATTERN (insn), 1), 0), 0)) == Pmode" 9368 "br\t%%r1" 9369 [(set_attr "op_type" "RR") 9370 (set_attr "type" "branch") 9371 (set_attr "atype" "agen")]) 9372 9373(define_insn "*sibcall_value_brc" 9374 [(set (match_operand 0 "" "") 9375 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 9376 (match_operand 2 "const_int_operand" "n")))] 9377 "SIBLING_CALL_P (insn) && TARGET_SMALL_EXEC" 9378 "j\t%1" 9379 [(set_attr "op_type" "RI") 9380 (set_attr "type" "branch")]) 9381 9382(define_insn "*sibcall_value_brcl" 9383 [(set (match_operand 0 "" "") 9384 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 9385 (match_operand 2 "const_int_operand" "n")))] 9386 "SIBLING_CALL_P (insn) && TARGET_CPU_ZARCH" 9387 "jg\t%1" 9388 [(set_attr "op_type" "RIL") 9389 (set_attr "type" "branch")]) 9390 9391 9392; 9393; call instruction pattern(s). 9394; 9395 9396(define_expand "call" 9397 [(call (match_operand 0 "" "") 9398 (match_operand 1 "" "")) 9399 (use (match_operand 2 "" ""))] 9400 "" 9401{ 9402 s390_emit_call (XEXP (operands[0], 0), NULL_RTX, NULL_RTX, 9403 gen_rtx_REG (Pmode, RETURN_REGNUM)); 9404 DONE; 9405}) 9406 9407(define_insn "*bras" 9408 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 9409 (match_operand 1 "const_int_operand" "n")) 9410 (clobber (match_operand 2 "register_operand" "=r"))] 9411 "!SIBLING_CALL_P (insn) 9412 && TARGET_SMALL_EXEC 9413 && GET_MODE (operands[2]) == Pmode" 9414 "bras\t%2,%0" 9415 [(set_attr "op_type" "RI") 9416 (set_attr "type" "jsr") 9417 (set_attr "z196prop" "z196_cracked")]) 9418 9419(define_insn "*brasl" 9420 [(call (mem:QI (match_operand 0 "bras_sym_operand" "X")) 9421 (match_operand 1 "const_int_operand" "n")) 9422 (clobber (match_operand 2 "register_operand" "=r"))] 9423 "!SIBLING_CALL_P (insn) 9424 && TARGET_CPU_ZARCH 9425 && GET_MODE (operands[2]) == Pmode" 9426 "brasl\t%2,%0" 9427 [(set_attr "op_type" "RIL") 9428 (set_attr "type" "jsr") 9429 (set_attr "z196prop" "z196_cracked")]) 9430 9431(define_insn "*basr" 9432 [(call (mem:QI (match_operand 0 "address_operand" "ZQZR")) 9433 (match_operand 1 "const_int_operand" "n")) 9434 (clobber (match_operand 2 "register_operand" "=r"))] 9435 "!SIBLING_CALL_P (insn) && GET_MODE (operands[2]) == Pmode" 9436{ 9437 if (get_attr_op_type (insn) == OP_TYPE_RR) 9438 return "basr\t%2,%0"; 9439 else 9440 return "bas\t%2,%a0"; 9441} 9442 [(set (attr "op_type") 9443 (if_then_else (match_operand 0 "register_operand" "") 9444 (const_string "RR") (const_string "RX"))) 9445 (set_attr "type" "jsr") 9446 (set_attr "atype" "agen") 9447 (set_attr "z196prop" "z196_cracked")]) 9448 9449; 9450; call_value instruction pattern(s). 9451; 9452 9453(define_expand "call_value" 9454 [(set (match_operand 0 "" "") 9455 (call (match_operand 1 "" "") 9456 (match_operand 2 "" ""))) 9457 (use (match_operand 3 "" ""))] 9458 "" 9459{ 9460 s390_emit_call (XEXP (operands[1], 0), NULL_RTX, operands[0], 9461 gen_rtx_REG (Pmode, RETURN_REGNUM)); 9462 DONE; 9463}) 9464 9465(define_insn "*bras_r" 9466 [(set (match_operand 0 "" "") 9467 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 9468 (match_operand:SI 2 "const_int_operand" "n"))) 9469 (clobber (match_operand 3 "register_operand" "=r"))] 9470 "!SIBLING_CALL_P (insn) 9471 && TARGET_SMALL_EXEC 9472 && GET_MODE (operands[3]) == Pmode" 9473 "bras\t%3,%1" 9474 [(set_attr "op_type" "RI") 9475 (set_attr "type" "jsr") 9476 (set_attr "z196prop" "z196_cracked")]) 9477 9478(define_insn "*brasl_r" 9479 [(set (match_operand 0 "" "") 9480 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 9481 (match_operand 2 "const_int_operand" "n"))) 9482 (clobber (match_operand 3 "register_operand" "=r"))] 9483 "!SIBLING_CALL_P (insn) 9484 && TARGET_CPU_ZARCH 9485 && GET_MODE (operands[3]) == Pmode" 9486 "brasl\t%3,%1" 9487 [(set_attr "op_type" "RIL") 9488 (set_attr "type" "jsr") 9489 (set_attr "z196prop" "z196_cracked")]) 9490 9491(define_insn "*basr_r" 9492 [(set (match_operand 0 "" "") 9493 (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) 9494 (match_operand 2 "const_int_operand" "n"))) 9495 (clobber (match_operand 3 "register_operand" "=r"))] 9496 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" 9497{ 9498 if (get_attr_op_type (insn) == OP_TYPE_RR) 9499 return "basr\t%3,%1"; 9500 else 9501 return "bas\t%3,%a1"; 9502} 9503 [(set (attr "op_type") 9504 (if_then_else (match_operand 1 "register_operand" "") 9505 (const_string "RR") (const_string "RX"))) 9506 (set_attr "type" "jsr") 9507 (set_attr "atype" "agen") 9508 (set_attr "z196prop" "z196_cracked")]) 9509 9510;; 9511;;- Thread-local storage support. 9512;; 9513 9514(define_expand "get_thread_pointer<mode>" 9515 [(set (match_operand:P 0 "nonimmediate_operand" "") (reg:P TP_REGNUM))] 9516 "" 9517 "") 9518 9519(define_expand "set_thread_pointer<mode>" 9520 [(set (reg:P TP_REGNUM) (match_operand:P 0 "nonimmediate_operand" "")) 9521 (set (reg:P TP_REGNUM) (unspec_volatile:P [(reg:P TP_REGNUM)] UNSPECV_SET_TP))] 9522 "" 9523 "") 9524 9525(define_insn "*set_tp" 9526 [(set (reg TP_REGNUM) (unspec_volatile [(reg TP_REGNUM)] UNSPECV_SET_TP))] 9527 "" 9528 "" 9529 [(set_attr "type" "none") 9530 (set_attr "length" "0")]) 9531 9532(define_insn "*tls_load_64" 9533 [(set (match_operand:DI 0 "register_operand" "=d") 9534 (unspec:DI [(match_operand:DI 1 "memory_operand" "RT") 9535 (match_operand:DI 2 "" "")] 9536 UNSPEC_TLS_LOAD))] 9537 "TARGET_64BIT" 9538 "lg\t%0,%1%J2" 9539 [(set_attr "op_type" "RXE") 9540 (set_attr "z10prop" "z10_fwd_A3")]) 9541 9542(define_insn "*tls_load_31" 9543 [(set (match_operand:SI 0 "register_operand" "=d,d") 9544 (unspec:SI [(match_operand:SI 1 "memory_operand" "R,T") 9545 (match_operand:SI 2 "" "")] 9546 UNSPEC_TLS_LOAD))] 9547 "!TARGET_64BIT" 9548 "@ 9549 l\t%0,%1%J2 9550 ly\t%0,%1%J2" 9551 [(set_attr "op_type" "RX,RXY") 9552 (set_attr "type" "load") 9553 (set_attr "z10prop" "z10_fwd_A3,z10_fwd_A3")]) 9554 9555(define_insn "*bras_tls" 9556 [(set (match_operand 0 "" "") 9557 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 9558 (match_operand 2 "const_int_operand" "n"))) 9559 (clobber (match_operand 3 "register_operand" "=r")) 9560 (use (match_operand 4 "" ""))] 9561 "!SIBLING_CALL_P (insn) 9562 && TARGET_SMALL_EXEC 9563 && GET_MODE (operands[3]) == Pmode" 9564 "bras\t%3,%1%J4" 9565 [(set_attr "op_type" "RI") 9566 (set_attr "type" "jsr") 9567 (set_attr "z196prop" "z196_cracked")]) 9568 9569(define_insn "*brasl_tls" 9570 [(set (match_operand 0 "" "") 9571 (call (mem:QI (match_operand 1 "bras_sym_operand" "X")) 9572 (match_operand 2 "const_int_operand" "n"))) 9573 (clobber (match_operand 3 "register_operand" "=r")) 9574 (use (match_operand 4 "" ""))] 9575 "!SIBLING_CALL_P (insn) 9576 && TARGET_CPU_ZARCH 9577 && GET_MODE (operands[3]) == Pmode" 9578 "brasl\t%3,%1%J4" 9579 [(set_attr "op_type" "RIL") 9580 (set_attr "type" "jsr") 9581 (set_attr "z196prop" "z196_cracked")]) 9582 9583(define_insn "*basr_tls" 9584 [(set (match_operand 0 "" "") 9585 (call (mem:QI (match_operand 1 "address_operand" "ZQZR")) 9586 (match_operand 2 "const_int_operand" "n"))) 9587 (clobber (match_operand 3 "register_operand" "=r")) 9588 (use (match_operand 4 "" ""))] 9589 "!SIBLING_CALL_P (insn) && GET_MODE (operands[3]) == Pmode" 9590{ 9591 if (get_attr_op_type (insn) == OP_TYPE_RR) 9592 return "basr\t%3,%1%J4"; 9593 else 9594 return "bas\t%3,%a1%J4"; 9595} 9596 [(set (attr "op_type") 9597 (if_then_else (match_operand 1 "register_operand" "") 9598 (const_string "RR") (const_string "RX"))) 9599 (set_attr "type" "jsr") 9600 (set_attr "atype" "agen") 9601 (set_attr "z196prop" "z196_cracked")]) 9602 9603;; 9604;;- Atomic operations 9605;; 9606 9607; 9608; memory barrier patterns. 9609; 9610 9611(define_expand "mem_signal_fence" 9612 [(match_operand:SI 0 "const_int_operand")] ;; model 9613 "" 9614{ 9615 /* The s390 memory model is strong enough not to require any 9616 barrier in order to synchronize a thread with itself. */ 9617 DONE; 9618}) 9619 9620(define_expand "mem_thread_fence" 9621 [(match_operand:SI 0 "const_int_operand")] ;; model 9622 "" 9623{ 9624 /* Unless this is a SEQ_CST fence, the s390 memory model is strong 9625 enough not to require barriers of any kind. */ 9626 if (is_mm_seq_cst (memmodel_from_int (INTVAL (operands[0])))) 9627 { 9628 rtx mem = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode)); 9629 MEM_VOLATILE_P (mem) = 1; 9630 emit_insn (gen_mem_thread_fence_1 (mem)); 9631 } 9632 DONE; 9633}) 9634 9635; Although bcr is superscalar on Z10, this variant will never 9636; become part of an execution group. 9637; With z196 we can make use of the fast-BCR-serialization facility. 9638; This allows for a slightly faster sync which is sufficient for our 9639; purposes. 9640(define_insn "mem_thread_fence_1" 9641 [(set (match_operand:BLK 0 "" "") 9642 (unspec:BLK [(match_dup 0)] UNSPEC_MB))] 9643 "" 9644{ 9645 if (TARGET_Z196) 9646 return "bcr\t14,0"; 9647 else 9648 return "bcr\t15,0"; 9649} 9650 [(set_attr "op_type" "RR") 9651 (set_attr "mnemonic" "bcr_flush") 9652 (set_attr "z196prop" "z196_alone")]) 9653 9654; 9655; atomic load/store operations 9656; 9657 9658; Atomic loads need not examine the memory model at all. 9659(define_expand "atomic_load<mode>" 9660 [(match_operand:DINT 0 "register_operand") ;; output 9661 (match_operand:DINT 1 "memory_operand") ;; memory 9662 (match_operand:SI 2 "const_int_operand")] ;; model 9663 "" 9664{ 9665 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) 9666 FAIL; 9667 9668 if (<MODE>mode == TImode) 9669 emit_insn (gen_atomic_loadti_1 (operands[0], operands[1])); 9670 else if (<MODE>mode == DImode && !TARGET_ZARCH) 9671 emit_insn (gen_atomic_loaddi_1 (operands[0], operands[1])); 9672 else 9673 emit_move_insn (operands[0], operands[1]); 9674 DONE; 9675}) 9676 9677; Different from movdi_31 in that we want no splitters. 9678(define_insn "atomic_loaddi_1" 9679 [(set (match_operand:DI 0 "register_operand" "=d,d,!*f,!*f") 9680 (unspec:DI [(match_operand:DI 1 "memory_operand" "Q,S,R,T")] 9681 UNSPEC_MOVA))] 9682 "!TARGET_ZARCH" 9683 "@ 9684 lm\t%0,%M0,%S1 9685 lmy\t%0,%M0,%S1 9686 ld\t%0,%1 9687 ldy\t%0,%1" 9688 [(set_attr "op_type" "RS,RSY,RS,RSY") 9689 (set_attr "type" "lm,lm,floaddf,floaddf")]) 9690 9691(define_insn "atomic_loadti_1" 9692 [(set (match_operand:TI 0 "register_operand" "=r") 9693 (unspec:TI [(match_operand:TI 1 "memory_operand" "RT")] 9694 UNSPEC_MOVA))] 9695 "TARGET_ZARCH" 9696 "lpq\t%0,%1" 9697 [(set_attr "op_type" "RXY") 9698 (set_attr "type" "other")]) 9699 9700; Atomic stores must(?) enforce sequential consistency. 9701(define_expand "atomic_store<mode>" 9702 [(match_operand:DINT 0 "memory_operand") ;; memory 9703 (match_operand:DINT 1 "register_operand") ;; input 9704 (match_operand:SI 2 "const_int_operand")] ;; model 9705 "" 9706{ 9707 enum memmodel model = memmodel_from_int (INTVAL (operands[2])); 9708 9709 if (MEM_ALIGN (operands[0]) < GET_MODE_BITSIZE (GET_MODE (operands[0]))) 9710 FAIL; 9711 9712 if (<MODE>mode == TImode) 9713 emit_insn (gen_atomic_storeti_1 (operands[0], operands[1])); 9714 else if (<MODE>mode == DImode && !TARGET_ZARCH) 9715 emit_insn (gen_atomic_storedi_1 (operands[0], operands[1])); 9716 else 9717 emit_move_insn (operands[0], operands[1]); 9718 if (is_mm_seq_cst (model)) 9719 emit_insn (gen_mem_thread_fence (operands[2])); 9720 DONE; 9721}) 9722 9723; Different from movdi_31 in that we want no splitters. 9724(define_insn "atomic_storedi_1" 9725 [(set (match_operand:DI 0 "memory_operand" "=Q,S,R,T") 9726 (unspec:DI [(match_operand:DI 1 "register_operand" "d,d,!*f,!*f")] 9727 UNSPEC_MOVA))] 9728 "!TARGET_ZARCH" 9729 "@ 9730 stm\t%1,%N1,%S0 9731 stmy\t%1,%N1,%S0 9732 std %1,%0 9733 stdy %1,%0" 9734 [(set_attr "op_type" "RS,RSY,RS,RSY") 9735 (set_attr "type" "stm,stm,fstoredf,fstoredf")]) 9736 9737(define_insn "atomic_storeti_1" 9738 [(set (match_operand:TI 0 "memory_operand" "=RT") 9739 (unspec:TI [(match_operand:TI 1 "register_operand" "r")] 9740 UNSPEC_MOVA))] 9741 "TARGET_ZARCH" 9742 "stpq\t%1,%0" 9743 [(set_attr "op_type" "RXY") 9744 (set_attr "type" "other")]) 9745 9746; 9747; compare and swap patterns. 9748; 9749 9750(define_expand "atomic_compare_and_swap<mode>" 9751 [(match_operand:SI 0 "register_operand") ;; bool success output 9752 (match_operand:DGPR 1 "nonimmediate_operand");; oldval output 9753 (match_operand:DGPR 2 "memory_operand") ;; memory 9754 (match_operand:DGPR 3 "register_operand") ;; expected intput 9755 (match_operand:DGPR 4 "register_operand") ;; newval intput 9756 (match_operand:SI 5 "const_int_operand") ;; is_weak 9757 (match_operand:SI 6 "const_int_operand") ;; success model 9758 (match_operand:SI 7 "const_int_operand")] ;; failure model 9759 "" 9760{ 9761 rtx cc, cmp, output = operands[1]; 9762 9763 if (!register_operand (output, <MODE>mode)) 9764 output = gen_reg_rtx (<MODE>mode); 9765 9766 if (MEM_ALIGN (operands[2]) < GET_MODE_BITSIZE (GET_MODE (operands[2]))) 9767 FAIL; 9768 9769 emit_insn (gen_atomic_compare_and_swap<mode>_internal 9770 (output, operands[2], operands[3], operands[4])); 9771 9772 /* We deliberately accept non-register operands in the predicate 9773 to ensure the write back to the output operand happens *before* 9774 the store-flags code below. This makes it easier for combine 9775 to merge the store-flags code with a potential test-and-branch 9776 pattern following (immediately!) afterwards. */ 9777 if (output != operands[1]) 9778 emit_move_insn (operands[1], output); 9779 9780 cc = gen_rtx_REG (CCZ1mode, CC_REGNUM); 9781 cmp = gen_rtx_EQ (SImode, cc, const0_rtx); 9782 emit_insn (gen_cstorecc4 (operands[0], cmp, cc, const0_rtx)); 9783 DONE; 9784}) 9785 9786(define_expand "atomic_compare_and_swap<mode>" 9787 [(match_operand:SI 0 "register_operand") ;; bool success output 9788 (match_operand:HQI 1 "nonimmediate_operand") ;; oldval output 9789 (match_operand:HQI 2 "memory_operand") ;; memory 9790 (match_operand:HQI 3 "general_operand") ;; expected intput 9791 (match_operand:HQI 4 "general_operand") ;; newval intput 9792 (match_operand:SI 5 "const_int_operand") ;; is_weak 9793 (match_operand:SI 6 "const_int_operand") ;; success model 9794 (match_operand:SI 7 "const_int_operand")] ;; failure model 9795 "" 9796{ 9797 s390_expand_cs_hqi (<MODE>mode, operands[0], operands[1], operands[2], 9798 operands[3], operands[4], INTVAL (operands[5])); 9799 DONE; 9800}) 9801 9802(define_expand "atomic_compare_and_swap<mode>_internal" 9803 [(parallel 9804 [(set (match_operand:DGPR 0 "register_operand") 9805 (match_operand:DGPR 1 "memory_operand")) 9806 (set (match_dup 1) 9807 (unspec_volatile:DGPR 9808 [(match_dup 1) 9809 (match_operand:DGPR 2 "register_operand") 9810 (match_operand:DGPR 3 "register_operand")] 9811 UNSPECV_CAS)) 9812 (set (reg:CCZ1 CC_REGNUM) 9813 (compare:CCZ1 (match_dup 1) (match_dup 2)))])] 9814 "") 9815 9816; cdsg, csg 9817(define_insn "*atomic_compare_and_swap<mode>_1" 9818 [(set (match_operand:TDI 0 "register_operand" "=r") 9819 (match_operand:TDI 1 "memory_operand" "+QS")) 9820 (set (match_dup 1) 9821 (unspec_volatile:TDI 9822 [(match_dup 1) 9823 (match_operand:TDI 2 "register_operand" "0") 9824 (match_operand:TDI 3 "register_operand" "r")] 9825 UNSPECV_CAS)) 9826 (set (reg:CCZ1 CC_REGNUM) 9827 (compare:CCZ1 (match_dup 1) (match_dup 2)))] 9828 "TARGET_ZARCH" 9829 "c<td>sg\t%0,%3,%S1" 9830 [(set_attr "op_type" "RSY") 9831 (set_attr "type" "sem")]) 9832 9833; cds, cdsy 9834(define_insn "*atomic_compare_and_swapdi_2" 9835 [(set (match_operand:DI 0 "register_operand" "=r,r") 9836 (match_operand:DI 1 "memory_operand" "+Q,S")) 9837 (set (match_dup 1) 9838 (unspec_volatile:DI 9839 [(match_dup 1) 9840 (match_operand:DI 2 "register_operand" "0,0") 9841 (match_operand:DI 3 "register_operand" "r,r")] 9842 UNSPECV_CAS)) 9843 (set (reg:CCZ1 CC_REGNUM) 9844 (compare:CCZ1 (match_dup 1) (match_dup 2)))] 9845 "!TARGET_ZARCH" 9846 "@ 9847 cds\t%0,%3,%S1 9848 cdsy\t%0,%3,%S1" 9849 [(set_attr "op_type" "RS,RSY") 9850 (set_attr "type" "sem")]) 9851 9852; cs, csy 9853(define_insn "*atomic_compare_and_swapsi_3" 9854 [(set (match_operand:SI 0 "register_operand" "=r,r") 9855 (match_operand:SI 1 "memory_operand" "+Q,S")) 9856 (set (match_dup 1) 9857 (unspec_volatile:SI 9858 [(match_dup 1) 9859 (match_operand:SI 2 "register_operand" "0,0") 9860 (match_operand:SI 3 "register_operand" "r,r")] 9861 UNSPECV_CAS)) 9862 (set (reg:CCZ1 CC_REGNUM) 9863 (compare:CCZ1 (match_dup 1) (match_dup 2)))] 9864 "" 9865 "@ 9866 cs\t%0,%3,%S1 9867 csy\t%0,%3,%S1" 9868 [(set_attr "op_type" "RS,RSY") 9869 (set_attr "type" "sem")]) 9870 9871; 9872; Other atomic instruction patterns. 9873; 9874 9875; z196 load and add, xor, or and and instructions 9876 9877(define_expand "atomic_fetch_<atomic><mode>" 9878 [(match_operand:GPR 0 "register_operand") ;; val out 9879 (ATOMIC_Z196:GPR 9880 (match_operand:GPR 1 "memory_operand") ;; memory 9881 (match_operand:GPR 2 "register_operand")) ;; val in 9882 (match_operand:SI 3 "const_int_operand")] ;; model 9883 "TARGET_Z196" 9884{ 9885 if (MEM_ALIGN (operands[1]) < GET_MODE_BITSIZE (GET_MODE (operands[1]))) 9886 FAIL; 9887 9888 emit_insn (gen_atomic_fetch_<atomic><mode>_iaf 9889 (operands[0], operands[1], operands[2])); 9890 DONE; 9891}) 9892 9893; lan, lang, lao, laog, lax, laxg, laa, laag 9894(define_insn "atomic_fetch_<atomic><mode>_iaf" 9895 [(set (match_operand:GPR 0 "register_operand" "=d") 9896 (match_operand:GPR 1 "memory_operand" "+QS")) 9897 (set (match_dup 1) 9898 (unspec_volatile:GPR 9899 [(ATOMIC_Z196:GPR (match_dup 1) 9900 (match_operand:GPR 2 "general_operand" "d"))] 9901 UNSPECV_ATOMIC_OP)) 9902 (clobber (reg:CC CC_REGNUM))] 9903 "TARGET_Z196" 9904 "la<noxa><g>\t%0,%2,%1" 9905 [(set_attr "op_type" "RSY") 9906 (set_attr "type" "sem")]) 9907 9908;; For SImode and larger, the optabs.c code will do just fine in 9909;; expanding a compare-and-swap loop. For QI/HImode, we can do 9910;; better by expanding our own loop. 9911 9912(define_expand "atomic_<atomic><mode>" 9913 [(ATOMIC:HQI 9914 (match_operand:HQI 0 "memory_operand") ;; memory 9915 (match_operand:HQI 1 "general_operand")) ;; val in 9916 (match_operand:SI 2 "const_int_operand")] ;; model 9917 "" 9918{ 9919 s390_expand_atomic (<MODE>mode, <CODE>, NULL_RTX, operands[0], 9920 operands[1], false); 9921 DONE; 9922}) 9923 9924(define_expand "atomic_fetch_<atomic><mode>" 9925 [(match_operand:HQI 0 "register_operand") ;; val out 9926 (ATOMIC:HQI 9927 (match_operand:HQI 1 "memory_operand") ;; memory 9928 (match_operand:HQI 2 "general_operand")) ;; val in 9929 (match_operand:SI 3 "const_int_operand")] ;; model 9930 "" 9931{ 9932 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], 9933 operands[2], false); 9934 DONE; 9935}) 9936 9937(define_expand "atomic_<atomic>_fetch<mode>" 9938 [(match_operand:HQI 0 "register_operand") ;; val out 9939 (ATOMIC:HQI 9940 (match_operand:HQI 1 "memory_operand") ;; memory 9941 (match_operand:HQI 2 "general_operand")) ;; val in 9942 (match_operand:SI 3 "const_int_operand")] ;; model 9943 "" 9944{ 9945 s390_expand_atomic (<MODE>mode, <CODE>, operands[0], operands[1], 9946 operands[2], true); 9947 DONE; 9948}) 9949 9950(define_expand "atomic_exchange<mode>" 9951 [(match_operand:HQI 0 "register_operand") ;; val out 9952 (match_operand:HQI 1 "memory_operand") ;; memory 9953 (match_operand:HQI 2 "general_operand") ;; val in 9954 (match_operand:SI 3 "const_int_operand")] ;; model 9955 "" 9956{ 9957 s390_expand_atomic (<MODE>mode, SET, operands[0], operands[1], 9958 operands[2], false); 9959 DONE; 9960}) 9961 9962;; 9963;;- Miscellaneous instructions. 9964;; 9965 9966; 9967; allocate stack instruction pattern(s). 9968; 9969 9970(define_expand "allocate_stack" 9971 [(match_operand 0 "general_operand" "") 9972 (match_operand 1 "general_operand" "")] 9973 "TARGET_BACKCHAIN" 9974{ 9975 rtx temp = gen_reg_rtx (Pmode); 9976 9977 emit_move_insn (temp, s390_back_chain_rtx ()); 9978 anti_adjust_stack (operands[1]); 9979 emit_move_insn (s390_back_chain_rtx (), temp); 9980 9981 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 9982 DONE; 9983}) 9984 9985 9986; 9987; setjmp instruction pattern. 9988; 9989 9990(define_expand "builtin_setjmp_receiver" 9991 [(match_operand 0 "" "")] 9992 "flag_pic" 9993{ 9994 emit_insn (s390_load_got ()); 9995 emit_use (pic_offset_table_rtx); 9996 DONE; 9997}) 9998 9999;; These patterns say how to save and restore the stack pointer. We need not 10000;; save the stack pointer at function level since we are careful to 10001;; preserve the backchain. At block level, we have to restore the backchain 10002;; when we restore the stack pointer. 10003;; 10004;; For nonlocal gotos, we must save both the stack pointer and its 10005;; backchain and restore both. Note that in the nonlocal case, the 10006;; save area is a memory location. 10007 10008(define_expand "save_stack_function" 10009 [(match_operand 0 "general_operand" "") 10010 (match_operand 1 "general_operand" "")] 10011 "" 10012 "DONE;") 10013 10014(define_expand "restore_stack_function" 10015 [(match_operand 0 "general_operand" "") 10016 (match_operand 1 "general_operand" "")] 10017 "" 10018 "DONE;") 10019 10020(define_expand "restore_stack_block" 10021 [(match_operand 0 "register_operand" "") 10022 (match_operand 1 "register_operand" "")] 10023 "TARGET_BACKCHAIN" 10024{ 10025 rtx temp = gen_reg_rtx (Pmode); 10026 10027 emit_move_insn (temp, s390_back_chain_rtx ()); 10028 emit_move_insn (operands[0], operands[1]); 10029 emit_move_insn (s390_back_chain_rtx (), temp); 10030 10031 DONE; 10032}) 10033 10034(define_expand "save_stack_nonlocal" 10035 [(match_operand 0 "memory_operand" "") 10036 (match_operand 1 "register_operand" "")] 10037 "" 10038{ 10039 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); 10040 10041 /* Copy the backchain to the first word, sp to the second and the 10042 literal pool base to the third. */ 10043 10044 rtx save_bc = adjust_address (operands[0], Pmode, 0); 10045 rtx save_sp = adjust_address (operands[0], Pmode, GET_MODE_SIZE (Pmode)); 10046 rtx save_bp = adjust_address (operands[0], Pmode, 2 * GET_MODE_SIZE (Pmode)); 10047 10048 if (TARGET_BACKCHAIN) 10049 emit_move_insn (save_bc, force_reg (Pmode, s390_back_chain_rtx ())); 10050 10051 emit_move_insn (save_sp, operands[1]); 10052 emit_move_insn (save_bp, base); 10053 10054 DONE; 10055}) 10056 10057(define_expand "restore_stack_nonlocal" 10058 [(match_operand 0 "register_operand" "") 10059 (match_operand 1 "memory_operand" "")] 10060 "" 10061{ 10062 rtx base = gen_rtx_REG (Pmode, BASE_REGNUM); 10063 rtx temp = NULL_RTX; 10064 10065 /* Restore the backchain from the first word, sp from the second and the 10066 literal pool base from the third. */ 10067 10068 rtx save_bc = adjust_address (operands[1], Pmode, 0); 10069 rtx save_sp = adjust_address (operands[1], Pmode, GET_MODE_SIZE (Pmode)); 10070 rtx save_bp = adjust_address (operands[1], Pmode, 2 * GET_MODE_SIZE (Pmode)); 10071 10072 if (TARGET_BACKCHAIN) 10073 temp = force_reg (Pmode, save_bc); 10074 10075 emit_move_insn (base, save_bp); 10076 emit_move_insn (operands[0], save_sp); 10077 10078 if (temp) 10079 emit_move_insn (s390_back_chain_rtx (), temp); 10080 10081 emit_use (base); 10082 DONE; 10083}) 10084 10085(define_expand "exception_receiver" 10086 [(const_int 0)] 10087 "" 10088{ 10089 s390_set_has_landing_pad_p (true); 10090 DONE; 10091}) 10092 10093; 10094; nop instruction pattern(s). 10095; 10096 10097(define_insn "nop" 10098 [(const_int 0)] 10099 "" 10100 "lr\t0,0" 10101 [(set_attr "op_type" "RR") 10102 (set_attr "z10prop" "z10_fr_E1")]) 10103 10104(define_insn "nop1" 10105 [(const_int 1)] 10106 "" 10107 "lr\t1,1" 10108 [(set_attr "op_type" "RR")]) 10109 10110;;- Undeletable nops (used for hotpatching) 10111 10112(define_insn "nop_2_byte" 10113 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_2_BYTE)] 10114 "" 10115 "nopr\t%%r7" 10116 [(set_attr "op_type" "RR")]) 10117 10118(define_insn "nop_4_byte" 10119 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_4_BYTE)] 10120 "" 10121 "nop\t0" 10122 [(set_attr "op_type" "RX")]) 10123 10124(define_insn "nop_6_byte" 10125 [(unspec_volatile [(const_int 0)] UNSPECV_NOP_6_BYTE)] 10126 "TARGET_CPU_ZARCH" 10127 "brcl\t0, 0" 10128 [(set_attr "op_type" "RIL")]) 10129 10130 10131; 10132; Special literal pool access instruction pattern(s). 10133; 10134 10135(define_insn "*pool_entry" 10136 [(unspec_volatile [(match_operand 0 "consttable_operand" "X")] 10137 UNSPECV_POOL_ENTRY)] 10138 "" 10139{ 10140 machine_mode mode = GET_MODE (PATTERN (insn)); 10141 unsigned int align = GET_MODE_BITSIZE (mode); 10142 s390_output_pool_entry (operands[0], mode, align); 10143 return ""; 10144} 10145 [(set (attr "length") 10146 (symbol_ref "GET_MODE_SIZE (GET_MODE (PATTERN (insn)))"))]) 10147 10148(define_insn "pool_align" 10149 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] 10150 UNSPECV_POOL_ALIGN)] 10151 "" 10152 ".align\t%0" 10153 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) 10154 10155(define_insn "pool_section_start" 10156 [(unspec_volatile [(const_int 1)] UNSPECV_POOL_SECTION)] 10157 "" 10158 ".section\t.rodata" 10159 [(set_attr "length" "0")]) 10160 10161(define_insn "pool_section_end" 10162 [(unspec_volatile [(const_int 0)] UNSPECV_POOL_SECTION)] 10163 "" 10164 ".previous" 10165 [(set_attr "length" "0")]) 10166 10167(define_insn "main_base_31_small" 10168 [(set (match_operand 0 "register_operand" "=a") 10169 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] 10170 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 10171 "basr\t%0,0" 10172 [(set_attr "op_type" "RR") 10173 (set_attr "type" "la") 10174 (set_attr "z196prop" "z196_cracked")]) 10175 10176(define_insn "main_base_31_large" 10177 [(set (match_operand 0 "register_operand" "=a") 10178 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE)) 10179 (set (pc) (label_ref (match_operand 2 "" "")))] 10180 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 10181 "bras\t%0,%2" 10182 [(set_attr "op_type" "RI") 10183 (set_attr "z196prop" "z196_cracked")]) 10184 10185(define_insn "main_base_64" 10186 [(set (match_operand 0 "register_operand" "=a") 10187 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_MAIN_BASE))] 10188 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 10189 "larl\t%0,%1" 10190 [(set_attr "op_type" "RIL") 10191 (set_attr "type" "larl") 10192 (set_attr "z10prop" "z10_fwd_A1")]) 10193 10194(define_insn "main_pool" 10195 [(set (match_operand 0 "register_operand" "=a") 10196 (unspec_volatile [(const_int 0)] UNSPECV_MAIN_POOL))] 10197 "GET_MODE (operands[0]) == Pmode" 10198{ 10199 gcc_unreachable (); 10200} 10201 [(set (attr "type") 10202 (if_then_else (match_test "TARGET_CPU_ZARCH") 10203 (const_string "larl") (const_string "la")))]) 10204 10205(define_insn "reload_base_31" 10206 [(set (match_operand 0 "register_operand" "=a") 10207 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] 10208 "!TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 10209 "basr\t%0,0\;la\t%0,%1-.(%0)" 10210 [(set_attr "length" "6") 10211 (set_attr "type" "la") 10212 (set_attr "z196prop" "z196_cracked")]) 10213 10214(define_insn "reload_base_64" 10215 [(set (match_operand 0 "register_operand" "=a") 10216 (unspec [(label_ref (match_operand 1 "" ""))] UNSPEC_RELOAD_BASE))] 10217 "TARGET_CPU_ZARCH && GET_MODE (operands[0]) == Pmode" 10218 "larl\t%0,%1" 10219 [(set_attr "op_type" "RIL") 10220 (set_attr "type" "larl") 10221 (set_attr "z10prop" "z10_fwd_A1")]) 10222 10223(define_insn "pool" 10224 [(unspec_volatile [(match_operand 0 "const_int_operand" "n")] UNSPECV_POOL)] 10225 "" 10226{ 10227 gcc_unreachable (); 10228} 10229 [(set (attr "length") (symbol_ref "INTVAL (operands[0])"))]) 10230 10231;; 10232;; Insns related to generating the function prologue and epilogue. 10233;; 10234 10235 10236(define_expand "prologue" 10237 [(use (const_int 0))] 10238 "" 10239 "s390_emit_prologue (); DONE;") 10240 10241(define_expand "epilogue" 10242 [(use (const_int 1))] 10243 "" 10244 "s390_emit_epilogue (false); DONE;") 10245 10246(define_expand "sibcall_epilogue" 10247 [(use (const_int 0))] 10248 "" 10249 "s390_emit_epilogue (true); DONE;") 10250 10251;; A direct return instruction, without using an epilogue. 10252(define_insn "<code>" 10253 [(ANY_RETURN)] 10254 "s390_can_use_<code>_insn ()" 10255 "br\t%%r14" 10256 [(set_attr "op_type" "RR") 10257 (set_attr "type" "jsr") 10258 (set_attr "atype" "agen")]) 10259 10260(define_insn "*return" 10261 [(return) 10262 (use (match_operand 0 "register_operand" "a"))] 10263 "GET_MODE (operands[0]) == Pmode" 10264 "br\t%0" 10265 [(set_attr "op_type" "RR") 10266 (set_attr "type" "jsr") 10267 (set_attr "atype" "agen")]) 10268 10269 10270;; Instruction definition to extend a 31-bit pointer into a 64-bit 10271;; pointer. This is used for compatibility. 10272 10273(define_expand "ptr_extend" 10274 [(set (match_operand:DI 0 "register_operand" "=r") 10275 (match_operand:SI 1 "register_operand" "r"))] 10276 "TARGET_64BIT" 10277{ 10278 emit_insn (gen_anddi3 (operands[0], 10279 gen_lowpart (DImode, operands[1]), 10280 GEN_INT (0x7fffffff))); 10281 DONE; 10282}) 10283 10284;; Instruction definition to expand eh_return macro to support 10285;; swapping in special linkage return addresses. 10286 10287(define_expand "eh_return" 10288 [(use (match_operand 0 "register_operand" ""))] 10289 "TARGET_TPF" 10290{ 10291 s390_emit_tpf_eh_return (operands[0]); 10292 DONE; 10293}) 10294 10295; 10296; Stack Protector Patterns 10297; 10298 10299(define_expand "stack_protect_set" 10300 [(set (match_operand 0 "memory_operand" "") 10301 (match_operand 1 "memory_operand" ""))] 10302 "" 10303{ 10304#ifdef TARGET_THREAD_SSP_OFFSET 10305 operands[1] 10306 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), 10307 GEN_INT (TARGET_THREAD_SSP_OFFSET))); 10308#endif 10309 if (TARGET_64BIT) 10310 emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); 10311 else 10312 emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); 10313 10314 DONE; 10315}) 10316 10317(define_insn "stack_protect_set<mode>" 10318 [(set (match_operand:DSI 0 "memory_operand" "=Q") 10319 (unspec:DSI [(match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_SET))] 10320 "" 10321 "mvc\t%O0(%G0,%R0),%S1" 10322 [(set_attr "op_type" "SS")]) 10323 10324(define_expand "stack_protect_test" 10325 [(set (reg:CC CC_REGNUM) 10326 (compare (match_operand 0 "memory_operand" "") 10327 (match_operand 1 "memory_operand" ""))) 10328 (match_operand 2 "" "")] 10329 "" 10330{ 10331 rtx cc_reg, test; 10332#ifdef TARGET_THREAD_SSP_OFFSET 10333 operands[1] 10334 = gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, s390_get_thread_pointer (), 10335 GEN_INT (TARGET_THREAD_SSP_OFFSET))); 10336#endif 10337 if (TARGET_64BIT) 10338 emit_insn (gen_stack_protect_testdi (operands[0], operands[1])); 10339 else 10340 emit_insn (gen_stack_protect_testsi (operands[0], operands[1])); 10341 10342 cc_reg = gen_rtx_REG (CCZmode, CC_REGNUM); 10343 test = gen_rtx_EQ (VOIDmode, cc_reg, const0_rtx); 10344 emit_jump_insn (gen_cbranchcc4 (test, cc_reg, const0_rtx, operands[2])); 10345 DONE; 10346}) 10347 10348(define_insn "stack_protect_test<mode>" 10349 [(set (reg:CCZ CC_REGNUM) 10350 (unspec:CCZ [(match_operand:DSI 0 "memory_operand" "Q") 10351 (match_operand:DSI 1 "memory_operand" "Q")] UNSPEC_SP_TEST))] 10352 "" 10353 "clc\t%O0(%G0,%R0),%S1" 10354 [(set_attr "op_type" "SS")]) 10355 10356; This is used in s390_emit_prologue in order to prevent insns 10357; adjusting the stack pointer to be moved over insns writing stack 10358; slots using a copy of the stack pointer in a different register. 10359(define_insn "stack_tie" 10360 [(set (match_operand:BLK 0 "memory_operand" "+m") 10361 (unspec:BLK [(match_dup 0)] UNSPEC_TIE))] 10362 "" 10363 "" 10364 [(set_attr "length" "0")]) 10365 10366 10367(define_insn "stack_restore_from_fpr" 10368 [(set (reg:DI STACK_REGNUM) 10369 (match_operand:DI 0 "register_operand" "f")) 10370 (clobber (mem:BLK (scratch)))] 10371 "TARGET_Z10" 10372 "lgdr\t%%r15,%0" 10373 [(set_attr "op_type" "RRE")]) 10374 10375; 10376; Data prefetch patterns 10377; 10378 10379(define_insn "prefetch" 10380 [(prefetch (match_operand 0 "address_operand" "ZQZRZSZT,X") 10381 (match_operand:SI 1 "const_int_operand" " n,n") 10382 (match_operand:SI 2 "const_int_operand" " n,n"))] 10383 "TARGET_Z10" 10384{ 10385 switch (which_alternative) 10386 { 10387 case 0: 10388 return INTVAL (operands[1]) == 1 ? "pfd\t2,%a0" : "pfd\t1,%a0"; 10389 case 1: 10390 if (larl_operand (operands[0], Pmode)) 10391 return INTVAL (operands[1]) == 1 ? "pfdrl\t2,%a0" : "pfdrl\t1,%a0"; 10392 default: 10393 10394 /* This might be reached for symbolic operands with an odd 10395 addend. We simply omit the prefetch for such rare cases. */ 10396 10397 return ""; 10398 } 10399} 10400 [(set_attr "type" "load,larl") 10401 (set_attr "op_type" "RXY,RIL") 10402 (set_attr "z10prop" "z10_super") 10403 (set_attr "z196prop" "z196_alone")]) 10404 10405 10406; 10407; Byte swap instructions 10408; 10409 10410; FIXME: There is also mvcin but we cannot use it since src and target 10411; may overlap. 10412(define_insn "bswap<mode>2" 10413 [(set (match_operand:GPR 0 "register_operand" "=d, d") 10414 (bswap:GPR (match_operand:GPR 1 "nonimmediate_operand" " d,RT")))] 10415 "TARGET_CPU_ZARCH" 10416 "@ 10417 lrv<g>r\t%0,%1 10418 lrv<g>\t%0,%1" 10419 [(set_attr "type" "*,load") 10420 (set_attr "op_type" "RRE,RXY") 10421 (set_attr "z10prop" "z10_super")]) 10422 10423(define_insn "bswaphi2" 10424 [(set (match_operand:HI 0 "register_operand" "=d") 10425 (bswap:HI (match_operand:HI 1 "memory_operand" "RT")))] 10426 "TARGET_CPU_ZARCH" 10427 "lrvh\t%0,%1" 10428 [(set_attr "type" "load") 10429 (set_attr "op_type" "RXY") 10430 (set_attr "z10prop" "z10_super")]) 10431 10432; 10433; Population count instruction 10434; 10435 10436; The S/390 popcount instruction counts the bits of op1 in 8 byte 10437; portions and stores the result in the corresponding bytes in op0. 10438(define_insn "*popcount<mode>" 10439 [(set (match_operand:INT 0 "register_operand" "=d") 10440 (unspec:INT [(match_operand:INT 1 "register_operand" "d")] UNSPEC_POPCNT)) 10441 (clobber (reg:CC CC_REGNUM))] 10442 "TARGET_Z196" 10443 "popcnt\t%0,%1" 10444 [(set_attr "op_type" "RRE")]) 10445 10446(define_expand "popcountdi2" 10447 [; popcnt op0, op1 10448 (parallel [(set (match_operand:DI 0 "register_operand" "") 10449 (unspec:DI [(match_operand:DI 1 "register_operand")] 10450 UNSPEC_POPCNT)) 10451 (clobber (reg:CC CC_REGNUM))]) 10452 ; sllg op2, op0, 32 10453 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 32))) 10454 ; agr op0, op2 10455 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) 10456 (clobber (reg:CC CC_REGNUM))]) 10457 ; sllg op2, op0, 16 10458 (set (match_dup 2) 10459 (ashift:DI (match_dup 0) (const_int 16))) 10460 ; agr op0, op2 10461 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) 10462 (clobber (reg:CC CC_REGNUM))]) 10463 ; sllg op2, op0, 8 10464 (set (match_dup 2) (ashift:DI (match_dup 0) (const_int 8))) 10465 ; agr op0, op2 10466 (parallel [(set (match_dup 0) (plus:DI (match_dup 0) (match_dup 2))) 10467 (clobber (reg:CC CC_REGNUM))]) 10468 ; srlg op0, op0, 56 10469 (set (match_dup 0) (lshiftrt:DI (match_dup 0) (const_int 56)))] 10470 "TARGET_Z196 && TARGET_64BIT" 10471 "operands[2] = gen_reg_rtx (DImode);") 10472 10473(define_expand "popcountsi2" 10474 [; popcnt op0, op1 10475 (parallel [(set (match_operand:SI 0 "register_operand" "") 10476 (unspec:SI [(match_operand:SI 1 "register_operand")] 10477 UNSPEC_POPCNT)) 10478 (clobber (reg:CC CC_REGNUM))]) 10479 ; sllk op2, op0, 16 10480 (set (match_dup 2) 10481 (ashift:SI (match_dup 0) (const_int 16))) 10482 ; ar op0, op2 10483 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) 10484 (clobber (reg:CC CC_REGNUM))]) 10485 ; sllk op2, op0, 8 10486 (set (match_dup 2) (ashift:SI (match_dup 0) (const_int 8))) 10487 ; ar op0, op2 10488 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) 10489 (clobber (reg:CC CC_REGNUM))]) 10490 ; srl op0, op0, 24 10491 (set (match_dup 0) (lshiftrt:SI (match_dup 0) (const_int 24)))] 10492 "TARGET_Z196" 10493 "operands[2] = gen_reg_rtx (SImode);") 10494 10495(define_expand "popcounthi2" 10496 [; popcnt op0, op1 10497 (parallel [(set (match_operand:HI 0 "register_operand" "") 10498 (unspec:HI [(match_operand:HI 1 "register_operand")] 10499 UNSPEC_POPCNT)) 10500 (clobber (reg:CC CC_REGNUM))]) 10501 ; sllk op2, op0, 8 10502 (set (match_dup 2) 10503 (ashift:SI (match_dup 0) (const_int 8))) 10504 ; ar op0, op2 10505 (parallel [(set (match_dup 0) (plus:SI (match_dup 0) (match_dup 2))) 10506 (clobber (reg:CC CC_REGNUM))]) 10507 ; srl op0, op0, 8 10508 (set (match_dup 0) (lshiftrt:HI (match_dup 0) (const_int 8)))] 10509 "TARGET_Z196" 10510 "operands[2] = gen_reg_rtx (SImode);") 10511 10512(define_expand "popcountqi2" 10513 [; popcnt op0, op1 10514 (parallel [(set (match_operand:QI 0 "register_operand" "") 10515 (unspec:QI [(match_operand:QI 1 "register_operand")] 10516 UNSPEC_POPCNT)) 10517 (clobber (reg:CC CC_REGNUM))])] 10518 "TARGET_Z196" 10519 "") 10520 10521;; 10522;;- Copy sign instructions 10523;; 10524 10525(define_insn "copysign<mode>3" 10526 [(set (match_operand:FP 0 "register_operand" "=f") 10527 (unspec:FP [(match_operand:FP 1 "register_operand" "<fT0>") 10528 (match_operand:FP 2 "register_operand" "f")] 10529 UNSPEC_COPYSIGN))] 10530 "TARGET_Z196" 10531 "cpsdr\t%0,%2,%1" 10532 [(set_attr "op_type" "RRF") 10533 (set_attr "type" "fsimp<mode>")]) 10534 10535 10536;; 10537;;- Transactional execution instructions 10538;; 10539 10540; This splitter helps combine to make use of CC directly when 10541; comparing the integer result of a tbegin builtin with a constant. 10542; The unspec is already removed by canonicalize_comparison. So this 10543; splitters only job is to turn the PARALLEL into separate insns 10544; again. Unfortunately this only works with the very first cc/int 10545; compare since combine is not able to deal with data flow across 10546; basic block boundaries. 10547 10548; It needs to be an insn pattern as well since combine does not apply 10549; the splitter directly. Combine would only use it if it actually 10550; would reduce the number of instructions. 10551(define_insn_and_split "*ccraw_to_int" 10552 [(set (pc) 10553 (if_then_else 10554 (match_operator 0 "s390_eqne_operator" 10555 [(reg:CCRAW CC_REGNUM) 10556 (match_operand 1 "const_int_operand" "")]) 10557 (label_ref (match_operand 2 "" "")) 10558 (pc))) 10559 (set (match_operand:SI 3 "register_operand" "=d") 10560 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] 10561 "" 10562 "#" 10563 "" 10564 [(set (match_dup 3) 10565 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT)) 10566 (set (pc) 10567 (if_then_else (match_op_dup 0 [(reg:CCRAW CC_REGNUM) (match_dup 1)]) 10568 (label_ref (match_dup 2)) 10569 (pc)))] 10570 "") 10571 10572; Non-constrained transaction begin 10573 10574(define_expand "tbegin" 10575 [(match_operand:SI 0 "register_operand" "") 10576 (match_operand:BLK 1 "memory_operand" "")] 10577 "TARGET_HTM" 10578{ 10579 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, true); 10580 DONE; 10581}) 10582 10583(define_expand "tbegin_nofloat" 10584 [(match_operand:SI 0 "register_operand" "") 10585 (match_operand:BLK 1 "memory_operand" "")] 10586 "TARGET_HTM" 10587{ 10588 s390_expand_tbegin (operands[0], operands[1], NULL_RTX, false); 10589 DONE; 10590}) 10591 10592(define_expand "tbegin_retry" 10593 [(match_operand:SI 0 "register_operand" "") 10594 (match_operand:BLK 1 "memory_operand" "") 10595 (match_operand:SI 2 "general_operand" "")] 10596 "TARGET_HTM" 10597{ 10598 s390_expand_tbegin (operands[0], operands[1], operands[2], true); 10599 DONE; 10600}) 10601 10602(define_expand "tbegin_retry_nofloat" 10603 [(match_operand:SI 0 "register_operand" "") 10604 (match_operand:BLK 1 "memory_operand" "") 10605 (match_operand:SI 2 "general_operand" "")] 10606 "TARGET_HTM" 10607{ 10608 s390_expand_tbegin (operands[0], operands[1], operands[2], false); 10609 DONE; 10610}) 10611 10612(define_insn "tbegin_1" 10613 [(set (reg:CCRAW CC_REGNUM) 10614 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] 10615 UNSPECV_TBEGIN)) 10616 (set (match_operand:BLK 1 "memory_operand" "=Q") 10617 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB)) 10618 (clobber (reg:DF 16)) 10619 (clobber (reg:DF 17)) 10620 (clobber (reg:DF 18)) 10621 (clobber (reg:DF 19)) 10622 (clobber (reg:DF 20)) 10623 (clobber (reg:DF 21)) 10624 (clobber (reg:DF 22)) 10625 (clobber (reg:DF 23)) 10626 (clobber (reg:DF 24)) 10627 (clobber (reg:DF 25)) 10628 (clobber (reg:DF 26)) 10629 (clobber (reg:DF 27)) 10630 (clobber (reg:DF 28)) 10631 (clobber (reg:DF 29)) 10632 (clobber (reg:DF 30)) 10633 (clobber (reg:DF 31))] 10634; CONST_OK_FOR_CONSTRAINT_P does not work with D constraint since D is 10635; not supposed to be used for immediates (see genpreds.c). 10636 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 10637 "tbegin\t%1,%x0" 10638 [(set_attr "op_type" "SIL")]) 10639 10640; Same as above but without the FPR clobbers 10641(define_insn "tbegin_nofloat_1" 10642 [(set (reg:CCRAW CC_REGNUM) 10643 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" "D")] 10644 UNSPECV_TBEGIN)) 10645 (set (match_operand:BLK 1 "memory_operand" "=Q") 10646 (unspec_volatile:BLK [(match_dup 0)] UNSPECV_TBEGIN_TDB))] 10647 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 10648 "tbegin\t%1,%x0" 10649 [(set_attr "op_type" "SIL")]) 10650 10651 10652; Constrained transaction begin 10653 10654(define_expand "tbeginc" 10655 [(set (reg:CCRAW CC_REGNUM) 10656 (unspec_volatile:CCRAW [(const_int TBEGINC_MASK)] 10657 UNSPECV_TBEGINC))] 10658 "TARGET_HTM" 10659 "") 10660 10661(define_insn "*tbeginc_1" 10662 [(set (reg:CCRAW CC_REGNUM) 10663 (unspec_volatile:CCRAW [(match_operand 0 "const_int_operand" " D")] 10664 UNSPECV_TBEGINC))] 10665 "TARGET_HTM && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 0xffff" 10666 "tbeginc\t0,%x0" 10667 [(set_attr "op_type" "SIL")]) 10668 10669; Transaction end 10670 10671(define_expand "tend" 10672 [(set (reg:CCRAW CC_REGNUM) 10673 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND)) 10674 (set (match_operand:SI 0 "register_operand" "") 10675 (unspec:SI [(reg:CCRAW CC_REGNUM)] UNSPEC_CC_TO_INT))] 10676 "TARGET_HTM" 10677 "") 10678 10679(define_insn "*tend_1" 10680 [(set (reg:CCRAW CC_REGNUM) 10681 (unspec_volatile:CCRAW [(const_int 0)] UNSPECV_TEND))] 10682 "TARGET_HTM" 10683 "tend" 10684 [(set_attr "op_type" "S")]) 10685 10686; Transaction abort 10687 10688(define_expand "tabort" 10689 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "")] 10690 UNSPECV_TABORT)] 10691 "TARGET_HTM && operands != NULL" 10692{ 10693 if (CONST_INT_P (operands[0]) 10694 && INTVAL (operands[0]) >= 0 && INTVAL (operands[0]) <= 255) 10695 { 10696 error ("Invalid transaction abort code: " HOST_WIDE_INT_PRINT_DEC 10697 ". Values in range 0 through 255 are reserved.", 10698 INTVAL (operands[0])); 10699 FAIL; 10700 } 10701}) 10702 10703(define_insn "*tabort_1" 10704 [(unspec_volatile [(match_operand:SI 0 "shift_count_or_setmem_operand" "Y")] 10705 UNSPECV_TABORT)] 10706 "TARGET_HTM && operands != NULL" 10707 "tabort\t%Y0" 10708 [(set_attr "op_type" "S")]) 10709 10710; Transaction extract nesting depth 10711 10712(define_insn "etnd" 10713 [(set (match_operand:SI 0 "register_operand" "=d") 10714 (unspec_volatile:SI [(const_int 0)] UNSPECV_ETND))] 10715 "TARGET_HTM" 10716 "etnd\t%0" 10717 [(set_attr "op_type" "RRE")]) 10718 10719; Non-transactional store 10720 10721(define_insn "ntstg" 10722 [(set (match_operand:DI 0 "memory_operand" "=RT") 10723 (unspec_volatile:DI [(match_operand:DI 1 "register_operand" "d")] 10724 UNSPECV_NTSTG))] 10725 "TARGET_HTM" 10726 "ntstg\t%1,%0" 10727 [(set_attr "op_type" "RXY")]) 10728 10729; Transaction perform processor assist 10730 10731(define_expand "tx_assist" 10732 [(unspec_volatile [(match_operand:SI 0 "register_operand" "") 10733 (reg:SI GPR0_REGNUM) 10734 (const_int 1)] 10735 UNSPECV_PPA)] 10736 "TARGET_HTM" 10737 "") 10738 10739(define_insn "*ppa" 10740 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d") 10741 (match_operand:SI 1 "register_operand" "d") 10742 (match_operand 2 "const_int_operand" "I")] 10743 UNSPECV_PPA)] 10744 "TARGET_HTM && INTVAL (operands[2]) < 16" 10745 "ppa\t%0,%1,%2" 10746 [(set_attr "op_type" "RRF")]) 10747 10748 10749; Set and get floating point control register 10750 10751(define_insn "sfpc" 10752 [(unspec_volatile [(match_operand:SI 0 "register_operand" "d")] 10753 UNSPECV_SFPC)] 10754 "TARGET_HARD_FLOAT" 10755 "sfpc\t%0") 10756 10757(define_insn "efpc" 10758 [(set (match_operand:SI 0 "register_operand" "=d") 10759 (unspec_volatile:SI [(const_int 0)] UNSPECV_EFPC))] 10760 "TARGET_HARD_FLOAT" 10761 "efpc\t%0") 10762 10763 10764; Load count to block boundary 10765 10766(define_insn "lcbb" 10767 [(set (match_operand:SI 0 "register_operand" "=d") 10768 (unspec:SI [(match_operand 1 "address_operand" "ZQZR") 10769 (match_operand:SI 2 "immediate_operand" "C")] UNSPEC_LCBB)) 10770 (clobber (reg:CC CC_REGNUM))] 10771 "TARGET_Z13" 10772 "lcbb\t%0,%a1,%b2" 10773 [(set_attr "op_type" "VRX")]) 10774