1 /* Definitions of target machine for GNU compiler, for IBM S/390 2 Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 3 2007, 2008, 2009 Free Software Foundation, Inc. 4 Contributed by Hartmut Penner (hpenner@de.ibm.com) and 5 Ulrich Weigand (uweigand@de.ibm.com). 6 Andreas Krebbel (Andreas.Krebbel@de.ibm.com) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it under 11 the terms of the GNU General Public License as published by the Free 12 Software Foundation; either version 3, or (at your option) any later 13 version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT ANY 16 WARRANTY; without even the implied warranty of MERCHANTABILITY or 17 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18 for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with GCC; see the file COPYING3. If not see 22 <http://www.gnu.org/licenses/>. */ 23 24 #ifndef _S390_H 25 #define _S390_H 26 27 /* Which processor to generate code or schedule for. The cpu attribute 28 defines a list that mirrors this list, so changes to s390.md must be 29 made at the same time. */ 30 31 enum processor_type 32 { 33 PROCESSOR_9672_G5, 34 PROCESSOR_9672_G6, 35 PROCESSOR_2064_Z900, 36 PROCESSOR_2084_Z990, 37 PROCESSOR_2094_Z9_109, 38 PROCESSOR_2097_Z10, 39 PROCESSOR_max 40 }; 41 42 /* Optional architectural facilities supported by the processor. */ 43 44 enum processor_flags 45 { 46 PF_IEEE_FLOAT = 1, 47 PF_ZARCH = 2, 48 PF_LONG_DISPLACEMENT = 4, 49 PF_EXTIMM = 8, 50 PF_DFP = 16, 51 PF_Z10 = 32 52 }; 53 54 extern enum processor_type s390_tune; 55 extern int s390_tune_flags; 56 57 /* This is necessary to avoid a warning about comparing different enum 58 types. */ 59 #define s390_tune_attr ((enum attr_cpu)s390_tune) 60 61 extern enum processor_type s390_arch; 62 extern int s390_arch_flags; 63 64 /* These flags indicate that the generated code should run on a cpu 65 providing the respective hardware facility regardless of the 66 current cpu mode (ESA or z/Architecture). */ 67 68 #define TARGET_CPU_IEEE_FLOAT \ 69 (s390_arch_flags & PF_IEEE_FLOAT) 70 #define TARGET_CPU_ZARCH \ 71 (s390_arch_flags & PF_ZARCH) 72 #define TARGET_CPU_LONG_DISPLACEMENT \ 73 (s390_arch_flags & PF_LONG_DISPLACEMENT) 74 #define TARGET_CPU_EXTIMM \ 75 (s390_arch_flags & PF_EXTIMM) 76 #define TARGET_CPU_DFP \ 77 (s390_arch_flags & PF_DFP) 78 #define TARGET_CPU_Z10 \ 79 (s390_arch_flags & PF_Z10) 80 81 /* These flags indicate that the generated code should run on a cpu 82 providing the respective hardware facility when run in 83 z/Architecture mode. */ 84 85 #define TARGET_LONG_DISPLACEMENT \ 86 (TARGET_ZARCH && TARGET_CPU_LONG_DISPLACEMENT) 87 #define TARGET_EXTIMM \ 88 (TARGET_ZARCH && TARGET_CPU_EXTIMM) 89 #define TARGET_DFP \ 90 (TARGET_ZARCH && TARGET_CPU_DFP && TARGET_HARD_FLOAT) 91 #define TARGET_Z10 \ 92 (TARGET_ZARCH && TARGET_CPU_Z10) 93 94 /* Run-time target specification. */ 95 96 /* Defaults for option flags defined only on some subtargets. */ 97 #ifndef TARGET_TPF_PROFILING 98 #define TARGET_TPF_PROFILING 0 99 #endif 100 101 /* This will be overridden by OS headers. */ 102 #define TARGET_TPF 0 103 104 /* Target CPU builtins. */ 105 #define TARGET_CPU_CPP_BUILTINS() \ 106 do \ 107 { \ 108 builtin_assert ("cpu=s390"); \ 109 builtin_assert ("machine=s390"); \ 110 builtin_define ("__s390__"); \ 111 if (TARGET_64BIT) \ 112 builtin_define ("__s390x__"); \ 113 if (TARGET_LONG_DOUBLE_128) \ 114 builtin_define ("__LONG_DOUBLE_128__"); \ 115 } \ 116 while (0) 117 118 #ifdef DEFAULT_TARGET_64BIT 119 #define TARGET_DEFAULT (MASK_64BIT | MASK_ZARCH | MASK_HARD_DFP) 120 #else 121 #define TARGET_DEFAULT 0 122 #endif 123 124 /* Support for configure-time defaults. */ 125 #define OPTION_DEFAULT_SPECS \ 126 { "mode", "%{!mesa:%{!mzarch:-m%(VALUE)}}" }, \ 127 { "arch", "%{!march=*:-march=%(VALUE)}" }, \ 128 { "tune", "%{!mtune=*:-mtune=%(VALUE)}" } 129 130 /* Defaulting rules. */ 131 #ifdef DEFAULT_TARGET_64BIT 132 #define DRIVER_SELF_SPECS \ 133 "%{!m31:%{!m64:-m64}}", \ 134 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ 135 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" 136 #else 137 #define DRIVER_SELF_SPECS \ 138 "%{!m31:%{!m64:-m31}}", \ 139 "%{!mesa:%{!mzarch:%{m31:-mesa}%{m64:-mzarch}}}", \ 140 "%{!march=*:%{mesa:-march=g5}%{mzarch:-march=z900}}" 141 #endif 142 143 /* Target version string. Overridden by the OS header. */ 144 #ifdef DEFAULT_TARGET_64BIT 145 #define TARGET_VERSION fprintf (stderr, " (zSeries)"); 146 #else 147 #define TARGET_VERSION fprintf (stderr, " (S/390)"); 148 #endif 149 150 /* Hooks to override options. */ 151 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) optimization_options(LEVEL, SIZE) 152 #define OVERRIDE_OPTIONS override_options () 153 154 /* Frame pointer is not used for debugging. */ 155 #define CAN_DEBUG_WITHOUT_FP 156 157 /* Constants needed to control the TEST DATA CLASS (TDC) instruction. */ 158 #define S390_TDC_POSITIVE_ZERO (1 << 11) 159 #define S390_TDC_NEGATIVE_ZERO (1 << 10) 160 #define S390_TDC_POSITIVE_NORMALIZED_BFP_NUMBER (1 << 9) 161 #define S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER (1 << 8) 162 #define S390_TDC_POSITIVE_DENORMALIZED_BFP_NUMBER (1 << 7) 163 #define S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER (1 << 6) 164 #define S390_TDC_POSITIVE_INFINITY (1 << 5) 165 #define S390_TDC_NEGATIVE_INFINITY (1 << 4) 166 #define S390_TDC_POSITIVE_QUIET_NAN (1 << 3) 167 #define S390_TDC_NEGATIVE_QUIET_NAN (1 << 2) 168 #define S390_TDC_POSITIVE_SIGNALING_NAN (1 << 1) 169 #define S390_TDC_NEGATIVE_SIGNALING_NAN (1 << 0) 170 171 /* The following values are different for DFP. */ 172 #define S390_TDC_POSITIVE_DENORMALIZED_DFP_NUMBER (1 << 9) 173 #define S390_TDC_NEGATIVE_DENORMALIZED_DFP_NUMBER (1 << 8) 174 #define S390_TDC_POSITIVE_NORMALIZED_DFP_NUMBER (1 << 7) 175 #define S390_TDC_NEGATIVE_NORMALIZED_DFP_NUMBER (1 << 6) 176 177 /* For signbit, the BFP-DFP-difference makes no difference. */ 178 #define S390_TDC_SIGNBIT_SET (S390_TDC_NEGATIVE_ZERO \ 179 | S390_TDC_NEGATIVE_NORMALIZED_BFP_NUMBER \ 180 | S390_TDC_NEGATIVE_DENORMALIZED_BFP_NUMBER\ 181 | S390_TDC_NEGATIVE_INFINITY \ 182 | S390_TDC_NEGATIVE_QUIET_NAN \ 183 | S390_TDC_NEGATIVE_SIGNALING_NAN ) 184 185 #define S390_TDC_INFINITY (S390_TDC_POSITIVE_INFINITY \ 186 | S390_TDC_NEGATIVE_INFINITY ) 187 188 /* In libgcc2, determine target settings as compile-time constants. */ 189 #ifdef IN_LIBGCC2 190 #undef TARGET_64BIT 191 #ifdef __s390x__ 192 #define TARGET_64BIT 1 193 #else 194 #define TARGET_64BIT 0 195 #endif 196 #endif 197 198 199 /* Target machine storage layout. */ 200 201 /* Everything is big-endian. */ 202 #define BITS_BIG_ENDIAN 1 203 #define BYTES_BIG_ENDIAN 1 204 #define WORDS_BIG_ENDIAN 1 205 206 /* Width of a word, in units (bytes). */ 207 #define UNITS_PER_WORD (TARGET_64BIT ? 8 : 4) 208 #ifndef IN_LIBGCC2 209 #define MIN_UNITS_PER_WORD 4 210 #endif 211 #define MAX_BITS_PER_WORD 64 212 213 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 214 #define PARM_BOUNDARY (TARGET_64BIT ? 64 : 32) 215 216 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 217 #define STACK_BOUNDARY 64 218 219 /* Allocation boundary (in *bits*) for the code of a function. */ 220 #define FUNCTION_BOUNDARY 32 221 222 /* There is no point aligning anything to a rounder boundary than this. */ 223 #define BIGGEST_ALIGNMENT 64 224 225 /* Alignment of field after `int : 0' in a structure. */ 226 #define EMPTY_FIELD_BOUNDARY 32 227 228 /* Alignment on even addresses for LARL instruction. */ 229 #define CONSTANT_ALIGNMENT(EXP, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) 230 #define DATA_ALIGNMENT(TYPE, ALIGN) (ALIGN) < 16 ? 16 : (ALIGN) 231 232 /* Alignment is not required by the hardware. */ 233 #define STRICT_ALIGNMENT 0 234 235 /* Mode of stack savearea. 236 FUNCTION is VOIDmode because calling convention maintains SP. 237 BLOCK needs Pmode for SP. 238 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 239 #define STACK_SAVEAREA_MODE(LEVEL) \ 240 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 241 : LEVEL == SAVE_NONLOCAL ? (TARGET_64BIT ? OImode : TImode) : Pmode) 242 243 244 /* Type layout. */ 245 246 /* Sizes in bits of the source language data types. */ 247 #define SHORT_TYPE_SIZE 16 248 #define INT_TYPE_SIZE 32 249 #define LONG_TYPE_SIZE (TARGET_64BIT ? 64 : 32) 250 #define LONG_LONG_TYPE_SIZE 64 251 #define FLOAT_TYPE_SIZE 32 252 #define DOUBLE_TYPE_SIZE 64 253 #define LONG_DOUBLE_TYPE_SIZE (TARGET_LONG_DOUBLE_128 ? 128 : 64) 254 255 /* Define this to set long double type size to use in libgcc2.c, which can 256 not depend on target_flags. */ 257 #ifdef __LONG_DOUBLE_128__ 258 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 259 #else 260 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 261 #endif 262 263 /* Work around target_flags dependency in ada/targtyps.c. */ 264 #define WIDEST_HARDWARE_FP_SIZE 64 265 266 /* We use "unsigned char" as default. */ 267 #define DEFAULT_SIGNED_CHAR 0 268 269 270 /* Register usage. */ 271 272 /* We have 16 general purpose registers (registers 0-15), 273 and 16 floating point registers (registers 16-31). 274 (On non-IEEE machines, we have only 4 fp registers.) 275 276 Amongst the general purpose registers, some are used 277 for specific purposes: 278 GPR 11: Hard frame pointer (if needed) 279 GPR 12: Global offset table pointer (if needed) 280 GPR 13: Literal pool base register 281 GPR 14: Return address register 282 GPR 15: Stack pointer 283 284 Registers 32-35 are 'fake' hard registers that do not 285 correspond to actual hardware: 286 Reg 32: Argument pointer 287 Reg 33: Condition code 288 Reg 34: Frame pointer 289 Reg 35: Return address pointer 290 291 Registers 36 and 37 are mapped to access registers 292 0 and 1, used to implement thread-local storage. */ 293 294 #define FIRST_PSEUDO_REGISTER 38 295 296 /* Standard register usage. */ 297 #define GENERAL_REGNO_P(N) ((int)(N) >= 0 && (N) < 16) 298 #define ADDR_REGNO_P(N) ((N) >= 1 && (N) < 16) 299 #define FP_REGNO_P(N) ((N) >= 16 && (N) < 32) 300 #define CC_REGNO_P(N) ((N) == 33) 301 #define FRAME_REGNO_P(N) ((N) == 32 || (N) == 34 || (N) == 35) 302 #define ACCESS_REGNO_P(N) ((N) == 36 || (N) == 37) 303 304 #define GENERAL_REG_P(X) (REG_P (X) && GENERAL_REGNO_P (REGNO (X))) 305 #define ADDR_REG_P(X) (REG_P (X) && ADDR_REGNO_P (REGNO (X))) 306 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 307 #define CC_REG_P(X) (REG_P (X) && CC_REGNO_P (REGNO (X))) 308 #define FRAME_REG_P(X) (REG_P (X) && FRAME_REGNO_P (REGNO (X))) 309 #define ACCESS_REG_P(X) (REG_P (X) && ACCESS_REGNO_P (REGNO (X))) 310 311 /* Set up fixed registers and calling convention: 312 313 GPRs 0-5 are always call-clobbered, 314 GPRs 6-15 are always call-saved. 315 GPR 12 is fixed if used as GOT pointer. 316 GPR 13 is always fixed (as literal pool pointer). 317 GPR 14 is always fixed on S/390 machines (as return address). 318 GPR 15 is always fixed (as stack pointer). 319 The 'fake' hard registers are call-clobbered and fixed. 320 The access registers are call-saved and fixed. 321 322 On 31-bit, FPRs 18-19 are call-clobbered; 323 on 64-bit, FPRs 24-31 are call-clobbered. 324 The remaining FPRs are call-saved. */ 325 326 #define FIXED_REGISTERS \ 327 { 0, 0, 0, 0, \ 328 0, 0, 0, 0, \ 329 0, 0, 0, 0, \ 330 0, 1, 1, 1, \ 331 0, 0, 0, 0, \ 332 0, 0, 0, 0, \ 333 0, 0, 0, 0, \ 334 0, 0, 0, 0, \ 335 1, 1, 1, 1, \ 336 1, 1 } 337 338 #define CALL_USED_REGISTERS \ 339 { 1, 1, 1, 1, \ 340 1, 1, 0, 0, \ 341 0, 0, 0, 0, \ 342 0, 1, 1, 1, \ 343 1, 1, 1, 1, \ 344 1, 1, 1, 1, \ 345 1, 1, 1, 1, \ 346 1, 1, 1, 1, \ 347 1, 1, 1, 1, \ 348 1, 1 } 349 350 #define CALL_REALLY_USED_REGISTERS \ 351 { 1, 1, 1, 1, \ 352 1, 1, 0, 0, \ 353 0, 0, 0, 0, \ 354 0, 0, 0, 0, \ 355 1, 1, 1, 1, \ 356 1, 1, 1, 1, \ 357 1, 1, 1, 1, \ 358 1, 1, 1, 1, \ 359 1, 1, 1, 1, \ 360 0, 0 } 361 362 #define CONDITIONAL_REGISTER_USAGE s390_conditional_register_usage () 363 364 /* Preferred register allocation order. */ 365 #define REG_ALLOC_ORDER \ 366 { 1, 2, 3, 4, 5, 0, 12, 11, 10, 9, 8, 7, 6, 14, 13, \ 367 16, 17, 18, 19, 20, 21, 22, 23, \ 368 24, 25, 26, 27, 28, 29, 30, 31, \ 369 15, 32, 33, 34, 35, 36, 37 } 370 371 372 /* Fitting values into registers. */ 373 374 /* Integer modes <= word size fit into any GPR. 375 Integer modes > word size fit into successive GPRs, starting with 376 an even-numbered register. 377 SImode and DImode fit into FPRs as well. 378 379 Floating point modes <= word size fit into any FPR or GPR. 380 Floating point modes > word size (i.e. DFmode on 32-bit) fit 381 into any FPR, or an even-odd GPR pair. 382 TFmode fits only into an even-odd FPR pair. 383 384 Complex floating point modes fit either into two FPRs, or into 385 successive GPRs (again starting with an even number). 386 TCmode fits only into two successive even-odd FPR pairs. 387 388 Condition code modes fit only into the CC register. */ 389 390 /* Because all registers in a class have the same size HARD_REGNO_NREGS 391 is equivalent to CLASS_MAX_NREGS. */ 392 #define HARD_REGNO_NREGS(REGNO, MODE) \ 393 s390_class_max_nregs (REGNO_REG_CLASS (REGNO), (MODE)) 394 395 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 396 s390_hard_regno_mode_ok ((REGNO), (MODE)) 397 398 #define HARD_REGNO_RENAME_OK(FROM, TO) \ 399 s390_hard_regno_rename_ok (FROM, TO) 400 401 #define MODES_TIEABLE_P(MODE1, MODE2) \ 402 (((MODE1) == SFmode || (MODE1) == DFmode) \ 403 == ((MODE2) == SFmode || (MODE2) == DFmode)) 404 405 /* Maximum number of registers to represent a value of mode MODE 406 in a register of class CLASS. */ 407 #define CLASS_MAX_NREGS(CLASS, MODE) \ 408 s390_class_max_nregs ((CLASS), (MODE)) 409 410 /* If a 4-byte value is loaded into a FPR, it is placed into the 411 *upper* half of the register, not the lower. Therefore, we 412 cannot use SUBREGs to switch between modes in FP registers. 413 Likewise for access registers, since they have only half the 414 word size on 64-bit. */ 415 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 416 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 417 ? ((reg_classes_intersect_p (FP_REGS, CLASS) \ 418 && (GET_MODE_SIZE (FROM) < 8 || GET_MODE_SIZE (TO) < 8)) \ 419 || reg_classes_intersect_p (ACCESS_REGS, CLASS)) : 0) 420 421 /* Register classes. */ 422 423 /* We use the following register classes: 424 GENERAL_REGS All general purpose registers 425 ADDR_REGS All general purpose registers except %r0 426 (These registers can be used in address generation) 427 FP_REGS All floating point registers 428 CC_REGS The condition code register 429 ACCESS_REGS The access registers 430 431 GENERAL_FP_REGS Union of GENERAL_REGS and FP_REGS 432 ADDR_FP_REGS Union of ADDR_REGS and FP_REGS 433 GENERAL_CC_REGS Union of GENERAL_REGS and CC_REGS 434 ADDR_CC_REGS Union of ADDR_REGS and CC_REGS 435 436 NO_REGS No registers 437 ALL_REGS All registers 438 439 Note that the 'fake' frame pointer and argument pointer registers 440 are included amongst the address registers here. */ 441 442 enum reg_class 443 { 444 NO_REGS, CC_REGS, ADDR_REGS, GENERAL_REGS, ACCESS_REGS, 445 ADDR_CC_REGS, GENERAL_CC_REGS, 446 FP_REGS, ADDR_FP_REGS, GENERAL_FP_REGS, 447 ALL_REGS, LIM_REG_CLASSES 448 }; 449 #define N_REG_CLASSES (int) LIM_REG_CLASSES 450 451 #define REG_CLASS_NAMES \ 452 { "NO_REGS", "CC_REGS", "ADDR_REGS", "GENERAL_REGS", "ACCESS_REGS", \ 453 "ADDR_CC_REGS", "GENERAL_CC_REGS", \ 454 "FP_REGS", "ADDR_FP_REGS", "GENERAL_FP_REGS", "ALL_REGS" } 455 456 /* Class -> register mapping. */ 457 #define REG_CLASS_CONTENTS \ 458 { \ 459 { 0x00000000, 0x00000000 }, /* NO_REGS */ \ 460 { 0x00000000, 0x00000002 }, /* CC_REGS */ \ 461 { 0x0000fffe, 0x0000000d }, /* ADDR_REGS */ \ 462 { 0x0000ffff, 0x0000000d }, /* GENERAL_REGS */ \ 463 { 0x00000000, 0x00000030 }, /* ACCESS_REGS */ \ 464 { 0x0000fffe, 0x0000000f }, /* ADDR_CC_REGS */ \ 465 { 0x0000ffff, 0x0000000f }, /* GENERAL_CC_REGS */ \ 466 { 0xffff0000, 0x00000000 }, /* FP_REGS */ \ 467 { 0xfffffffe, 0x0000000d }, /* ADDR_FP_REGS */ \ 468 { 0xffffffff, 0x0000000d }, /* GENERAL_FP_REGS */ \ 469 { 0xffffffff, 0x0000003f }, /* ALL_REGS */ \ 470 } 471 472 /* The following macro defines cover classes for Integrated Register 473 Allocator. Cover classes is a set of non-intersected register 474 classes covering all hard registers used for register allocation 475 purpose. Any move between two registers of a cover class should be 476 cheaper than load or store of the registers. The macro value is 477 array of register classes with LIM_REG_CLASSES used as the end 478 marker. */ 479 480 #define IRA_COVER_CLASSES \ 481 { \ 482 GENERAL_REGS, FP_REGS, CC_REGS, ACCESS_REGS, LIM_REG_CLASSES \ 483 } 484 485 /* In some case register allocation order is not enough for IRA to 486 generate a good code. The following macro (if defined) increases 487 cost of REGNO for a pseudo approximately by pseudo usage frequency 488 multiplied by the macro value. 489 490 We avoid usage of BASE_REGNUM by nonzero macro value because the 491 reload can decide not to use the hard register because some 492 constant was forced to be in memory. */ 493 #define IRA_HARD_REGNO_ADD_COST_MULTIPLIER(regno) \ 494 (regno == BASE_REGNUM ? 0.0 : 0.5) 495 496 /* Register -> class mapping. */ 497 extern const enum reg_class regclass_map[FIRST_PSEUDO_REGISTER]; 498 #define REGNO_REG_CLASS(REGNO) (regclass_map[REGNO]) 499 500 /* ADDR_REGS can be used as base or index register. */ 501 #define INDEX_REG_CLASS ADDR_REGS 502 #define BASE_REG_CLASS ADDR_REGS 503 504 /* Check whether REGNO is a hard register of the suitable class 505 or a pseudo register currently allocated to one such. */ 506 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 507 (((REGNO) < FIRST_PSEUDO_REGISTER \ 508 && REGNO_REG_CLASS ((REGNO)) == ADDR_REGS) \ 509 || ADDR_REGNO_P (reg_renumber[REGNO])) 510 #define REGNO_OK_FOR_BASE_P(REGNO) REGNO_OK_FOR_INDEX_P (REGNO) 511 512 513 /* Given an rtx X being reloaded into a reg required to be in class CLASS, 514 return the class of reg to actually use. */ 515 #define PREFERRED_RELOAD_CLASS(X, CLASS) \ 516 s390_preferred_reload_class ((X), (CLASS)) 517 518 /* We need secondary memory to move data between GPRs and FPRs. With 519 DFP the ldgr lgdr instructions are available. But these 520 instructions do not handle GPR pairs so it is not possible for 31 521 bit. */ 522 #define SECONDARY_MEMORY_NEEDED(CLASS1, CLASS2, MODE) \ 523 ((CLASS1) != (CLASS2) \ 524 && ((CLASS1) == FP_REGS || (CLASS2) == FP_REGS) \ 525 && (!TARGET_DFP || !TARGET_64BIT || GET_MODE_SIZE (MODE) != 8)) 526 527 /* Get_secondary_mem widens its argument to BITS_PER_WORD which loses on 64bit 528 because the movsi and movsf patterns don't handle r/f moves. */ 529 #define SECONDARY_MEMORY_NEEDED_MODE(MODE) \ 530 (GET_MODE_BITSIZE (MODE) < 32 \ 531 ? mode_for_size (32, GET_MODE_CLASS (MODE), 0) \ 532 : MODE) 533 534 535 /* Stack layout and calling conventions. */ 536 537 /* Our stack grows from higher to lower addresses. However, local variables 538 are accessed by positive offsets, and function arguments are stored at 539 increasing addresses. */ 540 #define STACK_GROWS_DOWNWARD 541 #define FRAME_GROWS_DOWNWARD 1 542 /* #undef ARGS_GROW_DOWNWARD */ 543 544 /* The basic stack layout looks like this: the stack pointer points 545 to the register save area for called functions. Above that area 546 is the location to place outgoing arguments. Above those follow 547 dynamic allocations (alloca), and finally the local variables. */ 548 549 /* Offset from stack-pointer to first location of outgoing args. */ 550 #define STACK_POINTER_OFFSET (TARGET_64BIT ? 160 : 96) 551 552 /* Offset within stack frame to start allocating local variables at. */ 553 #define STARTING_FRAME_OFFSET 0 554 555 /* Offset from the stack pointer register to an item dynamically 556 allocated on the stack, e.g., by `alloca'. */ 557 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 558 (STACK_POINTER_OFFSET + crtl->outgoing_args_size) 559 560 /* Offset of first parameter from the argument pointer register value. 561 We have a fake argument pointer register that points directly to 562 the argument area. */ 563 #define FIRST_PARM_OFFSET(FNDECL) 0 564 565 /* Defining this macro makes __builtin_frame_address(0) and 566 __builtin_return_address(0) work with -fomit-frame-pointer. */ 567 #define INITIAL_FRAME_ADDRESS_RTX \ 568 (plus_constant (arg_pointer_rtx, -STACK_POINTER_OFFSET)) 569 570 /* The return address of the current frame is retrieved 571 from the initial value of register RETURN_REGNUM. 572 For frames farther back, we use the stack slot where 573 the corresponding RETURN_REGNUM register was saved. */ 574 #define DYNAMIC_CHAIN_ADDRESS(FRAME) \ 575 (TARGET_PACKED_STACK ? \ 576 plus_constant ((FRAME), STACK_POINTER_OFFSET - UNITS_PER_WORD) : (FRAME)) 577 578 /* For -mpacked-stack this adds 160 - 8 (96 - 4) to the output of 579 builtin_frame_address. Otherwise arg pointer - 580 STACK_POINTER_OFFSET would be returned for 581 __builtin_frame_address(0) what might result in an address pointing 582 somewhere into the middle of the local variables since the packed 583 stack layout generally does not need all the bytes in the register 584 save area. */ 585 #define FRAME_ADDR_RTX(FRAME) \ 586 DYNAMIC_CHAIN_ADDRESS ((FRAME)) 587 588 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 589 s390_return_addr_rtx ((COUNT), DYNAMIC_CHAIN_ADDRESS ((FRAME))) 590 591 /* In 31-bit mode, we need to mask off the high bit of return addresses. */ 592 #define MASK_RETURN_ADDR (TARGET_64BIT ? constm1_rtx : GEN_INT (0x7fffffff)) 593 594 595 /* Exception handling. */ 596 597 /* Describe calling conventions for DWARF-2 exception handling. */ 598 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_REGNUM) 599 #define INCOMING_FRAME_SP_OFFSET STACK_POINTER_OFFSET 600 #define DWARF_FRAME_RETURN_COLUMN 14 601 602 /* Describe how we implement __builtin_eh_return. */ 603 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 6 : INVALID_REGNUM) 604 #define EH_RETURN_HANDLER_RTX gen_rtx_MEM (Pmode, return_address_pointer_rtx) 605 606 /* Select a format to encode pointers in exception handling data. */ 607 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 608 (flag_pic \ 609 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 610 : DW_EH_PE_absptr) 611 612 613 /* Frame registers. */ 614 615 #define STACK_POINTER_REGNUM 15 616 #define FRAME_POINTER_REGNUM 34 617 #define HARD_FRAME_POINTER_REGNUM 11 618 #define ARG_POINTER_REGNUM 32 619 #define RETURN_ADDRESS_POINTER_REGNUM 35 620 621 /* The static chain must be call-clobbered, but not used for 622 function argument passing. As register 1 is clobbered by 623 the trampoline code, we only have one option. */ 624 #define STATIC_CHAIN_REGNUM 0 625 626 /* Number of hardware registers that go into the DWARF-2 unwind info. 627 To avoid ABI incompatibility, this number must not change even as 628 'fake' hard registers are added or removed. */ 629 #define DWARF_FRAME_REGISTERS 34 630 631 632 /* Frame pointer and argument pointer elimination. */ 633 634 #define ELIMINABLE_REGS \ 635 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 636 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 637 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 638 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 639 { RETURN_ADDRESS_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 640 { RETURN_ADDRESS_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 641 { BASE_REGNUM, BASE_REGNUM }} 642 643 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 644 (OFFSET) = s390_initial_elimination_offset ((FROM), (TO)) 645 646 647 /* Stack arguments. */ 648 649 /* We need current_function_outgoing_args to be valid. */ 650 #define ACCUMULATE_OUTGOING_ARGS 1 651 652 /* Return doesn't modify the stack. */ 653 #define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 654 655 656 /* Register arguments. */ 657 658 typedef struct s390_arg_structure 659 { 660 int gprs; /* gpr so far */ 661 int fprs; /* fpr so far */ 662 } 663 CUMULATIVE_ARGS; 664 665 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, NN, N_NAMED_ARGS) \ 666 ((CUM).gprs=0, (CUM).fprs=0) 667 668 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 669 s390_function_arg_advance (&CUM, MODE, TYPE, NAMED) 670 671 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 672 s390_function_arg (&CUM, MODE, TYPE, NAMED) 673 674 /* Arguments can be placed in general registers 2 to 6, or in floating 675 point registers 0 and 2 for 31 bit and fprs 0, 2, 4 and 6 for 64 676 bit. */ 677 #define FUNCTION_ARG_REGNO_P(N) (((N) >=2 && (N) <7) || \ 678 (N) == 16 || (N) == 17 || (TARGET_64BIT && ((N) == 18 || (N) == 19))) 679 680 681 /* Scalar return values. */ 682 683 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 684 s390_function_value ((VALTYPE), (FUNC), VOIDmode) 685 686 #define LIBCALL_VALUE(MODE) \ 687 s390_function_value (NULL, NULL, (MODE)) 688 689 /* Only gpr 2 and fpr 0 are ever used as return registers. */ 690 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 2 || (N) == 16) 691 692 693 /* Function entry and exit. */ 694 695 /* When returning from a function, the stack pointer does not matter. */ 696 #define EXIT_IGNORE_STACK 1 697 698 699 /* Profiling. */ 700 701 #define FUNCTION_PROFILER(FILE, LABELNO) \ 702 s390_function_profiler ((FILE), ((LABELNO))) 703 704 #define PROFILE_BEFORE_PROLOGUE 1 705 706 707 /* Trampolines for nested functions. */ 708 709 #define TRAMPOLINE_SIZE (TARGET_64BIT ? 32 : 16) 710 #define TRAMPOLINE_ALIGNMENT BITS_PER_WORD 711 712 /* Addressing modes, and classification of registers for them. */ 713 714 /* Recognize any constant value that is a valid address. */ 715 #define CONSTANT_ADDRESS_P(X) 0 716 717 /* Maximum number of registers that can appear in a valid memory address. */ 718 #define MAX_REGS_PER_ADDRESS 2 719 720 /* This definition replaces the formerly used 'm' constraint with a 721 different constraint letter in order to avoid changing semantics of 722 the 'm' constraint when accepting new address formats in 723 TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here 724 must not be used in insn definitions or inline assemblies. */ 725 #define TARGET_MEM_CONSTRAINT 'e' 726 727 /* Try a machine-dependent way of reloading an illegitimate address 728 operand. If we find one, push the reload and jump to WIN. This 729 macro is used in only one place: `find_reloads_address' in reload.c. */ 730 #define LEGITIMIZE_RELOAD_ADDRESS(AD, MODE, OPNUM, TYPE, IND, WIN) \ 731 do { \ 732 rtx new_rtx = legitimize_reload_address (AD, MODE, OPNUM, (int)(TYPE)); \ 733 if (new_rtx) \ 734 { \ 735 (AD) = new_rtx; \ 736 goto WIN; \ 737 } \ 738 } while (0) 739 740 /* Nonzero if the constant value X is a legitimate general operand. 741 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 742 #define LEGITIMATE_CONSTANT_P(X) \ 743 legitimate_constant_p (X) 744 745 /* Helper macro for s390.c and s390.md to check for symbolic constants. */ 746 #define SYMBOLIC_CONST(X) \ 747 (GET_CODE (X) == SYMBOL_REF \ 748 || GET_CODE (X) == LABEL_REF \ 749 || (GET_CODE (X) == CONST && symbolic_reference_mentioned_p (X))) 750 751 #define TLS_SYMBOLIC_CONST(X) \ 752 ((GET_CODE (X) == SYMBOL_REF && tls_symbolic_operand (X)) \ 753 || (GET_CODE (X) == CONST && tls_symbolic_reference_mentioned_p (X))) 754 755 756 /* Condition codes. */ 757 758 /* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 759 return the mode to be used for the comparison. */ 760 #define SELECT_CC_MODE(OP, X, Y) s390_select_ccmode ((OP), (X), (Y)) 761 762 /* Canonicalize a comparison from one we don't have to one we do have. */ 763 #define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 764 s390_canonicalize_comparison (&(CODE), &(OP0), &(OP1)) 765 766 /* Relative costs of operations. */ 767 768 /* On s390, copy between fprs and gprs is expensive. */ 769 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 770 (( ( reg_classes_intersect_p ((CLASS1), GENERAL_REGS) \ 771 && reg_classes_intersect_p ((CLASS2), FP_REGS)) \ 772 || ( reg_classes_intersect_p ((CLASS1), FP_REGS) \ 773 && reg_classes_intersect_p ((CLASS2), GENERAL_REGS))) ? 10 : 1) 774 775 /* A C expression for the cost of moving data of mode M between a 776 register and memory. A value of 2 is the default; this cost is 777 relative to those in `REGISTER_MOVE_COST'. */ 778 #define MEMORY_MOVE_COST(M, C, I) 1 779 780 /* A C expression for the cost of a branch instruction. A value of 1 781 is the default; other values are interpreted relative to that. */ 782 #define BRANCH_COST(speed_p, predictable_p) 1 783 784 /* Nonzero if access to memory by bytes is slow and undesirable. */ 785 #define SLOW_BYTE_ACCESS 1 786 787 /* An integer expression for the size in bits of the largest integer machine 788 mode that should actually be used. We allow pairs of registers. */ 789 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_64BIT ? TImode : DImode) 790 791 /* The maximum number of bytes that a single instruction can move quickly 792 between memory and registers or between two memory locations. */ 793 #define MOVE_MAX (TARGET_64BIT ? 16 : 8) 794 #define MOVE_MAX_PIECES (TARGET_64BIT ? 8 : 4) 795 #define MAX_MOVE_MAX 16 796 797 /* Determine whether to use move_by_pieces or block move insn. */ 798 #define MOVE_BY_PIECES_P(SIZE, ALIGN) \ 799 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ 800 || (TARGET_64BIT && (SIZE) == 8) ) 801 802 /* Determine whether to use clear_by_pieces or block clear insn. */ 803 #define CLEAR_BY_PIECES_P(SIZE, ALIGN) \ 804 ( (SIZE) == 1 || (SIZE) == 2 || (SIZE) == 4 \ 805 || (TARGET_64BIT && (SIZE) == 8) ) 806 807 /* This macro is used to determine whether store_by_pieces should be 808 called to "memcpy" storage when the source is a constant string. */ 809 #define STORE_BY_PIECES_P(SIZE, ALIGN) MOVE_BY_PIECES_P (SIZE, ALIGN) 810 811 /* Likewise to decide whether to "memset" storage with byte values 812 other than zero. */ 813 #define SET_BY_PIECES_P(SIZE, ALIGN) STORE_BY_PIECES_P (SIZE, ALIGN) 814 815 /* Don't perform CSE on function addresses. */ 816 #define NO_FUNCTION_CSE 817 818 /* This value is used in tree-sra to decide whether it might benefical 819 to split a struct move into several word-size moves. For S/390 820 only small values make sense here since struct moves are relatively 821 cheap thanks to mvc so the small default value choosen for archs 822 with memmove patterns should be ok. But this value is multiplied 823 in tree-sra with UNITS_PER_WORD to make a decision so we adjust it 824 here to compensate for that factor since mvc costs exactly the same 825 on 31 and 64 bit. */ 826 #define MOVE_RATIO(speed) (TARGET_64BIT? 2 : 4) 827 828 829 /* Sections. */ 830 831 /* Output before read-only data. */ 832 #define TEXT_SECTION_ASM_OP ".text" 833 834 /* Output before writable (initialized) data. */ 835 #define DATA_SECTION_ASM_OP ".data" 836 837 /* Output before writable (uninitialized) data. */ 838 #define BSS_SECTION_ASM_OP ".bss" 839 840 /* S/390 constant pool breaks the devices in crtstuff.c to control section 841 in where code resides. We have to write it as asm code. */ 842 #ifndef __s390x__ 843 #define CRT_CALL_STATIC_FUNCTION(SECTION_OP, FUNC) \ 844 asm (SECTION_OP "\n\ 845 bras\t%r2,1f\n\ 846 0: .long\t" USER_LABEL_PREFIX #FUNC " - 0b\n\ 847 1: l\t%r3,0(%r2)\n\ 848 bas\t%r14,0(%r3,%r2)\n\ 849 .previous"); 850 #endif 851 852 853 /* Position independent code. */ 854 855 extern int flag_pic; 856 857 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? 12 : INVALID_REGNUM) 858 859 #define LEGITIMATE_PIC_OPERAND_P(X) legitimate_pic_operand_p (X) 860 861 862 /* Assembler file format. */ 863 864 /* Character to start a comment. */ 865 #define ASM_COMMENT_START "#" 866 867 /* Declare an uninitialized external linkage data object. */ 868 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 869 asm_output_aligned_bss (FILE, DECL, NAME, SIZE, ALIGN) 870 871 /* Globalizing directive for a label. */ 872 #define GLOBAL_ASM_OP ".globl " 873 874 /* Advance the location counter to a multiple of 2**LOG bytes. */ 875 #define ASM_OUTPUT_ALIGN(FILE, LOG) \ 876 if ((LOG)) fprintf ((FILE), "\t.align\t%d\n", 1 << (LOG)) 877 878 /* Advance the location counter by SIZE bytes. */ 879 #define ASM_OUTPUT_SKIP(FILE, SIZE) \ 880 fprintf ((FILE), "\t.set\t.,.+"HOST_WIDE_INT_PRINT_UNSIGNED"\n", (SIZE)) 881 882 /* The LOCAL_LABEL_PREFIX variable is used by dbxelf.h. */ 883 #define LOCAL_LABEL_PREFIX "." 884 885 /* How to refer to registers in assembler output. This sequence is 886 indexed by compiler's hard-register-number (see above). */ 887 #define REGISTER_NAMES \ 888 { "%r0", "%r1", "%r2", "%r3", "%r4", "%r5", "%r6", "%r7", \ 889 "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15", \ 890 "%f0", "%f2", "%f4", "%f6", "%f1", "%f3", "%f5", "%f7", \ 891 "%f8", "%f10", "%f12", "%f14", "%f9", "%f11", "%f13", "%f15", \ 892 "%ap", "%cc", "%fp", "%rp", "%a0", "%a1" \ 893 } 894 895 /* Print operand X (an rtx) in assembler syntax to file FILE. */ 896 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 897 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 898 899 /* Output machine-dependent UNSPECs in address constants. */ 900 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 901 do { \ 902 if (!s390_output_addr_const_extra (FILE, (X))) \ 903 goto FAIL; \ 904 } while (0); 905 906 /* Output an element of a case-vector that is absolute. */ 907 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 908 do { \ 909 char buf[32]; \ 910 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ 911 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 912 assemble_name ((FILE), buf); \ 913 fputc ('\n', (FILE)); \ 914 } while (0) 915 916 /* Output an element of a case-vector that is relative. */ 917 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 918 do { \ 919 char buf[32]; \ 920 fputs (integer_asm_op (UNITS_PER_WORD, TRUE), (FILE)); \ 921 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (VALUE)); \ 922 assemble_name ((FILE), buf); \ 923 fputc ('-', (FILE)); \ 924 ASM_GENERATE_INTERNAL_LABEL (buf, "L", (REL)); \ 925 assemble_name ((FILE), buf); \ 926 fputc ('\n', (FILE)); \ 927 } while (0) 928 929 930 /* Miscellaneous parameters. */ 931 932 /* Specify the machine mode that this machine uses for the index in the 933 tablejump instruction. */ 934 #define CASE_VECTOR_MODE (TARGET_64BIT ? DImode : SImode) 935 936 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 937 is done just by pretending it is already truncated. */ 938 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 939 940 /* Specify the machine mode that pointers have. 941 After generation of rtl, the compiler makes no further distinction 942 between pointers and any other objects of this machine mode. */ 943 #define Pmode ((enum machine_mode) (TARGET_64BIT ? DImode : SImode)) 944 945 /* This is -1 for "pointer mode" extend. See ptr_extend in s390.md. */ 946 #define POINTERS_EXTEND_UNSIGNED -1 947 948 /* A function address in a call instruction is a byte address (for 949 indexing purposes) so give the MEM rtx a byte's mode. */ 950 #define FUNCTION_MODE QImode 951 952 /* Specify the value which is used when clz operand is zero. */ 953 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 64, 1) 954 955 /* Machine-specific symbol_ref flags. */ 956 #define SYMBOL_FLAG_ALIGN1 (SYMBOL_FLAG_MACH_DEP << 0) 957 #define SYMBOL_REF_ALIGN1_P(X) \ 958 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_ALIGN1)) 959 #define SYMBOL_FLAG_NOT_NATURALLY_ALIGNED (SYMBOL_FLAG_MACH_DEP << 1) 960 #define SYMBOL_REF_NOT_NATURALLY_ALIGNED_P(X) \ 961 ((SYMBOL_REF_FLAGS (X) & SYMBOL_FLAG_NOT_NATURALLY_ALIGNED)) 962 963 /* Check whether integer displacement is in range. */ 964 #define DISP_IN_RANGE(d) \ 965 (TARGET_LONG_DISPLACEMENT? ((d) >= -524288 && (d) <= 524287) \ 966 : ((d) >= 0 && (d) <= 4095)) 967 968 #endif 969