1 /* GCC backend definitions for the Renesas RX processor. 2 Copyright (C) 2008-2018 Free Software Foundation, Inc. 3 Contributed by Red Hat. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 #define TARGET_CPU_CPP_BUILTINS() \ 23 do \ 24 { \ 25 builtin_define ("__RX__"); \ 26 builtin_assert ("cpu=RX"); \ 27 if (rx_cpu_type == RX610) \ 28 { \ 29 builtin_define ("__RX610__"); \ 30 builtin_assert ("machine=RX610"); \ 31 } \ 32 else if (rx_cpu_type == RX100) \ 33 { \ 34 builtin_define ("__RX100__"); \ 35 builtin_assert ("machine=RX100"); \ 36 } \ 37 else if (rx_cpu_type == RX200) \ 38 { \ 39 builtin_define ("__RX200__"); \ 40 builtin_assert ("machine=RX200"); \ 41 } \ 42 else if (rx_cpu_type == RX600) \ 43 { \ 44 builtin_define ("__RX600__"); \ 45 builtin_assert ("machine=RX600"); \ 46 } \ 47 \ 48 if (TARGET_BIG_ENDIAN_DATA) \ 49 builtin_define ("__RX_BIG_ENDIAN__"); \ 50 else \ 51 builtin_define ("__RX_LITTLE_ENDIAN__");\ 52 \ 53 if (TARGET_64BIT_DOUBLES) \ 54 builtin_define ("__RX_64BIT_DOUBLES__");\ 55 else \ 56 builtin_define ("__RX_32BIT_DOUBLES__");\ 57 \ 58 if (ALLOW_RX_FPU_INSNS) \ 59 builtin_define ("__RX_FPU_INSNS__"); \ 60 \ 61 if (TARGET_AS100_SYNTAX) \ 62 builtin_define ("__RX_AS100_SYNTAX__"); \ 63 else \ 64 builtin_define ("__RX_GAS_SYNTAX__"); \ 65 \ 66 if (TARGET_GCC_ABI) \ 67 builtin_define ("__RX_GCC_ABI__"); \ 68 else \ 69 builtin_define ("__RX_ABI__"); \ 70 \ 71 if (rx_allow_string_insns) \ 72 builtin_define ("__RX_ALLOW_STRING_INSNS__"); \ 73 else \ 74 builtin_define ("__RX_DISALLOW_STRING_INSNS__");\ 75 } \ 76 while (0) 77 78 #undef CC1_SPEC 79 #define CC1_SPEC "\ 80 %{mas100-syntax:%{gdwarf*:%e-mas100-syntax is incompatible with -gdwarf}} \ 81 %{mcpu=rx100:%{fpu:%erx100 cpu does not have FPU hardware}} \ 82 %{mcpu=rx200:%{fpu:%erx200 cpu does not have FPU hardware}}" 83 84 #undef STARTFILE_SPEC 85 #define STARTFILE_SPEC "%{pg:gcrt0.o%s}%{!pg:crt0.o%s} crtbegin.o%s" 86 87 #undef ENDFILE_SPEC 88 #define ENDFILE_SPEC "crtend.o%s crtn.o%s" 89 90 #undef CPP_SPEC 91 #define CPP_SPEC "\ 92 %{mpid:-D_RX_PID=1} \ 93 %{mint-register=*:-D_RX_INT_REGISTERS=%*} \ 94 %{msmall-data-limit*:-D_RX_SMALL_DATA} \ 95 " 96 97 #undef ASM_SPEC 98 #define ASM_SPEC "\ 99 %{mbig-endian-data:-mbig-endian-data} \ 100 %{m64bit-doubles:-m64bit-doubles} \ 101 %{!m64bit-doubles:-m32bit-doubles} \ 102 %{msmall-data-limit*:-msmall-data-limit} \ 103 %{mrelax:-relax} \ 104 %{mpid} \ 105 %{mno-allow-string-insns} \ 106 %{mint-register=*} \ 107 %{mgcc-abi:-mgcc-abi} %{!mgcc-abi:-mrx-abi} \ 108 %{mcpu=*} \ 109 " 110 111 #undef LIB_SPEC 112 #define LIB_SPEC " \ 113 --start-group \ 114 -lc \ 115 %{msim:-lsim}%{!msim:-lnosys} \ 116 %{fprofile-arcs|fprofile-generate|coverage:-lgcov} \ 117 --end-group \ 118 %{!T*: %{msim:%Trx-sim.ld}%{!msim:%Trx.ld}} \ 119 " 120 121 #undef LINK_SPEC 122 #define LINK_SPEC "%{mbig-endian-data:--oformat elf32-rx-be} %{mrelax:-relax}" 123 124 125 #define BITS_BIG_ENDIAN 0 126 #define BYTES_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA 127 #define WORDS_BIG_ENDIAN TARGET_BIG_ENDIAN_DATA 128 129 #define UNITS_PER_WORD 4 130 131 #define INT_TYPE_SIZE 32 132 #define LONG_TYPE_SIZE 32 133 #define LONG_LONG_TYPE_SIZE 64 134 135 #define FLOAT_TYPE_SIZE 32 136 #define DOUBLE_TYPE_SIZE (TARGET_64BIT_DOUBLES ? 64 : 32) 137 #define LONG_DOUBLE_TYPE_SIZE DOUBLE_TYPE_SIZE 138 139 #define DEFAULT_SIGNED_CHAR 0 140 141 /* RX load/store instructions can handle unaligned addresses. */ 142 #define STRICT_ALIGNMENT 0 143 #define FUNCTION_BOUNDARY ((rx_cpu_type == RX100 || rx_cpu_type == RX200) ? 4 : 8) 144 #define BIGGEST_ALIGNMENT 32 145 #define STACK_BOUNDARY 32 146 #define PARM_BOUNDARY 8 147 148 #define STACK_GROWS_DOWNWARD 1 149 #define FRAME_GROWS_DOWNWARD 0 150 #define FIRST_PARM_OFFSET(FNDECL) 0 151 152 #define MAX_REGS_PER_ADDRESS 2 153 154 #define Pmode SImode 155 #define POINTER_SIZE 32 156 #undef SIZE_TYPE 157 #define SIZE_TYPE "long unsigned int" 158 #undef PTRDIFF_TYPE 159 #define PTRDIFF_TYPE "long int" 160 #undef WCHAR_TYPE 161 #define WCHAR_TYPE "long int" 162 #undef WCHAR_TYPE_SIZE 163 #define WCHAR_TYPE_SIZE BITS_PER_WORD 164 #define POINTERS_EXTEND_UNSIGNED 1 165 #define FUNCTION_MODE QImode 166 #define CASE_VECTOR_MODE Pmode 167 #define WORD_REGISTER_OPERATIONS 1 168 #define HAS_LONG_COND_BRANCH 0 169 #define HAS_LONG_UNCOND_BRANCH 0 170 171 #define MOVE_MAX 4 172 173 #define HAVE_PRE_DECREMENT 1 174 #define HAVE_POST_INCREMENT 1 175 176 #define MOVE_RATIO(SPEED) ((SPEED) ? 4 : 2) 177 #define SLOW_BYTE_ACCESS 1 178 179 #define STORE_FLAG_VALUE 1 180 #define LOAD_EXTEND_OP(MODE) SIGN_EXTEND 181 #define SHORT_IMMEDIATES_SIGN_EXTEND 1 182 183 enum reg_class 184 { 185 NO_REGS, /* No registers in set. */ 186 GR_REGS, /* Integer registers. */ 187 ALL_REGS, /* All registers. */ 188 LIM_REG_CLASSES /* Max value + 1. */ 189 }; 190 191 #define REG_CLASS_NAMES \ 192 { \ 193 "NO_REGS", \ 194 "GR_REGS", \ 195 "ALL_REGS" \ 196 } 197 198 #define REG_CLASS_CONTENTS \ 199 { \ 200 { 0x00000000 }, /* No registers, */ \ 201 { 0x0000ffff }, /* Integer registers. */ \ 202 { 0x0000ffff } /* All registers. */ \ 203 } 204 205 #define N_REG_CLASSES (int) LIM_REG_CLASSES 206 #define CLASS_MAX_NREGS(CLASS, MODE) ((GET_MODE_SIZE (MODE) \ 207 + UNITS_PER_WORD - 1) \ 208 / UNITS_PER_WORD) 209 210 #define GENERAL_REGS GR_REGS 211 #define BASE_REG_CLASS GR_REGS 212 #define INDEX_REG_CLASS GR_REGS 213 214 #define FIRST_PSEUDO_REGISTER 17 215 216 #define REGNO_REG_CLASS(REGNO) ((REGNO) < FIRST_PSEUDO_REGISTER \ 217 ? GR_REGS : NO_REGS) 218 219 #define STACK_POINTER_REGNUM 0 220 #define FUNC_RETURN_REGNUM 1 221 #define FRAME_POINTER_REGNUM 6 222 #define ARG_POINTER_REGNUM 7 223 #define STATIC_CHAIN_REGNUM 8 224 #define TRAMPOLINE_TEMP_REGNUM 9 225 #define STRUCT_VAL_REGNUM 15 226 #define CC_REGNUM 16 227 228 /* This is the register which will probably be used to hold the address of 229 the start of the small data area, if -msmall-data-limit is being used, 230 or the address of the constant data area if -mpid is being used. If both 231 features are in use then two consecutive registers will be used. 232 233 Note - these registers must not be call_used because otherwise library 234 functions that are compiled without -msmall-data-limit/-mpid support 235 might clobber them. 236 237 Note that the actual values used depends on other options; use 238 rx_gp_base_regnum() and rx_pid_base_regnum() instead. */ 239 #define GP_BASE_REGNUM 13 240 241 #define ELIMINABLE_REGS \ 242 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 243 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ 244 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }} 245 246 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 247 (OFFSET) = rx_initial_elimination_offset ((FROM), (TO)) 248 249 250 #define FUNCTION_ARG_REGNO_P(N) (((N) >= 1) && ((N) <= 4)) 251 #define FUNCTION_VALUE_REGNO_P(N) ((N) == FUNC_RETURN_REGNUM) 252 #define DEFAULT_PCC_STRUCT_RETURN 0 253 254 #define FIXED_REGISTERS \ 255 { \ 256 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 1 \ 257 } 258 259 #define CALL_USED_REGISTERS \ 260 { \ 261 1, 1, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1 \ 262 } 263 264 #define LIBCALL_VALUE(MODE) \ 265 gen_rtx_REG (((GET_MODE_CLASS (MODE) != MODE_INT \ 266 || COMPLEX_MODE_P (MODE) \ 267 || VECTOR_MODE_P (MODE) \ 268 || GET_MODE_SIZE (MODE) >= 4) \ 269 ? (MODE) \ 270 : SImode), \ 271 FUNC_RETURN_REGNUM) 272 273 /* Order of allocation of registers. */ 274 275 #define REG_ALLOC_ORDER \ 276 { 7, 10, 11, 12, 13, 14, 4, 3, 2, 1, 9, 8, 6, 5, 15 \ 277 } 278 279 #define REGNO_IN_RANGE(REGNO, MIN, MAX) \ 280 (IN_RANGE ((REGNO), (MIN), (MAX)) \ 281 || (reg_renumber != NULL \ 282 && reg_renumber[(REGNO)] >= (MIN) \ 283 && reg_renumber[(REGNO)] <= (MAX))) 284 285 #ifdef REG_OK_STRICT 286 #define REGNO_OK_FOR_BASE_P(regno) REGNO_IN_RANGE (regno, 0, 15) 287 #else 288 #define REGNO_OK_FOR_BASE_P(regno) 1 289 #endif 290 291 #define REGNO_OK_FOR_INDEX_P(regno) REGNO_OK_FOR_BASE_P (regno) 292 293 #define RTX_OK_FOR_BASE(X, STRICT) \ 294 ((STRICT) ? \ 295 ( (REG_P (X) \ 296 && REGNO_IN_RANGE (REGNO (X), 0, 15)) \ 297 || (GET_CODE (X) == SUBREG \ 298 && REG_P (SUBREG_REG (X)) \ 299 && REGNO_IN_RANGE (REGNO (SUBREG_REG (X)), 0, 15))) \ 300 : \ 301 ( (REG_P (X) \ 302 || (GET_CODE (X) == SUBREG \ 303 && REG_P (SUBREG_REG (X)))))) 304 305 306 #define RETURN_ADDR_RTX(COUNT, FRAMEADDR) \ 307 ((COUNT) == 0 \ 308 ? gen_rtx_MEM (Pmode, gen_rtx_PLUS (Pmode, arg_pointer_rtx, GEN_INT (-4))) \ 309 : NULL_RTX) 310 311 #define INCOMING_RETURN_ADDR_RTX gen_rtx_MEM (Pmode, stack_pointer_rtx) 312 313 #define ACCUMULATE_OUTGOING_ARGS 1 314 315 typedef unsigned int CUMULATIVE_ARGS; 316 317 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 318 (CUM) = 0 319 320 321 #define TRAMPOLINE_SIZE (! TARGET_BIG_ENDIAN_DATA ? 14 : 20) 322 #define TRAMPOLINE_ALIGNMENT 32 323 324 #define NO_PROFILE_COUNTERS 1 325 #define PROFILE_BEFORE_PROLOGUE 1 326 327 #define FUNCTION_PROFILER(FILE, LABELNO) \ 328 fprintf (FILE, "\tbsr\t__mcount\n"); 329 330 331 #define REGISTER_NAMES \ 332 { \ 333 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 334 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", "cc" \ 335 } 336 337 #define ADDITIONAL_REGISTER_NAMES \ 338 { \ 339 { "sp", STACK_POINTER_REGNUM } \ 340 , { "fp", FRAME_POINTER_REGNUM } \ 341 , { "arg", ARG_POINTER_REGNUM } \ 342 , { "chain", STATIC_CHAIN_REGNUM } \ 343 } 344 345 #define DATA_SECTION_ASM_OP \ 346 (TARGET_AS100_SYNTAX ? "\t.SECTION D,DATA" \ 347 : "\t.section D,\"aw\",@progbits\n\t.p2align 2") 348 349 #define SDATA_SECTION_ASM_OP \ 350 (TARGET_AS100_SYNTAX ? "\t.SECTION D_2,DATA,ALIGN=2" \ 351 : "\t.section D_2,\"aw\",@progbits\n\t.p2align 1") 352 353 #undef READONLY_DATA_SECTION_ASM_OP 354 #define READONLY_DATA_SECTION_ASM_OP \ 355 (TARGET_AS100_SYNTAX ? "\t.SECTION C,ROMDATA,ALIGN=4" \ 356 : "\t.section C,\"a\",@progbits\n\t.p2align 2") 357 358 #define BSS_SECTION_ASM_OP \ 359 (TARGET_AS100_SYNTAX ? "\t.SECTION B,DATA,ALIGN=4" \ 360 : "\t.section B,\"w\",@nobits\n\t.p2align 2") 361 362 #define SBSS_SECTION_ASM_OP \ 363 (TARGET_AS100_SYNTAX ? "\t.SECTION B_2,DATA,ALIGN=2" \ 364 : "\t.section B_2,\"w\",@nobits\n\t.p2align 1") 365 366 /* The following definitions are conditional depending upon whether the 367 compiler is being built or crtstuff.c is being compiled by the built 368 compiler. */ 369 #if defined CRT_BEGIN || defined CRT_END 370 # ifdef __RX_AS100_SYNTAX 371 # define TEXT_SECTION_ASM_OP "\t.SECTION P,CODE" 372 # define CTORS_SECTION_ASM_OP "\t.SECTION init_array,CODE" 373 # define DTORS_SECTION_ASM_OP "\t.SECTION fini_array,CODE" 374 # define INIT_ARRAY_SECTION_ASM_OP "\t.SECTION init_array,CODE" 375 # define FINI_ARRAY_SECTION_ASM_OP "\t.SECTION fini_array,CODE" 376 # else 377 # define TEXT_SECTION_ASM_OP "\t.section P,\"ax\"" 378 # define CTORS_SECTION_ASM_OP \ 379 "\t.section\t.init_array,\"awx\",@init_array" 380 # define DTORS_SECTION_ASM_OP \ 381 "\t.section\t.fini_array,\"awx\",@fini_array" 382 # define INIT_ARRAY_SECTION_ASM_OP \ 383 "\t.section\t.init_array,\"awx\",@init_array" 384 # define FINI_ARRAY_SECTION_ASM_OP \ 385 "\t.section\t.fini_array,\"awx\",@fini_array" 386 # endif 387 #else 388 # define TEXT_SECTION_ASM_OP \ 389 (TARGET_AS100_SYNTAX ? "\t.SECTION P,CODE" : "\t.section P,\"ax\"") 390 391 # define CTORS_SECTION_ASM_OP \ 392 (TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \ 393 : "\t.section\t.init_array,\"awx\",@init_array") 394 395 # define DTORS_SECTION_ASM_OP \ 396 (TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \ 397 : "\t.section\t.fini_array,\"awx\",@fini_array") 398 399 # define INIT_ARRAY_SECTION_ASM_OP \ 400 (TARGET_AS100_SYNTAX ? "\t.SECTION init_array,CODE" \ 401 : "\t.section\t.init_array,\"awx\",@init_array") 402 403 # define FINI_ARRAY_SECTION_ASM_OP \ 404 (TARGET_AS100_SYNTAX ? "\t.SECTION fini_array,CODE" \ 405 : "\t.section\t.fini_array,\"awx\",@fini_array") 406 #endif 407 408 #define GLOBAL_ASM_OP \ 409 (TARGET_AS100_SYNTAX ? "\t.GLB\t" : "\t.global\t") 410 #define ASM_COMMENT_START " ;" 411 #define ASM_APP_ON "" 412 #define ASM_APP_OFF "" 413 #define LOCAL_LABEL_PREFIX "L" 414 #undef USER_LABEL_PREFIX 415 #define USER_LABEL_PREFIX "_" 416 417 /* Compute the alignment needed for label X in various situations. 418 If the user has specified an alignment then honour that, otherwise 419 use rx_align_for_label. */ 420 #define JUMP_ALIGN(x) (align_jumps > 1 ? align_jumps_log : rx_align_for_label (x, 0)) 421 #define LABEL_ALIGN(x) (align_labels > 1 ? align_labels_log : rx_align_for_label (x, 3)) 422 #define LOOP_ALIGN(x) (align_loops > 1 ? align_loops_log : rx_align_for_label (x, 2)) 423 #define LABEL_ALIGN_AFTER_BARRIER(x) rx_align_for_label (x, 0) 424 425 #define ASM_OUTPUT_MAX_SKIP_ALIGN(STREAM, LOG, MAX_SKIP) \ 426 do \ 427 { \ 428 if ((LOG) == 0 || (MAX_SKIP) == 0) \ 429 break; \ 430 if (TARGET_AS100_SYNTAX) \ 431 { \ 432 if ((LOG) >= 2) \ 433 fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \ 434 else \ 435 fprintf (STREAM, "\t.ALIGN 2\n"); \ 436 } \ 437 else \ 438 fprintf (STREAM, "\t.balign %d,3,%d\n", 1 << (LOG), (MAX_SKIP)); \ 439 } \ 440 while (0) 441 442 #define ASM_OUTPUT_ALIGN(STREAM, LOG) \ 443 do \ 444 { \ 445 if ((LOG) == 0) \ 446 break; \ 447 if (TARGET_AS100_SYNTAX) \ 448 { \ 449 if ((LOG) >= 2) \ 450 fprintf (STREAM, "\t.ALIGN 4\t; %d alignment actually requested\n", 1 << (LOG)); \ 451 else \ 452 fprintf (STREAM, "\t.ALIGN 2\n"); \ 453 } \ 454 else \ 455 fprintf (STREAM, "\t.balign %d\n", 1 << (LOG)); \ 456 } \ 457 while (0) 458 459 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 460 fprintf (FILE, TARGET_AS100_SYNTAX ? "\t.LWORD L%d\n" : "\t.long .L%d\n", \ 461 VALUE) 462 463 /* This is how to output an element of a case-vector that is relative. 464 Note: The local label referenced by the "1b" below is emitted by 465 the tablejump insn. */ 466 467 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 468 fprintf (FILE, TARGET_AS100_SYNTAX \ 469 ? "\t.LWORD L%d - ?-\n" : "\t.long .L%d - 1b\n", VALUE) 470 471 #define CASE_VECTOR_PC_RELATIVE (TARGET_PID) 472 473 #define ASM_OUTPUT_SIZE_DIRECTIVE(STREAM, NAME, SIZE) \ 474 do \ 475 { \ 476 HOST_WIDE_INT size_ = (SIZE); \ 477 \ 478 /* The as100 assembler does not have an equivalent of the SVR4 \ 479 .size pseudo-op. */ \ 480 if (TARGET_AS100_SYNTAX) \ 481 break; \ 482 \ 483 fputs (SIZE_ASM_OP, STREAM); \ 484 assemble_name (STREAM, NAME); \ 485 fprintf (STREAM, ", " HOST_WIDE_INT_PRINT_DEC "\n", size_); \ 486 } \ 487 while (0) 488 489 #define ASM_OUTPUT_MEASURED_SIZE(STREAM, NAME) \ 490 do \ 491 { \ 492 /* The as100 assembler does not have an equivalent of the SVR4 \ 493 .size pseudo-op. */ \ 494 if (TARGET_AS100_SYNTAX) \ 495 break; \ 496 fputs (SIZE_ASM_OP, STREAM); \ 497 assemble_name (STREAM, NAME); \ 498 fputs (", .-", STREAM); \ 499 assemble_name (STREAM, NAME); \ 500 putc ('\n', STREAM); \ 501 } \ 502 while (0) 503 504 #define ASM_OUTPUT_TYPE_DIRECTIVE(STREAM, NAME, TYPE) \ 505 do \ 506 { \ 507 /* The as100 assembler does not have an equivalent of the SVR4 \ 508 .size pseudo-op. */ \ 509 if (TARGET_AS100_SYNTAX) \ 510 break; \ 511 fputs (TYPE_ASM_OP, STREAM); \ 512 assemble_name (STREAM, NAME); \ 513 fputs (", ", STREAM); \ 514 fprintf (STREAM, TYPE_OPERAND_FMT, TYPE); \ 515 putc ('\n', STREAM); \ 516 } \ 517 while (0) 518 519 #undef ASM_GENERATE_INTERNAL_LABEL 520 #define ASM_GENERATE_INTERNAL_LABEL(LABEL, PREFIX, NUM) \ 521 do \ 522 { \ 523 sprintf (LABEL, TARGET_AS100_SYNTAX ? "*%s%u" : "*.%s%u", \ 524 PREFIX, (unsigned) (NUM)); \ 525 } \ 526 while (0) 527 528 #undef ASM_OUTPUT_EXTERNAL 529 #define ASM_OUTPUT_EXTERNAL(FILE, DECL, NAME) \ 530 do \ 531 { \ 532 if (TARGET_AS100_SYNTAX) \ 533 targetm.asm_out.globalize_label (FILE, NAME); \ 534 default_elf_asm_output_external (FILE, DECL, NAME); \ 535 } \ 536 while (0) 537 538 #undef ASM_OUTPUT_ALIGNED_COMMON 539 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 540 do \ 541 { \ 542 if (TARGET_AS100_SYNTAX) \ 543 { \ 544 fprintf ((FILE), "\t.GLB\t"); \ 545 assemble_name ((FILE), (NAME)); \ 546 fprintf ((FILE), "\n"); \ 547 assemble_name ((FILE), (NAME)); \ 548 switch ((ALIGN) / BITS_PER_UNIT) \ 549 { \ 550 case 4: \ 551 fprintf ((FILE), ":\t.BLKL\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n",\ 552 (SIZE) / 4); \ 553 break; \ 554 case 2: \ 555 fprintf ((FILE), ":\t.BLKW\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n",\ 556 (SIZE) / 2); \ 557 break; \ 558 default: \ 559 fprintf ((FILE), ":\t.BLKB\t" HOST_WIDE_INT_PRINT_UNSIGNED"\n",\ 560 (SIZE)); \ 561 break; \ 562 } \ 563 } \ 564 else \ 565 { \ 566 fprintf ((FILE), "%s", COMMON_ASM_OP); \ 567 assemble_name ((FILE), (NAME)); \ 568 fprintf ((FILE), "," HOST_WIDE_INT_PRINT_UNSIGNED",%u\n", \ 569 (SIZE), (ALIGN) / BITS_PER_UNIT); \ 570 } \ 571 } \ 572 while (0) 573 574 #undef SKIP_ASM_OP 575 #define SKIP_ASM_OP (TARGET_AS100_SYNTAX ? "\t.BLKB\t" : "\t.zero\t") 576 577 #undef ASM_OUTPUT_LIMITED_STRING 578 #define ASM_OUTPUT_LIMITED_STRING(FILE, STR) \ 579 do \ 580 { \ 581 const unsigned char *_limited_str = \ 582 (const unsigned char *) (STR); \ 583 unsigned ch; \ 584 \ 585 fprintf ((FILE), TARGET_AS100_SYNTAX \ 586 ? "\t.BYTE\t\"" : "\t.string\t\""); \ 587 \ 588 for (; (ch = *_limited_str); _limited_str++) \ 589 { \ 590 int escape; \ 591 \ 592 switch (escape = ESCAPES[ch]) \ 593 { \ 594 case 0: \ 595 putc (ch, (FILE)); \ 596 break; \ 597 case 1: \ 598 fprintf ((FILE), "\\%03o", ch); \ 599 break; \ 600 default: \ 601 putc ('\\', (FILE)); \ 602 putc (escape, (FILE)); \ 603 break; \ 604 } \ 605 } \ 606 \ 607 fprintf ((FILE), TARGET_AS100_SYNTAX ? "\"\n\t.BYTE\t0\n" : "\"\n");\ 608 } \ 609 while (0) 610 611 /* For PIC put jump tables into the text section so that the offsets that 612 they contain are always computed between two same-section symbols. */ 613 #define JUMP_TABLES_IN_TEXT_SECTION (TARGET_PID || flag_pic) 614 615 /* This is a version of REG_P that also returns TRUE for SUBREGs. */ 616 #define RX_REG_P(rtl) (REG_P (rtl) || GET_CODE (rtl) == SUBREG) 617 618 /* Like REG_P except that this macro is true for SET expressions. */ 619 #define SET_P(rtl) (GET_CODE (rtl) == SET) 620 621 /* The AS100 assembler does not support .leb128 and .uleb128, but 622 the compiler-build-time configure tests will have enabled their 623 use because GAS supports them. So default to generating STABS 624 debug information instead of DWARF2 when generating AS100 625 compatible output. */ 626 #undef PREFERRED_DEBUGGING_TYPE 627 #define PREFERRED_DEBUGGING_TYPE (TARGET_AS100_SYNTAX \ 628 ? DBX_DEBUG : DWARF2_DEBUG) 629 630 #define INCOMING_FRAME_SP_OFFSET 4 631 #define ARG_POINTER_CFA_OFFSET(FNDECL) 4 632 633 #define TARGET_USE_FPU (! TARGET_NO_USE_FPU) 634 635 /* This macro is used to decide when RX FPU instructions can be used. */ 636 #define ALLOW_RX_FPU_INSNS (TARGET_USE_FPU) 637 638 #define BRANCH_COST(SPEED,PREDICT) 1 639 #define REGISTER_MOVE_COST(MODE,FROM,TO) 2 640 641 #define SELECT_CC_MODE(OP,X,Y) rx_select_cc_mode(OP, X, Y) 642 643 #define ADJUST_INSN_LENGTH(INSN,LENGTH) \ 644 do \ 645 { \ 646 (LENGTH) = rx_adjust_insn_length ((INSN), (LENGTH)); \ 647 } \ 648 while (0) 649