1; Options for the rs6000 port of the compiler 2; 3; Copyright (C) 2005-2015 Free Software Foundation, Inc. 4; Contributed by Aldy Hernandez <aldy@quesejoda.com>. 5; 6; This file is part of GCC. 7; 8; GCC is free software; you can redistribute it and/or modify it under 9; the terms of the GNU General Public License as published by the Free 10; Software Foundation; either version 3, or (at your option) any later 11; version. 12; 13; GCC is distributed in the hope that it will be useful, but WITHOUT 14; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16; License for more details. 17; 18; You should have received a copy of the GNU General Public License 19; along with GCC; see the file COPYING3. If not see 20; <http://www.gnu.org/licenses/>. 21 22HeaderInclude 23config/rs6000/rs6000-opts.h 24 25;; ISA flag bits (on/off) 26Variable 27HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT 28 29TargetSave 30HOST_WIDE_INT x_rs6000_isa_flags 31 32;; Miscellaneous flag bits that were set explicitly by the user 33TargetSave 34HOST_WIDE_INT x_rs6000_isa_flags_explicit 35 36;; Current processor 37TargetVariable 38enum processor_type rs6000_cpu = PROCESSOR_PPC603 39 40;; Always emit branch hint bits. 41TargetVariable 42unsigned char rs6000_always_hint 43 44;; Schedule instructions for group formation. 45TargetVariable 46unsigned char rs6000_sched_groups 47 48;; Align branch targets. 49TargetVariable 50unsigned char rs6000_align_branch_targets 51 52;; Support for -msched-costly-dep option. 53TargetVariable 54enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly 55 56;; Support for -minsert-sched-nops option. 57TargetVariable 58enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none 59 60;; Non-zero to allow overriding loop alignment. 61TargetVariable 62unsigned char can_override_loop_align 63 64;; Which small data model to use (for System V targets only) 65TargetVariable 66enum rs6000_sdata_type rs6000_sdata = SDATA_DATA 67 68;; Bit size of immediate TLS offsets and string from which it is decoded. 69TargetVariable 70int rs6000_tls_size = 32 71 72;; ABI enumeration available for subtarget to use. 73TargetVariable 74enum rs6000_abi rs6000_current_abi = ABI_NONE 75 76;; Type of traceback to use. 77TargetVariable 78enum rs6000_traceback_type rs6000_traceback = traceback_default 79 80;; Control alignment for fields within structures. 81TargetVariable 82unsigned char rs6000_alignment_flags 83 84;; Code model for 64-bit linux. 85TargetVariable 86enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL 87 88;; What type of reciprocal estimation instructions to generate 89TargetVariable 90unsigned int rs6000_recip_control 91 92;; Mask of what builtin functions are allowed 93TargetVariable 94HOST_WIDE_INT rs6000_builtin_mask 95 96;; Debug flags 97TargetVariable 98unsigned int rs6000_debug 99 100;; This option existed in the past, but now is always on. 101mpowerpc 102Target RejectNegative Undocumented Ignore 103 104mpowerpc64 105Target Report Mask(POWERPC64) Var(rs6000_isa_flags) 106Use PowerPC-64 instruction set 107 108mpowerpc-gpopt 109Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) 110Use PowerPC General Purpose group optional instructions 111 112mpowerpc-gfxopt 113Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) 114Use PowerPC Graphics group optional instructions 115 116mmfcrf 117Target Report Mask(MFCRF) Var(rs6000_isa_flags) 118Use PowerPC V2.01 single field mfcr instruction 119 120mpopcntb 121Target Report Mask(POPCNTB) Var(rs6000_isa_flags) 122Use PowerPC V2.02 popcntb instruction 123 124mfprnd 125Target Report Mask(FPRND) Var(rs6000_isa_flags) 126Use PowerPC V2.02 floating point rounding instructions 127 128mcmpb 129Target Report Mask(CMPB) Var(rs6000_isa_flags) 130Use PowerPC V2.05 compare bytes instruction 131 132mmfpgpr 133Target Report Mask(MFPGPR) Var(rs6000_isa_flags) 134Use extended PowerPC V2.05 move floating point to/from GPR instructions 135 136maltivec 137Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) 138Use AltiVec instructions 139 140maltivec=le 141Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save 142Generate Altivec instructions using little-endian element order 143 144maltivec=be 145Target Report RejectNegative Var(rs6000_altivec_element_order, 2) 146Generate Altivec instructions using big-endian element order 147 148mhard-dfp 149Target Report Mask(DFP) Var(rs6000_isa_flags) 150Use decimal floating point instructions 151 152mmulhw 153Target Report Mask(MULHW) Var(rs6000_isa_flags) 154Use 4xx half-word multiply instructions 155 156mdlmzb 157Target Report Mask(DLMZB) Var(rs6000_isa_flags) 158Use 4xx string-search dlmzb instruction 159 160mmultiple 161Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) 162Generate load/store multiple instructions 163 164mstring 165Target Report Mask(STRING) Var(rs6000_isa_flags) 166Generate string instructions for block moves 167 168msoft-float 169Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) 170Do not use hardware floating point 171 172mhard-float 173Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) 174Use hardware floating point 175 176mpopcntd 177Target Report Mask(POPCNTD) Var(rs6000_isa_flags) 178Use PowerPC V2.06 popcntd instruction 179 180mfriz 181Target Report Var(TARGET_FRIZ) Init(-1) Save 182Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions 183 184mveclibabi= 185Target RejectNegative Joined Var(rs6000_veclibabi_name) 186Vector library ABI to use 187 188mvsx 189Target Report Mask(VSX) Var(rs6000_isa_flags) 190Use vector/scalar (VSX) instructions 191 192mvsx-scalar-float 193Target Undocumented Report Var(TARGET_VSX_SCALAR_FLOAT) Init(1) 194; If -mpower8-vector, use VSX arithmetic instructions for SFmode (on by default) 195 196mvsx-scalar-double 197Target Undocumented Report Var(TARGET_VSX_SCALAR_DOUBLE) Init(1) 198; If -mvsx, use VSX arithmetic instructions for DFmode (on by default) 199 200mvsx-scalar-memory 201Target Undocumented Report Alias(mupper-regs-df) 202 203mvsx-align-128 204Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save 205; If -mvsx, set alignment to 128 bits instead of 32/64 206 207mallow-movmisalign 208Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save 209; Allow/disallow the movmisalign in DF/DI vectors 210 211mefficient-unaligned-vector 212Target Undocumented Report Var(TARGET_EFFICIENT_UNALIGNED_VSX) Init(-1) Save 213; Consider unaligned VSX accesses to be efficient/inefficient 214 215mallow-df-permute 216Target Undocumented Var(TARGET_ALLOW_DF_PERMUTE) Save 217; Allow/disallow permutation of DF/DI vectors 218 219msched-groups 220Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save 221; Explicitly set/unset whether rs6000_sched_groups is set 222 223malways-hint 224Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save 225; Explicitly set/unset whether rs6000_always_hint is set 226 227malign-branch-targets 228Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save 229; Explicitly set/unset whether rs6000_align_branch_targets is set 230 231mvectorize-builtins 232Target Undocumented Report Var(TARGET_VECTORIZE_BUILTINS) Init(-1) Save 233; Explicitly control whether we vectorize the builtins or not. 234 235mno-update 236Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) 237Do not generate load/store with update instructions 238 239mupdate 240Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) 241Generate load/store with update instructions 242 243msingle-pic-base 244Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) 245Do not load the PIC register in function prologues 246 247mavoid-indexed-addresses 248Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save 249Avoid generation of indexed load/store instructions when possible 250 251mtls-markers 252Target Report Var(tls_markers) Init(1) Save 253Mark __tls_get_addr calls with argument info 254 255msched-epilog 256Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save 257 258msched-prolog 259Target Report Var(TARGET_SCHED_PROLOG) Save 260Schedule the start and end of the procedure 261 262maix-struct-return 263Target Report RejectNegative Var(aix_struct_return) Save 264Return all structures in memory (AIX default) 265 266msvr4-struct-return 267Target Report RejectNegative Var(aix_struct_return,0) Save 268Return small structures in registers (SVR4 default) 269 270mxl-compat 271Target Report Var(TARGET_XL_COMPAT) Save 272Conform more closely to IBM XLC semantics 273 274mrecip 275Target Report 276Generate software reciprocal divide and square root for better throughput. 277 278mrecip= 279Target Report RejectNegative Joined Var(rs6000_recip_name) 280Generate software reciprocal divide and square root for better throughput. 281 282mrecip-precision 283Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) 284Assume that the reciprocal estimate instructions provide more accuracy. 285 286mno-fp-in-toc 287Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save 288Do not place floating point constants in TOC 289 290mfp-in-toc 291Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save 292Place floating point constants in TOC 293 294mno-sum-in-toc 295Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save 296Do not place symbol+offset constants in TOC 297 298msum-in-toc 299Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save 300Place symbol+offset constants in TOC 301 302; Output only one TOC entry per module. Normally linking fails if 303; there are more than 16K unique variables/constants in an executable. With 304; this option, linking fails only if there are more than 16K modules, or 305; if there are more than 16K unique variables/constant in a single module. 306; 307; This is at the cost of having 2 extra loads and one extra store per 308; function, and one less allocable register. 309mminimal-toc 310Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) 311Use only one TOC entry per procedure 312 313mfull-toc 314Target Report 315Put everything in the regular TOC 316 317mvrsave 318Target Report Var(TARGET_ALTIVEC_VRSAVE) Save 319Generate VRSAVE instructions when generating AltiVec code 320 321mvrsave=no 322Target RejectNegative Alias(mvrsave) NegativeAlias 323Deprecated option. Use -mno-vrsave instead 324 325mvrsave=yes 326Target RejectNegative Alias(mvrsave) 327Deprecated option. Use -mvrsave instead 328 329mblock-move-inline-limit= 330Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save 331Specify how many bytes should be moved inline before calling out to memcpy/memmove 332 333misel 334Target Report Mask(ISEL) Var(rs6000_isa_flags) 335Generate isel instructions 336 337misel=no 338Target RejectNegative Alias(misel) NegativeAlias 339Deprecated option. Use -mno-isel instead 340 341misel=yes 342Target RejectNegative Alias(misel) 343Deprecated option. Use -misel instead 344 345mspe 346Target Var(rs6000_spe) Save 347Generate SPE SIMD instructions on E500 348 349mpaired 350Target Var(rs6000_paired_float) Save 351Generate PPC750CL paired-single instructions 352 353mspe=no 354Target RejectNegative Alias(mspe) NegativeAlias 355Deprecated option. Use -mno-spe instead 356 357mspe=yes 358Target RejectNegative Alias(mspe) 359Deprecated option. Use -mspe instead 360 361mdebug= 362Target RejectNegative Joined 363-mdebug= Enable debug output 364 365mabi=altivec 366Target RejectNegative Var(rs6000_altivec_abi) Save 367Use the AltiVec ABI extensions 368 369mabi=no-altivec 370Target RejectNegative Var(rs6000_altivec_abi, 0) 371Do not use the AltiVec ABI extensions 372 373mabi=spe 374Target RejectNegative Var(rs6000_spe_abi) Save 375Use the SPE ABI extensions 376 377mabi=no-spe 378Target RejectNegative Var(rs6000_spe_abi, 0) 379Do not use the SPE ABI extensions 380 381mabi=elfv1 382Target RejectNegative Var(rs6000_elf_abi, 1) Save 383Use the ELFv1 ABI 384 385mabi=elfv2 386Target RejectNegative Var(rs6000_elf_abi, 2) 387Use the ELFv2 ABI 388 389; These are here for testing during development only, do not document 390; in the manual please. 391 392; If we want Darwin's struct-by-value-in-regs ABI. 393mabi=d64 394Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save 395 396mabi=d32 397Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0) 398 399mabi=ieeelongdouble 400Target RejectNegative Undocumented Warn(using IEEE extended precision long double) Var(rs6000_ieeequad) Save 401 402mabi=ibmlongdouble 403Target RejectNegative Undocumented Warn(using IBM extended precision long double) Var(rs6000_ieeequad, 0) 404 405mcpu= 406Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save 407-mcpu= Use features of and schedule code for given CPU 408 409mtune= 410Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save 411-mtune= Schedule code for given CPU 412 413mtraceback= 414Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback) 415-mtraceback= Select full, part, or no traceback table 416 417Enum 418Name(rs6000_traceback_type) Type(enum rs6000_traceback_type) 419 420EnumValue 421Enum(rs6000_traceback_type) String(full) Value(traceback_full) 422 423EnumValue 424Enum(rs6000_traceback_type) String(part) Value(traceback_part) 425 426EnumValue 427Enum(rs6000_traceback_type) String(no) Value(traceback_none) 428 429mlongcall 430Target Report Var(rs6000_default_long_calls) Save 431Avoid all range limits on call instructions 432 433mgen-cell-microcode 434Target Report Var(rs6000_gen_cell_microcode) Init(-1) Save 435Generate Cell microcode 436 437mwarn-cell-microcode 438Target Var(rs6000_warn_cell_microcode) Init(0) Warning Save 439Warn when a Cell microcoded instruction is emitted 440 441mwarn-altivec-long 442Target Var(rs6000_warn_altivec_long) Init(1) Save 443Warn about deprecated 'vector long ...' AltiVec type usage 444 445mfloat-gprs= 446Target RejectNegative Joined Enum(rs6000_float_gprs) Var(rs6000_float_gprs) Save 447-mfloat-gprs= Select GPR floating point method 448 449Enum 450Name(rs6000_float_gprs) Type(unsigned char) 451Valid arguments to -mfloat-gprs=: 452 453EnumValue 454Enum(rs6000_float_gprs) String(yes) Value(1) 455 456EnumValue 457Enum(rs6000_float_gprs) String(single) Value(1) 458 459EnumValue 460Enum(rs6000_float_gprs) String(double) Value(2) 461 462EnumValue 463Enum(rs6000_float_gprs) String(no) Value(0) 464 465mlong-double- 466Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save 467-mlong-double-<n> Specify size of long double (64 or 128 bits) 468 469mlra 470Target Report Var(rs6000_lra_flag) Init(0) Save 471Use LRA instead of reload 472 473msched-costly-dep= 474Target RejectNegative Joined Var(rs6000_sched_costly_dep_str) 475Determine which dependences between insns are considered costly 476 477minsert-sched-nops= 478Target RejectNegative Joined Var(rs6000_sched_insert_nops_str) 479Specify which post scheduling nop insertion scheme to apply 480 481malign- 482Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags) 483Specify alignment of structure fields default/natural 484 485Enum 486Name(rs6000_alignment_flags) Type(unsigned char) 487Valid arguments to -malign-: 488 489EnumValue 490Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER) 491 492EnumValue 493Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL) 494 495mprioritize-restricted-insns= 496Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save 497Specify scheduling priority for dispatch slot restricted insns 498 499msingle-float 500Target RejectNegative Var(rs6000_single_float) Save 501Single-precision floating point unit 502 503mdouble-float 504Target RejectNegative Var(rs6000_double_float) Save 505Double-precision floating point unit 506 507msimple-fpu 508Target RejectNegative Var(rs6000_simple_fpu) Save 509Floating point unit does not support divide & sqrt 510 511mfpu= 512Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE) 513-mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu) 514 515Enum 516Name(fpu_type_t) Type(enum fpu_type_t) 517 518EnumValue 519Enum(fpu_type_t) String(none) Value(FPU_NONE) 520 521EnumValue 522Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE) 523 524EnumValue 525Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE) 526 527EnumValue 528Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL) 529 530EnumValue 531Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL) 532 533mxilinx-fpu 534Target Var(rs6000_xilinx_fpu) Save 535Specify Xilinx FPU. 536 537mpointers-to-nested-functions 538Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save 539Use/do not use r11 to hold the static link in calls to functions via pointers. 540 541msave-toc-indirect 542Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags) 543Control whether we save the TOC in the prologue for indirect calls or generate the save inline 544 545mvsx-timode 546Target Undocumented Mask(VSX_TIMODE) Var(rs6000_isa_flags) 547Allow 128-bit integers in VSX registers 548 549mpower8-fusion 550Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) 551Fuse certain integer operations together for better performance on power8 552 553mpower8-fusion-sign 554Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) 555Allow sign extension in fusion operations 556 557mpower8-vector 558Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) 559Use/do not use vector and scalar instructions added in ISA 2.07. 560 561mcrypto 562Target Report Mask(CRYPTO) Var(rs6000_isa_flags) 563Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions 564 565mdirect-move 566Target Report Mask(DIRECT_MOVE) Var(rs6000_isa_flags) 567Use ISA 2.07 direct move between GPR & VSX register instructions 568 569mhtm 570Target Report Mask(HTM) Var(rs6000_isa_flags) 571Use ISA 2.07 transactional memory (HTM) instructions 572 573mquad-memory 574Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) 575Generate the quad word memory instructions (lq/stq). 576 577mquad-memory-atomic 578Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) 579Generate the quad word memory atomic instructions (lqarx/stqcx). 580 581mcompat-align-parm 582Target Report Var(rs6000_compat_align_parm) Init(1) Save 583Generate aggregate parameter passing code with at most 64-bit alignment. 584 585mupper-regs-df 586Target Undocumented Mask(UPPER_REGS_DF) Var(rs6000_isa_flags) 587Allow double variables in upper registers with -mcpu=power7 or -mvsx 588 589mupper-regs-sf 590Target Undocumented Mask(UPPER_REGS_SF) Var(rs6000_isa_flags) 591Allow float variables in upper registers with -mcpu=power8 or -mp8-vector 592 593moptimize-swaps 594Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save 595Analyze and remove doubleword swaps from VSX computations. 596