1; Options for the rs6000 port of the compiler 2; 3; Copyright (C) 2005-2018 Free Software Foundation, Inc. 4; Contributed by Aldy Hernandez <aldy@quesejoda.com>. 5; 6; This file is part of GCC. 7; 8; GCC is free software; you can redistribute it and/or modify it under 9; the terms of the GNU General Public License as published by the Free 10; Software Foundation; either version 3, or (at your option) any later 11; version. 12; 13; GCC is distributed in the hope that it will be useful, but WITHOUT 14; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16; License for more details. 17; 18; You should have received a copy of the GNU General Public License 19; along with GCC; see the file COPYING3. If not see 20; <http://www.gnu.org/licenses/>. 21 22HeaderInclude 23config/rs6000/rs6000-opts.h 24 25;; ISA flag bits (on/off) 26Variable 27HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT 28 29TargetSave 30HOST_WIDE_INT x_rs6000_isa_flags 31 32;; Miscellaneous flag bits that were set explicitly by the user 33Variable 34HOST_WIDE_INT rs6000_isa_flags_explicit 35 36TargetSave 37HOST_WIDE_INT x_rs6000_isa_flags_explicit 38 39;; Current processor 40TargetVariable 41enum processor_type rs6000_cpu = PROCESSOR_PPC603 42 43;; Current tuning 44TargetVariable 45enum processor_type rs6000_tune = PROCESSOR_PPC603 46 47;; Always emit branch hint bits. 48TargetVariable 49unsigned char rs6000_always_hint 50 51;; Schedule instructions for group formation. 52TargetVariable 53unsigned char rs6000_sched_groups 54 55;; Align branch targets. 56TargetVariable 57unsigned char rs6000_align_branch_targets 58 59;; Support for -msched-costly-dep option. 60TargetVariable 61enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly 62 63;; Support for -minsert-sched-nops option. 64TargetVariable 65enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none 66 67;; Non-zero to allow overriding loop alignment. 68TargetVariable 69unsigned char can_override_loop_align 70 71;; Which small data model to use (for System V targets only) 72TargetVariable 73enum rs6000_sdata_type rs6000_sdata = SDATA_DATA 74 75;; Bit size of immediate TLS offsets and string from which it is decoded. 76TargetVariable 77int rs6000_tls_size = 32 78 79;; ABI enumeration available for subtarget to use. 80TargetVariable 81enum rs6000_abi rs6000_current_abi = ABI_NONE 82 83;; Type of traceback to use. 84TargetVariable 85enum rs6000_traceback_type rs6000_traceback = traceback_default 86 87;; Control alignment for fields within structures. 88TargetVariable 89unsigned char rs6000_alignment_flags 90 91;; Code model for 64-bit linux. 92TargetVariable 93enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL 94 95;; What type of reciprocal estimation instructions to generate 96TargetVariable 97unsigned int rs6000_recip_control 98 99;; Mask of what builtin functions are allowed 100TargetVariable 101HOST_WIDE_INT rs6000_builtin_mask 102 103;; Debug flags 104TargetVariable 105unsigned int rs6000_debug 106 107;; Whether to enable the -mfloat128 stuff without necessarily enabling the 108;; __float128 keyword. 109TargetSave 110unsigned char x_TARGET_FLOAT128_TYPE 111 112Variable 113unsigned char TARGET_FLOAT128_TYPE 114 115;; This option existed in the past, but now is always on. 116mpowerpc 117Target RejectNegative Undocumented Ignore 118 119mpowerpc64 120Target Report Mask(POWERPC64) Var(rs6000_isa_flags) 121Use PowerPC-64 instruction set. 122 123mpowerpc-gpopt 124Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) 125Use PowerPC General Purpose group optional instructions. 126 127mpowerpc-gfxopt 128Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) 129Use PowerPC Graphics group optional instructions. 130 131mmfcrf 132Target Report Mask(MFCRF) Var(rs6000_isa_flags) 133Use PowerPC V2.01 single field mfcr instruction. 134 135mpopcntb 136Target Report Mask(POPCNTB) Var(rs6000_isa_flags) 137Use PowerPC V2.02 popcntb instruction. 138 139mfprnd 140Target Report Mask(FPRND) Var(rs6000_isa_flags) 141Use PowerPC V2.02 floating point rounding instructions. 142 143mcmpb 144Target Report Mask(CMPB) Var(rs6000_isa_flags) 145Use PowerPC V2.05 compare bytes instruction. 146 147mmfpgpr 148Target Report Mask(MFPGPR) Var(rs6000_isa_flags) 149Use extended PowerPC V2.05 move floating point to/from GPR instructions. 150 151maltivec 152Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) 153Use AltiVec instructions. 154 155maltivec=le 156Target Report RejectNegative Var(rs6000_altivec_element_order, 1) Save 157Generate AltiVec instructions using little-endian element order. 158 159maltivec=be 160Target Report RejectNegative Var(rs6000_altivec_element_order, 2) 161Generate AltiVec instructions using big-endian element order. 162 163mfold-gimple 164Target Report Var(rs6000_fold_gimple) Init(1) 165Enable early gimple folding of builtins. 166 167mhard-dfp 168Target Report Mask(DFP) Var(rs6000_isa_flags) 169Use decimal floating point instructions. 170 171mmulhw 172Target Report Mask(MULHW) Var(rs6000_isa_flags) 173Use 4xx half-word multiply instructions. 174 175mdlmzb 176Target Report Mask(DLMZB) Var(rs6000_isa_flags) 177Use 4xx string-search dlmzb instruction. 178 179mmultiple 180Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) 181Generate load/store multiple instructions. 182 183;; This option existed in the past, but now is always off. 184mno-string 185Target RejectNegative Undocumented Ignore 186 187mstring 188Target RejectNegative Undocumented Warn(%<-mstring%> is deprecated) 189 190msoft-float 191Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) 192Do not use hardware floating point. 193 194mhard-float 195Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) 196Use hardware floating point. 197 198mpopcntd 199Target Report Mask(POPCNTD) Var(rs6000_isa_flags) 200Use PowerPC V2.06 popcntd instruction. 201 202mfriz 203Target Report Var(TARGET_FRIZ) Init(-1) Save 204Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions. 205 206mveclibabi= 207Target RejectNegative Joined Var(rs6000_veclibabi_name) 208Vector library ABI to use. 209 210mvsx 211Target Report Mask(VSX) Var(rs6000_isa_flags) 212Use vector/scalar (VSX) instructions. 213 214mvsx-align-128 215Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save 216; If -mvsx, set alignment to 128 bits instead of 32/64 217 218mallow-movmisalign 219Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save 220; Allow the movmisalign in DF/DI vectors 221 222mefficient-unaligned-vsx 223Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags) 224; Consider unaligned VSX vector and fp accesses to be efficient 225 226msched-groups 227Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save 228; Explicitly set rs6000_sched_groups 229 230malways-hint 231Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save 232; Explicitly set rs6000_always_hint 233 234malign-branch-targets 235Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save 236; Explicitly set rs6000_align_branch_targets 237 238mno-update 239Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) 240Do not generate load/store with update instructions. 241 242mupdate 243Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) 244Generate load/store with update instructions. 245 246msingle-pic-base 247Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) 248Do not load the PIC register in function prologues. 249 250mavoid-indexed-addresses 251Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save 252Avoid generation of indexed load/store instructions when possible. 253 254mtls-markers 255Target Report Var(tls_markers) Init(1) Save 256Mark __tls_get_addr calls with argument info. 257 258msched-epilog 259Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save 260 261msched-prolog 262Target Report Var(TARGET_SCHED_PROLOG) Save 263Schedule the start and end of the procedure. 264 265maix-struct-return 266Target Report RejectNegative Var(aix_struct_return) Save 267Return all structures in memory (AIX default). 268 269msvr4-struct-return 270Target Report RejectNegative Var(aix_struct_return,0) Save 271Return small structures in registers (SVR4 default). 272 273mxl-compat 274Target Report Var(TARGET_XL_COMPAT) Save 275Conform more closely to IBM XLC semantics. 276 277mrecip 278Target Report 279Generate software reciprocal divide and square root for better throughput. 280 281mrecip= 282Target Report RejectNegative Joined Var(rs6000_recip_name) 283Generate software reciprocal divide and square root for better throughput. 284 285mrecip-precision 286Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) 287Assume that the reciprocal estimate instructions provide more accuracy. 288 289mno-fp-in-toc 290Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save 291Do not place floating point constants in TOC. 292 293mfp-in-toc 294Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save 295Place floating point constants in TOC. 296 297mno-sum-in-toc 298Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save 299Do not place symbol+offset constants in TOC. 300 301msum-in-toc 302Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save 303Place symbol+offset constants in TOC. 304 305; Output only one TOC entry per module. Normally linking fails if 306; there are more than 16K unique variables/constants in an executable. With 307; this option, linking fails only if there are more than 16K modules, or 308; if there are more than 16K unique variables/constant in a single module. 309; 310; This is at the cost of having 2 extra loads and one extra store per 311; function, and one less allocable register. 312mminimal-toc 313Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) 314Use only one TOC entry per procedure. 315 316mfull-toc 317Target Report 318Put everything in the regular TOC. 319 320mvrsave 321Target Report Var(TARGET_ALTIVEC_VRSAVE) Save 322Generate VRSAVE instructions when generating AltiVec code. 323 324mvrsave=no 325Target RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead) 326Deprecated option. Use -mno-vrsave instead. 327 328mvrsave=yes 329Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead) 330Deprecated option. Use -mvrsave instead. 331 332mblock-move-inline-limit= 333Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save 334Max number of bytes to move inline. 335 336mblock-compare-inline-limit= 337Target Report Var(rs6000_block_compare_inline_limit) Init(31) RejectNegative Joined UInteger Save 338Max number of bytes to compare without loops. 339 340mblock-compare-inline-loop-limit= 341Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save 342Max number of bytes to compare with loops. 343 344mstring-compare-inline-limit= 345Target Report Var(rs6000_string_compare_inline_limit) Init(8) RejectNegative Joined UInteger Save 346Max number of pairs of load insns for compare. 347 348misel 349Target Report Mask(ISEL) Var(rs6000_isa_flags) 350Generate isel instructions. 351 352misel=no 353Target RejectNegative Alias(misel) NegativeAlias Warn(%<-misel=no%> is deprecated; use %<-mno-isel%> instead) 354Deprecated option. Use -mno-isel instead. 355 356misel=yes 357Target RejectNegative Alias(misel) Warn(%<-misel=yes%> is deprecated; use %<-misel%> instead) 358Deprecated option. Use -misel instead. 359 360mpaired 361Target Var(rs6000_paired_float) Save 362Generate PPC750CL paired-single instructions. 363 364mdebug= 365Target RejectNegative Joined 366-mdebug= Enable debug output. 367 368mabi=altivec 369Target RejectNegative Var(rs6000_altivec_abi) Save 370Use the AltiVec ABI extensions. 371 372mabi=no-altivec 373Target RejectNegative Var(rs6000_altivec_abi, 0) 374Do not use the AltiVec ABI extensions. 375 376mabi=elfv1 377Target RejectNegative Var(rs6000_elf_abi, 1) Save 378Use the ELFv1 ABI. 379 380mabi=elfv2 381Target RejectNegative Var(rs6000_elf_abi, 2) 382Use the ELFv2 ABI. 383 384; These are here for testing during development only, do not document 385; in the manual please. 386 387; If we want Darwin's struct-by-value-in-regs ABI. 388mabi=d64 389Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save 390 391mabi=d32 392Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0) 393 394mabi=ieeelongdouble 395Target RejectNegative Var(rs6000_ieeequad) Save 396 397mabi=ibmlongdouble 398Target RejectNegative Var(rs6000_ieeequad, 0) 399 400mcpu= 401Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save 402-mcpu= Use features of and schedule code for given CPU. 403 404mtune= 405Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save 406-mtune= Schedule code for given CPU. 407 408mtraceback= 409Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback) 410-mtraceback=[full,part,no] Select type of traceback table. 411 412Enum 413Name(rs6000_traceback_type) Type(enum rs6000_traceback_type) 414 415EnumValue 416Enum(rs6000_traceback_type) String(full) Value(traceback_full) 417 418EnumValue 419Enum(rs6000_traceback_type) String(part) Value(traceback_part) 420 421EnumValue 422Enum(rs6000_traceback_type) String(no) Value(traceback_none) 423 424mlongcall 425Target Report Var(rs6000_default_long_calls) Save 426Avoid all range limits on call instructions. 427 428; This option existed in the past, but now is always on. 429mgen-cell-microcode 430Target RejectNegative Undocumented Ignore 431 432mwarn-altivec-long 433Target Var(rs6000_warn_altivec_long) Init(1) Save 434Warn about deprecated 'vector long ...' AltiVec type usage. 435 436mlong-double- 437Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save 438-mlong-double-[64,128] Specify size of long double. 439 440; This option existed in the past, but now is always on. 441mlra 442Target RejectNegative Undocumented Ignore 443 444msched-costly-dep= 445Target RejectNegative Joined Var(rs6000_sched_costly_dep_str) 446Determine which dependences between insns are considered costly. 447 448minsert-sched-nops= 449Target RejectNegative Joined Var(rs6000_sched_insert_nops_str) 450Specify which post scheduling nop insertion scheme to apply. 451 452malign- 453Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags) 454Specify alignment of structure fields default/natural. 455 456Enum 457Name(rs6000_alignment_flags) Type(unsigned char) 458Valid arguments to -malign-: 459 460EnumValue 461Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER) 462 463EnumValue 464Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL) 465 466mprioritize-restricted-insns= 467Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save 468Specify scheduling priority for dispatch slot restricted insns. 469 470msingle-float 471Target RejectNegative Var(rs6000_single_float) Save 472Single-precision floating point unit. 473 474mdouble-float 475Target RejectNegative Var(rs6000_double_float) Save 476Double-precision floating point unit. 477 478msimple-fpu 479Target RejectNegative Var(rs6000_simple_fpu) Save 480Floating point unit does not support divide & sqrt. 481 482mfpu= 483Target RejectNegative Joined Enum(fpu_type_t) Var(rs6000_fpu_type) Init(FPU_NONE) 484-mfpu= Specify FP (sp, dp, sp-lite, dp-lite) (implies -mxilinx-fpu). 485 486Enum 487Name(fpu_type_t) Type(enum fpu_type_t) 488 489EnumValue 490Enum(fpu_type_t) String(none) Value(FPU_NONE) 491 492EnumValue 493Enum(fpu_type_t) String(sp_lite) Value(FPU_SF_LITE) 494 495EnumValue 496Enum(fpu_type_t) String(dp_lite) Value(FPU_DF_LITE) 497 498EnumValue 499Enum(fpu_type_t) String(sp_full) Value(FPU_SF_FULL) 500 501EnumValue 502Enum(fpu_type_t) String(dp_full) Value(FPU_DF_FULL) 503 504mxilinx-fpu 505Target Var(rs6000_xilinx_fpu) Save 506Specify Xilinx FPU. 507 508mpointers-to-nested-functions 509Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save 510Use r11 to hold the static link in calls to functions via pointers. 511 512msave-toc-indirect 513Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags) 514Save the TOC in the prologue for indirect calls rather than inline. 515 516; This option existed in the past, but now is always the same as -mvsx. 517mvsx-timode 518Target RejectNegative Undocumented Ignore 519 520mpower8-fusion 521Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) 522Fuse certain integer operations together for better performance on power8. 523 524mpower8-fusion-sign 525Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) 526Allow sign extension in fusion operations. 527 528mpower8-vector 529Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) 530Use vector and scalar instructions added in ISA 2.07. 531 532mcrypto 533Target Report Mask(CRYPTO) Var(rs6000_isa_flags) 534Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. 535 536mdirect-move 537Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) Ignore Warn(%qs is deprecated) 538 539mhtm 540Target Report Mask(HTM) Var(rs6000_isa_flags) 541Use ISA 2.07 transactional memory (HTM) instructions. 542 543mquad-memory 544Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) 545Generate the quad word memory instructions (lq/stq). 546 547mquad-memory-atomic 548Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) 549Generate the quad word memory atomic instructions (lqarx/stqcx). 550 551mcompat-align-parm 552Target Report Var(rs6000_compat_align_parm) Init(0) Save 553Generate aggregate parameter passing code with at most 64-bit alignment. 554 555moptimize-swaps 556Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save 557Analyze and remove doubleword swaps from VSX computations. 558 559mpower9-fusion 560Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags) 561Fuse certain operations together for better performance on power9. 562 563mpower9-misc 564Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags) 565Use certain scalar instructions added in ISA 3.0. 566 567mpower9-vector 568Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags) 569Use vector instructions added in ISA 3.0. 570 571mpower9-minmax 572Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags) 573Use the new min/max instructions defined in ISA 3.0. 574 575mtoc-fusion 576Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags) 577Fuse medium/large code model toc references with the memory instruction. 578 579mmodulo 580Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags) 581Generate the integer modulo instructions. 582 583mfloat128 584Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags) 585Enable IEEE 128-bit floating point via the __float128 keyword. 586 587mfloat128-hardware 588Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags) 589Enable using IEEE 128-bit floating point instructions. 590 591mfloat128-convert 592Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags) 593Enable default conversions between __float128 & long double. 594 595mstack-protector-guard= 596Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS) 597Use given stack-protector guard. 598 599Enum 600Name(stack_protector_guard) Type(enum stack_protector_guard) 601Valid arguments to -mstack-protector-guard=: 602 603EnumValue 604Enum(stack_protector_guard) String(tls) Value(SSP_TLS) 605 606EnumValue 607Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) 608 609mstack-protector-guard-reg= 610Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str) 611Use the given base register for addressing the stack-protector guard. 612 613TargetVariable 614int rs6000_stack_protector_guard_reg = 0 615 616mstack-protector-guard-offset= 617Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str) 618Use the given offset for addressing the stack-protector guard. 619 620TargetVariable 621long rs6000_stack_protector_guard_offset = 0 622 623;; -mno-speculate-indirect-jumps adds deliberate misprediction to indirect 624;; branches via the CTR. 625mspeculate-indirect-jumps 626Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save 627