1; Options for the rs6000 port of the compiler 2; 3; Copyright (C) 2005-2019 Free Software Foundation, Inc. 4; Contributed by Aldy Hernandez <aldy@quesejoda.com>. 5; 6; This file is part of GCC. 7; 8; GCC is free software; you can redistribute it and/or modify it under 9; the terms of the GNU General Public License as published by the Free 10; Software Foundation; either version 3, or (at your option) any later 11; version. 12; 13; GCC is distributed in the hope that it will be useful, but WITHOUT 14; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 15; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 16; License for more details. 17; 18; You should have received a copy of the GNU General Public License 19; along with GCC; see the file COPYING3. If not see 20; <http://www.gnu.org/licenses/>. 21 22HeaderInclude 23config/rs6000/rs6000-opts.h 24 25;; ISA flag bits (on/off) 26Variable 27HOST_WIDE_INT rs6000_isa_flags = TARGET_DEFAULT 28 29TargetSave 30HOST_WIDE_INT x_rs6000_isa_flags 31 32;; Miscellaneous flag bits that were set explicitly by the user 33Variable 34HOST_WIDE_INT rs6000_isa_flags_explicit 35 36TargetSave 37HOST_WIDE_INT x_rs6000_isa_flags_explicit 38 39;; Current processor 40TargetVariable 41enum processor_type rs6000_cpu = PROCESSOR_PPC603 42 43;; Current tuning 44TargetVariable 45enum processor_type rs6000_tune = PROCESSOR_PPC603 46 47;; Always emit branch hint bits. 48TargetVariable 49unsigned char rs6000_always_hint 50 51;; Schedule instructions for group formation. 52TargetVariable 53unsigned char rs6000_sched_groups 54 55;; Align branch targets. 56TargetVariable 57unsigned char rs6000_align_branch_targets 58 59;; Support for -msched-costly-dep option. 60TargetVariable 61enum rs6000_dependence_cost rs6000_sched_costly_dep = no_dep_costly 62 63;; Support for -minsert-sched-nops option. 64TargetVariable 65enum rs6000_nop_insertion rs6000_sched_insert_nops = sched_finish_none 66 67;; Non-zero to allow overriding loop alignment. 68TargetVariable 69unsigned char can_override_loop_align 70 71;; Which small data model to use (for System V targets only) 72TargetVariable 73enum rs6000_sdata_type rs6000_sdata = SDATA_DATA 74 75;; Bit size of immediate TLS offsets and string from which it is decoded. 76TargetVariable 77int rs6000_tls_size = 32 78 79;; ABI enumeration available for subtarget to use. 80TargetVariable 81enum rs6000_abi rs6000_current_abi = ABI_NONE 82 83;; Type of traceback to use. 84TargetVariable 85enum rs6000_traceback_type rs6000_traceback = traceback_default 86 87;; Control alignment for fields within structures. 88TargetVariable 89unsigned char rs6000_alignment_flags 90 91;; Code model for 64-bit linux. 92TargetVariable 93enum rs6000_cmodel rs6000_current_cmodel = CMODEL_SMALL 94 95;; What type of reciprocal estimation instructions to generate 96TargetVariable 97unsigned int rs6000_recip_control 98 99;; Mask of what builtin functions are allowed 100TargetVariable 101HOST_WIDE_INT rs6000_builtin_mask 102 103;; Debug flags 104TargetVariable 105unsigned int rs6000_debug 106 107;; Whether to enable the -mfloat128 stuff without necessarily enabling the 108;; __float128 keyword. 109TargetSave 110unsigned char x_TARGET_FLOAT128_TYPE 111 112Variable 113unsigned char TARGET_FLOAT128_TYPE 114 115;; This option existed in the past, but now is always on. 116mpowerpc 117Target RejectNegative Undocumented Ignore 118 119mpowerpc64 120Target Report Mask(POWERPC64) Var(rs6000_isa_flags) 121Use PowerPC-64 instruction set. 122 123mpowerpc-gpopt 124Target Report Mask(PPC_GPOPT) Var(rs6000_isa_flags) 125Use PowerPC General Purpose group optional instructions. 126 127mpowerpc-gfxopt 128Target Report Mask(PPC_GFXOPT) Var(rs6000_isa_flags) 129Use PowerPC Graphics group optional instructions. 130 131mmfcrf 132Target Report Mask(MFCRF) Var(rs6000_isa_flags) 133Use PowerPC V2.01 single field mfcr instruction. 134 135mpopcntb 136Target Report Mask(POPCNTB) Var(rs6000_isa_flags) 137Use PowerPC V2.02 popcntb instruction. 138 139mfprnd 140Target Report Mask(FPRND) Var(rs6000_isa_flags) 141Use PowerPC V2.02 floating point rounding instructions. 142 143mcmpb 144Target Report Mask(CMPB) Var(rs6000_isa_flags) 145Use PowerPC V2.05 compare bytes instruction. 146 147mmfpgpr 148Target Report Mask(MFPGPR) Var(rs6000_isa_flags) 149Use extended PowerPC V2.05 move floating point to/from GPR instructions. 150 151maltivec 152Target Report Mask(ALTIVEC) Var(rs6000_isa_flags) 153Use AltiVec instructions. 154 155mfold-gimple 156Target Report Var(rs6000_fold_gimple) Init(1) 157Enable early gimple folding of builtins. 158 159mhard-dfp 160Target Report Mask(DFP) Var(rs6000_isa_flags) 161Use decimal floating point instructions. 162 163mmulhw 164Target Report Mask(MULHW) Var(rs6000_isa_flags) 165Use 4xx half-word multiply instructions. 166 167mdlmzb 168Target Report Mask(DLMZB) Var(rs6000_isa_flags) 169Use 4xx string-search dlmzb instruction. 170 171mmultiple 172Target Report Mask(MULTIPLE) Var(rs6000_isa_flags) 173Generate load/store multiple instructions. 174 175;; This option existed in the past, but now is always off. 176mno-string 177Target RejectNegative Undocumented Ignore 178 179mstring 180Target RejectNegative Undocumented Deprecated 181 182msoft-float 183Target Report RejectNegative Mask(SOFT_FLOAT) Var(rs6000_isa_flags) 184Do not use hardware floating point. 185 186mhard-float 187Target Report RejectNegative InverseMask(SOFT_FLOAT, HARD_FLOAT) Var(rs6000_isa_flags) 188Use hardware floating point. 189 190mpopcntd 191Target Report Mask(POPCNTD) Var(rs6000_isa_flags) 192Use PowerPC V2.06 popcntd instruction. 193 194mfriz 195Target Report Var(TARGET_FRIZ) Init(-1) Save 196Under -ffast-math, generate a FRIZ instruction for (double)(long long) conversions. 197 198mveclibabi= 199Target RejectNegative Joined Var(rs6000_veclibabi_name) 200Vector library ABI to use. 201 202mvsx 203Target Report Mask(VSX) Var(rs6000_isa_flags) 204Use vector/scalar (VSX) instructions. 205 206mvsx-align-128 207Target Undocumented Report Var(TARGET_VSX_ALIGN_128) Save 208; If -mvsx, set alignment to 128 bits instead of 32/64 209 210mallow-movmisalign 211Target Undocumented Var(TARGET_ALLOW_MOVMISALIGN) Init(-1) Save 212; Allow the movmisalign in DF/DI vectors 213 214mefficient-unaligned-vsx 215Target Undocumented Report Mask(EFFICIENT_UNALIGNED_VSX) Var(rs6000_isa_flags) 216; Consider unaligned VSX vector and fp accesses to be efficient 217 218msched-groups 219Target Undocumented Report Var(TARGET_SCHED_GROUPS) Init(-1) Save 220; Explicitly set rs6000_sched_groups 221 222malways-hint 223Target Undocumented Report Var(TARGET_ALWAYS_HINT) Init(-1) Save 224; Explicitly set rs6000_always_hint 225 226malign-branch-targets 227Target Undocumented Report Var(TARGET_ALIGN_BRANCH_TARGETS) Init(-1) Save 228; Explicitly set rs6000_align_branch_targets 229 230mno-update 231Target Report RejectNegative Mask(NO_UPDATE) Var(rs6000_isa_flags) 232Do not generate load/store with update instructions. 233 234mupdate 235Target Report RejectNegative InverseMask(NO_UPDATE, UPDATE) Var(rs6000_isa_flags) 236Generate load/store with update instructions. 237 238msingle-pic-base 239Target Report Var(TARGET_SINGLE_PIC_BASE) Init(0) 240Do not load the PIC register in function prologues. 241 242mavoid-indexed-addresses 243Target Report Var(TARGET_AVOID_XFORM) Init(-1) Save 244Avoid generation of indexed load/store instructions when possible. 245 246mtls-markers 247Target Report Var(tls_markers) Init(1) Save 248Mark __tls_get_addr calls with argument info. 249 250msched-epilog 251Target Undocumented Var(TARGET_SCHED_PROLOG) Init(1) Save 252 253msched-prolog 254Target Report Var(TARGET_SCHED_PROLOG) Save 255Schedule the start and end of the procedure. 256 257maix-struct-return 258Target Report RejectNegative Var(aix_struct_return) Save 259Return all structures in memory (AIX default). 260 261msvr4-struct-return 262Target Report RejectNegative Var(aix_struct_return,0) Save 263Return small structures in registers (SVR4 default). 264 265mxl-compat 266Target Report Var(TARGET_XL_COMPAT) Save 267Conform more closely to IBM XLC semantics. 268 269mrecip 270Target Report 271Generate software reciprocal divide and square root for better throughput. 272 273mrecip= 274Target Report RejectNegative Joined Var(rs6000_recip_name) 275Generate software reciprocal divide and square root for better throughput. 276 277mrecip-precision 278Target Report Mask(RECIP_PRECISION) Var(rs6000_isa_flags) 279Assume that the reciprocal estimate instructions provide more accuracy. 280 281mno-fp-in-toc 282Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC) Save 283Do not place floating point constants in TOC. 284 285mfp-in-toc 286Target Report RejectNegative Var(TARGET_NO_FP_IN_TOC,0) Save 287Place floating point constants in TOC. 288 289mno-sum-in-toc 290Target RejectNegative Var(TARGET_NO_SUM_IN_TOC) Save 291Do not place symbol+offset constants in TOC. 292 293msum-in-toc 294Target RejectNegative Var(TARGET_NO_SUM_IN_TOC,0) Save 295Place symbol+offset constants in TOC. 296 297; Output only one TOC entry per module. Normally linking fails if 298; there are more than 16K unique variables/constants in an executable. With 299; this option, linking fails only if there are more than 16K modules, or 300; if there are more than 16K unique variables/constant in a single module. 301; 302; This is at the cost of having 2 extra loads and one extra store per 303; function, and one less allocable register. 304mminimal-toc 305Target Report Mask(MINIMAL_TOC) Var(rs6000_isa_flags) 306Use only one TOC entry per procedure. 307 308mfull-toc 309Target Report 310Put everything in the regular TOC. 311 312mvrsave 313Target Report Var(TARGET_ALTIVEC_VRSAVE) Save 314Generate VRSAVE instructions when generating AltiVec code. 315 316mvrsave=no 317Target RejectNegative Alias(mvrsave) NegativeAlias Warn(%<-mvrsave=no%> is deprecated; use %<-mno-vrsave%> instead) 318Deprecated option. Use -mno-vrsave instead. 319 320mvrsave=yes 321Target RejectNegative Alias(mvrsave) Warn(%<-mvrsave=yes%> is deprecated; use %<-mvrsave%> instead) 322Deprecated option. Use -mvrsave instead. 323 324mblock-move-inline-limit= 325Target Report Var(rs6000_block_move_inline_limit) Init(0) RejectNegative Joined UInteger Save 326Max number of bytes to move inline. 327 328mblock-compare-inline-limit= 329Target Report Var(rs6000_block_compare_inline_limit) Init(63) RejectNegative Joined UInteger Save 330Max number of bytes to compare without loops. 331 332mblock-compare-inline-loop-limit= 333Target Report Var(rs6000_block_compare_inline_loop_limit) Init(-1) RejectNegative Joined UInteger Save 334Max number of bytes to compare with loops. 335 336mstring-compare-inline-limit= 337Target Report Var(rs6000_string_compare_inline_limit) Init(64) RejectNegative Joined UInteger Save 338Max number of bytes to compare. 339 340misel 341Target Report Mask(ISEL) Var(rs6000_isa_flags) 342Generate isel instructions. 343 344mdebug= 345Target RejectNegative Joined 346-mdebug= Enable debug output. 347 348mabi=altivec 349Target RejectNegative Var(rs6000_altivec_abi) Save 350Use the AltiVec ABI extensions. 351 352mabi=no-altivec 353Target RejectNegative Var(rs6000_altivec_abi, 0) 354Do not use the AltiVec ABI extensions. 355 356mabi=elfv1 357Target RejectNegative Var(rs6000_elf_abi, 1) Save 358Use the ELFv1 ABI. 359 360mabi=elfv2 361Target RejectNegative Var(rs6000_elf_abi, 2) 362Use the ELFv2 ABI. 363 364; These are here for testing during development only, do not document 365; in the manual please. 366 367; If we want Darwin's struct-by-value-in-regs ABI. 368mabi=d64 369Target RejectNegative Undocumented Warn(using darwin64 ABI) Var(rs6000_darwin64_abi) Save 370 371mabi=d32 372Target RejectNegative Undocumented Warn(using old darwin ABI) Var(rs6000_darwin64_abi, 0) 373 374mabi=ieeelongdouble 375Target RejectNegative Var(rs6000_ieeequad) Save 376 377mabi=ibmlongdouble 378Target RejectNegative Var(rs6000_ieeequad, 0) 379 380mcpu= 381Target RejectNegative Joined Var(rs6000_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save 382-mcpu= Use features of and schedule code for given CPU. 383 384mtune= 385Target RejectNegative Joined Var(rs6000_tune_index) Init(-1) Enum(rs6000_cpu_opt_value) Save 386-mtune= Schedule code for given CPU. 387 388; Only for use in the testsuite. This simply overrides -mcpu=. With older 389; versions of Dejagnu the command line arguments you set in RUNTESTFLAGS 390; override those set in the testcases; with this option, the testcase will 391; always win. 392mdejagnu-cpu= 393Target Undocumented RejectNegative Joined Var(rs6000_dejagnu_cpu_index) Init(-1) Enum(rs6000_cpu_opt_value) Save 394 395mtraceback= 396Target RejectNegative Joined Enum(rs6000_traceback_type) Var(rs6000_traceback) 397-mtraceback=[full,part,no] Select type of traceback table. 398 399Enum 400Name(rs6000_traceback_type) Type(enum rs6000_traceback_type) 401 402EnumValue 403Enum(rs6000_traceback_type) String(full) Value(traceback_full) 404 405EnumValue 406Enum(rs6000_traceback_type) String(part) Value(traceback_part) 407 408EnumValue 409Enum(rs6000_traceback_type) String(no) Value(traceback_none) 410 411mlongcall 412Target Report Var(rs6000_default_long_calls) Save 413Avoid all range limits on call instructions. 414 415; This option existed in the past, but now is always on. 416mgen-cell-microcode 417Target RejectNegative Undocumented Ignore 418 419mwarn-altivec-long 420Target Var(rs6000_warn_altivec_long) Init(1) Save 421Warn about deprecated 'vector long ...' AltiVec type usage. 422 423mlong-double- 424Target RejectNegative Joined UInteger Var(rs6000_long_double_type_size) Save 425-mlong-double-[64,128] Specify size of long double. 426 427; This option existed in the past, but now is always on. 428mlra 429Target RejectNegative Undocumented Ignore 430 431msched-costly-dep= 432Target RejectNegative Joined Var(rs6000_sched_costly_dep_str) 433Determine which dependences between insns are considered costly. 434 435minsert-sched-nops= 436Target RejectNegative Joined Var(rs6000_sched_insert_nops_str) 437Specify which post scheduling nop insertion scheme to apply. 438 439malign- 440Target RejectNegative Joined Enum(rs6000_alignment_flags) Var(rs6000_alignment_flags) 441Specify alignment of structure fields default/natural. 442 443Enum 444Name(rs6000_alignment_flags) Type(unsigned char) 445Valid arguments to -malign-: 446 447EnumValue 448Enum(rs6000_alignment_flags) String(power) Value(MASK_ALIGN_POWER) 449 450EnumValue 451Enum(rs6000_alignment_flags) String(natural) Value(MASK_ALIGN_NATURAL) 452 453mprioritize-restricted-insns= 454Target RejectNegative Joined UInteger Var(rs6000_sched_restricted_insns_priority) Save 455Specify scheduling priority for dispatch slot restricted insns. 456 457mpointers-to-nested-functions 458Target Report Var(TARGET_POINTERS_TO_NESTED_FUNCTIONS) Init(1) Save 459Use r11 to hold the static link in calls to functions via pointers. 460 461msave-toc-indirect 462Target Report Mask(SAVE_TOC_INDIRECT) Var(rs6000_isa_flags) 463Save the TOC in the prologue for indirect calls rather than inline. 464 465; This option existed in the past, but now is always the same as -mvsx. 466mvsx-timode 467Target RejectNegative Undocumented Ignore 468 469mpower8-fusion 470Target Report Mask(P8_FUSION) Var(rs6000_isa_flags) 471Fuse certain integer operations together for better performance on power8. 472 473mpower8-fusion-sign 474Target Undocumented Mask(P8_FUSION_SIGN) Var(rs6000_isa_flags) 475Allow sign extension in fusion operations. 476 477mpower8-vector 478Target Report Mask(P8_VECTOR) Var(rs6000_isa_flags) 479Use vector and scalar instructions added in ISA 2.07. 480 481mcrypto 482Target Report Mask(CRYPTO) Var(rs6000_isa_flags) 483Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions. 484 485mdirect-move 486Target Undocumented Mask(DIRECT_MOVE) Var(rs6000_isa_flags) Deprecated 487 488mhtm 489Target Report Mask(HTM) Var(rs6000_isa_flags) 490Use ISA 2.07 transactional memory (HTM) instructions. 491 492mquad-memory 493Target Report Mask(QUAD_MEMORY) Var(rs6000_isa_flags) 494Generate the quad word memory instructions (lq/stq). 495 496mquad-memory-atomic 497Target Report Mask(QUAD_MEMORY_ATOMIC) Var(rs6000_isa_flags) 498Generate the quad word memory atomic instructions (lqarx/stqcx). 499 500mcompat-align-parm 501Target Report Var(rs6000_compat_align_parm) Init(0) Save 502Generate aggregate parameter passing code with at most 64-bit alignment. 503 504moptimize-swaps 505Target Undocumented Var(rs6000_optimize_swaps) Init(1) Save 506Analyze and remove doubleword swaps from VSX computations. 507 508mpower9-misc 509Target Undocumented Report Mask(P9_MISC) Var(rs6000_isa_flags) 510Use certain scalar instructions added in ISA 3.0. 511 512mpower9-vector 513Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags) 514Use vector instructions added in ISA 3.0. 515 516mpower9-minmax 517Target Undocumented Mask(P9_MINMAX) Var(rs6000_isa_flags) 518Use the new min/max instructions defined in ISA 3.0. 519 520mtoc-fusion 521Target Undocumented Mask(TOC_FUSION) Var(rs6000_isa_flags) 522Fuse medium/large code model toc references with the memory instruction. 523 524mmodulo 525Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags) 526Generate the integer modulo instructions. 527 528mfloat128 529Target Report Mask(FLOAT128_KEYWORD) Var(rs6000_isa_flags) 530Enable IEEE 128-bit floating point via the __float128 keyword. 531 532mfloat128-hardware 533Target Report Mask(FLOAT128_HW) Var(rs6000_isa_flags) 534Enable using IEEE 128-bit floating point instructions. 535 536mfloat128-convert 537Target Undocumented Mask(FLOAT128_CVT) Var(rs6000_isa_flags) 538Enable default conversions between __float128 & long double. 539 540mstack-protector-guard= 541Target RejectNegative Joined Enum(stack_protector_guard) Var(rs6000_stack_protector_guard) Init(SSP_TLS) 542Use given stack-protector guard. 543 544Enum 545Name(stack_protector_guard) Type(enum stack_protector_guard) 546Valid arguments to -mstack-protector-guard=: 547 548EnumValue 549Enum(stack_protector_guard) String(tls) Value(SSP_TLS) 550 551EnumValue 552Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL) 553 554mstack-protector-guard-reg= 555Target RejectNegative Joined Var(rs6000_stack_protector_guard_reg_str) 556Use the given base register for addressing the stack-protector guard. 557 558TargetVariable 559int rs6000_stack_protector_guard_reg = 0 560 561mstack-protector-guard-offset= 562Target RejectNegative Joined Integer Var(rs6000_stack_protector_guard_offset_str) 563Use the given offset for addressing the stack-protector guard. 564 565TargetVariable 566long rs6000_stack_protector_guard_offset = 0 567 568;; -mno-speculate-indirect-jumps adds deliberate misprediction to indirect 569;; branches via the CTR. 570mspeculate-indirect-jumps 571Target Undocumented Var(rs6000_speculate_indirect_jumps) Init(1) Save 572