1;; Machine description for IBM RISC System 6000 (POWER) for GNU C compiler 2;; Copyright (C) 1990-2013 Free Software Foundation, Inc. 3;; Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 22 23;; 24;; REGNOS 25;; 26 27(define_constants 28 [(FIRST_GPR_REGNO 0) 29 (STACK_POINTER_REGNUM 1) 30 (TOC_REGNUM 2) 31 (STATIC_CHAIN_REGNUM 11) 32 (HARD_FRAME_POINTER_REGNUM 31) 33 (LAST_GPR_REGNO 31) 34 (FIRST_FPR_REGNO 32) 35 (LAST_FPR_REGNO 63) 36 (LR_REGNO 65) 37 (CTR_REGNO 66) 38 (ARG_POINTER_REGNUM 67) 39 (CR0_REGNO 68) 40 (CR1_REGNO 69) 41 (CR2_REGNO 70) 42 (CR3_REGNO 71) 43 (CR4_REGNO 72) 44 (CR5_REGNO 73) 45 (CR6_REGNO 74) 46 (CR7_REGNO 75) 47 (MAX_CR_REGNO 75) 48 (CA_REGNO 76) 49 (FIRST_ALTIVEC_REGNO 77) 50 (LAST_ALTIVEC_REGNO 108) 51 (VRSAVE_REGNO 109) 52 (VSCR_REGNO 110) 53 (SPE_ACC_REGNO 111) 54 (SPEFSCR_REGNO 112) 55 (FRAME_POINTER_REGNUM 113) 56 (TFHAR_REGNO 114) 57 (TFIAR_REGNO 115) 58 (TEXASR_REGNO 116) 59 ]) 60 61;; 62;; UNSPEC usage 63;; 64 65(define_c_enum "unspec" 66 [UNSPEC_FRSP ; frsp for POWER machines 67 UNSPEC_PROBE_STACK ; probe stack memory reference 68 UNSPEC_TOCPTR ; address of a word pointing to the TOC 69 UNSPEC_TOC ; address of the TOC (more-or-less) 70 UNSPEC_MOVSI_GOT 71 UNSPEC_MV_CR_OV ; move_from_CR_ov_bit 72 UNSPEC_FCTIWZ 73 UNSPEC_FRIM 74 UNSPEC_FRIN 75 UNSPEC_FRIP 76 UNSPEC_FRIZ 77 UNSPEC_LD_MPIC ; load_macho_picbase 78 UNSPEC_MPIC_CORRECT ; macho_correct_pic 79 UNSPEC_TLSGD 80 UNSPEC_TLSLD 81 UNSPEC_MOVESI_FROM_CR 82 UNSPEC_MOVESI_TO_CR 83 UNSPEC_TLSDTPREL 84 UNSPEC_TLSDTPRELHA 85 UNSPEC_TLSDTPRELLO 86 UNSPEC_TLSGOTDTPREL 87 UNSPEC_TLSTPREL 88 UNSPEC_TLSTPRELHA 89 UNSPEC_TLSTPRELLO 90 UNSPEC_TLSGOTTPREL 91 UNSPEC_TLSTLS 92 UNSPEC_FIX_TRUNC_TF ; fadd, rounding towards zero 93 UNSPEC_MV_CR_GT ; move_from_CR_gt_bit 94 UNSPEC_STFIWX 95 UNSPEC_POPCNTB 96 UNSPEC_FRES 97 UNSPEC_SP_SET 98 UNSPEC_SP_TEST 99 UNSPEC_SYNC 100 UNSPEC_LWSYNC 101 UNSPEC_SYNC_OP 102 UNSPEC_ATOMIC 103 UNSPEC_CMPXCHG 104 UNSPEC_XCHG 105 UNSPEC_AND 106 UNSPEC_DLMZB 107 UNSPEC_DLMZB_CR 108 UNSPEC_DLMZB_STRLEN 109 UNSPEC_RSQRT 110 UNSPEC_TOCREL 111 UNSPEC_MACHOPIC_OFFSET 112 UNSPEC_BPERM 113 UNSPEC_COPYSIGN 114 UNSPEC_PARITY 115 UNSPEC_FCTIW 116 UNSPEC_FCTID 117 UNSPEC_LFIWAX 118 UNSPEC_LFIWZX 119 UNSPEC_FCTIWUZ 120 UNSPEC_GRP_END_NOP 121 UNSPEC_P8V_FMRGOW 122 UNSPEC_P8V_MTVSRWZ 123 UNSPEC_P8V_RELOAD_FROM_GPR 124 UNSPEC_P8V_MTVSRD 125 UNSPEC_P8V_XXPERMDI 126 UNSPEC_P8V_RELOAD_FROM_VSX 127 UNSPEC_ADDG6S 128 UNSPEC_CDTBCD 129 UNSPEC_CBCDTD 130 UNSPEC_DIVE 131 UNSPEC_DIVEO 132 UNSPEC_DIVEU 133 UNSPEC_DIVEUO 134 UNSPEC_UNPACK_128BIT 135 UNSPEC_PACK_128BIT 136 UNSPEC_LSQ 137 UNSPEC_FUSION_GPR 138 ]) 139 140;; 141;; UNSPEC_VOLATILE usage 142;; 143 144(define_c_enum "unspecv" 145 [UNSPECV_BLOCK 146 UNSPECV_LL ; load-locked 147 UNSPECV_SC ; store-conditional 148 UNSPECV_PROBE_STACK_RANGE ; probe range of stack addresses 149 UNSPECV_EH_RR ; eh_reg_restore 150 UNSPECV_ISYNC ; isync instruction 151 UNSPECV_MFTB ; move from time base 152 ]) 153 154 155;; Define an insn type attribute. This is used in function unit delay 156;; computations. 157(define_attr "type" "integer,two,three,load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,store,store_ux,store_u,fpload,fpload_ux,fpload_u,fpstore,fpstore_ux,fpstore_u,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,insert_word,branch,cmp,fast_compare,compare,var_delayed_compare,delayed_compare,imul_compare,lmul_compare,fpcompare,cr_logical,delayed_cr,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,brinc,vecsimple,veccomplex,vecdiv,veccmp,veccmpsimple,vecperm,vecfloat,vecfdiv,vecdouble,isync,sync,load_l,store_c,shift,trap,insert_dword,var_shift_rotate,cntlz,exts,mffgpr,mftgpr,isel,popcnt,crypto,htm" 158 (const_string "integer")) 159 160;; Define floating point instruction sub-types for use with Xfpu.md 161(define_attr "fp_type" "fp_default,fp_addsub_s,fp_addsub_d,fp_mul_s,fp_mul_d,fp_div_s,fp_div_d,fp_maddsub_s,fp_maddsub_d,fp_sqrt_s,fp_sqrt_d" (const_string "fp_default")) 162 163;; Length (in bytes). 164; '(pc)' in the following doesn't include the instruction itself; it is 165; calculated as if the instruction had zero size. 166(define_attr "length" "" 167 (if_then_else (eq_attr "type" "branch") 168 (if_then_else (and (ge (minus (match_dup 0) (pc)) 169 (const_int -32768)) 170 (lt (minus (match_dup 0) (pc)) 171 (const_int 32764))) 172 (const_int 4) 173 (const_int 8)) 174 (const_int 4))) 175 176;; Processor type -- this attribute must exactly match the processor_type 177;; enumeration in rs6000.h. 178 179(define_attr "cpu" "rs64a,mpccore,ppc403,ppc405,ppc440,ppc476,ppc601,ppc603,ppc604,ppc604e,ppc620,ppc630,ppc750,ppc7400,ppc7450,ppc8540,ppc8548,ppce300c2,ppce300c3,ppce500mc,ppce500mc64,ppce5500,ppce6500,power4,power5,power6,power7,cell,ppca2,titan,power8" 180 (const (symbol_ref "rs6000_cpu_attr"))) 181 182 183;; If this instruction is microcoded on the CELL processor 184; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded 185(define_attr "cell_micro" "not,conditional,always" 186 (if_then_else (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,load_ext,load_ext_ux,var_shift_rotate,var_delayed_compare") 187 (const_string "always") 188 (const_string "not"))) 189 190(automata_option "ndfa") 191 192(include "rs64.md") 193(include "mpc.md") 194(include "40x.md") 195(include "440.md") 196(include "476.md") 197(include "601.md") 198(include "603.md") 199(include "6xx.md") 200(include "7xx.md") 201(include "7450.md") 202(include "8540.md") 203(include "e300c2c3.md") 204(include "e500mc.md") 205(include "e500mc64.md") 206(include "e5500.md") 207(include "e6500.md") 208(include "power4.md") 209(include "power5.md") 210(include "power6.md") 211(include "power7.md") 212(include "power8.md") 213(include "cell.md") 214(include "xfpu.md") 215(include "a2.md") 216(include "titan.md") 217 218(include "predicates.md") 219(include "constraints.md") 220 221(include "darwin.md") 222 223 224;; Mode iterators 225 226; This mode iterator allows :GPR to be used to indicate the allowable size 227; of whole values in GPRs. 228(define_mode_iterator GPR [SI (DI "TARGET_POWERPC64")]) 229 230; Any supported integer mode. 231(define_mode_iterator INT [QI HI SI DI TI PTI]) 232 233; Any supported integer mode that fits in one register. 234(define_mode_iterator INT1 [QI HI SI (DI "TARGET_POWERPC64")]) 235 236; extend modes for DImode 237(define_mode_iterator QHSI [QI HI SI]) 238 239; QImode or HImode for small atomic ops 240(define_mode_iterator QHI [QI HI]) 241 242; HImode or SImode for sign extended fusion ops 243(define_mode_iterator HSI [HI SI]) 244 245; SImode or DImode, even if DImode doesn't fit in GPRs. 246(define_mode_iterator SDI [SI DI]) 247 248; The size of a pointer. Also, the size of the value that a record-condition 249; (one with a '.') will compare; and the size used for arithmetic carries. 250(define_mode_iterator P [(SI "TARGET_32BIT") (DI "TARGET_64BIT")]) 251 252; Iterator to add PTImode along with TImode (TImode can go in VSX registers, 253; PTImode is GPR only) 254(define_mode_iterator TI2 [TI PTI]) 255 256; Any hardware-supported floating-point mode 257(define_mode_iterator FP [ 258 (SF "TARGET_HARD_FLOAT 259 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) || TARGET_E500_SINGLE)") 260 (DF "TARGET_HARD_FLOAT 261 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)") 262 (TF "!TARGET_IEEEQUAD 263 && TARGET_HARD_FLOAT 264 && (TARGET_FPRS || TARGET_E500_DOUBLE) 265 && TARGET_LONG_DOUBLE_128") 266 (DD "TARGET_DFP") 267 (TD "TARGET_DFP")]) 268 269; Any fma capable floating-point mode. 270(define_mode_iterator FMA_F [ 271 (SF "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT") 272 (DF "(TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT) 273 || VECTOR_UNIT_VSX_P (DFmode)") 274 (V2SF "TARGET_PAIRED_FLOAT") 275 (V4SF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V4SFmode)") 276 (V2DF "VECTOR_UNIT_ALTIVEC_OR_VSX_P (V2DFmode)") 277 ]) 278 279; Floating point move iterators to combine binary and decimal moves 280(define_mode_iterator FMOVE32 [SF SD]) 281(define_mode_iterator FMOVE64 [DF DD]) 282(define_mode_iterator FMOVE64X [DI DF DD]) 283(define_mode_iterator FMOVE128 [(TF "!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128") 284 (TD "TARGET_HARD_FLOAT && TARGET_FPRS")]) 285 286; Iterators for 128 bit types for direct move 287(define_mode_iterator FMOVE128_GPR [(TI "TARGET_VSX_TIMODE") 288 (V16QI "") 289 (V8HI "") 290 (V4SI "") 291 (V4SF "") 292 (V2DI "") 293 (V2DF "") 294 (V1TI "")]) 295 296; Whether a floating point move is ok, don't allow SD without hardware FP 297(define_mode_attr fmove_ok [(SF "") 298 (DF "") 299 (SD "TARGET_HARD_FLOAT && TARGET_FPRS") 300 (DD "")]) 301 302; Convert REAL_VALUE to the appropriate bits 303(define_mode_attr real_value_to_target [(SF "REAL_VALUE_TO_TARGET_SINGLE") 304 (DF "REAL_VALUE_TO_TARGET_DOUBLE") 305 (SD "REAL_VALUE_TO_TARGET_DECIMAL32") 306 (DD "REAL_VALUE_TO_TARGET_DECIMAL64")]) 307 308; Definitions for load to 32-bit fpr register 309(define_mode_attr f32_lr [(SF "f") (SD "wz")]) 310(define_mode_attr f32_lm [(SF "m") (SD "Z")]) 311(define_mode_attr f32_li [(SF "lfs%U1%X1 %0,%1") (SD "lfiwzx %0,%y1")]) 312(define_mode_attr f32_lv [(SF "lxsspx %x0,%y1") (SD "lxsiwzx %x0,%y1")]) 313 314; Definitions for store from 32-bit fpr register 315(define_mode_attr f32_sr [(SF "f") (SD "wx")]) 316(define_mode_attr f32_sm [(SF "m") (SD "Z")]) 317(define_mode_attr f32_si [(SF "stfs%U0%X0 %1,%0") (SD "stfiwx %1,%y0")]) 318(define_mode_attr f32_sv [(SF "stxsspx %x1,%y0") (SD "stxsiwzx %x1,%y0")]) 319 320; Definitions for 32-bit fpr direct move 321; At present, the decimal modes are not allowed in the traditional altivec 322; registers, so restrict the constraints to just the traditional FPRs. 323(define_mode_attr f32_dm [(SF "wn") (SD "wh")]) 324 325; Definitions for 32-bit VSX 326(define_mode_attr f32_vsx [(SF "ww") (SD "wn")]) 327 328; Definitions for 32-bit use of altivec registers 329(define_mode_attr f32_av [(SF "wu") (SD "wn")]) 330 331; Definitions for 64-bit VSX 332(define_mode_attr f64_vsx [(DF "ws") (DD "wn")]) 333 334; Definitions for 64-bit direct move 335(define_mode_attr f64_dm [(DF "wk") (DD "wh")]) 336 337; Definitions for 64-bit use of altivec registers 338(define_mode_attr f64_av [(DF "wv") (DD "wn")]) 339 340; These modes do not fit in integer registers in 32-bit mode. 341; but on e500v2, the gpr are 64 bit registers 342(define_mode_iterator DIFD [DI (DF "!TARGET_E500_DOUBLE") DD]) 343 344; Iterator for reciprocal estimate instructions 345(define_mode_iterator RECIPF [SF DF V4SF V2DF]) 346 347; Iterator for just SF/DF 348(define_mode_iterator SFDF [SF DF]) 349 350; SF/DF suffix for traditional floating instructions 351(define_mode_attr Ftrad [(SF "s") (DF "")]) 352 353; SF/DF suffix for VSX instructions 354(define_mode_attr Fvsx [(SF "sp") (DF "dp")]) 355 356; SF/DF constraint for arithmetic on traditional floating point registers 357(define_mode_attr Ff [(SF "f") (DF "d")]) 358 359; SF/DF constraint for arithmetic on VSX registers 360(define_mode_attr Fv [(SF "wy") (DF "ws")]) 361 362; s/d suffix for things like fp_addsub_s/fp_addsub_d 363(define_mode_attr Fs [(SF "s") (DF "d")]) 364 365; FRE/FRES support 366(define_mode_attr Ffre [(SF "fres") (DF "fre")]) 367(define_mode_attr FFRE [(SF "FRES") (DF "FRE")]) 368 369; Conditional returns. 370(define_code_iterator any_return [return simple_return]) 371(define_code_attr return_pred [(return "direct_return ()") 372 (simple_return "1")]) 373(define_code_attr return_str [(return "") (simple_return "simple_")]) 374 375; Various instructions that come in SI and DI forms. 376; A generic w/d attribute, for things like cmpw/cmpd. 377(define_mode_attr wd [(QI "b") 378 (HI "h") 379 (SI "w") 380 (DI "d") 381 (V16QI "b") 382 (V8HI "h") 383 (V4SI "w") 384 (V2DI "d")]) 385 386; DImode bits 387(define_mode_attr dbits [(QI "56") (HI "48") (SI "32")]) 388 389;; ISEL/ISEL64 target selection 390(define_mode_attr sel [(SI "") (DI "64")]) 391 392;; Suffix for reload patterns 393(define_mode_attr ptrsize [(SI "32bit") 394 (DI "64bit")]) 395 396(define_mode_attr tptrsize [(SI "TARGET_32BIT") 397 (DI "TARGET_64BIT")]) 398 399(define_mode_attr mptrsize [(SI "si") 400 (DI "di")]) 401 402(define_mode_attr ptrload [(SI "lwz") 403 (DI "ld")]) 404 405(define_mode_attr ptrm [(SI "m") 406 (DI "Y")]) 407 408(define_mode_attr rreg [(SF "f") 409 (DF "ws") 410 (TF "f") 411 (TD "f") 412 (V4SF "wf") 413 (V2DF "wd")]) 414 415(define_mode_attr rreg2 [(SF "f") 416 (DF "d")]) 417 418(define_mode_attr SI_CONVERT_FP [(SF "TARGET_FCFIDS") 419 (DF "TARGET_FCFID")]) 420 421(define_mode_attr E500_CONVERT [(SF "!TARGET_FPRS") 422 (DF "TARGET_E500_DOUBLE")]) 423 424(define_mode_attr TARGET_FLOAT [(SF "TARGET_SINGLE_FLOAT") 425 (DF "TARGET_DOUBLE_FLOAT")]) 426 427;; Mode iterator for logical operations on 128-bit types 428(define_mode_iterator BOOL_128 [TI 429 PTI 430 (V16QI "TARGET_ALTIVEC") 431 (V8HI "TARGET_ALTIVEC") 432 (V4SI "TARGET_ALTIVEC") 433 (V4SF "TARGET_ALTIVEC") 434 (V2DI "TARGET_ALTIVEC") 435 (V2DF "TARGET_ALTIVEC") 436 (V1TI "TARGET_ALTIVEC")]) 437 438;; For the GPRs we use 3 constraints for register outputs, two that are the 439;; same as the output register, and a third where the output register is an 440;; early clobber, so we don't have to deal with register overlaps. For the 441;; vector types, we prefer to use the vector registers. For TI mode, allow 442;; either. 443 444;; Mode attribute for boolean operation register constraints for output 445(define_mode_attr BOOL_REGS_OUTPUT [(TI "&r,r,r,wt,v") 446 (PTI "&r,r,r") 447 (V16QI "wa,v,&?r,?r,?r") 448 (V8HI "wa,v,&?r,?r,?r") 449 (V4SI "wa,v,&?r,?r,?r") 450 (V4SF "wa,v,&?r,?r,?r") 451 (V2DI "wa,v,&?r,?r,?r") 452 (V2DF "wa,v,&?r,?r,?r") 453 (V1TI "wa,v,&?r,?r,?r")]) 454 455;; Mode attribute for boolean operation register constraints for operand1 456(define_mode_attr BOOL_REGS_OP1 [(TI "r,0,r,wt,v") 457 (PTI "r,0,r") 458 (V16QI "wa,v,r,0,r") 459 (V8HI "wa,v,r,0,r") 460 (V4SI "wa,v,r,0,r") 461 (V4SF "wa,v,r,0,r") 462 (V2DI "wa,v,r,0,r") 463 (V2DF "wa,v,r,0,r") 464 (V1TI "wa,v,r,0,r")]) 465 466;; Mode attribute for boolean operation register constraints for operand2 467(define_mode_attr BOOL_REGS_OP2 [(TI "r,r,0,wt,v") 468 (PTI "r,r,0") 469 (V16QI "wa,v,r,r,0") 470 (V8HI "wa,v,r,r,0") 471 (V4SI "wa,v,r,r,0") 472 (V4SF "wa,v,r,r,0") 473 (V2DI "wa,v,r,r,0") 474 (V2DF "wa,v,r,r,0") 475 (V1TI "wa,v,r,r,0")]) 476 477;; Mode attribute for boolean operation register constraints for operand1 478;; for one_cmpl. To simplify things, we repeat the constraint where 0 479;; is used for operand1 or operand2 480(define_mode_attr BOOL_REGS_UNARY [(TI "r,0,0,wt,v") 481 (PTI "r,0,0") 482 (V16QI "wa,v,r,0,0") 483 (V8HI "wa,v,r,0,0") 484 (V4SI "wa,v,r,0,0") 485 (V4SF "wa,v,r,0,0") 486 (V2DI "wa,v,r,0,0") 487 (V2DF "wa,v,r,0,0") 488 (V1TI "wa,v,r,0,0")]) 489 490;; Mode attribute for the clobber of CC0 for AND expansion. 491;; For the 128-bit types, we never do AND immediate, but we need to 492;; get the correct number of X's for the number of operands. 493(define_mode_attr BOOL_REGS_AND_CR0 [(TI "X,X,X,X,X") 494 (PTI "X,X,X") 495 (V16QI "X,X,X,X,X") 496 (V8HI "X,X,X,X,X") 497 (V4SI "X,X,X,X,X") 498 (V4SF "X,X,X,X,X") 499 (V2DI "X,X,X,X,X") 500 (V2DF "X,X,X,X,X") 501 (V1TI "X,X,X,X,X")]) 502 503;; Mode attribute to give the correct type for integer divides 504(define_mode_attr idiv_ldiv [(SI "idiv") 505 (DI "ldiv")]) 506 507 508;; Start with fixed-point load and store insns. Here we put only the more 509;; complex forms. Basic data transfer is done later. 510 511(define_expand "zero_extend<mode>di2" 512 [(set (match_operand:DI 0 "gpc_reg_operand" "") 513 (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")))] 514 "TARGET_POWERPC64" 515 "") 516 517(define_insn "*zero_extend<mode>di2_internal1" 518 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 519 (zero_extend:DI (match_operand:QHSI 1 "reg_or_mem_operand" "m,r")))] 520 "TARGET_POWERPC64 && (<MODE>mode != SImode || !TARGET_LFIWZX)" 521 "@ 522 l<wd>z%U1%X1 %0,%1 523 rldicl %0,%1,0,<dbits>" 524 [(set_attr_alternative "type" 525 [(if_then_else 526 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 527 (const_string "load_ux") 528 (if_then_else 529 (match_test "update_address_mem (operands[1], VOIDmode)") 530 (const_string "load_u") 531 (const_string "load"))) 532 (const_string "*")])]) 533 534(define_insn "*zero_extend<mode>di2_internal2" 535 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 536 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) 537 (const_int 0))) 538 (clobber (match_scratch:DI 2 "=r,r"))] 539 "TARGET_64BIT" 540 "@ 541 rldicl. %2,%1,0,<dbits> 542 #" 543 [(set_attr "type" "compare") 544 (set_attr "length" "4,8")]) 545 546(define_split 547 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 548 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) 549 (const_int 0))) 550 (clobber (match_scratch:DI 2 ""))] 551 "TARGET_POWERPC64 && reload_completed" 552 [(set (match_dup 2) 553 (zero_extend:DI (match_dup 1))) 554 (set (match_dup 0) 555 (compare:CC (match_dup 2) 556 (const_int 0)))] 557 "") 558 559(define_insn "*zero_extend<mode>di2_internal3" 560 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 561 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "r,r")) 562 (const_int 0))) 563 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 564 (zero_extend:DI (match_dup 1)))] 565 "TARGET_64BIT" 566 "@ 567 rldicl. %0,%1,0,<dbits> 568 #" 569 [(set_attr "type" "compare") 570 (set_attr "length" "4,8")]) 571 572(define_split 573 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 574 (compare:CC (zero_extend:DI (match_operand:QHSI 1 "gpc_reg_operand" "")) 575 (const_int 0))) 576 (set (match_operand:DI 0 "gpc_reg_operand" "") 577 (zero_extend:DI (match_dup 1)))] 578 "TARGET_POWERPC64 && reload_completed" 579 [(set (match_dup 0) 580 (zero_extend:DI (match_dup 1))) 581 (set (match_dup 2) 582 (compare:CC (match_dup 0) 583 (const_int 0)))] 584 "") 585 586(define_insn "*zero_extendsidi2_lfiwzx" 587 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wz,!wu") 588 (zero_extend:DI (match_operand:SI 1 "reg_or_mem_operand" "m,r,r,Z,Z")))] 589 "TARGET_POWERPC64 && TARGET_LFIWZX" 590 "@ 591 lwz%U1%X1 %0,%1 592 rldicl %0,%1,0,32 593 mtvsrwz %x0,%1 594 lfiwzx %0,%y1 595 lxsiwzx %x0,%y1" 596 [(set_attr_alternative "type" 597 [(if_then_else 598 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 599 (const_string "load_ux") 600 (if_then_else 601 (match_test "update_address_mem (operands[1], VOIDmode)") 602 (const_string "load_u") 603 (const_string "load"))) 604 (const_string "*") 605 (const_string "mffgpr") 606 (const_string "fpload") 607 (const_string "fpload")])]) 608 609(define_insn "extendqidi2" 610 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 611 (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r")))] 612 "TARGET_POWERPC64" 613 "extsb %0,%1" 614 [(set_attr "type" "exts")]) 615 616(define_insn "" 617 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 618 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 619 (const_int 0))) 620 (clobber (match_scratch:DI 2 "=r,r"))] 621 "TARGET_64BIT" 622 "@ 623 extsb. %2,%1 624 #" 625 [(set_attr "type" "compare") 626 (set_attr "length" "4,8")]) 627 628(define_split 629 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 630 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 631 (const_int 0))) 632 (clobber (match_scratch:DI 2 ""))] 633 "TARGET_POWERPC64 && reload_completed" 634 [(set (match_dup 2) 635 (sign_extend:DI (match_dup 1))) 636 (set (match_dup 0) 637 (compare:CC (match_dup 2) 638 (const_int 0)))] 639 "") 640 641(define_insn "" 642 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 643 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 644 (const_int 0))) 645 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 646 (sign_extend:DI (match_dup 1)))] 647 "TARGET_64BIT" 648 "@ 649 extsb. %0,%1 650 #" 651 [(set_attr "type" "compare") 652 (set_attr "length" "4,8")]) 653 654(define_split 655 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 656 (compare:CC (sign_extend:DI (match_operand:QI 1 "gpc_reg_operand" "")) 657 (const_int 0))) 658 (set (match_operand:DI 0 "gpc_reg_operand" "") 659 (sign_extend:DI (match_dup 1)))] 660 "TARGET_POWERPC64 && reload_completed" 661 [(set (match_dup 0) 662 (sign_extend:DI (match_dup 1))) 663 (set (match_dup 2) 664 (compare:CC (match_dup 0) 665 (const_int 0)))] 666 "") 667 668(define_expand "extendhidi2" 669 [(set (match_operand:DI 0 "gpc_reg_operand" "") 670 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")))] 671 "TARGET_POWERPC64" 672 "") 673 674(define_insn "" 675 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 676 (sign_extend:DI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 677 "TARGET_POWERPC64 && rs6000_gen_cell_microcode" 678 "@ 679 lha%U1%X1 %0,%1 680 extsh %0,%1" 681 [(set_attr_alternative "type" 682 [(if_then_else 683 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 684 (const_string "load_ext_ux") 685 (if_then_else 686 (match_test "update_address_mem (operands[1], VOIDmode)") 687 (const_string "load_ext_u") 688 (const_string "load_ext"))) 689 (const_string "exts")])]) 690 691(define_insn "" 692 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 693 (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r")))] 694 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" 695 "extsh %0,%1" 696 [(set_attr "type" "exts")]) 697 698(define_insn "" 699 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 700 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 701 (const_int 0))) 702 (clobber (match_scratch:DI 2 "=r,r"))] 703 "TARGET_64BIT" 704 "@ 705 extsh. %2,%1 706 #" 707 [(set_attr "type" "compare") 708 (set_attr "length" "4,8")]) 709 710(define_split 711 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 712 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 713 (const_int 0))) 714 (clobber (match_scratch:DI 2 ""))] 715 "TARGET_POWERPC64 && reload_completed" 716 [(set (match_dup 2) 717 (sign_extend:DI (match_dup 1))) 718 (set (match_dup 0) 719 (compare:CC (match_dup 2) 720 (const_int 0)))] 721 "") 722 723(define_insn "" 724 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 725 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 726 (const_int 0))) 727 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 728 (sign_extend:DI (match_dup 1)))] 729 "TARGET_64BIT" 730 "@ 731 extsh. %0,%1 732 #" 733 [(set_attr "type" "compare") 734 (set_attr "length" "4,8")]) 735 736(define_split 737 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 738 (compare:CC (sign_extend:DI (match_operand:HI 1 "gpc_reg_operand" "")) 739 (const_int 0))) 740 (set (match_operand:DI 0 "gpc_reg_operand" "") 741 (sign_extend:DI (match_dup 1)))] 742 "TARGET_POWERPC64 && reload_completed" 743 [(set (match_dup 0) 744 (sign_extend:DI (match_dup 1))) 745 (set (match_dup 2) 746 (compare:CC (match_dup 0) 747 (const_int 0)))] 748 "") 749 750(define_expand "extendsidi2" 751 [(set (match_operand:DI 0 "gpc_reg_operand" "") 752 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")))] 753 "TARGET_POWERPC64" 754 "") 755 756(define_insn "*extendsidi2_lfiwax" 757 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,??wj,!wl,!wu") 758 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r,r,Z,Z")))] 759 "TARGET_POWERPC64 && TARGET_LFIWAX" 760 "@ 761 lwa%U1%X1 %0,%1 762 extsw %0,%1 763 mtvsrwa %x0,%1 764 lfiwax %0,%y1 765 lxsiwax %x0,%y1" 766 [(set_attr_alternative "type" 767 [(if_then_else 768 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 769 (const_string "load_ext_ux") 770 (if_then_else 771 (match_test "update_address_mem (operands[1], VOIDmode)") 772 (const_string "load_ext_u") 773 (const_string "load_ext"))) 774 (const_string "exts") 775 (const_string "mffgpr") 776 (const_string "fpload") 777 (const_string "fpload")])]) 778 779(define_insn "*extendsidi2_nocell" 780 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 781 (sign_extend:DI (match_operand:SI 1 "lwa_operand" "Y,r")))] 782 "TARGET_POWERPC64 && rs6000_gen_cell_microcode && !TARGET_LFIWAX" 783 "@ 784 lwa%U1%X1 %0,%1 785 extsw %0,%1" 786 [(set_attr_alternative "type" 787 [(if_then_else 788 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 789 (const_string "load_ext_ux") 790 (if_then_else 791 (match_test "update_address_mem (operands[1], VOIDmode)") 792 (const_string "load_ext_u") 793 (const_string "load_ext"))) 794 (const_string "exts")])]) 795 796(define_insn "*extendsidi2_nocell" 797 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 798 (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r")))] 799 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" 800 "extsw %0,%1" 801 [(set_attr "type" "exts")]) 802 803(define_insn "" 804 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 805 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 806 (const_int 0))) 807 (clobber (match_scratch:DI 2 "=r,r"))] 808 "TARGET_64BIT" 809 "@ 810 extsw. %2,%1 811 #" 812 [(set_attr "type" "compare") 813 (set_attr "length" "4,8")]) 814 815(define_split 816 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 817 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 818 (const_int 0))) 819 (clobber (match_scratch:DI 2 ""))] 820 "TARGET_POWERPC64 && reload_completed" 821 [(set (match_dup 2) 822 (sign_extend:DI (match_dup 1))) 823 (set (match_dup 0) 824 (compare:CC (match_dup 2) 825 (const_int 0)))] 826 "") 827 828(define_insn "" 829 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 830 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 831 (const_int 0))) 832 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 833 (sign_extend:DI (match_dup 1)))] 834 "TARGET_64BIT" 835 "@ 836 extsw. %0,%1 837 #" 838 [(set_attr "type" "compare") 839 (set_attr "length" "4,8")]) 840 841(define_split 842 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 843 (compare:CC (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 844 (const_int 0))) 845 (set (match_operand:DI 0 "gpc_reg_operand" "") 846 (sign_extend:DI (match_dup 1)))] 847 "TARGET_POWERPC64 && reload_completed" 848 [(set (match_dup 0) 849 (sign_extend:DI (match_dup 1))) 850 (set (match_dup 2) 851 (compare:CC (match_dup 0) 852 (const_int 0)))] 853 "") 854 855(define_expand "zero_extendqisi2" 856 [(set (match_operand:SI 0 "gpc_reg_operand" "") 857 (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")))] 858 "" 859 "") 860 861(define_insn "" 862 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 863 (zero_extend:SI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 864 "" 865 "@ 866 lbz%U1%X1 %0,%1 867 rlwinm %0,%1,0,0xff" 868 [(set_attr_alternative "type" 869 [(if_then_else 870 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 871 (const_string "load_ux") 872 (if_then_else 873 (match_test "update_address_mem (operands[1], VOIDmode)") 874 (const_string "load_u") 875 (const_string "load"))) 876 (const_string "*")])]) 877 878(define_insn "" 879 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 880 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 881 (const_int 0))) 882 (clobber (match_scratch:SI 2 "=r,r"))] 883 "" 884 "@ 885 andi. %2,%1,0xff 886 #" 887 [(set_attr "type" "fast_compare,compare") 888 (set_attr "length" "4,8")]) 889 890(define_split 891 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 892 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 893 (const_int 0))) 894 (clobber (match_scratch:SI 2 ""))] 895 "reload_completed" 896 [(set (match_dup 2) 897 (zero_extend:SI (match_dup 1))) 898 (set (match_dup 0) 899 (compare:CC (match_dup 2) 900 (const_int 0)))] 901 "") 902 903(define_insn "" 904 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 905 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 906 (const_int 0))) 907 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 908 (zero_extend:SI (match_dup 1)))] 909 "" 910 "@ 911 andi. %0,%1,0xff 912 #" 913 [(set_attr "type" "fast_compare,compare") 914 (set_attr "length" "4,8")]) 915 916(define_split 917 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 918 (compare:CC (zero_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 919 (const_int 0))) 920 (set (match_operand:SI 0 "gpc_reg_operand" "") 921 (zero_extend:SI (match_dup 1)))] 922 "reload_completed" 923 [(set (match_dup 0) 924 (zero_extend:SI (match_dup 1))) 925 (set (match_dup 2) 926 (compare:CC (match_dup 0) 927 (const_int 0)))] 928 "") 929 930(define_insn "extendqisi2" 931 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 932 (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r")))] 933 "" 934 "extsb %0,%1" 935 [(set_attr "type" "exts")]) 936 937(define_insn "" 938 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 939 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 940 (const_int 0))) 941 (clobber (match_scratch:SI 2 "=r,r"))] 942 "" 943 "@ 944 extsb. %2,%1 945 #" 946 [(set_attr "type" "compare") 947 (set_attr "length" "4,8")]) 948 949(define_split 950 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 951 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 952 (const_int 0))) 953 (clobber (match_scratch:SI 2 ""))] 954 "reload_completed" 955 [(set (match_dup 2) 956 (sign_extend:SI (match_dup 1))) 957 (set (match_dup 0) 958 (compare:CC (match_dup 2) 959 (const_int 0)))] 960 "") 961 962(define_insn "" 963 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 964 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 965 (const_int 0))) 966 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 967 (sign_extend:SI (match_dup 1)))] 968 "" 969 "@ 970 extsb. %0,%1 971 #" 972 [(set_attr "type" "compare") 973 (set_attr "length" "4,8")]) 974 975(define_split 976 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 977 (compare:CC (sign_extend:SI (match_operand:QI 1 "gpc_reg_operand" "")) 978 (const_int 0))) 979 (set (match_operand:SI 0 "gpc_reg_operand" "") 980 (sign_extend:SI (match_dup 1)))] 981 "reload_completed" 982 [(set (match_dup 0) 983 (sign_extend:SI (match_dup 1))) 984 (set (match_dup 2) 985 (compare:CC (match_dup 0) 986 (const_int 0)))] 987 "") 988 989(define_insn "" 990 [(set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 991 (zero_extend:HI (match_operand:QI 1 "reg_or_mem_operand" "m,r")))] 992 "" 993 "@ 994 lbz%U1%X1 %0,%1 995 rlwinm %0,%1,0,0xff" 996 [(set_attr_alternative "type" 997 [(if_then_else 998 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 999 (const_string "load_ux") 1000 (if_then_else 1001 (match_test "update_address_mem (operands[1], VOIDmode)") 1002 (const_string "load_u") 1003 (const_string "load"))) 1004 (const_string "*")])]) 1005 1006(define_insn "" 1007 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1008 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1009 (const_int 0))) 1010 (clobber (match_scratch:HI 2 "=r,r"))] 1011 "" 1012 "@ 1013 andi. %2,%1,0xff 1014 #" 1015 [(set_attr "type" "fast_compare,compare") 1016 (set_attr "length" "4,8")]) 1017 1018(define_split 1019 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 1020 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 1021 (const_int 0))) 1022 (clobber (match_scratch:HI 2 ""))] 1023 "reload_completed" 1024 [(set (match_dup 2) 1025 (zero_extend:HI (match_dup 1))) 1026 (set (match_dup 0) 1027 (compare:CC (match_dup 2) 1028 (const_int 0)))] 1029 "") 1030 1031(define_insn "" 1032 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1033 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1034 (const_int 0))) 1035 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 1036 (zero_extend:HI (match_dup 1)))] 1037 "" 1038 "@ 1039 andi. %0,%1,0xff 1040 #" 1041 [(set_attr "type" "fast_compare,compare") 1042 (set_attr "length" "4,8")]) 1043 1044(define_split 1045 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 1046 (compare:CC (zero_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 1047 (const_int 0))) 1048 (set (match_operand:HI 0 "gpc_reg_operand" "") 1049 (zero_extend:HI (match_dup 1)))] 1050 "reload_completed" 1051 [(set (match_dup 0) 1052 (zero_extend:HI (match_dup 1))) 1053 (set (match_dup 2) 1054 (compare:CC (match_dup 0) 1055 (const_int 0)))] 1056 "") 1057 1058(define_insn "extendqihi2" 1059 [(set (match_operand:HI 0 "gpc_reg_operand" "=r") 1060 (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r")))] 1061 "" 1062 "extsb %0,%1" 1063 [(set_attr "type" "exts")]) 1064 1065(define_insn "" 1066 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1067 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1068 (const_int 0))) 1069 (clobber (match_scratch:HI 2 "=r,r"))] 1070 "" 1071 "@ 1072 extsb. %2,%1 1073 #" 1074 [(set_attr "type" "compare") 1075 (set_attr "length" "4,8")]) 1076 1077(define_split 1078 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 1079 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 1080 (const_int 0))) 1081 (clobber (match_scratch:HI 2 ""))] 1082 "reload_completed" 1083 [(set (match_dup 2) 1084 (sign_extend:HI (match_dup 1))) 1085 (set (match_dup 0) 1086 (compare:CC (match_dup 2) 1087 (const_int 0)))] 1088 "") 1089 1090(define_insn "" 1091 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1092 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "r,r")) 1093 (const_int 0))) 1094 (set (match_operand:HI 0 "gpc_reg_operand" "=r,r") 1095 (sign_extend:HI (match_dup 1)))] 1096 "" 1097 "@ 1098 extsb. %0,%1 1099 #" 1100 [(set_attr "type" "compare") 1101 (set_attr "length" "4,8")]) 1102 1103(define_split 1104 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 1105 (compare:CC (sign_extend:HI (match_operand:QI 1 "gpc_reg_operand" "")) 1106 (const_int 0))) 1107 (set (match_operand:HI 0 "gpc_reg_operand" "") 1108 (sign_extend:HI (match_dup 1)))] 1109 "reload_completed" 1110 [(set (match_dup 0) 1111 (sign_extend:HI (match_dup 1))) 1112 (set (match_dup 2) 1113 (compare:CC (match_dup 0) 1114 (const_int 0)))] 1115 "") 1116 1117(define_expand "zero_extendhisi2" 1118 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1119 (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 1120 "" 1121 "") 1122 1123(define_insn "" 1124 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1125 (zero_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 1126 "" 1127 "@ 1128 lhz%U1%X1 %0,%1 1129 rlwinm %0,%1,0,0xffff" 1130 [(set_attr_alternative "type" 1131 [(if_then_else 1132 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 1133 (const_string "load_ux") 1134 (if_then_else 1135 (match_test "update_address_mem (operands[1], VOIDmode)") 1136 (const_string "load_u") 1137 (const_string "load"))) 1138 (const_string "*")])]) 1139 1140(define_insn "" 1141 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1142 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 1143 (const_int 0))) 1144 (clobber (match_scratch:SI 2 "=r,r"))] 1145 "" 1146 "@ 1147 andi. %2,%1,0xffff 1148 #" 1149 [(set_attr "type" "fast_compare,compare") 1150 (set_attr "length" "4,8")]) 1151 1152(define_split 1153 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 1154 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 1155 (const_int 0))) 1156 (clobber (match_scratch:SI 2 ""))] 1157 "reload_completed" 1158 [(set (match_dup 2) 1159 (zero_extend:SI (match_dup 1))) 1160 (set (match_dup 0) 1161 (compare:CC (match_dup 2) 1162 (const_int 0)))] 1163 "") 1164 1165(define_insn "" 1166 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1167 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 1168 (const_int 0))) 1169 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1170 (zero_extend:SI (match_dup 1)))] 1171 "" 1172 "@ 1173 andi. %0,%1,0xffff 1174 #" 1175 [(set_attr "type" "fast_compare,compare") 1176 (set_attr "length" "4,8")]) 1177 1178(define_split 1179 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 1180 (compare:CC (zero_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 1181 (const_int 0))) 1182 (set (match_operand:SI 0 "gpc_reg_operand" "") 1183 (zero_extend:SI (match_dup 1)))] 1184 "reload_completed" 1185 [(set (match_dup 0) 1186 (zero_extend:SI (match_dup 1))) 1187 (set (match_dup 2) 1188 (compare:CC (match_dup 0) 1189 (const_int 0)))] 1190 "") 1191 1192(define_expand "extendhisi2" 1193 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1194 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")))] 1195 "" 1196 "") 1197 1198(define_insn "" 1199 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1200 (sign_extend:SI (match_operand:HI 1 "reg_or_mem_operand" "m,r")))] 1201 "rs6000_gen_cell_microcode" 1202 "@ 1203 lha%U1%X1 %0,%1 1204 extsh %0,%1" 1205 [(set_attr_alternative "type" 1206 [(if_then_else 1207 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 1208 (const_string "load_ext_ux") 1209 (if_then_else 1210 (match_test "update_address_mem (operands[1], VOIDmode)") 1211 (const_string "load_ext_u") 1212 (const_string "load_ext"))) 1213 (const_string "exts")])]) 1214 1215(define_insn "" 1216 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1217 (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r")))] 1218 "!rs6000_gen_cell_microcode" 1219 "extsh %0,%1" 1220 [(set_attr "type" "exts")]) 1221 1222(define_insn "" 1223 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1224 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 1225 (const_int 0))) 1226 (clobber (match_scratch:SI 2 "=r,r"))] 1227 "" 1228 "@ 1229 extsh. %2,%1 1230 #" 1231 [(set_attr "type" "compare") 1232 (set_attr "length" "4,8")]) 1233 1234(define_split 1235 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 1236 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 1237 (const_int 0))) 1238 (clobber (match_scratch:SI 2 ""))] 1239 "reload_completed" 1240 [(set (match_dup 2) 1241 (sign_extend:SI (match_dup 1))) 1242 (set (match_dup 0) 1243 (compare:CC (match_dup 2) 1244 (const_int 0)))] 1245 "") 1246 1247(define_insn "" 1248 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 1249 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "r,r")) 1250 (const_int 0))) 1251 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 1252 (sign_extend:SI (match_dup 1)))] 1253 "" 1254 "@ 1255 extsh. %0,%1 1256 #" 1257 [(set_attr "type" "compare") 1258 (set_attr "length" "4,8")]) 1259 1260(define_split 1261 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 1262 (compare:CC (sign_extend:SI (match_operand:HI 1 "gpc_reg_operand" "")) 1263 (const_int 0))) 1264 (set (match_operand:SI 0 "gpc_reg_operand" "") 1265 (sign_extend:SI (match_dup 1)))] 1266 "reload_completed" 1267 [(set (match_dup 0) 1268 (sign_extend:SI (match_dup 1))) 1269 (set (match_dup 2) 1270 (compare:CC (match_dup 0) 1271 (const_int 0)))] 1272 "") 1273 1274;; IBM 405, 440, 464 and 476 half-word multiplication operations. 1275 1276(define_insn "*macchwc" 1277 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1278 (compare:CC (plus:SI (mult:SI (ashiftrt:SI 1279 (match_operand:SI 2 "gpc_reg_operand" "r") 1280 (const_int 16)) 1281 (sign_extend:SI 1282 (match_operand:HI 1 "gpc_reg_operand" "r"))) 1283 (match_operand:SI 4 "gpc_reg_operand" "0")) 1284 (const_int 0))) 1285 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1286 (plus:SI (mult:SI (ashiftrt:SI 1287 (match_dup 2) 1288 (const_int 16)) 1289 (sign_extend:SI 1290 (match_dup 1))) 1291 (match_dup 4)))] 1292 "TARGET_MULHW" 1293 "macchw. %0,%1,%2" 1294 [(set_attr "type" "imul3")]) 1295 1296(define_insn "*macchw" 1297 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1298 (plus:SI (mult:SI (ashiftrt:SI 1299 (match_operand:SI 2 "gpc_reg_operand" "r") 1300 (const_int 16)) 1301 (sign_extend:SI 1302 (match_operand:HI 1 "gpc_reg_operand" "r"))) 1303 (match_operand:SI 3 "gpc_reg_operand" "0")))] 1304 "TARGET_MULHW" 1305 "macchw %0,%1,%2" 1306 [(set_attr "type" "imul3")]) 1307 1308(define_insn "*macchwuc" 1309 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1310 (compare:CC (plus:SI (mult:SI (lshiftrt:SI 1311 (match_operand:SI 2 "gpc_reg_operand" "r") 1312 (const_int 16)) 1313 (zero_extend:SI 1314 (match_operand:HI 1 "gpc_reg_operand" "r"))) 1315 (match_operand:SI 4 "gpc_reg_operand" "0")) 1316 (const_int 0))) 1317 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1318 (plus:SI (mult:SI (lshiftrt:SI 1319 (match_dup 2) 1320 (const_int 16)) 1321 (zero_extend:SI 1322 (match_dup 1))) 1323 (match_dup 4)))] 1324 "TARGET_MULHW" 1325 "macchwu. %0,%1,%2" 1326 [(set_attr "type" "imul3")]) 1327 1328(define_insn "*macchwu" 1329 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1330 (plus:SI (mult:SI (lshiftrt:SI 1331 (match_operand:SI 2 "gpc_reg_operand" "r") 1332 (const_int 16)) 1333 (zero_extend:SI 1334 (match_operand:HI 1 "gpc_reg_operand" "r"))) 1335 (match_operand:SI 3 "gpc_reg_operand" "0")))] 1336 "TARGET_MULHW" 1337 "macchwu %0,%1,%2" 1338 [(set_attr "type" "imul3")]) 1339 1340(define_insn "*machhwc" 1341 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1342 (compare:CC (plus:SI (mult:SI (ashiftrt:SI 1343 (match_operand:SI 1 "gpc_reg_operand" "%r") 1344 (const_int 16)) 1345 (ashiftrt:SI 1346 (match_operand:SI 2 "gpc_reg_operand" "r") 1347 (const_int 16))) 1348 (match_operand:SI 4 "gpc_reg_operand" "0")) 1349 (const_int 0))) 1350 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1351 (plus:SI (mult:SI (ashiftrt:SI 1352 (match_dup 1) 1353 (const_int 16)) 1354 (ashiftrt:SI 1355 (match_dup 2) 1356 (const_int 16))) 1357 (match_dup 4)))] 1358 "TARGET_MULHW" 1359 "machhw. %0,%1,%2" 1360 [(set_attr "type" "imul3")]) 1361 1362(define_insn "*machhw" 1363 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1364 (plus:SI (mult:SI (ashiftrt:SI 1365 (match_operand:SI 1 "gpc_reg_operand" "%r") 1366 (const_int 16)) 1367 (ashiftrt:SI 1368 (match_operand:SI 2 "gpc_reg_operand" "r") 1369 (const_int 16))) 1370 (match_operand:SI 3 "gpc_reg_operand" "0")))] 1371 "TARGET_MULHW" 1372 "machhw %0,%1,%2" 1373 [(set_attr "type" "imul3")]) 1374 1375(define_insn "*machhwuc" 1376 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1377 (compare:CC (plus:SI (mult:SI (lshiftrt:SI 1378 (match_operand:SI 1 "gpc_reg_operand" "%r") 1379 (const_int 16)) 1380 (lshiftrt:SI 1381 (match_operand:SI 2 "gpc_reg_operand" "r") 1382 (const_int 16))) 1383 (match_operand:SI 4 "gpc_reg_operand" "0")) 1384 (const_int 0))) 1385 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1386 (plus:SI (mult:SI (lshiftrt:SI 1387 (match_dup 1) 1388 (const_int 16)) 1389 (lshiftrt:SI 1390 (match_dup 2) 1391 (const_int 16))) 1392 (match_dup 4)))] 1393 "TARGET_MULHW" 1394 "machhwu. %0,%1,%2" 1395 [(set_attr "type" "imul3")]) 1396 1397(define_insn "*machhwu" 1398 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1399 (plus:SI (mult:SI (lshiftrt:SI 1400 (match_operand:SI 1 "gpc_reg_operand" "%r") 1401 (const_int 16)) 1402 (lshiftrt:SI 1403 (match_operand:SI 2 "gpc_reg_operand" "r") 1404 (const_int 16))) 1405 (match_operand:SI 3 "gpc_reg_operand" "0")))] 1406 "TARGET_MULHW" 1407 "machhwu %0,%1,%2" 1408 [(set_attr "type" "imul3")]) 1409 1410(define_insn "*maclhwc" 1411 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1412 (compare:CC (plus:SI (mult:SI (sign_extend:SI 1413 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1414 (sign_extend:SI 1415 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1416 (match_operand:SI 4 "gpc_reg_operand" "0")) 1417 (const_int 0))) 1418 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1419 (plus:SI (mult:SI (sign_extend:SI 1420 (match_dup 1)) 1421 (sign_extend:SI 1422 (match_dup 2))) 1423 (match_dup 4)))] 1424 "TARGET_MULHW" 1425 "maclhw. %0,%1,%2" 1426 [(set_attr "type" "imul3")]) 1427 1428(define_insn "*maclhw" 1429 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1430 (plus:SI (mult:SI (sign_extend:SI 1431 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1432 (sign_extend:SI 1433 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1434 (match_operand:SI 3 "gpc_reg_operand" "0")))] 1435 "TARGET_MULHW" 1436 "maclhw %0,%1,%2" 1437 [(set_attr "type" "imul3")]) 1438 1439(define_insn "*maclhwuc" 1440 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1441 (compare:CC (plus:SI (mult:SI (zero_extend:SI 1442 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1443 (zero_extend:SI 1444 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1445 (match_operand:SI 4 "gpc_reg_operand" "0")) 1446 (const_int 0))) 1447 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1448 (plus:SI (mult:SI (zero_extend:SI 1449 (match_dup 1)) 1450 (zero_extend:SI 1451 (match_dup 2))) 1452 (match_dup 4)))] 1453 "TARGET_MULHW" 1454 "maclhwu. %0,%1,%2" 1455 [(set_attr "type" "imul3")]) 1456 1457(define_insn "*maclhwu" 1458 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1459 (plus:SI (mult:SI (zero_extend:SI 1460 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1461 (zero_extend:SI 1462 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1463 (match_operand:SI 3 "gpc_reg_operand" "0")))] 1464 "TARGET_MULHW" 1465 "maclhwu %0,%1,%2" 1466 [(set_attr "type" "imul3")]) 1467 1468(define_insn "*nmacchwc" 1469 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1470 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") 1471 (mult:SI (ashiftrt:SI 1472 (match_operand:SI 2 "gpc_reg_operand" "r") 1473 (const_int 16)) 1474 (sign_extend:SI 1475 (match_operand:HI 1 "gpc_reg_operand" "r")))) 1476 (const_int 0))) 1477 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1478 (minus:SI (match_dup 4) 1479 (mult:SI (ashiftrt:SI 1480 (match_dup 2) 1481 (const_int 16)) 1482 (sign_extend:SI 1483 (match_dup 1)))))] 1484 "TARGET_MULHW" 1485 "nmacchw. %0,%1,%2" 1486 [(set_attr "type" "imul3")]) 1487 1488(define_insn "*nmacchw" 1489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1490 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") 1491 (mult:SI (ashiftrt:SI 1492 (match_operand:SI 2 "gpc_reg_operand" "r") 1493 (const_int 16)) 1494 (sign_extend:SI 1495 (match_operand:HI 1 "gpc_reg_operand" "r")))))] 1496 "TARGET_MULHW" 1497 "nmacchw %0,%1,%2" 1498 [(set_attr "type" "imul3")]) 1499 1500(define_insn "*nmachhwc" 1501 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1502 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") 1503 (mult:SI (ashiftrt:SI 1504 (match_operand:SI 1 "gpc_reg_operand" "%r") 1505 (const_int 16)) 1506 (ashiftrt:SI 1507 (match_operand:SI 2 "gpc_reg_operand" "r") 1508 (const_int 16)))) 1509 (const_int 0))) 1510 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1511 (minus:SI (match_dup 4) 1512 (mult:SI (ashiftrt:SI 1513 (match_dup 1) 1514 (const_int 16)) 1515 (ashiftrt:SI 1516 (match_dup 2) 1517 (const_int 16)))))] 1518 "TARGET_MULHW" 1519 "nmachhw. %0,%1,%2" 1520 [(set_attr "type" "imul3")]) 1521 1522(define_insn "*nmachhw" 1523 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1524 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") 1525 (mult:SI (ashiftrt:SI 1526 (match_operand:SI 1 "gpc_reg_operand" "%r") 1527 (const_int 16)) 1528 (ashiftrt:SI 1529 (match_operand:SI 2 "gpc_reg_operand" "r") 1530 (const_int 16)))))] 1531 "TARGET_MULHW" 1532 "nmachhw %0,%1,%2" 1533 [(set_attr "type" "imul3")]) 1534 1535(define_insn "*nmaclhwc" 1536 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1537 (compare:CC (minus:SI (match_operand:SI 4 "gpc_reg_operand" "0") 1538 (mult:SI (sign_extend:SI 1539 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1540 (sign_extend:SI 1541 (match_operand:HI 2 "gpc_reg_operand" "r")))) 1542 (const_int 0))) 1543 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1544 (minus:SI (match_dup 4) 1545 (mult:SI (sign_extend:SI 1546 (match_dup 1)) 1547 (sign_extend:SI 1548 (match_dup 2)))))] 1549 "TARGET_MULHW" 1550 "nmaclhw. %0,%1,%2" 1551 [(set_attr "type" "imul3")]) 1552 1553(define_insn "*nmaclhw" 1554 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1555 (minus:SI (match_operand:SI 3 "gpc_reg_operand" "0") 1556 (mult:SI (sign_extend:SI 1557 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1558 (sign_extend:SI 1559 (match_operand:HI 2 "gpc_reg_operand" "r")))))] 1560 "TARGET_MULHW" 1561 "nmaclhw %0,%1,%2" 1562 [(set_attr "type" "imul3")]) 1563 1564(define_insn "*mulchwc" 1565 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1566 (compare:CC (mult:SI (ashiftrt:SI 1567 (match_operand:SI 2 "gpc_reg_operand" "r") 1568 (const_int 16)) 1569 (sign_extend:SI 1570 (match_operand:HI 1 "gpc_reg_operand" "r"))) 1571 (const_int 0))) 1572 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1573 (mult:SI (ashiftrt:SI 1574 (match_dup 2) 1575 (const_int 16)) 1576 (sign_extend:SI 1577 (match_dup 1))))] 1578 "TARGET_MULHW" 1579 "mulchw. %0,%1,%2" 1580 [(set_attr "type" "imul3")]) 1581 1582(define_insn "*mulchw" 1583 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1584 (mult:SI (ashiftrt:SI 1585 (match_operand:SI 2 "gpc_reg_operand" "r") 1586 (const_int 16)) 1587 (sign_extend:SI 1588 (match_operand:HI 1 "gpc_reg_operand" "r"))))] 1589 "TARGET_MULHW" 1590 "mulchw %0,%1,%2" 1591 [(set_attr "type" "imul3")]) 1592 1593(define_insn "*mulchwuc" 1594 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1595 (compare:CC (mult:SI (lshiftrt:SI 1596 (match_operand:SI 2 "gpc_reg_operand" "r") 1597 (const_int 16)) 1598 (zero_extend:SI 1599 (match_operand:HI 1 "gpc_reg_operand" "r"))) 1600 (const_int 0))) 1601 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1602 (mult:SI (lshiftrt:SI 1603 (match_dup 2) 1604 (const_int 16)) 1605 (zero_extend:SI 1606 (match_dup 1))))] 1607 "TARGET_MULHW" 1608 "mulchwu. %0,%1,%2" 1609 [(set_attr "type" "imul3")]) 1610 1611(define_insn "*mulchwu" 1612 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1613 (mult:SI (lshiftrt:SI 1614 (match_operand:SI 2 "gpc_reg_operand" "r") 1615 (const_int 16)) 1616 (zero_extend:SI 1617 (match_operand:HI 1 "gpc_reg_operand" "r"))))] 1618 "TARGET_MULHW" 1619 "mulchwu %0,%1,%2" 1620 [(set_attr "type" "imul3")]) 1621 1622(define_insn "*mulhhwc" 1623 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1624 (compare:CC (mult:SI (ashiftrt:SI 1625 (match_operand:SI 1 "gpc_reg_operand" "%r") 1626 (const_int 16)) 1627 (ashiftrt:SI 1628 (match_operand:SI 2 "gpc_reg_operand" "r") 1629 (const_int 16))) 1630 (const_int 0))) 1631 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1632 (mult:SI (ashiftrt:SI 1633 (match_dup 1) 1634 (const_int 16)) 1635 (ashiftrt:SI 1636 (match_dup 2) 1637 (const_int 16))))] 1638 "TARGET_MULHW" 1639 "mulhhw. %0,%1,%2" 1640 [(set_attr "type" "imul3")]) 1641 1642(define_insn "*mulhhw" 1643 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1644 (mult:SI (ashiftrt:SI 1645 (match_operand:SI 1 "gpc_reg_operand" "%r") 1646 (const_int 16)) 1647 (ashiftrt:SI 1648 (match_operand:SI 2 "gpc_reg_operand" "r") 1649 (const_int 16))))] 1650 "TARGET_MULHW" 1651 "mulhhw %0,%1,%2" 1652 [(set_attr "type" "imul3")]) 1653 1654(define_insn "*mulhhwuc" 1655 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1656 (compare:CC (mult:SI (lshiftrt:SI 1657 (match_operand:SI 1 "gpc_reg_operand" "%r") 1658 (const_int 16)) 1659 (lshiftrt:SI 1660 (match_operand:SI 2 "gpc_reg_operand" "r") 1661 (const_int 16))) 1662 (const_int 0))) 1663 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1664 (mult:SI (lshiftrt:SI 1665 (match_dup 1) 1666 (const_int 16)) 1667 (lshiftrt:SI 1668 (match_dup 2) 1669 (const_int 16))))] 1670 "TARGET_MULHW" 1671 "mulhhwu. %0,%1,%2" 1672 [(set_attr "type" "imul3")]) 1673 1674(define_insn "*mulhhwu" 1675 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1676 (mult:SI (lshiftrt:SI 1677 (match_operand:SI 1 "gpc_reg_operand" "%r") 1678 (const_int 16)) 1679 (lshiftrt:SI 1680 (match_operand:SI 2 "gpc_reg_operand" "r") 1681 (const_int 16))))] 1682 "TARGET_MULHW" 1683 "mulhhwu %0,%1,%2" 1684 [(set_attr "type" "imul3")]) 1685 1686(define_insn "*mullhwc" 1687 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1688 (compare:CC (mult:SI (sign_extend:SI 1689 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1690 (sign_extend:SI 1691 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1692 (const_int 0))) 1693 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1694 (mult:SI (sign_extend:SI 1695 (match_dup 1)) 1696 (sign_extend:SI 1697 (match_dup 2))))] 1698 "TARGET_MULHW" 1699 "mullhw. %0,%1,%2" 1700 [(set_attr "type" "imul3")]) 1701 1702(define_insn "*mullhw" 1703 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1704 (mult:SI (sign_extend:SI 1705 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1706 (sign_extend:SI 1707 (match_operand:HI 2 "gpc_reg_operand" "r"))))] 1708 "TARGET_MULHW" 1709 "mullhw %0,%1,%2" 1710 [(set_attr "type" "imul3")]) 1711 1712(define_insn "*mullhwuc" 1713 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1714 (compare:CC (mult:SI (zero_extend:SI 1715 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1716 (zero_extend:SI 1717 (match_operand:HI 2 "gpc_reg_operand" "r"))) 1718 (const_int 0))) 1719 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1720 (mult:SI (zero_extend:SI 1721 (match_dup 1)) 1722 (zero_extend:SI 1723 (match_dup 2))))] 1724 "TARGET_MULHW" 1725 "mullhwu. %0,%1,%2" 1726 [(set_attr "type" "imul3")]) 1727 1728(define_insn "*mullhwu" 1729 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 1730 (mult:SI (zero_extend:SI 1731 (match_operand:HI 1 "gpc_reg_operand" "%r")) 1732 (zero_extend:SI 1733 (match_operand:HI 2 "gpc_reg_operand" "r"))))] 1734 "TARGET_MULHW" 1735 "mullhwu %0,%1,%2" 1736 [(set_attr "type" "imul3")]) 1737 1738;; IBM 405, 440, 464 and 476 string-search dlmzb instruction support. 1739(define_insn "dlmzb" 1740 [(set (match_operand:CC 3 "cc_reg_operand" "=x") 1741 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 1742 (match_operand:SI 2 "gpc_reg_operand" "r")] 1743 UNSPEC_DLMZB_CR)) 1744 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 1745 (unspec:SI [(match_dup 1) 1746 (match_dup 2)] 1747 UNSPEC_DLMZB))] 1748 "TARGET_DLMZB" 1749 "dlmzb. %0,%1,%2") 1750 1751(define_expand "strlensi" 1752 [(set (match_operand:SI 0 "gpc_reg_operand" "") 1753 (unspec:SI [(match_operand:BLK 1 "general_operand" "") 1754 (match_operand:QI 2 "const_int_operand" "") 1755 (match_operand 3 "const_int_operand" "")] 1756 UNSPEC_DLMZB_STRLEN)) 1757 (clobber (match_scratch:CC 4 "=x"))] 1758 "TARGET_DLMZB && WORDS_BIG_ENDIAN && !optimize_size" 1759{ 1760 rtx result = operands[0]; 1761 rtx src = operands[1]; 1762 rtx search_char = operands[2]; 1763 rtx align = operands[3]; 1764 rtx addr, scratch_string, word1, word2, scratch_dlmzb; 1765 rtx loop_label, end_label, mem, cr0, cond; 1766 if (search_char != const0_rtx 1767 || GET_CODE (align) != CONST_INT 1768 || INTVAL (align) < 8) 1769 FAIL; 1770 word1 = gen_reg_rtx (SImode); 1771 word2 = gen_reg_rtx (SImode); 1772 scratch_dlmzb = gen_reg_rtx (SImode); 1773 scratch_string = gen_reg_rtx (Pmode); 1774 loop_label = gen_label_rtx (); 1775 end_label = gen_label_rtx (); 1776 addr = force_reg (Pmode, XEXP (src, 0)); 1777 emit_move_insn (scratch_string, addr); 1778 emit_label (loop_label); 1779 mem = change_address (src, SImode, scratch_string); 1780 emit_move_insn (word1, mem); 1781 emit_move_insn (word2, adjust_address (mem, SImode, 4)); 1782 cr0 = gen_rtx_REG (CCmode, CR0_REGNO); 1783 emit_insn (gen_dlmzb (scratch_dlmzb, word1, word2, cr0)); 1784 cond = gen_rtx_NE (VOIDmode, cr0, const0_rtx); 1785 emit_jump_insn (gen_rtx_SET (VOIDmode, 1786 pc_rtx, 1787 gen_rtx_IF_THEN_ELSE (VOIDmode, 1788 cond, 1789 gen_rtx_LABEL_REF 1790 (VOIDmode, 1791 end_label), 1792 pc_rtx))); 1793 emit_insn (gen_addsi3 (scratch_string, scratch_string, GEN_INT (8))); 1794 emit_jump_insn (gen_rtx_SET (VOIDmode, 1795 pc_rtx, 1796 gen_rtx_LABEL_REF (VOIDmode, loop_label))); 1797 emit_barrier (); 1798 emit_label (end_label); 1799 emit_insn (gen_addsi3 (scratch_string, scratch_string, scratch_dlmzb)); 1800 emit_insn (gen_subsi3 (result, scratch_string, addr)); 1801 emit_insn (gen_subsi3 (result, result, const1_rtx)); 1802 DONE; 1803}) 1804 1805;; Fixed-point arithmetic insns. 1806 1807(define_expand "add<mode>3" 1808 [(set (match_operand:SDI 0 "gpc_reg_operand" "") 1809 (plus:SDI (match_operand:SDI 1 "gpc_reg_operand" "") 1810 (match_operand:SDI 2 "reg_or_add_cint_operand" "")))] 1811 "" 1812{ 1813 if (<MODE>mode == DImode && ! TARGET_POWERPC64) 1814 { 1815 if (non_short_cint_operand (operands[2], DImode)) 1816 FAIL; 1817 } 1818 else if (GET_CODE (operands[2]) == CONST_INT 1819 && ! add_operand (operands[2], <MODE>mode)) 1820 { 1821 rtx tmp = ((!can_create_pseudo_p () 1822 || rtx_equal_p (operands[0], operands[1])) 1823 ? operands[0] : gen_reg_rtx (<MODE>mode)); 1824 1825 HOST_WIDE_INT val = INTVAL (operands[2]); 1826 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; 1827 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); 1828 1829 if (<MODE>mode == DImode && !satisfies_constraint_L (GEN_INT (rest))) 1830 FAIL; 1831 1832 /* The ordering here is important for the prolog expander. 1833 When space is allocated from the stack, adding 'low' first may 1834 produce a temporary deallocation (which would be bad). */ 1835 emit_insn (gen_add<mode>3 (tmp, operands[1], GEN_INT (rest))); 1836 emit_insn (gen_add<mode>3 (operands[0], tmp, GEN_INT (low))); 1837 DONE; 1838 } 1839}) 1840 1841;; Discourage ai/addic because of carry but provide it in an alternative 1842;; allowing register zero as source. 1843(define_insn "*add<mode>3_internal1" 1844 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r,?r,r") 1845 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "%r,b,r,b") 1846 (match_operand:GPR 2 "add_operand" "r,I,I,L")))] 1847 "!DECIMAL_FLOAT_MODE_P (GET_MODE (operands[0])) && !DECIMAL_FLOAT_MODE_P (GET_MODE (operands[1]))" 1848 "@ 1849 add %0,%1,%2 1850 addi %0,%1,%2 1851 addic %0,%1,%2 1852 addis %0,%1,%v2" 1853 [(set_attr "length" "4,4,4,4")]) 1854 1855(define_insn "addsi3_high" 1856 [(set (match_operand:SI 0 "gpc_reg_operand" "=b") 1857 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 1858 (high:SI (match_operand 2 "" ""))))] 1859 "TARGET_MACHO && !TARGET_64BIT" 1860 "addis %0,%1,ha16(%2)" 1861 [(set_attr "length" "4")]) 1862 1863(define_insn "*add<mode>3_internal2" 1864 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 1865 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") 1866 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) 1867 (const_int 0))) 1868 (clobber (match_scratch:P 3 "=r,r,r,r"))] 1869 "" 1870 "@ 1871 add. %3,%1,%2 1872 addic. %3,%1,%2 1873 # 1874 #" 1875 [(set_attr "type" "fast_compare,compare,compare,compare") 1876 (set_attr "length" "4,4,8,8")]) 1877 1878(define_split 1879 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 1880 (compare:CC (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 1881 (match_operand:GPR 2 "reg_or_short_operand" "")) 1882 (const_int 0))) 1883 (clobber (match_scratch:GPR 3 ""))] 1884 "reload_completed" 1885 [(set (match_dup 3) 1886 (plus:GPR (match_dup 1) 1887 (match_dup 2))) 1888 (set (match_dup 0) 1889 (compare:CC (match_dup 3) 1890 (const_int 0)))] 1891 "") 1892 1893(define_insn "*add<mode>3_internal3" 1894 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 1895 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "%r,r,r,r") 1896 (match_operand:P 2 "reg_or_short_operand" "r,I,r,I")) 1897 (const_int 0))) 1898 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") 1899 (plus:P (match_dup 1) 1900 (match_dup 2)))] 1901 "" 1902 "@ 1903 add. %0,%1,%2 1904 addic. %0,%1,%2 1905 # 1906 #" 1907 [(set_attr "type" "fast_compare,compare,compare,compare") 1908 (set_attr "length" "4,4,8,8")]) 1909 1910(define_split 1911 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 1912 (compare:CC (plus:P (match_operand:P 1 "gpc_reg_operand" "") 1913 (match_operand:P 2 "reg_or_short_operand" "")) 1914 (const_int 0))) 1915 (set (match_operand:P 0 "gpc_reg_operand" "") 1916 (plus:P (match_dup 1) (match_dup 2)))] 1917 "reload_completed" 1918 [(set (match_dup 0) 1919 (plus:P (match_dup 1) 1920 (match_dup 2))) 1921 (set (match_dup 3) 1922 (compare:CC (match_dup 0) 1923 (const_int 0)))] 1924 "") 1925 1926;; Split an add that we can't do in one insn into two insns, each of which 1927;; does one 16-bit part. This is used by combine. Note that the low-order 1928;; add should be last in case the result gets used in an address. 1929 1930(define_split 1931 [(set (match_operand:GPR 0 "gpc_reg_operand" "") 1932 (plus:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 1933 (match_operand:GPR 2 "non_add_cint_operand" "")))] 1934 "" 1935 [(set (match_dup 0) (plus:GPR (match_dup 1) (match_dup 3))) 1936 (set (match_dup 0) (plus:GPR (match_dup 0) (match_dup 4)))] 1937{ 1938 HOST_WIDE_INT val = INTVAL (operands[2]); 1939 HOST_WIDE_INT low = ((val & 0xffff) ^ 0x8000) - 0x8000; 1940 HOST_WIDE_INT rest = trunc_int_for_mode (val - low, <MODE>mode); 1941 1942 operands[4] = GEN_INT (low); 1943 if (<MODE>mode == SImode || satisfies_constraint_L (GEN_INT (rest))) 1944 operands[3] = GEN_INT (rest); 1945 else if (can_create_pseudo_p ()) 1946 { 1947 operands[3] = gen_reg_rtx (DImode); 1948 emit_move_insn (operands[3], operands[2]); 1949 emit_insn (gen_adddi3 (operands[0], operands[1], operands[3])); 1950 DONE; 1951 } 1952 else 1953 FAIL; 1954}) 1955 1956(define_expand "one_cmpl<mode>2" 1957 [(set (match_operand:SDI 0 "gpc_reg_operand" "") 1958 (not:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] 1959 "" 1960{ 1961 if (<MODE>mode == DImode && !TARGET_POWERPC64) 1962 { 1963 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX); 1964 DONE; 1965 } 1966}) 1967 1968(define_insn "*one_cmpl<mode>2" 1969 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 1970 (not:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] 1971 "" 1972 "nor %0,%1,%1") 1973 1974(define_insn "" 1975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 1976 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) 1977 (const_int 0))) 1978 (clobber (match_scratch:P 2 "=r,r"))] 1979 "" 1980 "@ 1981 nor. %2,%1,%1 1982 #" 1983 [(set_attr "type" "fast_compare,compare") 1984 (set_attr "length" "4,8")]) 1985 1986(define_split 1987 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 1988 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) 1989 (const_int 0))) 1990 (clobber (match_scratch:P 2 ""))] 1991 "reload_completed" 1992 [(set (match_dup 2) 1993 (not:P (match_dup 1))) 1994 (set (match_dup 0) 1995 (compare:CC (match_dup 2) 1996 (const_int 0)))] 1997 "") 1998 1999(define_insn "" 2000 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 2001 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "r,r")) 2002 (const_int 0))) 2003 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 2004 (not:P (match_dup 1)))] 2005 "" 2006 "@ 2007 nor. %0,%1,%1 2008 #" 2009 [(set_attr "type" "fast_compare,compare") 2010 (set_attr "length" "4,8")]) 2011 2012(define_split 2013 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 2014 (compare:CC (not:P (match_operand:P 1 "gpc_reg_operand" "")) 2015 (const_int 0))) 2016 (set (match_operand:P 0 "gpc_reg_operand" "") 2017 (not:P (match_dup 1)))] 2018 "reload_completed" 2019 [(set (match_dup 0) 2020 (not:P (match_dup 1))) 2021 (set (match_dup 2) 2022 (compare:CC (match_dup 0) 2023 (const_int 0)))] 2024 "") 2025 2026(define_insn "" 2027 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") 2028 (minus:GPR (match_operand:GPR 1 "reg_or_short_operand" "r,I") 2029 (match_operand:GPR 2 "gpc_reg_operand" "r,r")))] 2030 "" 2031 "@ 2032 subf %0,%2,%1 2033 subfic %0,%2,%1") 2034 2035(define_insn "" 2036 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2037 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") 2038 (match_operand:P 2 "gpc_reg_operand" "r,r")) 2039 (const_int 0))) 2040 (clobber (match_scratch:P 3 "=r,r"))] 2041 "" 2042 "@ 2043 subf. %3,%2,%1 2044 #" 2045 [(set_attr "type" "fast_compare") 2046 (set_attr "length" "4,8")]) 2047 2048(define_split 2049 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2050 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") 2051 (match_operand:P 2 "gpc_reg_operand" "")) 2052 (const_int 0))) 2053 (clobber (match_scratch:P 3 ""))] 2054 "reload_completed" 2055 [(set (match_dup 3) 2056 (minus:P (match_dup 1) 2057 (match_dup 2))) 2058 (set (match_dup 0) 2059 (compare:CC (match_dup 3) 2060 (const_int 0)))] 2061 "") 2062 2063(define_insn "" 2064 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2065 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "r,r") 2066 (match_operand:P 2 "gpc_reg_operand" "r,r")) 2067 (const_int 0))) 2068 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 2069 (minus:P (match_dup 1) 2070 (match_dup 2)))] 2071 "" 2072 "@ 2073 subf. %0,%2,%1 2074 #" 2075 [(set_attr "type" "fast_compare") 2076 (set_attr "length" "4,8")]) 2077 2078(define_split 2079 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2080 (compare:CC (minus:P (match_operand:P 1 "gpc_reg_operand" "") 2081 (match_operand:P 2 "gpc_reg_operand" "")) 2082 (const_int 0))) 2083 (set (match_operand:P 0 "gpc_reg_operand" "") 2084 (minus:P (match_dup 1) 2085 (match_dup 2)))] 2086 "reload_completed" 2087 [(set (match_dup 0) 2088 (minus:P (match_dup 1) 2089 (match_dup 2))) 2090 (set (match_dup 3) 2091 (compare:CC (match_dup 0) 2092 (const_int 0)))] 2093 "") 2094 2095(define_expand "sub<mode>3" 2096 [(set (match_operand:SDI 0 "gpc_reg_operand" "") 2097 (minus:SDI (match_operand:SDI 1 "reg_or_short_operand" "") 2098 (match_operand:SDI 2 "reg_or_sub_cint_operand" "")))] 2099 "" 2100 " 2101{ 2102 if (GET_CODE (operands[2]) == CONST_INT) 2103 { 2104 emit_insn (gen_add<mode>3 (operands[0], operands[1], 2105 negate_rtx (<MODE>mode, operands[2]))); 2106 DONE; 2107 } 2108}") 2109 2110(define_expand "neg<mode>2" 2111 [(set (match_operand:SDI 0 "gpc_reg_operand" "") 2112 (neg:SDI (match_operand:SDI 1 "gpc_reg_operand" "")))] 2113 "" 2114 "") 2115 2116(define_insn "*neg<mode>2_internal" 2117 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2118 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] 2119 "" 2120 "neg %0,%1") 2121 2122(define_insn "" 2123 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2124 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) 2125 (const_int 0))) 2126 (clobber (match_scratch:P 2 "=r,r"))] 2127 "" 2128 "@ 2129 neg. %2,%1 2130 #" 2131 [(set_attr "type" "fast_compare") 2132 (set_attr "length" "4,8")]) 2133 2134(define_split 2135 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2136 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) 2137 (const_int 0))) 2138 (clobber (match_scratch:P 2 ""))] 2139 "reload_completed" 2140 [(set (match_dup 2) 2141 (neg:P (match_dup 1))) 2142 (set (match_dup 0) 2143 (compare:CC (match_dup 2) 2144 (const_int 0)))] 2145 "") 2146 2147(define_insn "" 2148 [(set (match_operand:CC 2 "cc_reg_operand" "=x,?y") 2149 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "r,r")) 2150 (const_int 0))) 2151 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 2152 (neg:P (match_dup 1)))] 2153 "" 2154 "@ 2155 neg. %0,%1 2156 #" 2157 [(set_attr "type" "fast_compare") 2158 (set_attr "length" "4,8")]) 2159 2160(define_split 2161 [(set (match_operand:CC 2 "cc_reg_not_cr0_operand" "") 2162 (compare:CC (neg:P (match_operand:P 1 "gpc_reg_operand" "")) 2163 (const_int 0))) 2164 (set (match_operand:P 0 "gpc_reg_operand" "") 2165 (neg:P (match_dup 1)))] 2166 "reload_completed" 2167 [(set (match_dup 0) 2168 (neg:P (match_dup 1))) 2169 (set (match_dup 2) 2170 (compare:CC (match_dup 0) 2171 (const_int 0)))] 2172 "") 2173 2174(define_insn "clz<mode>2" 2175 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2176 (clz:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] 2177 "" 2178 "cntlz<wd> %0,%1" 2179 [(set_attr "type" "cntlz")]) 2180 2181(define_expand "ctz<mode>2" 2182 [(set (match_dup 2) 2183 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" ""))) 2184 (parallel [(set (match_dup 3) (and:GPR (match_dup 1) 2185 (match_dup 2))) 2186 (clobber (scratch:CC))]) 2187 (set (match_dup 4) (clz:GPR (match_dup 3))) 2188 (set (match_operand:GPR 0 "gpc_reg_operand" "") 2189 (minus:GPR (match_dup 5) (match_dup 4)))] 2190 "" 2191 { 2192 operands[2] = gen_reg_rtx (<MODE>mode); 2193 operands[3] = gen_reg_rtx (<MODE>mode); 2194 operands[4] = gen_reg_rtx (<MODE>mode); 2195 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode) - 1); 2196 }) 2197 2198(define_expand "ffs<mode>2" 2199 [(set (match_dup 2) 2200 (neg:GPR (match_operand:GPR 1 "gpc_reg_operand" ""))) 2201 (parallel [(set (match_dup 3) (and:GPR (match_dup 1) 2202 (match_dup 2))) 2203 (clobber (scratch:CC))]) 2204 (set (match_dup 4) (clz:GPR (match_dup 3))) 2205 (set (match_operand:GPR 0 "gpc_reg_operand" "") 2206 (minus:GPR (match_dup 5) (match_dup 4)))] 2207 "" 2208 { 2209 operands[2] = gen_reg_rtx (<MODE>mode); 2210 operands[3] = gen_reg_rtx (<MODE>mode); 2211 operands[4] = gen_reg_rtx (<MODE>mode); 2212 operands[5] = GEN_INT (GET_MODE_BITSIZE (<MODE>mode)); 2213 }) 2214 2215(define_insn "popcntb<mode>2" 2216 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2217 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] 2218 UNSPEC_POPCNTB))] 2219 "TARGET_POPCNTB" 2220 "popcntb %0,%1" 2221 [(set_attr "length" "4") 2222 (set_attr "type" "popcnt")]) 2223 2224(define_insn "popcntd<mode>2" 2225 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2226 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))] 2227 "TARGET_POPCNTD" 2228 "popcnt<wd> %0,%1" 2229 [(set_attr "length" "4") 2230 (set_attr "type" "popcnt")]) 2231 2232(define_expand "popcount<mode>2" 2233 [(set (match_operand:GPR 0 "gpc_reg_operand" "") 2234 (popcount:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))] 2235 "TARGET_POPCNTB || TARGET_POPCNTD" 2236 { 2237 rs6000_emit_popcount (operands[0], operands[1]); 2238 DONE; 2239 }) 2240 2241(define_insn "parity<mode>2_cmpb" 2242 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2243 (unspec:GPR [(match_operand:GPR 1 "gpc_reg_operand" "r")] UNSPEC_PARITY))] 2244 "TARGET_CMPB && TARGET_POPCNTB" 2245 "prty<wd> %0,%1" 2246 [(set_attr "length" "4") 2247 (set_attr "type" "popcnt")]) 2248 2249(define_expand "parity<mode>2" 2250 [(set (match_operand:GPR 0 "gpc_reg_operand" "") 2251 (parity:GPR (match_operand:GPR 1 "gpc_reg_operand" "")))] 2252 "TARGET_POPCNTB" 2253 { 2254 rs6000_emit_parity (operands[0], operands[1]); 2255 DONE; 2256 }) 2257 2258;; Since the hardware zeros the upper part of the register, save generating the 2259;; AND immediate if we are converting to unsigned 2260(define_insn "*bswaphi2_extenddi" 2261 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 2262 (zero_extend:DI 2263 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))] 2264 "TARGET_POWERPC64" 2265 "lhbrx %0,%y1" 2266 [(set_attr "length" "4") 2267 (set_attr "type" "load")]) 2268 2269(define_insn "*bswaphi2_extendsi" 2270 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 2271 (zero_extend:SI 2272 (bswap:HI (match_operand:HI 1 "memory_operand" "Z"))))] 2273 "" 2274 "lhbrx %0,%y1" 2275 [(set_attr "length" "4") 2276 (set_attr "type" "load")]) 2277 2278(define_expand "bswaphi2" 2279 [(parallel [(set (match_operand:HI 0 "reg_or_mem_operand" "") 2280 (bswap:HI 2281 (match_operand:HI 1 "reg_or_mem_operand" ""))) 2282 (clobber (match_scratch:SI 2 ""))])] 2283 "" 2284{ 2285 if (!REG_P (operands[0]) && !REG_P (operands[1])) 2286 operands[1] = force_reg (HImode, operands[1]); 2287}) 2288 2289(define_insn "bswaphi2_internal" 2290 [(set (match_operand:HI 0 "reg_or_mem_operand" "=r,Z,&r") 2291 (bswap:HI 2292 (match_operand:HI 1 "reg_or_mem_operand" "Z,r,r"))) 2293 (clobber (match_scratch:SI 2 "=X,X,&r"))] 2294 "" 2295 "@ 2296 lhbrx %0,%y1 2297 sthbrx %1,%y0 2298 #" 2299 [(set_attr "length" "4,4,12") 2300 (set_attr "type" "load,store,*")]) 2301 2302;; We are always BITS_BIG_ENDIAN, so the (const_int 16) below is 2303;; correct for -mlittle as well as -mbig. 2304(define_split 2305 [(set (match_operand:HI 0 "gpc_reg_operand" "") 2306 (bswap:HI (match_operand:HI 1 "gpc_reg_operand" ""))) 2307 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] 2308 "reload_completed" 2309 [(set (match_dup 3) 2310 (zero_extract:SI (match_dup 4) 2311 (const_int 8) 2312 (const_int 16))) 2313 (set (match_dup 2) 2314 (and:SI (ashift:SI (match_dup 4) 2315 (const_int 8)) 2316 (const_int 65280))) ;; 0xff00 2317 (set (match_dup 3) 2318 (ior:SI (match_dup 3) 2319 (match_dup 2)))] 2320 " 2321{ 2322 operands[3] = simplify_gen_subreg (SImode, operands[0], HImode, 0); 2323 operands[4] = simplify_gen_subreg (SImode, operands[1], HImode, 0); 2324}") 2325 2326(define_insn "*bswapsi2_extenddi" 2327 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 2328 (zero_extend:DI 2329 (bswap:SI (match_operand:SI 1 "memory_operand" "Z"))))] 2330 "TARGET_POWERPC64" 2331 "lwbrx %0,%y1" 2332 [(set_attr "length" "4") 2333 (set_attr "type" "load")]) 2334 2335(define_expand "bswapsi2" 2336 [(set (match_operand:SI 0 "reg_or_mem_operand" "") 2337 (bswap:SI 2338 (match_operand:SI 1 "reg_or_mem_operand" "")))] 2339 "" 2340{ 2341 if (!REG_P (operands[0]) && !REG_P (operands[1])) 2342 operands[1] = force_reg (SImode, operands[1]); 2343}) 2344 2345(define_insn "*bswapsi2_internal" 2346 [(set (match_operand:SI 0 "reg_or_mem_operand" "=r,Z,&r") 2347 (bswap:SI 2348 (match_operand:SI 1 "reg_or_mem_operand" "Z,r,r")))] 2349 "" 2350 "@ 2351 lwbrx %0,%y1 2352 stwbrx %1,%y0 2353 #" 2354 [(set_attr "length" "4,4,12") 2355 (set_attr "type" "load,store,*")]) 2356 2357;; We are always BITS_BIG_ENDIAN, so the bit positions below in 2358;; zero_extract insns do not change for -mlittle. 2359(define_split 2360 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2361 (bswap:SI (match_operand:SI 1 "gpc_reg_operand" "")))] 2362 "reload_completed" 2363 [(set (match_dup 0) 2364 (rotate:SI (match_dup 1) (const_int 8))) 2365 (set (zero_extract:SI (match_dup 0) 2366 (const_int 8) 2367 (const_int 0)) 2368 (match_dup 1)) 2369 (set (zero_extract:SI (match_dup 0) 2370 (const_int 8) 2371 (const_int 16)) 2372 (rotate:SI (match_dup 1) 2373 (const_int 16)))] 2374 "") 2375 2376(define_expand "bswapdi2" 2377 [(parallel [(set (match_operand:DI 0 "reg_or_mem_operand" "") 2378 (bswap:DI 2379 (match_operand:DI 1 "reg_or_mem_operand" ""))) 2380 (clobber (match_scratch:DI 2 "")) 2381 (clobber (match_scratch:DI 3 "")) 2382 (clobber (match_scratch:DI 4 ""))])] 2383 "" 2384{ 2385 if (!REG_P (operands[0]) && !REG_P (operands[1])) 2386 operands[1] = force_reg (DImode, operands[1]); 2387 2388 if (!TARGET_POWERPC64) 2389 { 2390 /* 32-bit mode needs fewer scratch registers, but 32-bit addressing mode 2391 that uses 64-bit registers needs the same scratch registers as 64-bit 2392 mode. */ 2393 emit_insn (gen_bswapdi2_32bit (operands[0], operands[1])); 2394 DONE; 2395 } 2396}) 2397 2398;; Power7/cell has ldbrx/stdbrx, so use it directly 2399(define_insn "*bswapdi2_ldbrx" 2400 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r") 2401 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r"))) 2402 (clobber (match_scratch:DI 2 "=X,X,&r")) 2403 (clobber (match_scratch:DI 3 "=X,X,&r")) 2404 (clobber (match_scratch:DI 4 "=X,X,&r"))] 2405 "TARGET_POWERPC64 && TARGET_LDBRX 2406 && (REG_P (operands[0]) || REG_P (operands[1]))" 2407 "@ 2408 ldbrx %0,%y1 2409 stdbrx %1,%y0 2410 #" 2411 [(set_attr "length" "4,4,36") 2412 (set_attr "type" "load,store,*")]) 2413 2414;; Non-power7/cell, fall back to use lwbrx/stwbrx 2415(define_insn "*bswapdi2_64bit" 2416 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r") 2417 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r"))) 2418 (clobber (match_scratch:DI 2 "=&b,&b,&r")) 2419 (clobber (match_scratch:DI 3 "=&r,&r,&r")) 2420 (clobber (match_scratch:DI 4 "=&r,X,&r"))] 2421 "TARGET_POWERPC64 && !TARGET_LDBRX 2422 && (REG_P (operands[0]) || REG_P (operands[1])) 2423 && !(MEM_P (operands[0]) && MEM_VOLATILE_P (operands[0])) 2424 && !(MEM_P (operands[1]) && MEM_VOLATILE_P (operands[1]))" 2425 "#" 2426 [(set_attr "length" "16,12,36")]) 2427 2428(define_split 2429 [(set (match_operand:DI 0 "gpc_reg_operand" "") 2430 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" ""))) 2431 (clobber (match_operand:DI 2 "gpc_reg_operand" "")) 2432 (clobber (match_operand:DI 3 "gpc_reg_operand" "")) 2433 (clobber (match_operand:DI 4 "gpc_reg_operand" ""))] 2434 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed" 2435 [(const_int 0)] 2436 " 2437{ 2438 rtx dest = operands[0]; 2439 rtx src = operands[1]; 2440 rtx op2 = operands[2]; 2441 rtx op3 = operands[3]; 2442 rtx op4 = operands[4]; 2443 rtx op3_32 = simplify_gen_subreg (SImode, op3, DImode, 2444 BYTES_BIG_ENDIAN ? 4 : 0); 2445 rtx op4_32 = simplify_gen_subreg (SImode, op4, DImode, 2446 BYTES_BIG_ENDIAN ? 4 : 0); 2447 rtx addr1; 2448 rtx addr2; 2449 rtx word_high; 2450 rtx word_low; 2451 2452 addr1 = XEXP (src, 0); 2453 if (GET_CODE (addr1) == PLUS) 2454 { 2455 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4))); 2456 if (TARGET_AVOID_XFORM) 2457 { 2458 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2)); 2459 addr2 = op2; 2460 } 2461 else 2462 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1)); 2463 } 2464 else if (TARGET_AVOID_XFORM) 2465 { 2466 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4))); 2467 addr2 = op2; 2468 } 2469 else 2470 { 2471 emit_move_insn (op2, GEN_INT (4)); 2472 addr2 = gen_rtx_PLUS (Pmode, op2, addr1); 2473 } 2474 2475 if (BYTES_BIG_ENDIAN) 2476 { 2477 word_high = change_address (src, SImode, addr1); 2478 word_low = change_address (src, SImode, addr2); 2479 } 2480 else 2481 { 2482 word_high = change_address (src, SImode, addr2); 2483 word_low = change_address (src, SImode, addr1); 2484 } 2485 2486 emit_insn (gen_bswapsi2 (op3_32, word_low)); 2487 emit_insn (gen_bswapsi2 (op4_32, word_high)); 2488 emit_insn (gen_ashldi3 (dest, op3, GEN_INT (32))); 2489 emit_insn (gen_iordi3 (dest, dest, op4)); 2490}") 2491 2492(define_split 2493 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "") 2494 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 2495 (clobber (match_operand:DI 2 "gpc_reg_operand" "")) 2496 (clobber (match_operand:DI 3 "gpc_reg_operand" "")) 2497 (clobber (match_operand:DI 4 "" ""))] 2498 "TARGET_POWERPC64 && !TARGET_LDBRX && reload_completed" 2499 [(const_int 0)] 2500 " 2501{ 2502 rtx dest = operands[0]; 2503 rtx src = operands[1]; 2504 rtx op2 = operands[2]; 2505 rtx op3 = operands[3]; 2506 rtx src_si = simplify_gen_subreg (SImode, src, DImode, 2507 BYTES_BIG_ENDIAN ? 4 : 0); 2508 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, 2509 BYTES_BIG_ENDIAN ? 4 : 0); 2510 rtx addr1; 2511 rtx addr2; 2512 rtx word_high; 2513 rtx word_low; 2514 2515 addr1 = XEXP (dest, 0); 2516 if (GET_CODE (addr1) == PLUS) 2517 { 2518 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4))); 2519 if (TARGET_AVOID_XFORM) 2520 { 2521 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2)); 2522 addr2 = op2; 2523 } 2524 else 2525 addr2 = gen_rtx_PLUS (Pmode, op2, XEXP (addr1, 1)); 2526 } 2527 else if (TARGET_AVOID_XFORM) 2528 { 2529 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4))); 2530 addr2 = op2; 2531 } 2532 else 2533 { 2534 emit_move_insn (op2, GEN_INT (4)); 2535 addr2 = gen_rtx_PLUS (Pmode, op2, addr1); 2536 } 2537 2538 emit_insn (gen_lshrdi3 (op3, src, GEN_INT (32))); 2539 if (BYTES_BIG_ENDIAN) 2540 { 2541 word_high = change_address (dest, SImode, addr1); 2542 word_low = change_address (dest, SImode, addr2); 2543 } 2544 else 2545 { 2546 word_high = change_address (dest, SImode, addr2); 2547 word_low = change_address (dest, SImode, addr1); 2548 } 2549 emit_insn (gen_bswapsi2 (word_high, src_si)); 2550 emit_insn (gen_bswapsi2 (word_low, op3_si)); 2551}") 2552 2553(define_split 2554 [(set (match_operand:DI 0 "gpc_reg_operand" "") 2555 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 2556 (clobber (match_operand:DI 2 "gpc_reg_operand" "")) 2557 (clobber (match_operand:DI 3 "gpc_reg_operand" "")) 2558 (clobber (match_operand:DI 4 "" ""))] 2559 "TARGET_POWERPC64 && reload_completed" 2560 [(const_int 0)] 2561 " 2562{ 2563 rtx dest = operands[0]; 2564 rtx src = operands[1]; 2565 rtx op2 = operands[2]; 2566 rtx op3 = operands[3]; 2567 int lo_off = BYTES_BIG_ENDIAN ? 4 : 0; 2568 rtx dest_si = simplify_gen_subreg (SImode, dest, DImode, lo_off); 2569 rtx src_si = simplify_gen_subreg (SImode, src, DImode, lo_off); 2570 rtx op2_si = simplify_gen_subreg (SImode, op2, DImode, lo_off); 2571 rtx op3_si = simplify_gen_subreg (SImode, op3, DImode, lo_off); 2572 2573 emit_insn (gen_lshrdi3 (op2, src, GEN_INT (32))); 2574 emit_insn (gen_bswapsi2 (dest_si, src_si)); 2575 emit_insn (gen_bswapsi2 (op3_si, op2_si)); 2576 emit_insn (gen_ashldi3 (dest, dest, GEN_INT (32))); 2577 emit_insn (gen_iordi3 (dest, dest, op3)); 2578}") 2579 2580(define_insn "bswapdi2_32bit" 2581 [(set (match_operand:DI 0 "reg_or_mem_operand" "=&r,Z,??&r") 2582 (bswap:DI (match_operand:DI 1 "reg_or_mem_operand" "Z,r,r"))) 2583 (clobber (match_scratch:SI 2 "=&b,&b,X"))] 2584 "!TARGET_POWERPC64 && (REG_P (operands[0]) || REG_P (operands[1]))" 2585 "#" 2586 [(set_attr "length" "16,12,36")]) 2587 2588(define_split 2589 [(set (match_operand:DI 0 "gpc_reg_operand" "") 2590 (bswap:DI (match_operand:DI 1 "indexed_or_indirect_operand" ""))) 2591 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] 2592 "!TARGET_POWERPC64 && reload_completed" 2593 [(const_int 0)] 2594 " 2595{ 2596 rtx dest = operands[0]; 2597 rtx src = operands[1]; 2598 rtx op2 = operands[2]; 2599 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0); 2600 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4); 2601 rtx addr1; 2602 rtx addr2; 2603 rtx word1; 2604 rtx word2; 2605 2606 addr1 = XEXP (src, 0); 2607 if (GET_CODE (addr1) == PLUS) 2608 { 2609 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4))); 2610 if (TARGET_AVOID_XFORM) 2611 { 2612 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2)); 2613 addr2 = op2; 2614 } 2615 else 2616 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1)); 2617 } 2618 else if (TARGET_AVOID_XFORM) 2619 { 2620 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4))); 2621 addr2 = op2; 2622 } 2623 else 2624 { 2625 emit_move_insn (op2, GEN_INT (4)); 2626 addr2 = gen_rtx_PLUS (SImode, op2, addr1); 2627 } 2628 2629 word1 = change_address (src, SImode, addr1); 2630 word2 = change_address (src, SImode, addr2); 2631 2632 emit_insn (gen_bswapsi2 (dest2, word1)); 2633 emit_insn (gen_bswapsi2 (dest1, word2)); 2634}") 2635 2636(define_split 2637 [(set (match_operand:DI 0 "indexed_or_indirect_operand" "") 2638 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 2639 (clobber (match_operand:SI 2 "gpc_reg_operand" ""))] 2640 "!TARGET_POWERPC64 && reload_completed" 2641 [(const_int 0)] 2642 " 2643{ 2644 rtx dest = operands[0]; 2645 rtx src = operands[1]; 2646 rtx op2 = operands[2]; 2647 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0); 2648 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4); 2649 rtx addr1; 2650 rtx addr2; 2651 rtx word1; 2652 rtx word2; 2653 2654 addr1 = XEXP (dest, 0); 2655 if (GET_CODE (addr1) == PLUS) 2656 { 2657 emit_insn (gen_add3_insn (op2, XEXP (addr1, 0), GEN_INT (4))); 2658 if (TARGET_AVOID_XFORM) 2659 { 2660 emit_insn (gen_add3_insn (op2, XEXP (addr1, 1), op2)); 2661 addr2 = op2; 2662 } 2663 else 2664 addr2 = gen_rtx_PLUS (SImode, op2, XEXP (addr1, 1)); 2665 } 2666 else if (TARGET_AVOID_XFORM) 2667 { 2668 emit_insn (gen_add3_insn (op2, addr1, GEN_INT (4))); 2669 addr2 = op2; 2670 } 2671 else 2672 { 2673 emit_move_insn (op2, GEN_INT (4)); 2674 addr2 = gen_rtx_PLUS (SImode, op2, addr1); 2675 } 2676 2677 word1 = change_address (dest, SImode, addr1); 2678 word2 = change_address (dest, SImode, addr2); 2679 2680 emit_insn (gen_bswapsi2 (word2, src1)); 2681 emit_insn (gen_bswapsi2 (word1, src2)); 2682}") 2683 2684(define_split 2685 [(set (match_operand:DI 0 "gpc_reg_operand" "") 2686 (bswap:DI (match_operand:DI 1 "gpc_reg_operand" ""))) 2687 (clobber (match_operand:SI 2 "" ""))] 2688 "!TARGET_POWERPC64 && reload_completed" 2689 [(const_int 0)] 2690 " 2691{ 2692 rtx dest = operands[0]; 2693 rtx src = operands[1]; 2694 rtx src1 = simplify_gen_subreg (SImode, src, DImode, 0); 2695 rtx src2 = simplify_gen_subreg (SImode, src, DImode, 4); 2696 rtx dest1 = simplify_gen_subreg (SImode, dest, DImode, 0); 2697 rtx dest2 = simplify_gen_subreg (SImode, dest, DImode, 4); 2698 2699 emit_insn (gen_bswapsi2 (dest1, src2)); 2700 emit_insn (gen_bswapsi2 (dest2, src1)); 2701}") 2702 2703(define_insn "mulsi3" 2704 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2705 (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2706 (match_operand:SI 2 "reg_or_short_operand" "r,I")))] 2707 "" 2708 "@ 2709 mullw %0,%1,%2 2710 mulli %0,%1,%2" 2711 [(set (attr "type") 2712 (cond [(match_operand:SI 2 "s8bit_cint_operand" "") 2713 (const_string "imul3") 2714 (match_operand:SI 2 "short_cint_operand" "") 2715 (const_string "imul2")] 2716 (const_string "imul")))]) 2717 2718(define_insn "*mulsi3_internal1" 2719 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2720 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2721 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2722 (const_int 0))) 2723 (clobber (match_scratch:SI 3 "=r,r"))] 2724 "TARGET_32BIT" 2725 "@ 2726 mullw. %3,%1,%2 2727 #" 2728 [(set_attr "type" "imul_compare") 2729 (set_attr "length" "4,8")]) 2730 2731(define_split 2732 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 2733 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2734 (match_operand:SI 2 "gpc_reg_operand" "")) 2735 (const_int 0))) 2736 (clobber (match_scratch:SI 3 ""))] 2737 "TARGET_32BIT && reload_completed" 2738 [(set (match_dup 3) 2739 (mult:SI (match_dup 1) (match_dup 2))) 2740 (set (match_dup 0) 2741 (compare:CC (match_dup 3) 2742 (const_int 0)))] 2743 "") 2744 2745(define_insn "*mulsi3_internal2" 2746 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2747 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2748 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 2749 (const_int 0))) 2750 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2751 (mult:SI (match_dup 1) (match_dup 2)))] 2752 "TARGET_32BIT" 2753 "@ 2754 mullw. %0,%1,%2 2755 #" 2756 [(set_attr "type" "imul_compare") 2757 (set_attr "length" "4,8")]) 2758 2759(define_split 2760 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 2761 (compare:CC (mult:SI (match_operand:SI 1 "gpc_reg_operand" "") 2762 (match_operand:SI 2 "gpc_reg_operand" "")) 2763 (const_int 0))) 2764 (set (match_operand:SI 0 "gpc_reg_operand" "") 2765 (mult:SI (match_dup 1) (match_dup 2)))] 2766 "TARGET_32BIT && reload_completed" 2767 [(set (match_dup 0) 2768 (mult:SI (match_dup 1) (match_dup 2))) 2769 (set (match_dup 3) 2770 (compare:CC (match_dup 0) 2771 (const_int 0)))] 2772 "") 2773 2774 2775(define_insn "udiv<mode>3" 2776 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2777 (udiv:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") 2778 (match_operand:GPR 2 "gpc_reg_operand" "r")))] 2779 "" 2780 "div<wd>u %0,%1,%2" 2781 [(set_attr "type" "<idiv_ldiv>")]) 2782 2783 2784;; For powers of two we can do srai/aze for divide and then adjust for 2785;; modulus. If it isn't a power of two, force operands into register and do 2786;; a normal divide. 2787(define_expand "div<mode>3" 2788 [(set (match_operand:GPR 0 "gpc_reg_operand" "") 2789 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 2790 (match_operand:GPR 2 "reg_or_cint_operand" "")))] 2791 "" 2792{ 2793 if (GET_CODE (operands[2]) != CONST_INT 2794 || INTVAL (operands[2]) <= 0 2795 || exact_log2 (INTVAL (operands[2])) < 0) 2796 operands[2] = force_reg (<MODE>mode, operands[2]); 2797}) 2798 2799(define_insn "*div<mode>3" 2800 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2801 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") 2802 (match_operand:GPR 2 "gpc_reg_operand" "r")))] 2803 "" 2804 "div<wd> %0,%1,%2" 2805 [(set_attr "type" "<idiv_ldiv>")]) 2806 2807(define_expand "mod<mode>3" 2808 [(use (match_operand:GPR 0 "gpc_reg_operand" "")) 2809 (use (match_operand:GPR 1 "gpc_reg_operand" "")) 2810 (use (match_operand:GPR 2 "reg_or_cint_operand" ""))] 2811 "" 2812 " 2813{ 2814 int i; 2815 rtx temp1; 2816 rtx temp2; 2817 2818 if (GET_CODE (operands[2]) != CONST_INT 2819 || INTVAL (operands[2]) <= 0 2820 || (i = exact_log2 (INTVAL (operands[2]))) < 0) 2821 FAIL; 2822 2823 temp1 = gen_reg_rtx (<MODE>mode); 2824 temp2 = gen_reg_rtx (<MODE>mode); 2825 2826 emit_insn (gen_div<mode>3 (temp1, operands[1], operands[2])); 2827 emit_insn (gen_ashl<mode>3 (temp2, temp1, GEN_INT (i))); 2828 emit_insn (gen_sub<mode>3 (operands[0], operands[1], temp2)); 2829 DONE; 2830}") 2831 2832(define_insn "" 2833 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 2834 (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") 2835 (match_operand:GPR 2 "exact_log2_cint_operand" "N")))] 2836 "" 2837 "sra<wd>i %0,%1,%p2\;addze %0,%0" 2838 [(set_attr "type" "two") 2839 (set_attr "length" "8")]) 2840 2841(define_insn "" 2842 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 2843 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") 2844 (match_operand:P 2 "exact_log2_cint_operand" "N,N")) 2845 (const_int 0))) 2846 (clobber (match_scratch:P 3 "=r,r"))] 2847 "" 2848 "@ 2849 sra<wd>i %3,%1,%p2\;addze. %3,%3 2850 #" 2851 [(set_attr "type" "compare") 2852 (set_attr "length" "8,12") 2853 (set_attr "cell_micro" "not")]) 2854 2855(define_split 2856 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 2857 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 2858 (match_operand:GPR 2 "exact_log2_cint_operand" 2859 "")) 2860 (const_int 0))) 2861 (clobber (match_scratch:GPR 3 ""))] 2862 "reload_completed" 2863 [(set (match_dup 3) 2864 (div:<MODE> (match_dup 1) (match_dup 2))) 2865 (set (match_dup 0) 2866 (compare:CC (match_dup 3) 2867 (const_int 0)))] 2868 "") 2869 2870(define_insn "" 2871 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 2872 (compare:CC (div:P (match_operand:P 1 "gpc_reg_operand" "r,r") 2873 (match_operand:P 2 "exact_log2_cint_operand" "N,N")) 2874 (const_int 0))) 2875 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 2876 (div:P (match_dup 1) (match_dup 2)))] 2877 "" 2878 "@ 2879 sra<wd>i %0,%1,%p2\;addze. %0,%0 2880 #" 2881 [(set_attr "type" "compare") 2882 (set_attr "length" "8,12") 2883 (set_attr "cell_micro" "not")]) 2884 2885(define_split 2886 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 2887 (compare:CC (div:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 2888 (match_operand:GPR 2 "exact_log2_cint_operand" 2889 "")) 2890 (const_int 0))) 2891 (set (match_operand:GPR 0 "gpc_reg_operand" "") 2892 (div:GPR (match_dup 1) (match_dup 2)))] 2893 "reload_completed" 2894 [(set (match_dup 0) 2895 (div:<MODE> (match_dup 1) (match_dup 2))) 2896 (set (match_dup 3) 2897 (compare:CC (match_dup 0) 2898 (const_int 0)))] 2899 "") 2900 2901;; Logical instructions 2902;; The logical instructions are mostly combined by using match_operator, 2903;; but the plain AND insns are somewhat different because there is no 2904;; plain 'andi' (only 'andi.'), no plain 'andis', and there are all 2905;; those rotate-and-mask operations. Thus, the AND insns come first. 2906 2907(define_expand "andsi3" 2908 [(parallel 2909 [(set (match_operand:SI 0 "gpc_reg_operand" "") 2910 (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 2911 (match_operand:SI 2 "and_operand" ""))) 2912 (clobber (match_scratch:CC 3 ""))])] 2913 "" 2914 "") 2915 2916(define_insn "andsi3_mc" 2917 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 2918 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r") 2919 (match_operand:SI 2 "and_operand" "?r,T,K,L"))) 2920 (clobber (match_scratch:CC 3 "=X,X,x,x"))] 2921 "rs6000_gen_cell_microcode" 2922 "@ 2923 and %0,%1,%2 2924 rlwinm %0,%1,0,%m2,%M2 2925 andi. %0,%1,%b2 2926 andis. %0,%1,%u2" 2927 [(set_attr "type" "*,*,fast_compare,fast_compare")]) 2928 2929(define_insn "andsi3_nomc" 2930 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2931 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2932 (match_operand:SI 2 "and_operand" "?r,T"))) 2933 (clobber (match_scratch:CC 3 "=X,X"))] 2934 "!rs6000_gen_cell_microcode" 2935 "@ 2936 and %0,%1,%2 2937 rlwinm %0,%1,0,%m2,%M2") 2938 2939(define_insn "andsi3_internal0_nomc" 2940 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 2941 (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r") 2942 (match_operand:SI 2 "and_operand" "?r,T")))] 2943 "!rs6000_gen_cell_microcode" 2944 "@ 2945 and %0,%1,%2 2946 rlwinm %0,%1,0,%m2,%M2") 2947 2948 2949;; Note to set cr's other than cr0 we do the and immediate and then 2950;; the test again -- this avoids a mfcr which on the higher end 2951;; machines causes an execution serialization 2952 2953(define_insn "*andsi3_internal2_mc" 2954 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2955 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2956 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2957 (const_int 0))) 2958 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) 2959 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2960 "TARGET_32BIT && rs6000_gen_cell_microcode" 2961 "@ 2962 and. %3,%1,%2 2963 andi. %3,%1,%b2 2964 andis. %3,%1,%u2 2965 rlwinm. %3,%1,0,%m2,%M2 2966 # 2967 # 2968 # 2969 #" 2970 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\ 2971 compare,compare,compare,compare") 2972 (set_attr "length" "4,4,4,4,8,8,8,8")]) 2973 2974(define_insn "*andsi3_internal3_mc" 2975 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 2976 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 2977 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 2978 (const_int 0))) 2979 (clobber (match_scratch:SI 3 "=r,r,r,r,r,r,r,r")) 2980 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 2981 "TARGET_64BIT && rs6000_gen_cell_microcode" 2982 "@ 2983 # 2984 andi. %3,%1,%b2 2985 andis. %3,%1,%u2 2986 rlwinm. %3,%1,0,%m2,%M2 2987 # 2988 # 2989 # 2990 #" 2991 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\ 2992 compare,compare,compare") 2993 (set_attr "length" "8,4,4,4,8,8,8,8")]) 2994 2995(define_split 2996 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 2997 (compare:CC (and:GPR (match_operand:GPR 1 "gpc_reg_operand" "") 2998 (match_operand:GPR 2 "and_operand" "")) 2999 (const_int 0))) 3000 (clobber (match_scratch:GPR 3 "")) 3001 (clobber (match_scratch:CC 4 ""))] 3002 "reload_completed" 3003 [(parallel [(set (match_dup 3) 3004 (and:<MODE> (match_dup 1) 3005 (match_dup 2))) 3006 (clobber (match_dup 4))]) 3007 (set (match_dup 0) 3008 (compare:CC (match_dup 3) 3009 (const_int 0)))] 3010 "") 3011 3012;; We don't have a 32 bit "and. rt,ra,rb" for ppc64. cr is set from the 3013;; whole 64 bit reg, and we don't know what is in the high 32 bits. 3014 3015(define_split 3016 [(set (match_operand:CC 0 "cc_reg_operand" "") 3017 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 3018 (match_operand:SI 2 "gpc_reg_operand" "")) 3019 (const_int 0))) 3020 (clobber (match_scratch:SI 3 "")) 3021 (clobber (match_scratch:CC 4 ""))] 3022 "TARGET_POWERPC64 && reload_completed" 3023 [(parallel [(set (match_dup 3) 3024 (and:SI (match_dup 1) 3025 (match_dup 2))) 3026 (clobber (match_dup 4))]) 3027 (set (match_dup 0) 3028 (compare:CC (match_dup 3) 3029 (const_int 0)))] 3030 "") 3031 3032(define_insn "*andsi3_internal4" 3033 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 3034 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 3035 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 3036 (const_int 0))) 3037 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") 3038 (and:SI (match_dup 1) 3039 (match_dup 2))) 3040 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 3041 "TARGET_32BIT && rs6000_gen_cell_microcode" 3042 "@ 3043 and. %0,%1,%2 3044 andi. %0,%1,%b2 3045 andis. %0,%1,%u2 3046 rlwinm. %0,%1,0,%m2,%M2 3047 # 3048 # 3049 # 3050 #" 3051 [(set_attr "type" "fast_compare,fast_compare,fast_compare,delayed_compare,\ 3052 compare,compare,compare,compare") 3053 (set_attr "length" "4,4,4,4,8,8,8,8")]) 3054 3055(define_insn "*andsi3_internal5_mc" 3056 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,?y,??y,??y,?y") 3057 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r") 3058 (match_operand:SI 2 "and_operand" "r,K,L,T,r,K,L,T")) 3059 (const_int 0))) 3060 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r") 3061 (and:SI (match_dup 1) 3062 (match_dup 2))) 3063 (clobber (match_scratch:CC 4 "=X,X,X,X,X,x,x,X"))] 3064 "TARGET_64BIT && rs6000_gen_cell_microcode" 3065 "@ 3066 # 3067 andi. %0,%1,%b2 3068 andis. %0,%1,%u2 3069 rlwinm. %0,%1,0,%m2,%M2 3070 # 3071 # 3072 # 3073 #" 3074 [(set_attr "type" "compare,fast_compare,fast_compare,delayed_compare,compare,\ 3075 compare,compare,compare") 3076 (set_attr "length" "8,4,4,4,8,8,8,8")]) 3077 3078(define_split 3079 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 3080 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 3081 (match_operand:SI 2 "and_operand" "")) 3082 (const_int 0))) 3083 (set (match_operand:SI 0 "gpc_reg_operand" "") 3084 (and:SI (match_dup 1) 3085 (match_dup 2))) 3086 (clobber (match_scratch:CC 4 ""))] 3087 "reload_completed" 3088 [(parallel [(set (match_dup 0) 3089 (and:SI (match_dup 1) 3090 (match_dup 2))) 3091 (clobber (match_dup 4))]) 3092 (set (match_dup 3) 3093 (compare:CC (match_dup 0) 3094 (const_int 0)))] 3095 "") 3096 3097(define_split 3098 [(set (match_operand:CC 3 "cc_reg_operand" "") 3099 (compare:CC (and:SI (match_operand:SI 1 "gpc_reg_operand" "") 3100 (match_operand:SI 2 "gpc_reg_operand" "")) 3101 (const_int 0))) 3102 (set (match_operand:SI 0 "gpc_reg_operand" "") 3103 (and:SI (match_dup 1) 3104 (match_dup 2))) 3105 (clobber (match_scratch:CC 4 ""))] 3106 "TARGET_POWERPC64 && reload_completed" 3107 [(parallel [(set (match_dup 0) 3108 (and:SI (match_dup 1) 3109 (match_dup 2))) 3110 (clobber (match_dup 4))]) 3111 (set (match_dup 3) 3112 (compare:CC (match_dup 0) 3113 (const_int 0)))] 3114 "") 3115 3116;; Handle the PowerPC64 rlwinm corner case 3117 3118(define_insn_and_split "*andsi3_internal6" 3119 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3120 (and:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3121 (match_operand:SI 2 "mask_operand_wrap" "i")))] 3122 "TARGET_POWERPC64" 3123 "#" 3124 "TARGET_POWERPC64" 3125 [(set (match_dup 0) 3126 (and:SI (rotate:SI (match_dup 1) (match_dup 3)) 3127 (match_dup 4))) 3128 (set (match_dup 0) 3129 (rotate:SI (match_dup 0) (match_dup 5)))] 3130 " 3131{ 3132 int mb = extract_MB (operands[2]); 3133 int me = extract_ME (operands[2]); 3134 operands[3] = GEN_INT (me + 1); 3135 operands[5] = GEN_INT (32 - (me + 1)); 3136 operands[4] = GEN_INT (~((HOST_WIDE_INT) -1 << (33 + me - mb))); 3137}" 3138 [(set_attr "length" "8")]) 3139 3140(define_expand "iorsi3" 3141 [(set (match_operand:SI 0 "gpc_reg_operand" "") 3142 (ior:SI (match_operand:SI 1 "gpc_reg_operand" "") 3143 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] 3144 "" 3145 " 3146{ 3147 if (GET_CODE (operands[2]) == CONST_INT 3148 && ! logical_operand (operands[2], SImode)) 3149 { 3150 HOST_WIDE_INT value = INTVAL (operands[2]); 3151 rtx tmp = ((!can_create_pseudo_p () 3152 || rtx_equal_p (operands[0], operands[1])) 3153 ? operands[0] : gen_reg_rtx (SImode)); 3154 3155 emit_insn (gen_iorsi3 (tmp, operands[1], 3156 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 3157 emit_insn (gen_iorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 3158 DONE; 3159 } 3160}") 3161 3162(define_expand "xorsi3" 3163 [(set (match_operand:SI 0 "gpc_reg_operand" "") 3164 (xor:SI (match_operand:SI 1 "gpc_reg_operand" "") 3165 (match_operand:SI 2 "reg_or_logical_cint_operand" "")))] 3166 "" 3167 " 3168{ 3169 if (GET_CODE (operands[2]) == CONST_INT 3170 && ! logical_operand (operands[2], SImode)) 3171 { 3172 HOST_WIDE_INT value = INTVAL (operands[2]); 3173 rtx tmp = ((!can_create_pseudo_p () 3174 || rtx_equal_p (operands[0], operands[1])) 3175 ? operands[0] : gen_reg_rtx (SImode)); 3176 3177 emit_insn (gen_xorsi3 (tmp, operands[1], 3178 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 3179 emit_insn (gen_xorsi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 3180 DONE; 3181 } 3182}") 3183 3184(define_insn "*boolsi3_internal1" 3185 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 3186 (match_operator:SI 3 "boolean_or_operator" 3187 [(match_operand:SI 1 "gpc_reg_operand" "%r,r,r") 3188 (match_operand:SI 2 "logical_operand" "r,K,L")]))] 3189 "" 3190 "@ 3191 %q3 %0,%1,%2 3192 %q3i %0,%1,%b2 3193 %q3is %0,%1,%u2") 3194 3195(define_insn "*boolsi3_internal2" 3196 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3197 (compare:CC (match_operator:SI 4 "boolean_or_operator" 3198 [(match_operand:SI 1 "gpc_reg_operand" "%r,r") 3199 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 3200 (const_int 0))) 3201 (clobber (match_scratch:SI 3 "=r,r"))] 3202 "TARGET_32BIT" 3203 "@ 3204 %q4. %3,%1,%2 3205 #" 3206 [(set_attr "type" "fast_compare,compare") 3207 (set_attr "length" "4,8")]) 3208 3209(define_split 3210 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 3211 (compare:CC (match_operator:SI 4 "boolean_operator" 3212 [(match_operand:SI 1 "gpc_reg_operand" "") 3213 (match_operand:SI 2 "gpc_reg_operand" "")]) 3214 (const_int 0))) 3215 (clobber (match_scratch:SI 3 ""))] 3216 "TARGET_32BIT && reload_completed" 3217 [(set (match_dup 3) (match_dup 4)) 3218 (set (match_dup 0) 3219 (compare:CC (match_dup 3) 3220 (const_int 0)))] 3221 "") 3222 3223(define_insn "*boolsi3_internal3" 3224 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3225 (compare:CC (match_operator:SI 4 "boolean_operator" 3226 [(match_operand:SI 1 "gpc_reg_operand" "%r,r") 3227 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 3228 (const_int 0))) 3229 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3230 (match_dup 4))] 3231 "TARGET_32BIT" 3232 "@ 3233 %q4. %0,%1,%2 3234 #" 3235 [(set_attr "type" "fast_compare,compare") 3236 (set_attr "length" "4,8")]) 3237 3238(define_split 3239 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 3240 (compare:CC (match_operator:SI 4 "boolean_operator" 3241 [(match_operand:SI 1 "gpc_reg_operand" "") 3242 (match_operand:SI 2 "gpc_reg_operand" "")]) 3243 (const_int 0))) 3244 (set (match_operand:SI 0 "gpc_reg_operand" "") 3245 (match_dup 4))] 3246 "TARGET_32BIT && reload_completed" 3247 [(set (match_dup 0) (match_dup 4)) 3248 (set (match_dup 3) 3249 (compare:CC (match_dup 0) 3250 (const_int 0)))] 3251 "") 3252 3253;; Split a logical operation that we can't do in one insn into two insns, 3254;; each of which does one 16-bit part. This is used by combine. 3255 3256(define_split 3257 [(set (match_operand:SI 0 "gpc_reg_operand" "") 3258 (match_operator:SI 3 "boolean_or_operator" 3259 [(match_operand:SI 1 "gpc_reg_operand" "") 3260 (match_operand:SI 2 "non_logical_cint_operand" "")]))] 3261 "" 3262 [(set (match_dup 0) (match_dup 4)) 3263 (set (match_dup 0) (match_dup 5))] 3264" 3265{ 3266 rtx i; 3267 i = GEN_INT (INTVAL (operands[2]) & (~ (HOST_WIDE_INT) 0xffff)); 3268 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 3269 operands[1], i); 3270 i = GEN_INT (INTVAL (operands[2]) & 0xffff); 3271 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 3272 operands[0], i); 3273}") 3274 3275(define_insn "*boolcsi3_internal1" 3276 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3277 (match_operator:SI 3 "boolean_operator" 3278 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 3279 (match_operand:SI 2 "gpc_reg_operand" "r")]))] 3280 "" 3281 "%q3 %0,%2,%1") 3282 3283(define_insn "*boolcsi3_internal2" 3284 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3285 (compare:CC (match_operator:SI 4 "boolean_operator" 3286 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 3287 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 3288 (const_int 0))) 3289 (clobber (match_scratch:SI 3 "=r,r"))] 3290 "TARGET_32BIT" 3291 "@ 3292 %q4. %3,%2,%1 3293 #" 3294 [(set_attr "type" "compare") 3295 (set_attr "length" "4,8")]) 3296 3297(define_split 3298 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 3299 (compare:CC (match_operator:SI 4 "boolean_operator" 3300 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3301 (match_operand:SI 2 "gpc_reg_operand" "")]) 3302 (const_int 0))) 3303 (clobber (match_scratch:SI 3 ""))] 3304 "TARGET_32BIT && reload_completed" 3305 [(set (match_dup 3) (match_dup 4)) 3306 (set (match_dup 0) 3307 (compare:CC (match_dup 3) 3308 (const_int 0)))] 3309 "") 3310 3311(define_insn "*boolcsi3_internal3" 3312 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3313 (compare:CC (match_operator:SI 4 "boolean_operator" 3314 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) 3315 (match_operand:SI 2 "gpc_reg_operand" "r,r")]) 3316 (const_int 0))) 3317 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3318 (match_dup 4))] 3319 "TARGET_32BIT" 3320 "@ 3321 %q4. %0,%2,%1 3322 #" 3323 [(set_attr "type" "compare") 3324 (set_attr "length" "4,8")]) 3325 3326(define_split 3327 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 3328 (compare:CC (match_operator:SI 4 "boolean_operator" 3329 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3330 (match_operand:SI 2 "gpc_reg_operand" "")]) 3331 (const_int 0))) 3332 (set (match_operand:SI 0 "gpc_reg_operand" "") 3333 (match_dup 4))] 3334 "TARGET_32BIT && reload_completed" 3335 [(set (match_dup 0) (match_dup 4)) 3336 (set (match_dup 3) 3337 (compare:CC (match_dup 0) 3338 (const_int 0)))] 3339 "") 3340 3341(define_insn "*boolccsi3_internal1" 3342 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3343 (match_operator:SI 3 "boolean_operator" 3344 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r")) 3345 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r"))]))] 3346 "" 3347 "%q3 %0,%1,%2") 3348 3349(define_insn "*boolccsi3_internal2" 3350 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3351 (compare:CC (match_operator:SI 4 "boolean_operator" 3352 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")) 3353 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) 3354 (const_int 0))) 3355 (clobber (match_scratch:SI 3 "=r,r"))] 3356 "TARGET_32BIT" 3357 "@ 3358 %q4. %3,%1,%2 3359 #" 3360 [(set_attr "type" "fast_compare,compare") 3361 (set_attr "length" "4,8")]) 3362 3363(define_split 3364 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 3365 (compare:CC (match_operator:SI 4 "boolean_operator" 3366 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3367 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) 3368 (const_int 0))) 3369 (clobber (match_scratch:SI 3 ""))] 3370 "TARGET_32BIT && reload_completed" 3371 [(set (match_dup 3) (match_dup 4)) 3372 (set (match_dup 0) 3373 (compare:CC (match_dup 3) 3374 (const_int 0)))] 3375 "") 3376 3377(define_insn "*boolccsi3_internal3" 3378 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 3379 (compare:CC (match_operator:SI 4 "boolean_operator" 3380 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r")) 3381 (not:SI (match_operand:SI 2 "gpc_reg_operand" "r,r"))]) 3382 (const_int 0))) 3383 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3384 (match_dup 4))] 3385 "TARGET_32BIT" 3386 "@ 3387 %q4. %0,%1,%2 3388 #" 3389 [(set_attr "type" "fast_compare,compare") 3390 (set_attr "length" "4,8")]) 3391 3392(define_split 3393 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 3394 (compare:CC (match_operator:SI 4 "boolean_operator" 3395 [(not:SI (match_operand:SI 1 "gpc_reg_operand" "")) 3396 (not:SI (match_operand:SI 2 "gpc_reg_operand" ""))]) 3397 (const_int 0))) 3398 (set (match_operand:SI 0 "gpc_reg_operand" "") 3399 (match_dup 4))] 3400 "TARGET_32BIT && reload_completed" 3401 [(set (match_dup 0) (match_dup 4)) 3402 (set (match_dup 3) 3403 (compare:CC (match_dup 0) 3404 (const_int 0)))] 3405 "") 3406 3407;; Rotate and shift insns, in all their variants. These support shifts, 3408;; field inserts and extracts, and various combinations thereof. 3409(define_expand "insv" 3410 [(set (zero_extract (match_operand 0 "gpc_reg_operand" "") 3411 (match_operand:SI 1 "const_int_operand" "") 3412 (match_operand:SI 2 "const_int_operand" "")) 3413 (match_operand 3 "gpc_reg_operand" ""))] 3414 "" 3415 " 3416{ 3417 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 3418 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 3419 compiler if the address of the structure is taken later. Likewise, do 3420 not handle invalid E500 subregs. */ 3421 if (GET_CODE (operands[0]) == SUBREG 3422 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD 3423 || ((TARGET_E500_DOUBLE || TARGET_SPE) 3424 && invalid_e500_subreg (operands[0], GET_MODE (operands[0]))))) 3425 FAIL; 3426 3427 if (TARGET_POWERPC64 && GET_MODE (operands[0]) == DImode) 3428 emit_insn (gen_insvdi_internal (operands[0], operands[1], operands[2], 3429 operands[3])); 3430 else 3431 emit_insn (gen_insvsi_internal (operands[0], operands[1], operands[2], 3432 operands[3])); 3433 DONE; 3434}") 3435 3436(define_insn "insvsi_internal" 3437 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3438 (match_operand:SI 1 "const_int_operand" "i") 3439 (match_operand:SI 2 "const_int_operand" "i")) 3440 (match_operand:SI 3 "gpc_reg_operand" "r"))] 3441 "" 3442 "* 3443{ 3444 int start = INTVAL (operands[2]) & 31; 3445 int size = INTVAL (operands[1]) & 31; 3446 3447 operands[4] = GEN_INT (32 - start - size); 3448 operands[1] = GEN_INT (start + size - 1); 3449 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3450}" 3451 [(set_attr "type" "insert_word")]) 3452 3453(define_insn "*insvsi_internal1" 3454 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3455 (match_operand:SI 1 "const_int_operand" "i") 3456 (match_operand:SI 2 "const_int_operand" "i")) 3457 (rotate:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3458 (match_operand:SI 4 "const_int_operand" "i")))] 3459 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 3460 "* 3461{ 3462 int shift = INTVAL (operands[4]) & 31; 3463 int start = INTVAL (operands[2]) & 31; 3464 int size = INTVAL (operands[1]) & 31; 3465 3466 operands[4] = GEN_INT (shift - start - size); 3467 operands[1] = GEN_INT (start + size - 1); 3468 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3469}" 3470 [(set_attr "type" "insert_word")]) 3471 3472(define_insn "*insvsi_internal2" 3473 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3474 (match_operand:SI 1 "const_int_operand" "i") 3475 (match_operand:SI 2 "const_int_operand" "i")) 3476 (ashiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3477 (match_operand:SI 4 "const_int_operand" "i")))] 3478 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 3479 "* 3480{ 3481 int shift = INTVAL (operands[4]) & 31; 3482 int start = INTVAL (operands[2]) & 31; 3483 int size = INTVAL (operands[1]) & 31; 3484 3485 operands[4] = GEN_INT (32 - shift - start - size); 3486 operands[1] = GEN_INT (start + size - 1); 3487 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3488}" 3489 [(set_attr "type" "insert_word")]) 3490 3491(define_insn "*insvsi_internal3" 3492 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3493 (match_operand:SI 1 "const_int_operand" "i") 3494 (match_operand:SI 2 "const_int_operand" "i")) 3495 (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3496 (match_operand:SI 4 "const_int_operand" "i")))] 3497 "(32 - (INTVAL (operands[4]) & 31)) >= INTVAL (operands[1])" 3498 "* 3499{ 3500 int shift = INTVAL (operands[4]) & 31; 3501 int start = INTVAL (operands[2]) & 31; 3502 int size = INTVAL (operands[1]) & 31; 3503 3504 operands[4] = GEN_INT (32 - shift - start - size); 3505 operands[1] = GEN_INT (start + size - 1); 3506 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3507}" 3508 [(set_attr "type" "insert_word")]) 3509 3510(define_insn "*insvsi_internal4" 3511 [(set (zero_extract:SI (match_operand:SI 0 "gpc_reg_operand" "+r") 3512 (match_operand:SI 1 "const_int_operand" "i") 3513 (match_operand:SI 2 "const_int_operand" "i")) 3514 (zero_extract:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3515 (match_operand:SI 4 "const_int_operand" "i") 3516 (match_operand:SI 5 "const_int_operand" "i")))] 3517 "INTVAL (operands[4]) >= INTVAL (operands[1])" 3518 "* 3519{ 3520 int extract_start = INTVAL (operands[5]) & 31; 3521 int extract_size = INTVAL (operands[4]) & 31; 3522 int insert_start = INTVAL (operands[2]) & 31; 3523 int insert_size = INTVAL (operands[1]) & 31; 3524 3525/* Align extract field with insert field */ 3526 operands[5] = GEN_INT (extract_start + extract_size - insert_start - insert_size); 3527 operands[1] = GEN_INT (insert_start + insert_size - 1); 3528 return \"rlwimi %0,%3,%h5,%h2,%h1\"; 3529}" 3530 [(set_attr "type" "insert_word")]) 3531 3532;; combine patterns for rlwimi 3533(define_insn "*insvsi_internal5" 3534 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3535 (ior:SI (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") 3536 (match_operand:SI 1 "mask_operand" "i")) 3537 (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3538 (match_operand:SI 2 "const_int_operand" "i")) 3539 (match_operand:SI 5 "mask_operand" "i"))))] 3540 "INTVAL(operands[1]) == ~INTVAL(operands[5])" 3541 "* 3542{ 3543 int me = extract_ME(operands[5]); 3544 int mb = extract_MB(operands[5]); 3545 operands[4] = GEN_INT(32 - INTVAL(operands[2])); 3546 operands[2] = GEN_INT(mb); 3547 operands[1] = GEN_INT(me); 3548 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3549}" 3550 [(set_attr "type" "insert_word")]) 3551 3552(define_insn "*insvsi_internal6" 3553 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3554 (ior:SI (and:SI (lshiftrt:SI (match_operand:SI 3 "gpc_reg_operand" "r") 3555 (match_operand:SI 2 "const_int_operand" "i")) 3556 (match_operand:SI 5 "mask_operand" "i")) 3557 (and:SI (match_operand:SI 4 "gpc_reg_operand" "0") 3558 (match_operand:SI 1 "mask_operand" "i"))))] 3559 "INTVAL(operands[1]) == ~INTVAL(operands[5])" 3560 "* 3561{ 3562 int me = extract_ME(operands[5]); 3563 int mb = extract_MB(operands[5]); 3564 operands[4] = GEN_INT(32 - INTVAL(operands[2])); 3565 operands[2] = GEN_INT(mb); 3566 operands[1] = GEN_INT(me); 3567 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3568}" 3569 [(set_attr "type" "insert_word")]) 3570 3571(define_insn "insvdi_internal" 3572 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") 3573 (match_operand:SI 1 "const_int_operand" "i") 3574 (match_operand:SI 2 "const_int_operand" "i")) 3575 (match_operand:DI 3 "gpc_reg_operand" "r"))] 3576 "TARGET_POWERPC64" 3577 "* 3578{ 3579 int start = INTVAL (operands[2]) & 63; 3580 int size = INTVAL (operands[1]) & 63; 3581 3582 operands[1] = GEN_INT (64 - start - size); 3583 return \"rldimi %0,%3,%H1,%H2\"; 3584}" 3585 [(set_attr "type" "insert_dword")]) 3586 3587(define_insn "*insvdi_internal2" 3588 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") 3589 (match_operand:SI 1 "const_int_operand" "i") 3590 (match_operand:SI 2 "const_int_operand" "i")) 3591 (ashiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") 3592 (match_operand:SI 4 "const_int_operand" "i")))] 3593 "TARGET_POWERPC64 3594 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" 3595 "* 3596{ 3597 int shift = INTVAL (operands[4]) & 63; 3598 int start = (INTVAL (operands[2]) & 63) - 32; 3599 int size = INTVAL (operands[1]) & 63; 3600 3601 operands[4] = GEN_INT (64 - shift - start - size); 3602 operands[2] = GEN_INT (start); 3603 operands[1] = GEN_INT (start + size - 1); 3604 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3605}") 3606 3607(define_insn "*insvdi_internal3" 3608 [(set (zero_extract:DI (match_operand:DI 0 "gpc_reg_operand" "+r") 3609 (match_operand:SI 1 "const_int_operand" "i") 3610 (match_operand:SI 2 "const_int_operand" "i")) 3611 (lshiftrt:DI (match_operand:DI 3 "gpc_reg_operand" "r") 3612 (match_operand:SI 4 "const_int_operand" "i")))] 3613 "TARGET_POWERPC64 3614 && insvdi_rshift_rlwimi_p (operands[1], operands[2], operands[4])" 3615 "* 3616{ 3617 int shift = INTVAL (operands[4]) & 63; 3618 int start = (INTVAL (operands[2]) & 63) - 32; 3619 int size = INTVAL (operands[1]) & 63; 3620 3621 operands[4] = GEN_INT (64 - shift - start - size); 3622 operands[2] = GEN_INT (start); 3623 operands[1] = GEN_INT (start + size - 1); 3624 return \"rlwimi %0,%3,%h4,%h2,%h1\"; 3625}") 3626 3627(define_expand "extzv" 3628 [(set (match_operand 0 "gpc_reg_operand" "") 3629 (zero_extract (match_operand 1 "gpc_reg_operand" "") 3630 (match_operand:SI 2 "const_int_operand" "") 3631 (match_operand:SI 3 "const_int_operand" "")))] 3632 "" 3633 " 3634{ 3635 /* Do not handle 16/8 bit structures that fit in HI/QI modes directly, since 3636 the (SUBREG:SI (REG:HI xxx)) that is otherwise generated can confuse the 3637 compiler if the address of the structure is taken later. */ 3638 if (GET_CODE (operands[0]) == SUBREG 3639 && (GET_MODE_SIZE (GET_MODE (SUBREG_REG (operands[0]))) < UNITS_PER_WORD)) 3640 FAIL; 3641 3642 if (TARGET_POWERPC64 && GET_MODE (operands[1]) == DImode) 3643 emit_insn (gen_extzvdi_internal (operands[0], operands[1], operands[2], 3644 operands[3])); 3645 else 3646 emit_insn (gen_extzvsi_internal (operands[0], operands[1], operands[2], 3647 operands[3])); 3648 DONE; 3649}") 3650 3651(define_insn "extzvsi_internal" 3652 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 3653 (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r") 3654 (match_operand:SI 2 "const_int_operand" "i") 3655 (match_operand:SI 3 "const_int_operand" "i")))] 3656 "" 3657 "* 3658{ 3659 int start = INTVAL (operands[3]) & 31; 3660 int size = INTVAL (operands[2]) & 31; 3661 3662 if (start + size >= 32) 3663 operands[3] = const0_rtx; 3664 else 3665 operands[3] = GEN_INT (start + size); 3666 return \"rlwinm %0,%1,%3,%s2,31\"; 3667}") 3668 3669(define_insn "*extzvsi_internal1" 3670 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 3671 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3672 (match_operand:SI 2 "const_int_operand" "i,i") 3673 (match_operand:SI 3 "const_int_operand" "i,i")) 3674 (const_int 0))) 3675 (clobber (match_scratch:SI 4 "=r,r"))] 3676 "" 3677 "* 3678{ 3679 int start = INTVAL (operands[3]) & 31; 3680 int size = INTVAL (operands[2]) & 31; 3681 3682 /* Force split for non-cc0 compare. */ 3683 if (which_alternative == 1) 3684 return \"#\"; 3685 3686 /* If the bit-field being tested fits in the upper or lower half of a 3687 word, it is possible to use andiu. or andil. to test it. This is 3688 useful because the condition register set-use delay is smaller for 3689 andi[ul]. than for rlinm. This doesn't work when the starting bit 3690 position is 0 because the LT and GT bits may be set wrong. */ 3691 3692 if ((start > 0 && start + size <= 16) || start >= 16) 3693 { 3694 operands[3] = GEN_INT (((1 << (16 - (start & 15))) 3695 - (1 << (16 - (start & 15) - size)))); 3696 if (start < 16) 3697 return \"andis. %4,%1,%3\"; 3698 else 3699 return \"andi. %4,%1,%3\"; 3700 } 3701 3702 if (start + size >= 32) 3703 operands[3] = const0_rtx; 3704 else 3705 operands[3] = GEN_INT (start + size); 3706 return \"rlwinm. %4,%1,%3,%s2,31\"; 3707}" 3708 [(set_attr "type" "delayed_compare") 3709 (set_attr "length" "4,8")]) 3710 3711(define_split 3712 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 3713 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 3714 (match_operand:SI 2 "const_int_operand" "") 3715 (match_operand:SI 3 "const_int_operand" "")) 3716 (const_int 0))) 3717 (clobber (match_scratch:SI 4 ""))] 3718 "reload_completed" 3719 [(set (match_dup 4) 3720 (zero_extract:SI (match_dup 1) (match_dup 2) 3721 (match_dup 3))) 3722 (set (match_dup 0) 3723 (compare:CC (match_dup 4) 3724 (const_int 0)))] 3725 "") 3726 3727(define_insn "*extzvsi_internal2" 3728 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 3729 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3730 (match_operand:SI 2 "const_int_operand" "i,i") 3731 (match_operand:SI 3 "const_int_operand" "i,i")) 3732 (const_int 0))) 3733 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3734 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 3735 "" 3736 "* 3737{ 3738 int start = INTVAL (operands[3]) & 31; 3739 int size = INTVAL (operands[2]) & 31; 3740 3741 /* Force split for non-cc0 compare. */ 3742 if (which_alternative == 1) 3743 return \"#\"; 3744 3745 /* Since we are using the output value, we can't ignore any need for 3746 a shift. The bit-field must end at the LSB. */ 3747 if (start >= 16 && start + size == 32) 3748 { 3749 operands[3] = GEN_INT ((1 << size) - 1); 3750 return \"andi. %0,%1,%3\"; 3751 } 3752 3753 if (start + size >= 32) 3754 operands[3] = const0_rtx; 3755 else 3756 operands[3] = GEN_INT (start + size); 3757 return \"rlwinm. %0,%1,%3,%s2,31\"; 3758}" 3759 [(set_attr "type" "delayed_compare") 3760 (set_attr "length" "4,8")]) 3761 3762(define_split 3763 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") 3764 (compare:CC (zero_extract:SI (match_operand:SI 1 "gpc_reg_operand" "") 3765 (match_operand:SI 2 "const_int_operand" "") 3766 (match_operand:SI 3 "const_int_operand" "")) 3767 (const_int 0))) 3768 (set (match_operand:SI 0 "gpc_reg_operand" "") 3769 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3)))] 3770 "reload_completed" 3771 [(set (match_dup 0) 3772 (zero_extract:SI (match_dup 1) (match_dup 2) (match_dup 3))) 3773 (set (match_dup 4) 3774 (compare:CC (match_dup 0) 3775 (const_int 0)))] 3776 "") 3777 3778(define_insn "extzvdi_internal" 3779 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 3780 (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3781 (match_operand:SI 2 "const_int_operand" "i") 3782 (match_operand:SI 3 "const_int_operand" "i")))] 3783 "TARGET_POWERPC64" 3784 "* 3785{ 3786 int start = INTVAL (operands[3]) & 63; 3787 int size = INTVAL (operands[2]) & 63; 3788 3789 if (start + size >= 64) 3790 operands[3] = const0_rtx; 3791 else 3792 operands[3] = GEN_INT (start + size); 3793 operands[2] = GEN_INT (64 - size); 3794 return \"rldicl %0,%1,%3,%2\"; 3795}") 3796 3797(define_insn "*extzvdi_internal1" 3798 [(set (match_operand:CC 0 "gpc_reg_operand" "=x") 3799 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3800 (match_operand:SI 2 "const_int_operand" "i") 3801 (match_operand:SI 3 "const_int_operand" "i")) 3802 (const_int 0))) 3803 (clobber (match_scratch:DI 4 "=r"))] 3804 "TARGET_64BIT && rs6000_gen_cell_microcode" 3805 "* 3806{ 3807 int start = INTVAL (operands[3]) & 63; 3808 int size = INTVAL (operands[2]) & 63; 3809 3810 if (start + size >= 64) 3811 operands[3] = const0_rtx; 3812 else 3813 operands[3] = GEN_INT (start + size); 3814 operands[2] = GEN_INT (64 - size); 3815 return \"rldicl. %4,%1,%3,%2\"; 3816}" 3817 [(set_attr "type" "compare")]) 3818 3819(define_insn "*extzvdi_internal2" 3820 [(set (match_operand:CC 4 "gpc_reg_operand" "=x") 3821 (compare:CC (zero_extract:DI (match_operand:DI 1 "gpc_reg_operand" "r") 3822 (match_operand:SI 2 "const_int_operand" "i") 3823 (match_operand:SI 3 "const_int_operand" "i")) 3824 (const_int 0))) 3825 (set (match_operand:DI 0 "gpc_reg_operand" "=r") 3826 (zero_extract:DI (match_dup 1) (match_dup 2) (match_dup 3)))] 3827 "TARGET_64BIT && rs6000_gen_cell_microcode" 3828 "* 3829{ 3830 int start = INTVAL (operands[3]) & 63; 3831 int size = INTVAL (operands[2]) & 63; 3832 3833 if (start + size >= 64) 3834 operands[3] = const0_rtx; 3835 else 3836 operands[3] = GEN_INT (start + size); 3837 operands[2] = GEN_INT (64 - size); 3838 return \"rldicl. %0,%1,%3,%2\"; 3839}" 3840 [(set_attr "type" "compare")]) 3841 3842(define_insn "rotlsi3" 3843 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3844 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3845 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] 3846 "" 3847 "@ 3848 rlwnm %0,%1,%2,0xffffffff 3849 rlwinm %0,%1,%h2,0xffffffff" 3850 [(set_attr "type" "var_shift_rotate,integer")]) 3851 3852(define_insn "*rotlsi3_64" 3853 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 3854 (zero_extend:DI 3855 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3856 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] 3857 "TARGET_64BIT" 3858 "@ 3859 rlwnm %0,%1,%2,0xffffffff 3860 rlwinm %0,%1,%h2,0xffffffff" 3861 [(set_attr "type" "var_shift_rotate,integer")]) 3862 3863(define_insn "*rotlsi3_internal2" 3864 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 3865 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 3866 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3867 (const_int 0))) 3868 (clobber (match_scratch:SI 3 "=r,r,r,r"))] 3869 "" 3870 "@ 3871 rlwnm. %3,%1,%2,0xffffffff 3872 rlwinm. %3,%1,%h2,0xffffffff 3873 # 3874 #" 3875 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 3876 (set_attr "length" "4,4,8,8")]) 3877 3878(define_split 3879 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 3880 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3881 (match_operand:SI 2 "reg_or_cint_operand" "")) 3882 (const_int 0))) 3883 (clobber (match_scratch:SI 3 ""))] 3884 "reload_completed" 3885 [(set (match_dup 3) 3886 (rotate:SI (match_dup 1) (match_dup 2))) 3887 (set (match_dup 0) 3888 (compare:CC (match_dup 3) 3889 (const_int 0)))] 3890 "") 3891 3892(define_insn "*rotlsi3_internal3" 3893 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 3894 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 3895 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3896 (const_int 0))) 3897 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 3898 (rotate:SI (match_dup 1) (match_dup 2)))] 3899 "" 3900 "@ 3901 rlwnm. %0,%1,%2,0xffffffff 3902 rlwinm. %0,%1,%h2,0xffffffff 3903 # 3904 #" 3905 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 3906 (set_attr "length" "4,4,8,8")]) 3907 3908(define_split 3909 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 3910 (compare:CC (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3911 (match_operand:SI 2 "reg_or_cint_operand" "")) 3912 (const_int 0))) 3913 (set (match_operand:SI 0 "gpc_reg_operand" "") 3914 (rotate:SI (match_dup 1) (match_dup 2)))] 3915 "reload_completed" 3916 [(set (match_dup 0) 3917 (rotate:SI (match_dup 1) (match_dup 2))) 3918 (set (match_dup 3) 3919 (compare:CC (match_dup 0) 3920 (const_int 0)))] 3921 "") 3922 3923(define_insn "*rotlsi3_internal4" 3924 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 3925 (and:SI (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 3926 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 3927 (match_operand:SI 3 "mask_operand" "n,n")))] 3928 "" 3929 "@ 3930 rlwnm %0,%1,%2,%m3,%M3 3931 rlwinm %0,%1,%h2,%m3,%M3" 3932 [(set_attr "type" "var_shift_rotate,integer")]) 3933 3934(define_insn "*rotlsi3_internal5" 3935 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 3936 (compare:CC (and:SI 3937 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 3938 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3939 (match_operand:SI 3 "mask_operand" "n,n,n,n")) 3940 (const_int 0))) 3941 (clobber (match_scratch:SI 4 "=r,r,r,r"))] 3942 "" 3943 "@ 3944 rlwnm. %4,%1,%2,%m3,%M3 3945 rlwinm. %4,%1,%h2,%m3,%M3 3946 # 3947 #" 3948 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 3949 (set_attr "length" "4,4,8,8")]) 3950 3951(define_split 3952 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 3953 (compare:CC (and:SI 3954 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3955 (match_operand:SI 2 "reg_or_cint_operand" "")) 3956 (match_operand:SI 3 "mask_operand" "")) 3957 (const_int 0))) 3958 (clobber (match_scratch:SI 4 ""))] 3959 "reload_completed" 3960 [(set (match_dup 4) 3961 (and:SI (rotate:SI (match_dup 1) 3962 (match_dup 2)) 3963 (match_dup 3))) 3964 (set (match_dup 0) 3965 (compare:CC (match_dup 4) 3966 (const_int 0)))] 3967 "") 3968 3969(define_insn "*rotlsi3_internal6" 3970 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 3971 (compare:CC (and:SI 3972 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 3973 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3974 (match_operand:SI 3 "mask_operand" "n,n,n,n")) 3975 (const_int 0))) 3976 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 3977 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3978 "" 3979 "@ 3980 rlwnm. %0,%1,%2,%m3,%M3 3981 rlwinm. %0,%1,%h2,%m3,%M3 3982 # 3983 #" 3984 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 3985 (set_attr "length" "4,4,8,8")]) 3986 3987(define_split 3988 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") 3989 (compare:CC (and:SI 3990 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 3991 (match_operand:SI 2 "reg_or_cint_operand" "")) 3992 (match_operand:SI 3 "mask_operand" "")) 3993 (const_int 0))) 3994 (set (match_operand:SI 0 "gpc_reg_operand" "") 3995 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 3996 "reload_completed" 3997 [(set (match_dup 0) 3998 (and:SI (rotate:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 3999 (set (match_dup 4) 4000 (compare:CC (match_dup 0) 4001 (const_int 0)))] 4002 "") 4003 4004(define_insn "*rotlsi3_internal7le" 4005 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4006 (zero_extend:SI 4007 (subreg:QI 4008 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4009 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 0)))] 4010 "!BYTES_BIG_ENDIAN" 4011 "rlw%I2nm %0,%1,%h2,0xff" 4012 [(set (attr "cell_micro") 4013 (if_then_else (match_operand:SI 2 "const_int_operand" "") 4014 (const_string "not") 4015 (const_string "always")))]) 4016 4017(define_insn "*rotlsi3_internal7be" 4018 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4019 (zero_extend:SI 4020 (subreg:QI 4021 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4022 (match_operand:SI 2 "reg_or_cint_operand" "ri")) 3)))] 4023 "BYTES_BIG_ENDIAN" 4024 "rlw%I2nm %0,%1,%h2,0xff" 4025 [(set (attr "cell_micro") 4026 (if_then_else (match_operand:SI 2 "const_int_operand" "") 4027 (const_string "not") 4028 (const_string "always")))]) 4029 4030(define_insn "*rotlsi3_internal8le" 4031 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4032 (compare:CC (zero_extend:SI 4033 (subreg:QI 4034 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4035 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 4036 (const_int 0))) 4037 (clobber (match_scratch:SI 3 "=r,r,r,r"))] 4038 "!BYTES_BIG_ENDIAN" 4039 "@ 4040 rlwnm. %3,%1,%2,0xff 4041 rlwinm. %3,%1,%h2,0xff 4042 # 4043 #" 4044 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4045 (set_attr "length" "4,4,8,8")]) 4046 4047(define_insn "*rotlsi3_internal8be" 4048 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4049 (compare:CC (zero_extend:SI 4050 (subreg:QI 4051 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4052 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3)) 4053 (const_int 0))) 4054 (clobber (match_scratch:SI 3 "=r,r,r,r"))] 4055 "BYTES_BIG_ENDIAN" 4056 "@ 4057 rlwnm. %3,%1,%2,0xff 4058 rlwinm. %3,%1,%h2,0xff 4059 # 4060 #" 4061 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4062 (set_attr "length" "4,4,8,8")]) 4063 4064(define_split 4065 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4066 (compare:CC (zero_extend:SI 4067 (subreg:QI 4068 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4069 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 4070 (const_int 0))) 4071 (clobber (match_scratch:SI 3 ""))] 4072 "!BYTES_BIG_ENDIAN && reload_completed" 4073 [(set (match_dup 3) 4074 (zero_extend:SI (subreg:QI 4075 (rotate:SI (match_dup 1) 4076 (match_dup 2)) 0))) 4077 (set (match_dup 0) 4078 (compare:CC (match_dup 3) 4079 (const_int 0)))] 4080 "") 4081 4082(define_split 4083 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4084 (compare:CC (zero_extend:SI 4085 (subreg:QI 4086 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4087 (match_operand:SI 2 "reg_or_cint_operand" "")) 3)) 4088 (const_int 0))) 4089 (clobber (match_scratch:SI 3 ""))] 4090 "BYTES_BIG_ENDIAN && reload_completed" 4091 [(set (match_dup 3) 4092 (zero_extend:SI (subreg:QI 4093 (rotate:SI (match_dup 1) 4094 (match_dup 2)) 3))) 4095 (set (match_dup 0) 4096 (compare:CC (match_dup 3) 4097 (const_int 0)))] 4098 "") 4099 4100(define_insn "*rotlsi3_internal9le" 4101 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4102 (compare:CC (zero_extend:SI 4103 (subreg:QI 4104 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4105 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 4106 (const_int 0))) 4107 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4108 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 4109 "!BYTES_BIG_ENDIAN" 4110 "@ 4111 rlwnm. %0,%1,%2,0xff 4112 rlwinm. %0,%1,%h2,0xff 4113 # 4114 #" 4115 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4116 (set_attr "length" "4,4,8,8")]) 4117 4118(define_insn "*rotlsi3_internal9be" 4119 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4120 (compare:CC (zero_extend:SI 4121 (subreg:QI 4122 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4123 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 3)) 4124 (const_int 0))) 4125 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4126 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))] 4127 "BYTES_BIG_ENDIAN" 4128 "@ 4129 rlwnm. %0,%1,%2,0xff 4130 rlwinm. %0,%1,%h2,0xff 4131 # 4132 #" 4133 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4134 (set_attr "length" "4,4,8,8")]) 4135 4136(define_split 4137 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 4138 (compare:CC (zero_extend:SI 4139 (subreg:QI 4140 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4141 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 4142 (const_int 0))) 4143 (set (match_operand:SI 0 "gpc_reg_operand" "") 4144 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 4145 "!BYTES_BIG_ENDIAN && reload_completed" 4146 [(set (match_dup 0) 4147 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 0))) 4148 (set (match_dup 3) 4149 (compare:CC (match_dup 0) 4150 (const_int 0)))] 4151 "") 4152 4153(define_split 4154 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 4155 (compare:CC (zero_extend:SI 4156 (subreg:QI 4157 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4158 (match_operand:SI 2 "reg_or_cint_operand" "")) 3)) 4159 (const_int 0))) 4160 (set (match_operand:SI 0 "gpc_reg_operand" "") 4161 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3)))] 4162 "BYTES_BIG_ENDIAN && reload_completed" 4163 [(set (match_dup 0) 4164 (zero_extend:SI (subreg:QI (rotate:SI (match_dup 1) (match_dup 2)) 3))) 4165 (set (match_dup 3) 4166 (compare:CC (match_dup 0) 4167 (const_int 0)))] 4168 "") 4169 4170(define_insn "*rotlsi3_internal10le" 4171 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4172 (zero_extend:SI 4173 (subreg:HI 4174 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4175 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 0)))] 4176 "!BYTES_BIG_ENDIAN" 4177 "@ 4178 rlwnm %0,%1,%2,0xffff 4179 rlwinm %0,%1,%h2,0xffff" 4180 [(set_attr "type" "var_shift_rotate,integer")]) 4181 4182(define_insn "*rotlsi3_internal10be" 4183 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4184 (zero_extend:SI 4185 (subreg:HI 4186 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4187 (match_operand:SI 2 "reg_or_cint_operand" "r,i")) 2)))] 4188 "BYTES_BIG_ENDIAN" 4189 "@ 4190 rlwnm %0,%1,%2,0xffff 4191 rlwinm %0,%1,%h2,0xffff" 4192 [(set_attr "type" "var_shift_rotate,integer")]) 4193 4194(define_insn "*rotlsi3_internal11le" 4195 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4196 (compare:CC (zero_extend:SI 4197 (subreg:HI 4198 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4199 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 4200 (const_int 0))) 4201 (clobber (match_scratch:SI 3 "=r,r,r,r"))] 4202 "!BYTES_BIG_ENDIAN" 4203 "@ 4204 rlwnm. %3,%1,%2,0xffff 4205 rlwinm. %3,%1,%h2,0xffff 4206 # 4207 #" 4208 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4209 (set_attr "length" "4,4,8,8")]) 4210 4211(define_insn "*rotlsi3_internal11be" 4212 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4213 (compare:CC (zero_extend:SI 4214 (subreg:HI 4215 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4216 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2)) 4217 (const_int 0))) 4218 (clobber (match_scratch:SI 3 "=r,r,r,r"))] 4219 "BYTES_BIG_ENDIAN" 4220 "@ 4221 rlwnm. %3,%1,%2,0xffff 4222 rlwinm. %3,%1,%h2,0xffff 4223 # 4224 #" 4225 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4226 (set_attr "length" "4,4,8,8")]) 4227 4228(define_split 4229 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4230 (compare:CC (zero_extend:SI 4231 (subreg:HI 4232 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4233 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 4234 (const_int 0))) 4235 (clobber (match_scratch:SI 3 ""))] 4236 "!BYTES_BIG_ENDIAN && reload_completed" 4237 [(set (match_dup 3) 4238 (zero_extend:SI (subreg:HI 4239 (rotate:SI (match_dup 1) 4240 (match_dup 2)) 0))) 4241 (set (match_dup 0) 4242 (compare:CC (match_dup 3) 4243 (const_int 0)))] 4244 "") 4245 4246(define_split 4247 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4248 (compare:CC (zero_extend:SI 4249 (subreg:HI 4250 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4251 (match_operand:SI 2 "reg_or_cint_operand" "")) 2)) 4252 (const_int 0))) 4253 (clobber (match_scratch:SI 3 ""))] 4254 "BYTES_BIG_ENDIAN && reload_completed" 4255 [(set (match_dup 3) 4256 (zero_extend:SI (subreg:HI 4257 (rotate:SI (match_dup 1) 4258 (match_dup 2)) 2))) 4259 (set (match_dup 0) 4260 (compare:CC (match_dup 3) 4261 (const_int 0)))] 4262 "") 4263 4264(define_insn "*rotlsi3_internal12le" 4265 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4266 (compare:CC (zero_extend:SI 4267 (subreg:HI 4268 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4269 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 4270 (const_int 0))) 4271 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4272 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 4273 "!BYTES_BIG_ENDIAN" 4274 "@ 4275 rlwnm. %0,%1,%2,0xffff 4276 rlwinm. %0,%1,%h2,0xffff 4277 # 4278 #" 4279 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4280 (set_attr "length" "4,4,8,8")]) 4281 4282(define_insn "*rotlsi3_internal12be" 4283 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4284 (compare:CC (zero_extend:SI 4285 (subreg:HI 4286 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4287 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 2)) 4288 (const_int 0))) 4289 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4290 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))] 4291 "BYTES_BIG_ENDIAN" 4292 "@ 4293 rlwnm. %0,%1,%2,0xffff 4294 rlwinm. %0,%1,%h2,0xffff 4295 # 4296 #" 4297 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4298 (set_attr "length" "4,4,8,8")]) 4299 4300(define_split 4301 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 4302 (compare:CC (zero_extend:SI 4303 (subreg:HI 4304 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4305 (match_operand:SI 2 "reg_or_cint_operand" "")) 0)) 4306 (const_int 0))) 4307 (set (match_operand:SI 0 "gpc_reg_operand" "") 4308 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0)))] 4309 "!BYTES_BIG_ENDIAN && reload_completed" 4310 [(set (match_dup 0) 4311 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 0))) 4312 (set (match_dup 3) 4313 (compare:CC (match_dup 0) 4314 (const_int 0)))] 4315 "") 4316 4317(define_split 4318 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 4319 (compare:CC (zero_extend:SI 4320 (subreg:HI 4321 (rotate:SI (match_operand:SI 1 "gpc_reg_operand" "") 4322 (match_operand:SI 2 "reg_or_cint_operand" "")) 2)) 4323 (const_int 0))) 4324 (set (match_operand:SI 0 "gpc_reg_operand" "") 4325 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2)))] 4326 "BYTES_BIG_ENDIAN && reload_completed" 4327 [(set (match_dup 0) 4328 (zero_extend:SI (subreg:HI (rotate:SI (match_dup 1) (match_dup 2)) 2))) 4329 (set (match_dup 3) 4330 (compare:CC (match_dup 0) 4331 (const_int 0)))] 4332 "") 4333 4334(define_insn "ashlsi3" 4335 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4336 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4337 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] 4338 "" 4339 "@ 4340 slw %0,%1,%2 4341 slwi %0,%1,%h2" 4342 [(set_attr "type" "var_shift_rotate,shift")]) 4343 4344(define_insn "*ashlsi3_64" 4345 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 4346 (zero_extend:DI 4347 (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4348 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] 4349 "TARGET_POWERPC64" 4350 "@ 4351 slw %0,%1,%2 4352 slwi %0,%1,%h2" 4353 [(set_attr "type" "var_shift_rotate,shift")]) 4354 4355(define_insn "" 4356 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4357 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4358 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4359 (const_int 0))) 4360 (clobber (match_scratch:SI 3 "=r,r,r,r"))] 4361 "TARGET_32BIT" 4362 "@ 4363 slw. %3,%1,%2 4364 slwi. %3,%1,%h2 4365 # 4366 #" 4367 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4368 (set_attr "length" "4,4,8,8")]) 4369 4370(define_split 4371 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4372 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4373 (match_operand:SI 2 "reg_or_cint_operand" "")) 4374 (const_int 0))) 4375 (clobber (match_scratch:SI 3 ""))] 4376 "TARGET_32BIT && reload_completed" 4377 [(set (match_dup 3) 4378 (ashift:SI (match_dup 1) (match_dup 2))) 4379 (set (match_dup 0) 4380 (compare:CC (match_dup 3) 4381 (const_int 0)))] 4382 "") 4383 4384(define_insn "" 4385 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 4386 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4387 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4388 (const_int 0))) 4389 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 4390 (ashift:SI (match_dup 1) (match_dup 2)))] 4391 "TARGET_32BIT" 4392 "@ 4393 slw. %0,%1,%2 4394 slwi. %0,%1,%h2 4395 # 4396 #" 4397 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4398 (set_attr "length" "4,4,8,8")]) 4399 4400(define_split 4401 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4402 (compare:CC (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4403 (match_operand:SI 2 "reg_or_cint_operand" "")) 4404 (const_int 0))) 4405 (set (match_operand:SI 0 "gpc_reg_operand" "") 4406 (ashift:SI (match_dup 1) (match_dup 2)))] 4407 "TARGET_32BIT && reload_completed" 4408 [(set (match_dup 0) 4409 (ashift:SI (match_dup 1) (match_dup 2))) 4410 (set (match_dup 3) 4411 (compare:CC (match_dup 0) 4412 (const_int 0)))] 4413 "") 4414 4415(define_insn "rlwinm" 4416 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4417 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4418 (match_operand:SI 2 "const_int_operand" "i")) 4419 (match_operand:SI 3 "mask_operand" "n")))] 4420 "includes_lshift_p (operands[2], operands[3])" 4421 "rlwinm %0,%1,%h2,%m3,%M3") 4422 4423(define_insn "" 4424 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4425 (compare:CC 4426 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4427 (match_operand:SI 2 "const_int_operand" "i,i")) 4428 (match_operand:SI 3 "mask_operand" "n,n")) 4429 (const_int 0))) 4430 (clobber (match_scratch:SI 4 "=r,r"))] 4431 "includes_lshift_p (operands[2], operands[3])" 4432 "@ 4433 rlwinm. %4,%1,%h2,%m3,%M3 4434 #" 4435 [(set_attr "type" "delayed_compare") 4436 (set_attr "length" "4,8")]) 4437 4438(define_split 4439 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4440 (compare:CC 4441 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4442 (match_operand:SI 2 "const_int_operand" "")) 4443 (match_operand:SI 3 "mask_operand" "")) 4444 (const_int 0))) 4445 (clobber (match_scratch:SI 4 ""))] 4446 "includes_lshift_p (operands[2], operands[3]) && reload_completed" 4447 [(set (match_dup 4) 4448 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) 4449 (match_dup 3))) 4450 (set (match_dup 0) 4451 (compare:CC (match_dup 4) 4452 (const_int 0)))] 4453 "") 4454 4455(define_insn "" 4456 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 4457 (compare:CC 4458 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4459 (match_operand:SI 2 "const_int_operand" "i,i")) 4460 (match_operand:SI 3 "mask_operand" "n,n")) 4461 (const_int 0))) 4462 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4463 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4464 "includes_lshift_p (operands[2], operands[3])" 4465 "@ 4466 rlwinm. %0,%1,%h2,%m3,%M3 4467 #" 4468 [(set_attr "type" "delayed_compare") 4469 (set_attr "length" "4,8")]) 4470 4471(define_split 4472 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") 4473 (compare:CC 4474 (and:SI (ashift:SI (match_operand:SI 1 "gpc_reg_operand" "") 4475 (match_operand:SI 2 "const_int_operand" "")) 4476 (match_operand:SI 3 "mask_operand" "")) 4477 (const_int 0))) 4478 (set (match_operand:SI 0 "gpc_reg_operand" "") 4479 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4480 "includes_lshift_p (operands[2], operands[3]) && reload_completed" 4481 [(set (match_dup 0) 4482 (and:SI (ashift:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 4483 (set (match_dup 4) 4484 (compare:CC (match_dup 0) 4485 (const_int 0)))] 4486 "") 4487 4488(define_insn "lshrsi3" 4489 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r") 4490 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r") 4491 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))] 4492 "" 4493 "@ 4494 mr %0,%1 4495 srw %0,%1,%2 4496 srwi %0,%1,%h2" 4497 [(set_attr "type" "integer,var_shift_rotate,shift")]) 4498 4499(define_insn "*lshrsi3_64" 4500 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 4501 (zero_extend:DI 4502 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4503 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] 4504 "TARGET_POWERPC64" 4505 "@ 4506 srw %0,%1,%2 4507 srwi %0,%1,%h2" 4508 [(set_attr "type" "var_shift_rotate,shift")]) 4509 4510(define_insn "" 4511 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y") 4512 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") 4513 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i")) 4514 (const_int 0))) 4515 (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))] 4516 "TARGET_32BIT" 4517 "@ 4518 mr. %1,%1 4519 srw. %3,%1,%2 4520 srwi. %3,%1,%h2 4521 # 4522 # 4523 #" 4524 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4525 (set_attr "length" "4,4,4,8,8,8")]) 4526 4527(define_split 4528 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 4529 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4530 (match_operand:SI 2 "reg_or_cint_operand" "")) 4531 (const_int 0))) 4532 (clobber (match_scratch:SI 3 ""))] 4533 "TARGET_32BIT && reload_completed" 4534 [(set (match_dup 3) 4535 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4536 (set (match_dup 0) 4537 (compare:CC (match_dup 3) 4538 (const_int 0)))] 4539 "") 4540 4541(define_insn "" 4542 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y") 4543 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r") 4544 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i")) 4545 (const_int 0))) 4546 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r") 4547 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 4548 "TARGET_32BIT" 4549 "@ 4550 mr. %0,%1 4551 srw. %0,%1,%2 4552 srwi. %0,%1,%h2 4553 # 4554 # 4555 #" 4556 [(set_attr "type" "fast_compare,var_delayed_compare,delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4557 (set_attr "length" "4,4,4,8,8,8")]) 4558 4559(define_split 4560 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 4561 (compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4562 (match_operand:SI 2 "reg_or_cint_operand" "")) 4563 (const_int 0))) 4564 (set (match_operand:SI 0 "gpc_reg_operand" "") 4565 (lshiftrt:SI (match_dup 1) (match_dup 2)))] 4566 "TARGET_32BIT && reload_completed" 4567 [(set (match_dup 0) 4568 (lshiftrt:SI (match_dup 1) (match_dup 2))) 4569 (set (match_dup 3) 4570 (compare:CC (match_dup 0) 4571 (const_int 0)))] 4572 "") 4573 4574(define_insn "" 4575 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4576 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4577 (match_operand:SI 2 "const_int_operand" "i")) 4578 (match_operand:SI 3 "mask_operand" "n")))] 4579 "includes_rshift_p (operands[2], operands[3])" 4580 "rlwinm %0,%1,%s2,%m3,%M3") 4581 4582(define_insn "" 4583 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4584 (compare:CC 4585 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4586 (match_operand:SI 2 "const_int_operand" "i,i")) 4587 (match_operand:SI 3 "mask_operand" "n,n")) 4588 (const_int 0))) 4589 (clobber (match_scratch:SI 4 "=r,r"))] 4590 "includes_rshift_p (operands[2], operands[3])" 4591 "@ 4592 rlwinm. %4,%1,%s2,%m3,%M3 4593 #" 4594 [(set_attr "type" "delayed_compare") 4595 (set_attr "length" "4,8")]) 4596 4597(define_split 4598 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4599 (compare:CC 4600 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4601 (match_operand:SI 2 "const_int_operand" "")) 4602 (match_operand:SI 3 "mask_operand" "")) 4603 (const_int 0))) 4604 (clobber (match_scratch:SI 4 ""))] 4605 "includes_rshift_p (operands[2], operands[3]) && reload_completed" 4606 [(set (match_dup 4) 4607 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) 4608 (match_dup 3))) 4609 (set (match_dup 0) 4610 (compare:CC (match_dup 4) 4611 (const_int 0)))] 4612 "") 4613 4614(define_insn "" 4615 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 4616 (compare:CC 4617 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4618 (match_operand:SI 2 "const_int_operand" "i,i")) 4619 (match_operand:SI 3 "mask_operand" "n,n")) 4620 (const_int 0))) 4621 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4622 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4623 "includes_rshift_p (operands[2], operands[3])" 4624 "@ 4625 rlwinm. %0,%1,%s2,%m3,%M3 4626 #" 4627 [(set_attr "type" "delayed_compare") 4628 (set_attr "length" "4,8")]) 4629 4630(define_split 4631 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") 4632 (compare:CC 4633 (and:SI (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4634 (match_operand:SI 2 "const_int_operand" "")) 4635 (match_operand:SI 3 "mask_operand" "")) 4636 (const_int 0))) 4637 (set (match_operand:SI 0 "gpc_reg_operand" "") 4638 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 4639 "includes_rshift_p (operands[2], operands[3]) && reload_completed" 4640 [(set (match_dup 0) 4641 (and:SI (lshiftrt:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 4642 (set (match_dup 4) 4643 (compare:CC (match_dup 0) 4644 (const_int 0)))] 4645 "") 4646 4647(define_insn "*lshiftrt_internal1le" 4648 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4649 (zero_extend:SI 4650 (subreg:QI 4651 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4652 (match_operand:SI 2 "const_int_operand" "i")) 0)))] 4653 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" 4654 "rlwinm %0,%1,%s2,0xff") 4655 4656(define_insn "*lshiftrt_internal1be" 4657 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4658 (zero_extend:SI 4659 (subreg:QI 4660 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4661 (match_operand:SI 2 "const_int_operand" "i")) 3)))] 4662 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" 4663 "rlwinm %0,%1,%s2,0xff") 4664 4665(define_insn "*lshiftrt_internal2le" 4666 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4667 (compare:CC 4668 (zero_extend:SI 4669 (subreg:QI 4670 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4671 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4672 (const_int 0))) 4673 (clobber (match_scratch:SI 3 "=r,r"))] 4674 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" 4675 "@ 4676 rlwinm. %3,%1,%s2,0xff 4677 #" 4678 [(set_attr "type" "delayed_compare") 4679 (set_attr "length" "4,8")]) 4680 4681(define_insn "*lshiftrt_internal2be" 4682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4683 (compare:CC 4684 (zero_extend:SI 4685 (subreg:QI 4686 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4687 (match_operand:SI 2 "const_int_operand" "i,i")) 3)) 4688 (const_int 0))) 4689 (clobber (match_scratch:SI 3 "=r,r"))] 4690 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" 4691 "@ 4692 rlwinm. %3,%1,%s2,0xff 4693 #" 4694 [(set_attr "type" "delayed_compare") 4695 (set_attr "length" "4,8")]) 4696 4697(define_split 4698 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4699 (compare:CC 4700 (zero_extend:SI 4701 (subreg:QI 4702 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4703 (match_operand:SI 2 "const_int_operand" "")) 0)) 4704 (const_int 0))) 4705 (clobber (match_scratch:SI 3 ""))] 4706 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4707 [(set (match_dup 3) 4708 (zero_extend:SI (subreg:QI 4709 (lshiftrt:SI (match_dup 1) 4710 (match_dup 2)) 0))) 4711 (set (match_dup 0) 4712 (compare:CC (match_dup 3) 4713 (const_int 0)))] 4714 "") 4715 4716(define_split 4717 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4718 (compare:CC 4719 (zero_extend:SI 4720 (subreg:QI 4721 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4722 (match_operand:SI 2 "const_int_operand" "")) 3)) 4723 (const_int 0))) 4724 (clobber (match_scratch:SI 3 ""))] 4725 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4726 [(set (match_dup 3) 4727 (zero_extend:SI (subreg:QI 4728 (lshiftrt:SI (match_dup 1) 4729 (match_dup 2)) 3))) 4730 (set (match_dup 0) 4731 (compare:CC (match_dup 3) 4732 (const_int 0)))] 4733 "") 4734 4735(define_insn "*lshiftrt_internal3le" 4736 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4737 (compare:CC 4738 (zero_extend:SI 4739 (subreg:QI 4740 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4741 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4742 (const_int 0))) 4743 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4744 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4745 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" 4746 "@ 4747 rlwinm. %0,%1,%s2,0xff 4748 #" 4749 [(set_attr "type" "delayed_compare") 4750 (set_attr "length" "4,8")]) 4751 4752(define_insn "*lshiftrt_internal3be" 4753 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4754 (compare:CC 4755 (zero_extend:SI 4756 (subreg:QI 4757 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4758 (match_operand:SI 2 "const_int_operand" "i,i")) 3)) 4759 (const_int 0))) 4760 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4761 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))] 4762 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255))" 4763 "@ 4764 rlwinm. %0,%1,%s2,0xff 4765 #" 4766 [(set_attr "type" "delayed_compare") 4767 (set_attr "length" "4,8")]) 4768 4769(define_split 4770 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 4771 (compare:CC 4772 (zero_extend:SI 4773 (subreg:QI 4774 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4775 (match_operand:SI 2 "const_int_operand" "")) 0)) 4776 (const_int 0))) 4777 (set (match_operand:SI 0 "gpc_reg_operand" "") 4778 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4779 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4780 [(set (match_dup 0) 4781 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) 4782 (set (match_dup 3) 4783 (compare:CC (match_dup 0) 4784 (const_int 0)))] 4785 "") 4786 4787(define_split 4788 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 4789 (compare:CC 4790 (zero_extend:SI 4791 (subreg:QI 4792 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4793 (match_operand:SI 2 "const_int_operand" "")) 3)) 4794 (const_int 0))) 4795 (set (match_operand:SI 0 "gpc_reg_operand" "") 4796 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3)))] 4797 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (255)) && reload_completed" 4798 [(set (match_dup 0) 4799 (zero_extend:SI (subreg:QI (lshiftrt:SI (match_dup 1) (match_dup 2)) 3))) 4800 (set (match_dup 3) 4801 (compare:CC (match_dup 0) 4802 (const_int 0)))] 4803 "") 4804 4805(define_insn "*lshiftrt_internal4le" 4806 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4807 (zero_extend:SI 4808 (subreg:HI 4809 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4810 (match_operand:SI 2 "const_int_operand" "i")) 0)))] 4811 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" 4812 "rlwinm %0,%1,%s2,0xffff") 4813 4814(define_insn "*lshiftrt_internal4be" 4815 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 4816 (zero_extend:SI 4817 (subreg:HI 4818 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r") 4819 (match_operand:SI 2 "const_int_operand" "i")) 2)))] 4820 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" 4821 "rlwinm %0,%1,%s2,0xffff") 4822 4823(define_insn "*lshiftrt_internal5le" 4824 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4825 (compare:CC 4826 (zero_extend:SI 4827 (subreg:HI 4828 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4829 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4830 (const_int 0))) 4831 (clobber (match_scratch:SI 3 "=r,r"))] 4832 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" 4833 "@ 4834 rlwinm. %3,%1,%s2,0xffff 4835 #" 4836 [(set_attr "type" "delayed_compare") 4837 (set_attr "length" "4,8")]) 4838 4839(define_insn "*lshiftrt_internal5be" 4840 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 4841 (compare:CC 4842 (zero_extend:SI 4843 (subreg:HI 4844 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4845 (match_operand:SI 2 "const_int_operand" "i,i")) 2)) 4846 (const_int 0))) 4847 (clobber (match_scratch:SI 3 "=r,r"))] 4848 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" 4849 "@ 4850 rlwinm. %3,%1,%s2,0xffff 4851 #" 4852 [(set_attr "type" "delayed_compare") 4853 (set_attr "length" "4,8")]) 4854 4855(define_split 4856 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4857 (compare:CC 4858 (zero_extend:SI 4859 (subreg:HI 4860 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4861 (match_operand:SI 2 "const_int_operand" "")) 0)) 4862 (const_int 0))) 4863 (clobber (match_scratch:SI 3 ""))] 4864 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4865 [(set (match_dup 3) 4866 (zero_extend:SI (subreg:HI 4867 (lshiftrt:SI (match_dup 1) 4868 (match_dup 2)) 0))) 4869 (set (match_dup 0) 4870 (compare:CC (match_dup 3) 4871 (const_int 0)))] 4872 "") 4873 4874(define_split 4875 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 4876 (compare:CC 4877 (zero_extend:SI 4878 (subreg:HI 4879 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4880 (match_operand:SI 2 "const_int_operand" "")) 2)) 4881 (const_int 0))) 4882 (clobber (match_scratch:SI 3 ""))] 4883 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4884 [(set (match_dup 3) 4885 (zero_extend:SI (subreg:HI 4886 (lshiftrt:SI (match_dup 1) 4887 (match_dup 2)) 2))) 4888 (set (match_dup 0) 4889 (compare:CC (match_dup 3) 4890 (const_int 0)))] 4891 "") 4892 4893(define_insn "*lshiftrt_internal5le" 4894 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4895 (compare:CC 4896 (zero_extend:SI 4897 (subreg:HI 4898 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4899 (match_operand:SI 2 "const_int_operand" "i,i")) 0)) 4900 (const_int 0))) 4901 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4902 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4903 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" 4904 "@ 4905 rlwinm. %0,%1,%s2,0xffff 4906 #" 4907 [(set_attr "type" "delayed_compare") 4908 (set_attr "length" "4,8")]) 4909 4910(define_insn "*lshiftrt_internal5be" 4911 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 4912 (compare:CC 4913 (zero_extend:SI 4914 (subreg:HI 4915 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4916 (match_operand:SI 2 "const_int_operand" "i,i")) 2)) 4917 (const_int 0))) 4918 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4919 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))] 4920 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535))" 4921 "@ 4922 rlwinm. %0,%1,%s2,0xffff 4923 #" 4924 [(set_attr "type" "delayed_compare") 4925 (set_attr "length" "4,8")]) 4926 4927(define_split 4928 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 4929 (compare:CC 4930 (zero_extend:SI 4931 (subreg:HI 4932 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4933 (match_operand:SI 2 "const_int_operand" "")) 0)) 4934 (const_int 0))) 4935 (set (match_operand:SI 0 "gpc_reg_operand" "") 4936 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0)))] 4937 "!BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4938 [(set (match_dup 0) 4939 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 0))) 4940 (set (match_dup 3) 4941 (compare:CC (match_dup 0) 4942 (const_int 0)))] 4943 "") 4944 4945(define_split 4946 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 4947 (compare:CC 4948 (zero_extend:SI 4949 (subreg:HI 4950 (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 4951 (match_operand:SI 2 "const_int_operand" "")) 2)) 4952 (const_int 0))) 4953 (set (match_operand:SI 0 "gpc_reg_operand" "") 4954 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2)))] 4955 "BYTES_BIG_ENDIAN && includes_rshift_p (operands[2], GEN_INT (65535)) && reload_completed" 4956 [(set (match_dup 0) 4957 (zero_extend:SI (subreg:HI (lshiftrt:SI (match_dup 1) (match_dup 2)) 2))) 4958 (set (match_dup 3) 4959 (compare:CC (match_dup 0) 4960 (const_int 0)))] 4961 "") 4962 4963(define_insn "ashrsi3" 4964 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 4965 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4966 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] 4967 "" 4968 "@ 4969 sraw %0,%1,%2 4970 srawi %0,%1,%h2" 4971 [(set_attr "type" "var_shift_rotate,shift")]) 4972 4973(define_insn "*ashrsi3_64" 4974 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 4975 (sign_extend:DI 4976 (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 4977 (match_operand:SI 2 "reg_or_cint_operand" "r,i"))))] 4978 "TARGET_POWERPC64" 4979 "@ 4980 sraw %0,%1,%2 4981 srawi %0,%1,%h2" 4982 [(set_attr "type" "var_shift_rotate,shift")]) 4983 4984(define_insn "" 4985 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 4986 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 4987 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 4988 (const_int 0))) 4989 (clobber (match_scratch:SI 3 "=r,r,r,r"))] 4990 "" 4991 "@ 4992 sraw. %3,%1,%2 4993 srawi. %3,%1,%h2 4994 # 4995 #" 4996 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 4997 (set_attr "length" "4,4,8,8")]) 4998 4999(define_split 5000 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 5001 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 5002 (match_operand:SI 2 "reg_or_cint_operand" "")) 5003 (const_int 0))) 5004 (clobber (match_scratch:SI 3 ""))] 5005 "reload_completed" 5006 [(set (match_dup 3) 5007 (ashiftrt:SI (match_dup 1) (match_dup 2))) 5008 (set (match_dup 0) 5009 (compare:CC (match_dup 3) 5010 (const_int 0)))] 5011 "") 5012 5013(define_insn "" 5014 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 5015 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 5016 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 5017 (const_int 0))) 5018 (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r") 5019 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 5020 "" 5021 "@ 5022 sraw. %0,%1,%2 5023 srawi. %0,%1,%h2 5024 # 5025 #" 5026 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 5027 (set_attr "length" "4,4,8,8")]) 5028 5029;; Builtins to replace a division to generate FRE reciprocal estimate 5030;; instructions and the necessary fixup instructions 5031(define_expand "recip<mode>3" 5032 [(match_operand:RECIPF 0 "gpc_reg_operand" "") 5033 (match_operand:RECIPF 1 "gpc_reg_operand" "") 5034 (match_operand:RECIPF 2 "gpc_reg_operand" "")] 5035 "RS6000_RECIP_HAVE_RE_P (<MODE>mode)" 5036{ 5037 rs6000_emit_swdiv (operands[0], operands[1], operands[2], false); 5038 DONE; 5039}) 5040 5041;; Split to create division from FRE/FRES/etc. and fixup instead of the normal 5042;; hardware division. This is only done before register allocation and with 5043;; -ffast-math. This must appear before the divsf3/divdf3 insns. 5044(define_split 5045 [(set (match_operand:RECIPF 0 "gpc_reg_operand" "") 5046 (div:RECIPF (match_operand 1 "gpc_reg_operand" "") 5047 (match_operand 2 "gpc_reg_operand" "")))] 5048 "RS6000_RECIP_AUTO_RE_P (<MODE>mode) 5049 && can_create_pseudo_p () && optimize_insn_for_speed_p () 5050 && flag_finite_math_only && !flag_trapping_math && flag_reciprocal_math" 5051 [(const_int 0)] 5052{ 5053 rs6000_emit_swdiv (operands[0], operands[1], operands[2], true); 5054 DONE; 5055}) 5056 5057;; Builtins to replace 1/sqrt(x) with instructions using RSQRTE and the 5058;; appropriate fixup. 5059(define_expand "rsqrt<mode>2" 5060 [(match_operand:RECIPF 0 "gpc_reg_operand" "") 5061 (match_operand:RECIPF 1 "gpc_reg_operand" "")] 5062 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)" 5063{ 5064 rs6000_emit_swrsqrt (operands[0], operands[1]); 5065 DONE; 5066}) 5067 5068(define_split 5069 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 5070 (compare:CC (ashiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "") 5071 (match_operand:SI 2 "reg_or_cint_operand" "")) 5072 (const_int 0))) 5073 (set (match_operand:SI 0 "gpc_reg_operand" "") 5074 (ashiftrt:SI (match_dup 1) (match_dup 2)))] 5075 "reload_completed" 5076 [(set (match_dup 0) 5077 (ashiftrt:SI (match_dup 1) (match_dup 2))) 5078 (set (match_dup 3) 5079 (compare:CC (match_dup 0) 5080 (const_int 0)))] 5081 "") 5082 5083 5084;; Floating-point insns, excluding normal data motion. We combine the SF/DF 5085;; modes here, and also add in conditional vsx/power8-vector support to access 5086;; values in the traditional Altivec registers if the appropriate 5087;; -mupper-regs-{df,sf} option is enabled. 5088 5089(define_expand "abs<mode>2" 5090 [(set (match_operand:SFDF 0 "gpc_reg_operand" "") 5091 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] 5092 "TARGET_<MODE>_INSN" 5093 "") 5094 5095(define_insn "*abs<mode>2_fpr" 5096 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5097 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))] 5098 "TARGET_<MODE>_FPR" 5099 "@ 5100 fabs %0,%1 5101 xsabsdp %x0,%x1" 5102 [(set_attr "type" "fp") 5103 (set_attr "fp_type" "fp_addsub_<Fs>")]) 5104 5105(define_insn "*nabs<mode>2_fpr" 5106 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5107 (neg:SFDF 5108 (abs:SFDF 5109 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>"))))] 5110 "TARGET_<MODE>_FPR" 5111 "@ 5112 fnabs %0,%1 5113 xsnabsdp %x0,%x1" 5114 [(set_attr "type" "fp") 5115 (set_attr "fp_type" "fp_addsub_<Fs>")]) 5116 5117(define_expand "neg<mode>2" 5118 [(set (match_operand:SFDF 0 "gpc_reg_operand" "") 5119 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "")))] 5120 "TARGET_<MODE>_INSN" 5121 "") 5122 5123(define_insn "*neg<mode>2_fpr" 5124 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5125 (neg:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))] 5126 "TARGET_<MODE>_FPR" 5127 "@ 5128 fneg %0,%1 5129 xsnegdp %x0,%x1" 5130 [(set_attr "type" "fp") 5131 (set_attr "fp_type" "fp_addsub_<Fs>")]) 5132 5133(define_expand "add<mode>3" 5134 [(set (match_operand:SFDF 0 "gpc_reg_operand" "") 5135 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") 5136 (match_operand:SFDF 2 "gpc_reg_operand" "")))] 5137 "TARGET_<MODE>_INSN" 5138 "") 5139 5140(define_insn "*add<mode>3_fpr" 5141 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5142 (plus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>") 5143 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))] 5144 "TARGET_<MODE>_FPR" 5145 "@ 5146 fadd<Ftrad> %0,%1,%2 5147 xsadd<Fvsx> %x0,%x1,%x2" 5148 [(set_attr "type" "fp") 5149 (set_attr "fp_type" "fp_addsub_<Fs>")]) 5150 5151(define_expand "sub<mode>3" 5152 [(set (match_operand:SFDF 0 "gpc_reg_operand" "") 5153 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") 5154 (match_operand:SFDF 2 "gpc_reg_operand" "")))] 5155 "TARGET_<MODE>_INSN" 5156 "") 5157 5158(define_insn "*sub<mode>3_fpr" 5159 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5160 (minus:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>") 5161 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))] 5162 "TARGET_<MODE>_FPR" 5163 "@ 5164 fsub<Ftrad> %0,%1,%2 5165 xssub<Fvsx> %x0,%x1,%x2" 5166 [(set_attr "type" "fp") 5167 (set_attr "fp_type" "fp_addsub_<Fs>")]) 5168 5169(define_expand "mul<mode>3" 5170 [(set (match_operand:SFDF 0 "gpc_reg_operand" "") 5171 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") 5172 (match_operand:SFDF 2 "gpc_reg_operand" "")))] 5173 "TARGET_<MODE>_INSN" 5174 "") 5175 5176(define_insn "*mul<mode>3_fpr" 5177 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5178 (mult:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>") 5179 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))] 5180 "TARGET_<MODE>_FPR" 5181 "@ 5182 fmul<Ftrad> %0,%1,%2 5183 xsmul<Fvsx> %x0,%x1,%x2" 5184 [(set_attr "type" "dmul") 5185 (set_attr "fp_type" "fp_mul_<Fs>")]) 5186 5187(define_expand "div<mode>3" 5188 [(set (match_operand:SFDF 0 "gpc_reg_operand" "") 5189 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "") 5190 (match_operand:SFDF 2 "gpc_reg_operand" "")))] 5191 "TARGET_<MODE>_INSN && !TARGET_SIMPLE_FPU" 5192 "") 5193 5194(define_insn "*div<mode>3_fpr" 5195 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5196 (div:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>") 5197 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))] 5198 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU" 5199 "@ 5200 fdiv<Ftrad> %0,%1,%2 5201 xsdiv<Fvsx> %x0,%x1,%x2" 5202 [(set_attr "type" "<Fs>div") 5203 (set_attr "fp_type" "fp_div_<Fs>")]) 5204 5205(define_insn "sqrt<mode>2" 5206 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5207 (sqrt:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")))] 5208 "TARGET_<MODE>_FPR && !TARGET_SIMPLE_FPU 5209 && (TARGET_PPC_GPOPT || (<MODE>mode == SFmode && TARGET_XILINX_FPU))" 5210 "@ 5211 fsqrt<Ftrad> %0,%1 5212 xssqrt<Fvsx> %x0,%x1" 5213 [(set_attr "type" "<Fs>sqrt") 5214 (set_attr "fp_type" "fp_sqrt_<Fs>")]) 5215 5216;; Floating point reciprocal approximation 5217(define_insn "fre<Fs>" 5218 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5219 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] 5220 UNSPEC_FRES))] 5221 "TARGET_<FFRE>" 5222 "@ 5223 fre<Ftrad> %0,%1 5224 xsre<Fvsx> %x0,%x1" 5225 [(set_attr "type" "fp")]) 5226 5227(define_insn "*rsqrt<mode>2" 5228 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5229 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] 5230 UNSPEC_RSQRT))] 5231 "RS6000_RECIP_HAVE_RSQRTE_P (<MODE>mode)" 5232 "@ 5233 frsqrte<Ftrad> %0,%1 5234 xsrsqrte<Fvsx> %x0,%x1" 5235 [(set_attr "type" "fp")]) 5236 5237;; Floating point comparisons 5238(define_insn "*cmp<mode>_fpr" 5239 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y,y") 5240 (compare:CCFP (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>") 5241 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))] 5242 "TARGET_<MODE>_FPR" 5243 "@ 5244 fcmpu %0,%1,%2 5245 xscmpudp %0,%x1,%x2" 5246 [(set_attr "type" "fpcompare")]) 5247 5248;; Floating point conversions 5249(define_expand "extendsfdf2" 5250 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5251 (float_extend:DF (match_operand:SF 1 "reg_or_none500mem_operand" "")))] 5252 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 5253 "") 5254 5255(define_insn_and_split "*extendsfdf2_fpr" 5256 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d,d,ws,?ws,wv") 5257 (float_extend:DF (match_operand:SF 1 "reg_or_mem_operand" "0,f,m,0,wy,Z")))] 5258 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 5259 "@ 5260 # 5261 fmr %0,%1 5262 lfs%U1%X1 %0,%1 5263 # 5264 xxlor %x0,%x1,%x1 5265 lxsspx %x0,%y1" 5266 "&& reload_completed && REG_P (operands[1]) && REGNO (operands[0]) == REGNO (operands[1])" 5267 [(const_int 0)] 5268{ 5269 emit_note (NOTE_INSN_DELETED); 5270 DONE; 5271} 5272 [(set_attr_alternative "type" 5273 [(const_string "fp") 5274 (const_string "fp") 5275 (if_then_else 5276 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 5277 (const_string "fpload_ux") 5278 (if_then_else 5279 (match_test "update_address_mem (operands[1], VOIDmode)") 5280 (const_string "fpload_u") 5281 (const_string "fpload"))) 5282 (const_string "fp") 5283 (const_string "vecsimple") 5284 (if_then_else 5285 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 5286 (const_string "fpload_ux") 5287 (if_then_else 5288 (match_test "update_address_mem (operands[1], VOIDmode)") 5289 (const_string "fpload_u") 5290 (const_string "fpload")))])]) 5291 5292(define_expand "truncdfsf2" 5293 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5294 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "")))] 5295 "TARGET_HARD_FLOAT && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 5296 "") 5297 5298(define_insn "*truncdfsf2_fpr" 5299 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5300 (float_truncate:SF (match_operand:DF 1 "gpc_reg_operand" "d")))] 5301 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 5302 "frsp %0,%1" 5303 [(set_attr "type" "fp")]) 5304 5305;; This expander is here to avoid FLOAT_WORDS_BIGENDIAN tests in 5306;; builtins.c and optabs.c that are not correct for IBM long double 5307;; when little-endian. 5308(define_expand "signbittf2" 5309 [(set (match_dup 2) 5310 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" ""))) 5311 (set (match_dup 3) 5312 (subreg:DI (match_dup 2) 0)) 5313 (set (match_dup 4) 5314 (match_dup 5)) 5315 (set (match_operand:SI 0 "gpc_reg_operand" "") 5316 (match_dup 6))] 5317 "!TARGET_IEEEQUAD 5318 && TARGET_HARD_FLOAT 5319 && (TARGET_FPRS || TARGET_E500_DOUBLE) 5320 && TARGET_LONG_DOUBLE_128" 5321{ 5322 operands[2] = gen_reg_rtx (DFmode); 5323 operands[3] = gen_reg_rtx (DImode); 5324 if (TARGET_POWERPC64) 5325 { 5326 operands[4] = gen_reg_rtx (DImode); 5327 operands[5] = gen_rtx_LSHIFTRT (DImode, operands[3], GEN_INT (63)); 5328 operands[6] = gen_rtx_SUBREG (SImode, operands[4], 5329 WORDS_BIG_ENDIAN ? 4 : 0); 5330 } 5331 else 5332 { 5333 operands[4] = gen_reg_rtx (SImode); 5334 operands[5] = gen_rtx_SUBREG (SImode, operands[3], 5335 WORDS_BIG_ENDIAN ? 0 : 4); 5336 operands[6] = gen_rtx_LSHIFTRT (SImode, operands[4], GEN_INT (31)); 5337 } 5338}) 5339 5340(define_expand "copysign<mode>3" 5341 [(set (match_dup 3) 5342 (abs:SFDF (match_operand:SFDF 1 "gpc_reg_operand" ""))) 5343 (set (match_dup 4) 5344 (neg:SFDF (abs:SFDF (match_dup 1)))) 5345 (set (match_operand:SFDF 0 "gpc_reg_operand" "") 5346 (if_then_else:SFDF (ge (match_operand:SFDF 2 "gpc_reg_operand" "") 5347 (match_dup 5)) 5348 (match_dup 3) 5349 (match_dup 4)))] 5350 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> 5351 && ((TARGET_PPC_GFXOPT 5352 && !HONOR_NANS (<MODE>mode) 5353 && !HONOR_SIGNED_ZEROS (<MODE>mode)) 5354 || TARGET_CMPB 5355 || VECTOR_UNIT_VSX_P (<MODE>mode))" 5356{ 5357 if (TARGET_CMPB || VECTOR_UNIT_VSX_P (<MODE>mode)) 5358 { 5359 emit_insn (gen_copysign<mode>3_fcpsgn (operands[0], operands[1], 5360 operands[2])); 5361 DONE; 5362 } 5363 5364 operands[3] = gen_reg_rtx (<MODE>mode); 5365 operands[4] = gen_reg_rtx (<MODE>mode); 5366 operands[5] = CONST0_RTX (<MODE>mode); 5367 }) 5368 5369;; Use an unspec rather providing an if-then-else in RTL, to prevent the 5370;; compiler from optimizing -0.0 5371(define_insn "copysign<mode>3_fcpsgn" 5372 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5373 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>") 5374 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")] 5375 UNSPEC_COPYSIGN))] 5376 "TARGET_<MODE>_FPR && TARGET_CMPB" 5377 "@ 5378 fcpsgn %0,%2,%1 5379 xscpsgn<Fvsx> %x0,%x2,%x1" 5380 [(set_attr "type" "fp")]) 5381 5382;; For MIN, MAX, and conditional move, we use DEFINE_EXPAND's that involve a 5383;; fsel instruction and some auxiliary computations. Then we just have a 5384;; single DEFINE_INSN for fsel and the define_splits to make them if made by 5385;; combine. 5386;; For MIN, MAX on non-VSX machines, and conditional move all of the time, we 5387;; use DEFINE_EXPAND's that involve a fsel instruction and some auxiliary 5388;; computations. Then we just have a single DEFINE_INSN for fsel and the 5389;; define_splits to make them if made by combine. On VSX machines we have the 5390;; min/max instructions. 5391;; 5392;; On VSX, we only check for TARGET_VSX instead of checking for a vsx/p8 vector 5393;; to allow either DF/SF to use only traditional registers. 5394 5395(define_expand "smax<mode>3" 5396 [(set (match_operand:SFDF 0 "gpc_reg_operand" "") 5397 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "") 5398 (match_operand:SFDF 2 "gpc_reg_operand" "")) 5399 (match_dup 1) 5400 (match_dup 2)))] 5401 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math" 5402{ 5403 rs6000_emit_minmax (operands[0], SMAX, operands[1], operands[2]); 5404 DONE; 5405}) 5406 5407(define_insn "*smax<mode>3_vsx" 5408 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5409 (smax:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>") 5410 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))] 5411 "TARGET_<MODE>_FPR && TARGET_VSX" 5412 "xsmaxdp %x0,%x1,%x2" 5413 [(set_attr "type" "fp")]) 5414 5415(define_expand "smin<mode>3" 5416 [(set (match_operand:SFDF 0 "gpc_reg_operand" "") 5417 (if_then_else:SFDF (ge (match_operand:SFDF 1 "gpc_reg_operand" "") 5418 (match_operand:SFDF 2 "gpc_reg_operand" "")) 5419 (match_dup 2) 5420 (match_dup 1)))] 5421 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math" 5422{ 5423 rs6000_emit_minmax (operands[0], SMIN, operands[1], operands[2]); 5424 DONE; 5425}) 5426 5427(define_insn "*smin<mode>3_vsx" 5428 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 5429 (smin:SFDF (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>") 5430 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>")))] 5431 "TARGET_<MODE>_FPR && TARGET_VSX" 5432 "xsmindp %x0,%x1,%x2" 5433 [(set_attr "type" "fp")]) 5434 5435(define_split 5436 [(set (match_operand:SFDF 0 "gpc_reg_operand" "") 5437 (match_operator:SFDF 3 "min_max_operator" 5438 [(match_operand:SFDF 1 "gpc_reg_operand" "") 5439 (match_operand:SFDF 2 "gpc_reg_operand" "")]))] 5440 "TARGET_<MODE>_FPR && TARGET_PPC_GFXOPT && !flag_trapping_math 5441 && !TARGET_VSX" 5442 [(const_int 0)] 5443{ 5444 rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), operands[1], 5445 operands[2]); 5446 DONE; 5447}) 5448 5449(define_split 5450 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5451 (match_operator:SF 3 "min_max_operator" 5452 [(match_operand:SF 1 "gpc_reg_operand" "") 5453 (match_operand:SF 2 "gpc_reg_operand" "")]))] 5454 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS 5455 && TARGET_SINGLE_FLOAT && !flag_trapping_math" 5456 [(const_int 0)] 5457 " 5458{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), 5459 operands[1], operands[2]); 5460 DONE; 5461}") 5462 5463(define_expand "mov<mode>cc" 5464 [(set (match_operand:GPR 0 "gpc_reg_operand" "") 5465 (if_then_else:GPR (match_operand 1 "comparison_operator" "") 5466 (match_operand:GPR 2 "gpc_reg_operand" "") 5467 (match_operand:GPR 3 "gpc_reg_operand" "")))] 5468 "TARGET_ISEL<sel>" 5469 " 5470{ 5471 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 5472 DONE; 5473 else 5474 FAIL; 5475}") 5476 5477;; We use the BASE_REGS for the isel input operands because, if rA is 5478;; 0, the value of 0 is placed in rD upon truth. Similarly for rB 5479;; because we may switch the operands and rB may end up being rA. 5480;; 5481;; We need 2 patterns: an unsigned and a signed pattern. We could 5482;; leave out the mode in operand 4 and use one pattern, but reload can 5483;; change the mode underneath our feet and then gets confused trying 5484;; to reload the value. 5485(define_insn "isel_signed_<mode>" 5486 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") 5487 (if_then_else:GPR 5488 (match_operator 1 "scc_comparison_operator" 5489 [(match_operand:CC 4 "cc_reg_operand" "y,y") 5490 (const_int 0)]) 5491 (match_operand:GPR 2 "reg_or_cint_operand" "O,b") 5492 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))] 5493 "TARGET_ISEL<sel>" 5494 "* 5495{ return output_isel (operands); }" 5496 [(set_attr "type" "isel") 5497 (set_attr "length" "4")]) 5498 5499(define_insn "isel_unsigned_<mode>" 5500 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r,r") 5501 (if_then_else:GPR 5502 (match_operator 1 "scc_comparison_operator" 5503 [(match_operand:CCUNS 4 "cc_reg_operand" "y,y") 5504 (const_int 0)]) 5505 (match_operand:GPR 2 "reg_or_cint_operand" "O,b") 5506 (match_operand:GPR 3 "gpc_reg_operand" "r,r")))] 5507 "TARGET_ISEL<sel>" 5508 "* 5509{ return output_isel (operands); }" 5510 [(set_attr "type" "isel") 5511 (set_attr "length" "4")]) 5512 5513;; These patterns can be useful for combine; they let combine know that 5514;; isel can handle reversed comparisons so long as the operands are 5515;; registers. 5516 5517(define_insn "*isel_reversed_signed_<mode>" 5518 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 5519 (if_then_else:GPR 5520 (match_operator 1 "scc_rev_comparison_operator" 5521 [(match_operand:CC 4 "cc_reg_operand" "y") 5522 (const_int 0)]) 5523 (match_operand:GPR 2 "gpc_reg_operand" "b") 5524 (match_operand:GPR 3 "gpc_reg_operand" "b")))] 5525 "TARGET_ISEL<sel>" 5526 "* 5527{ return output_isel (operands); }" 5528 [(set_attr "type" "isel") 5529 (set_attr "length" "4")]) 5530 5531(define_insn "*isel_reversed_unsigned_<mode>" 5532 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 5533 (if_then_else:GPR 5534 (match_operator 1 "scc_rev_comparison_operator" 5535 [(match_operand:CCUNS 4 "cc_reg_operand" "y") 5536 (const_int 0)]) 5537 (match_operand:GPR 2 "gpc_reg_operand" "b") 5538 (match_operand:GPR 3 "gpc_reg_operand" "b")))] 5539 "TARGET_ISEL<sel>" 5540 "* 5541{ return output_isel (operands); }" 5542 [(set_attr "type" "isel") 5543 (set_attr "length" "4")]) 5544 5545(define_expand "movsfcc" 5546 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5547 (if_then_else:SF (match_operand 1 "comparison_operator" "") 5548 (match_operand:SF 2 "gpc_reg_operand" "") 5549 (match_operand:SF 3 "gpc_reg_operand" "")))] 5550 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" 5551 " 5552{ 5553 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 5554 DONE; 5555 else 5556 FAIL; 5557}") 5558 5559(define_insn "*fselsfsf4" 5560 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5561 (if_then_else:SF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 5562 (match_operand:SF 4 "zero_fp_constant" "F")) 5563 (match_operand:SF 2 "gpc_reg_operand" "f") 5564 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5565 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" 5566 "fsel %0,%1,%2,%3" 5567 [(set_attr "type" "fp")]) 5568 5569(define_insn "*fseldfsf4" 5570 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 5571 (if_then_else:SF (ge (match_operand:DF 1 "gpc_reg_operand" "d") 5572 (match_operand:DF 4 "zero_fp_constant" "F")) 5573 (match_operand:SF 2 "gpc_reg_operand" "f") 5574 (match_operand:SF 3 "gpc_reg_operand" "f")))] 5575 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT" 5576 "fsel %0,%1,%2,%3" 5577 [(set_attr "type" "fp")]) 5578 5579;; The conditional move instructions allow us to perform max and min 5580;; operations even when 5581 5582(define_split 5583 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5584 (match_operator:DF 3 "min_max_operator" 5585 [(match_operand:DF 1 "gpc_reg_operand" "") 5586 (match_operand:DF 2 "gpc_reg_operand" "")]))] 5587 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 5588 && !flag_trapping_math" 5589 [(const_int 0)] 5590 " 5591{ rs6000_emit_minmax (operands[0], GET_CODE (operands[3]), 5592 operands[1], operands[2]); 5593 DONE; 5594}") 5595 5596(define_expand "movdfcc" 5597 [(set (match_operand:DF 0 "gpc_reg_operand" "") 5598 (if_then_else:DF (match_operand 1 "comparison_operator" "") 5599 (match_operand:DF 2 "gpc_reg_operand" "") 5600 (match_operand:DF 3 "gpc_reg_operand" "")))] 5601 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 5602 " 5603{ 5604 if (rs6000_emit_cmove (operands[0], operands[1], operands[2], operands[3])) 5605 DONE; 5606 else 5607 FAIL; 5608}") 5609 5610(define_insn "*fseldfdf4" 5611 [(set (match_operand:DF 0 "gpc_reg_operand" "=d") 5612 (if_then_else:DF (ge (match_operand:DF 1 "gpc_reg_operand" "d") 5613 (match_operand:DF 4 "zero_fp_constant" "F")) 5614 (match_operand:DF 2 "gpc_reg_operand" "d") 5615 (match_operand:DF 3 "gpc_reg_operand" "d")))] 5616 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 5617 "fsel %0,%1,%2,%3" 5618 [(set_attr "type" "fp")]) 5619 5620(define_insn "*fselsfdf4" 5621 [(set (match_operand:DF 0 "gpc_reg_operand" "=d") 5622 (if_then_else:DF (ge (match_operand:SF 1 "gpc_reg_operand" "f") 5623 (match_operand:SF 4 "zero_fp_constant" "F")) 5624 (match_operand:DF 2 "gpc_reg_operand" "d") 5625 (match_operand:DF 3 "gpc_reg_operand" "d")))] 5626 "TARGET_PPC_GFXOPT && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_SINGLE_FLOAT" 5627 "fsel %0,%1,%2,%3" 5628 [(set_attr "type" "fp")]) 5629 5630;; Conversions to and from floating-point. 5631 5632; We don't define lfiwax/lfiwzx with the normal definition, because we 5633; don't want to support putting SImode in FPR registers. 5634(define_insn "lfiwax" 5635 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj") 5636 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] 5637 UNSPEC_LFIWAX))] 5638 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX" 5639 "@ 5640 lfiwax %0,%y1 5641 lxsiwax %x0,%y1 5642 mtvsrwa %x0,%1" 5643 [(set_attr "type" "fpload,fpload,mffgpr")]) 5644 5645; This split must be run before register allocation because it allocates the 5646; memory slot that is needed to move values to/from the FPR. We don't allocate 5647; it earlier to allow for the combiner to merge insns together where it might 5648; not be needed and also in case the insns are deleted as dead code. 5649 5650(define_insn_and_split "floatsi<mode>2_lfiwax" 5651 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d") 5652 (float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) 5653 (clobber (match_scratch:DI 2 "=d"))] 5654 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX 5655 && <SI_CONVERT_FP> && can_create_pseudo_p ()" 5656 "#" 5657 "" 5658 [(pc)] 5659 " 5660{ 5661 rtx dest = operands[0]; 5662 rtx src = operands[1]; 5663 rtx tmp; 5664 5665 if (!MEM_P (src) && TARGET_POWERPC64 5666 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE)) 5667 tmp = convert_to_mode (DImode, src, false); 5668 else 5669 { 5670 tmp = operands[2]; 5671 if (GET_CODE (tmp) == SCRATCH) 5672 tmp = gen_reg_rtx (DImode); 5673 if (MEM_P (src)) 5674 { 5675 src = rs6000_address_for_fpconvert (src); 5676 emit_insn (gen_lfiwax (tmp, src)); 5677 } 5678 else 5679 { 5680 rtx stack = rs6000_allocate_stack_temp (SImode, false, true); 5681 emit_move_insn (stack, src); 5682 emit_insn (gen_lfiwax (tmp, stack)); 5683 } 5684 } 5685 emit_insn (gen_floatdi<mode>2 (dest, tmp)); 5686 DONE; 5687}" 5688 [(set_attr "length" "12") 5689 (set_attr "type" "fpload")]) 5690 5691(define_insn_and_split "floatsi<mode>2_lfiwax_mem" 5692 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>") 5693 (float:SFDF 5694 (sign_extend:DI 5695 (match_operand:SI 1 "memory_operand" "Z,Z")))) 5696 (clobber (match_scratch:DI 2 "=0,d"))] 5697 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWAX 5698 && <SI_CONVERT_FP>" 5699 "#" 5700 "" 5701 [(pc)] 5702 " 5703{ 5704 operands[1] = rs6000_address_for_fpconvert (operands[1]); 5705 if (GET_CODE (operands[2]) == SCRATCH) 5706 operands[2] = gen_reg_rtx (DImode); 5707 emit_insn (gen_lfiwax (operands[2], operands[1])); 5708 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2])); 5709 DONE; 5710}" 5711 [(set_attr "length" "8") 5712 (set_attr "type" "fpload")]) 5713 5714(define_insn "lfiwzx" 5715 [(set (match_operand:DI 0 "gpc_reg_operand" "=d,wj,!wj") 5716 (unspec:DI [(match_operand:SI 1 "reg_or_indexed_operand" "Z,Z,r")] 5717 UNSPEC_LFIWZX))] 5718 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX" 5719 "@ 5720 lfiwzx %0,%y1 5721 lxsiwzx %x0,%y1 5722 mtvsrwz %x0,%1" 5723 [(set_attr "type" "fpload,fpload,mftgpr")]) 5724 5725(define_insn_and_split "floatunssi<mode>2_lfiwzx" 5726 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d") 5727 (unsigned_float:SFDF (match_operand:SI 1 "nonimmediate_operand" "r"))) 5728 (clobber (match_scratch:DI 2 "=d"))] 5729 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX 5730 && <SI_CONVERT_FP>" 5731 "#" 5732 "" 5733 [(pc)] 5734 " 5735{ 5736 rtx dest = operands[0]; 5737 rtx src = operands[1]; 5738 rtx tmp; 5739 5740 if (!MEM_P (src) && TARGET_POWERPC64 5741 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE)) 5742 tmp = convert_to_mode (DImode, src, true); 5743 else 5744 { 5745 tmp = operands[2]; 5746 if (GET_CODE (tmp) == SCRATCH) 5747 tmp = gen_reg_rtx (DImode); 5748 if (MEM_P (src)) 5749 { 5750 src = rs6000_address_for_fpconvert (src); 5751 emit_insn (gen_lfiwzx (tmp, src)); 5752 } 5753 else 5754 { 5755 rtx stack = rs6000_allocate_stack_temp (SImode, false, true); 5756 emit_move_insn (stack, src); 5757 emit_insn (gen_lfiwzx (tmp, stack)); 5758 } 5759 } 5760 emit_insn (gen_floatdi<mode>2 (dest, tmp)); 5761 DONE; 5762}" 5763 [(set_attr "length" "12") 5764 (set_attr "type" "fpload")]) 5765 5766(define_insn_and_split "floatunssi<mode>2_lfiwzx_mem" 5767 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d,<rreg2>") 5768 (unsigned_float:SFDF 5769 (zero_extend:DI 5770 (match_operand:SI 1 "memory_operand" "Z,Z")))) 5771 (clobber (match_scratch:DI 2 "=0,d"))] 5772 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LFIWZX 5773 && <SI_CONVERT_FP>" 5774 "#" 5775 "" 5776 [(pc)] 5777 " 5778{ 5779 operands[1] = rs6000_address_for_fpconvert (operands[1]); 5780 if (GET_CODE (operands[2]) == SCRATCH) 5781 operands[2] = gen_reg_rtx (DImode); 5782 emit_insn (gen_lfiwzx (operands[2], operands[1])); 5783 emit_insn (gen_floatdi<mode>2 (operands[0], operands[2])); 5784 DONE; 5785}" 5786 [(set_attr "length" "8") 5787 (set_attr "type" "fpload")]) 5788 5789; For each of these conversions, there is a define_expand, a define_insn 5790; with a '#' template, and a define_split (with C code). The idea is 5791; to allow constant folding with the template of the define_insn, 5792; then to have the insns split later (between sched1 and final). 5793 5794(define_expand "floatsidf2" 5795 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") 5796 (float:DF (match_operand:SI 1 "nonimmediate_operand" ""))) 5797 (use (match_dup 2)) 5798 (use (match_dup 3)) 5799 (clobber (match_dup 4)) 5800 (clobber (match_dup 5)) 5801 (clobber (match_dup 6))])] 5802 "TARGET_HARD_FLOAT 5803 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 5804 " 5805{ 5806 if (TARGET_E500_DOUBLE) 5807 { 5808 if (!REG_P (operands[1])) 5809 operands[1] = force_reg (SImode, operands[1]); 5810 emit_insn (gen_spe_floatsidf2 (operands[0], operands[1])); 5811 DONE; 5812 } 5813 else if (TARGET_LFIWAX && TARGET_FCFID) 5814 { 5815 emit_insn (gen_floatsidf2_lfiwax (operands[0], operands[1])); 5816 DONE; 5817 } 5818 else if (TARGET_FCFID) 5819 { 5820 rtx dreg = operands[1]; 5821 if (!REG_P (dreg)) 5822 dreg = force_reg (SImode, dreg); 5823 dreg = convert_to_mode (DImode, dreg, false); 5824 emit_insn (gen_floatdidf2 (operands[0], dreg)); 5825 DONE; 5826 } 5827 5828 if (!REG_P (operands[1])) 5829 operands[1] = force_reg (SImode, operands[1]); 5830 operands[2] = force_reg (SImode, GEN_INT (0x43300000)); 5831 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503601774854144\", DFmode)); 5832 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false); 5833 operands[5] = gen_reg_rtx (DFmode); 5834 operands[6] = gen_reg_rtx (SImode); 5835}") 5836 5837(define_insn_and_split "*floatsidf2_internal" 5838 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d") 5839 (float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5840 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 5841 (use (match_operand:DF 3 "gpc_reg_operand" "d")) 5842 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) 5843 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d")) 5844 (clobber (match_operand:SI 6 "gpc_reg_operand" "=&r"))] 5845 "! TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 5846 "#" 5847 "" 5848 [(pc)] 5849 " 5850{ 5851 rtx lowword, highword; 5852 gcc_assert (MEM_P (operands[4])); 5853 highword = adjust_address (operands[4], SImode, 0); 5854 lowword = adjust_address (operands[4], SImode, 4); 5855 if (! WORDS_BIG_ENDIAN) 5856 { 5857 rtx tmp; 5858 tmp = highword; highword = lowword; lowword = tmp; 5859 } 5860 5861 emit_insn (gen_xorsi3 (operands[6], operands[1], 5862 GEN_INT (~ (HOST_WIDE_INT) 0x7fffffff))); 5863 emit_move_insn (lowword, operands[6]); 5864 emit_move_insn (highword, operands[2]); 5865 emit_move_insn (operands[5], operands[4]); 5866 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); 5867 DONE; 5868}" 5869 [(set_attr "length" "24") 5870 (set_attr "type" "fp")]) 5871 5872;; If we don't have a direct conversion to single precision, don't enable this 5873;; conversion for 32-bit without fast math, because we don't have the insn to 5874;; generate the fixup swizzle to avoid double rounding problems. 5875(define_expand "floatunssisf2" 5876 [(set (match_operand:SF 0 "gpc_reg_operand" "") 5877 (unsigned_float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] 5878 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT 5879 && (!TARGET_FPRS 5880 || (TARGET_FPRS 5881 && ((TARGET_FCFIDUS && TARGET_LFIWZX) 5882 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID 5883 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))" 5884 " 5885{ 5886 if (!TARGET_FPRS) 5887 { 5888 if (!REG_P (operands[1])) 5889 operands[1] = force_reg (SImode, operands[1]); 5890 } 5891 else if (TARGET_LFIWZX && TARGET_FCFIDUS) 5892 { 5893 emit_insn (gen_floatunssisf2_lfiwzx (operands[0], operands[1])); 5894 DONE; 5895 } 5896 else 5897 { 5898 rtx dreg = operands[1]; 5899 if (!REG_P (dreg)) 5900 dreg = force_reg (SImode, dreg); 5901 dreg = convert_to_mode (DImode, dreg, true); 5902 emit_insn (gen_floatdisf2 (operands[0], dreg)); 5903 DONE; 5904 } 5905}") 5906 5907(define_expand "floatunssidf2" 5908 [(parallel [(set (match_operand:DF 0 "gpc_reg_operand" "") 5909 (unsigned_float:DF (match_operand:SI 1 "nonimmediate_operand" ""))) 5910 (use (match_dup 2)) 5911 (use (match_dup 3)) 5912 (clobber (match_dup 4)) 5913 (clobber (match_dup 5))])] 5914 "TARGET_HARD_FLOAT 5915 && ((TARGET_FPRS && TARGET_DOUBLE_FLOAT) || TARGET_E500_DOUBLE)" 5916 " 5917{ 5918 if (TARGET_E500_DOUBLE) 5919 { 5920 if (!REG_P (operands[1])) 5921 operands[1] = force_reg (SImode, operands[1]); 5922 emit_insn (gen_spe_floatunssidf2 (operands[0], operands[1])); 5923 DONE; 5924 } 5925 else if (TARGET_LFIWZX && TARGET_FCFID) 5926 { 5927 emit_insn (gen_floatunssidf2_lfiwzx (operands[0], operands[1])); 5928 DONE; 5929 } 5930 else if (TARGET_FCFID) 5931 { 5932 rtx dreg = operands[1]; 5933 if (!REG_P (dreg)) 5934 dreg = force_reg (SImode, dreg); 5935 dreg = convert_to_mode (DImode, dreg, true); 5936 emit_insn (gen_floatdidf2 (operands[0], dreg)); 5937 DONE; 5938 } 5939 5940 if (!REG_P (operands[1])) 5941 operands[1] = force_reg (SImode, operands[1]); 5942 operands[2] = force_reg (SImode, GEN_INT (0x43300000)); 5943 operands[3] = force_reg (DFmode, CONST_DOUBLE_ATOF (\"4503599627370496\", DFmode)); 5944 operands[4] = rs6000_allocate_stack_temp (DFmode, true, false); 5945 operands[5] = gen_reg_rtx (DFmode); 5946}") 5947 5948(define_insn_and_split "*floatunssidf2_internal" 5949 [(set (match_operand:DF 0 "gpc_reg_operand" "=&d") 5950 (unsigned_float:DF (match_operand:SI 1 "gpc_reg_operand" "r"))) 5951 (use (match_operand:SI 2 "gpc_reg_operand" "r")) 5952 (use (match_operand:DF 3 "gpc_reg_operand" "d")) 5953 (clobber (match_operand:DF 4 "offsettable_mem_operand" "=o")) 5954 (clobber (match_operand:DF 5 "gpc_reg_operand" "=&d"))] 5955 "! TARGET_FCFIDU && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 5956 && !(TARGET_FCFID && TARGET_POWERPC64)" 5957 "#" 5958 "" 5959 [(pc)] 5960 " 5961{ 5962 rtx lowword, highword; 5963 gcc_assert (MEM_P (operands[4])); 5964 highword = adjust_address (operands[4], SImode, 0); 5965 lowword = adjust_address (operands[4], SImode, 4); 5966 if (! WORDS_BIG_ENDIAN) 5967 { 5968 rtx tmp; 5969 tmp = highword; highword = lowword; lowword = tmp; 5970 } 5971 5972 emit_move_insn (lowword, operands[1]); 5973 emit_move_insn (highword, operands[2]); 5974 emit_move_insn (operands[5], operands[4]); 5975 emit_insn (gen_subdf3 (operands[0], operands[5], operands[3])); 5976 DONE; 5977}" 5978 [(set_attr "length" "20") 5979 (set_attr "type" "fp")]) 5980 5981(define_expand "fix_trunc<mode>si2" 5982 [(set (match_operand:SI 0 "gpc_reg_operand" "") 5983 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))] 5984 "TARGET_HARD_FLOAT && ((TARGET_FPRS && <TARGET_FLOAT>) || <E500_CONVERT>)" 5985 " 5986{ 5987 if (!<E500_CONVERT>) 5988 { 5989 rtx tmp, stack; 5990 5991 if (TARGET_STFIWX) 5992 emit_insn (gen_fix_trunc<mode>si2_stfiwx (operands[0], operands[1])); 5993 else 5994 { 5995 tmp = gen_reg_rtx (DImode); 5996 stack = rs6000_allocate_stack_temp (DImode, true, false); 5997 emit_insn (gen_fix_trunc<mode>si2_internal (operands[0], operands[1], 5998 tmp, stack)); 5999 } 6000 DONE; 6001 } 6002}") 6003 6004; Like the convert to float patterns, this insn must be split before 6005; register allocation so that it can allocate the memory slot if it 6006; needed 6007(define_insn_and_split "fix_trunc<mode>si2_stfiwx" 6008 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 6009 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))) 6010 (clobber (match_scratch:DI 2 "=d"))] 6011 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 6012 && (<MODE>mode != SFmode || TARGET_SINGLE_FLOAT) 6013 && TARGET_STFIWX && can_create_pseudo_p ()" 6014 "#" 6015 "" 6016 [(pc)] 6017{ 6018 rtx dest = operands[0]; 6019 rtx src = operands[1]; 6020 rtx tmp = operands[2]; 6021 6022 if (GET_CODE (tmp) == SCRATCH) 6023 tmp = gen_reg_rtx (DImode); 6024 6025 emit_insn (gen_fctiwz_<mode> (tmp, src)); 6026 if (MEM_P (dest)) 6027 { 6028 dest = rs6000_address_for_fpconvert (dest); 6029 emit_insn (gen_stfiwx (dest, tmp)); 6030 DONE; 6031 } 6032 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE)) 6033 { 6034 dest = gen_lowpart (DImode, dest); 6035 emit_move_insn (dest, tmp); 6036 DONE; 6037 } 6038 else 6039 { 6040 rtx stack = rs6000_allocate_stack_temp (SImode, false, true); 6041 emit_insn (gen_stfiwx (stack, tmp)); 6042 emit_move_insn (dest, stack); 6043 DONE; 6044 } 6045} 6046 [(set_attr "length" "12") 6047 (set_attr "type" "fp")]) 6048 6049(define_insn_and_split "fix_trunc<mode>si2_internal" 6050 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,?r") 6051 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d,<rreg>"))) 6052 (clobber (match_operand:DI 2 "gpc_reg_operand" "=1,d")) 6053 (clobber (match_operand:DI 3 "offsettable_mem_operand" "=o,o"))] 6054 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6055 "#" 6056 "" 6057 [(pc)] 6058 " 6059{ 6060 rtx lowword; 6061 gcc_assert (MEM_P (operands[3])); 6062 lowword = adjust_address (operands[3], SImode, WORDS_BIG_ENDIAN ? 4 : 0); 6063 6064 emit_insn (gen_fctiwz_<mode> (operands[2], operands[1])); 6065 emit_move_insn (operands[3], operands[2]); 6066 emit_move_insn (operands[0], lowword); 6067 DONE; 6068}" 6069 [(set_attr "length" "16") 6070 (set_attr "type" "fp")]) 6071 6072(define_expand "fix_trunc<mode>di2" 6073 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6074 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "")))] 6075 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS 6076 && TARGET_FCFID" 6077 "") 6078 6079(define_insn "*fix_trunc<mode>di2_fctidz" 6080 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") 6081 (fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))] 6082 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS 6083 && TARGET_FCFID && !VECTOR_UNIT_VSX_P (<MODE>mode)" 6084 "fctidz %0,%1" 6085 [(set_attr "type" "fp")]) 6086 6087(define_expand "fixuns_trunc<mode>si2" 6088 [(set (match_operand:SI 0 "gpc_reg_operand" "") 6089 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "")))] 6090 "TARGET_HARD_FLOAT 6091 && ((TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ && TARGET_STFIWX) 6092 || <E500_CONVERT>)" 6093 " 6094{ 6095 if (!<E500_CONVERT>) 6096 { 6097 emit_insn (gen_fixuns_trunc<mode>si2_stfiwx (operands[0], operands[1])); 6098 DONE; 6099 } 6100}") 6101 6102(define_insn_and_split "fixuns_trunc<mode>si2_stfiwx" 6103 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 6104 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))) 6105 (clobber (match_scratch:DI 2 "=d"))] 6106 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ 6107 && TARGET_STFIWX && can_create_pseudo_p ()" 6108 "#" 6109 "" 6110 [(pc)] 6111{ 6112 rtx dest = operands[0]; 6113 rtx src = operands[1]; 6114 rtx tmp = operands[2]; 6115 6116 if (GET_CODE (tmp) == SCRATCH) 6117 tmp = gen_reg_rtx (DImode); 6118 6119 emit_insn (gen_fctiwuz_<mode> (tmp, src)); 6120 if (MEM_P (dest)) 6121 { 6122 dest = rs6000_address_for_fpconvert (dest); 6123 emit_insn (gen_stfiwx (dest, tmp)); 6124 DONE; 6125 } 6126 else if (TARGET_POWERPC64 && (TARGET_MFPGPR || TARGET_DIRECT_MOVE)) 6127 { 6128 dest = gen_lowpart (DImode, dest); 6129 emit_move_insn (dest, tmp); 6130 DONE; 6131 } 6132 else 6133 { 6134 rtx stack = rs6000_allocate_stack_temp (SImode, false, true); 6135 emit_insn (gen_stfiwx (stack, tmp)); 6136 emit_move_insn (dest, stack); 6137 DONE; 6138 } 6139} 6140 [(set_attr "length" "12") 6141 (set_attr "type" "fp")]) 6142 6143(define_expand "fixuns_trunc<mode>di2" 6144 [(set (match_operand:DI 0 "register_operand" "") 6145 (unsigned_fix:DI (match_operand:SFDF 1 "register_operand" "")))] 6146 "TARGET_HARD_FLOAT && (TARGET_FCTIDUZ || VECTOR_UNIT_VSX_P (<MODE>mode))" 6147 "") 6148 6149(define_insn "*fixuns_trunc<mode>di2_fctiduz" 6150 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") 6151 (unsigned_fix:DI (match_operand:SFDF 1 "gpc_reg_operand" "d")))] 6152 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS 6153 && TARGET_FCTIDUZ && !VECTOR_UNIT_VSX_P (<MODE>mode)" 6154 "fctiduz %0,%1" 6155 [(set_attr "type" "fp")]) 6156 6157; Here, we use (set (reg) (unspec:DI [(fix:SI ...)] UNSPEC_FCTIWZ)) 6158; rather than (set (subreg:SI (reg)) (fix:SI ...)) 6159; because the first makes it clear that operand 0 is not live 6160; before the instruction. 6161(define_insn "fctiwz_<mode>" 6162 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") 6163 (unspec:DI [(fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d"))] 6164 UNSPEC_FCTIWZ))] 6165 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 6166 "fctiwz %0,%1" 6167 [(set_attr "type" "fp")]) 6168 6169(define_insn "fctiwuz_<mode>" 6170 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") 6171 (unspec:DI [(unsigned_fix:SI 6172 (match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>"))] 6173 UNSPEC_FCTIWUZ))] 6174 "TARGET_HARD_FLOAT && TARGET_FPRS && <TARGET_FLOAT> && TARGET_FCTIWUZ" 6175 "fctiwuz %0,%1" 6176 [(set_attr "type" "fp")]) 6177 6178;; Only optimize (float (fix x)) -> frz if we are in fast-math mode, since 6179;; since the friz instruction does not truncate the value if the floating 6180;; point value is < LONG_MIN or > LONG_MAX. 6181(define_insn "*friz" 6182 [(set (match_operand:DF 0 "gpc_reg_operand" "=d") 6183 (float:DF (fix:DI (match_operand:DF 1 "gpc_reg_operand" "d"))))] 6184 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_FPRND 6185 && !VECTOR_UNIT_VSX_P (DFmode) && flag_unsafe_math_optimizations 6186 && !flag_trapping_math && TARGET_FRIZ" 6187 "friz %0,%1" 6188 [(set_attr "type" "fp")]) 6189 6190;; Since FCTIWZ doesn't sign extend the upper bits, we have to do a store and a 6191;; load to properly sign extend the value, but at least doing a store, load 6192;; into a GPR to sign extend, a store from the GPR and a load back into the FPR 6193;; if we have 32-bit memory ops 6194(define_insn_and_split "*round32<mode>2_fprs" 6195 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d") 6196 (float:SFDF 6197 (fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))) 6198 (clobber (match_scratch:DI 2 "=d")) 6199 (clobber (match_scratch:DI 3 "=d"))] 6200 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 6201 && <SI_CONVERT_FP> && TARGET_LFIWAX && TARGET_STFIWX && TARGET_FCFID 6202 && can_create_pseudo_p ()" 6203 "#" 6204 "" 6205 [(pc)] 6206{ 6207 rtx dest = operands[0]; 6208 rtx src = operands[1]; 6209 rtx tmp1 = operands[2]; 6210 rtx tmp2 = operands[3]; 6211 rtx stack = rs6000_allocate_stack_temp (SImode, false, true); 6212 6213 if (GET_CODE (tmp1) == SCRATCH) 6214 tmp1 = gen_reg_rtx (DImode); 6215 if (GET_CODE (tmp2) == SCRATCH) 6216 tmp2 = gen_reg_rtx (DImode); 6217 6218 emit_insn (gen_fctiwz_<mode> (tmp1, src)); 6219 emit_insn (gen_stfiwx (stack, tmp1)); 6220 emit_insn (gen_lfiwax (tmp2, stack)); 6221 emit_insn (gen_floatdi<mode>2 (dest, tmp2)); 6222 DONE; 6223} 6224 [(set_attr "type" "fpload") 6225 (set_attr "length" "16")]) 6226 6227(define_insn_and_split "*roundu32<mode>2_fprs" 6228 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=d") 6229 (unsigned_float:SFDF 6230 (unsigned_fix:SI (match_operand:SFDF 1 "gpc_reg_operand" "d")))) 6231 (clobber (match_scratch:DI 2 "=d")) 6232 (clobber (match_scratch:DI 3 "=d"))] 6233 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 6234 && TARGET_LFIWZX && TARGET_STFIWX && TARGET_FCFIDU 6235 && can_create_pseudo_p ()" 6236 "#" 6237 "" 6238 [(pc)] 6239{ 6240 rtx dest = operands[0]; 6241 rtx src = operands[1]; 6242 rtx tmp1 = operands[2]; 6243 rtx tmp2 = operands[3]; 6244 rtx stack = rs6000_allocate_stack_temp (SImode, false, true); 6245 6246 if (GET_CODE (tmp1) == SCRATCH) 6247 tmp1 = gen_reg_rtx (DImode); 6248 if (GET_CODE (tmp2) == SCRATCH) 6249 tmp2 = gen_reg_rtx (DImode); 6250 6251 emit_insn (gen_fctiwuz_<mode> (tmp1, src)); 6252 emit_insn (gen_stfiwx (stack, tmp1)); 6253 emit_insn (gen_lfiwzx (tmp2, stack)); 6254 emit_insn (gen_floatdi<mode>2 (dest, tmp2)); 6255 DONE; 6256} 6257 [(set_attr "type" "fpload") 6258 (set_attr "length" "16")]) 6259 6260;; No VSX equivalent to fctid 6261(define_insn "lrint<mode>di2" 6262 [(set (match_operand:DI 0 "gpc_reg_operand" "=d") 6263 (unspec:DI [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")] 6264 UNSPEC_FCTID))] 6265 "TARGET_<MODE>_FPR && TARGET_FPRND" 6266 "fctid %0,%1" 6267 [(set_attr "type" "fp")]) 6268 6269(define_insn "btrunc<mode>2" 6270 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 6271 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] 6272 UNSPEC_FRIZ))] 6273 "TARGET_<MODE>_FPR && TARGET_FPRND" 6274 "@ 6275 friz %0,%1 6276 xsrdpiz %x0,%x1" 6277 [(set_attr "type" "fp") 6278 (set_attr "fp_type" "fp_addsub_<Fs>")]) 6279 6280(define_insn "ceil<mode>2" 6281 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 6282 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] 6283 UNSPEC_FRIP))] 6284 "TARGET_<MODE>_FPR && TARGET_FPRND" 6285 "@ 6286 frip %0,%1 6287 xsrdpip %x0,%x1" 6288 [(set_attr "type" "fp") 6289 (set_attr "fp_type" "fp_addsub_<Fs>")]) 6290 6291(define_insn "floor<mode>2" 6292 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>") 6293 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>")] 6294 UNSPEC_FRIM))] 6295 "TARGET_<MODE>_FPR && TARGET_FPRND" 6296 "@ 6297 frim %0,%1 6298 xsrdpim %x0,%x1" 6299 [(set_attr "type" "fp") 6300 (set_attr "fp_type" "fp_addsub_<Fs>")]) 6301 6302;; No VSX equivalent to frin 6303(define_insn "round<mode>2" 6304 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<rreg2>") 6305 (unspec:SFDF [(match_operand:SFDF 1 "gpc_reg_operand" "<rreg2>")] 6306 UNSPEC_FRIN))] 6307 "TARGET_<MODE>_FPR && TARGET_FPRND" 6308 "frin %0,%1" 6309 [(set_attr "type" "fp") 6310 (set_attr "fp_type" "fp_addsub_<Fs>")]) 6311 6312; An UNSPEC is used so we don't have to support SImode in FP registers. 6313(define_insn "stfiwx" 6314 [(set (match_operand:SI 0 "memory_operand" "=Z") 6315 (unspec:SI [(match_operand:DI 1 "gpc_reg_operand" "d")] 6316 UNSPEC_STFIWX))] 6317 "TARGET_PPC_GFXOPT" 6318 "stfiwx %1,%y0" 6319 [(set_attr "type" "fpstore")]) 6320 6321;; If we don't have a direct conversion to single precision, don't enable this 6322;; conversion for 32-bit without fast math, because we don't have the insn to 6323;; generate the fixup swizzle to avoid double rounding problems. 6324(define_expand "floatsisf2" 6325 [(set (match_operand:SF 0 "gpc_reg_operand" "") 6326 (float:SF (match_operand:SI 1 "nonimmediate_operand" "")))] 6327 "TARGET_HARD_FLOAT && TARGET_SINGLE_FLOAT 6328 && (!TARGET_FPRS 6329 || (TARGET_FPRS 6330 && ((TARGET_FCFIDS && TARGET_LFIWAX) 6331 || (TARGET_DOUBLE_FLOAT && TARGET_FCFID 6332 && (TARGET_POWERPC64 || flag_unsafe_math_optimizations)))))" 6333 " 6334{ 6335 if (!TARGET_FPRS) 6336 { 6337 if (!REG_P (operands[1])) 6338 operands[1] = force_reg (SImode, operands[1]); 6339 } 6340 else if (TARGET_FCFIDS && TARGET_LFIWAX) 6341 { 6342 emit_insn (gen_floatsisf2_lfiwax (operands[0], operands[1])); 6343 DONE; 6344 } 6345 else if (TARGET_FCFID && TARGET_LFIWAX) 6346 { 6347 rtx dfreg = gen_reg_rtx (DFmode); 6348 emit_insn (gen_floatsidf2_lfiwax (dfreg, operands[1])); 6349 emit_insn (gen_truncdfsf2 (operands[0], dfreg)); 6350 DONE; 6351 } 6352 else 6353 { 6354 rtx dreg = operands[1]; 6355 if (!REG_P (dreg)) 6356 dreg = force_reg (SImode, dreg); 6357 dreg = convert_to_mode (DImode, dreg, false); 6358 emit_insn (gen_floatdisf2 (operands[0], dreg)); 6359 DONE; 6360 } 6361}") 6362 6363(define_expand "floatdidf2" 6364 [(set (match_operand:DF 0 "gpc_reg_operand" "") 6365 (float:DF (match_operand:DI 1 "gpc_reg_operand" "")))] 6366 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS" 6367 "") 6368 6369(define_insn "*floatdidf2_fpr" 6370 [(set (match_operand:DF 0 "gpc_reg_operand" "=d") 6371 (float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))] 6372 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS 6373 && !VECTOR_UNIT_VSX_P (DFmode)" 6374 "fcfid %0,%1" 6375 [(set_attr "type" "fp")]) 6376 6377; Allow the combiner to merge source memory operands to the conversion so that 6378; the optimizer/register allocator doesn't try to load the value too early in a 6379; GPR and then use store/load to move it to a FPR and suffer from a store-load 6380; hit. We will split after reload to avoid the trip through the GPRs 6381 6382(define_insn_and_split "*floatdidf2_mem" 6383 [(set (match_operand:DF 0 "gpc_reg_operand" "=d") 6384 (float:DF (match_operand:DI 1 "memory_operand" "m"))) 6385 (clobber (match_scratch:DI 2 "=d"))] 6386 "TARGET_HARD_FLOAT && TARGET_DOUBLE_FLOAT && TARGET_FPRS && TARGET_FCFID" 6387 "#" 6388 "&& reload_completed" 6389 [(set (match_dup 2) (match_dup 1)) 6390 (set (match_dup 0) (float:DF (match_dup 2)))] 6391 "" 6392 [(set_attr "length" "8") 6393 (set_attr "type" "fpload")]) 6394 6395(define_expand "floatunsdidf2" 6396 [(set (match_operand:DF 0 "gpc_reg_operand" "") 6397 (unsigned_float:DF 6398 (match_operand:DI 1 "gpc_reg_operand" "")))] 6399 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))" 6400 "") 6401 6402(define_insn "*floatunsdidf2_fcfidu" 6403 [(set (match_operand:DF 0 "gpc_reg_operand" "=d") 6404 (unsigned_float:DF (match_operand:DI 1 "gpc_reg_operand" "d")))] 6405 "TARGET_HARD_FLOAT && TARGET_FCFIDU && !VECTOR_UNIT_VSX_P (DFmode)" 6406 "fcfidu %0,%1" 6407 [(set_attr "type" "fp") 6408 (set_attr "length" "4")]) 6409 6410(define_insn_and_split "*floatunsdidf2_mem" 6411 [(set (match_operand:DF 0 "gpc_reg_operand" "=d") 6412 (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m"))) 6413 (clobber (match_scratch:DI 2 "=d"))] 6414 "TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))" 6415 "#" 6416 "&& reload_completed" 6417 [(set (match_dup 2) (match_dup 1)) 6418 (set (match_dup 0) (unsigned_float:DF (match_dup 2)))] 6419 "" 6420 [(set_attr "length" "8") 6421 (set_attr "type" "fpload")]) 6422 6423(define_expand "floatdisf2" 6424 [(set (match_operand:SF 0 "gpc_reg_operand" "") 6425 (float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] 6426 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT 6427 && (TARGET_FCFIDS || TARGET_POWERPC64 || flag_unsafe_math_optimizations)" 6428 " 6429{ 6430 if (!TARGET_FCFIDS) 6431 { 6432 rtx val = operands[1]; 6433 if (!flag_unsafe_math_optimizations) 6434 { 6435 rtx label = gen_label_rtx (); 6436 val = gen_reg_rtx (DImode); 6437 emit_insn (gen_floatdisf2_internal2 (val, operands[1], label)); 6438 emit_label (label); 6439 } 6440 emit_insn (gen_floatdisf2_internal1 (operands[0], val)); 6441 DONE; 6442 } 6443}") 6444 6445(define_insn "floatdisf2_fcfids" 6446 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6447 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))] 6448 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT 6449 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS" 6450 "fcfids %0,%1" 6451 [(set_attr "type" "fp")]) 6452 6453(define_insn_and_split "*floatdisf2_mem" 6454 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6455 (float:SF (match_operand:DI 1 "memory_operand" "m"))) 6456 (clobber (match_scratch:DI 2 "=f"))] 6457 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT 6458 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDS" 6459 "#" 6460 "&& reload_completed" 6461 [(pc)] 6462 " 6463{ 6464 emit_move_insn (operands[2], operands[1]); 6465 emit_insn (gen_floatdisf2_fcfids (operands[0], operands[2])); 6466 DONE; 6467}" 6468 [(set_attr "length" "8")]) 6469 6470;; This is not IEEE compliant if rounding mode is "round to nearest". 6471;; If the DI->DF conversion is inexact, then it's possible to suffer 6472;; from double rounding. 6473;; Instead of creating a new cpu type for two FP operations, just use fp 6474(define_insn_and_split "floatdisf2_internal1" 6475 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6476 (float:SF (match_operand:DI 1 "gpc_reg_operand" "d"))) 6477 (clobber (match_scratch:DF 2 "=d"))] 6478 "TARGET_FCFID && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" 6479 "#" 6480 "&& reload_completed" 6481 [(set (match_dup 2) 6482 (float:DF (match_dup 1))) 6483 (set (match_dup 0) 6484 (float_truncate:SF (match_dup 2)))] 6485 "" 6486 [(set_attr "length" "8") 6487 (set_attr "type" "fp")]) 6488 6489;; Twiddles bits to avoid double rounding. 6490;; Bits that might be truncated when converting to DFmode are replaced 6491;; by a bit that won't be lost at that stage, but is below the SFmode 6492;; rounding position. 6493(define_expand "floatdisf2_internal2" 6494 [(set (match_dup 3) (ashiftrt:DI (match_operand:DI 1 "" "") 6495 (const_int 53))) 6496 (parallel [(set (match_operand:DI 0 "" "") (and:DI (match_dup 1) 6497 (const_int 2047))) 6498 (clobber (scratch:CC))]) 6499 (set (match_dup 3) (plus:DI (match_dup 3) 6500 (const_int 1))) 6501 (set (match_dup 0) (plus:DI (match_dup 0) 6502 (const_int 2047))) 6503 (set (match_dup 4) (compare:CCUNS (match_dup 3) 6504 (const_int 2))) 6505 (set (match_dup 0) (ior:DI (match_dup 0) 6506 (match_dup 1))) 6507 (parallel [(set (match_dup 0) (and:DI (match_dup 0) 6508 (const_int -2048))) 6509 (clobber (scratch:CC))]) 6510 (set (pc) (if_then_else (geu (match_dup 4) (const_int 0)) 6511 (label_ref (match_operand:DI 2 "" "")) 6512 (pc))) 6513 (set (match_dup 0) (match_dup 1))] 6514 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT" 6515 " 6516{ 6517 operands[3] = gen_reg_rtx (DImode); 6518 operands[4] = gen_reg_rtx (CCUNSmode); 6519}") 6520 6521(define_expand "floatunsdisf2" 6522 [(set (match_operand:SF 0 "gpc_reg_operand" "") 6523 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "")))] 6524 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT 6525 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS" 6526 "") 6527 6528(define_insn "floatunsdisf2_fcfidus" 6529 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6530 (unsigned_float:SF (match_operand:DI 1 "gpc_reg_operand" "d")))] 6531 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT 6532 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS" 6533 "fcfidus %0,%1" 6534 [(set_attr "type" "fp")]) 6535 6536(define_insn_and_split "*floatunsdisf2_mem" 6537 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 6538 (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m"))) 6539 (clobber (match_scratch:DI 2 "=f"))] 6540 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT 6541 && TARGET_DOUBLE_FLOAT && TARGET_FCFIDUS" 6542 "#" 6543 "&& reload_completed" 6544 [(pc)] 6545 " 6546{ 6547 emit_move_insn (operands[2], operands[1]); 6548 emit_insn (gen_floatunsdisf2_fcfidus (operands[0], operands[2])); 6549 DONE; 6550}" 6551 [(set_attr "length" "8") 6552 (set_attr "type" "fpload")]) 6553 6554;; Define the TImode operations that can be done in a small number 6555;; of instructions. The & constraints are to prevent the register 6556;; allocator from allocating registers that overlap with the inputs 6557;; (for example, having an input in 7,8 and an output in 6,7). We 6558;; also allow for the output being the same as one of the inputs. 6559 6560(define_insn "addti3" 6561 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r") 6562 (plus:TI (match_operand:TI 1 "gpc_reg_operand" "%r,r,0,0") 6563 (match_operand:TI 2 "reg_or_short_operand" "r,I,r,I")))] 6564 "TARGET_64BIT" 6565{ 6566 if (WORDS_BIG_ENDIAN) 6567 return (GET_CODE (operands[2])) != CONST_INT 6568 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\" 6569 : \"addic %L0,%L1,%2\;add%G2e %0,%1\"; 6570 else 6571 return (GET_CODE (operands[2])) != CONST_INT 6572 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\" 6573 : \"addic %0,%1,%2\;add%G2e %L0,%L1\"; 6574} 6575 [(set_attr "type" "two") 6576 (set_attr "length" "8")]) 6577 6578(define_insn "subti3" 6579 [(set (match_operand:TI 0 "gpc_reg_operand" "=&r,&r,r,r,r") 6580 (minus:TI (match_operand:TI 1 "reg_or_short_operand" "r,I,0,r,I") 6581 (match_operand:TI 2 "gpc_reg_operand" "r,r,r,0,0")))] 6582 "TARGET_64BIT" 6583{ 6584 if (WORDS_BIG_ENDIAN) 6585 return (GET_CODE (operands[1]) != CONST_INT) 6586 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\" 6587 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\"; 6588 else 6589 return (GET_CODE (operands[1]) != CONST_INT) 6590 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\" 6591 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\"; 6592} 6593 [(set_attr "type" "two") 6594 (set_attr "length" "8")]) 6595 6596 6597;; Define the DImode operations that can be done in a small number 6598;; of instructions. The & constraints are to prevent the register 6599;; allocator from allocating registers that overlap with the inputs 6600;; (for example, having an input in 7,8 and an output in 6,7). We 6601;; also allow for the output being the same as one of the inputs. 6602 6603(define_insn "*adddi3_noppc64" 6604 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r") 6605 (plus:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,0,0") 6606 (match_operand:DI 2 "reg_or_short_operand" "r,I,r,I")))] 6607 "! TARGET_POWERPC64" 6608 "* 6609{ 6610 if (WORDS_BIG_ENDIAN) 6611 return (GET_CODE (operands[2])) != CONST_INT 6612 ? \"addc %L0,%L1,%L2\;adde %0,%1,%2\" 6613 : \"addic %L0,%L1,%2\;add%G2e %0,%1\"; 6614 else 6615 return (GET_CODE (operands[2])) != CONST_INT 6616 ? \"addc %0,%1,%2\;adde %L0,%L1,%L2\" 6617 : \"addic %0,%1,%2\;add%G2e %L0,%L1\"; 6618}" 6619 [(set_attr "type" "two") 6620 (set_attr "length" "8")]) 6621 6622(define_insn "*subdi3_noppc64" 6623 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r,r,r,r") 6624 (minus:DI (match_operand:DI 1 "reg_or_short_operand" "r,I,0,r,I") 6625 (match_operand:DI 2 "gpc_reg_operand" "r,r,r,0,0")))] 6626 "! TARGET_POWERPC64" 6627 "* 6628{ 6629 if (WORDS_BIG_ENDIAN) 6630 return (GET_CODE (operands[1]) != CONST_INT) 6631 ? \"subfc %L0,%L2,%L1\;subfe %0,%2,%1\" 6632 : \"subfic %L0,%L2,%1\;subf%G1e %0,%2\"; 6633 else 6634 return (GET_CODE (operands[1]) != CONST_INT) 6635 ? \"subfc %0,%2,%1\;subfe %L0,%L2,%L1\" 6636 : \"subfic %0,%2,%1\;subf%G1e %L0,%L2\"; 6637}" 6638 [(set_attr "type" "two") 6639 (set_attr "length" "8")]) 6640 6641(define_insn "*negdi2_noppc64" 6642 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,r") 6643 (neg:DI (match_operand:DI 1 "gpc_reg_operand" "r,0")))] 6644 "! TARGET_POWERPC64" 6645 "* 6646{ 6647 return (WORDS_BIG_ENDIAN) 6648 ? \"subfic %L0,%L1,0\;subfze %0,%1\" 6649 : \"subfic %0,%1,0\;subfze %L0,%L1\"; 6650}" 6651 [(set_attr "type" "two") 6652 (set_attr "length" "8")]) 6653 6654(define_insn "mulsidi3" 6655 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 6656 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 6657 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 6658 "! TARGET_POWERPC64" 6659{ 6660 return (WORDS_BIG_ENDIAN) 6661 ? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\" 6662 : \"mulhw %L0,%1,%2\;mullw %0,%1,%2\"; 6663} 6664 [(set_attr "type" "imul") 6665 (set_attr "length" "8")]) 6666 6667(define_split 6668 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6669 (mult:DI (sign_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 6670 (sign_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 6671 "! TARGET_POWERPC64 && reload_completed" 6672 [(set (match_dup 3) 6673 (truncate:SI 6674 (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 6675 (sign_extend:DI (match_dup 2))) 6676 (const_int 32)))) 6677 (set (match_dup 4) 6678 (mult:SI (match_dup 1) 6679 (match_dup 2)))] 6680 " 6681{ 6682 int endian = (WORDS_BIG_ENDIAN == 0); 6683 operands[3] = operand_subword (operands[0], endian, 0, DImode); 6684 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); 6685}") 6686 6687(define_insn "umulsidi3" 6688 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r") 6689 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "%r")) 6690 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" "r"))))] 6691 "! TARGET_POWERPC64" 6692 "* 6693{ 6694 return (WORDS_BIG_ENDIAN) 6695 ? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\" 6696 : \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\"; 6697}" 6698 [(set_attr "type" "imul") 6699 (set_attr "length" "8")]) 6700 6701(define_split 6702 [(set (match_operand:DI 0 "gpc_reg_operand" "") 6703 (mult:DI (zero_extend:DI (match_operand:SI 1 "gpc_reg_operand" "")) 6704 (zero_extend:DI (match_operand:SI 2 "gpc_reg_operand" ""))))] 6705 "! TARGET_POWERPC64 && reload_completed" 6706 [(set (match_dup 3) 6707 (truncate:SI 6708 (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 6709 (zero_extend:DI (match_dup 2))) 6710 (const_int 32)))) 6711 (set (match_dup 4) 6712 (mult:SI (match_dup 1) 6713 (match_dup 2)))] 6714 " 6715{ 6716 int endian = (WORDS_BIG_ENDIAN == 0); 6717 operands[3] = operand_subword (operands[0], endian, 0, DImode); 6718 operands[4] = operand_subword (operands[0], 1 - endian, 0, DImode); 6719}") 6720 6721(define_insn "smulsi3_highpart" 6722 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6723 (truncate:SI 6724 (lshiftrt:DI (mult:DI (sign_extend:DI 6725 (match_operand:SI 1 "gpc_reg_operand" "%r")) 6726 (sign_extend:DI 6727 (match_operand:SI 2 "gpc_reg_operand" "r"))) 6728 (const_int 32))))] 6729 "" 6730 "mulhw %0,%1,%2" 6731 [(set_attr "type" "imul")]) 6732 6733(define_insn "umulsi3_highpart" 6734 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6735 (truncate:SI 6736 (lshiftrt:DI (mult:DI (zero_extend:DI 6737 (match_operand:SI 1 "gpc_reg_operand" "%r")) 6738 (zero_extend:DI 6739 (match_operand:SI 2 "gpc_reg_operand" "r"))) 6740 (const_int 32))))] 6741 "" 6742 "mulhwu %0,%1,%2" 6743 [(set_attr "type" "imul")]) 6744 6745;; Shift by a variable amount is too complex to be worth open-coding. We 6746;; just handle shifts by constants. 6747(define_insn "ashrdi3_no_power" 6748 [(set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") 6749 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6750 (match_operand:SI 2 "const_int_operand" "M,i")))] 6751 "!TARGET_POWERPC64" 6752 "* 6753{ 6754 switch (which_alternative) 6755 { 6756 default: 6757 gcc_unreachable (); 6758 case 0: 6759 if (WORDS_BIG_ENDIAN) 6760 return \"srawi %0,%1,31\;srawi %L0,%1,%h2\"; 6761 else 6762 return \"srawi %L0,%L1,31\;srawi %0,%L1,%h2\"; 6763 case 1: 6764 if (WORDS_BIG_ENDIAN) 6765 return \"srwi %L0,%L1,%h2\;insrwi %L0,%1,%h2,0\;srawi %0,%1,%h2\"; 6766 else 6767 return \"srwi %0,%1,%h2\;insrwi %0,%L1,%h2,0\;srawi %L0,%L1,%h2\"; 6768 } 6769}" 6770 [(set_attr "type" "two,three") 6771 (set_attr "length" "8,12")]) 6772 6773(define_insn "*ashrdisi3_noppc64be" 6774 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 6775 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r") 6776 (const_int 32)) 4))] 6777 "TARGET_32BIT && !TARGET_POWERPC64 && WORDS_BIG_ENDIAN" 6778 "* 6779{ 6780 if (REGNO (operands[0]) == REGNO (operands[1])) 6781 return \"\"; 6782 else 6783 return \"mr %0,%1\"; 6784}" 6785 [(set_attr "length" "4")]) 6786 6787 6788;; PowerPC64 DImode operations. 6789 6790(define_insn "muldi3" 6791 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6792 (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") 6793 (match_operand:DI 2 "reg_or_short_operand" "r,I")))] 6794 "TARGET_POWERPC64" 6795 "@ 6796 mulld %0,%1,%2 6797 mulli %0,%1,%2" 6798 [(set (attr "type") 6799 (cond [(match_operand:SI 2 "s8bit_cint_operand" "") 6800 (const_string "imul3") 6801 (match_operand:SI 2 "short_cint_operand" "") 6802 (const_string "imul2")] 6803 (const_string "lmul")))]) 6804 6805(define_insn "*muldi3_internal1" 6806 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 6807 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") 6808 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 6809 (const_int 0))) 6810 (clobber (match_scratch:DI 3 "=r,r"))] 6811 "TARGET_POWERPC64" 6812 "@ 6813 mulld. %3,%1,%2 6814 #" 6815 [(set_attr "type" "lmul_compare") 6816 (set_attr "length" "4,8")]) 6817 6818(define_split 6819 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 6820 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") 6821 (match_operand:DI 2 "gpc_reg_operand" "")) 6822 (const_int 0))) 6823 (clobber (match_scratch:DI 3 ""))] 6824 "TARGET_POWERPC64 && reload_completed" 6825 [(set (match_dup 3) 6826 (mult:DI (match_dup 1) (match_dup 2))) 6827 (set (match_dup 0) 6828 (compare:CC (match_dup 3) 6829 (const_int 0)))] 6830 "") 6831 6832(define_insn "*muldi3_internal2" 6833 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 6834 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r") 6835 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 6836 (const_int 0))) 6837 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6838 (mult:DI (match_dup 1) (match_dup 2)))] 6839 "TARGET_POWERPC64" 6840 "@ 6841 mulld. %0,%1,%2 6842 #" 6843 [(set_attr "type" "lmul_compare") 6844 (set_attr "length" "4,8")]) 6845 6846(define_split 6847 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 6848 (compare:CC (mult:DI (match_operand:DI 1 "gpc_reg_operand" "") 6849 (match_operand:DI 2 "gpc_reg_operand" "")) 6850 (const_int 0))) 6851 (set (match_operand:DI 0 "gpc_reg_operand" "") 6852 (mult:DI (match_dup 1) (match_dup 2)))] 6853 "TARGET_POWERPC64 && reload_completed" 6854 [(set (match_dup 0) 6855 (mult:DI (match_dup 1) (match_dup 2))) 6856 (set (match_dup 3) 6857 (compare:CC (match_dup 0) 6858 (const_int 0)))] 6859 "") 6860 6861(define_insn "smuldi3_highpart" 6862 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6863 (truncate:DI 6864 (lshiftrt:TI (mult:TI (sign_extend:TI 6865 (match_operand:DI 1 "gpc_reg_operand" "%r")) 6866 (sign_extend:TI 6867 (match_operand:DI 2 "gpc_reg_operand" "r"))) 6868 (const_int 64))))] 6869 "TARGET_POWERPC64" 6870 "mulhd %0,%1,%2" 6871 [(set_attr "type" "lmul")]) 6872 6873(define_insn "umuldi3_highpart" 6874 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 6875 (truncate:DI 6876 (lshiftrt:TI (mult:TI (zero_extend:TI 6877 (match_operand:DI 1 "gpc_reg_operand" "%r")) 6878 (zero_extend:TI 6879 (match_operand:DI 2 "gpc_reg_operand" "r"))) 6880 (const_int 64))))] 6881 "TARGET_POWERPC64" 6882 "mulhdu %0,%1,%2" 6883 [(set_attr "type" "lmul")]) 6884 6885(define_expand "mulditi3" 6886 [(set (match_operand:TI 0 "gpc_reg_operand") 6887 (mult:TI (sign_extend:TI (match_operand:DI 1 "gpc_reg_operand")) 6888 (sign_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))] 6889 "TARGET_POWERPC64" 6890{ 6891 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode); 6892 emit_insn (gen_muldi3 (l, operands[1], operands[2])); 6893 emit_insn (gen_smuldi3_highpart (h, operands[1], operands[2])); 6894 emit_move_insn (gen_lowpart (DImode, operands[0]), l); 6895 emit_move_insn (gen_highpart (DImode, operands[0]), h); 6896 DONE; 6897}) 6898 6899(define_expand "umulditi3" 6900 [(set (match_operand:TI 0 "gpc_reg_operand") 6901 (mult:TI (zero_extend:TI (match_operand:DI 1 "gpc_reg_operand")) 6902 (zero_extend:TI (match_operand:DI 2 "gpc_reg_operand"))))] 6903 "TARGET_POWERPC64" 6904{ 6905 rtx l = gen_reg_rtx (DImode), h = gen_reg_rtx (DImode); 6906 emit_insn (gen_muldi3 (l, operands[1], operands[2])); 6907 emit_insn (gen_umuldi3_highpart (h, operands[1], operands[2])); 6908 emit_move_insn (gen_lowpart (DImode, operands[0]), l); 6909 emit_move_insn (gen_highpart (DImode, operands[0]), h); 6910 DONE; 6911}) 6912 6913(define_insn "rotldi3" 6914 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6915 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6916 (match_operand:DI 2 "reg_or_cint_operand" "r,i")))] 6917 "TARGET_POWERPC64" 6918 "@ 6919 rldcl %0,%1,%2,0 6920 rldicl %0,%1,%H2,0" 6921 [(set_attr "type" "var_shift_rotate,integer")]) 6922 6923(define_insn "*rotldi3_internal2" 6924 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 6925 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 6926 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6927 (const_int 0))) 6928 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 6929 "TARGET_64BIT" 6930 "@ 6931 rldcl. %3,%1,%2,0 6932 rldicl. %3,%1,%H2,0 6933 # 6934 #" 6935 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 6936 (set_attr "length" "4,4,8,8")]) 6937 6938(define_split 6939 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 6940 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6941 (match_operand:DI 2 "reg_or_cint_operand" "")) 6942 (const_int 0))) 6943 (clobber (match_scratch:DI 3 ""))] 6944 "TARGET_POWERPC64 && reload_completed" 6945 [(set (match_dup 3) 6946 (rotate:DI (match_dup 1) (match_dup 2))) 6947 (set (match_dup 0) 6948 (compare:CC (match_dup 3) 6949 (const_int 0)))] 6950 "") 6951 6952(define_insn "*rotldi3_internal3" 6953 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 6954 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 6955 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6956 (const_int 0))) 6957 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 6958 (rotate:DI (match_dup 1) (match_dup 2)))] 6959 "TARGET_64BIT" 6960 "@ 6961 rldcl. %0,%1,%2,0 6962 rldicl. %0,%1,%H2,0 6963 # 6964 #" 6965 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 6966 (set_attr "length" "4,4,8,8")]) 6967 6968(define_split 6969 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 6970 (compare:CC (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 6971 (match_operand:DI 2 "reg_or_cint_operand" "")) 6972 (const_int 0))) 6973 (set (match_operand:DI 0 "gpc_reg_operand" "") 6974 (rotate:DI (match_dup 1) (match_dup 2)))] 6975 "TARGET_POWERPC64 && reload_completed" 6976 [(set (match_dup 0) 6977 (rotate:DI (match_dup 1) (match_dup 2))) 6978 (set (match_dup 3) 6979 (compare:CC (match_dup 0) 6980 (const_int 0)))] 6981 "") 6982 6983(define_insn "*rotldi3_internal4" 6984 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 6985 (and:DI (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 6986 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6987 (match_operand:DI 3 "mask64_operand" "n,n")))] 6988 "TARGET_POWERPC64" 6989 "@ 6990 rldc%B3 %0,%1,%2,%S3 6991 rldic%B3 %0,%1,%H2,%S3" 6992 [(set_attr "type" "var_shift_rotate,integer")]) 6993 6994(define_insn "*rotldi3_internal5" 6995 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 6996 (compare:CC (and:DI 6997 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 6998 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6999 (match_operand:DI 3 "mask64_operand" "n,n,n,n")) 7000 (const_int 0))) 7001 (clobber (match_scratch:DI 4 "=r,r,r,r"))] 7002 "TARGET_64BIT" 7003 "@ 7004 rldc%B3. %4,%1,%2,%S3 7005 rldic%B3. %4,%1,%H2,%S3 7006 # 7007 #" 7008 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7009 (set_attr "length" "4,4,8,8")]) 7010 7011(define_split 7012 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7013 (compare:CC (and:DI 7014 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7015 (match_operand:DI 2 "reg_or_cint_operand" "")) 7016 (match_operand:DI 3 "mask64_operand" "")) 7017 (const_int 0))) 7018 (clobber (match_scratch:DI 4 ""))] 7019 "TARGET_POWERPC64 && reload_completed" 7020 [(set (match_dup 4) 7021 (and:DI (rotate:DI (match_dup 1) 7022 (match_dup 2)) 7023 (match_dup 3))) 7024 (set (match_dup 0) 7025 (compare:CC (match_dup 4) 7026 (const_int 0)))] 7027 "") 7028 7029(define_insn "*rotldi3_internal6" 7030 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 7031 (compare:CC (and:DI 7032 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7033 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7034 (match_operand:DI 3 "mask64_operand" "n,n,n,n")) 7035 (const_int 0))) 7036 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7037 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7038 "TARGET_64BIT" 7039 "@ 7040 rldc%B3. %0,%1,%2,%S3 7041 rldic%B3. %0,%1,%H2,%S3 7042 # 7043 #" 7044 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7045 (set_attr "length" "4,4,8,8")]) 7046 7047(define_split 7048 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") 7049 (compare:CC (and:DI 7050 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7051 (match_operand:DI 2 "reg_or_cint_operand" "")) 7052 (match_operand:DI 3 "mask64_operand" "")) 7053 (const_int 0))) 7054 (set (match_operand:DI 0 "gpc_reg_operand" "") 7055 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7056 "TARGET_POWERPC64 && reload_completed" 7057 [(set (match_dup 0) 7058 (and:DI (rotate:DI (match_dup 1) (match_dup 2)) (match_dup 3))) 7059 (set (match_dup 4) 7060 (compare:CC (match_dup 0) 7061 (const_int 0)))] 7062 "") 7063 7064(define_insn "*rotldi3_internal7le" 7065 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7066 (zero_extend:DI 7067 (subreg:QI 7068 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7069 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] 7070 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" 7071 "@ 7072 rldcl %0,%1,%2,56 7073 rldicl %0,%1,%H2,56" 7074 [(set_attr "type" "var_shift_rotate,integer")]) 7075 7076(define_insn "*rotldi3_internal7be" 7077 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7078 (zero_extend:DI 7079 (subreg:QI 7080 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7081 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 7)))] 7082 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" 7083 "@ 7084 rldcl %0,%1,%2,56 7085 rldicl %0,%1,%H2,56" 7086 [(set_attr "type" "var_shift_rotate,integer")]) 7087 7088(define_insn "*rotldi3_internal8le" 7089 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 7090 (compare:CC (zero_extend:DI 7091 (subreg:QI 7092 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7093 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 7094 (const_int 0))) 7095 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 7096 "TARGET_64BIT && !BYTES_BIG_ENDIAN" 7097 "@ 7098 rldcl. %3,%1,%2,56 7099 rldicl. %3,%1,%H2,56 7100 # 7101 #" 7102 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7103 (set_attr "length" "4,4,8,8")]) 7104 7105(define_insn "*rotldi3_internal8be" 7106 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 7107 (compare:CC (zero_extend:DI 7108 (subreg:QI 7109 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7110 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7)) 7111 (const_int 0))) 7112 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 7113 "TARGET_64BIT && BYTES_BIG_ENDIAN" 7114 "@ 7115 rldcl. %3,%1,%2,56 7116 rldicl. %3,%1,%H2,56 7117 # 7118 #" 7119 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7120 (set_attr "length" "4,4,8,8")]) 7121 7122(define_split 7123 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7124 (compare:CC (zero_extend:DI 7125 (subreg:QI 7126 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7127 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 7128 (const_int 0))) 7129 (clobber (match_scratch:DI 3 ""))] 7130 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" 7131 [(set (match_dup 3) 7132 (zero_extend:DI (subreg:QI 7133 (rotate:DI (match_dup 1) 7134 (match_dup 2)) 0))) 7135 (set (match_dup 0) 7136 (compare:CC (match_dup 3) 7137 (const_int 0)))] 7138 "") 7139 7140(define_split 7141 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7142 (compare:CC (zero_extend:DI 7143 (subreg:QI 7144 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7145 (match_operand:DI 2 "reg_or_cint_operand" "")) 7)) 7146 (const_int 0))) 7147 (clobber (match_scratch:DI 3 ""))] 7148 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" 7149 [(set (match_dup 3) 7150 (zero_extend:DI (subreg:QI 7151 (rotate:DI (match_dup 1) 7152 (match_dup 2)) 7))) 7153 (set (match_dup 0) 7154 (compare:CC (match_dup 3) 7155 (const_int 0)))] 7156 "") 7157 7158(define_insn "*rotldi3_internal9le" 7159 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 7160 (compare:CC (zero_extend:DI 7161 (subreg:QI 7162 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7163 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 7164 (const_int 0))) 7165 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7166 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 7167 "TARGET_64BIT && !BYTES_BIG_ENDIAN" 7168 "@ 7169 rldcl. %0,%1,%2,56 7170 rldicl. %0,%1,%H2,56 7171 # 7172 #" 7173 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7174 (set_attr "length" "4,4,8,8")]) 7175 7176(define_insn "*rotldi3_internal9be" 7177 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 7178 (compare:CC (zero_extend:DI 7179 (subreg:QI 7180 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7181 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 7)) 7182 (const_int 0))) 7183 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7184 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))] 7185 "TARGET_64BIT && BYTES_BIG_ENDIAN" 7186 "@ 7187 rldcl. %0,%1,%2,56 7188 rldicl. %0,%1,%H2,56 7189 # 7190 #" 7191 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7192 (set_attr "length" "4,4,8,8")]) 7193 7194(define_split 7195 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 7196 (compare:CC (zero_extend:DI 7197 (subreg:QI 7198 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7199 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 7200 (const_int 0))) 7201 (set (match_operand:DI 0 "gpc_reg_operand" "") 7202 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 7203 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" 7204 [(set (match_dup 0) 7205 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 7206 (set (match_dup 3) 7207 (compare:CC (match_dup 0) 7208 (const_int 0)))] 7209 "") 7210 7211(define_split 7212 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 7213 (compare:CC (zero_extend:DI 7214 (subreg:QI 7215 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7216 (match_operand:DI 2 "reg_or_cint_operand" "")) 7)) 7217 (const_int 0))) 7218 (set (match_operand:DI 0 "gpc_reg_operand" "") 7219 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7)))] 7220 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" 7221 [(set (match_dup 0) 7222 (zero_extend:DI (subreg:QI (rotate:DI (match_dup 1) (match_dup 2)) 7))) 7223 (set (match_dup 3) 7224 (compare:CC (match_dup 0) 7225 (const_int 0)))] 7226 "") 7227 7228(define_insn "*rotldi3_internal10le" 7229 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7230 (zero_extend:DI 7231 (subreg:HI 7232 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7233 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] 7234 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" 7235 "@ 7236 rldcl %0,%1,%2,48 7237 rldicl %0,%1,%H2,48" 7238 [(set_attr "type" "var_shift_rotate,integer")]) 7239 7240(define_insn "*rotldi3_internal10be" 7241 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7242 (zero_extend:DI 7243 (subreg:HI 7244 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7245 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 6)))] 7246 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" 7247 "@ 7248 rldcl %0,%1,%2,48 7249 rldicl %0,%1,%H2,48" 7250 [(set_attr "type" "var_shift_rotate,integer")]) 7251 7252(define_insn "*rotldi3_internal11le" 7253 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 7254 (compare:CC (zero_extend:DI 7255 (subreg:HI 7256 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7257 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 7258 (const_int 0))) 7259 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 7260 "TARGET_64BIT && !BYTES_BIG_ENDIAN" 7261 "@ 7262 rldcl. %3,%1,%2,48 7263 rldicl. %3,%1,%H2,48 7264 # 7265 #" 7266 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7267 (set_attr "length" "4,4,8,8")]) 7268 7269(define_insn "*rotldi3_internal11be" 7270 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 7271 (compare:CC (zero_extend:DI 7272 (subreg:HI 7273 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7274 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6)) 7275 (const_int 0))) 7276 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 7277 "TARGET_64BIT && BYTES_BIG_ENDIAN" 7278 "@ 7279 rldcl. %3,%1,%2,48 7280 rldicl. %3,%1,%H2,48 7281 # 7282 #" 7283 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7284 (set_attr "length" "4,4,8,8")]) 7285 7286(define_split 7287 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7288 (compare:CC (zero_extend:DI 7289 (subreg:HI 7290 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7291 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 7292 (const_int 0))) 7293 (clobber (match_scratch:DI 3 ""))] 7294 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" 7295 [(set (match_dup 3) 7296 (zero_extend:DI (subreg:HI 7297 (rotate:DI (match_dup 1) 7298 (match_dup 2)) 0))) 7299 (set (match_dup 0) 7300 (compare:CC (match_dup 3) 7301 (const_int 0)))] 7302 "") 7303 7304(define_split 7305 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7306 (compare:CC (zero_extend:DI 7307 (subreg:HI 7308 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7309 (match_operand:DI 2 "reg_or_cint_operand" "")) 6)) 7310 (const_int 0))) 7311 (clobber (match_scratch:DI 3 ""))] 7312 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" 7313 [(set (match_dup 3) 7314 (zero_extend:DI (subreg:HI 7315 (rotate:DI (match_dup 1) 7316 (match_dup 2)) 6))) 7317 (set (match_dup 0) 7318 (compare:CC (match_dup 3) 7319 (const_int 0)))] 7320 "") 7321 7322(define_insn "*rotldi3_internal12le" 7323 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 7324 (compare:CC (zero_extend:DI 7325 (subreg:HI 7326 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7327 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 7328 (const_int 0))) 7329 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7330 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 7331 "TARGET_64BIT && !BYTES_BIG_ENDIAN" 7332 "@ 7333 rldcl. %0,%1,%2,48 7334 rldicl. %0,%1,%H2,48 7335 # 7336 #" 7337 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7338 (set_attr "length" "4,4,8,8")]) 7339 7340(define_insn "*rotldi3_internal12be" 7341 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 7342 (compare:CC (zero_extend:DI 7343 (subreg:HI 7344 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7345 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 6)) 7346 (const_int 0))) 7347 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7348 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))] 7349 "TARGET_64BIT && BYTES_BIG_ENDIAN" 7350 "@ 7351 rldcl. %0,%1,%2,48 7352 rldicl. %0,%1,%H2,48 7353 # 7354 #" 7355 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7356 (set_attr "length" "4,4,8,8")]) 7357 7358(define_split 7359 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 7360 (compare:CC (zero_extend:DI 7361 (subreg:HI 7362 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7363 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 7364 (const_int 0))) 7365 (set (match_operand:DI 0 "gpc_reg_operand" "") 7366 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 7367 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" 7368 [(set (match_dup 0) 7369 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 7370 (set (match_dup 3) 7371 (compare:CC (match_dup 0) 7372 (const_int 0)))] 7373 "") 7374 7375(define_split 7376 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 7377 (compare:CC (zero_extend:DI 7378 (subreg:HI 7379 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7380 (match_operand:DI 2 "reg_or_cint_operand" "")) 6)) 7381 (const_int 0))) 7382 (set (match_operand:DI 0 "gpc_reg_operand" "") 7383 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6)))] 7384 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" 7385 [(set (match_dup 0) 7386 (zero_extend:DI (subreg:HI (rotate:DI (match_dup 1) (match_dup 2)) 6))) 7387 (set (match_dup 3) 7388 (compare:CC (match_dup 0) 7389 (const_int 0)))] 7390 "") 7391 7392(define_insn "*rotldi3_internal13le" 7393 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7394 (zero_extend:DI 7395 (subreg:SI 7396 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7397 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 0)))] 7398 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN" 7399 "@ 7400 rldcl %0,%1,%2,32 7401 rldicl %0,%1,%H2,32" 7402 [(set_attr "type" "var_shift_rotate,integer")]) 7403 7404(define_insn "*rotldi3_internal13be" 7405 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7406 (zero_extend:DI 7407 (subreg:SI 7408 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7409 (match_operand:DI 2 "reg_or_cint_operand" "r,i")) 4)))] 7410 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN" 7411 "@ 7412 rldcl %0,%1,%2,32 7413 rldicl %0,%1,%H2,32" 7414 [(set_attr "type" "var_shift_rotate,integer")]) 7415 7416(define_insn "*rotldi3_internal14le" 7417 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 7418 (compare:CC (zero_extend:DI 7419 (subreg:SI 7420 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7421 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 7422 (const_int 0))) 7423 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 7424 "TARGET_64BIT && !BYTES_BIG_ENDIAN" 7425 "@ 7426 rldcl. %3,%1,%2,32 7427 rldicl. %3,%1,%H2,32 7428 # 7429 #" 7430 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7431 (set_attr "length" "4,4,8,8")]) 7432 7433(define_insn "*rotldi3_internal14be" 7434 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 7435 (compare:CC (zero_extend:DI 7436 (subreg:SI 7437 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7438 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4)) 7439 (const_int 0))) 7440 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 7441 "TARGET_64BIT && BYTES_BIG_ENDIAN" 7442 "@ 7443 rldcl. %3,%1,%2,32 7444 rldicl. %3,%1,%H2,32 7445 # 7446 #" 7447 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7448 (set_attr "length" "4,4,8,8")]) 7449 7450(define_split 7451 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7452 (compare:CC (zero_extend:DI 7453 (subreg:SI 7454 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7455 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 7456 (const_int 0))) 7457 (clobber (match_scratch:DI 3 ""))] 7458 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" 7459 [(set (match_dup 3) 7460 (zero_extend:DI (subreg:SI 7461 (rotate:DI (match_dup 1) 7462 (match_dup 2)) 0))) 7463 (set (match_dup 0) 7464 (compare:CC (match_dup 3) 7465 (const_int 0)))] 7466 "") 7467 7468(define_split 7469 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7470 (compare:CC (zero_extend:DI 7471 (subreg:SI 7472 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7473 (match_operand:DI 2 "reg_or_cint_operand" "")) 4)) 7474 (const_int 0))) 7475 (clobber (match_scratch:DI 3 ""))] 7476 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" 7477 [(set (match_dup 3) 7478 (zero_extend:DI (subreg:SI 7479 (rotate:DI (match_dup 1) 7480 (match_dup 2)) 4))) 7481 (set (match_dup 0) 7482 (compare:CC (match_dup 3) 7483 (const_int 0)))] 7484 "") 7485 7486(define_insn "*rotldi3_internal15le" 7487 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 7488 (compare:CC (zero_extend:DI 7489 (subreg:SI 7490 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7491 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 0)) 7492 (const_int 0))) 7493 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7494 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 7495 "TARGET_64BIT && !BYTES_BIG_ENDIAN" 7496 "@ 7497 rldcl. %0,%1,%2,32 7498 rldicl. %0,%1,%H2,32 7499 # 7500 #" 7501 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7502 (set_attr "length" "4,4,8,8")]) 7503 7504(define_insn "*rotldi3_internal15be" 7505 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 7506 (compare:CC (zero_extend:DI 7507 (subreg:SI 7508 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7509 (match_operand:DI 2 "reg_or_cint_operand" "r,i,r,i")) 4)) 7510 (const_int 0))) 7511 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7512 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))] 7513 "TARGET_64BIT && BYTES_BIG_ENDIAN" 7514 "@ 7515 rldcl. %0,%1,%2,32 7516 rldicl. %0,%1,%H2,32 7517 # 7518 #" 7519 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7520 (set_attr "length" "4,4,8,8")]) 7521 7522(define_split 7523 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 7524 (compare:CC (zero_extend:DI 7525 (subreg:SI 7526 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7527 (match_operand:DI 2 "reg_or_cint_operand" "")) 0)) 7528 (const_int 0))) 7529 (set (match_operand:DI 0 "gpc_reg_operand" "") 7530 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0)))] 7531 "TARGET_POWERPC64 && !BYTES_BIG_ENDIAN && reload_completed" 7532 [(set (match_dup 0) 7533 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 0))) 7534 (set (match_dup 3) 7535 (compare:CC (match_dup 0) 7536 (const_int 0)))] 7537 "") 7538 7539(define_split 7540 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 7541 (compare:CC (zero_extend:DI 7542 (subreg:SI 7543 (rotate:DI (match_operand:DI 1 "gpc_reg_operand" "") 7544 (match_operand:DI 2 "reg_or_cint_operand" "")) 4)) 7545 (const_int 0))) 7546 (set (match_operand:DI 0 "gpc_reg_operand" "") 7547 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4)))] 7548 "TARGET_POWERPC64 && BYTES_BIG_ENDIAN && reload_completed" 7549 [(set (match_dup 0) 7550 (zero_extend:DI (subreg:SI (rotate:DI (match_dup 1) (match_dup 2)) 4))) 7551 (set (match_dup 3) 7552 (compare:CC (match_dup 0) 7553 (const_int 0)))] 7554 "") 7555 7556(define_expand "ashldi3" 7557 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7558 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7559 (match_operand:SI 2 "reg_or_cint_operand" "")))] 7560 "TARGET_POWERPC64" 7561 "") 7562 7563(define_insn "*ashldi3_internal1" 7564 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7565 (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7566 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] 7567 "TARGET_POWERPC64" 7568 "@ 7569 sld %0,%1,%2 7570 sldi %0,%1,%H2" 7571 [(set_attr "type" "var_shift_rotate,shift")]) 7572 7573(define_insn "*ashldi3_internal2" 7574 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 7575 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7576 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 7577 (const_int 0))) 7578 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 7579 "TARGET_64BIT" 7580 "@ 7581 sld. %3,%1,%2 7582 sldi. %3,%1,%H2 7583 # 7584 #" 7585 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7586 (set_attr "length" "4,4,8,8")]) 7587 7588(define_split 7589 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7590 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7591 (match_operand:SI 2 "reg_or_cint_operand" "")) 7592 (const_int 0))) 7593 (clobber (match_scratch:DI 3 ""))] 7594 "TARGET_POWERPC64 && reload_completed" 7595 [(set (match_dup 3) 7596 (ashift:DI (match_dup 1) (match_dup 2))) 7597 (set (match_dup 0) 7598 (compare:CC (match_dup 3) 7599 (const_int 0)))] 7600 "") 7601 7602(define_insn "*ashldi3_internal3" 7603 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 7604 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7605 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 7606 (const_int 0))) 7607 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7608 (ashift:DI (match_dup 1) (match_dup 2)))] 7609 "TARGET_64BIT" 7610 "@ 7611 sld. %0,%1,%2 7612 sldi. %0,%1,%H2 7613 # 7614 #" 7615 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7616 (set_attr "length" "4,4,8,8")]) 7617 7618(define_split 7619 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7620 (compare:CC (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7621 (match_operand:SI 2 "reg_or_cint_operand" "")) 7622 (const_int 0))) 7623 (set (match_operand:DI 0 "gpc_reg_operand" "") 7624 (ashift:DI (match_dup 1) (match_dup 2)))] 7625 "TARGET_POWERPC64 && reload_completed" 7626 [(set (match_dup 0) 7627 (ashift:DI (match_dup 1) (match_dup 2))) 7628 (set (match_dup 3) 7629 (compare:CC (match_dup 0) 7630 (const_int 0)))] 7631 "") 7632 7633(define_insn "*ashldi3_internal4" 7634 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7635 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 7636 (match_operand:SI 2 "const_int_operand" "i")) 7637 (match_operand:DI 3 "const_int_operand" "n")))] 7638 "TARGET_POWERPC64 && includes_rldic_lshift_p (operands[2], operands[3])" 7639 "rldic %0,%1,%H2,%W3") 7640 7641(define_insn "ashldi3_internal5" 7642 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7643 (compare:CC 7644 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7645 (match_operand:SI 2 "const_int_operand" "i,i")) 7646 (match_operand:DI 3 "const_int_operand" "n,n")) 7647 (const_int 0))) 7648 (clobber (match_scratch:DI 4 "=r,r"))] 7649 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" 7650 "@ 7651 rldic. %4,%1,%H2,%W3 7652 #" 7653 [(set_attr "type" "compare") 7654 (set_attr "length" "4,8")]) 7655 7656(define_split 7657 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7658 (compare:CC 7659 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7660 (match_operand:SI 2 "const_int_operand" "")) 7661 (match_operand:DI 3 "const_int_operand" "")) 7662 (const_int 0))) 7663 (clobber (match_scratch:DI 4 ""))] 7664 "TARGET_POWERPC64 && reload_completed 7665 && includes_rldic_lshift_p (operands[2], operands[3])" 7666 [(set (match_dup 4) 7667 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 7668 (match_dup 3))) 7669 (set (match_dup 0) 7670 (compare:CC (match_dup 4) 7671 (const_int 0)))] 7672 "") 7673 7674(define_insn "*ashldi3_internal6" 7675 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 7676 (compare:CC 7677 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7678 (match_operand:SI 2 "const_int_operand" "i,i")) 7679 (match_operand:DI 3 "const_int_operand" "n,n")) 7680 (const_int 0))) 7681 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7682 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7683 "TARGET_64BIT && includes_rldic_lshift_p (operands[2], operands[3])" 7684 "@ 7685 rldic. %0,%1,%H2,%W3 7686 #" 7687 [(set_attr "type" "compare") 7688 (set_attr "length" "4,8")]) 7689 7690(define_split 7691 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") 7692 (compare:CC 7693 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7694 (match_operand:SI 2 "const_int_operand" "")) 7695 (match_operand:DI 3 "const_int_operand" "")) 7696 (const_int 0))) 7697 (set (match_operand:DI 0 "gpc_reg_operand" "") 7698 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7699 "TARGET_POWERPC64 && reload_completed 7700 && includes_rldic_lshift_p (operands[2], operands[3])" 7701 [(set (match_dup 0) 7702 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 7703 (match_dup 3))) 7704 (set (match_dup 4) 7705 (compare:CC (match_dup 0) 7706 (const_int 0)))] 7707 "") 7708 7709(define_insn "*ashldi3_internal7" 7710 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 7711 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r") 7712 (match_operand:SI 2 "const_int_operand" "i")) 7713 (match_operand:DI 3 "mask64_operand" "n")))] 7714 "TARGET_POWERPC64 && includes_rldicr_lshift_p (operands[2], operands[3])" 7715 "rldicr %0,%1,%H2,%S3") 7716 7717(define_insn "ashldi3_internal8" 7718 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 7719 (compare:CC 7720 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7721 (match_operand:SI 2 "const_int_operand" "i,i")) 7722 (match_operand:DI 3 "mask64_operand" "n,n")) 7723 (const_int 0))) 7724 (clobber (match_scratch:DI 4 "=r,r"))] 7725 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" 7726 "@ 7727 rldicr. %4,%1,%H2,%S3 7728 #" 7729 [(set_attr "type" "compare") 7730 (set_attr "length" "4,8")]) 7731 7732(define_split 7733 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7734 (compare:CC 7735 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7736 (match_operand:SI 2 "const_int_operand" "")) 7737 (match_operand:DI 3 "mask64_operand" "")) 7738 (const_int 0))) 7739 (clobber (match_scratch:DI 4 ""))] 7740 "TARGET_POWERPC64 && reload_completed 7741 && includes_rldicr_lshift_p (operands[2], operands[3])" 7742 [(set (match_dup 4) 7743 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 7744 (match_dup 3))) 7745 (set (match_dup 0) 7746 (compare:CC (match_dup 4) 7747 (const_int 0)))] 7748 "") 7749 7750(define_insn "*ashldi3_internal9" 7751 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 7752 (compare:CC 7753 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7754 (match_operand:SI 2 "const_int_operand" "i,i")) 7755 (match_operand:DI 3 "mask64_operand" "n,n")) 7756 (const_int 0))) 7757 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7758 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7759 "TARGET_64BIT && includes_rldicr_lshift_p (operands[2], operands[3])" 7760 "@ 7761 rldicr. %0,%1,%H2,%S3 7762 #" 7763 [(set_attr "type" "compare") 7764 (set_attr "length" "4,8")]) 7765 7766(define_split 7767 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") 7768 (compare:CC 7769 (and:DI (ashift:DI (match_operand:DI 1 "gpc_reg_operand" "") 7770 (match_operand:SI 2 "const_int_operand" "")) 7771 (match_operand:DI 3 "mask64_operand" "")) 7772 (const_int 0))) 7773 (set (match_operand:DI 0 "gpc_reg_operand" "") 7774 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) (match_dup 3)))] 7775 "TARGET_POWERPC64 && reload_completed 7776 && includes_rldicr_lshift_p (operands[2], operands[3])" 7777 [(set (match_dup 0) 7778 (and:DI (ashift:DI (match_dup 1) (match_dup 2)) 7779 (match_dup 3))) 7780 (set (match_dup 4) 7781 (compare:CC (match_dup 0) 7782 (const_int 0)))] 7783 "") 7784 7785(define_expand "lshrdi3" 7786 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7787 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7788 (match_operand:SI 2 "reg_or_cint_operand" "")))] 7789 "TARGET_POWERPC64" 7790 "") 7791 7792(define_insn "*lshrdi3_internal1" 7793 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7794 (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7795 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] 7796 "TARGET_POWERPC64" 7797 "@ 7798 srd %0,%1,%2 7799 srdi %0,%1,%H2" 7800 [(set_attr "type" "var_shift_rotate,shift")]) 7801 7802(define_insn "*lshrdi3_internal2" 7803 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 7804 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7805 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 7806 (const_int 0))) 7807 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 7808 "TARGET_64BIT " 7809 "@ 7810 srd. %3,%1,%2 7811 srdi. %3,%1,%H2 7812 # 7813 #" 7814 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7815 (set_attr "length" "4,4,8,8")]) 7816 7817(define_split 7818 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 7819 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7820 (match_operand:SI 2 "reg_or_cint_operand" "")) 7821 (const_int 0))) 7822 (clobber (match_scratch:DI 3 ""))] 7823 "TARGET_POWERPC64 && reload_completed" 7824 [(set (match_dup 3) 7825 (lshiftrt:DI (match_dup 1) (match_dup 2))) 7826 (set (match_dup 0) 7827 (compare:CC (match_dup 3) 7828 (const_int 0)))] 7829 "") 7830 7831(define_insn "*lshrdi3_internal3" 7832 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 7833 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7834 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 7835 (const_int 0))) 7836 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7837 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 7838 "TARGET_64BIT" 7839 "@ 7840 srd. %0,%1,%2 7841 srdi. %0,%1,%H2 7842 # 7843 #" 7844 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7845 (set_attr "length" "4,4,8,8")]) 7846 7847(define_split 7848 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 7849 (compare:CC (lshiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7850 (match_operand:SI 2 "reg_or_cint_operand" "")) 7851 (const_int 0))) 7852 (set (match_operand:DI 0 "gpc_reg_operand" "") 7853 (lshiftrt:DI (match_dup 1) (match_dup 2)))] 7854 "TARGET_POWERPC64 && reload_completed" 7855 [(set (match_dup 0) 7856 (lshiftrt:DI (match_dup 1) (match_dup 2))) 7857 (set (match_dup 3) 7858 (compare:CC (match_dup 0) 7859 (const_int 0)))] 7860 "") 7861 7862(define_expand "ashrdi3" 7863 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7864 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7865 (match_operand:SI 2 "reg_or_cint_operand" "")))] 7866 "" 7867 " 7868{ 7869 if (TARGET_POWERPC64) 7870 ; 7871 else if (GET_CODE (operands[2]) == CONST_INT) 7872 { 7873 emit_insn (gen_ashrdi3_no_power (operands[0], operands[1], operands[2])); 7874 DONE; 7875 } 7876 else 7877 FAIL; 7878}") 7879 7880(define_insn "*ashrdi3_internal1" 7881 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 7882 (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 7883 (match_operand:SI 2 "reg_or_cint_operand" "r,i")))] 7884 "TARGET_POWERPC64" 7885 "@ 7886 srad %0,%1,%2 7887 sradi %0,%1,%H2" 7888 [(set_attr "type" "var_shift_rotate,shift")]) 7889 7890(define_insn "*ashrdi3_internal2" 7891 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 7892 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7893 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 7894 (const_int 0))) 7895 (clobber (match_scratch:DI 3 "=r,r,r,r"))] 7896 "TARGET_64BIT" 7897 "@ 7898 srad. %3,%1,%2 7899 sradi. %3,%1,%H2 7900 # 7901 #" 7902 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7903 (set_attr "length" "4,4,8,8")]) 7904 7905(define_split 7906 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 7907 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7908 (match_operand:SI 2 "reg_or_cint_operand" "")) 7909 (const_int 0))) 7910 (clobber (match_scratch:DI 3 ""))] 7911 "TARGET_POWERPC64 && reload_completed" 7912 [(set (match_dup 3) 7913 (ashiftrt:DI (match_dup 1) (match_dup 2))) 7914 (set (match_dup 0) 7915 (compare:CC (match_dup 3) 7916 (const_int 0)))] 7917 "") 7918 7919(define_insn "*ashrdi3_internal3" 7920 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 7921 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r,r,r") 7922 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i")) 7923 (const_int 0))) 7924 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7925 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 7926 "TARGET_64BIT" 7927 "@ 7928 srad. %0,%1,%2 7929 sradi. %0,%1,%H2 7930 # 7931 #" 7932 [(set_attr "type" "var_delayed_compare,delayed_compare,var_delayed_compare,delayed_compare") 7933 (set_attr "length" "4,4,8,8")]) 7934 7935(define_split 7936 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 7937 (compare:CC (ashiftrt:DI (match_operand:DI 1 "gpc_reg_operand" "") 7938 (match_operand:SI 2 "reg_or_cint_operand" "")) 7939 (const_int 0))) 7940 (set (match_operand:DI 0 "gpc_reg_operand" "") 7941 (ashiftrt:DI (match_dup 1) (match_dup 2)))] 7942 "TARGET_POWERPC64 && reload_completed" 7943 [(set (match_dup 0) 7944 (ashiftrt:DI (match_dup 1) (match_dup 2))) 7945 (set (match_dup 3) 7946 (compare:CC (match_dup 0) 7947 (const_int 0)))] 7948 "") 7949 7950(define_expand "anddi3" 7951 [(parallel 7952 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7953 (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 7954 (match_operand:DI 2 "reg_or_cint_operand" ""))) 7955 (clobber (match_scratch:CC 3 ""))])] 7956 "" 7957{ 7958 if (!TARGET_POWERPC64) 7959 { 7960 rtx cc = gen_rtx_SCRATCH (CCmode); 7961 rs6000_split_logical (operands, AND, false, false, false, cc); 7962 DONE; 7963 } 7964 else if (!and64_2_operand (operands[2], DImode)) 7965 operands[2] = force_reg (DImode, operands[2]); 7966}) 7967 7968(define_insn "anddi3_mc" 7969 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r") 7970 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r") 7971 (match_operand:DI 2 "and64_2_operand" "?r,S,T,K,J,t"))) 7972 (clobber (match_scratch:CC 3 "=X,X,X,x,x,X"))] 7973 "TARGET_POWERPC64 && rs6000_gen_cell_microcode" 7974 "@ 7975 and %0,%1,%2 7976 rldic%B2 %0,%1,0,%S2 7977 rlwinm %0,%1,0,%m2,%M2 7978 andi. %0,%1,%b2 7979 andis. %0,%1,%u2 7980 #" 7981 [(set_attr "type" "*,*,*,fast_compare,fast_compare,*") 7982 (set_attr "length" "4,4,4,4,4,8")]) 7983 7984(define_insn "anddi3_nomc" 7985 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r") 7986 (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r") 7987 (match_operand:DI 2 "and64_2_operand" "?r,S,T,t"))) 7988 (clobber (match_scratch:CC 3 "=X,X,X,X"))] 7989 "TARGET_POWERPC64 && !rs6000_gen_cell_microcode" 7990 "@ 7991 and %0,%1,%2 7992 rldic%B2 %0,%1,0,%S2 7993 rlwinm %0,%1,0,%m2,%M2 7994 #" 7995 [(set_attr "length" "4,4,4,8")]) 7996 7997(define_split 7998 [(set (match_operand:DI 0 "gpc_reg_operand" "") 7999 (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 8000 (match_operand:DI 2 "mask64_2_operand" ""))) 8001 (clobber (match_scratch:CC 3 ""))] 8002 "TARGET_POWERPC64 8003 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) 8004 && !mask_operand (operands[2], DImode) 8005 && !mask64_operand (operands[2], DImode)" 8006 [(set (match_dup 0) 8007 (and:DI (rotate:DI (match_dup 1) 8008 (match_dup 4)) 8009 (match_dup 5))) 8010 (set (match_dup 0) 8011 (and:DI (rotate:DI (match_dup 0) 8012 (match_dup 6)) 8013 (match_dup 7)))] 8014{ 8015 build_mask64_2_operands (operands[2], &operands[4]); 8016}) 8017 8018(define_insn "*anddi3_internal2_mc" 8019 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") 8020 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") 8021 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) 8022 (const_int 0))) 8023 (clobber (match_scratch:DI 3 "=r,r,r,r,r,r,r,r,r,r,r,r")) 8024 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] 8025 "TARGET_64BIT && rs6000_gen_cell_microcode" 8026 "@ 8027 and. %3,%1,%2 8028 rldic%B2. %3,%1,0,%S2 8029 rlwinm. %3,%1,0,%m2,%M2 8030 andi. %3,%1,%b2 8031 andis. %3,%1,%u2 8032 # 8033 # 8034 # 8035 # 8036 # 8037 # 8038 #" 8039 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\ 8040 fast_compare,compare,compare,compare,compare,compare,\ 8041 compare,compare") 8042 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) 8043 8044(define_split 8045 [(set (match_operand:CC 0 "cc_reg_operand" "") 8046 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 8047 (match_operand:DI 2 "mask64_2_operand" "")) 8048 (const_int 0))) 8049 (clobber (match_scratch:DI 3 "")) 8050 (clobber (match_scratch:CC 4 ""))] 8051 "TARGET_64BIT && reload_completed 8052 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) 8053 && !mask_operand (operands[2], DImode) 8054 && !mask64_operand (operands[2], DImode)" 8055 [(set (match_dup 3) 8056 (and:DI (rotate:DI (match_dup 1) 8057 (match_dup 5)) 8058 (match_dup 6))) 8059 (parallel [(set (match_dup 0) 8060 (compare:CC (and:DI (rotate:DI (match_dup 3) 8061 (match_dup 7)) 8062 (match_dup 8)) 8063 (const_int 0))) 8064 (clobber (match_dup 3))])] 8065 " 8066{ 8067 build_mask64_2_operands (operands[2], &operands[5]); 8068}") 8069 8070(define_insn "*anddi3_internal3_mc" 8071 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,x,x,x,?y,?y,?y,??y,??y,?y") 8072 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r,r,r") 8073 (match_operand:DI 2 "and64_2_operand" "r,S,T,K,J,t,r,S,T,K,J,t")) 8074 (const_int 0))) 8075 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r,r,r,r,r,r,r,r,r,r") 8076 (and:DI (match_dup 1) (match_dup 2))) 8077 (clobber (match_scratch:CC 4 "=X,X,X,X,X,X,X,X,X,x,x,X"))] 8078 "TARGET_64BIT && rs6000_gen_cell_microcode" 8079 "@ 8080 and. %0,%1,%2 8081 rldic%B2. %0,%1,0,%S2 8082 rlwinm. %0,%1,0,%m2,%M2 8083 andi. %0,%1,%b2 8084 andis. %0,%1,%u2 8085 # 8086 # 8087 # 8088 # 8089 # 8090 # 8091 #" 8092 [(set_attr "type" "fast_compare,compare,delayed_compare,fast_compare,\ 8093 fast_compare,compare,compare,compare,compare,compare,\ 8094 compare,compare") 8095 (set_attr "length" "4,4,4,4,4,8,8,8,8,8,8,12")]) 8096 8097(define_split 8098 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 8099 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 8100 (match_operand:DI 2 "and64_2_operand" "")) 8101 (const_int 0))) 8102 (set (match_operand:DI 0 "gpc_reg_operand" "") 8103 (and:DI (match_dup 1) (match_dup 2))) 8104 (clobber (match_scratch:CC 4 ""))] 8105 "TARGET_64BIT && reload_completed" 8106 [(parallel [(set (match_dup 0) 8107 (and:DI (match_dup 1) (match_dup 2))) 8108 (clobber (match_dup 4))]) 8109 (set (match_dup 3) 8110 (compare:CC (match_dup 0) 8111 (const_int 0)))] 8112 "") 8113 8114(define_split 8115 [(set (match_operand:CC 3 "cc_reg_operand" "") 8116 (compare:CC (and:DI (match_operand:DI 1 "gpc_reg_operand" "") 8117 (match_operand:DI 2 "mask64_2_operand" "")) 8118 (const_int 0))) 8119 (set (match_operand:DI 0 "gpc_reg_operand" "") 8120 (and:DI (match_dup 1) (match_dup 2))) 8121 (clobber (match_scratch:CC 4 ""))] 8122 "TARGET_64BIT && reload_completed 8123 && (fixed_regs[CR0_REGNO] || !logical_operand (operands[2], DImode)) 8124 && !mask_operand (operands[2], DImode) 8125 && !mask64_operand (operands[2], DImode)" 8126 [(set (match_dup 0) 8127 (and:DI (rotate:DI (match_dup 1) 8128 (match_dup 5)) 8129 (match_dup 6))) 8130 (parallel [(set (match_dup 3) 8131 (compare:CC (and:DI (rotate:DI (match_dup 0) 8132 (match_dup 7)) 8133 (match_dup 8)) 8134 (const_int 0))) 8135 (set (match_dup 0) 8136 (and:DI (rotate:DI (match_dup 0) 8137 (match_dup 7)) 8138 (match_dup 8)))])] 8139 " 8140{ 8141 build_mask64_2_operands (operands[2], &operands[5]); 8142}") 8143 8144(define_expand "iordi3" 8145 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8146 (ior:DI (match_operand:DI 1 "gpc_reg_operand" "") 8147 (match_operand:DI 2 "reg_or_cint_operand" "")))] 8148 "" 8149{ 8150 if (!TARGET_POWERPC64) 8151 { 8152 rs6000_split_logical (operands, IOR, false, false, false, NULL_RTX); 8153 DONE; 8154 } 8155 else if (!reg_or_logical_cint_operand (operands[2], DImode)) 8156 operands[2] = force_reg (DImode, operands[2]); 8157 else if (non_logical_cint_operand (operands[2], DImode)) 8158 { 8159 HOST_WIDE_INT value; 8160 rtx tmp = ((!can_create_pseudo_p () 8161 || rtx_equal_p (operands[0], operands[1])) 8162 ? operands[0] : gen_reg_rtx (DImode)); 8163 8164 if (GET_CODE (operands[2]) == CONST_INT) 8165 { 8166 value = INTVAL (operands[2]); 8167 emit_insn (gen_iordi3 (tmp, operands[1], 8168 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 8169 } 8170 else 8171 { 8172 value = CONST_DOUBLE_LOW (operands[2]); 8173 emit_insn (gen_iordi3 (tmp, operands[1], 8174 immed_double_const (value 8175 & (~ (HOST_WIDE_INT) 0xffff), 8176 0, DImode))); 8177 } 8178 8179 emit_insn (gen_iordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 8180 DONE; 8181 } 8182}) 8183 8184(define_expand "xordi3" 8185 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8186 (xor:DI (match_operand:DI 1 "gpc_reg_operand" "") 8187 (match_operand:DI 2 "reg_or_cint_operand" "")))] 8188 "" 8189{ 8190 if (!TARGET_POWERPC64) 8191 { 8192 rs6000_split_logical (operands, XOR, false, false, false, NULL_RTX); 8193 DONE; 8194 } 8195 else if (!reg_or_logical_cint_operand (operands[2], DImode)) 8196 operands[2] = force_reg (DImode, operands[2]); 8197 if (non_logical_cint_operand (operands[2], DImode)) 8198 { 8199 HOST_WIDE_INT value; 8200 rtx tmp = ((!can_create_pseudo_p () 8201 || rtx_equal_p (operands[0], operands[1])) 8202 ? operands[0] : gen_reg_rtx (DImode)); 8203 8204 if (GET_CODE (operands[2]) == CONST_INT) 8205 { 8206 value = INTVAL (operands[2]); 8207 emit_insn (gen_xordi3 (tmp, operands[1], 8208 GEN_INT (value & (~ (HOST_WIDE_INT) 0xffff)))); 8209 } 8210 else 8211 { 8212 value = CONST_DOUBLE_LOW (operands[2]); 8213 emit_insn (gen_xordi3 (tmp, operands[1], 8214 immed_double_const (value 8215 & (~ (HOST_WIDE_INT) 0xffff), 8216 0, DImode))); 8217 } 8218 8219 emit_insn (gen_xordi3 (operands[0], tmp, GEN_INT (value & 0xffff))); 8220 DONE; 8221 } 8222}) 8223 8224(define_insn "*booldi3_internal1" 8225 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r,r") 8226 (match_operator:DI 3 "boolean_or_operator" 8227 [(match_operand:DI 1 "gpc_reg_operand" "%r,r,r") 8228 (match_operand:DI 2 "logical_operand" "r,K,JF")]))] 8229 "TARGET_POWERPC64" 8230 "@ 8231 %q3 %0,%1,%2 8232 %q3i %0,%1,%b2 8233 %q3is %0,%1,%u2") 8234 8235(define_insn "*booldi3_internal2" 8236 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 8237 (compare:CC (match_operator:DI 4 "boolean_or_operator" 8238 [(match_operand:DI 1 "gpc_reg_operand" "%r,r") 8239 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 8240 (const_int 0))) 8241 (clobber (match_scratch:DI 3 "=r,r"))] 8242 "TARGET_64BIT" 8243 "@ 8244 %q4. %3,%1,%2 8245 #" 8246 [(set_attr "type" "fast_compare,compare") 8247 (set_attr "length" "4,8")]) 8248 8249(define_split 8250 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 8251 (compare:CC (match_operator:DI 4 "boolean_operator" 8252 [(match_operand:DI 1 "gpc_reg_operand" "") 8253 (match_operand:DI 2 "gpc_reg_operand" "")]) 8254 (const_int 0))) 8255 (clobber (match_scratch:DI 3 ""))] 8256 "TARGET_POWERPC64 && reload_completed" 8257 [(set (match_dup 3) (match_dup 4)) 8258 (set (match_dup 0) 8259 (compare:CC (match_dup 3) 8260 (const_int 0)))] 8261 "") 8262 8263(define_insn "*booldi3_internal3" 8264 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 8265 (compare:CC (match_operator:DI 4 "boolean_or_operator" 8266 [(match_operand:DI 1 "gpc_reg_operand" "%r,r") 8267 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 8268 (const_int 0))) 8269 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 8270 (match_dup 4))] 8271 "TARGET_64BIT" 8272 "@ 8273 %q4. %0,%1,%2 8274 #" 8275 [(set_attr "type" "fast_compare,compare") 8276 (set_attr "length" "4,8")]) 8277 8278(define_split 8279 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 8280 (compare:CC (match_operator:DI 4 "boolean_operator" 8281 [(match_operand:DI 1 "gpc_reg_operand" "") 8282 (match_operand:DI 2 "gpc_reg_operand" "")]) 8283 (const_int 0))) 8284 (set (match_operand:DI 0 "gpc_reg_operand" "") 8285 (match_dup 4))] 8286 "TARGET_POWERPC64 && reload_completed" 8287 [(set (match_dup 0) (match_dup 4)) 8288 (set (match_dup 3) 8289 (compare:CC (match_dup 0) 8290 (const_int 0)))] 8291 "") 8292 8293;; Split a logical operation that we can't do in one insn into two insns, 8294;; each of which does one 16-bit part. This is used by combine. 8295 8296(define_split 8297 [(set (match_operand:DI 0 "gpc_reg_operand" "") 8298 (match_operator:DI 3 "boolean_or_operator" 8299 [(match_operand:DI 1 "gpc_reg_operand" "") 8300 (match_operand:DI 2 "non_logical_cint_operand" "")]))] 8301 "TARGET_POWERPC64" 8302 [(set (match_dup 0) (match_dup 4)) 8303 (set (match_dup 0) (match_dup 5))] 8304" 8305{ 8306 rtx i3,i4; 8307 8308 if (GET_CODE (operands[2]) == CONST_DOUBLE) 8309 { 8310 HOST_WIDE_INT value = CONST_DOUBLE_LOW (operands[2]); 8311 i3 = immed_double_const (value & (~ (HOST_WIDE_INT) 0xffff), 8312 0, DImode); 8313 i4 = GEN_INT (value & 0xffff); 8314 } 8315 else 8316 { 8317 i3 = GEN_INT (INTVAL (operands[2]) 8318 & (~ (HOST_WIDE_INT) 0xffff)); 8319 i4 = GEN_INT (INTVAL (operands[2]) & 0xffff); 8320 } 8321 operands[4] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, 8322 operands[1], i3); 8323 operands[5] = gen_rtx_fmt_ee (GET_CODE (operands[3]), DImode, 8324 operands[0], i4); 8325}") 8326 8327(define_insn "*boolcdi3_internal1" 8328 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 8329 (match_operator:DI 3 "boolean_operator" 8330 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) 8331 (match_operand:DI 2 "gpc_reg_operand" "r")]))] 8332 "TARGET_POWERPC64" 8333 "%q3 %0,%2,%1") 8334 8335(define_insn "*boolcdi3_internal2" 8336 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 8337 (compare:CC (match_operator:DI 4 "boolean_operator" 8338 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 8339 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 8340 (const_int 0))) 8341 (clobber (match_scratch:DI 3 "=r,r"))] 8342 "TARGET_64BIT" 8343 "@ 8344 %q4. %3,%2,%1 8345 #" 8346 [(set_attr "type" "fast_compare,compare") 8347 (set_attr "length" "4,8")]) 8348 8349(define_split 8350 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 8351 (compare:CC (match_operator:DI 4 "boolean_operator" 8352 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 8353 (match_operand:DI 2 "gpc_reg_operand" "")]) 8354 (const_int 0))) 8355 (clobber (match_scratch:DI 3 ""))] 8356 "TARGET_POWERPC64 && reload_completed" 8357 [(set (match_dup 3) (match_dup 4)) 8358 (set (match_dup 0) 8359 (compare:CC (match_dup 3) 8360 (const_int 0)))] 8361 "") 8362 8363(define_insn "*boolcdi3_internal3" 8364 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 8365 (compare:CC (match_operator:DI 4 "boolean_operator" 8366 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) 8367 (match_operand:DI 2 "gpc_reg_operand" "r,r")]) 8368 (const_int 0))) 8369 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 8370 (match_dup 4))] 8371 "TARGET_64BIT" 8372 "@ 8373 %q4. %0,%2,%1 8374 #" 8375 [(set_attr "type" "fast_compare,compare") 8376 (set_attr "length" "4,8")]) 8377 8378(define_split 8379 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 8380 (compare:CC (match_operator:DI 4 "boolean_operator" 8381 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 8382 (match_operand:DI 2 "gpc_reg_operand" "")]) 8383 (const_int 0))) 8384 (set (match_operand:DI 0 "gpc_reg_operand" "") 8385 (match_dup 4))] 8386 "TARGET_POWERPC64 && reload_completed" 8387 [(set (match_dup 0) (match_dup 4)) 8388 (set (match_dup 3) 8389 (compare:CC (match_dup 0) 8390 (const_int 0)))] 8391 "") 8392 8393(define_insn "*boolccdi3_internal1" 8394 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 8395 (match_operator:DI 3 "boolean_operator" 8396 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r")) 8397 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r"))]))] 8398 "TARGET_POWERPC64" 8399 "%q3 %0,%1,%2") 8400 8401(define_insn "*boolccdi3_internal2" 8402 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 8403 (compare:CC (match_operator:DI 4 "boolean_operator" 8404 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "r,r")) 8405 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) 8406 (const_int 0))) 8407 (clobber (match_scratch:DI 3 "=r,r"))] 8408 "TARGET_64BIT" 8409 "@ 8410 %q4. %3,%1,%2 8411 #" 8412 [(set_attr "type" "fast_compare,compare") 8413 (set_attr "length" "4,8")]) 8414 8415(define_split 8416 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 8417 (compare:CC (match_operator:DI 4 "boolean_operator" 8418 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 8419 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) 8420 (const_int 0))) 8421 (clobber (match_scratch:DI 3 ""))] 8422 "TARGET_POWERPC64 && reload_completed" 8423 [(set (match_dup 3) (match_dup 4)) 8424 (set (match_dup 0) 8425 (compare:CC (match_dup 3) 8426 (const_int 0)))] 8427 "") 8428 8429(define_insn "*boolccdi3_internal3" 8430 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 8431 (compare:CC (match_operator:DI 4 "boolean_operator" 8432 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "%r,r")) 8433 (not:DI (match_operand:DI 2 "gpc_reg_operand" "r,r"))]) 8434 (const_int 0))) 8435 (set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 8436 (match_dup 4))] 8437 "TARGET_64BIT" 8438 "@ 8439 %q4. %0,%1,%2 8440 #" 8441 [(set_attr "type" "fast_compare,compare") 8442 (set_attr "length" "4,8")]) 8443 8444(define_split 8445 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 8446 (compare:CC (match_operator:DI 4 "boolean_operator" 8447 [(not:DI (match_operand:DI 1 "gpc_reg_operand" "")) 8448 (not:DI (match_operand:DI 2 "gpc_reg_operand" ""))]) 8449 (const_int 0))) 8450 (set (match_operand:DI 0 "gpc_reg_operand" "") 8451 (match_dup 4))] 8452 "TARGET_POWERPC64 && reload_completed" 8453 [(set (match_dup 0) (match_dup 4)) 8454 (set (match_dup 3) 8455 (compare:CC (match_dup 0) 8456 (const_int 0)))] 8457 "") 8458 8459;; Eqv operation. 8460(define_insn "*eqv<mode>3" 8461 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 8462 (not:GPR 8463 (xor:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") 8464 (match_operand:GPR 2 "gpc_reg_operand" "r"))))] 8465 "" 8466 "eqv %0,%1,%2" 8467 [(set_attr "type" "integer") 8468 (set_attr "length" "4")]) 8469 8470 8471;; 128-bit logical operations expanders 8472 8473(define_expand "and<mode>3" 8474 [(parallel [(set (match_operand:BOOL_128 0 "vlogical_operand" "") 8475 (and:BOOL_128 8476 (match_operand:BOOL_128 1 "vlogical_operand" "") 8477 (match_operand:BOOL_128 2 "vlogical_operand" ""))) 8478 (clobber (match_scratch:CC 3 ""))])] 8479 "" 8480 "") 8481 8482(define_expand "ior<mode>3" 8483 [(set (match_operand:BOOL_128 0 "vlogical_operand" "") 8484 (ior:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") 8485 (match_operand:BOOL_128 2 "vlogical_operand" "")))] 8486 "" 8487 "") 8488 8489(define_expand "xor<mode>3" 8490 [(set (match_operand:BOOL_128 0 "vlogical_operand" "") 8491 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") 8492 (match_operand:BOOL_128 2 "vlogical_operand" "")))] 8493 "" 8494 "") 8495 8496(define_expand "one_cmpl<mode>2" 8497 [(set (match_operand:BOOL_128 0 "vlogical_operand" "") 8498 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")))] 8499 "" 8500 "") 8501 8502(define_expand "nor<mode>3" 8503 [(set (match_operand:BOOL_128 0 "vlogical_operand" "") 8504 (and:BOOL_128 8505 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) 8506 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] 8507 "" 8508 "") 8509 8510(define_expand "andc<mode>3" 8511 [(set (match_operand:BOOL_128 0 "vlogical_operand" "") 8512 (and:BOOL_128 8513 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) 8514 (match_operand:BOOL_128 1 "vlogical_operand" "")))] 8515 "" 8516 "") 8517 8518;; Power8 vector logical instructions. 8519(define_expand "eqv<mode>3" 8520 [(set (match_operand:BOOL_128 0 "vlogical_operand" "") 8521 (not:BOOL_128 8522 (xor:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "") 8523 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] 8524 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" 8525 "") 8526 8527;; Rewrite nand into canonical form 8528(define_expand "nand<mode>3" 8529 [(set (match_operand:BOOL_128 0 "vlogical_operand" "") 8530 (ior:BOOL_128 8531 (not:BOOL_128 (match_operand:BOOL_128 1 "vlogical_operand" "")) 8532 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" ""))))] 8533 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" 8534 "") 8535 8536;; The canonical form is to have the negated element first, so we need to 8537;; reverse arguments. 8538(define_expand "orc<mode>3" 8539 [(set (match_operand:BOOL_128 0 "vlogical_operand" "") 8540 (ior:BOOL_128 8541 (not:BOOL_128 (match_operand:BOOL_128 2 "vlogical_operand" "")) 8542 (match_operand:BOOL_128 1 "vlogical_operand" "")))] 8543 "<MODE>mode == TImode || <MODE>mode == PTImode || TARGET_P8_VECTOR" 8544 "") 8545 8546;; 128-bit logical operations insns and split operations 8547(define_insn_and_split "*and<mode>3_internal" 8548 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>") 8549 (and:BOOL_128 8550 (match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>") 8551 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))) 8552 (clobber (match_scratch:CC 3 "<BOOL_REGS_AND_CR0>"))] 8553 "" 8554{ 8555 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode)) 8556 return "xxland %x0,%x1,%x2"; 8557 8558 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode)) 8559 return "vand %0,%1,%2"; 8560 8561 return "#"; 8562} 8563 "reload_completed && int_reg_operand (operands[0], <MODE>mode)" 8564 [(const_int 0)] 8565{ 8566 rs6000_split_logical (operands, AND, false, false, false, operands[3]); 8567 DONE; 8568} 8569 [(set (attr "type") 8570 (if_then_else 8571 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8572 (const_string "vecsimple") 8573 (const_string "integer"))) 8574 (set (attr "length") 8575 (if_then_else 8576 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8577 (const_string "4") 8578 (if_then_else 8579 (match_test "TARGET_POWERPC64") 8580 (const_string "8") 8581 (const_string "16"))))]) 8582 8583;; 128-bit IOR/XOR 8584(define_insn_and_split "*bool<mode>3_internal" 8585 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>") 8586 (match_operator:BOOL_128 3 "boolean_or_operator" 8587 [(match_operand:BOOL_128 1 "vlogical_operand" "%<BOOL_REGS_OP1>") 8588 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")]))] 8589 "" 8590{ 8591 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode)) 8592 return "xxl%q3 %x0,%x1,%x2"; 8593 8594 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode)) 8595 return "v%q3 %0,%1,%2"; 8596 8597 return "#"; 8598} 8599 "reload_completed && int_reg_operand (operands[0], <MODE>mode)" 8600 [(const_int 0)] 8601{ 8602 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, false, 8603 NULL_RTX); 8604 DONE; 8605} 8606 [(set (attr "type") 8607 (if_then_else 8608 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8609 (const_string "vecsimple") 8610 (const_string "integer"))) 8611 (set (attr "length") 8612 (if_then_else 8613 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8614 (const_string "4") 8615 (if_then_else 8616 (match_test "TARGET_POWERPC64") 8617 (const_string "8") 8618 (const_string "16"))))]) 8619 8620;; 128-bit ANDC/ORC 8621(define_insn_and_split "*boolc<mode>3_internal1" 8622 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>") 8623 (match_operator:BOOL_128 3 "boolean_operator" 8624 [(not:BOOL_128 8625 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>")) 8626 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")]))] 8627 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)" 8628{ 8629 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode)) 8630 return "xxl%q3 %x0,%x1,%x2"; 8631 8632 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode)) 8633 return "v%q3 %0,%1,%2"; 8634 8635 return "#"; 8636} 8637 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)) 8638 && reload_completed && int_reg_operand (operands[0], <MODE>mode)" 8639 [(const_int 0)] 8640{ 8641 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true, 8642 NULL_RTX); 8643 DONE; 8644} 8645 [(set (attr "type") 8646 (if_then_else 8647 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8648 (const_string "vecsimple") 8649 (const_string "integer"))) 8650 (set (attr "length") 8651 (if_then_else 8652 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8653 (const_string "4") 8654 (if_then_else 8655 (match_test "TARGET_POWERPC64") 8656 (const_string "8") 8657 (const_string "16"))))]) 8658 8659(define_insn_and_split "*boolc<mode>3_internal2" 8660 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r") 8661 (match_operator:TI2 3 "boolean_operator" 8662 [(not:TI2 8663 (match_operand:TI2 2 "int_reg_operand" "r,0,r")) 8664 (match_operand:TI2 1 "int_reg_operand" "r,r,0")]))] 8665 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" 8666 "#" 8667 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" 8668 [(const_int 0)] 8669{ 8670 rs6000_split_logical (operands, GET_CODE (operands[3]), false, false, true, 8671 NULL_RTX); 8672 DONE; 8673} 8674 [(set_attr "type" "integer") 8675 (set (attr "length") 8676 (if_then_else 8677 (match_test "TARGET_POWERPC64") 8678 (const_string "8") 8679 (const_string "16")))]) 8680 8681;; 128-bit NAND/NOR 8682(define_insn_and_split "*boolcc<mode>3_internal1" 8683 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>") 8684 (match_operator:BOOL_128 3 "boolean_operator" 8685 [(not:BOOL_128 8686 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>")) 8687 (not:BOOL_128 8688 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))]))] 8689 "TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)" 8690{ 8691 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode)) 8692 return "xxl%q3 %x0,%x1,%x2"; 8693 8694 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode)) 8695 return "v%q3 %0,%1,%2"; 8696 8697 return "#"; 8698} 8699 "(TARGET_P8_VECTOR || (GET_CODE (operands[3]) == AND)) 8700 && reload_completed && int_reg_operand (operands[0], <MODE>mode)" 8701 [(const_int 0)] 8702{ 8703 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true, 8704 NULL_RTX); 8705 DONE; 8706} 8707 [(set (attr "type") 8708 (if_then_else 8709 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8710 (const_string "vecsimple") 8711 (const_string "integer"))) 8712 (set (attr "length") 8713 (if_then_else 8714 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8715 (const_string "4") 8716 (if_then_else 8717 (match_test "TARGET_POWERPC64") 8718 (const_string "8") 8719 (const_string "16"))))]) 8720 8721(define_insn_and_split "*boolcc<mode>3_internal2" 8722 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r") 8723 (match_operator:TI2 3 "boolean_operator" 8724 [(not:TI2 8725 (match_operand:TI2 1 "int_reg_operand" "r,0,r")) 8726 (not:TI2 8727 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))]))] 8728 "!TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" 8729 "#" 8730 "reload_completed && !TARGET_P8_VECTOR && (GET_CODE (operands[3]) != AND)" 8731 [(const_int 0)] 8732{ 8733 rs6000_split_logical (operands, GET_CODE (operands[3]), false, true, true, 8734 NULL_RTX); 8735 DONE; 8736} 8737 [(set_attr "type" "integer") 8738 (set (attr "length") 8739 (if_then_else 8740 (match_test "TARGET_POWERPC64") 8741 (const_string "8") 8742 (const_string "16")))]) 8743 8744 8745;; 128-bit EQV 8746(define_insn_and_split "*eqv<mode>3_internal1" 8747 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>") 8748 (not:BOOL_128 8749 (xor:BOOL_128 8750 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_OP1>") 8751 (match_operand:BOOL_128 2 "vlogical_operand" "<BOOL_REGS_OP2>"))))] 8752 "TARGET_P8_VECTOR" 8753{ 8754 if (vsx_register_operand (operands[0], <MODE>mode)) 8755 return "xxleqv %x0,%x1,%x2"; 8756 8757 return "#"; 8758} 8759 "TARGET_P8_VECTOR && reload_completed 8760 && int_reg_operand (operands[0], <MODE>mode)" 8761 [(const_int 0)] 8762{ 8763 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX); 8764 DONE; 8765} 8766 [(set (attr "type") 8767 (if_then_else 8768 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8769 (const_string "vecsimple") 8770 (const_string "integer"))) 8771 (set (attr "length") 8772 (if_then_else 8773 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8774 (const_string "4") 8775 (if_then_else 8776 (match_test "TARGET_POWERPC64") 8777 (const_string "8") 8778 (const_string "16"))))]) 8779 8780(define_insn_and_split "*eqv<mode>3_internal2" 8781 [(set (match_operand:TI2 0 "int_reg_operand" "=&r,r,r") 8782 (not:TI2 8783 (xor:TI2 8784 (match_operand:TI2 1 "int_reg_operand" "r,0,r") 8785 (match_operand:TI2 2 "int_reg_operand" "r,r,0"))))] 8786 "!TARGET_P8_VECTOR" 8787 "#" 8788 "reload_completed && !TARGET_P8_VECTOR" 8789 [(const_int 0)] 8790{ 8791 rs6000_split_logical (operands, XOR, true, false, false, NULL_RTX); 8792 DONE; 8793} 8794 [(set_attr "type" "integer") 8795 (set (attr "length") 8796 (if_then_else 8797 (match_test "TARGET_POWERPC64") 8798 (const_string "8") 8799 (const_string "16")))]) 8800 8801;; 128-bit one's complement 8802(define_insn_and_split "*one_cmpl<mode>3_internal" 8803 [(set (match_operand:BOOL_128 0 "vlogical_operand" "=<BOOL_REGS_OUTPUT>") 8804 (not:BOOL_128 8805 (match_operand:BOOL_128 1 "vlogical_operand" "<BOOL_REGS_UNARY>")))] 8806 "" 8807{ 8808 if (TARGET_VSX && vsx_register_operand (operands[0], <MODE>mode)) 8809 return "xxlnor %x0,%x1,%x1"; 8810 8811 if (TARGET_ALTIVEC && altivec_register_operand (operands[0], <MODE>mode)) 8812 return "vnor %0,%1,%1"; 8813 8814 return "#"; 8815} 8816 "reload_completed && int_reg_operand (operands[0], <MODE>mode)" 8817 [(const_int 0)] 8818{ 8819 rs6000_split_logical (operands, NOT, false, false, false, NULL_RTX); 8820 DONE; 8821} 8822 [(set (attr "type") 8823 (if_then_else 8824 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8825 (const_string "vecsimple") 8826 (const_string "integer"))) 8827 (set (attr "length") 8828 (if_then_else 8829 (match_test "vsx_register_operand (operands[0], <MODE>mode)") 8830 (const_string "4") 8831 (if_then_else 8832 (match_test "TARGET_POWERPC64") 8833 (const_string "8") 8834 (const_string "16"))))]) 8835 8836 8837;; Now define ways of moving data around. 8838 8839;; Set up a register with a value from the GOT table 8840 8841(define_expand "movsi_got" 8842 [(set (match_operand:SI 0 "gpc_reg_operand" "") 8843 (unspec:SI [(match_operand:SI 1 "got_operand" "") 8844 (match_dup 2)] UNSPEC_MOVSI_GOT))] 8845 "DEFAULT_ABI == ABI_V4 && flag_pic == 1" 8846 " 8847{ 8848 if (GET_CODE (operands[1]) == CONST) 8849 { 8850 rtx offset = const0_rtx; 8851 HOST_WIDE_INT value; 8852 8853 operands[1] = eliminate_constant_term (XEXP (operands[1], 0), &offset); 8854 value = INTVAL (offset); 8855 if (value != 0) 8856 { 8857 rtx tmp = (!can_create_pseudo_p () 8858 ? operands[0] 8859 : gen_reg_rtx (Pmode)); 8860 emit_insn (gen_movsi_got (tmp, operands[1])); 8861 emit_insn (gen_addsi3 (operands[0], tmp, offset)); 8862 DONE; 8863 } 8864 } 8865 8866 operands[2] = rs6000_got_register (operands[1]); 8867}") 8868 8869(define_insn "*movsi_got_internal" 8870 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 8871 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") 8872 (match_operand:SI 2 "gpc_reg_operand" "b")] 8873 UNSPEC_MOVSI_GOT))] 8874 "DEFAULT_ABI == ABI_V4 && flag_pic == 1" 8875 "lwz %0,%a1@got(%2)" 8876 [(set_attr "type" "load")]) 8877 8878;; Used by sched, shorten_branches and final when the GOT pseudo reg 8879;; didn't get allocated to a hard register. 8880(define_split 8881 [(set (match_operand:SI 0 "gpc_reg_operand" "") 8882 (unspec:SI [(match_operand:SI 1 "got_no_const_operand" "") 8883 (match_operand:SI 2 "memory_operand" "")] 8884 UNSPEC_MOVSI_GOT))] 8885 "DEFAULT_ABI == ABI_V4 8886 && flag_pic == 1 8887 && (reload_in_progress || reload_completed)" 8888 [(set (match_dup 0) (match_dup 2)) 8889 (set (match_dup 0) (unspec:SI [(match_dup 1)(match_dup 0)] 8890 UNSPEC_MOVSI_GOT))] 8891 "") 8892 8893;; For SI, we special-case integers that can't be loaded in one insn. We 8894;; do the load 16-bits at a time. We could do this by loading from memory, 8895;; and this is even supposed to be faster, but it is simpler not to get 8896;; integers in the TOC. 8897(define_insn "movsi_low" 8898 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 8899 (mem:SI (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") 8900 (match_operand 2 "" ""))))] 8901 "TARGET_MACHO && ! TARGET_64BIT" 8902 "lwz %0,lo16(%2)(%1)" 8903 [(set_attr "type" "load") 8904 (set_attr "length" "4")]) 8905 8906(define_insn "*movsi_internal1" 8907 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h") 8908 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0"))] 8909 "!TARGET_SINGLE_FPU && 8910 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))" 8911 "@ 8912 mr %0,%1 8913 la %0,%a1 8914 lwz%U1%X1 %0,%1 8915 stw%U0%X0 %1,%0 8916 li %0,%1 8917 lis %0,%v1 8918 # 8919 mf%1 %0 8920 mt%0 %1 8921 mt%0 %1 8922 nop" 8923 [(set_attr_alternative "type" 8924 [(const_string "*") 8925 (const_string "*") 8926 (if_then_else 8927 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 8928 (const_string "load_ux") 8929 (if_then_else 8930 (match_test "update_address_mem (operands[1], VOIDmode)") 8931 (const_string "load_u") 8932 (const_string "load"))) 8933 (if_then_else 8934 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 8935 (const_string "store_ux") 8936 (if_then_else 8937 (match_test "update_address_mem (operands[0], VOIDmode)") 8938 (const_string "store_u") 8939 (const_string "store"))) 8940 (const_string "*") 8941 (const_string "*") 8942 (const_string "*") 8943 (const_string "mfjmpr") 8944 (const_string "mtjmpr") 8945 (const_string "*") 8946 (const_string "*")]) 8947 8948 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4")]) 8949 8950(define_insn "*movsi_internal1_single" 8951 [(set (match_operand:SI 0 "rs6000_nonimmediate_operand" "=r,r,r,m,r,r,r,r,*c*l,*h,*h,m,*f") 8952 (match_operand:SI 1 "input_operand" "r,U,m,r,I,L,n,*h,r,r,0,f,m"))] 8953 "TARGET_SINGLE_FPU && 8954 (gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode))" 8955 "@ 8956 mr %0,%1 8957 la %0,%a1 8958 lwz%U1%X1 %0,%1 8959 stw%U0%X0 %1,%0 8960 li %0,%1 8961 lis %0,%v1 8962 # 8963 mf%1 %0 8964 mt%0 %1 8965 mt%0 %1 8966 nop 8967 stfs%U0%X0 %1,%0 8968 lfs%U1%X1 %0,%1" 8969 [(set_attr_alternative "type" 8970 [(const_string "*") 8971 (const_string "*") 8972 (if_then_else 8973 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 8974 (const_string "load_ux") 8975 (if_then_else 8976 (match_test "update_address_mem (operands[1], VOIDmode)") 8977 (const_string "load_u") 8978 (const_string "load"))) 8979 (if_then_else 8980 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 8981 (const_string "store_ux") 8982 (if_then_else 8983 (match_test "update_address_mem (operands[0], VOIDmode)") 8984 (const_string "store_u") 8985 (const_string "store"))) 8986 (const_string "*") 8987 (const_string "*") 8988 (const_string "*") 8989 (const_string "mfjmpr") 8990 (const_string "mtjmpr") 8991 (const_string "*") 8992 (const_string "*") 8993 (if_then_else 8994 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 8995 (const_string "fpstore_ux") 8996 (if_then_else 8997 (match_test "update_address_mem (operands[0], VOIDmode)") 8998 (const_string "fpstore_u") 8999 (const_string "fpstore"))) 9000 (if_then_else 9001 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9002 (const_string "fpload_ux") 9003 (if_then_else 9004 (match_test "update_address_mem (operands[1], VOIDmode)") 9005 (const_string "fpload_u") 9006 (const_string "fpload")))]) 9007 (set_attr "length" "4,4,4,4,4,4,8,4,4,4,4,4,4")]) 9008 9009;; Split a load of a large constant into the appropriate two-insn 9010;; sequence. 9011 9012(define_split 9013 [(set (match_operand:SI 0 "gpc_reg_operand" "") 9014 (match_operand:SI 1 "const_int_operand" ""))] 9015 "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 9016 && (INTVAL (operands[1]) & 0xffff) != 0" 9017 [(set (match_dup 0) 9018 (match_dup 2)) 9019 (set (match_dup 0) 9020 (ior:SI (match_dup 0) 9021 (match_dup 3)))] 9022 " 9023{ rtx tem = rs6000_emit_set_const (operands[0], SImode, operands[1], 2); 9024 9025 if (tem == operands[0]) 9026 DONE; 9027 else 9028 FAIL; 9029}") 9030 9031(define_insn "*mov<mode>_internal2" 9032 [(set (match_operand:CC 2 "cc_reg_operand" "=y,x,?y") 9033 (compare:CC (match_operand:P 1 "gpc_reg_operand" "0,r,r") 9034 (const_int 0))) 9035 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r") (match_dup 1))] 9036 "" 9037 "@ 9038 cmp<wd>i %2,%0,0 9039 mr. %0,%1 9040 #" 9041 [(set_attr "type" "cmp,fast_compare,cmp") 9042 (set_attr "length" "4,4,8")]) 9043 9044(define_split 9045 [(set (match_operand:CC 2 "cc_reg_not_micro_cr0_operand" "") 9046 (compare:CC (match_operand:P 1 "gpc_reg_operand" "") 9047 (const_int 0))) 9048 (set (match_operand:P 0 "gpc_reg_operand" "") (match_dup 1))] 9049 "reload_completed" 9050 [(set (match_dup 0) (match_dup 1)) 9051 (set (match_dup 2) 9052 (compare:CC (match_dup 0) 9053 (const_int 0)))] 9054 "") 9055 9056(define_insn "*movhi_internal" 9057 [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h") 9058 (match_operand:HI 1 "input_operand" "r,m,r,i,*h,r,0"))] 9059 "gpc_reg_operand (operands[0], HImode) 9060 || gpc_reg_operand (operands[1], HImode)" 9061 "@ 9062 mr %0,%1 9063 lhz%U1%X1 %0,%1 9064 sth%U0%X0 %1,%0 9065 li %0,%w1 9066 mf%1 %0 9067 mt%0 %1 9068 nop" 9069 [(set_attr_alternative "type" 9070 [(const_string "*") 9071 (if_then_else 9072 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9073 (const_string "load_ux") 9074 (if_then_else 9075 (match_test "update_address_mem (operands[1], VOIDmode)") 9076 (const_string "load_u") 9077 (const_string "load"))) 9078 (if_then_else 9079 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9080 (const_string "store_ux") 9081 (if_then_else 9082 (match_test "update_address_mem (operands[0], VOIDmode)") 9083 (const_string "store_u") 9084 (const_string "store"))) 9085 (const_string "*") 9086 (const_string "mfjmpr") 9087 (const_string "mtjmpr") 9088 (const_string "*")])]) 9089 9090(define_expand "mov<mode>" 9091 [(set (match_operand:INT 0 "general_operand" "") 9092 (match_operand:INT 1 "any_operand" ""))] 9093 "" 9094 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") 9095 9096(define_insn "*movqi_internal" 9097 [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,m,r,r,*c*l,*h") 9098 (match_operand:QI 1 "input_operand" "r,m,r,i,*h,r,0"))] 9099 "gpc_reg_operand (operands[0], QImode) 9100 || gpc_reg_operand (operands[1], QImode)" 9101 "@ 9102 mr %0,%1 9103 lbz%U1%X1 %0,%1 9104 stb%U0%X0 %1,%0 9105 li %0,%1 9106 mf%1 %0 9107 mt%0 %1 9108 nop" 9109 [(set_attr_alternative "type" 9110 [(const_string "*") 9111 (if_then_else 9112 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9113 (const_string "load_ux") 9114 (if_then_else 9115 (match_test "update_address_mem (operands[1], VOIDmode)") 9116 (const_string "load_u") 9117 (const_string "load"))) 9118 (if_then_else 9119 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9120 (const_string "store_ux") 9121 (if_then_else 9122 (match_test "update_address_mem (operands[0], VOIDmode)") 9123 (const_string "store_u") 9124 (const_string "store"))) 9125 (const_string "*") 9126 (const_string "mfjmpr") 9127 (const_string "mtjmpr") 9128 (const_string "*")])]) 9129 9130;; Here is how to move condition codes around. When we store CC data in 9131;; an integer register or memory, we store just the high-order 4 bits. 9132;; This lets us not shift in the most common case of CR0. 9133(define_expand "movcc" 9134 [(set (match_operand:CC 0 "nonimmediate_operand" "") 9135 (match_operand:CC 1 "nonimmediate_operand" ""))] 9136 "" 9137 "") 9138 9139(define_insn "*movcc_internal1" 9140 [(set (match_operand:CC 0 "nonimmediate_operand" "=y,x,?y,y,r,r,r,r,r,cl,r,m") 9141 (match_operand:CC 1 "general_operand" "y,r,r,O,x,y,r,I,h,r,m,r"))] 9142 "register_operand (operands[0], CCmode) 9143 || register_operand (operands[1], CCmode)" 9144 "@ 9145 mcrf %0,%1 9146 mtcrf 128,%1 9147 rlwinm %1,%1,%F0,0xffffffff\;mtcrf %R0,%1\;rlwinm %1,%1,%f0,0xffffffff 9148 crxor %0,%0,%0 9149 mfcr %0%Q1 9150 mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf0000000 9151 mr %0,%1 9152 li %0,%1 9153 mf%1 %0 9154 mt%0 %1 9155 lwz%U1%X1 %0,%1 9156 stw%U0%X0 %1,%0" 9157 [(set (attr "type") 9158 (cond [(eq_attr "alternative" "0,3") 9159 (const_string "cr_logical") 9160 (eq_attr "alternative" "1,2") 9161 (const_string "mtcr") 9162 (eq_attr "alternative" "6,7") 9163 (const_string "integer") 9164 (eq_attr "alternative" "8") 9165 (const_string "mfjmpr") 9166 (eq_attr "alternative" "9") 9167 (const_string "mtjmpr") 9168 (eq_attr "alternative" "10") 9169 (if_then_else 9170 (match_test "update_indexed_address_mem (operands[1], 9171 VOIDmode)") 9172 (const_string "load_ux") 9173 (if_then_else 9174 (match_test "update_address_mem (operands[1], VOIDmode)") 9175 (const_string "load_u") 9176 (const_string "load"))) 9177 (eq_attr "alternative" "11") 9178 (if_then_else 9179 (match_test "update_indexed_address_mem (operands[0], 9180 VOIDmode)") 9181 (const_string "store_ux") 9182 (if_then_else 9183 (match_test "update_address_mem (operands[0], VOIDmode)") 9184 (const_string "store_u") 9185 (const_string "store"))) 9186 (match_test "TARGET_MFCRF") 9187 (const_string "mfcrf") 9188 ] 9189 (const_string "mfcr"))) 9190 (set_attr "length" "4,4,12,4,4,8,4,4,4,4,4,4")]) 9191 9192;; For floating-point, we normally deal with the floating-point registers 9193;; unless -msoft-float is used. The sole exception is that parameter passing 9194;; can produce floating-point values in fixed-point registers. Unless the 9195;; value is a simple constant or already in memory, we deal with this by 9196;; allocating memory and copying the value explicitly via that memory location. 9197 9198;; Move 32-bit binary/decimal floating point 9199(define_expand "mov<mode>" 9200 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "") 9201 (match_operand:FMOVE32 1 "any_operand" ""))] 9202 "<fmove_ok>" 9203 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") 9204 9205(define_split 9206 [(set (match_operand:FMOVE32 0 "gpc_reg_operand" "") 9207 (match_operand:FMOVE32 1 "const_double_operand" ""))] 9208 "reload_completed 9209 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 9210 || (GET_CODE (operands[0]) == SUBREG 9211 && GET_CODE (SUBREG_REG (operands[0])) == REG 9212 && REGNO (SUBREG_REG (operands[0])) <= 31))" 9213 [(set (match_dup 2) (match_dup 3))] 9214 " 9215{ 9216 long l; 9217 REAL_VALUE_TYPE rv; 9218 9219 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 9220 <real_value_to_target> (rv, l); 9221 9222 if (! TARGET_POWERPC64) 9223 operands[2] = operand_subword (operands[0], 0, 0, <MODE>mode); 9224 else 9225 operands[2] = gen_lowpart (SImode, operands[0]); 9226 9227 operands[3] = gen_int_mode (l, SImode); 9228}") 9229 9230(define_insn "mov<mode>_hardfloat" 9231 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=!r,!r,m,f,<f32_vsx>,<f32_vsx>,<f32_lr>,<f32_sm>,<f32_av>,Z,?<f32_dm>,?r,*c*l,!r,*h,!r,!r") 9232 (match_operand:FMOVE32 1 "input_operand" "r,m,r,f,<f32_vsx>,j,<f32_lm>,<f32_sr>,Z,<f32_av>,r,<f32_dm>,r, h, 0, G,Fn"))] 9233 "(gpc_reg_operand (operands[0], <MODE>mode) 9234 || gpc_reg_operand (operands[1], <MODE>mode)) 9235 && (TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT)" 9236 "@ 9237 mr %0,%1 9238 lwz%U1%X1 %0,%1 9239 stw%U0%X0 %1,%0 9240 fmr %0,%1 9241 xxlor %x0,%x1,%x1 9242 xxlxor %x0,%x0,%x0 9243 <f32_li> 9244 <f32_si> 9245 <f32_lv> 9246 <f32_sv> 9247 mtvsrwz %x0,%1 9248 mfvsrwz %0,%x1 9249 mt%0 %1 9250 mf%1 %0 9251 nop 9252 # 9253 #" 9254 [(set_attr_alternative "type" 9255 [(const_string "*") 9256 (if_then_else 9257 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9258 (const_string "load_ux") 9259 (if_then_else 9260 (match_test "update_address_mem (operands[1], VOIDmode)") 9261 (const_string "load_u") 9262 (const_string "load"))) 9263 (if_then_else 9264 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9265 (const_string "store_ux") 9266 (if_then_else 9267 (match_test "update_address_mem (operands[0], VOIDmode)") 9268 (const_string "store_u") 9269 (const_string "store"))) 9270 (const_string "fp") 9271 (const_string "vecsimple") 9272 (const_string "vecsimple") 9273 (if_then_else 9274 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9275 (const_string "fpload_ux") 9276 (if_then_else 9277 (match_test "update_address_mem (operands[1], VOIDmode)") 9278 (const_string "fpload_u") 9279 (const_string "fpload"))) 9280 (if_then_else 9281 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9282 (const_string "fpstore_ux") 9283 (if_then_else 9284 (match_test "update_address_mem (operands[0], VOIDmode)") 9285 (const_string "fpstore_u") 9286 (const_string "fpstore"))) 9287 (const_string "fpload") 9288 (const_string "fpstore") 9289 (const_string "mftgpr") 9290 (const_string "mffgpr") 9291 (const_string "mtjmpr") 9292 (const_string "mfjmpr") 9293 (const_string "*") 9294 (const_string "*") 9295 (const_string "*")]) 9296 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,4,8")]) 9297 9298(define_insn "*mov<mode>_softfloat" 9299 [(set (match_operand:FMOVE32 0 "nonimmediate_operand" "=r,cl,r,r,m,r,r,r,r,*h") 9300 (match_operand:FMOVE32 1 "input_operand" "r,r,h,m,r,I,L,G,Fn,0"))] 9301 "(gpc_reg_operand (operands[0], <MODE>mode) 9302 || gpc_reg_operand (operands[1], <MODE>mode)) 9303 && (TARGET_SOFT_FLOAT || !TARGET_FPRS)" 9304 "@ 9305 mr %0,%1 9306 mt%0 %1 9307 mf%1 %0 9308 lwz%U1%X1 %0,%1 9309 stw%U0%X0 %1,%0 9310 li %0,%1 9311 lis %0,%v1 9312 # 9313 # 9314 nop" 9315 [(set_attr_alternative "type" 9316 [(const_string "*") 9317 (const_string "mtjmpr") 9318 (const_string "mfjmpr") 9319 (if_then_else 9320 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9321 (const_string "load_ux") 9322 (if_then_else 9323 (match_test "update_address_mem (operands[1], VOIDmode)") 9324 (const_string "load_u") 9325 (const_string "load"))) 9326 (if_then_else 9327 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9328 (const_string "store_ux") 9329 (if_then_else 9330 (match_test "update_address_mem (operands[0], VOIDmode)") 9331 (const_string "store_u") 9332 (const_string "store"))) 9333 (const_string "*") 9334 (const_string "*") 9335 (const_string "*") 9336 (const_string "*") 9337 (const_string "*")]) 9338 (set_attr "length" "4,4,4,4,4,4,4,4,8,4")]) 9339 9340 9341;; Move 64-bit binary/decimal floating point 9342(define_expand "mov<mode>" 9343 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "") 9344 (match_operand:FMOVE64 1 "any_operand" ""))] 9345 "" 9346 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") 9347 9348(define_split 9349 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") 9350 (match_operand:FMOVE64 1 "const_int_operand" ""))] 9351 "! TARGET_POWERPC64 && reload_completed 9352 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 9353 || (GET_CODE (operands[0]) == SUBREG 9354 && GET_CODE (SUBREG_REG (operands[0])) == REG 9355 && REGNO (SUBREG_REG (operands[0])) <= 31))" 9356 [(set (match_dup 2) (match_dup 4)) 9357 (set (match_dup 3) (match_dup 1))] 9358 " 9359{ 9360 int endian = (WORDS_BIG_ENDIAN == 0); 9361 HOST_WIDE_INT value = INTVAL (operands[1]); 9362 9363 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode); 9364 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode); 9365#if HOST_BITS_PER_WIDE_INT == 32 9366 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; 9367#else 9368 operands[4] = GEN_INT (value >> 32); 9369 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); 9370#endif 9371}") 9372 9373(define_split 9374 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") 9375 (match_operand:FMOVE64 1 "const_double_operand" ""))] 9376 "! TARGET_POWERPC64 && reload_completed 9377 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 9378 || (GET_CODE (operands[0]) == SUBREG 9379 && GET_CODE (SUBREG_REG (operands[0])) == REG 9380 && REGNO (SUBREG_REG (operands[0])) <= 31))" 9381 [(set (match_dup 2) (match_dup 4)) 9382 (set (match_dup 3) (match_dup 5))] 9383 " 9384{ 9385 int endian = (WORDS_BIG_ENDIAN == 0); 9386 long l[2]; 9387 REAL_VALUE_TYPE rv; 9388 9389 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 9390 <real_value_to_target> (rv, l); 9391 9392 operands[2] = operand_subword (operands[0], endian, 0, <MODE>mode); 9393 operands[3] = operand_subword (operands[0], 1 - endian, 0, <MODE>mode); 9394 operands[4] = gen_int_mode (l[endian], SImode); 9395 operands[5] = gen_int_mode (l[1 - endian], SImode); 9396}") 9397 9398(define_split 9399 [(set (match_operand:FMOVE64 0 "gpc_reg_operand" "") 9400 (match_operand:FMOVE64 1 "const_double_operand" ""))] 9401 "TARGET_POWERPC64 && reload_completed 9402 && ((GET_CODE (operands[0]) == REG && REGNO (operands[0]) <= 31) 9403 || (GET_CODE (operands[0]) == SUBREG 9404 && GET_CODE (SUBREG_REG (operands[0])) == REG 9405 && REGNO (SUBREG_REG (operands[0])) <= 31))" 9406 [(set (match_dup 2) (match_dup 3))] 9407 " 9408{ 9409 int endian = (WORDS_BIG_ENDIAN == 0); 9410 long l[2]; 9411 REAL_VALUE_TYPE rv; 9412#if HOST_BITS_PER_WIDE_INT >= 64 9413 HOST_WIDE_INT val; 9414#endif 9415 9416 REAL_VALUE_FROM_CONST_DOUBLE (rv, operands[1]); 9417 <real_value_to_target> (rv, l); 9418 9419 operands[2] = gen_lowpart (DImode, operands[0]); 9420 /* HIGHPART is lower memory address when WORDS_BIG_ENDIAN. */ 9421#if HOST_BITS_PER_WIDE_INT >= 64 9422 val = ((HOST_WIDE_INT)(unsigned long)l[endian] << 32 9423 | ((HOST_WIDE_INT)(unsigned long)l[1 - endian])); 9424 9425 operands[3] = gen_int_mode (val, DImode); 9426#else 9427 operands[3] = immed_double_const (l[1 - endian], l[endian], DImode); 9428#endif 9429}") 9430 9431;; Don't have reload use general registers to load a constant. It is 9432;; less efficient than loading the constant into an FP register, since 9433;; it will probably be used there. 9434 9435;; The move constraints are ordered to prefer floating point registers before 9436;; general purpose registers to avoid doing a store and a load to get the value 9437;; into a floating point register when it is needed for a floating point 9438;; operation. Prefer traditional floating point registers over VSX registers, 9439;; since the D-form version of the memory instructions does not need a GPR for 9440;; reloading. 9441 9442(define_insn "*mov<mode>_hardfloat32" 9443 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,!r,!r,!r") 9444 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,G,H,F"))] 9445 "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 9446 && (gpc_reg_operand (operands[0], <MODE>mode) 9447 || gpc_reg_operand (operands[1], <MODE>mode))" 9448 "@ 9449 stfd%U0%X0 %1,%0 9450 lfd%U1%X1 %0,%1 9451 fmr %0,%1 9452 lxsd%U1x %x0,%y1 9453 stxsd%U0x %x1,%y0 9454 xxlor %x0,%x1,%x1 9455 xxlxor %x0,%x0,%x0 9456 # 9457 # 9458 # 9459 # 9460 # 9461 #" 9462 [(set_attr_alternative "type" 9463 [(if_then_else 9464 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9465 (const_string "fpstore_ux") 9466 (if_then_else 9467 (match_test "update_address_mem (operands[0], VOIDmode)") 9468 (const_string "fpstore_u") 9469 (const_string "fpstore"))) 9470 (if_then_else 9471 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9472 (const_string "fpload_ux") 9473 (if_then_else 9474 (match_test "update_address_mem (operands[1], VOIDmode)") 9475 (const_string "fpload_u") 9476 (const_string "fpload"))) 9477 (const_string "fp") 9478 (if_then_else 9479 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9480 (const_string "fpload_ux") 9481 (const_string "fpload")) 9482 (if_then_else 9483 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9484 (const_string "fpstore_ux") 9485 (const_string "fpstore")) 9486 (const_string "vecsimple") 9487 (const_string "vecsimple") 9488 (const_string "store") 9489 (const_string "load") 9490 (const_string "two") 9491 (const_string "fp") 9492 (const_string "fp") 9493 (const_string "*")]) 9494 (set_attr "length" "4,4,4,4,4,4,4,8,8,8,8,12,16")]) 9495 9496(define_insn "*mov<mode>_softfloat32" 9497 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,r,r,r") 9498 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,G,H,F"))] 9499 "! TARGET_POWERPC64 9500 && ((TARGET_FPRS && TARGET_SINGLE_FLOAT) 9501 || TARGET_SOFT_FLOAT || TARGET_E500_SINGLE 9502 || (<MODE>mode == DDmode && TARGET_E500_DOUBLE)) 9503 && (gpc_reg_operand (operands[0], <MODE>mode) 9504 || gpc_reg_operand (operands[1], <MODE>mode))" 9505 "#" 9506 [(set_attr "type" "store,load,two,*,*,*") 9507 (set_attr "length" "8,8,8,8,12,16")]) 9508 9509; ld/std require word-aligned displacements -> 'Y' constraint. 9510; List Y->r and r->Y before r->r for reload. 9511(define_insn "*mov<mode>_hardfloat64" 9512 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m,d,d,<f64_av>,Z,<f64_vsx>,<f64_vsx>,Y,r,!r,*c*l,!r,*h,!r,!r,!r,r,wg,r,<f64_dm>") 9513 (match_operand:FMOVE64 1 "input_operand" "d,m,d,Z,<f64_av>,<f64_vsx>,j,r,Y,r,r,h,0,G,H,F,wg,r,<f64_dm>,r"))] 9514 "TARGET_POWERPC64 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 9515 && (gpc_reg_operand (operands[0], <MODE>mode) 9516 || gpc_reg_operand (operands[1], <MODE>mode))" 9517 "@ 9518 stfd%U0%X0 %1,%0 9519 lfd%U1%X1 %0,%1 9520 fmr %0,%1 9521 lxsd%U1x %x0,%y1 9522 stxsd%U0x %x1,%y0 9523 xxlor %x0,%x1,%x1 9524 xxlxor %x0,%x0,%x0 9525 std%U0%X0 %1,%0 9526 ld%U1%X1 %0,%1 9527 mr %0,%1 9528 mt%0 %1 9529 mf%1 %0 9530 nop 9531 # 9532 # 9533 # 9534 mftgpr %0,%1 9535 mffgpr %0,%1 9536 mfvsrd %0,%x1 9537 mtvsrd %x0,%1" 9538 [(set_attr_alternative "type" 9539 [(if_then_else 9540 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9541 (const_string "fpstore_ux") 9542 (if_then_else 9543 (match_test "update_address_mem (operands[0], VOIDmode)") 9544 (const_string "fpstore_u") 9545 (const_string "fpstore"))) 9546 (if_then_else 9547 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9548 (const_string "fpload_ux") 9549 (if_then_else 9550 (match_test "update_address_mem (operands[1], VOIDmode)") 9551 (const_string "fpload_u") 9552 (const_string "fpload"))) 9553 (const_string "fp") 9554 (if_then_else 9555 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9556 (const_string "fpload_ux") 9557 (const_string "fpload")) 9558 (if_then_else 9559 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9560 (const_string "fpstore_ux") 9561 (const_string "fpstore")) 9562 (const_string "vecsimple") 9563 (const_string "vecsimple") 9564 (if_then_else 9565 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9566 (const_string "store_ux") 9567 (if_then_else 9568 (match_test "update_address_mem (operands[0], VOIDmode)") 9569 (const_string "store_u") 9570 (const_string "store"))) 9571 (if_then_else 9572 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9573 (const_string "load_ux") 9574 (if_then_else 9575 (match_test "update_address_mem (operands[1], VOIDmode)") 9576 (const_string "load_u") 9577 (const_string "load"))) 9578 (const_string "*") 9579 (const_string "mtjmpr") 9580 (const_string "mfjmpr") 9581 (const_string "*") 9582 (const_string "*") 9583 (const_string "*") 9584 (const_string "*") 9585 (const_string "mftgpr") 9586 (const_string "mffgpr") 9587 (const_string "mftgpr") 9588 (const_string "mffgpr")]) 9589 (set_attr "length" "4,4,4,4,4,4,4,4,4,4,4,4,4,8,12,16,4,4,4,4")]) 9590 9591(define_insn "*mov<mode>_softfloat64" 9592 [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=Y,r,r,cl,r,r,r,r,*h") 9593 (match_operand:FMOVE64 1 "input_operand" "r,Y,r,r,h,G,H,F,0"))] 9594 "TARGET_POWERPC64 && (TARGET_SOFT_FLOAT || !TARGET_FPRS) 9595 && (gpc_reg_operand (operands[0], <MODE>mode) 9596 || gpc_reg_operand (operands[1], <MODE>mode))" 9597 "@ 9598 std%U0%X0 %1,%0 9599 ld%U1%X1 %0,%1 9600 mr %0,%1 9601 mt%0 %1 9602 mf%1 %0 9603 # 9604 # 9605 # 9606 nop" 9607 [(set_attr_alternative "type" 9608 [(if_then_else 9609 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 9610 (const_string "store_ux") 9611 (if_then_else 9612 (match_test "update_address_mem (operands[0], VOIDmode)") 9613 (const_string "store_u") 9614 (const_string "store"))) 9615 (if_then_else 9616 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 9617 (const_string "load_ux") 9618 (if_then_else 9619 (match_test "update_address_mem (operands[1], VOIDmode)") 9620 (const_string "load_u") 9621 (const_string "load"))) 9622 (const_string "*") 9623 (const_string "mtjmpr") 9624 (const_string "mfjmpr") 9625 (const_string "*") 9626 (const_string "*") 9627 (const_string "*") 9628 (const_string "*")]) 9629 (set_attr "length" "4,4,4,4,4,8,12,16,4")]) 9630 9631(define_expand "mov<mode>" 9632 [(set (match_operand:FMOVE128 0 "general_operand" "") 9633 (match_operand:FMOVE128 1 "any_operand" ""))] 9634 "" 9635 "{ rs6000_emit_move (operands[0], operands[1], <MODE>mode); DONE; }") 9636 9637;; It's important to list Y->r and r->Y before r->r because otherwise 9638;; reload, given m->r, will try to pick r->r and reload it, which 9639;; doesn't make progress. 9640 9641;; We can't split little endian direct moves of TDmode, because the words are 9642;; not swapped like they are for TImode or TFmode. Subregs therefore are 9643;; problematical. Don't allow direct move for this case. 9644 9645(define_insn_and_split "*mov<mode>_64bit_dm" 9646 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r,r,wm") 9647 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r,wm,r"))] 9648 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 9649 && (<MODE>mode != TDmode || WORDS_BIG_ENDIAN) 9650 && (gpc_reg_operand (operands[0], <MODE>mode) 9651 || gpc_reg_operand (operands[1], <MODE>mode))" 9652 "#" 9653 "&& reload_completed" 9654 [(pc)] 9655{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } 9656 [(set_attr "length" "8,8,8,12,12,8,8,8")]) 9657 9658(define_insn_and_split "*movtd_64bit_nodm" 9659 [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") 9660 (match_operand:TD 1 "input_operand" "d,m,d,r,YGHF,r"))] 9661 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN 9662 && (gpc_reg_operand (operands[0], TDmode) 9663 || gpc_reg_operand (operands[1], TDmode))" 9664 "#" 9665 "&& reload_completed" 9666 [(pc)] 9667{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } 9668 [(set_attr "length" "8,8,8,12,12,8")]) 9669 9670(define_insn_and_split "*mov<mode>_32bit" 9671 [(set (match_operand:FMOVE128 0 "nonimmediate_operand" "=m,d,d,Y,r,r") 9672 (match_operand:FMOVE128 1 "input_operand" "d,m,d,r,YGHF,r"))] 9673 "TARGET_HARD_FLOAT && TARGET_FPRS && !TARGET_POWERPC64 9674 && (gpc_reg_operand (operands[0], <MODE>mode) 9675 || gpc_reg_operand (operands[1], <MODE>mode))" 9676 "#" 9677 "&& reload_completed" 9678 [(pc)] 9679{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } 9680 [(set_attr "length" "8,8,8,20,20,16")]) 9681 9682(define_insn_and_split "*mov<mode>_softfloat" 9683 [(set (match_operand:FMOVE128 0 "rs6000_nonimmediate_operand" "=Y,r,r") 9684 (match_operand:FMOVE128 1 "input_operand" "r,YGHF,r"))] 9685 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) 9686 && (gpc_reg_operand (operands[0], <MODE>mode) 9687 || gpc_reg_operand (operands[1], <MODE>mode))" 9688 "#" 9689 "&& reload_completed" 9690 [(pc)] 9691{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } 9692 [(set_attr "length" "20,20,16")]) 9693 9694(define_expand "extenddftf2" 9695 [(set (match_operand:TF 0 "nonimmediate_operand" "") 9696 (float_extend:TF (match_operand:DF 1 "input_operand" "")))] 9697 "!TARGET_IEEEQUAD 9698 && TARGET_HARD_FLOAT 9699 && (TARGET_FPRS || TARGET_E500_DOUBLE) 9700 && TARGET_LONG_DOUBLE_128" 9701{ 9702 if (TARGET_E500_DOUBLE) 9703 emit_insn (gen_spe_extenddftf2 (operands[0], operands[1])); 9704 else 9705 emit_insn (gen_extenddftf2_fprs (operands[0], operands[1])); 9706 DONE; 9707}) 9708 9709(define_expand "extenddftf2_fprs" 9710 [(parallel [(set (match_operand:TF 0 "nonimmediate_operand" "") 9711 (float_extend:TF (match_operand:DF 1 "input_operand" ""))) 9712 (use (match_dup 2))])] 9713 "!TARGET_IEEEQUAD 9714 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 9715 && TARGET_LONG_DOUBLE_128" 9716{ 9717 operands[2] = CONST0_RTX (DFmode); 9718 /* Generate GOT reference early for SVR4 PIC. */ 9719 if (DEFAULT_ABI == ABI_V4 && flag_pic) 9720 operands[2] = validize_mem (force_const_mem (DFmode, operands[2])); 9721}) 9722 9723(define_insn_and_split "*extenddftf2_internal" 9724 [(set (match_operand:TF 0 "nonimmediate_operand" "=m,Y,d,&d,r") 9725 (float_extend:TF (match_operand:DF 1 "input_operand" "d,r,md,md,rmGHF"))) 9726 (use (match_operand:DF 2 "zero_reg_mem_operand" "d,r,m,d,n"))] 9727 "!TARGET_IEEEQUAD 9728 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 9729 && TARGET_LONG_DOUBLE_128" 9730 "#" 9731 "&& reload_completed" 9732 [(pc)] 9733{ 9734 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0; 9735 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode); 9736 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word), 9737 operands[1]); 9738 emit_move_insn (simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word), 9739 operands[2]); 9740 DONE; 9741}) 9742 9743(define_expand "extendsftf2" 9744 [(set (match_operand:TF 0 "nonimmediate_operand" "") 9745 (float_extend:TF (match_operand:SF 1 "gpc_reg_operand" "")))] 9746 "!TARGET_IEEEQUAD 9747 && TARGET_HARD_FLOAT 9748 && (TARGET_FPRS || TARGET_E500_DOUBLE) 9749 && TARGET_LONG_DOUBLE_128" 9750{ 9751 rtx tmp = gen_reg_rtx (DFmode); 9752 emit_insn (gen_extendsfdf2 (tmp, operands[1])); 9753 emit_insn (gen_extenddftf2 (operands[0], tmp)); 9754 DONE; 9755}) 9756 9757(define_expand "trunctfdf2" 9758 [(set (match_operand:DF 0 "gpc_reg_operand" "") 9759 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "")))] 9760 "!TARGET_IEEEQUAD 9761 && TARGET_HARD_FLOAT 9762 && (TARGET_FPRS || TARGET_E500_DOUBLE) 9763 && TARGET_LONG_DOUBLE_128" 9764 "") 9765 9766(define_insn_and_split "trunctfdf2_internal1" 9767 [(set (match_operand:DF 0 "gpc_reg_operand" "=d,?d") 9768 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "0,d")))] 9769 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT 9770 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 9771 "@ 9772 # 9773 fmr %0,%1" 9774 "&& reload_completed && REGNO (operands[0]) == REGNO (operands[1])" 9775 [(const_int 0)] 9776{ 9777 emit_note (NOTE_INSN_DELETED); 9778 DONE; 9779} 9780 [(set_attr "type" "fp")]) 9781 9782(define_insn "trunctfdf2_internal2" 9783 [(set (match_operand:DF 0 "gpc_reg_operand" "=d") 9784 (float_truncate:DF (match_operand:TF 1 "gpc_reg_operand" "d")))] 9785 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT 9786 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 9787 && TARGET_LONG_DOUBLE_128" 9788 "fadd %0,%1,%L1" 9789 [(set_attr "type" "fp") 9790 (set_attr "fp_type" "fp_addsub_d")]) 9791 9792(define_expand "trunctfsf2" 9793 [(set (match_operand:SF 0 "gpc_reg_operand" "") 9794 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "")))] 9795 "!TARGET_IEEEQUAD 9796 && TARGET_HARD_FLOAT 9797 && (TARGET_FPRS || TARGET_E500_DOUBLE) 9798 && TARGET_LONG_DOUBLE_128" 9799{ 9800 if (TARGET_E500_DOUBLE) 9801 emit_insn (gen_spe_trunctfsf2 (operands[0], operands[1])); 9802 else 9803 emit_insn (gen_trunctfsf2_fprs (operands[0], operands[1])); 9804 DONE; 9805}) 9806 9807(define_insn_and_split "trunctfsf2_fprs" 9808 [(set (match_operand:SF 0 "gpc_reg_operand" "=f") 9809 (float_truncate:SF (match_operand:TF 1 "gpc_reg_operand" "d"))) 9810 (clobber (match_scratch:DF 2 "=d"))] 9811 "!TARGET_IEEEQUAD 9812 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT 9813 && TARGET_LONG_DOUBLE_128" 9814 "#" 9815 "&& reload_completed" 9816 [(set (match_dup 2) 9817 (float_truncate:DF (match_dup 1))) 9818 (set (match_dup 0) 9819 (float_truncate:SF (match_dup 2)))] 9820 "") 9821 9822(define_expand "floatsitf2" 9823 [(set (match_operand:TF 0 "gpc_reg_operand" "") 9824 (float:TF (match_operand:SI 1 "gpc_reg_operand" "")))] 9825 "!TARGET_IEEEQUAD 9826 && TARGET_HARD_FLOAT 9827 && (TARGET_FPRS || TARGET_E500_DOUBLE) 9828 && TARGET_LONG_DOUBLE_128" 9829{ 9830 rtx tmp = gen_reg_rtx (DFmode); 9831 expand_float (tmp, operands[1], false); 9832 emit_insn (gen_extenddftf2 (operands[0], tmp)); 9833 DONE; 9834}) 9835 9836; fadd, but rounding towards zero. 9837; This is probably not the optimal code sequence. 9838(define_insn "fix_trunc_helper" 9839 [(set (match_operand:DF 0 "gpc_reg_operand" "=d") 9840 (unspec:DF [(match_operand:TF 1 "gpc_reg_operand" "d")] 9841 UNSPEC_FIX_TRUNC_TF)) 9842 (clobber (match_operand:DF 2 "gpc_reg_operand" "=&d"))] 9843 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT" 9844 "mffs %2\n\tmtfsb1 31\n\tmtfsb0 30\n\tfadd %0,%1,%L1\n\tmtfsf 1,%2" 9845 [(set_attr "type" "fp") 9846 (set_attr "length" "20")]) 9847 9848(define_expand "fix_trunctfsi2" 9849 [(set (match_operand:SI 0 "gpc_reg_operand" "") 9850 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "")))] 9851 "!TARGET_IEEEQUAD && TARGET_HARD_FLOAT 9852 && (TARGET_FPRS || TARGET_E500_DOUBLE) && TARGET_LONG_DOUBLE_128" 9853{ 9854 if (TARGET_E500_DOUBLE) 9855 emit_insn (gen_spe_fix_trunctfsi2 (operands[0], operands[1])); 9856 else 9857 emit_insn (gen_fix_trunctfsi2_fprs (operands[0], operands[1])); 9858 DONE; 9859}) 9860 9861(define_expand "fix_trunctfsi2_fprs" 9862 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "") 9863 (fix:SI (match_operand:TF 1 "gpc_reg_operand" ""))) 9864 (clobber (match_dup 2)) 9865 (clobber (match_dup 3)) 9866 (clobber (match_dup 4)) 9867 (clobber (match_dup 5))])] 9868 "!TARGET_IEEEQUAD 9869 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 9870{ 9871 operands[2] = gen_reg_rtx (DFmode); 9872 operands[3] = gen_reg_rtx (DFmode); 9873 operands[4] = gen_reg_rtx (DImode); 9874 operands[5] = assign_stack_temp (DImode, GET_MODE_SIZE (DImode)); 9875}) 9876 9877(define_insn_and_split "*fix_trunctfsi2_internal" 9878 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 9879 (fix:SI (match_operand:TF 1 "gpc_reg_operand" "d"))) 9880 (clobber (match_operand:DF 2 "gpc_reg_operand" "=d")) 9881 (clobber (match_operand:DF 3 "gpc_reg_operand" "=&d")) 9882 (clobber (match_operand:DI 4 "gpc_reg_operand" "=d")) 9883 (clobber (match_operand:DI 5 "offsettable_mem_operand" "=o"))] 9884 "!TARGET_IEEEQUAD 9885 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 9886 "#" 9887 "" 9888 [(pc)] 9889{ 9890 rtx lowword; 9891 emit_insn (gen_fix_trunc_helper (operands[2], operands[1], operands[3])); 9892 9893 gcc_assert (MEM_P (operands[5])); 9894 lowword = adjust_address (operands[5], SImode, WORDS_BIG_ENDIAN ? 4 : 0); 9895 9896 emit_insn (gen_fctiwz_df (operands[4], operands[2])); 9897 emit_move_insn (operands[5], operands[4]); 9898 emit_move_insn (operands[0], lowword); 9899 DONE; 9900}) 9901 9902(define_expand "negtf2" 9903 [(set (match_operand:TF 0 "gpc_reg_operand" "") 9904 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "")))] 9905 "!TARGET_IEEEQUAD 9906 && TARGET_HARD_FLOAT 9907 && (TARGET_FPRS || TARGET_E500_DOUBLE) 9908 && TARGET_LONG_DOUBLE_128" 9909 "") 9910 9911(define_insn "negtf2_internal" 9912 [(set (match_operand:TF 0 "gpc_reg_operand" "=d") 9913 (neg:TF (match_operand:TF 1 "gpc_reg_operand" "d")))] 9914 "!TARGET_IEEEQUAD 9915 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_LONG_DOUBLE_128" 9916 "* 9917{ 9918 if (REGNO (operands[0]) == REGNO (operands[1]) + 1) 9919 return \"fneg %L0,%L1\;fneg %0,%1\"; 9920 else 9921 return \"fneg %0,%1\;fneg %L0,%L1\"; 9922}" 9923 [(set_attr "type" "fp") 9924 (set_attr "length" "8")]) 9925 9926(define_expand "abstf2" 9927 [(set (match_operand:TF 0 "gpc_reg_operand" "") 9928 (abs:TF (match_operand:TF 1 "gpc_reg_operand" "")))] 9929 "!TARGET_IEEEQUAD 9930 && TARGET_HARD_FLOAT 9931 && (TARGET_FPRS || TARGET_E500_DOUBLE) 9932 && TARGET_LONG_DOUBLE_128" 9933 " 9934{ 9935 rtx label = gen_label_rtx (); 9936 if (TARGET_E500_DOUBLE) 9937 { 9938 if (flag_finite_math_only && !flag_trapping_math) 9939 emit_insn (gen_spe_abstf2_tst (operands[0], operands[1], label)); 9940 else 9941 emit_insn (gen_spe_abstf2_cmp (operands[0], operands[1], label)); 9942 } 9943 else 9944 emit_insn (gen_abstf2_internal (operands[0], operands[1], label)); 9945 emit_label (label); 9946 DONE; 9947}") 9948 9949(define_expand "abstf2_internal" 9950 [(set (match_operand:TF 0 "gpc_reg_operand" "") 9951 (match_operand:TF 1 "gpc_reg_operand" "")) 9952 (set (match_dup 3) (match_dup 5)) 9953 (set (match_dup 5) (abs:DF (match_dup 5))) 9954 (set (match_dup 4) (compare:CCFP (match_dup 3) (match_dup 5))) 9955 (set (pc) (if_then_else (eq (match_dup 4) (const_int 0)) 9956 (label_ref (match_operand 2 "" "")) 9957 (pc))) 9958 (set (match_dup 6) (neg:DF (match_dup 6)))] 9959 "!TARGET_IEEEQUAD 9960 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT 9961 && TARGET_LONG_DOUBLE_128" 9962 " 9963{ 9964 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode); 9965 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0; 9966 operands[3] = gen_reg_rtx (DFmode); 9967 operands[4] = gen_reg_rtx (CCFPmode); 9968 operands[5] = simplify_gen_subreg (DFmode, operands[0], TFmode, hi_word); 9969 operands[6] = simplify_gen_subreg (DFmode, operands[0], TFmode, lo_word); 9970}") 9971 9972;; Reload helper functions used by rs6000_secondary_reload. The patterns all 9973;; must have 3 arguments, and scratch register constraint must be a single 9974;; constraint. 9975 9976;; Reload patterns to support gpr load/store with misaligned mem. 9977;; and multiple gpr load/store at offset >= 0xfffc 9978(define_expand "reload_<mode>_store" 9979 [(parallel [(match_operand 0 "memory_operand" "=m") 9980 (match_operand 1 "gpc_reg_operand" "r") 9981 (match_operand:GPR 2 "register_operand" "=&b")])] 9982 "" 9983{ 9984 rs6000_secondary_reload_gpr (operands[1], operands[0], operands[2], true); 9985 DONE; 9986}) 9987 9988(define_expand "reload_<mode>_load" 9989 [(parallel [(match_operand 0 "gpc_reg_operand" "=r") 9990 (match_operand 1 "memory_operand" "m") 9991 (match_operand:GPR 2 "register_operand" "=b")])] 9992 "" 9993{ 9994 rs6000_secondary_reload_gpr (operands[0], operands[1], operands[2], false); 9995 DONE; 9996}) 9997 9998 9999;; Power8 merge instructions to allow direct move to/from floating point 10000;; registers in 32-bit mode. We use TF mode to get two registers to move the 10001;; individual 32-bit parts across. Subreg doesn't work too well on the TF 10002;; value, since it is allocated in reload and not all of the flow information 10003;; is setup for it. We have two patterns to do the two moves between gprs and 10004;; fprs. There isn't a dependancy between the two, but we could potentially 10005;; schedule other instructions between the two instructions. TFmode is 10006;; currently limited to traditional FPR registers. If/when this is changed, we 10007;; will need to revist %L to make sure it works with VSX registers, or add an 10008;; %x version of %L. 10009 10010(define_insn "p8_fmrgow_<mode>" 10011 [(set (match_operand:FMOVE64X 0 "register_operand" "=d") 10012 (unspec:FMOVE64X [(match_operand:TF 1 "register_operand" "d")] 10013 UNSPEC_P8V_FMRGOW))] 10014 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10015 "fmrgow %0,%1,%L1" 10016 [(set_attr "type" "vecperm")]) 10017 10018(define_insn "p8_mtvsrwz_1" 10019 [(set (match_operand:TF 0 "register_operand" "=d") 10020 (unspec:TF [(match_operand:SI 1 "register_operand" "r")] 10021 UNSPEC_P8V_MTVSRWZ))] 10022 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10023 "mtvsrwz %x0,%1" 10024 [(set_attr "type" "mftgpr")]) 10025 10026(define_insn "p8_mtvsrwz_2" 10027 [(set (match_operand:TF 0 "register_operand" "+d") 10028 (unspec:TF [(match_dup 0) 10029 (match_operand:SI 1 "register_operand" "r")] 10030 UNSPEC_P8V_MTVSRWZ))] 10031 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10032 "mtvsrwz %L0,%1" 10033 [(set_attr "type" "mftgpr")]) 10034 10035(define_insn_and_split "reload_fpr_from_gpr<mode>" 10036 [(set (match_operand:FMOVE64X 0 "register_operand" "=ws") 10037 (unspec:FMOVE64X [(match_operand:FMOVE64X 1 "register_operand" "r")] 10038 UNSPEC_P8V_RELOAD_FROM_GPR)) 10039 (clobber (match_operand:TF 2 "register_operand" "=d"))] 10040 "!TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10041 "#" 10042 "&& reload_completed" 10043 [(const_int 0)] 10044{ 10045 rtx dest = operands[0]; 10046 rtx src = operands[1]; 10047 rtx tmp = operands[2]; 10048 rtx gpr_hi_reg = gen_highpart (SImode, src); 10049 rtx gpr_lo_reg = gen_lowpart (SImode, src); 10050 10051 emit_insn (gen_p8_mtvsrwz_1 (tmp, gpr_hi_reg)); 10052 emit_insn (gen_p8_mtvsrwz_2 (tmp, gpr_lo_reg)); 10053 emit_insn (gen_p8_fmrgow_<mode> (dest, tmp)); 10054 DONE; 10055} 10056 [(set_attr "length" "12") 10057 (set_attr "type" "three")]) 10058 10059;; Move 128 bit values from GPRs to VSX registers in 64-bit mode 10060(define_insn "p8_mtvsrd_1" 10061 [(set (match_operand:TF 0 "register_operand" "=ws") 10062 (unspec:TF [(match_operand:DI 1 "register_operand" "r")] 10063 UNSPEC_P8V_MTVSRD))] 10064 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10065 "mtvsrd %0,%1" 10066 [(set_attr "type" "mftgpr")]) 10067 10068(define_insn "p8_mtvsrd_2" 10069 [(set (match_operand:TF 0 "register_operand" "+ws") 10070 (unspec:TF [(match_dup 0) 10071 (match_operand:DI 1 "register_operand" "r")] 10072 UNSPEC_P8V_MTVSRD))] 10073 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10074 "mtvsrd %L0,%1" 10075 [(set_attr "type" "mftgpr")]) 10076 10077(define_insn "p8_xxpermdi_<mode>" 10078 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa") 10079 (unspec:FMOVE128_GPR [(match_operand:TF 1 "register_operand" "ws")] 10080 UNSPEC_P8V_XXPERMDI))] 10081 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10082 "xxpermdi %x0,%1,%L1,0" 10083 [(set_attr "type" "vecperm")]) 10084 10085(define_insn_and_split "reload_vsx_from_gpr<mode>" 10086 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=wa") 10087 (unspec:FMOVE128_GPR 10088 [(match_operand:FMOVE128_GPR 1 "register_operand" "r")] 10089 UNSPEC_P8V_RELOAD_FROM_GPR)) 10090 (clobber (match_operand:TF 2 "register_operand" "=ws"))] 10091 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10092 "#" 10093 "&& reload_completed" 10094 [(const_int 0)] 10095{ 10096 rtx dest = operands[0]; 10097 rtx src = operands[1]; 10098 rtx tmp = operands[2]; 10099 rtx gpr_hi_reg = gen_highpart (DImode, src); 10100 rtx gpr_lo_reg = gen_lowpart (DImode, src); 10101 10102 emit_insn (gen_p8_mtvsrd_1 (tmp, gpr_hi_reg)); 10103 emit_insn (gen_p8_mtvsrd_2 (tmp, gpr_lo_reg)); 10104 emit_insn (gen_p8_xxpermdi_<mode> (dest, tmp)); 10105} 10106 [(set_attr "length" "12") 10107 (set_attr "type" "three")]) 10108 10109(define_split 10110 [(set (match_operand:FMOVE128_GPR 0 "nonimmediate_operand" "") 10111 (match_operand:FMOVE128_GPR 1 "input_operand" ""))] 10112 "reload_completed 10113 && (int_reg_operand (operands[0], <MODE>mode) 10114 || int_reg_operand (operands[1], <MODE>mode))" 10115 [(pc)] 10116{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 10117 10118;; Move SFmode to a VSX from a GPR register. Because scalar floating point 10119;; type is stored internally as double precision in the VSX registers, we have 10120;; to convert it from the vector format. 10121 10122(define_insn_and_split "reload_vsx_from_gprsf" 10123 [(set (match_operand:SF 0 "register_operand" "=wa") 10124 (unspec:SF [(match_operand:SF 1 "register_operand" "r")] 10125 UNSPEC_P8V_RELOAD_FROM_GPR)) 10126 (clobber (match_operand:DI 2 "register_operand" "=r"))] 10127 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10128 "#" 10129 "&& reload_completed" 10130 [(const_int 0)] 10131{ 10132 rtx op0 = operands[0]; 10133 rtx op1 = operands[1]; 10134 rtx op2 = operands[2]; 10135 rtx op0_di = simplify_gen_subreg (DImode, op0, SFmode, 0); 10136 rtx op1_di = simplify_gen_subreg (DImode, op1, SFmode, 0); 10137 10138 /* Move SF value to upper 32-bits for xscvspdpn. */ 10139 emit_insn (gen_ashldi3 (op2, op1_di, GEN_INT (32))); 10140 emit_move_insn (op0_di, op2); 10141 emit_insn (gen_vsx_xscvspdpn_directmove (op0, op0)); 10142 DONE; 10143} 10144 [(set_attr "length" "8") 10145 (set_attr "type" "two")]) 10146 10147;; Move 128 bit values from VSX registers to GPRs in 64-bit mode by doing a 10148;; normal 64-bit move, followed by an xxpermdi to get the bottom 64-bit value, 10149;; and then doing a move of that. 10150(define_insn "p8_mfvsrd_3_<mode>" 10151 [(set (match_operand:DF 0 "register_operand" "=r") 10152 (unspec:DF [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")] 10153 UNSPEC_P8V_RELOAD_FROM_VSX))] 10154 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10155 "mfvsrd %0,%x1" 10156 [(set_attr "type" "mftgpr")]) 10157 10158(define_insn_and_split "reload_gpr_from_vsx<mode>" 10159 [(set (match_operand:FMOVE128_GPR 0 "register_operand" "=r") 10160 (unspec:FMOVE128_GPR 10161 [(match_operand:FMOVE128_GPR 1 "register_operand" "wa")] 10162 UNSPEC_P8V_RELOAD_FROM_VSX)) 10163 (clobber (match_operand:FMOVE128_GPR 2 "register_operand" "=wa"))] 10164 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10165 "#" 10166 "&& reload_completed" 10167 [(const_int 0)] 10168{ 10169 rtx dest = operands[0]; 10170 rtx src = operands[1]; 10171 rtx tmp = operands[2]; 10172 rtx gpr_hi_reg = gen_highpart (DFmode, dest); 10173 rtx gpr_lo_reg = gen_lowpart (DFmode, dest); 10174 10175 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_hi_reg, src)); 10176 emit_insn (gen_vsx_xxpermdi_<mode> (tmp, src, src, GEN_INT (3))); 10177 emit_insn (gen_p8_mfvsrd_3_<mode> (gpr_lo_reg, tmp)); 10178} 10179 [(set_attr "length" "12") 10180 (set_attr "type" "three")]) 10181 10182;; Move SFmode to a GPR from a VSX register. Because scalar floating point 10183;; type is stored internally as double precision, we have to convert it to the 10184;; vector format. 10185 10186(define_insn_and_split "reload_gpr_from_vsxsf" 10187 [(set (match_operand:SF 0 "register_operand" "=r") 10188 (unspec:SF [(match_operand:SF 1 "register_operand" "wa")] 10189 UNSPEC_P8V_RELOAD_FROM_VSX)) 10190 (clobber (match_operand:V4SF 2 "register_operand" "=wa"))] 10191 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10192 "#" 10193 "&& reload_completed" 10194 [(const_int 0)] 10195{ 10196 rtx op0 = operands[0]; 10197 rtx op1 = operands[1]; 10198 rtx op2 = operands[2]; 10199 rtx diop0 = simplify_gen_subreg (DImode, op0, SFmode, 0); 10200 10201 emit_insn (gen_vsx_xscvdpspn_scalar (op2, op1)); 10202 emit_insn (gen_p8_mfvsrd_4_disf (diop0, op2)); 10203 emit_insn (gen_lshrdi3 (diop0, diop0, GEN_INT (32))); 10204 DONE; 10205} 10206 [(set_attr "length" "12") 10207 (set_attr "type" "three")]) 10208 10209(define_insn "p8_mfvsrd_4_disf" 10210 [(set (match_operand:DI 0 "register_operand" "=r") 10211 (unspec:DI [(match_operand:V4SF 1 "register_operand" "wa")] 10212 UNSPEC_P8V_RELOAD_FROM_VSX))] 10213 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 10214 "mfvsrd %0,%x1" 10215 [(set_attr "type" "mftgpr")]) 10216 10217 10218;; Next come the multi-word integer load and store and the load and store 10219;; multiple insns. 10220 10221;; List r->r after r->Y, otherwise reload will try to reload a 10222;; non-offsettable address by using r->r which won't make progress. 10223;; Use of fprs is disparaged slightly otherwise reload prefers to reload 10224;; a gpr into a fpr instead of reloading an invalid 'Y' address 10225(define_insn "*movdi_internal32" 10226 [(set (match_operand:DI 0 "rs6000_nonimmediate_operand" "=Y,r,r,?m,?*d,?*d,r") 10227 (match_operand:DI 1 "input_operand" "r,Y,r,d,m,d,IJKnGHF"))] 10228 "! TARGET_POWERPC64 10229 && (gpc_reg_operand (operands[0], DImode) 10230 || gpc_reg_operand (operands[1], DImode))" 10231 "@ 10232 # 10233 # 10234 # 10235 stfd%U0%X0 %1,%0 10236 lfd%U1%X1 %0,%1 10237 fmr %0,%1 10238 #" 10239 [(set_attr_alternative "type" 10240 [(const_string "store") 10241 (const_string "load") 10242 (const_string "*") 10243 (if_then_else 10244 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 10245 (const_string "fpstore_ux") 10246 (if_then_else 10247 (match_test "update_address_mem (operands[0], VOIDmode)") 10248 (const_string "fpstore_u") 10249 (const_string "fpstore"))) 10250 (if_then_else 10251 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 10252 (const_string "fpload_ux") 10253 (if_then_else 10254 (match_test "update_address_mem (operands[1], VOIDmode)") 10255 (const_string "fpload_u") 10256 (const_string "fpload"))) 10257 (const_string "fp") 10258 (const_string "*")])]) 10259 10260(define_split 10261 [(set (match_operand:DI 0 "gpc_reg_operand" "") 10262 (match_operand:DI 1 "const_int_operand" ""))] 10263 "! TARGET_POWERPC64 && reload_completed 10264 && gpr_or_gpr_p (operands[0], operands[1]) 10265 && !direct_move_p (operands[0], operands[1])" 10266 [(set (match_dup 2) (match_dup 4)) 10267 (set (match_dup 3) (match_dup 1))] 10268 " 10269{ 10270 HOST_WIDE_INT value = INTVAL (operands[1]); 10271 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, 10272 DImode); 10273 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, 10274 DImode); 10275#if HOST_BITS_PER_WIDE_INT == 32 10276 operands[4] = (value & 0x80000000) ? constm1_rtx : const0_rtx; 10277#else 10278 operands[4] = GEN_INT (value >> 32); 10279 operands[1] = GEN_INT (((value & 0xffffffff) ^ 0x80000000) - 0x80000000); 10280#endif 10281}") 10282 10283(define_split 10284 [(set (match_operand:DIFD 0 "rs6000_nonimmediate_operand" "") 10285 (match_operand:DIFD 1 "input_operand" ""))] 10286 "reload_completed && !TARGET_POWERPC64 10287 && gpr_or_gpr_p (operands[0], operands[1]) 10288 && !direct_move_p (operands[0], operands[1])" 10289 [(pc)] 10290{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 10291 10292(define_insn "*movdi_internal64" 10293 [(set (match_operand:DI 0 "nonimmediate_operand" "=Y,r,r,r,r,r,?m,?*d,?*d,r,*h,*h,r,?*wg,r,?*wj,?*wi") 10294 (match_operand:DI 1 "input_operand" "r,Y,r,I,L,nF,d,m,d,*h,r,0,*wg,r,*wj,r,O"))] 10295 "TARGET_POWERPC64 10296 && (gpc_reg_operand (operands[0], DImode) 10297 || gpc_reg_operand (operands[1], DImode))" 10298 "@ 10299 std%U0%X0 %1,%0 10300 ld%U1%X1 %0,%1 10301 mr %0,%1 10302 li %0,%1 10303 lis %0,%v1 10304 # 10305 stfd%U0%X0 %1,%0 10306 lfd%U1%X1 %0,%1 10307 fmr %0,%1 10308 mf%1 %0 10309 mt%0 %1 10310 nop 10311 mftgpr %0,%1 10312 mffgpr %0,%1 10313 mfvsrd %0,%x1 10314 mtvsrd %x0,%1 10315 xxlxor %x0,%x0,%x0" 10316 [(set_attr_alternative "type" 10317 [(if_then_else 10318 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 10319 (const_string "store_ux") 10320 (if_then_else 10321 (match_test "update_address_mem (operands[0], VOIDmode)") 10322 (const_string "store_u") 10323 (const_string "store"))) 10324 (if_then_else 10325 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 10326 (const_string "load_ux") 10327 (if_then_else 10328 (match_test "update_address_mem (operands[1], VOIDmode)") 10329 (const_string "load_u") 10330 (const_string "load"))) 10331 (const_string "*") 10332 (const_string "*") 10333 (const_string "*") 10334 (const_string "*") 10335 (if_then_else 10336 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 10337 (const_string "fpstore_ux") 10338 (if_then_else 10339 (match_test "update_address_mem (operands[0], VOIDmode)") 10340 (const_string "fpstore_u") 10341 (const_string "fpstore"))) 10342 (if_then_else 10343 (match_test "update_indexed_address_mem (operands[1], VOIDmode)") 10344 (const_string "fpload_ux") 10345 (if_then_else 10346 (match_test "update_address_mem (operands[1], VOIDmode)") 10347 (const_string "fpload_u") 10348 (const_string "fpload"))) 10349 (const_string "fp") 10350 (const_string "mfjmpr") 10351 (const_string "mtjmpr") 10352 (const_string "*") 10353 (const_string "mftgpr") 10354 (const_string "mffgpr") 10355 (const_string "mftgpr") 10356 (const_string "mffgpr") 10357 (const_string "vecsimple")]) 10358 (set_attr "length" "4,4,4,4,4,20,4,4,4,4,4,4,4,4,4,4,4")]) 10359 10360;; immediate value valid for a single instruction hiding in a const_double 10361(define_insn "" 10362 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 10363 (match_operand:DI 1 "const_double_operand" "F"))] 10364 "HOST_BITS_PER_WIDE_INT == 32 && TARGET_POWERPC64 10365 && GET_CODE (operands[1]) == CONST_DOUBLE 10366 && num_insns_constant (operands[1], DImode) == 1" 10367 "* 10368{ 10369 return ((unsigned HOST_WIDE_INT) 10370 (CONST_DOUBLE_LOW (operands[1]) + 0x8000) < 0x10000) 10371 ? \"li %0,%1\" : \"lis %0,%v1\"; 10372}") 10373 10374;; Generate all one-bits and clear left or right. 10375;; Use (and:DI (rotate:DI ...)) to avoid anddi3 unnecessary clobber. 10376(define_split 10377 [(set (match_operand:DI 0 "gpc_reg_operand" "") 10378 (match_operand:DI 1 "mask64_operand" ""))] 10379 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 10380 [(set (match_dup 0) (const_int -1)) 10381 (set (match_dup 0) 10382 (and:DI (rotate:DI (match_dup 0) 10383 (const_int 0)) 10384 (match_dup 1)))] 10385 "") 10386 10387;; Split a load of a large constant into the appropriate five-instruction 10388;; sequence. Handle anything in a constant number of insns. 10389;; When non-easy constants can go in the TOC, this should use 10390;; easy_fp_constant predicate. 10391(define_split 10392 [(set (match_operand:DI 0 "gpc_reg_operand" "") 10393 (match_operand:DI 1 "const_int_operand" ""))] 10394 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 10395 [(set (match_dup 0) (match_dup 2)) 10396 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 10397 " 10398{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); 10399 10400 if (tem == operands[0]) 10401 DONE; 10402 else 10403 FAIL; 10404}") 10405 10406(define_split 10407 [(set (match_operand:DI 0 "gpc_reg_operand" "") 10408 (match_operand:DI 1 "const_double_operand" ""))] 10409 "TARGET_POWERPC64 && num_insns_constant (operands[1], DImode) > 1" 10410 [(set (match_dup 0) (match_dup 2)) 10411 (set (match_dup 0) (plus:DI (match_dup 0) (match_dup 3)))] 10412 " 10413{ rtx tem = rs6000_emit_set_const (operands[0], DImode, operands[1], 5); 10414 10415 if (tem == operands[0]) 10416 DONE; 10417 else 10418 FAIL; 10419}") 10420 10421;; TImode/PTImode is similar, except that we usually want to compute the 10422;; address into a register and use lsi/stsi (the exception is during reload). 10423 10424(define_insn "*mov<mode>_string" 10425 [(set (match_operand:TI2 0 "reg_or_mem_operand" "=Q,Y,????r,????r,????r,r") 10426 (match_operand:TI2 1 "input_operand" "r,r,Q,Y,r,n"))] 10427 "! TARGET_POWERPC64 10428 && (<MODE>mode != TImode || VECTOR_MEM_NONE_P (TImode)) 10429 && (gpc_reg_operand (operands[0], <MODE>mode) 10430 || gpc_reg_operand (operands[1], <MODE>mode))" 10431 "* 10432{ 10433 switch (which_alternative) 10434 { 10435 default: 10436 gcc_unreachable (); 10437 case 0: 10438 if (TARGET_STRING) 10439 return \"stswi %1,%P0,16\"; 10440 case 1: 10441 return \"#\"; 10442 case 2: 10443 /* If the address is not used in the output, we can use lsi. Otherwise, 10444 fall through to generating four loads. */ 10445 if (TARGET_STRING 10446 && ! reg_overlap_mentioned_p (operands[0], operands[1])) 10447 return \"lswi %0,%P1,16\"; 10448 /* ... fall through ... */ 10449 case 3: 10450 case 4: 10451 case 5: 10452 return \"#\"; 10453 } 10454}" 10455 [(set_attr "type" "store_ux,store_ux,load_ux,load_ux,*,*") 10456 (set (attr "cell_micro") (if_then_else (match_test "TARGET_STRING") 10457 (const_string "always") 10458 (const_string "conditional")))]) 10459 10460(define_insn "*mov<mode>_ppc64" 10461 [(set (match_operand:TI2 0 "nonimmediate_operand" "=wQ,Y,r,r,r,r") 10462 (match_operand:TI2 1 "input_operand" "r,r,wQ,Y,r,n"))] 10463 "(TARGET_POWERPC64 && VECTOR_MEM_NONE_P (<MODE>mode) 10464 && (gpc_reg_operand (operands[0], <MODE>mode) 10465 || gpc_reg_operand (operands[1], <MODE>mode)))" 10466{ 10467 return rs6000_output_move_128bit (operands); 10468} 10469 [(set_attr "type" "store,store,load,load,*,*") 10470 (set_attr "length" "8")]) 10471 10472(define_split 10473 [(set (match_operand:TI2 0 "int_reg_operand" "") 10474 (match_operand:TI2 1 "const_double_operand" ""))] 10475 "TARGET_POWERPC64 10476 && (VECTOR_MEM_NONE_P (<MODE>mode) 10477 || (reload_completed && INT_REGNO_P (REGNO (operands[0]))))" 10478 [(set (match_dup 2) (match_dup 4)) 10479 (set (match_dup 3) (match_dup 5))] 10480 " 10481{ 10482 operands[2] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN == 0, 10483 <MODE>mode); 10484 operands[3] = operand_subword_force (operands[0], WORDS_BIG_ENDIAN != 0, 10485 <MODE>mode); 10486 if (GET_CODE (operands[1]) == CONST_DOUBLE) 10487 { 10488 operands[4] = GEN_INT (CONST_DOUBLE_HIGH (operands[1])); 10489 operands[5] = GEN_INT (CONST_DOUBLE_LOW (operands[1])); 10490 } 10491 else if (GET_CODE (operands[1]) == CONST_INT) 10492 { 10493 operands[4] = GEN_INT (- (INTVAL (operands[1]) < 0)); 10494 operands[5] = operands[1]; 10495 } 10496 else 10497 FAIL; 10498}") 10499 10500(define_split 10501 [(set (match_operand:TI2 0 "nonimmediate_operand" "") 10502 (match_operand:TI2 1 "input_operand" ""))] 10503 "reload_completed 10504 && gpr_or_gpr_p (operands[0], operands[1]) 10505 && !direct_move_p (operands[0], operands[1]) 10506 && !quad_load_store_p (operands[0], operands[1])" 10507 [(pc)] 10508{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; }) 10509 10510(define_expand "load_multiple" 10511 [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 10512 (match_operand:SI 1 "" "")) 10513 (use (match_operand:SI 2 "" ""))])] 10514 "TARGET_STRING && !TARGET_POWERPC64" 10515 " 10516{ 10517 int regno; 10518 int count; 10519 rtx op1; 10520 int i; 10521 10522 /* Support only loading a constant number of fixed-point registers from 10523 memory and only bother with this if more than two; the machine 10524 doesn't support more than eight. */ 10525 if (GET_CODE (operands[2]) != CONST_INT 10526 || INTVAL (operands[2]) <= 2 10527 || INTVAL (operands[2]) > 8 10528 || GET_CODE (operands[1]) != MEM 10529 || GET_CODE (operands[0]) != REG 10530 || REGNO (operands[0]) >= 32) 10531 FAIL; 10532 10533 count = INTVAL (operands[2]); 10534 regno = REGNO (operands[0]); 10535 10536 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count)); 10537 op1 = replace_equiv_address (operands[1], 10538 force_reg (SImode, XEXP (operands[1], 0))); 10539 10540 for (i = 0; i < count; i++) 10541 XVECEXP (operands[3], 0, i) 10542 = gen_rtx_SET (VOIDmode, gen_rtx_REG (SImode, regno + i), 10543 adjust_address_nv (op1, SImode, i * 4)); 10544}") 10545 10546(define_insn "*ldmsi8" 10547 [(match_parallel 0 "load_multiple_operation" 10548 [(set (match_operand:SI 2 "gpc_reg_operand" "") 10549 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 10550 (set (match_operand:SI 3 "gpc_reg_operand" "") 10551 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 10552 (set (match_operand:SI 4 "gpc_reg_operand" "") 10553 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 10554 (set (match_operand:SI 5 "gpc_reg_operand" "") 10555 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 10556 (set (match_operand:SI 6 "gpc_reg_operand" "") 10557 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) 10558 (set (match_operand:SI 7 "gpc_reg_operand" "") 10559 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) 10560 (set (match_operand:SI 8 "gpc_reg_operand" "") 10561 (mem:SI (plus:SI (match_dup 1) (const_int 24)))) 10562 (set (match_operand:SI 9 "gpc_reg_operand" "") 10563 (mem:SI (plus:SI (match_dup 1) (const_int 28))))])] 10564 "TARGET_STRING && XVECLEN (operands[0], 0) == 8" 10565 "* 10566{ return rs6000_output_load_multiple (operands); }" 10567 [(set_attr "type" "load_ux") 10568 (set_attr "length" "32")]) 10569 10570(define_insn "*ldmsi7" 10571 [(match_parallel 0 "load_multiple_operation" 10572 [(set (match_operand:SI 2 "gpc_reg_operand" "") 10573 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 10574 (set (match_operand:SI 3 "gpc_reg_operand" "") 10575 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 10576 (set (match_operand:SI 4 "gpc_reg_operand" "") 10577 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 10578 (set (match_operand:SI 5 "gpc_reg_operand" "") 10579 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 10580 (set (match_operand:SI 6 "gpc_reg_operand" "") 10581 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) 10582 (set (match_operand:SI 7 "gpc_reg_operand" "") 10583 (mem:SI (plus:SI (match_dup 1) (const_int 20)))) 10584 (set (match_operand:SI 8 "gpc_reg_operand" "") 10585 (mem:SI (plus:SI (match_dup 1) (const_int 24))))])] 10586 "TARGET_STRING && XVECLEN (operands[0], 0) == 7" 10587 "* 10588{ return rs6000_output_load_multiple (operands); }" 10589 [(set_attr "type" "load_ux") 10590 (set_attr "length" "32")]) 10591 10592(define_insn "*ldmsi6" 10593 [(match_parallel 0 "load_multiple_operation" 10594 [(set (match_operand:SI 2 "gpc_reg_operand" "") 10595 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 10596 (set (match_operand:SI 3 "gpc_reg_operand" "") 10597 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 10598 (set (match_operand:SI 4 "gpc_reg_operand" "") 10599 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 10600 (set (match_operand:SI 5 "gpc_reg_operand" "") 10601 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 10602 (set (match_operand:SI 6 "gpc_reg_operand" "") 10603 (mem:SI (plus:SI (match_dup 1) (const_int 16)))) 10604 (set (match_operand:SI 7 "gpc_reg_operand" "") 10605 (mem:SI (plus:SI (match_dup 1) (const_int 20))))])] 10606 "TARGET_STRING && XVECLEN (operands[0], 0) == 6" 10607 "* 10608{ return rs6000_output_load_multiple (operands); }" 10609 [(set_attr "type" "load_ux") 10610 (set_attr "length" "32")]) 10611 10612(define_insn "*ldmsi5" 10613 [(match_parallel 0 "load_multiple_operation" 10614 [(set (match_operand:SI 2 "gpc_reg_operand" "") 10615 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 10616 (set (match_operand:SI 3 "gpc_reg_operand" "") 10617 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 10618 (set (match_operand:SI 4 "gpc_reg_operand" "") 10619 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 10620 (set (match_operand:SI 5 "gpc_reg_operand" "") 10621 (mem:SI (plus:SI (match_dup 1) (const_int 12)))) 10622 (set (match_operand:SI 6 "gpc_reg_operand" "") 10623 (mem:SI (plus:SI (match_dup 1) (const_int 16))))])] 10624 "TARGET_STRING && XVECLEN (operands[0], 0) == 5" 10625 "* 10626{ return rs6000_output_load_multiple (operands); }" 10627 [(set_attr "type" "load_ux") 10628 (set_attr "length" "32")]) 10629 10630(define_insn "*ldmsi4" 10631 [(match_parallel 0 "load_multiple_operation" 10632 [(set (match_operand:SI 2 "gpc_reg_operand" "") 10633 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 10634 (set (match_operand:SI 3 "gpc_reg_operand" "") 10635 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 10636 (set (match_operand:SI 4 "gpc_reg_operand" "") 10637 (mem:SI (plus:SI (match_dup 1) (const_int 8)))) 10638 (set (match_operand:SI 5 "gpc_reg_operand" "") 10639 (mem:SI (plus:SI (match_dup 1) (const_int 12))))])] 10640 "TARGET_STRING && XVECLEN (operands[0], 0) == 4" 10641 "* 10642{ return rs6000_output_load_multiple (operands); }" 10643 [(set_attr "type" "load_ux") 10644 (set_attr "length" "32")]) 10645 10646(define_insn "*ldmsi3" 10647 [(match_parallel 0 "load_multiple_operation" 10648 [(set (match_operand:SI 2 "gpc_reg_operand" "") 10649 (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b"))) 10650 (set (match_operand:SI 3 "gpc_reg_operand" "") 10651 (mem:SI (plus:SI (match_dup 1) (const_int 4)))) 10652 (set (match_operand:SI 4 "gpc_reg_operand" "") 10653 (mem:SI (plus:SI (match_dup 1) (const_int 8))))])] 10654 "TARGET_STRING && XVECLEN (operands[0], 0) == 3" 10655 "* 10656{ return rs6000_output_load_multiple (operands); }" 10657 [(set_attr "type" "load_ux") 10658 (set_attr "length" "32")]) 10659 10660(define_expand "store_multiple" 10661 [(match_par_dup 3 [(set (match_operand:SI 0 "" "") 10662 (match_operand:SI 1 "" "")) 10663 (clobber (scratch:SI)) 10664 (use (match_operand:SI 2 "" ""))])] 10665 "TARGET_STRING && !TARGET_POWERPC64" 10666 " 10667{ 10668 int regno; 10669 int count; 10670 rtx to; 10671 rtx op0; 10672 int i; 10673 10674 /* Support only storing a constant number of fixed-point registers to 10675 memory and only bother with this if more than two; the machine 10676 doesn't support more than eight. */ 10677 if (GET_CODE (operands[2]) != CONST_INT 10678 || INTVAL (operands[2]) <= 2 10679 || INTVAL (operands[2]) > 8 10680 || GET_CODE (operands[0]) != MEM 10681 || GET_CODE (operands[1]) != REG 10682 || REGNO (operands[1]) >= 32) 10683 FAIL; 10684 10685 count = INTVAL (operands[2]); 10686 regno = REGNO (operands[1]); 10687 10688 operands[3] = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (count + 1)); 10689 to = force_reg (SImode, XEXP (operands[0], 0)); 10690 op0 = replace_equiv_address (operands[0], to); 10691 10692 XVECEXP (operands[3], 0, 0) 10693 = gen_rtx_SET (VOIDmode, adjust_address_nv (op0, SImode, 0), operands[1]); 10694 XVECEXP (operands[3], 0, 1) = gen_rtx_CLOBBER (VOIDmode, 10695 gen_rtx_SCRATCH (SImode)); 10696 10697 for (i = 1; i < count; i++) 10698 XVECEXP (operands[3], 0, i + 1) 10699 = gen_rtx_SET (VOIDmode, 10700 adjust_address_nv (op0, SImode, i * 4), 10701 gen_rtx_REG (SImode, regno + i)); 10702}") 10703 10704(define_insn "*stmsi8" 10705 [(match_parallel 0 "store_multiple_operation" 10706 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 10707 (match_operand:SI 2 "gpc_reg_operand" "r")) 10708 (clobber (match_scratch:SI 3 "=X")) 10709 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 10710 (match_operand:SI 4 "gpc_reg_operand" "r")) 10711 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 10712 (match_operand:SI 5 "gpc_reg_operand" "r")) 10713 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 10714 (match_operand:SI 6 "gpc_reg_operand" "r")) 10715 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 10716 (match_operand:SI 7 "gpc_reg_operand" "r")) 10717 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 10718 (match_operand:SI 8 "gpc_reg_operand" "r")) 10719 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) 10720 (match_operand:SI 9 "gpc_reg_operand" "r")) 10721 (set (mem:SI (plus:SI (match_dup 1) (const_int 28))) 10722 (match_operand:SI 10 "gpc_reg_operand" "r"))])] 10723 "TARGET_STRING && XVECLEN (operands[0], 0) == 9" 10724 "stswi %2,%1,%O0" 10725 [(set_attr "type" "store_ux") 10726 (set_attr "cell_micro" "always")]) 10727 10728(define_insn "*stmsi7" 10729 [(match_parallel 0 "store_multiple_operation" 10730 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 10731 (match_operand:SI 2 "gpc_reg_operand" "r")) 10732 (clobber (match_scratch:SI 3 "=X")) 10733 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 10734 (match_operand:SI 4 "gpc_reg_operand" "r")) 10735 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 10736 (match_operand:SI 5 "gpc_reg_operand" "r")) 10737 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 10738 (match_operand:SI 6 "gpc_reg_operand" "r")) 10739 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 10740 (match_operand:SI 7 "gpc_reg_operand" "r")) 10741 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 10742 (match_operand:SI 8 "gpc_reg_operand" "r")) 10743 (set (mem:SI (plus:SI (match_dup 1) (const_int 24))) 10744 (match_operand:SI 9 "gpc_reg_operand" "r"))])] 10745 "TARGET_STRING && XVECLEN (operands[0], 0) == 8" 10746 "stswi %2,%1,%O0" 10747 [(set_attr "type" "store_ux") 10748 (set_attr "cell_micro" "always")]) 10749 10750(define_insn "*stmsi6" 10751 [(match_parallel 0 "store_multiple_operation" 10752 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 10753 (match_operand:SI 2 "gpc_reg_operand" "r")) 10754 (clobber (match_scratch:SI 3 "=X")) 10755 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 10756 (match_operand:SI 4 "gpc_reg_operand" "r")) 10757 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 10758 (match_operand:SI 5 "gpc_reg_operand" "r")) 10759 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 10760 (match_operand:SI 6 "gpc_reg_operand" "r")) 10761 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 10762 (match_operand:SI 7 "gpc_reg_operand" "r")) 10763 (set (mem:SI (plus:SI (match_dup 1) (const_int 20))) 10764 (match_operand:SI 8 "gpc_reg_operand" "r"))])] 10765 "TARGET_STRING && XVECLEN (operands[0], 0) == 7" 10766 "stswi %2,%1,%O0" 10767 [(set_attr "type" "store_ux") 10768 (set_attr "cell_micro" "always")]) 10769 10770(define_insn "*stmsi5" 10771 [(match_parallel 0 "store_multiple_operation" 10772 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 10773 (match_operand:SI 2 "gpc_reg_operand" "r")) 10774 (clobber (match_scratch:SI 3 "=X")) 10775 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 10776 (match_operand:SI 4 "gpc_reg_operand" "r")) 10777 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 10778 (match_operand:SI 5 "gpc_reg_operand" "r")) 10779 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 10780 (match_operand:SI 6 "gpc_reg_operand" "r")) 10781 (set (mem:SI (plus:SI (match_dup 1) (const_int 16))) 10782 (match_operand:SI 7 "gpc_reg_operand" "r"))])] 10783 "TARGET_STRING && XVECLEN (operands[0], 0) == 6" 10784 "stswi %2,%1,%O0" 10785 [(set_attr "type" "store_ux") 10786 (set_attr "cell_micro" "always")]) 10787 10788(define_insn "*stmsi4" 10789 [(match_parallel 0 "store_multiple_operation" 10790 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 10791 (match_operand:SI 2 "gpc_reg_operand" "r")) 10792 (clobber (match_scratch:SI 3 "=X")) 10793 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 10794 (match_operand:SI 4 "gpc_reg_operand" "r")) 10795 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 10796 (match_operand:SI 5 "gpc_reg_operand" "r")) 10797 (set (mem:SI (plus:SI (match_dup 1) (const_int 12))) 10798 (match_operand:SI 6 "gpc_reg_operand" "r"))])] 10799 "TARGET_STRING && XVECLEN (operands[0], 0) == 5" 10800 "stswi %2,%1,%O0" 10801 [(set_attr "type" "store_ux") 10802 (set_attr "cell_micro" "always")]) 10803 10804(define_insn "*stmsi3" 10805 [(match_parallel 0 "store_multiple_operation" 10806 [(set (mem:SI (match_operand:SI 1 "gpc_reg_operand" "b")) 10807 (match_operand:SI 2 "gpc_reg_operand" "r")) 10808 (clobber (match_scratch:SI 3 "=X")) 10809 (set (mem:SI (plus:SI (match_dup 1) (const_int 4))) 10810 (match_operand:SI 4 "gpc_reg_operand" "r")) 10811 (set (mem:SI (plus:SI (match_dup 1) (const_int 8))) 10812 (match_operand:SI 5 "gpc_reg_operand" "r"))])] 10813 "TARGET_STRING && XVECLEN (operands[0], 0) == 4" 10814 "stswi %2,%1,%O0" 10815 [(set_attr "type" "store_ux") 10816 (set_attr "cell_micro" "always")]) 10817 10818(define_expand "setmemsi" 10819 [(parallel [(set (match_operand:BLK 0 "" "") 10820 (match_operand 2 "const_int_operand" "")) 10821 (use (match_operand:SI 1 "" "")) 10822 (use (match_operand:SI 3 "" ""))])] 10823 "" 10824 " 10825{ 10826 /* If value to set is not zero, use the library routine. */ 10827 if (operands[2] != const0_rtx) 10828 FAIL; 10829 10830 if (expand_block_clear (operands)) 10831 DONE; 10832 else 10833 FAIL; 10834}") 10835 10836;; String/block move insn. 10837;; Argument 0 is the destination 10838;; Argument 1 is the source 10839;; Argument 2 is the length 10840;; Argument 3 is the alignment 10841 10842(define_expand "movmemsi" 10843 [(parallel [(set (match_operand:BLK 0 "" "") 10844 (match_operand:BLK 1 "" "")) 10845 (use (match_operand:SI 2 "" "")) 10846 (use (match_operand:SI 3 "" ""))])] 10847 "" 10848 " 10849{ 10850 if (expand_block_move (operands)) 10851 DONE; 10852 else 10853 FAIL; 10854}") 10855 10856;; Move up to 32 bytes at a time. The fixed registers are needed because the 10857;; register allocator doesn't have a clue about allocating 8 word registers. 10858;; rD/rS = r5 is preferred, efficient form. 10859(define_expand "movmemsi_8reg" 10860 [(parallel [(set (match_operand 0 "" "") 10861 (match_operand 1 "" "")) 10862 (use (match_operand 2 "" "")) 10863 (use (match_operand 3 "" "")) 10864 (clobber (reg:SI 5)) 10865 (clobber (reg:SI 6)) 10866 (clobber (reg:SI 7)) 10867 (clobber (reg:SI 8)) 10868 (clobber (reg:SI 9)) 10869 (clobber (reg:SI 10)) 10870 (clobber (reg:SI 11)) 10871 (clobber (reg:SI 12)) 10872 (clobber (match_scratch:SI 4 ""))])] 10873 "TARGET_STRING" 10874 "") 10875 10876(define_insn "" 10877 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) 10878 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) 10879 (use (match_operand:SI 2 "immediate_operand" "i")) 10880 (use (match_operand:SI 3 "immediate_operand" "i")) 10881 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r")) 10882 (clobber (reg:SI 6)) 10883 (clobber (reg:SI 7)) 10884 (clobber (reg:SI 8)) 10885 (clobber (reg:SI 9)) 10886 (clobber (reg:SI 10)) 10887 (clobber (reg:SI 11)) 10888 (clobber (reg:SI 12)) 10889 (clobber (match_scratch:SI 5 "=X"))] 10890 "TARGET_STRING 10891 && ((INTVAL (operands[2]) > 24 && INTVAL (operands[2]) < 32) 10892 || INTVAL (operands[2]) == 0) 10893 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 12) 10894 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 12) 10895 && REGNO (operands[4]) == 5" 10896 "lswi %4,%1,%2\;stswi %4,%0,%2" 10897 [(set_attr "type" "store_ux") 10898 (set_attr "cell_micro" "always") 10899 (set_attr "length" "8")]) 10900 10901;; Move up to 24 bytes at a time. The fixed registers are needed because the 10902;; register allocator doesn't have a clue about allocating 6 word registers. 10903;; rD/rS = r5 is preferred, efficient form. 10904(define_expand "movmemsi_6reg" 10905 [(parallel [(set (match_operand 0 "" "") 10906 (match_operand 1 "" "")) 10907 (use (match_operand 2 "" "")) 10908 (use (match_operand 3 "" "")) 10909 (clobber (reg:SI 5)) 10910 (clobber (reg:SI 6)) 10911 (clobber (reg:SI 7)) 10912 (clobber (reg:SI 8)) 10913 (clobber (reg:SI 9)) 10914 (clobber (reg:SI 10)) 10915 (clobber (match_scratch:SI 4 ""))])] 10916 "TARGET_STRING" 10917 "") 10918 10919(define_insn "" 10920 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) 10921 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) 10922 (use (match_operand:SI 2 "immediate_operand" "i")) 10923 (use (match_operand:SI 3 "immediate_operand" "i")) 10924 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r")) 10925 (clobber (reg:SI 6)) 10926 (clobber (reg:SI 7)) 10927 (clobber (reg:SI 8)) 10928 (clobber (reg:SI 9)) 10929 (clobber (reg:SI 10)) 10930 (clobber (match_scratch:SI 5 "=X"))] 10931 "TARGET_STRING 10932 && INTVAL (operands[2]) > 16 && INTVAL (operands[2]) <= 32 10933 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 10) 10934 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 10) 10935 && REGNO (operands[4]) == 5" 10936 "lswi %4,%1,%2\;stswi %4,%0,%2" 10937 [(set_attr "type" "store_ux") 10938 (set_attr "cell_micro" "always") 10939 (set_attr "length" "8")]) 10940 10941;; Move up to 16 bytes at a time, using 4 fixed registers to avoid spill 10942;; problems with TImode. 10943;; rD/rS = r5 is preferred, efficient form. 10944(define_expand "movmemsi_4reg" 10945 [(parallel [(set (match_operand 0 "" "") 10946 (match_operand 1 "" "")) 10947 (use (match_operand 2 "" "")) 10948 (use (match_operand 3 "" "")) 10949 (clobber (reg:SI 5)) 10950 (clobber (reg:SI 6)) 10951 (clobber (reg:SI 7)) 10952 (clobber (reg:SI 8)) 10953 (clobber (match_scratch:SI 4 ""))])] 10954 "TARGET_STRING" 10955 "") 10956 10957(define_insn "" 10958 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) 10959 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) 10960 (use (match_operand:SI 2 "immediate_operand" "i")) 10961 (use (match_operand:SI 3 "immediate_operand" "i")) 10962 (clobber (match_operand:SI 4 "gpc_reg_operand" "=&r")) 10963 (clobber (reg:SI 6)) 10964 (clobber (reg:SI 7)) 10965 (clobber (reg:SI 8)) 10966 (clobber (match_scratch:SI 5 "=X"))] 10967 "TARGET_STRING 10968 && INTVAL (operands[2]) > 8 && INTVAL (operands[2]) <= 16 10969 && (REGNO (operands[0]) < 5 || REGNO (operands[0]) > 8) 10970 && (REGNO (operands[1]) < 5 || REGNO (operands[1]) > 8) 10971 && REGNO (operands[4]) == 5" 10972 "lswi %4,%1,%2\;stswi %4,%0,%2" 10973 [(set_attr "type" "store_ux") 10974 (set_attr "cell_micro" "always") 10975 (set_attr "length" "8")]) 10976 10977;; Move up to 8 bytes at a time. 10978(define_expand "movmemsi_2reg" 10979 [(parallel [(set (match_operand 0 "" "") 10980 (match_operand 1 "" "")) 10981 (use (match_operand 2 "" "")) 10982 (use (match_operand 3 "" "")) 10983 (clobber (match_scratch:DI 4 "")) 10984 (clobber (match_scratch:SI 5 ""))])] 10985 "TARGET_STRING && ! TARGET_POWERPC64" 10986 "") 10987 10988(define_insn "" 10989 [(set (mem:BLK (match_operand:SI 0 "gpc_reg_operand" "b")) 10990 (mem:BLK (match_operand:SI 1 "gpc_reg_operand" "b"))) 10991 (use (match_operand:SI 2 "immediate_operand" "i")) 10992 (use (match_operand:SI 3 "immediate_operand" "i")) 10993 (clobber (match_scratch:DI 4 "=&r")) 10994 (clobber (match_scratch:SI 5 "=X"))] 10995 "TARGET_STRING && ! TARGET_POWERPC64 10996 && INTVAL (operands[2]) > 4 && INTVAL (operands[2]) <= 8" 10997 "lswi %4,%1,%2\;stswi %4,%0,%2" 10998 [(set_attr "type" "store_ux") 10999 (set_attr "cell_micro" "always") 11000 (set_attr "length" "8")]) 11001 11002;; Move up to 4 bytes at a time. 11003(define_expand "movmemsi_1reg" 11004 [(parallel [(set (match_operand 0 "" "") 11005 (match_operand 1 "" "")) 11006 (use (match_operand 2 "" "")) 11007 (use (match_operand 3 "" "")) 11008 (clobber (match_scratch:SI 4 "")) 11009 (clobber (match_scratch:SI 5 ""))])] 11010 "TARGET_STRING" 11011 "") 11012 11013(define_insn "" 11014 [(set (mem:BLK (match_operand:P 0 "gpc_reg_operand" "b")) 11015 (mem:BLK (match_operand:P 1 "gpc_reg_operand" "b"))) 11016 (use (match_operand:SI 2 "immediate_operand" "i")) 11017 (use (match_operand:SI 3 "immediate_operand" "i")) 11018 (clobber (match_scratch:SI 4 "=&r")) 11019 (clobber (match_scratch:SI 5 "=X"))] 11020 "TARGET_STRING && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 4" 11021 "lswi %4,%1,%2\;stswi %4,%0,%2" 11022 [(set_attr "type" "store_ux") 11023 (set_attr "cell_micro" "always") 11024 (set_attr "length" "8")]) 11025 11026;; Define insns that do load or store with update. Some of these we can 11027;; get by using pre-decrement or pre-increment, but the hardware can also 11028;; do cases where the increment is not the size of the object. 11029;; 11030;; In all these cases, we use operands 0 and 1 for the register being 11031;; incremented because those are the operands that local-alloc will 11032;; tie and these are the pair most likely to be tieable (and the ones 11033;; that will benefit the most). 11034 11035(define_insn "*movdi_update1" 11036 [(set (match_operand:DI 3 "gpc_reg_operand" "=r,r") 11037 (mem:DI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0,0") 11038 (match_operand:DI 2 "reg_or_aligned_short_operand" "r,I")))) 11039 (set (match_operand:DI 0 "gpc_reg_operand" "=b,b") 11040 (plus:DI (match_dup 1) (match_dup 2)))] 11041 "TARGET_POWERPC64 && TARGET_UPDATE 11042 && (!avoiding_indexed_address_p (DImode) 11043 || !gpc_reg_operand (operands[2], DImode))" 11044 "@ 11045 ldux %3,%0,%2 11046 ldu %3,%2(%0)" 11047 [(set_attr "type" "load_ux,load_u")]) 11048 11049(define_insn "movdi_<mode>_update" 11050 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") 11051 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) 11052 (match_operand:DI 3 "gpc_reg_operand" "r,r")) 11053 (set (match_operand:P 0 "gpc_reg_operand" "=b,b") 11054 (plus:P (match_dup 1) (match_dup 2)))] 11055 "TARGET_POWERPC64 && TARGET_UPDATE 11056 && (!avoiding_indexed_address_p (Pmode) 11057 || !gpc_reg_operand (operands[2], Pmode) 11058 || (REG_P (operands[0]) 11059 && REGNO (operands[0]) == STACK_POINTER_REGNUM))" 11060 "@ 11061 stdux %3,%0,%2 11062 stdu %3,%2(%0)" 11063 [(set_attr "type" "store_ux,store_u")]) 11064 11065;; This pattern is only conditional on TARGET_POWERPC64, as it is 11066;; needed for stack allocation, even if the user passes -mno-update. 11067(define_insn "movdi_<mode>_update_stack" 11068 [(set (mem:DI (plus:P (match_operand:P 1 "gpc_reg_operand" "0,0") 11069 (match_operand:P 2 "reg_or_aligned_short_operand" "r,I"))) 11070 (match_operand:DI 3 "gpc_reg_operand" "r,r")) 11071 (set (match_operand:P 0 "gpc_reg_operand" "=b,b") 11072 (plus:P (match_dup 1) (match_dup 2)))] 11073 "TARGET_POWERPC64" 11074 "@ 11075 stdux %3,%0,%2 11076 stdu %3,%2(%0)" 11077 [(set_attr "type" "store_ux,store_u")]) 11078 11079(define_insn "*movsi_update1" 11080 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 11081 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11082 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 11083 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11084 (plus:SI (match_dup 1) (match_dup 2)))] 11085 "TARGET_UPDATE 11086 && (!avoiding_indexed_address_p (SImode) 11087 || !gpc_reg_operand (operands[2], SImode))" 11088 "@ 11089 lwzux %3,%0,%2 11090 lwzu %3,%2(%0)" 11091 [(set_attr "type" "load_ux,load_u")]) 11092 11093(define_insn "*movsi_update2" 11094 [(set (match_operand:DI 3 "gpc_reg_operand" "=r") 11095 (sign_extend:DI 11096 (mem:SI (plus:DI (match_operand:DI 1 "gpc_reg_operand" "0") 11097 (match_operand:DI 2 "gpc_reg_operand" "r"))))) 11098 (set (match_operand:DI 0 "gpc_reg_operand" "=b") 11099 (plus:DI (match_dup 1) (match_dup 2)))] 11100 "TARGET_POWERPC64 && rs6000_gen_cell_microcode 11101 && !avoiding_indexed_address_p (DImode)" 11102 "lwaux %3,%0,%2" 11103 [(set_attr "type" "load_ext_ux")]) 11104 11105(define_insn "movsi_update" 11106 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11107 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 11108 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11109 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11110 (plus:SI (match_dup 1) (match_dup 2)))] 11111 "TARGET_UPDATE 11112 && (!avoiding_indexed_address_p (SImode) 11113 || !gpc_reg_operand (operands[2], SImode) 11114 || (REG_P (operands[0]) 11115 && REGNO (operands[0]) == STACK_POINTER_REGNUM))" 11116 "@ 11117 stwux %3,%0,%2 11118 stwu %3,%2(%0)" 11119 [(set_attr "type" "store_ux,store_u")]) 11120 11121;; This is an unconditional pattern; needed for stack allocation, even 11122;; if the user passes -mno-update. 11123(define_insn "movsi_update_stack" 11124 [(set (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11125 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 11126 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 11127 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11128 (plus:SI (match_dup 1) (match_dup 2)))] 11129 "" 11130 "@ 11131 stwux %3,%0,%2 11132 stwu %3,%2(%0)" 11133 [(set_attr "type" "store_ux,store_u")]) 11134 11135(define_insn "*movhi_update1" 11136 [(set (match_operand:HI 3 "gpc_reg_operand" "=r,r") 11137 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11138 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 11139 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11140 (plus:SI (match_dup 1) (match_dup 2)))] 11141 "TARGET_UPDATE 11142 && (!avoiding_indexed_address_p (SImode) 11143 || !gpc_reg_operand (operands[2], SImode))" 11144 "@ 11145 lhzux %3,%0,%2 11146 lhzu %3,%2(%0)" 11147 [(set_attr "type" "load_ux,load_u")]) 11148 11149(define_insn "*movhi_update2" 11150 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 11151 (zero_extend:SI 11152 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11153 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 11154 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11155 (plus:SI (match_dup 1) (match_dup 2)))] 11156 "TARGET_UPDATE 11157 && (!avoiding_indexed_address_p (SImode) 11158 || !gpc_reg_operand (operands[2], SImode))" 11159 "@ 11160 lhzux %3,%0,%2 11161 lhzu %3,%2(%0)" 11162 [(set_attr "type" "load_ux,load_u")]) 11163 11164(define_insn "*movhi_update3" 11165 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 11166 (sign_extend:SI 11167 (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11168 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 11169 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11170 (plus:SI (match_dup 1) (match_dup 2)))] 11171 "TARGET_UPDATE && rs6000_gen_cell_microcode 11172 && (!avoiding_indexed_address_p (SImode) 11173 || !gpc_reg_operand (operands[2], SImode))" 11174 "@ 11175 lhaux %3,%0,%2 11176 lhau %3,%2(%0)" 11177 [(set_attr "type" "load_ext_ux,load_ext_u")]) 11178 11179(define_insn "*movhi_update4" 11180 [(set (mem:HI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11181 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 11182 (match_operand:HI 3 "gpc_reg_operand" "r,r")) 11183 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11184 (plus:SI (match_dup 1) (match_dup 2)))] 11185 "TARGET_UPDATE 11186 && (!avoiding_indexed_address_p (SImode) 11187 || !gpc_reg_operand (operands[2], SImode))" 11188 "@ 11189 sthux %3,%0,%2 11190 sthu %3,%2(%0)" 11191 [(set_attr "type" "store_ux,store_u")]) 11192 11193(define_insn "*movqi_update1" 11194 [(set (match_operand:QI 3 "gpc_reg_operand" "=r,r") 11195 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11196 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 11197 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11198 (plus:SI (match_dup 1) (match_dup 2)))] 11199 "TARGET_UPDATE 11200 && (!avoiding_indexed_address_p (SImode) 11201 || !gpc_reg_operand (operands[2], SImode))" 11202 "@ 11203 lbzux %3,%0,%2 11204 lbzu %3,%2(%0)" 11205 [(set_attr "type" "load_ux,load_u")]) 11206 11207(define_insn "*movqi_update2" 11208 [(set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 11209 (zero_extend:SI 11210 (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11211 (match_operand:SI 2 "reg_or_short_operand" "r,I"))))) 11212 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11213 (plus:SI (match_dup 1) (match_dup 2)))] 11214 "TARGET_UPDATE 11215 && (!avoiding_indexed_address_p (SImode) 11216 || !gpc_reg_operand (operands[2], SImode))" 11217 "@ 11218 lbzux %3,%0,%2 11219 lbzu %3,%2(%0)" 11220 [(set_attr "type" "load_ux,load_u")]) 11221 11222(define_insn "*movqi_update3" 11223 [(set (mem:QI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11224 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 11225 (match_operand:QI 3 "gpc_reg_operand" "r,r")) 11226 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11227 (plus:SI (match_dup 1) (match_dup 2)))] 11228 "TARGET_UPDATE 11229 && (!avoiding_indexed_address_p (SImode) 11230 || !gpc_reg_operand (operands[2], SImode))" 11231 "@ 11232 stbux %3,%0,%2 11233 stbu %3,%2(%0)" 11234 [(set_attr "type" "store_ux,store_u")]) 11235 11236(define_insn "*movsf_update1" 11237 [(set (match_operand:SF 3 "gpc_reg_operand" "=f,f") 11238 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11239 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 11240 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11241 (plus:SI (match_dup 1) (match_dup 2)))] 11242 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE 11243 && (!avoiding_indexed_address_p (SImode) 11244 || !gpc_reg_operand (operands[2], SImode))" 11245 "@ 11246 lfsux %3,%0,%2 11247 lfsu %3,%2(%0)" 11248 [(set_attr "type" "fpload_ux,fpload_u")]) 11249 11250(define_insn "*movsf_update2" 11251 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11252 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 11253 (match_operand:SF 3 "gpc_reg_operand" "f,f")) 11254 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11255 (plus:SI (match_dup 1) (match_dup 2)))] 11256 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_SINGLE_FLOAT && TARGET_UPDATE 11257 && (!avoiding_indexed_address_p (SImode) 11258 || !gpc_reg_operand (operands[2], SImode))" 11259 "@ 11260 stfsux %3,%0,%2 11261 stfsu %3,%2(%0)" 11262 [(set_attr "type" "fpstore_ux,fpstore_u")]) 11263 11264(define_insn "*movsf_update3" 11265 [(set (match_operand:SF 3 "gpc_reg_operand" "=r,r") 11266 (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11267 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 11268 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11269 (plus:SI (match_dup 1) (match_dup 2)))] 11270 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE 11271 && (!avoiding_indexed_address_p (SImode) 11272 || !gpc_reg_operand (operands[2], SImode))" 11273 "@ 11274 lwzux %3,%0,%2 11275 lwzu %3,%2(%0)" 11276 [(set_attr "type" "load_ux,load_u")]) 11277 11278(define_insn "*movsf_update4" 11279 [(set (mem:SF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11280 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 11281 (match_operand:SF 3 "gpc_reg_operand" "r,r")) 11282 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11283 (plus:SI (match_dup 1) (match_dup 2)))] 11284 "(TARGET_SOFT_FLOAT || !TARGET_FPRS) && TARGET_UPDATE 11285 && (!avoiding_indexed_address_p (SImode) 11286 || !gpc_reg_operand (operands[2], SImode))" 11287 "@ 11288 stwux %3,%0,%2 11289 stwu %3,%2(%0)" 11290 [(set_attr "type" "store_ux,store_u")]) 11291 11292(define_insn "*movdf_update1" 11293 [(set (match_operand:DF 3 "gpc_reg_operand" "=d,d") 11294 (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11295 (match_operand:SI 2 "reg_or_short_operand" "r,I")))) 11296 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11297 (plus:SI (match_dup 1) (match_dup 2)))] 11298 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE 11299 && (!avoiding_indexed_address_p (SImode) 11300 || !gpc_reg_operand (operands[2], SImode))" 11301 "@ 11302 lfdux %3,%0,%2 11303 lfdu %3,%2(%0)" 11304 [(set_attr "type" "fpload_ux,fpload_u")]) 11305 11306(define_insn "*movdf_update2" 11307 [(set (mem:DF (plus:SI (match_operand:SI 1 "gpc_reg_operand" "0,0") 11308 (match_operand:SI 2 "reg_or_short_operand" "r,I"))) 11309 (match_operand:DF 3 "gpc_reg_operand" "d,d")) 11310 (set (match_operand:SI 0 "gpc_reg_operand" "=b,b") 11311 (plus:SI (match_dup 1) (match_dup 2)))] 11312 "TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_UPDATE 11313 && (!avoiding_indexed_address_p (SImode) 11314 || !gpc_reg_operand (operands[2], SImode))" 11315 "@ 11316 stfdux %3,%0,%2 11317 stfdu %3,%2(%0)" 11318 [(set_attr "type" "fpstore_ux,fpstore_u")]) 11319 11320 11321;; After inserting conditional returns we can sometimes have 11322;; unnecessary register moves. Unfortunately we cannot have a 11323;; modeless peephole here, because some single SImode sets have early 11324;; clobber outputs. Although those sets expand to multi-ppc-insn 11325;; sequences, using get_attr_length here will smash the operands 11326;; array. Neither is there an early_cobbler_p predicate. 11327;; Disallow subregs for E500 so we don't munge frob_di_df_2. 11328(define_peephole2 11329 [(set (match_operand:DF 0 "gpc_reg_operand" "") 11330 (match_operand:DF 1 "any_operand" "")) 11331 (set (match_operand:DF 2 "gpc_reg_operand" "") 11332 (match_dup 0))] 11333 "!(TARGET_E500_DOUBLE && GET_CODE (operands[2]) == SUBREG) 11334 && peep2_reg_dead_p (2, operands[0])" 11335 [(set (match_dup 2) (match_dup 1))]) 11336 11337(define_peephole2 11338 [(set (match_operand:SF 0 "gpc_reg_operand" "") 11339 (match_operand:SF 1 "any_operand" "")) 11340 (set (match_operand:SF 2 "gpc_reg_operand" "") 11341 (match_dup 0))] 11342 "peep2_reg_dead_p (2, operands[0])" 11343 [(set (match_dup 2) (match_dup 1))]) 11344 11345 11346;; TLS support. 11347 11348;; Mode attributes for different ABIs. 11349(define_mode_iterator TLSmode [(SI "! TARGET_64BIT") (DI "TARGET_64BIT")]) 11350(define_mode_attr tls_abi_suffix [(SI "32") (DI "64")]) 11351(define_mode_attr tls_sysv_suffix [(SI "si") (DI "di")]) 11352(define_mode_attr tls_insn_suffix [(SI "wz") (DI "d")]) 11353 11354(define_insn_and_split "tls_gd_aix<TLSmode:tls_abi_suffix>" 11355 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11356 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s")) 11357 (match_operand 4 "" "g"))) 11358 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11359 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11360 UNSPEC_TLSGD) 11361 (clobber (reg:SI LR_REGNO))] 11362 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)" 11363{ 11364 if (TARGET_CMODEL != CMODEL_SMALL) 11365 return "addis %0,%1,%2@got@tlsgd@ha\;addi %0,%0,%2@got@tlsgd@l\;" 11366 "bl %z3\;nop"; 11367 else 11368 return "addi %0,%1,%2@got@tlsgd\;bl %z3\;nop"; 11369} 11370 "&& TARGET_TLS_MARKERS" 11371 [(set (match_dup 0) 11372 (unspec:TLSmode [(match_dup 1) 11373 (match_dup 2)] 11374 UNSPEC_TLSGD)) 11375 (parallel [(set (match_dup 0) 11376 (call (mem:TLSmode (match_dup 3)) 11377 (match_dup 4))) 11378 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD) 11379 (clobber (reg:SI LR_REGNO))])] 11380 "" 11381 [(set_attr "type" "two") 11382 (set (attr "length") 11383 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) 11384 (const_int 16) 11385 (const_int 12)))]) 11386 11387(define_insn_and_split "tls_gd_sysv<TLSmode:tls_sysv_suffix>" 11388 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11389 (call (mem:TLSmode (match_operand:TLSmode 3 "symbol_ref_operand" "s")) 11390 (match_operand 4 "" "g"))) 11391 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11392 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11393 UNSPEC_TLSGD) 11394 (clobber (reg:SI LR_REGNO))] 11395 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4" 11396{ 11397 if (flag_pic) 11398 { 11399 if (TARGET_SECURE_PLT && flag_pic == 2) 11400 return "addi %0,%1,%2@got@tlsgd\;bl %z3+32768@plt"; 11401 else 11402 return "addi %0,%1,%2@got@tlsgd\;bl %z3@plt"; 11403 } 11404 else 11405 return "addi %0,%1,%2@got@tlsgd\;bl %z3"; 11406} 11407 "&& TARGET_TLS_MARKERS" 11408 [(set (match_dup 0) 11409 (unspec:TLSmode [(match_dup 1) 11410 (match_dup 2)] 11411 UNSPEC_TLSGD)) 11412 (parallel [(set (match_dup 0) 11413 (call (mem:TLSmode (match_dup 3)) 11414 (match_dup 4))) 11415 (unspec:TLSmode [(match_dup 2)] UNSPEC_TLSGD) 11416 (clobber (reg:SI LR_REGNO))])] 11417 "" 11418 [(set_attr "type" "two") 11419 (set_attr "length" "8")]) 11420 11421(define_insn_and_split "*tls_gd<TLSmode:tls_abi_suffix>" 11422 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11423 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11424 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11425 UNSPEC_TLSGD))] 11426 "HAVE_AS_TLS && TARGET_TLS_MARKERS" 11427 "addi %0,%1,%2@got@tlsgd" 11428 "&& TARGET_CMODEL != CMODEL_SMALL" 11429 [(set (match_dup 3) 11430 (high:TLSmode 11431 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD))) 11432 (set (match_dup 0) 11433 (lo_sum:TLSmode (match_dup 3) 11434 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGD)))] 11435 " 11436{ 11437 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); 11438}" 11439 [(set (attr "length") 11440 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) 11441 (const_int 8) 11442 (const_int 4)))]) 11443 11444(define_insn "*tls_gd_high<TLSmode:tls_abi_suffix>" 11445 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11446 (high:TLSmode 11447 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11448 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11449 UNSPEC_TLSGD)))] 11450 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" 11451 "addis %0,%1,%2@got@tlsgd@ha" 11452 [(set_attr "length" "4")]) 11453 11454(define_insn "*tls_gd_low<TLSmode:tls_abi_suffix>" 11455 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11456 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") 11457 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") 11458 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11459 UNSPEC_TLSGD)))] 11460 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" 11461 "addi %0,%1,%2@got@tlsgd@l" 11462 [(set_attr "length" "4")]) 11463 11464(define_insn "*tls_gd_call_aix<TLSmode:tls_abi_suffix>" 11465 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11466 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s")) 11467 (match_operand 2 "" "g"))) 11468 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")] 11469 UNSPEC_TLSGD) 11470 (clobber (reg:SI LR_REGNO))] 11471 "HAVE_AS_TLS && TARGET_TLS_MARKERS 11472 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)" 11473 "bl %z1(%3@tlsgd)\;nop" 11474 [(set_attr "type" "branch") 11475 (set_attr "length" "8")]) 11476 11477(define_insn "*tls_gd_call_sysv<TLSmode:tls_abi_suffix>" 11478 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11479 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s")) 11480 (match_operand 2 "" "g"))) 11481 (unspec:TLSmode [(match_operand:TLSmode 3 "rs6000_tls_symbol_ref" "")] 11482 UNSPEC_TLSGD) 11483 (clobber (reg:SI LR_REGNO))] 11484 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS" 11485{ 11486 if (flag_pic) 11487 { 11488 if (TARGET_SECURE_PLT && flag_pic == 2) 11489 return "bl %z1+32768(%3@tlsgd)@plt"; 11490 return "bl %z1(%3@tlsgd)@plt"; 11491 } 11492 return "bl %z1(%3@tlsgd)"; 11493} 11494 [(set_attr "type" "branch") 11495 (set_attr "length" "4")]) 11496 11497(define_insn_and_split "tls_ld_aix<TLSmode:tls_abi_suffix>" 11498 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11499 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s")) 11500 (match_operand 3 "" "g"))) 11501 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")] 11502 UNSPEC_TLSLD) 11503 (clobber (reg:SI LR_REGNO))] 11504 "HAVE_AS_TLS && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)" 11505{ 11506 if (TARGET_CMODEL != CMODEL_SMALL) 11507 return "addis %0,%1,%&@got@tlsld@ha\;addi %0,%0,%&@got@tlsld@l\;" 11508 "bl %z2\;nop"; 11509 else 11510 return "addi %0,%1,%&@got@tlsld\;bl %z2\;nop"; 11511} 11512 "&& TARGET_TLS_MARKERS" 11513 [(set (match_dup 0) 11514 (unspec:TLSmode [(match_dup 1)] 11515 UNSPEC_TLSLD)) 11516 (parallel [(set (match_dup 0) 11517 (call (mem:TLSmode (match_dup 2)) 11518 (match_dup 3))) 11519 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD) 11520 (clobber (reg:SI LR_REGNO))])] 11521 "" 11522 [(set_attr "type" "two") 11523 (set (attr "length") 11524 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) 11525 (const_int 16) 11526 (const_int 12)))]) 11527 11528(define_insn_and_split "tls_ld_sysv<TLSmode:tls_sysv_suffix>" 11529 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11530 (call (mem:TLSmode (match_operand:TLSmode 2 "symbol_ref_operand" "s")) 11531 (match_operand 3 "" "g"))) 11532 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")] 11533 UNSPEC_TLSLD) 11534 (clobber (reg:SI LR_REGNO))] 11535 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4" 11536{ 11537 if (flag_pic) 11538 { 11539 if (TARGET_SECURE_PLT && flag_pic == 2) 11540 return "addi %0,%1,%&@got@tlsld\;bl %z2+32768@plt"; 11541 else 11542 return "addi %0,%1,%&@got@tlsld\;bl %z2@plt"; 11543 } 11544 else 11545 return "addi %0,%1,%&@got@tlsld\;bl %z2"; 11546} 11547 "&& TARGET_TLS_MARKERS" 11548 [(set (match_dup 0) 11549 (unspec:TLSmode [(match_dup 1)] 11550 UNSPEC_TLSLD)) 11551 (parallel [(set (match_dup 0) 11552 (call (mem:TLSmode (match_dup 2)) 11553 (match_dup 3))) 11554 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD) 11555 (clobber (reg:SI LR_REGNO))])] 11556 "" 11557 [(set_attr "length" "8")]) 11558 11559(define_insn_and_split "*tls_ld<TLSmode:tls_abi_suffix>" 11560 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11561 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b")] 11562 UNSPEC_TLSLD))] 11563 "HAVE_AS_TLS && TARGET_TLS_MARKERS" 11564 "addi %0,%1,%&@got@tlsld" 11565 "&& TARGET_CMODEL != CMODEL_SMALL" 11566 [(set (match_dup 2) 11567 (high:TLSmode 11568 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD))) 11569 (set (match_dup 0) 11570 (lo_sum:TLSmode (match_dup 2) 11571 (unspec:TLSmode [(const_int 0) (match_dup 1)] UNSPEC_TLSLD)))] 11572 " 11573{ 11574 operands[2] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); 11575}" 11576 [(set (attr "length") 11577 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) 11578 (const_int 8) 11579 (const_int 4)))]) 11580 11581(define_insn "*tls_ld_high<TLSmode:tls_abi_suffix>" 11582 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11583 (high:TLSmode 11584 (unspec:TLSmode [(const_int 0) 11585 (match_operand:TLSmode 1 "gpc_reg_operand" "b")] 11586 UNSPEC_TLSLD)))] 11587 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" 11588 "addis %0,%1,%&@got@tlsld@ha" 11589 [(set_attr "length" "4")]) 11590 11591(define_insn "*tls_ld_low<TLSmode:tls_abi_suffix>" 11592 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11593 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") 11594 (unspec:TLSmode [(const_int 0) 11595 (match_operand:TLSmode 2 "gpc_reg_operand" "b")] 11596 UNSPEC_TLSLD)))] 11597 "HAVE_AS_TLS && TARGET_TLS_MARKERS && TARGET_CMODEL != CMODEL_SMALL" 11598 "addi %0,%1,%&@got@tlsld@l" 11599 [(set_attr "length" "4")]) 11600 11601(define_insn "*tls_ld_call_aix<TLSmode:tls_abi_suffix>" 11602 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11603 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s")) 11604 (match_operand 2 "" "g"))) 11605 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD) 11606 (clobber (reg:SI LR_REGNO))] 11607 "HAVE_AS_TLS && TARGET_TLS_MARKERS 11608 && (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2)" 11609 "bl %z1(%&@tlsld)\;nop" 11610 [(set_attr "type" "branch") 11611 (set_attr "length" "8")]) 11612 11613(define_insn "*tls_ld_call_sysv<TLSmode:tls_abi_suffix>" 11614 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11615 (call (mem:TLSmode (match_operand:TLSmode 1 "symbol_ref_operand" "s")) 11616 (match_operand 2 "" "g"))) 11617 (unspec:TLSmode [(const_int 0)] UNSPEC_TLSLD) 11618 (clobber (reg:SI LR_REGNO))] 11619 "HAVE_AS_TLS && DEFAULT_ABI == ABI_V4 && TARGET_TLS_MARKERS" 11620{ 11621 if (flag_pic) 11622 { 11623 if (TARGET_SECURE_PLT && flag_pic == 2) 11624 return "bl %z1+32768(%&@tlsld)@plt"; 11625 return "bl %z1(%&@tlsld)@plt"; 11626 } 11627 return "bl %z1(%&@tlsld)"; 11628} 11629 [(set_attr "type" "branch") 11630 (set_attr "length" "4")]) 11631 11632(define_insn "tls_dtprel_<TLSmode:tls_abi_suffix>" 11633 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11634 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11635 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11636 UNSPEC_TLSDTPREL))] 11637 "HAVE_AS_TLS" 11638 "addi %0,%1,%2@dtprel") 11639 11640(define_insn "tls_dtprel_ha_<TLSmode:tls_abi_suffix>" 11641 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11642 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11643 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11644 UNSPEC_TLSDTPRELHA))] 11645 "HAVE_AS_TLS" 11646 "addis %0,%1,%2@dtprel@ha") 11647 11648(define_insn "tls_dtprel_lo_<TLSmode:tls_abi_suffix>" 11649 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11650 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11651 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11652 UNSPEC_TLSDTPRELLO))] 11653 "HAVE_AS_TLS" 11654 "addi %0,%1,%2@dtprel@l") 11655 11656(define_insn_and_split "tls_got_dtprel_<TLSmode:tls_abi_suffix>" 11657 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11658 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11659 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11660 UNSPEC_TLSGOTDTPREL))] 11661 "HAVE_AS_TLS" 11662 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel(%1)" 11663 "&& TARGET_CMODEL != CMODEL_SMALL" 11664 [(set (match_dup 3) 11665 (high:TLSmode 11666 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL))) 11667 (set (match_dup 0) 11668 (lo_sum:TLSmode (match_dup 3) 11669 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTDTPREL)))] 11670 " 11671{ 11672 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); 11673}" 11674 [(set (attr "length") 11675 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) 11676 (const_int 8) 11677 (const_int 4)))]) 11678 11679(define_insn "*tls_got_dtprel_high<TLSmode:tls_abi_suffix>" 11680 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11681 (high:TLSmode 11682 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11683 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11684 UNSPEC_TLSGOTDTPREL)))] 11685 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" 11686 "addis %0,%1,%2@got@dtprel@ha" 11687 [(set_attr "length" "4")]) 11688 11689(define_insn "*tls_got_dtprel_low<TLSmode:tls_abi_suffix>" 11690 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11691 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") 11692 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") 11693 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11694 UNSPEC_TLSGOTDTPREL)))] 11695 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" 11696 "l<TLSmode:tls_insn_suffix> %0,%2@got@dtprel@l(%1)" 11697 [(set_attr "length" "4")]) 11698 11699(define_insn "tls_tprel_<TLSmode:tls_abi_suffix>" 11700 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11701 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11702 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11703 UNSPEC_TLSTPREL))] 11704 "HAVE_AS_TLS" 11705 "addi %0,%1,%2@tprel") 11706 11707(define_insn "tls_tprel_ha_<TLSmode:tls_abi_suffix>" 11708 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11709 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11710 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11711 UNSPEC_TLSTPRELHA))] 11712 "HAVE_AS_TLS" 11713 "addis %0,%1,%2@tprel@ha") 11714 11715(define_insn "tls_tprel_lo_<TLSmode:tls_abi_suffix>" 11716 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11717 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11718 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11719 UNSPEC_TLSTPRELLO))] 11720 "HAVE_AS_TLS" 11721 "addi %0,%1,%2@tprel@l") 11722 11723;; "b" output constraint here and on tls_tls input to support linker tls 11724;; optimization. The linker may edit the instructions emitted by a 11725;; tls_got_tprel/tls_tls pair to addis,addi. 11726(define_insn_and_split "tls_got_tprel_<TLSmode:tls_abi_suffix>" 11727 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11728 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11729 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11730 UNSPEC_TLSGOTTPREL))] 11731 "HAVE_AS_TLS" 11732 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel(%1)" 11733 "&& TARGET_CMODEL != CMODEL_SMALL" 11734 [(set (match_dup 3) 11735 (high:TLSmode 11736 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL))) 11737 (set (match_dup 0) 11738 (lo_sum:TLSmode (match_dup 3) 11739 (unspec:TLSmode [(match_dup 1) (match_dup 2)] UNSPEC_TLSGOTTPREL)))] 11740 " 11741{ 11742 operands[3] = gen_reg_rtx (TARGET_64BIT ? DImode : SImode); 11743}" 11744 [(set (attr "length") 11745 (if_then_else (ne (symbol_ref "TARGET_CMODEL") (symbol_ref "CMODEL_SMALL")) 11746 (const_int 8) 11747 (const_int 4)))]) 11748 11749(define_insn "*tls_got_tprel_high<TLSmode:tls_abi_suffix>" 11750 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=b") 11751 (high:TLSmode 11752 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11753 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11754 UNSPEC_TLSGOTTPREL)))] 11755 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" 11756 "addis %0,%1,%2@got@tprel@ha" 11757 [(set_attr "length" "4")]) 11758 11759(define_insn "*tls_got_tprel_low<TLSmode:tls_abi_suffix>" 11760 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11761 (lo_sum:TLSmode (match_operand:TLSmode 1 "gpc_reg_operand" "b") 11762 (unspec:TLSmode [(match_operand:TLSmode 3 "gpc_reg_operand" "b") 11763 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11764 UNSPEC_TLSGOTTPREL)))] 11765 "HAVE_AS_TLS && TARGET_CMODEL != CMODEL_SMALL" 11766 "l<TLSmode:tls_insn_suffix> %0,%2@got@tprel@l(%1)" 11767 [(set_attr "length" "4")]) 11768 11769(define_insn "tls_tls_<TLSmode:tls_abi_suffix>" 11770 [(set (match_operand:TLSmode 0 "gpc_reg_operand" "=r") 11771 (unspec:TLSmode [(match_operand:TLSmode 1 "gpc_reg_operand" "b") 11772 (match_operand:TLSmode 2 "rs6000_tls_symbol_ref" "")] 11773 UNSPEC_TLSTLS))] 11774 "TARGET_ELF && HAVE_AS_TLS" 11775 "add %0,%1,%2@tls") 11776 11777(define_expand "tls_get_tpointer" 11778 [(set (match_operand:SI 0 "gpc_reg_operand" "") 11779 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS))] 11780 "TARGET_XCOFF && HAVE_AS_TLS" 11781 " 11782{ 11783 emit_insn (gen_tls_get_tpointer_internal ()); 11784 emit_move_insn (operands[0], gen_rtx_REG (SImode, 3)); 11785 DONE; 11786}") 11787 11788(define_insn "tls_get_tpointer_internal" 11789 [(set (reg:SI 3) 11790 (unspec:SI [(const_int 0)] UNSPEC_TLSTLS)) 11791 (clobber (reg:SI LR_REGNO))] 11792 "TARGET_XCOFF && HAVE_AS_TLS" 11793 "bla __get_tpointer") 11794 11795(define_expand "tls_get_addr<mode>" 11796 [(set (match_operand:P 0 "gpc_reg_operand" "") 11797 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "") 11798 (match_operand:P 2 "gpc_reg_operand" "")] UNSPEC_TLSTLS))] 11799 "TARGET_XCOFF && HAVE_AS_TLS" 11800 " 11801{ 11802 emit_move_insn (gen_rtx_REG (Pmode, 3), operands[1]); 11803 emit_move_insn (gen_rtx_REG (Pmode, 4), operands[2]); 11804 emit_insn (gen_tls_get_addr_internal<mode> ()); 11805 emit_move_insn (operands[0], gen_rtx_REG (Pmode, 3)); 11806 DONE; 11807}") 11808 11809(define_insn "tls_get_addr_internal<mode>" 11810 [(set (reg:P 3) 11811 (unspec:P [(reg:P 3) (reg:P 4)] UNSPEC_TLSTLS)) 11812 (clobber (reg:P 0)) 11813 (clobber (reg:P 4)) 11814 (clobber (reg:P 5)) 11815 (clobber (reg:P 11)) 11816 (clobber (reg:CC CR0_REGNO)) 11817 (clobber (reg:P LR_REGNO))] 11818 "TARGET_XCOFF && HAVE_AS_TLS" 11819 "bla __tls_get_addr") 11820 11821;; Next come insns related to the calling sequence. 11822;; 11823;; First, an insn to allocate new stack space for dynamic use (e.g., alloca). 11824;; We move the back-chain and decrement the stack pointer. 11825 11826(define_expand "allocate_stack" 11827 [(set (match_operand 0 "gpc_reg_operand" "") 11828 (minus (reg 1) (match_operand 1 "reg_or_short_operand" ""))) 11829 (set (reg 1) 11830 (minus (reg 1) (match_dup 1)))] 11831 "" 11832 " 11833{ rtx chain = gen_reg_rtx (Pmode); 11834 rtx stack_bot = gen_rtx_MEM (Pmode, stack_pointer_rtx); 11835 rtx neg_op0; 11836 rtx insn, par, set, mem; 11837 11838 emit_move_insn (chain, stack_bot); 11839 11840 /* Check stack bounds if necessary. */ 11841 if (crtl->limit_stack) 11842 { 11843 rtx available; 11844 available = expand_binop (Pmode, sub_optab, 11845 stack_pointer_rtx, stack_limit_rtx, 11846 NULL_RTX, 1, OPTAB_WIDEN); 11847 emit_insn (gen_cond_trap (LTU, available, operands[1], const0_rtx)); 11848 } 11849 11850 if (GET_CODE (operands[1]) != CONST_INT 11851 || INTVAL (operands[1]) < -32767 11852 || INTVAL (operands[1]) > 32768) 11853 { 11854 neg_op0 = gen_reg_rtx (Pmode); 11855 if (TARGET_32BIT) 11856 emit_insn (gen_negsi2 (neg_op0, operands[1])); 11857 else 11858 emit_insn (gen_negdi2 (neg_op0, operands[1])); 11859 } 11860 else 11861 neg_op0 = GEN_INT (- INTVAL (operands[1])); 11862 11863 insn = emit_insn ((* ((TARGET_32BIT) ? gen_movsi_update_stack 11864 : gen_movdi_di_update_stack)) 11865 (stack_pointer_rtx, stack_pointer_rtx, neg_op0, 11866 chain)); 11867 /* Since we didn't use gen_frame_mem to generate the MEM, grab 11868 it now and set the alias set/attributes. The above gen_*_update 11869 calls will generate a PARALLEL with the MEM set being the first 11870 operation. */ 11871 par = PATTERN (insn); 11872 gcc_assert (GET_CODE (par) == PARALLEL); 11873 set = XVECEXP (par, 0, 0); 11874 gcc_assert (GET_CODE (set) == SET); 11875 mem = SET_DEST (set); 11876 gcc_assert (MEM_P (mem)); 11877 MEM_NOTRAP_P (mem) = 1; 11878 set_mem_alias_set (mem, get_frame_alias_set ()); 11879 11880 emit_move_insn (operands[0], virtual_stack_dynamic_rtx); 11881 DONE; 11882}") 11883 11884;; These patterns say how to save and restore the stack pointer. We need not 11885;; save the stack pointer at function level since we are careful to 11886;; preserve the backchain. At block level, we have to restore the backchain 11887;; when we restore the stack pointer. 11888;; 11889;; For nonlocal gotos, we must save both the stack pointer and its 11890;; backchain and restore both. Note that in the nonlocal case, the 11891;; save area is a memory location. 11892 11893(define_expand "save_stack_function" 11894 [(match_operand 0 "any_operand" "") 11895 (match_operand 1 "any_operand" "")] 11896 "" 11897 "DONE;") 11898 11899(define_expand "restore_stack_function" 11900 [(match_operand 0 "any_operand" "") 11901 (match_operand 1 "any_operand" "")] 11902 "" 11903 "DONE;") 11904 11905;; Adjust stack pointer (op0) to a new value (op1). 11906;; First copy old stack backchain to new location, and ensure that the 11907;; scheduler won't reorder the sp assignment before the backchain write. 11908(define_expand "restore_stack_block" 11909 [(set (match_dup 2) (match_dup 3)) 11910 (set (match_dup 4) (match_dup 2)) 11911 (match_dup 5) 11912 (set (match_operand 0 "register_operand" "") 11913 (match_operand 1 "register_operand" ""))] 11914 "" 11915 " 11916{ 11917 rtvec p; 11918 11919 operands[1] = force_reg (Pmode, operands[1]); 11920 operands[2] = gen_reg_rtx (Pmode); 11921 operands[3] = gen_frame_mem (Pmode, operands[0]); 11922 operands[4] = gen_frame_mem (Pmode, operands[1]); 11923 p = rtvec_alloc (1); 11924 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode, 11925 gen_frame_mem (BLKmode, operands[0]), 11926 const0_rtx); 11927 operands[5] = gen_rtx_PARALLEL (VOIDmode, p); 11928}") 11929 11930(define_expand "save_stack_nonlocal" 11931 [(set (match_dup 3) (match_dup 4)) 11932 (set (match_operand 0 "memory_operand" "") (match_dup 3)) 11933 (set (match_dup 2) (match_operand 1 "register_operand" ""))] 11934 "" 11935 " 11936{ 11937 int units_per_word = (TARGET_32BIT) ? 4 : 8; 11938 11939 /* Copy the backchain to the first word, sp to the second. */ 11940 operands[0] = adjust_address_nv (operands[0], Pmode, 0); 11941 operands[2] = adjust_address_nv (operands[0], Pmode, units_per_word); 11942 operands[3] = gen_reg_rtx (Pmode); 11943 operands[4] = gen_frame_mem (Pmode, operands[1]); 11944}") 11945 11946(define_expand "restore_stack_nonlocal" 11947 [(set (match_dup 2) (match_operand 1 "memory_operand" "")) 11948 (set (match_dup 3) (match_dup 4)) 11949 (set (match_dup 5) (match_dup 2)) 11950 (match_dup 6) 11951 (set (match_operand 0 "register_operand" "") (match_dup 3))] 11952 "" 11953 " 11954{ 11955 int units_per_word = (TARGET_32BIT) ? 4 : 8; 11956 rtvec p; 11957 11958 /* Restore the backchain from the first word, sp from the second. */ 11959 operands[2] = gen_reg_rtx (Pmode); 11960 operands[3] = gen_reg_rtx (Pmode); 11961 operands[1] = adjust_address_nv (operands[1], Pmode, 0); 11962 operands[4] = adjust_address_nv (operands[1], Pmode, units_per_word); 11963 operands[5] = gen_frame_mem (Pmode, operands[3]); 11964 p = rtvec_alloc (1); 11965 RTVEC_ELT (p, 0) = gen_rtx_SET (VOIDmode, 11966 gen_frame_mem (BLKmode, operands[0]), 11967 const0_rtx); 11968 operands[6] = gen_rtx_PARALLEL (VOIDmode, p); 11969}") 11970 11971;; TOC register handling. 11972 11973;; Code to initialize the TOC register... 11974 11975(define_insn "load_toc_aix_si" 11976 [(parallel [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 11977 (unspec:SI [(const_int 0)] UNSPEC_TOC)) 11978 (use (reg:SI 2))])] 11979 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_32BIT" 11980 "* 11981{ 11982 char buf[30]; 11983 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); 11984 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 11985 operands[2] = gen_rtx_REG (Pmode, 2); 11986 return \"lwz %0,%1(%2)\"; 11987}" 11988 [(set_attr "type" "load")]) 11989 11990(define_insn "load_toc_aix_di" 11991 [(parallel [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 11992 (unspec:DI [(const_int 0)] UNSPEC_TOC)) 11993 (use (reg:DI 2))])] 11994 "(DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) && TARGET_64BIT" 11995 "* 11996{ 11997 char buf[30]; 11998#ifdef TARGET_RELOCATABLE 11999 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 12000 !TARGET_MINIMAL_TOC || TARGET_RELOCATABLE); 12001#else 12002 ASM_GENERATE_INTERNAL_LABEL (buf, \"LCTOC\", 1); 12003#endif 12004 if (TARGET_ELF) 12005 strcat (buf, \"@toc\"); 12006 operands[1] = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 12007 operands[2] = gen_rtx_REG (Pmode, 2); 12008 return \"ld %0,%1(%2)\"; 12009}" 12010 [(set_attr "type" "load")]) 12011 12012(define_insn "load_toc_v4_pic_si" 12013 [(set (reg:SI LR_REGNO) 12014 (unspec:SI [(const_int 0)] UNSPEC_TOC))] 12015 "DEFAULT_ABI == ABI_V4 && flag_pic == 1 && TARGET_32BIT" 12016 "bl _GLOBAL_OFFSET_TABLE_@local-4" 12017 [(set_attr "type" "branch") 12018 (set_attr "length" "4")]) 12019 12020(define_expand "load_toc_v4_PIC_1" 12021 [(parallel [(set (reg:SI LR_REGNO) 12022 (match_operand:SI 0 "immediate_operand" "s")) 12023 (use (unspec [(match_dup 0)] UNSPEC_TOC))])] 12024 "TARGET_ELF && DEFAULT_ABI == ABI_V4 12025 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" 12026 "") 12027 12028(define_insn "load_toc_v4_PIC_1_normal" 12029 [(set (reg:SI LR_REGNO) 12030 (match_operand:SI 0 "immediate_operand" "s")) 12031 (use (unspec [(match_dup 0)] UNSPEC_TOC))] 12032 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 12033 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" 12034 "bcl 20,31,%0\\n%0:" 12035 [(set_attr "type" "branch") 12036 (set_attr "length" "4")]) 12037 12038(define_insn "load_toc_v4_PIC_1_476" 12039 [(set (reg:SI LR_REGNO) 12040 (match_operand:SI 0 "immediate_operand" "s")) 12041 (use (unspec [(match_dup 0)] UNSPEC_TOC))] 12042 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 12043 && (flag_pic == 2 || (flag_pic && TARGET_SECURE_PLT))" 12044 "* 12045{ 12046 char name[32]; 12047 static char templ[32]; 12048 12049 get_ppc476_thunk_name (name); 12050 sprintf (templ, \"bl %s\\n%%0:\", name); 12051 return templ; 12052}" 12053 [(set_attr "type" "branch") 12054 (set_attr "length" "4")]) 12055 12056(define_expand "load_toc_v4_PIC_1b" 12057 [(parallel [(set (reg:SI LR_REGNO) 12058 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s") 12059 (label_ref (match_operand 1 "" ""))] 12060 UNSPEC_TOCPTR)) 12061 (match_dup 1)])] 12062 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" 12063 "") 12064 12065(define_insn "load_toc_v4_PIC_1b_normal" 12066 [(set (reg:SI LR_REGNO) 12067 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s") 12068 (label_ref (match_operand 1 "" ""))] 12069 UNSPEC_TOCPTR)) 12070 (match_dup 1)] 12071 "!TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" 12072 "bcl 20,31,$+8\;.long %0-$" 12073 [(set_attr "type" "branch") 12074 (set_attr "length" "8")]) 12075 12076(define_insn "load_toc_v4_PIC_1b_476" 12077 [(set (reg:SI LR_REGNO) 12078 (unspec:SI [(match_operand:SI 0 "immediate_operand" "s") 12079 (label_ref (match_operand 1 "" ""))] 12080 UNSPEC_TOCPTR)) 12081 (match_dup 1)] 12082 "TARGET_LINK_STACK && TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" 12083 "* 12084{ 12085 char name[32]; 12086 static char templ[32]; 12087 12088 get_ppc476_thunk_name (name); 12089 sprintf (templ, \"bl %s\\n\\tb $+8\\n\\t.long %%0-$\", name); 12090 return templ; 12091}" 12092 [(set_attr "type" "branch") 12093 (set_attr "length" "16")]) 12094 12095(define_insn "load_toc_v4_PIC_2" 12096 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12097 (mem:SI (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 12098 (minus:SI (match_operand:SI 2 "immediate_operand" "s") 12099 (match_operand:SI 3 "immediate_operand" "s")))))] 12100 "TARGET_ELF && DEFAULT_ABI == ABI_V4 && flag_pic == 2" 12101 "lwz %0,%2-%3(%1)" 12102 [(set_attr "type" "load")]) 12103 12104(define_insn "load_toc_v4_PIC_3b" 12105 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12106 (plus:SI (match_operand:SI 1 "gpc_reg_operand" "b") 12107 (high:SI 12108 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") 12109 (match_operand:SI 3 "symbol_ref_operand" "s")))))] 12110 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic" 12111 "addis %0,%1,%2-%3@ha") 12112 12113(define_insn "load_toc_v4_PIC_3c" 12114 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 12115 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b") 12116 (minus:SI (match_operand:SI 2 "symbol_ref_operand" "s") 12117 (match_operand:SI 3 "symbol_ref_operand" "s"))))] 12118 "TARGET_ELF && TARGET_SECURE_PLT && DEFAULT_ABI == ABI_V4 && flag_pic" 12119 "addi %0,%1,%2-%3@l") 12120 12121;; If the TOC is shared over a translation unit, as happens with all 12122;; the kinds of PIC that we support, we need to restore the TOC 12123;; pointer only when jumping over units of translation. 12124;; On Darwin, we need to reload the picbase. 12125 12126(define_expand "builtin_setjmp_receiver" 12127 [(use (label_ref (match_operand 0 "" "")))] 12128 "(DEFAULT_ABI == ABI_V4 && flag_pic == 1) 12129 || (TARGET_TOC && TARGET_MINIMAL_TOC) 12130 || (DEFAULT_ABI == ABI_DARWIN && flag_pic)" 12131 " 12132{ 12133#if TARGET_MACHO 12134 if (DEFAULT_ABI == ABI_DARWIN) 12135 { 12136 rtx picrtx = gen_rtx_SYMBOL_REF (Pmode, MACHOPIC_FUNCTION_BASE_NAME); 12137 rtx picreg = gen_rtx_REG (Pmode, RS6000_PIC_OFFSET_TABLE_REGNUM); 12138 rtx tmplabrtx; 12139 char tmplab[20]; 12140 12141 crtl->uses_pic_offset_table = 1; 12142 ASM_GENERATE_INTERNAL_LABEL(tmplab, \"LSJR\", 12143 CODE_LABEL_NUMBER (operands[0])); 12144 tmplabrtx = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (tmplab)); 12145 12146 emit_insn (gen_load_macho_picbase (tmplabrtx)); 12147 emit_move_insn (picreg, gen_rtx_REG (Pmode, LR_REGNO)); 12148 emit_insn (gen_macho_correct_pic (picreg, picreg, picrtx, tmplabrtx)); 12149 } 12150 else 12151#endif 12152 rs6000_emit_load_toc_table (FALSE); 12153 DONE; 12154}") 12155 12156;; Largetoc support 12157(define_insn "*largetoc_high" 12158 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r") 12159 (high:DI 12160 (unspec [(match_operand:DI 1 "" "") 12161 (match_operand:DI 2 "gpc_reg_operand" "b")] 12162 UNSPEC_TOCREL)))] 12163 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" 12164 "addis %0,%2,%1@toc@ha") 12165 12166(define_insn "*largetoc_high_aix<mode>" 12167 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r") 12168 (high:P 12169 (unspec [(match_operand:P 1 "" "") 12170 (match_operand:P 2 "gpc_reg_operand" "b")] 12171 UNSPEC_TOCREL)))] 12172 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL" 12173 "addis %0,%1@u(%2)") 12174 12175(define_insn "*largetoc_high_plus" 12176 [(set (match_operand:DI 0 "gpc_reg_operand" "=b*r") 12177 (high:DI 12178 (plus:DI 12179 (unspec [(match_operand:DI 1 "" "") 12180 (match_operand:DI 2 "gpc_reg_operand" "b")] 12181 UNSPEC_TOCREL) 12182 (match_operand:DI 3 "add_cint_operand" "n"))))] 12183 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" 12184 "addis %0,%2,%1+%3@toc@ha") 12185 12186(define_insn "*largetoc_high_plus_aix<mode>" 12187 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r") 12188 (high:P 12189 (plus:P 12190 (unspec [(match_operand:P 1 "" "") 12191 (match_operand:P 2 "gpc_reg_operand" "b")] 12192 UNSPEC_TOCREL) 12193 (match_operand:P 3 "add_cint_operand" "n"))))] 12194 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL" 12195 "addis %0,%1+%3@u(%2)") 12196 12197(define_insn "*largetoc_low" 12198 [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r") 12199 (lo_sum:DI (match_operand:DI 1 "gpc_reg_operand" "b,!*r") 12200 (match_operand:DI 2 "" "")))] 12201 "TARGET_ELF && TARGET_CMODEL != CMODEL_SMALL" 12202 "@ 12203 addi %0,%1,%2@l 12204 addic %0,%1,%2@l") 12205 12206(define_insn "*largetoc_low_aix<mode>" 12207 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 12208 (lo_sum:P (match_operand:P 1 "gpc_reg_operand" "b") 12209 (match_operand:P 2 "" "")))] 12210 "TARGET_XCOFF && TARGET_CMODEL != CMODEL_SMALL" 12211 "la %0,%2@l(%1)") 12212 12213(define_insn_and_split "*tocref<mode>" 12214 [(set (match_operand:P 0 "gpc_reg_operand" "=b*r") 12215 (match_operand:P 1 "small_toc_ref" "R"))] 12216 "TARGET_TOC" 12217 "la %0,%a1" 12218 "&& TARGET_CMODEL != CMODEL_SMALL && reload_completed" 12219 [(set (match_dup 0) (high:P (match_dup 1))) 12220 (set (match_dup 0) (lo_sum:P (match_dup 0) (match_dup 1)))]) 12221 12222;; Elf specific ways of loading addresses for non-PIC code. 12223;; The output of this could be r0, but we make a very strong 12224;; preference for a base register because it will usually 12225;; be needed there. 12226(define_insn "elf_high" 12227 [(set (match_operand:SI 0 "gpc_reg_operand" "=b*r") 12228 (high:SI (match_operand 1 "" "")))] 12229 "TARGET_ELF && ! TARGET_64BIT" 12230 "lis %0,%1@ha") 12231 12232(define_insn "elf_low" 12233 [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r") 12234 (lo_sum:SI (match_operand:SI 1 "gpc_reg_operand" "b,!*r") 12235 (match_operand 2 "" "")))] 12236 "TARGET_ELF && ! TARGET_64BIT" 12237 "@ 12238 la %0,%2@l(%1) 12239 addic %0,%1,%K2") 12240 12241;; Call and call_value insns 12242(define_expand "call" 12243 [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) 12244 (match_operand 1 "" "")) 12245 (use (match_operand 2 "" "")) 12246 (clobber (reg:SI LR_REGNO))])] 12247 "" 12248 " 12249{ 12250#if TARGET_MACHO 12251 if (MACHOPIC_INDIRECT) 12252 operands[0] = machopic_indirect_call_target (operands[0]); 12253#endif 12254 12255 gcc_assert (GET_CODE (operands[0]) == MEM); 12256 gcc_assert (GET_CODE (operands[1]) == CONST_INT); 12257 12258 operands[0] = XEXP (operands[0], 0); 12259 12260 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) 12261 { 12262 rs6000_call_aix (NULL_RTX, operands[0], operands[1], operands[2]); 12263 DONE; 12264 } 12265 12266 if (GET_CODE (operands[0]) != SYMBOL_REF 12267 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[2]) & CALL_LONG) != 0)) 12268 { 12269 if (INTVAL (operands[2]) & CALL_LONG) 12270 operands[0] = rs6000_longcall_ref (operands[0]); 12271 12272 switch (DEFAULT_ABI) 12273 { 12274 case ABI_V4: 12275 case ABI_DARWIN: 12276 operands[0] = force_reg (Pmode, operands[0]); 12277 break; 12278 12279 default: 12280 gcc_unreachable (); 12281 } 12282 } 12283}") 12284 12285(define_expand "call_value" 12286 [(parallel [(set (match_operand 0 "" "") 12287 (call (mem:SI (match_operand 1 "address_operand" "")) 12288 (match_operand 2 "" ""))) 12289 (use (match_operand 3 "" "")) 12290 (clobber (reg:SI LR_REGNO))])] 12291 "" 12292 " 12293{ 12294#if TARGET_MACHO 12295 if (MACHOPIC_INDIRECT) 12296 operands[1] = machopic_indirect_call_target (operands[1]); 12297#endif 12298 12299 gcc_assert (GET_CODE (operands[1]) == MEM); 12300 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 12301 12302 operands[1] = XEXP (operands[1], 0); 12303 12304 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) 12305 { 12306 rs6000_call_aix (operands[0], operands[1], operands[2], operands[3]); 12307 DONE; 12308 } 12309 12310 if (GET_CODE (operands[1]) != SYMBOL_REF 12311 || (DEFAULT_ABI != ABI_DARWIN && (INTVAL (operands[3]) & CALL_LONG) != 0)) 12312 { 12313 if (INTVAL (operands[3]) & CALL_LONG) 12314 operands[1] = rs6000_longcall_ref (operands[1]); 12315 12316 switch (DEFAULT_ABI) 12317 { 12318 case ABI_V4: 12319 case ABI_DARWIN: 12320 operands[1] = force_reg (Pmode, operands[1]); 12321 break; 12322 12323 default: 12324 gcc_unreachable (); 12325 } 12326 } 12327}") 12328 12329;; Call to function in current module. No TOC pointer reload needed. 12330;; Operand2 is nonzero if we are using the V.4 calling sequence and 12331;; either the function was not prototyped, or it was prototyped as a 12332;; variable argument function. It is > 0 if FP registers were passed 12333;; and < 0 if they were not. 12334 12335(define_insn "*call_local32" 12336 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) 12337 (match_operand 1 "" "g,g")) 12338 (use (match_operand:SI 2 "immediate_operand" "O,n")) 12339 (clobber (reg:SI LR_REGNO))] 12340 "(INTVAL (operands[2]) & CALL_LONG) == 0" 12341 "* 12342{ 12343 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 12344 output_asm_insn (\"crxor 6,6,6\", operands); 12345 12346 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 12347 output_asm_insn (\"creqv 6,6,6\", operands); 12348 12349 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; 12350}" 12351 [(set_attr "type" "branch") 12352 (set_attr "length" "4,8")]) 12353 12354(define_insn "*call_local64" 12355 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) 12356 (match_operand 1 "" "g,g")) 12357 (use (match_operand:SI 2 "immediate_operand" "O,n")) 12358 (clobber (reg:SI LR_REGNO))] 12359 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" 12360 "* 12361{ 12362 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 12363 output_asm_insn (\"crxor 6,6,6\", operands); 12364 12365 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 12366 output_asm_insn (\"creqv 6,6,6\", operands); 12367 12368 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z0@local\" : \"bl %z0\"; 12369}" 12370 [(set_attr "type" "branch") 12371 (set_attr "length" "4,8")]) 12372 12373(define_insn "*call_value_local32" 12374 [(set (match_operand 0 "" "") 12375 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) 12376 (match_operand 2 "" "g,g"))) 12377 (use (match_operand:SI 3 "immediate_operand" "O,n")) 12378 (clobber (reg:SI LR_REGNO))] 12379 "(INTVAL (operands[3]) & CALL_LONG) == 0" 12380 "* 12381{ 12382 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 12383 output_asm_insn (\"crxor 6,6,6\", operands); 12384 12385 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 12386 output_asm_insn (\"creqv 6,6,6\", operands); 12387 12388 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; 12389}" 12390 [(set_attr "type" "branch") 12391 (set_attr "length" "4,8")]) 12392 12393 12394(define_insn "*call_value_local64" 12395 [(set (match_operand 0 "" "") 12396 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) 12397 (match_operand 2 "" "g,g"))) 12398 (use (match_operand:SI 3 "immediate_operand" "O,n")) 12399 (clobber (reg:SI LR_REGNO))] 12400 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" 12401 "* 12402{ 12403 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 12404 output_asm_insn (\"crxor 6,6,6\", operands); 12405 12406 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 12407 output_asm_insn (\"creqv 6,6,6\", operands); 12408 12409 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"bl %z1@local\" : \"bl %z1\"; 12410}" 12411 [(set_attr "type" "branch") 12412 (set_attr "length" "4,8")]) 12413 12414 12415;; A function pointer under System V is just a normal pointer 12416;; operands[0] is the function pointer 12417;; operands[1] is the stack size to clean up 12418;; operands[2] is the value FUNCTION_ARG returns for the VOID argument 12419;; which indicates how to set cr1 12420 12421(define_insn "*call_indirect_nonlocal_sysv<mode>" 12422 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l,c,*l")) 12423 (match_operand 1 "" "g,g,g,g")) 12424 (use (match_operand:SI 2 "immediate_operand" "O,O,n,n")) 12425 (clobber (reg:SI LR_REGNO))] 12426 "DEFAULT_ABI == ABI_V4 12427 || DEFAULT_ABI == ABI_DARWIN" 12428{ 12429 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 12430 output_asm_insn ("crxor 6,6,6", operands); 12431 12432 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 12433 output_asm_insn ("creqv 6,6,6", operands); 12434 12435 return "b%T0l"; 12436} 12437 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") 12438 (set_attr "length" "4,4,8,8")]) 12439 12440(define_insn_and_split "*call_nonlocal_sysv<mode>" 12441 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s")) 12442 (match_operand 1 "" "g,g")) 12443 (use (match_operand:SI 2 "immediate_operand" "O,n")) 12444 (clobber (reg:SI LR_REGNO))] 12445 "(DEFAULT_ABI == ABI_DARWIN 12446 || (DEFAULT_ABI == ABI_V4 12447 && (INTVAL (operands[2]) & CALL_LONG) == 0))" 12448{ 12449 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 12450 output_asm_insn ("crxor 6,6,6", operands); 12451 12452 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 12453 output_asm_insn ("creqv 6,6,6", operands); 12454 12455#if TARGET_MACHO 12456 return output_call(insn, operands, 0, 2); 12457#else 12458 if (DEFAULT_ABI == ABI_V4 && flag_pic) 12459 { 12460 gcc_assert (!TARGET_SECURE_PLT); 12461 return "bl %z0@plt"; 12462 } 12463 else 12464 return "bl %z0"; 12465#endif 12466} 12467 "DEFAULT_ABI == ABI_V4 12468 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0]) 12469 && (INTVAL (operands[2]) & CALL_LONG) == 0" 12470 [(parallel [(call (mem:SI (match_dup 0)) 12471 (match_dup 1)) 12472 (use (match_dup 2)) 12473 (use (match_dup 3)) 12474 (clobber (reg:SI LR_REGNO))])] 12475{ 12476 operands[3] = pic_offset_table_rtx; 12477} 12478 [(set_attr "type" "branch,branch") 12479 (set_attr "length" "4,8")]) 12480 12481(define_insn "*call_nonlocal_sysv_secure<mode>" 12482 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s,s")) 12483 (match_operand 1 "" "g,g")) 12484 (use (match_operand:SI 2 "immediate_operand" "O,n")) 12485 (use (match_operand:SI 3 "register_operand" "r,r")) 12486 (clobber (reg:SI LR_REGNO))] 12487 "(DEFAULT_ABI == ABI_V4 12488 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[0]) 12489 && (INTVAL (operands[2]) & CALL_LONG) == 0)" 12490{ 12491 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 12492 output_asm_insn ("crxor 6,6,6", operands); 12493 12494 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 12495 output_asm_insn ("creqv 6,6,6", operands); 12496 12497 if (flag_pic == 2) 12498 /* The magic 32768 offset here and in the other sysv call insns 12499 corresponds to the offset of r30 in .got2, as given by LCTOC1. 12500 See sysv4.h:toc_section. */ 12501 return "bl %z0+32768@plt"; 12502 else 12503 return "bl %z0@plt"; 12504} 12505 [(set_attr "type" "branch,branch") 12506 (set_attr "length" "4,8")]) 12507 12508(define_insn "*call_value_indirect_nonlocal_sysv<mode>" 12509 [(set (match_operand 0 "" "") 12510 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l,c,*l")) 12511 (match_operand 2 "" "g,g,g,g"))) 12512 (use (match_operand:SI 3 "immediate_operand" "O,O,n,n")) 12513 (clobber (reg:SI LR_REGNO))] 12514 "DEFAULT_ABI == ABI_V4 12515 || DEFAULT_ABI == ABI_DARWIN" 12516{ 12517 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 12518 output_asm_insn ("crxor 6,6,6", operands); 12519 12520 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 12521 output_asm_insn ("creqv 6,6,6", operands); 12522 12523 return "b%T1l"; 12524} 12525 [(set_attr "type" "jmpreg,jmpreg,jmpreg,jmpreg") 12526 (set_attr "length" "4,4,8,8")]) 12527 12528(define_insn_and_split "*call_value_nonlocal_sysv<mode>" 12529 [(set (match_operand 0 "" "") 12530 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s")) 12531 (match_operand 2 "" "g,g"))) 12532 (use (match_operand:SI 3 "immediate_operand" "O,n")) 12533 (clobber (reg:SI LR_REGNO))] 12534 "(DEFAULT_ABI == ABI_DARWIN 12535 || (DEFAULT_ABI == ABI_V4 12536 && (INTVAL (operands[3]) & CALL_LONG) == 0))" 12537{ 12538 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 12539 output_asm_insn ("crxor 6,6,6", operands); 12540 12541 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 12542 output_asm_insn ("creqv 6,6,6", operands); 12543 12544#if TARGET_MACHO 12545 return output_call(insn, operands, 1, 3); 12546#else 12547 if (DEFAULT_ABI == ABI_V4 && flag_pic) 12548 { 12549 gcc_assert (!TARGET_SECURE_PLT); 12550 return "bl %z1@plt"; 12551 } 12552 else 12553 return "bl %z1"; 12554#endif 12555} 12556 "DEFAULT_ABI == ABI_V4 12557 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1]) 12558 && (INTVAL (operands[3]) & CALL_LONG) == 0" 12559 [(parallel [(set (match_dup 0) 12560 (call (mem:SI (match_dup 1)) 12561 (match_dup 2))) 12562 (use (match_dup 3)) 12563 (use (match_dup 4)) 12564 (clobber (reg:SI LR_REGNO))])] 12565{ 12566 operands[4] = pic_offset_table_rtx; 12567} 12568 [(set_attr "type" "branch,branch") 12569 (set_attr "length" "4,8")]) 12570 12571(define_insn "*call_value_nonlocal_sysv_secure<mode>" 12572 [(set (match_operand 0 "" "") 12573 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s,s")) 12574 (match_operand 2 "" "g,g"))) 12575 (use (match_operand:SI 3 "immediate_operand" "O,n")) 12576 (use (match_operand:SI 4 "register_operand" "r,r")) 12577 (clobber (reg:SI LR_REGNO))] 12578 "(DEFAULT_ABI == ABI_V4 12579 && TARGET_SECURE_PLT && flag_pic && !SYMBOL_REF_LOCAL_P (operands[1]) 12580 && (INTVAL (operands[3]) & CALL_LONG) == 0)" 12581{ 12582 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 12583 output_asm_insn ("crxor 6,6,6", operands); 12584 12585 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 12586 output_asm_insn ("creqv 6,6,6", operands); 12587 12588 if (flag_pic == 2) 12589 return "bl %z1+32768@plt"; 12590 else 12591 return "bl %z1@plt"; 12592} 12593 [(set_attr "type" "branch,branch") 12594 (set_attr "length" "4,8")]) 12595 12596 12597;; Call to AIX abi function in the same module. 12598 12599(define_insn "*call_local_aix<mode>" 12600 [(call (mem:SI (match_operand:P 0 "current_file_function_operand" "s")) 12601 (match_operand 1 "" "g")) 12602 (clobber (reg:P LR_REGNO))] 12603 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" 12604 "bl %z0" 12605 [(set_attr "type" "branch") 12606 (set_attr "length" "4")]) 12607 12608(define_insn "*call_value_local_aix<mode>" 12609 [(set (match_operand 0 "" "") 12610 (call (mem:SI (match_operand:P 1 "current_file_function_operand" "s")) 12611 (match_operand 2 "" "g"))) 12612 (clobber (reg:P LR_REGNO))] 12613 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" 12614 "bl %z1" 12615 [(set_attr "type" "branch") 12616 (set_attr "length" "4")]) 12617 12618;; Call to AIX abi function which may be in another module. 12619;; Restore the TOC pointer (r2) after the call. 12620 12621(define_insn "*call_nonlocal_aix<mode>" 12622 [(call (mem:SI (match_operand:P 0 "symbol_ref_operand" "s")) 12623 (match_operand 1 "" "g")) 12624 (clobber (reg:P LR_REGNO))] 12625 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" 12626 "bl %z0\;nop" 12627 [(set_attr "type" "branch") 12628 (set_attr "length" "8")]) 12629 12630(define_insn "*call_value_nonlocal_aix<mode>" 12631 [(set (match_operand 0 "" "") 12632 (call (mem:SI (match_operand:P 1 "symbol_ref_operand" "s")) 12633 (match_operand 2 "" "g"))) 12634 (clobber (reg:P LR_REGNO))] 12635 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" 12636 "bl %z1\;nop" 12637 [(set_attr "type" "branch") 12638 (set_attr "length" "8")]) 12639 12640;; Call to indirect functions with the AIX abi using a 3 word descriptor. 12641;; Operand0 is the addresss of the function to call 12642;; Operand2 is the location in the function descriptor to load r2 from 12643;; Operand3 is the stack location to hold the current TOC pointer 12644 12645(define_insn "*call_indirect_aix<mode>" 12646 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l")) 12647 (match_operand 1 "" "g,g")) 12648 (use (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>")) 12649 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>")) 12650 (clobber (reg:P LR_REGNO))] 12651 "DEFAULT_ABI == ABI_AIX" 12652 "<ptrload> 2,%2\;b%T0l\;<ptrload> 2,%3" 12653 [(set_attr "type" "jmpreg") 12654 (set_attr "length" "12")]) 12655 12656(define_insn "*call_value_indirect_aix<mode>" 12657 [(set (match_operand 0 "" "") 12658 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l")) 12659 (match_operand 2 "" "g,g"))) 12660 (use (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>")) 12661 (set (reg:P TOC_REGNUM) (match_operand:P 4 "memory_operand" "<ptrm>,<ptrm>")) 12662 (clobber (reg:P LR_REGNO))] 12663 "DEFAULT_ABI == ABI_AIX" 12664 "<ptrload> 2,%3\;b%T1l\;<ptrload> 2,%4" 12665 [(set_attr "type" "jmpreg") 12666 (set_attr "length" "12")]) 12667 12668;; Call to indirect functions with the ELFv2 ABI. 12669;; Operand0 is the addresss of the function to call 12670;; Operand2 is the stack location to hold the current TOC pointer 12671 12672(define_insn "*call_indirect_elfv2<mode>" 12673 [(call (mem:SI (match_operand:P 0 "register_operand" "c,*l")) 12674 (match_operand 1 "" "g,g")) 12675 (set (reg:P TOC_REGNUM) (match_operand:P 2 "memory_operand" "<ptrm>,<ptrm>")) 12676 (clobber (reg:P LR_REGNO))] 12677 "DEFAULT_ABI == ABI_ELFv2" 12678 "b%T0l\;<ptrload> 2,%2" 12679 [(set_attr "type" "jmpreg") 12680 (set_attr "length" "8")]) 12681 12682(define_insn "*call_value_indirect_elfv2<mode>" 12683 [(set (match_operand 0 "" "") 12684 (call (mem:SI (match_operand:P 1 "register_operand" "c,*l")) 12685 (match_operand 2 "" "g,g"))) 12686 (set (reg:P TOC_REGNUM) (match_operand:P 3 "memory_operand" "<ptrm>,<ptrm>")) 12687 (clobber (reg:P LR_REGNO))] 12688 "DEFAULT_ABI == ABI_ELFv2" 12689 "b%T1l\;<ptrload> 2,%3" 12690 [(set_attr "type" "jmpreg") 12691 (set_attr "length" "8")]) 12692 12693 12694;; Call subroutine returning any type. 12695(define_expand "untyped_call" 12696 [(parallel [(call (match_operand 0 "" "") 12697 (const_int 0)) 12698 (match_operand 1 "" "") 12699 (match_operand 2 "" "")])] 12700 "" 12701 " 12702{ 12703 int i; 12704 12705 emit_call_insn (GEN_CALL (operands[0], const0_rtx, const0_rtx, const0_rtx)); 12706 12707 for (i = 0; i < XVECLEN (operands[2], 0); i++) 12708 { 12709 rtx set = XVECEXP (operands[2], 0, i); 12710 emit_move_insn (SET_DEST (set), SET_SRC (set)); 12711 } 12712 12713 /* The optimizer does not know that the call sets the function value 12714 registers we stored in the result block. We avoid problems by 12715 claiming that all hard registers are used and clobbered at this 12716 point. */ 12717 emit_insn (gen_blockage ()); 12718 12719 DONE; 12720}") 12721 12722;; sibling call patterns 12723(define_expand "sibcall" 12724 [(parallel [(call (mem:SI (match_operand 0 "address_operand" "")) 12725 (match_operand 1 "" "")) 12726 (use (match_operand 2 "" "")) 12727 (use (reg:SI LR_REGNO)) 12728 (simple_return)])] 12729 "" 12730 " 12731{ 12732#if TARGET_MACHO 12733 if (MACHOPIC_INDIRECT) 12734 operands[0] = machopic_indirect_call_target (operands[0]); 12735#endif 12736 12737 gcc_assert (GET_CODE (operands[0]) == MEM); 12738 gcc_assert (GET_CODE (operands[1]) == CONST_INT); 12739 12740 operands[0] = XEXP (operands[0], 0); 12741 12742 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) 12743 { 12744 rs6000_sibcall_aix (NULL_RTX, operands[0], operands[1], operands[2]); 12745 DONE; 12746 } 12747}") 12748 12749(define_expand "sibcall_value" 12750 [(parallel [(set (match_operand 0 "register_operand" "") 12751 (call (mem:SI (match_operand 1 "address_operand" "")) 12752 (match_operand 2 "" ""))) 12753 (use (match_operand 3 "" "")) 12754 (use (reg:SI LR_REGNO)) 12755 (simple_return)])] 12756 "" 12757 " 12758{ 12759#if TARGET_MACHO 12760 if (MACHOPIC_INDIRECT) 12761 operands[1] = machopic_indirect_call_target (operands[1]); 12762#endif 12763 12764 gcc_assert (GET_CODE (operands[1]) == MEM); 12765 gcc_assert (GET_CODE (operands[2]) == CONST_INT); 12766 12767 operands[1] = XEXP (operands[1], 0); 12768 12769 if (DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2) 12770 { 12771 rs6000_sibcall_aix (operands[0], operands[1], operands[2], operands[3]); 12772 DONE; 12773 } 12774}") 12775 12776;; this and similar patterns must be marked as using LR, otherwise 12777;; dataflow will try to delete the store into it. This is true 12778;; even when the actual reg to jump to is in CTR, when LR was 12779;; saved and restored around the PIC-setting BCL. 12780(define_insn "*sibcall_local32" 12781 [(call (mem:SI (match_operand:SI 0 "current_file_function_operand" "s,s")) 12782 (match_operand 1 "" "g,g")) 12783 (use (match_operand:SI 2 "immediate_operand" "O,n")) 12784 (use (reg:SI LR_REGNO)) 12785 (simple_return)] 12786 "(INTVAL (operands[2]) & CALL_LONG) == 0" 12787 "* 12788{ 12789 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 12790 output_asm_insn (\"crxor 6,6,6\", operands); 12791 12792 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 12793 output_asm_insn (\"creqv 6,6,6\", operands); 12794 12795 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; 12796}" 12797 [(set_attr "type" "branch") 12798 (set_attr "length" "4,8")]) 12799 12800(define_insn "*sibcall_local64" 12801 [(call (mem:SI (match_operand:DI 0 "current_file_function_operand" "s,s")) 12802 (match_operand 1 "" "g,g")) 12803 (use (match_operand:SI 2 "immediate_operand" "O,n")) 12804 (use (reg:SI LR_REGNO)) 12805 (simple_return)] 12806 "TARGET_64BIT && (INTVAL (operands[2]) & CALL_LONG) == 0" 12807 "* 12808{ 12809 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 12810 output_asm_insn (\"crxor 6,6,6\", operands); 12811 12812 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 12813 output_asm_insn (\"creqv 6,6,6\", operands); 12814 12815 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z0@local\" : \"b %z0\"; 12816}" 12817 [(set_attr "type" "branch") 12818 (set_attr "length" "4,8")]) 12819 12820(define_insn "*sibcall_value_local32" 12821 [(set (match_operand 0 "" "") 12822 (call (mem:SI (match_operand:SI 1 "current_file_function_operand" "s,s")) 12823 (match_operand 2 "" "g,g"))) 12824 (use (match_operand:SI 3 "immediate_operand" "O,n")) 12825 (use (reg:SI LR_REGNO)) 12826 (simple_return)] 12827 "(INTVAL (operands[3]) & CALL_LONG) == 0" 12828 "* 12829{ 12830 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 12831 output_asm_insn (\"crxor 6,6,6\", operands); 12832 12833 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 12834 output_asm_insn (\"creqv 6,6,6\", operands); 12835 12836 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; 12837}" 12838 [(set_attr "type" "branch") 12839 (set_attr "length" "4,8")]) 12840 12841(define_insn "*sibcall_value_local64" 12842 [(set (match_operand 0 "" "") 12843 (call (mem:SI (match_operand:DI 1 "current_file_function_operand" "s,s")) 12844 (match_operand 2 "" "g,g"))) 12845 (use (match_operand:SI 3 "immediate_operand" "O,n")) 12846 (use (reg:SI LR_REGNO)) 12847 (simple_return)] 12848 "TARGET_64BIT && (INTVAL (operands[3]) & CALL_LONG) == 0" 12849 "* 12850{ 12851 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 12852 output_asm_insn (\"crxor 6,6,6\", operands); 12853 12854 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 12855 output_asm_insn (\"creqv 6,6,6\", operands); 12856 12857 return (DEFAULT_ABI == ABI_V4 && flag_pic) ? \"b %z1@local\" : \"b %z1\"; 12858}" 12859 [(set_attr "type" "branch") 12860 (set_attr "length" "4,8")]) 12861 12862(define_insn "*sibcall_nonlocal_sysv<mode>" 12863 [(call (mem:SI (match_operand:P 0 "call_operand" "s,s,c,c")) 12864 (match_operand 1 "" "")) 12865 (use (match_operand 2 "immediate_operand" "O,n,O,n")) 12866 (use (reg:SI LR_REGNO)) 12867 (simple_return)] 12868 "(DEFAULT_ABI == ABI_DARWIN 12869 || DEFAULT_ABI == ABI_V4) 12870 && (INTVAL (operands[2]) & CALL_LONG) == 0" 12871 "* 12872{ 12873 if (INTVAL (operands[2]) & CALL_V4_SET_FP_ARGS) 12874 output_asm_insn (\"crxor 6,6,6\", operands); 12875 12876 else if (INTVAL (operands[2]) & CALL_V4_CLEAR_FP_ARGS) 12877 output_asm_insn (\"creqv 6,6,6\", operands); 12878 12879 if (which_alternative >= 2) 12880 return \"b%T0\"; 12881 else if (DEFAULT_ABI == ABI_V4 && flag_pic) 12882 { 12883 gcc_assert (!TARGET_SECURE_PLT); 12884 return \"b %z0@plt\"; 12885 } 12886 else 12887 return \"b %z0\"; 12888}" 12889 [(set_attr "type" "branch") 12890 (set_attr "length" "4,8,4,8")]) 12891 12892(define_insn "*sibcall_value_nonlocal_sysv<mode>" 12893 [(set (match_operand 0 "" "") 12894 (call (mem:SI (match_operand:P 1 "call_operand" "s,s,c,c")) 12895 (match_operand 2 "" ""))) 12896 (use (match_operand:SI 3 "immediate_operand" "O,n,O,n")) 12897 (use (reg:SI LR_REGNO)) 12898 (simple_return)] 12899 "(DEFAULT_ABI == ABI_DARWIN 12900 || DEFAULT_ABI == ABI_V4) 12901 && (INTVAL (operands[3]) & CALL_LONG) == 0" 12902 "* 12903{ 12904 if (INTVAL (operands[3]) & CALL_V4_SET_FP_ARGS) 12905 output_asm_insn (\"crxor 6,6,6\", operands); 12906 12907 else if (INTVAL (operands[3]) & CALL_V4_CLEAR_FP_ARGS) 12908 output_asm_insn (\"creqv 6,6,6\", operands); 12909 12910 if (which_alternative >= 2) 12911 return \"b%T1\"; 12912 else if (DEFAULT_ABI == ABI_V4 && flag_pic) 12913 { 12914 gcc_assert (!TARGET_SECURE_PLT); 12915 return \"b %z1@plt\"; 12916 } 12917 else 12918 return \"b %z1\"; 12919}" 12920 [(set_attr "type" "branch") 12921 (set_attr "length" "4,8,4,8")]) 12922 12923;; AIX ABI sibling call patterns. 12924 12925(define_insn "*sibcall_aix<mode>" 12926 [(call (mem:SI (match_operand:P 0 "call_operand" "s,c")) 12927 (match_operand 1 "" "g,g")) 12928 (simple_return)] 12929 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" 12930 "@ 12931 b %z0 12932 b%T0" 12933 [(set_attr "type" "branch") 12934 (set_attr "length" "4")]) 12935 12936(define_insn "*sibcall_value_aix<mode>" 12937 [(set (match_operand 0 "" "") 12938 (call (mem:SI (match_operand:P 1 "call_operand" "s,c")) 12939 (match_operand 2 "" "g,g"))) 12940 (simple_return)] 12941 "DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_ELFv2" 12942 "@ 12943 b %z1 12944 b%T1" 12945 [(set_attr "type" "branch") 12946 (set_attr "length" "4")]) 12947 12948(define_expand "sibcall_epilogue" 12949 [(use (const_int 0))] 12950 "" 12951{ 12952 if (!TARGET_SCHED_PROLOG) 12953 emit_insn (gen_blockage ()); 12954 rs6000_emit_epilogue (TRUE); 12955 DONE; 12956}) 12957 12958;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 12959;; all of memory. This blocks insns from being moved across this point. 12960 12961(define_insn "blockage" 12962 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCK)] 12963 "" 12964 "") 12965 12966(define_expand "probe_stack" 12967 [(set (match_operand 0 "memory_operand" "=m") 12968 (unspec [(const_int 0)] UNSPEC_PROBE_STACK))] 12969 "" 12970{ 12971 if (TARGET_64BIT) 12972 emit_insn (gen_probe_stack_di (operands[0])); 12973 else 12974 emit_insn (gen_probe_stack_si (operands[0])); 12975 DONE; 12976}) 12977 12978(define_insn "probe_stack_<mode>" 12979 [(set (match_operand:P 0 "memory_operand" "=m") 12980 (unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))] 12981 "" 12982{ 12983 operands[1] = gen_rtx_REG (Pmode, 0); 12984 return "st<wd>%U0%X0 %1,%0"; 12985} 12986 [(set (attr "type") 12987 (if_then_else 12988 (match_test "update_indexed_address_mem (operands[0], VOIDmode)") 12989 (const_string "store_ux") 12990 (if_then_else 12991 (match_test "update_address_mem (operands[0], VOIDmode)") 12992 (const_string "store_u") 12993 (const_string "store")))) 12994 (set_attr "length" "4")]) 12995 12996(define_insn "probe_stack_range<P:mode>" 12997 [(set (match_operand:P 0 "register_operand" "=r") 12998 (unspec_volatile:P [(match_operand:P 1 "register_operand" "0") 12999 (match_operand:P 2 "register_operand" "r")] 13000 UNSPECV_PROBE_STACK_RANGE))] 13001 "" 13002 "* return output_probe_stack_range (operands[0], operands[2]);" 13003 [(set_attr "type" "three")]) 13004 13005;; Compare insns are next. Note that the RS/6000 has two types of compares, 13006;; signed & unsigned, and one type of branch. 13007;; 13008;; Start with the DEFINE_EXPANDs to generate the rtl for compares, scc 13009;; insns, and branches. 13010 13011(define_expand "cbranch<mode>4" 13012 [(use (match_operator 0 "rs6000_cbranch_operator" 13013 [(match_operand:GPR 1 "gpc_reg_operand" "") 13014 (match_operand:GPR 2 "reg_or_short_operand" "")])) 13015 (use (match_operand 3 ""))] 13016 "" 13017 " 13018{ 13019 /* Take care of the possibility that operands[2] might be negative but 13020 this might be a logical operation. That insn doesn't exist. */ 13021 if (GET_CODE (operands[2]) == CONST_INT 13022 && INTVAL (operands[2]) < 0) 13023 { 13024 operands[2] = force_reg (<MODE>mode, operands[2]); 13025 operands[0] = gen_rtx_fmt_ee (GET_CODE (operands[0]), 13026 GET_MODE (operands[0]), 13027 operands[1], operands[2]); 13028 } 13029 13030 rs6000_emit_cbranch (<MODE>mode, operands); 13031 DONE; 13032}") 13033 13034(define_expand "cbranch<mode>4" 13035 [(use (match_operator 0 "rs6000_cbranch_operator" 13036 [(match_operand:FP 1 "gpc_reg_operand" "") 13037 (match_operand:FP 2 "gpc_reg_operand" "")])) 13038 (use (match_operand 3 ""))] 13039 "" 13040 " 13041{ 13042 rs6000_emit_cbranch (<MODE>mode, operands); 13043 DONE; 13044}") 13045 13046(define_expand "cstore<mode>4" 13047 [(use (match_operator 1 "rs6000_cbranch_operator" 13048 [(match_operand:GPR 2 "gpc_reg_operand" "") 13049 (match_operand:GPR 3 "reg_or_short_operand" "")])) 13050 (clobber (match_operand:SI 0 "register_operand"))] 13051 "" 13052 " 13053{ 13054 /* Take care of the possibility that operands[3] might be negative but 13055 this might be a logical operation. That insn doesn't exist. */ 13056 if (GET_CODE (operands[3]) == CONST_INT 13057 && INTVAL (operands[3]) < 0) 13058 { 13059 operands[3] = force_reg (<MODE>mode, operands[3]); 13060 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), 13061 GET_MODE (operands[1]), 13062 operands[2], operands[3]); 13063 } 13064 13065 /* For SNE, we would prefer that the xor/abs sequence be used for integers. 13066 For SEQ, likewise, except that comparisons with zero should be done 13067 with an scc insns. However, due to the order that combine see the 13068 resulting insns, we must, in fact, allow SEQ for integers. Fail in 13069 the cases we don't want to handle or are best handled by portable 13070 code. */ 13071 if (GET_CODE (operands[1]) == NE) 13072 FAIL; 13073 if ((GET_CODE (operands[1]) == LT || GET_CODE (operands[1]) == LE 13074 || GET_CODE (operands[1]) == GT || GET_CODE (operands[1]) == GE) 13075 && operands[3] == const0_rtx) 13076 FAIL; 13077 rs6000_emit_sCOND (<MODE>mode, operands); 13078 DONE; 13079}") 13080 13081(define_expand "cstore<mode>4" 13082 [(use (match_operator 1 "rs6000_cbranch_operator" 13083 [(match_operand:FP 2 "gpc_reg_operand" "") 13084 (match_operand:FP 3 "gpc_reg_operand" "")])) 13085 (clobber (match_operand:SI 0 "register_operand"))] 13086 "" 13087 " 13088{ 13089 rs6000_emit_sCOND (<MODE>mode, operands); 13090 DONE; 13091}") 13092 13093 13094(define_expand "stack_protect_set" 13095 [(match_operand 0 "memory_operand" "") 13096 (match_operand 1 "memory_operand" "")] 13097 "" 13098{ 13099#ifdef TARGET_THREAD_SSP_OFFSET 13100 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2); 13101 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET)); 13102 operands[1] = gen_rtx_MEM (Pmode, addr); 13103#endif 13104 if (TARGET_64BIT) 13105 emit_insn (gen_stack_protect_setdi (operands[0], operands[1])); 13106 else 13107 emit_insn (gen_stack_protect_setsi (operands[0], operands[1])); 13108 DONE; 13109}) 13110 13111(define_insn "stack_protect_setsi" 13112 [(set (match_operand:SI 0 "memory_operand" "=m") 13113 (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET)) 13114 (set (match_scratch:SI 2 "=&r") (const_int 0))] 13115 "TARGET_32BIT" 13116 "lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0" 13117 [(set_attr "type" "three") 13118 (set_attr "length" "12")]) 13119 13120(define_insn "stack_protect_setdi" 13121 [(set (match_operand:DI 0 "memory_operand" "=Y") 13122 (unspec:DI [(match_operand:DI 1 "memory_operand" "Y")] UNSPEC_SP_SET)) 13123 (set (match_scratch:DI 2 "=&r") (const_int 0))] 13124 "TARGET_64BIT" 13125 "ld%U1%X1 %2,%1\;std%U0%X0 %2,%0\;li %2,0" 13126 [(set_attr "type" "three") 13127 (set_attr "length" "12")]) 13128 13129(define_expand "stack_protect_test" 13130 [(match_operand 0 "memory_operand" "") 13131 (match_operand 1 "memory_operand" "") 13132 (match_operand 2 "" "")] 13133 "" 13134{ 13135 rtx test, op0, op1; 13136#ifdef TARGET_THREAD_SSP_OFFSET 13137 rtx tlsreg = gen_rtx_REG (Pmode, TARGET_64BIT ? 13 : 2); 13138 rtx addr = gen_rtx_PLUS (Pmode, tlsreg, GEN_INT (TARGET_THREAD_SSP_OFFSET)); 13139 operands[1] = gen_rtx_MEM (Pmode, addr); 13140#endif 13141 op0 = operands[0]; 13142 op1 = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, operands[1]), UNSPEC_SP_TEST); 13143 test = gen_rtx_EQ (VOIDmode, op0, op1); 13144 emit_jump_insn (gen_cbranchsi4 (test, op0, op1, operands[2])); 13145 DONE; 13146}) 13147 13148(define_insn "stack_protect_testsi" 13149 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") 13150 (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m") 13151 (match_operand:SI 2 "memory_operand" "m,m")] 13152 UNSPEC_SP_TEST)) 13153 (set (match_scratch:SI 4 "=r,r") (const_int 0)) 13154 (clobber (match_scratch:SI 3 "=&r,&r"))] 13155 "TARGET_32BIT" 13156 "@ 13157 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0 13158 lwz%U1%X1 %3,%1\;lwz%U2%X2 %4,%2\;cmplw %0,%3,%4\;li %3,0\;li %4,0" 13159 [(set_attr "length" "16,20")]) 13160 13161(define_insn "stack_protect_testdi" 13162 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") 13163 (unspec:CCEQ [(match_operand:DI 1 "memory_operand" "Y,Y") 13164 (match_operand:DI 2 "memory_operand" "Y,Y")] 13165 UNSPEC_SP_TEST)) 13166 (set (match_scratch:DI 4 "=r,r") (const_int 0)) 13167 (clobber (match_scratch:DI 3 "=&r,&r"))] 13168 "TARGET_64BIT" 13169 "@ 13170 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;xor. %3,%3,%4\;li %4,0 13171 ld%U1%X1 %3,%1\;ld%U2%X2 %4,%2\;cmpld %0,%3,%4\;li %3,0\;li %4,0" 13172 [(set_attr "length" "16,20")]) 13173 13174 13175;; Here are the actual compare insns. 13176(define_insn "*cmp<mode>_internal1" 13177 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 13178 (compare:CC (match_operand:GPR 1 "gpc_reg_operand" "r") 13179 (match_operand:GPR 2 "reg_or_short_operand" "rI")))] 13180 "" 13181 "cmp<wd>%I2 %0,%1,%2" 13182 [(set_attr "type" "cmp")]) 13183 13184;; If we are comparing a register for equality with a large constant, 13185;; we can do this with an XOR followed by a compare. But this is profitable 13186;; only if the large constant is only used for the comparison (and in this 13187;; case we already have a register to reuse as scratch). 13188;; 13189;; For 64-bit registers, we could only do so if the constant's bit 15 is clear: 13190;; otherwise we'd need to XOR with FFFFFFFF????0000 which is not available. 13191 13192(define_peephole2 13193 [(set (match_operand:SI 0 "register_operand") 13194 (match_operand:SI 1 "logical_const_operand" "")) 13195 (set (match_dup 0) (match_operator:SI 3 "boolean_or_operator" 13196 [(match_dup 0) 13197 (match_operand:SI 2 "logical_const_operand" "")])) 13198 (set (match_operand:CC 4 "cc_reg_operand" "") 13199 (compare:CC (match_operand:SI 5 "gpc_reg_operand" "") 13200 (match_dup 0))) 13201 (set (pc) 13202 (if_then_else (match_operator 6 "equality_operator" 13203 [(match_dup 4) (const_int 0)]) 13204 (match_operand 7 "" "") 13205 (match_operand 8 "" "")))] 13206 "peep2_reg_dead_p (3, operands[0]) 13207 && peep2_reg_dead_p (4, operands[4])" 13208 [(set (match_dup 0) (xor:SI (match_dup 5) (match_dup 9))) 13209 (set (match_dup 4) (compare:CC (match_dup 0) (match_dup 10))) 13210 (set (pc) (if_then_else (match_dup 6) (match_dup 7) (match_dup 8)))] 13211 13212{ 13213 /* Get the constant we are comparing against, and see what it looks like 13214 when sign-extended from 16 to 32 bits. Then see what constant we could 13215 XOR with SEXTC to get the sign-extended value. */ 13216 rtx cnst = simplify_const_binary_operation (GET_CODE (operands[3]), 13217 SImode, 13218 operands[1], operands[2]); 13219 HOST_WIDE_INT c = INTVAL (cnst); 13220 HOST_WIDE_INT sextc = ((c & 0xffff) ^ 0x8000) - 0x8000; 13221 HOST_WIDE_INT xorv = c ^ sextc; 13222 13223 operands[9] = GEN_INT (xorv); 13224 operands[10] = GEN_INT (sextc); 13225}) 13226 13227(define_insn "*cmpsi_internal2" 13228 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 13229 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 13230 (match_operand:SI 2 "reg_or_u_short_operand" "rK")))] 13231 "" 13232 "cmplw%I2 %0,%1,%b2" 13233 [(set_attr "type" "cmp")]) 13234 13235(define_insn "*cmpdi_internal2" 13236 [(set (match_operand:CCUNS 0 "cc_reg_operand" "=y") 13237 (compare:CCUNS (match_operand:DI 1 "gpc_reg_operand" "r") 13238 (match_operand:DI 2 "reg_or_u_short_operand" "rK")))] 13239 "" 13240 "cmpld%I2 %0,%1,%b2" 13241 [(set_attr "type" "cmp")]) 13242 13243;; The following two insns don't exist as single insns, but if we provide 13244;; them, we can swap an add and compare, which will enable us to overlap more 13245;; of the required delay between a compare and branch. We generate code for 13246;; them by splitting. 13247 13248(define_insn "" 13249 [(set (match_operand:CC 3 "cc_reg_operand" "=y") 13250 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "r") 13251 (match_operand:SI 2 "short_cint_operand" "i"))) 13252 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 13253 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 13254 "" 13255 "#" 13256 [(set_attr "length" "8")]) 13257 13258(define_insn "" 13259 [(set (match_operand:CCUNS 3 "cc_reg_operand" "=y") 13260 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "r") 13261 (match_operand:SI 2 "u_short_cint_operand" "i"))) 13262 (set (match_operand:SI 0 "gpc_reg_operand" "=r") 13263 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "i")))] 13264 "" 13265 "#" 13266 [(set_attr "length" "8")]) 13267 13268(define_split 13269 [(set (match_operand:CC 3 "cc_reg_operand" "") 13270 (compare:CC (match_operand:SI 1 "gpc_reg_operand" "") 13271 (match_operand:SI 2 "short_cint_operand" ""))) 13272 (set (match_operand:SI 0 "gpc_reg_operand" "") 13273 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 13274 "" 13275 [(set (match_dup 3) (compare:CC (match_dup 1) (match_dup 2))) 13276 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 13277 13278(define_split 13279 [(set (match_operand:CCUNS 3 "cc_reg_operand" "") 13280 (compare:CCUNS (match_operand:SI 1 "gpc_reg_operand" "") 13281 (match_operand:SI 2 "u_short_cint_operand" ""))) 13282 (set (match_operand:SI 0 "gpc_reg_operand" "") 13283 (plus:SI (match_dup 1) (match_operand:SI 4 "short_cint_operand" "")))] 13284 "" 13285 [(set (match_dup 3) (compare:CCUNS (match_dup 1) (match_dup 2))) 13286 (set (match_dup 0) (plus:SI (match_dup 1) (match_dup 4)))]) 13287 13288;; Only need to compare second words if first words equal 13289(define_insn "*cmptf_internal1" 13290 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 13291 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d") 13292 (match_operand:TF 2 "gpc_reg_operand" "d")))] 13293 "!TARGET_IEEEQUAD && !TARGET_XL_COMPAT 13294 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" 13295 "fcmpu %0,%1,%2\;bne %0,$+8\;fcmpu %0,%L1,%L2" 13296 [(set_attr "type" "fpcompare") 13297 (set_attr "length" "12")]) 13298 13299(define_insn_and_split "*cmptf_internal2" 13300 [(set (match_operand:CCFP 0 "cc_reg_operand" "=y") 13301 (compare:CCFP (match_operand:TF 1 "gpc_reg_operand" "d") 13302 (match_operand:TF 2 "gpc_reg_operand" "d"))) 13303 (clobber (match_scratch:DF 3 "=d")) 13304 (clobber (match_scratch:DF 4 "=d")) 13305 (clobber (match_scratch:DF 5 "=d")) 13306 (clobber (match_scratch:DF 6 "=d")) 13307 (clobber (match_scratch:DF 7 "=d")) 13308 (clobber (match_scratch:DF 8 "=d")) 13309 (clobber (match_scratch:DF 9 "=d")) 13310 (clobber (match_scratch:DF 10 "=d")) 13311 (clobber (match_scratch:GPR 11 "=b"))] 13312 "!TARGET_IEEEQUAD && TARGET_XL_COMPAT 13313 && TARGET_HARD_FLOAT && TARGET_FPRS && TARGET_DOUBLE_FLOAT && TARGET_LONG_DOUBLE_128" 13314 "#" 13315 "&& reload_completed" 13316 [(set (match_dup 3) (match_dup 14)) 13317 (set (match_dup 4) (match_dup 15)) 13318 (set (match_dup 9) (abs:DF (match_dup 5))) 13319 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 3))) 13320 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0)) 13321 (label_ref (match_dup 12)) 13322 (pc))) 13323 (set (match_dup 0) (compare:CCFP (match_dup 5) (match_dup 7))) 13324 (set (pc) (label_ref (match_dup 13))) 13325 (match_dup 12) 13326 (set (match_dup 10) (minus:DF (match_dup 5) (match_dup 7))) 13327 (set (match_dup 9) (minus:DF (match_dup 6) (match_dup 8))) 13328 (set (match_dup 9) (plus:DF (match_dup 10) (match_dup 9))) 13329 (set (match_dup 0) (compare:CCFP (match_dup 9) (match_dup 4))) 13330 (match_dup 13)] 13331{ 13332 REAL_VALUE_TYPE rv; 13333 const int lo_word = LONG_DOUBLE_LARGE_FIRST ? GET_MODE_SIZE (DFmode) : 0; 13334 const int hi_word = LONG_DOUBLE_LARGE_FIRST ? 0 : GET_MODE_SIZE (DFmode); 13335 13336 operands[5] = simplify_gen_subreg (DFmode, operands[1], TFmode, hi_word); 13337 operands[6] = simplify_gen_subreg (DFmode, operands[1], TFmode, lo_word); 13338 operands[7] = simplify_gen_subreg (DFmode, operands[2], TFmode, hi_word); 13339 operands[8] = simplify_gen_subreg (DFmode, operands[2], TFmode, lo_word); 13340 operands[12] = gen_label_rtx (); 13341 operands[13] = gen_label_rtx (); 13342 real_inf (&rv); 13343 operands[14] = force_const_mem (DFmode, 13344 CONST_DOUBLE_FROM_REAL_VALUE (rv, DFmode)); 13345 operands[15] = force_const_mem (DFmode, 13346 CONST_DOUBLE_FROM_REAL_VALUE (dconst0, 13347 DFmode)); 13348 if (TARGET_TOC) 13349 { 13350 rtx tocref; 13351 tocref = create_TOC_reference (XEXP (operands[14], 0), operands[11]); 13352 operands[14] = gen_const_mem (DFmode, tocref); 13353 tocref = create_TOC_reference (XEXP (operands[15], 0), operands[11]); 13354 operands[15] = gen_const_mem (DFmode, tocref); 13355 set_mem_alias_set (operands[14], get_TOC_alias_set ()); 13356 set_mem_alias_set (operands[15], get_TOC_alias_set ()); 13357 } 13358}) 13359 13360;; Now we have the scc insns. We can do some combinations because of the 13361;; way the machine works. 13362;; 13363;; Note that this is probably faster if we can put an insn between the 13364;; mfcr and rlinm, but this is tricky. Let's leave it for now. In most 13365;; cases the insns below which don't use an intermediate CR field will 13366;; be used instead. 13367(define_insn "" 13368 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13369 (match_operator:SI 1 "scc_comparison_operator" 13370 [(match_operand 2 "cc_reg_operand" "y") 13371 (const_int 0)]))] 13372 "" 13373 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1" 13374 [(set (attr "type") 13375 (cond [(match_test "TARGET_MFCRF") 13376 (const_string "mfcrf") 13377 ] 13378 (const_string "mfcr"))) 13379 (set_attr "length" "8")]) 13380 13381;; Same as above, but get the GT bit. 13382(define_insn "move_from_CR_gt_bit" 13383 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13384 (unspec:SI [(match_operand 1 "cc_reg_operand" "y")] UNSPEC_MV_CR_GT))] 13385 "TARGET_HARD_FLOAT && !TARGET_FPRS" 13386 "mfcr %0\;rlwinm %0,%0,%D1,31,31" 13387 [(set_attr "type" "mfcr") 13388 (set_attr "length" "8")]) 13389 13390;; Same as above, but get the OV/ORDERED bit. 13391(define_insn "move_from_CR_ov_bit" 13392 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13393 (unspec:SI [(match_operand:CC 1 "cc_reg_operand" "y")] 13394 UNSPEC_MV_CR_OV))] 13395 "TARGET_ISEL" 13396 "mfcr %0\;rlwinm %0,%0,%t1,1" 13397 [(set_attr "type" "mfcr") 13398 (set_attr "length" "8")]) 13399 13400(define_insn "" 13401 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 13402 (match_operator:DI 1 "scc_comparison_operator" 13403 [(match_operand 2 "cc_reg_operand" "y") 13404 (const_int 0)]))] 13405 "TARGET_POWERPC64" 13406 "mfcr %0%Q2\;rlwinm %0,%0,%J1,1" 13407 [(set (attr "type") 13408 (cond [(match_test "TARGET_MFCRF") 13409 (const_string "mfcrf") 13410 ] 13411 (const_string "mfcr"))) 13412 (set_attr "length" "8")]) 13413 13414(define_insn "" 13415 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13416 (compare:CC (match_operator:SI 1 "scc_comparison_operator" 13417 [(match_operand 2 "cc_reg_operand" "y,y") 13418 (const_int 0)]) 13419 (const_int 0))) 13420 (set (match_operand:SI 3 "gpc_reg_operand" "=r,r") 13421 (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 13422 "TARGET_32BIT" 13423 "@ 13424 mfcr %3%Q2\;rlwinm. %3,%3,%J1,1 13425 #" 13426 [(set_attr "type" "delayed_compare") 13427 (set_attr "length" "8,16")]) 13428 13429(define_split 13430 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13431 (compare:CC (match_operator:SI 1 "scc_comparison_operator" 13432 [(match_operand 2 "cc_reg_operand" "") 13433 (const_int 0)]) 13434 (const_int 0))) 13435 (set (match_operand:SI 3 "gpc_reg_operand" "") 13436 (match_op_dup 1 [(match_dup 2) (const_int 0)]))] 13437 "TARGET_32BIT && reload_completed" 13438 [(set (match_dup 3) 13439 (match_op_dup 1 [(match_dup 2) (const_int 0)])) 13440 (set (match_dup 0) 13441 (compare:CC (match_dup 3) 13442 (const_int 0)))] 13443 "") 13444 13445(define_insn "" 13446 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13447 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 13448 [(match_operand 2 "cc_reg_operand" "y") 13449 (const_int 0)]) 13450 (match_operand:SI 3 "const_int_operand" "n")))] 13451 "" 13452 "* 13453{ 13454 int is_bit = ccr_bit (operands[1], 1); 13455 int put_bit = 31 - (INTVAL (operands[3]) & 31); 13456 int count; 13457 13458 if (is_bit >= put_bit) 13459 count = is_bit - put_bit; 13460 else 13461 count = 32 - (put_bit - is_bit); 13462 13463 operands[4] = GEN_INT (count); 13464 operands[5] = GEN_INT (put_bit); 13465 13466 return \"mfcr %0%Q2\;rlwinm %0,%0,%4,%5,%5\"; 13467}" 13468 [(set (attr "type") 13469 (cond [(match_test "TARGET_MFCRF") 13470 (const_string "mfcrf") 13471 ] 13472 (const_string "mfcr"))) 13473 (set_attr "length" "8")]) 13474 13475(define_insn "" 13476 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13477 (compare:CC 13478 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 13479 [(match_operand 2 "cc_reg_operand" "y,y") 13480 (const_int 0)]) 13481 (match_operand:SI 3 "const_int_operand" "n,n")) 13482 (const_int 0))) 13483 (set (match_operand:SI 4 "gpc_reg_operand" "=r,r") 13484 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 13485 (match_dup 3)))] 13486 "" 13487 "* 13488{ 13489 int is_bit = ccr_bit (operands[1], 1); 13490 int put_bit = 31 - (INTVAL (operands[3]) & 31); 13491 int count; 13492 13493 /* Force split for non-cc0 compare. */ 13494 if (which_alternative == 1) 13495 return \"#\"; 13496 13497 if (is_bit >= put_bit) 13498 count = is_bit - put_bit; 13499 else 13500 count = 32 - (put_bit - is_bit); 13501 13502 operands[5] = GEN_INT (count); 13503 operands[6] = GEN_INT (put_bit); 13504 13505 return \"mfcr %4%Q2\;rlwinm. %4,%4,%5,%6,%6\"; 13506}" 13507 [(set_attr "type" "delayed_compare") 13508 (set_attr "length" "8,16")]) 13509 13510(define_split 13511 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 13512 (compare:CC 13513 (ashift:SI (match_operator:SI 1 "scc_comparison_operator" 13514 [(match_operand 2 "cc_reg_operand" "") 13515 (const_int 0)]) 13516 (match_operand:SI 3 "const_int_operand" "")) 13517 (const_int 0))) 13518 (set (match_operand:SI 4 "gpc_reg_operand" "") 13519 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 13520 (match_dup 3)))] 13521 "reload_completed" 13522 [(set (match_dup 4) 13523 (ashift:SI (match_op_dup 1 [(match_dup 2) (const_int 0)]) 13524 (match_dup 3))) 13525 (set (match_dup 0) 13526 (compare:CC (match_dup 4) 13527 (const_int 0)))] 13528 "") 13529 13530;; There is a 3 cycle delay between consecutive mfcr instructions 13531;; so it is useful to combine 2 scc instructions to use only one mfcr. 13532 13533(define_peephole 13534 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 13535 (match_operator:SI 1 "scc_comparison_operator" 13536 [(match_operand 2 "cc_reg_operand" "y") 13537 (const_int 0)])) 13538 (set (match_operand:SI 3 "gpc_reg_operand" "=r") 13539 (match_operator:SI 4 "scc_comparison_operator" 13540 [(match_operand 5 "cc_reg_operand" "y") 13541 (const_int 0)]))] 13542 "REGNO (operands[2]) != REGNO (operands[5])" 13543 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1" 13544 [(set_attr "type" "mfcr") 13545 (set_attr "length" "12")]) 13546 13547(define_peephole 13548 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 13549 (match_operator:DI 1 "scc_comparison_operator" 13550 [(match_operand 2 "cc_reg_operand" "y") 13551 (const_int 0)])) 13552 (set (match_operand:DI 3 "gpc_reg_operand" "=r") 13553 (match_operator:DI 4 "scc_comparison_operator" 13554 [(match_operand 5 "cc_reg_operand" "y") 13555 (const_int 0)]))] 13556 "TARGET_POWERPC64 && REGNO (operands[2]) != REGNO (operands[5])" 13557 "mfcr %3\;rlwinm %0,%3,%J1,1\;rlwinm %3,%3,%J4,1" 13558 [(set_attr "type" "mfcr") 13559 (set_attr "length" "12")]) 13560 13561;; There are some scc insns that can be done directly, without a compare. 13562;; These are faster because they don't involve the communications between 13563;; the FXU and branch units. In fact, we will be replacing all of the 13564;; integer scc insns here or in the portable methods in emit_store_flag. 13565;; 13566;; Also support (neg (scc ..)) since that construct is used to replace 13567;; branches, (plus (scc ..) ..) since that construct is common and 13568;; takes no more insns than scc, and (and (neg (scc ..)) ..) in the 13569;; cases where it is no more expensive than (neg (scc ..)). 13570 13571;; Have reload force a constant into a register for the simple insns that 13572;; otherwise won't accept constants. We do this because it is faster than 13573;; the cmp/mfcr sequence we would otherwise generate. 13574 13575(define_mode_attr scc_eq_op2 [(SI "rKLI") 13576 (DI "rKJI")]) 13577 13578(define_insn_and_split "*eq<mode>" 13579 [(set (match_operand:GPR 0 "gpc_reg_operand" "=r") 13580 (eq:GPR (match_operand:GPR 1 "gpc_reg_operand" "r") 13581 (match_operand:GPR 2 "scc_eq_operand" "<scc_eq_op2>")))] 13582 "" 13583 "#" 13584 "" 13585 [(set (match_dup 0) 13586 (clz:GPR (match_dup 3))) 13587 (set (match_dup 0) 13588 (lshiftrt:GPR (match_dup 0) (match_dup 4)))] 13589 { 13590 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) 13591 { 13592 /* Use output operand as intermediate. */ 13593 operands[3] = operands[0]; 13594 13595 if (logical_operand (operands[2], <MODE>mode)) 13596 emit_insn (gen_rtx_SET (VOIDmode, operands[3], 13597 gen_rtx_XOR (<MODE>mode, 13598 operands[1], operands[2]))); 13599 else 13600 emit_insn (gen_rtx_SET (VOIDmode, operands[3], 13601 gen_rtx_PLUS (<MODE>mode, operands[1], 13602 negate_rtx (<MODE>mode, 13603 operands[2])))); 13604 } 13605 else 13606 operands[3] = operands[1]; 13607 13608 operands[4] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode))); 13609 }) 13610 13611(define_insn_and_split "*eq<mode>_compare" 13612 [(set (match_operand:CC 3 "cc_reg_operand" "=y") 13613 (compare:CC 13614 (eq:P (match_operand:P 1 "gpc_reg_operand" "=r") 13615 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>")) 13616 (const_int 0))) 13617 (set (match_operand:P 0 "gpc_reg_operand" "=r") 13618 (eq:P (match_dup 1) (match_dup 2)))] 13619 "optimize_size" 13620 "#" 13621 "optimize_size" 13622 [(set (match_dup 0) 13623 (clz:P (match_dup 4))) 13624 (parallel [(set (match_dup 3) 13625 (compare:CC (lshiftrt:P (match_dup 0) (match_dup 5)) 13626 (const_int 0))) 13627 (set (match_dup 0) 13628 (lshiftrt:P (match_dup 0) (match_dup 5)))])] 13629 { 13630 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) 13631 { 13632 /* Use output operand as intermediate. */ 13633 operands[4] = operands[0]; 13634 13635 if (logical_operand (operands[2], <MODE>mode)) 13636 emit_insn (gen_rtx_SET (VOIDmode, operands[4], 13637 gen_rtx_XOR (<MODE>mode, 13638 operands[1], operands[2]))); 13639 else 13640 emit_insn (gen_rtx_SET (VOIDmode, operands[4], 13641 gen_rtx_PLUS (<MODE>mode, operands[1], 13642 negate_rtx (<MODE>mode, 13643 operands[2])))); 13644 } 13645 else 13646 operands[4] = operands[1]; 13647 13648 operands[5] = GEN_INT (exact_log2 (GET_MODE_BITSIZE (<MODE>mode))); 13649 }) 13650 13651;; We have insns of the form shown by the first define_insn below. If 13652;; there is something inside the comparison operation, we must split it. 13653(define_split 13654 [(set (match_operand:SI 0 "gpc_reg_operand" "") 13655 (plus:SI (match_operator 1 "comparison_operator" 13656 [(match_operand:SI 2 "" "") 13657 (match_operand:SI 3 13658 "reg_or_cint_operand" "")]) 13659 (match_operand:SI 4 "gpc_reg_operand" ""))) 13660 (clobber (match_operand:SI 5 "register_operand" ""))] 13661 "! gpc_reg_operand (operands[2], SImode)" 13662 [(set (match_dup 5) (match_dup 2)) 13663 (set (match_dup 0) (plus:SI (match_op_dup 1 [(match_dup 5) (match_dup 3)]) 13664 (match_dup 4)))]) 13665 13666(define_insn "*plus_eqsi" 13667 [(set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r") 13668 (plus:SI (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r") 13669 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I")) 13670 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r")))] 13671 "TARGET_32BIT" 13672 "@ 13673 xor %0,%1,%2\;subfic %0,%0,0\;addze %0,%3 13674 subfic %0,%1,0\;addze %0,%3 13675 xori %0,%1,%b2\;subfic %0,%0,0\;addze %0,%3 13676 xoris %0,%1,%u2\;subfic %0,%0,0\;addze %0,%3 13677 subfic %0,%1,%2\;subfic %0,%0,0\;addze %0,%3" 13678 [(set_attr "type" "three,two,three,three,three") 13679 (set_attr "length" "12,8,12,12,12")]) 13680 13681(define_insn "*compare_plus_eqsi" 13682 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 13683 (compare:CC 13684 (plus:SI 13685 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 13686 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) 13687 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) 13688 (const_int 0))) 13689 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r"))] 13690 "TARGET_32BIT && optimize_size" 13691 "@ 13692 xor %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3 13693 subfic %4,%1,0\;addze. %4,%3 13694 xori %4,%1,%b2\;subfic %4,%4,0\;addze. %4,%3 13695 xoris %4,%1,%u2\;subfic %4,%4,0\;addze. %4,%3 13696 subfic %4,%1,%2\;subfic %4,%4,0\;addze. %4,%3 13697 # 13698 # 13699 # 13700 # 13701 #" 13702 [(set_attr "type" "compare") 13703 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 13704 13705(define_split 13706 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 13707 (compare:CC 13708 (plus:SI 13709 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 13710 (match_operand:SI 2 "scc_eq_operand" "")) 13711 (match_operand:SI 3 "gpc_reg_operand" "")) 13712 (const_int 0))) 13713 (clobber (match_scratch:SI 4 ""))] 13714 "TARGET_32BIT && optimize_size && reload_completed" 13715 [(set (match_dup 4) 13716 (plus:SI (eq:SI (match_dup 1) 13717 (match_dup 2)) 13718 (match_dup 3))) 13719 (set (match_dup 0) 13720 (compare:CC (match_dup 4) 13721 (const_int 0)))] 13722 "") 13723 13724(define_insn "*plus_eqsi_compare" 13725 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,x,x,x,?y,?y,?y,?y,?y") 13726 (compare:CC 13727 (plus:SI 13728 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "%r,r,r,r,r,r,r,r,r,r") 13729 (match_operand:SI 2 "scc_eq_operand" "r,O,K,L,I,r,O,K,L,I")) 13730 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r,r,r,r,r,r,r")) 13731 (const_int 0))) 13732 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r,&r,&r,&r,&r,&r,&r") 13733 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13734 "TARGET_32BIT && optimize_size" 13735 "@ 13736 xor %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3 13737 subfic %0,%1,0\;addze. %0,%3 13738 xori %0,%1,%b2\;subfic %0,%0,0\;addze. %0,%3 13739 xoris %0,%1,%u2\;subfic %0,%0,0\;addze. %0,%3 13740 subfic %0,%1,%2\;subfic %0,%0,0\;addze. %0,%3 13741 # 13742 # 13743 # 13744 # 13745 #" 13746 [(set_attr "type" "compare") 13747 (set_attr "length" "12,8,12,12,12,16,12,16,16,16")]) 13748 13749(define_split 13750 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 13751 (compare:CC 13752 (plus:SI 13753 (eq:SI (match_operand:SI 1 "gpc_reg_operand" "") 13754 (match_operand:SI 2 "scc_eq_operand" "")) 13755 (match_operand:SI 3 "gpc_reg_operand" "")) 13756 (const_int 0))) 13757 (set (match_operand:SI 0 "gpc_reg_operand" "") 13758 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 13759 "TARGET_32BIT && optimize_size && reload_completed" 13760 [(set (match_dup 0) 13761 (plus:SI (eq:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 13762 (set (match_dup 4) 13763 (compare:CC (match_dup 0) 13764 (const_int 0)))] 13765 "") 13766 13767(define_insn "*neg_eq0<mode>" 13768 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 13769 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "r") 13770 (const_int 0))))] 13771 "" 13772 "addic %0,%1,-1\;subfe %0,%0,%0" 13773 [(set_attr "type" "two") 13774 (set_attr "length" "8")]) 13775 13776(define_insn_and_split "*neg_eq<mode>" 13777 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 13778 (neg:P (eq:P (match_operand:P 1 "gpc_reg_operand" "%r") 13779 (match_operand:P 2 "scc_eq_operand" "<scc_eq_op2>"))))] 13780 "" 13781 "#" 13782 "" 13783 [(set (match_dup 0) (neg:P (eq:P (match_dup 3) (const_int 0))))] 13784 { 13785 if (GET_CODE (operands[2]) != CONST_INT || INTVAL (operands[2]) != 0) 13786 { 13787 /* Use output operand as intermediate. */ 13788 operands[3] = operands[0]; 13789 13790 if (logical_operand (operands[2], <MODE>mode)) 13791 emit_insn (gen_rtx_SET (VOIDmode, operands[3], 13792 gen_rtx_XOR (<MODE>mode, 13793 operands[1], operands[2]))); 13794 else 13795 emit_insn (gen_rtx_SET (VOIDmode, operands[3], 13796 gen_rtx_PLUS (<MODE>mode, operands[1], 13797 negate_rtx (<MODE>mode, 13798 operands[2])))); 13799 } 13800 else 13801 operands[3] = operands[1]; 13802 }) 13803 13804(define_insn "*ne0_<mode>" 13805 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 13806 (ne:P (match_operand:P 1 "gpc_reg_operand" "r") 13807 (const_int 0))) 13808 (clobber (match_scratch:P 2 "=&r"))] 13809 "!(TARGET_32BIT && TARGET_ISEL)" 13810 "addic %2,%1,-1\;subfe %0,%2,%1" 13811 [(set_attr "type" "two") 13812 (set_attr "length" "8")]) 13813 13814(define_insn "*plus_ne0_<mode>" 13815 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 13816 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r") 13817 (const_int 0)) 13818 (match_operand:P 2 "gpc_reg_operand" "r"))) 13819 (clobber (match_scratch:P 3 "=&r"))] 13820 "" 13821 "addic %3,%1,-1\;addze %0,%2" 13822 [(set_attr "type" "two") 13823 (set_attr "length" "8")]) 13824 13825(define_insn "*compare_plus_ne0_<mode>" 13826 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13827 (compare:CC (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r") 13828 (const_int 0)) 13829 (match_operand:P 2 "gpc_reg_operand" "r,r")) 13830 (const_int 0))) 13831 (clobber (match_scratch:P 3 "=&r,&r")) 13832 (clobber (match_scratch:P 4 "=X,&r"))] 13833 "" 13834 "@ 13835 addic %3,%1,-1\;addze. %3,%2 13836 #" 13837 [(set_attr "type" "compare") 13838 (set_attr "length" "8,12")]) 13839 13840(define_split 13841 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 13842 (compare:CC (ne:P (match_operand:SI 1 "gpc_reg_operand" "") 13843 (const_int 0)) 13844 (neg:P (match_operand:P 2 "gpc_reg_operand" "")))) 13845 (clobber (match_scratch:P 3 "")) 13846 (clobber (match_scratch:P 4 ""))] 13847 "reload_completed" 13848 [(parallel [(set (match_dup 3) 13849 (plus:P (ne:P (match_dup 1) 13850 (const_int 0)) 13851 (match_dup 2))) 13852 (clobber (match_dup 4))]) 13853 (set (match_dup 0) 13854 (compare:CC (match_dup 3) 13855 (const_int 0)))] 13856 "") 13857 13858; For combine. 13859(define_insn "*compare_plus_ne0_<mode>_1" 13860 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y") 13861 (compare:CCEQ (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r") 13862 (const_int 0)) 13863 (neg:P (match_operand:P 2 "gpc_reg_operand" "r,r")))) 13864 (clobber (match_scratch:P 3 "=&r,&r")) 13865 (clobber (match_scratch:P 4 "=X,&r"))] 13866 "" 13867 "@ 13868 addic %3,%1,-1\;addze. %3,%2 13869 #" 13870 [(set_attr "type" "compare") 13871 (set_attr "length" "8,12")]) 13872 13873(define_split 13874 [(set (match_operand:CCEQ 0 "cc_reg_not_micro_cr0_operand" "") 13875 (compare:CCEQ (ne:P (match_operand:SI 1 "gpc_reg_operand" "") 13876 (const_int 0)) 13877 (neg:P (match_operand:P 2 "gpc_reg_operand" "")))) 13878 (clobber (match_scratch:P 3 "")) 13879 (clobber (match_scratch:P 4 ""))] 13880 "reload_completed" 13881 [(parallel [(set (match_dup 3) 13882 (plus:P (ne:P (match_dup 1) 13883 (const_int 0)) 13884 (match_dup 2))) 13885 (clobber (match_dup 4))]) 13886 (set (match_dup 0) 13887 (compare:CC (match_dup 3) 13888 (const_int 0)))] 13889 "") 13890 13891(define_insn "*plus_ne0_<mode>_compare" 13892 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 13893 (compare:CC 13894 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "r,r") 13895 (const_int 0)) 13896 (match_operand:P 2 "gpc_reg_operand" "r,r")) 13897 (const_int 0))) 13898 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 13899 (plus:P (ne:P (match_dup 1) 13900 (const_int 0)) 13901 (match_dup 2))) 13902 (clobber (match_scratch:P 3 "=&r,&r"))] 13903 "" 13904 "@ 13905 addic %3,%1,-1\;addze. %0,%2 13906 #" 13907 [(set_attr "type" "compare") 13908 (set_attr "length" "8,12")]) 13909 13910(define_split 13911 [(set (match_operand:CC 4 "cc_reg_not_micro_cr0_operand" "") 13912 (compare:CC 13913 (plus:P (ne:P (match_operand:P 1 "gpc_reg_operand" "") 13914 (const_int 0)) 13915 (match_operand:P 2 "gpc_reg_operand" "")) 13916 (const_int 0))) 13917 (set (match_operand:P 0 "gpc_reg_operand" "") 13918 (plus:P (ne:P (match_dup 1) 13919 (const_int 0)) 13920 (match_dup 2))) 13921 (clobber (match_scratch:P 3 ""))] 13922 "reload_completed" 13923 [(parallel [(set (match_dup 0) 13924 (plus:P (ne:P (match_dup 1) 13925 (const_int 0)) 13926 (match_dup 2))) 13927 (clobber (match_dup 3))]) 13928 (set (match_dup 4) 13929 (compare:CC (match_dup 0) 13930 (const_int 0)))] 13931 "") 13932 13933(define_insn "*leu<mode>" 13934 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 13935 (leu:P (match_operand:P 1 "gpc_reg_operand" "r") 13936 (match_operand:P 2 "reg_or_short_operand" "rI")))] 13937 "" 13938 "subf%I2c %0,%1,%2\;li %0,0\;adde %0,%0,%0" 13939 [(set_attr "type" "three") 13940 (set_attr "length" "12")]) 13941 13942(define_insn "*leu<mode>_compare" 13943 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 13944 (compare:CC 13945 (leu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 13946 (match_operand:P 2 "reg_or_short_operand" "rI,rI")) 13947 (const_int 0))) 13948 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 13949 (leu:P (match_dup 1) (match_dup 2)))] 13950 "" 13951 "@ 13952 subf%I2c %0,%1,%2\;li %0,0\;adde. %0,%0,%0 13953 #" 13954 [(set_attr "type" "compare") 13955 (set_attr "length" "12,16")]) 13956 13957(define_split 13958 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 13959 (compare:CC 13960 (leu:P (match_operand:P 1 "gpc_reg_operand" "") 13961 (match_operand:P 2 "reg_or_short_operand" "")) 13962 (const_int 0))) 13963 (set (match_operand:P 0 "gpc_reg_operand" "") 13964 (leu:P (match_dup 1) (match_dup 2)))] 13965 "reload_completed" 13966 [(set (match_dup 0) 13967 (leu:P (match_dup 1) (match_dup 2))) 13968 (set (match_dup 3) 13969 (compare:CC (match_dup 0) 13970 (const_int 0)))] 13971 "") 13972 13973(define_insn "*plus_leu<mode>" 13974 [(set (match_operand:P 0 "gpc_reg_operand" "=&r") 13975 (plus:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") 13976 (match_operand:P 2 "reg_or_short_operand" "rI")) 13977 (match_operand:P 3 "gpc_reg_operand" "r")))] 13978 "" 13979 "subf%I2c %0,%1,%2\;addze %0,%3" 13980 [(set_attr "type" "two") 13981 (set_attr "length" "8")]) 13982 13983(define_insn "" 13984 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 13985 (compare:CC 13986 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 13987 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 13988 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 13989 (const_int 0))) 13990 (clobber (match_scratch:SI 4 "=&r,&r"))] 13991 "TARGET_32BIT" 13992 "@ 13993 subf%I2c %4,%1,%2\;addze. %4,%3 13994 #" 13995 [(set_attr "type" "compare") 13996 (set_attr "length" "8,12")]) 13997 13998(define_split 13999 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 14000 (compare:CC 14001 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 14002 (match_operand:SI 2 "reg_or_short_operand" "")) 14003 (match_operand:SI 3 "gpc_reg_operand" "")) 14004 (const_int 0))) 14005 (clobber (match_scratch:SI 4 ""))] 14006 "TARGET_32BIT && reload_completed" 14007 [(set (match_dup 4) 14008 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) 14009 (match_dup 3))) 14010 (set (match_dup 0) 14011 (compare:CC (match_dup 4) 14012 (const_int 0)))] 14013 "") 14014 14015(define_insn "" 14016 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 14017 (compare:CC 14018 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 14019 (match_operand:SI 2 "reg_or_short_operand" "rI,rI")) 14020 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 14021 (const_int 0))) 14022 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 14023 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 14024 "TARGET_32BIT" 14025 "@ 14026 subf%I2c %0,%1,%2\;addze. %0,%3 14027 #" 14028 [(set_attr "type" "compare") 14029 (set_attr "length" "8,12")]) 14030 14031(define_split 14032 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 14033 (compare:CC 14034 (plus:SI (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 14035 (match_operand:SI 2 "reg_or_short_operand" "")) 14036 (match_operand:SI 3 "gpc_reg_operand" "")) 14037 (const_int 0))) 14038 (set (match_operand:SI 0 "gpc_reg_operand" "") 14039 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 14040 "TARGET_32BIT && reload_completed" 14041 [(set (match_dup 0) 14042 (plus:SI (leu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 14043 (set (match_dup 4) 14044 (compare:CC (match_dup 0) 14045 (const_int 0)))] 14046 "") 14047 14048(define_insn "*neg_leu<mode>" 14049 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 14050 (neg:P (leu:P (match_operand:P 1 "gpc_reg_operand" "r") 14051 (match_operand:P 2 "reg_or_short_operand" "rI"))))] 14052 "" 14053 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;nand %0,%0,%0" 14054 [(set_attr "type" "three") 14055 (set_attr "length" "12")]) 14056 14057(define_insn "*and_neg_leu<mode>" 14058 [(set (match_operand:P 0 "gpc_reg_operand" "=&r") 14059 (and:P (neg:P 14060 (leu:P (match_operand:P 1 "gpc_reg_operand" "r") 14061 (match_operand:P 2 "reg_or_short_operand" "rI"))) 14062 (match_operand:P 3 "gpc_reg_operand" "r")))] 14063 "" 14064 "subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc %0,%3,%0" 14065 [(set_attr "type" "three") 14066 (set_attr "length" "12")]) 14067 14068(define_insn "" 14069 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 14070 (compare:CC 14071 (and:SI (neg:SI 14072 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 14073 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) 14074 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 14075 (const_int 0))) 14076 (clobber (match_scratch:SI 4 "=&r,&r"))] 14077 "TARGET_32BIT" 14078 "@ 14079 subf%I2c %4,%1,%2\;subfe %4,%4,%4\;andc. %4,%3,%4 14080 #" 14081 [(set_attr "type" "compare") 14082 (set_attr "length" "12,16")]) 14083 14084(define_split 14085 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 14086 (compare:CC 14087 (and:SI (neg:SI 14088 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 14089 (match_operand:SI 2 "reg_or_short_operand" ""))) 14090 (match_operand:SI 3 "gpc_reg_operand" "")) 14091 (const_int 0))) 14092 (clobber (match_scratch:SI 4 ""))] 14093 "TARGET_32BIT && reload_completed" 14094 [(set (match_dup 4) 14095 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) 14096 (match_dup 3))) 14097 (set (match_dup 0) 14098 (compare:CC (match_dup 4) 14099 (const_int 0)))] 14100 "") 14101 14102(define_insn "" 14103 [(set (match_operand:CC 4 "cc_reg_operand" "=x,?y") 14104 (compare:CC 14105 (and:SI (neg:SI 14106 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 14107 (match_operand:SI 2 "reg_or_short_operand" "rI,rI"))) 14108 (match_operand:SI 3 "gpc_reg_operand" "r,r")) 14109 (const_int 0))) 14110 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 14111 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 14112 "TARGET_32BIT" 14113 "@ 14114 subf%I2c %0,%1,%2\;subfe %0,%0,%0\;andc. %0,%3,%0 14115 #" 14116 [(set_attr "type" "compare") 14117 (set_attr "length" "12,16")]) 14118 14119(define_split 14120 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 14121 (compare:CC 14122 (and:SI (neg:SI 14123 (leu:SI (match_operand:SI 1 "gpc_reg_operand" "") 14124 (match_operand:SI 2 "reg_or_short_operand" ""))) 14125 (match_operand:SI 3 "gpc_reg_operand" "")) 14126 (const_int 0))) 14127 (set (match_operand:SI 0 "gpc_reg_operand" "") 14128 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 14129 "TARGET_32BIT && reload_completed" 14130 [(set (match_dup 0) 14131 (and:SI (neg:SI (leu:SI (match_dup 1) (match_dup 2))) 14132 (match_dup 3))) 14133 (set (match_dup 4) 14134 (compare:CC (match_dup 0) 14135 (const_int 0)))] 14136 "") 14137 14138(define_insn_and_split "*ltu<mode>" 14139 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") 14140 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 14141 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))] 14142 "" 14143 "#" 14144 "" 14145 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) 14146 (set (match_dup 0) (neg:P (match_dup 0)))] 14147 "") 14148 14149(define_insn_and_split "*ltu<mode>_compare" 14150 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 14151 (compare:CC 14152 (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") 14153 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) 14154 (const_int 0))) 14155 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") 14156 (ltu:P (match_dup 1) (match_dup 2)))] 14157 "" 14158 "#" 14159 "" 14160 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) 14161 (parallel [(set (match_dup 3) 14162 (compare:CC (neg:P (match_dup 0)) (const_int 0))) 14163 (set (match_dup 0) (neg:P (match_dup 0)))])] 14164 "") 14165 14166(define_insn_and_split "*plus_ltu<mode>" 14167 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,r") 14168 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 14169 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")) 14170 (match_operand:P 3 "reg_or_short_operand" "rI,rI")))] 14171 "" 14172 "#" 14173 "&& !reg_overlap_mentioned_p (operands[0], operands[3])" 14174 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) 14175 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] 14176 "") 14177 14178(define_insn_and_split "*plus_ltu<mode>_compare" 14179 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 14180 (compare:CC 14181 (plus:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") 14182 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) 14183 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r")) 14184 (const_int 0))) 14185 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r") 14186 (plus:P (ltu:P (match_dup 1) (match_dup 2)) (match_dup 3)))] 14187 "" 14188 "#" 14189 "&& !reg_overlap_mentioned_p (operands[0], operands[3])" 14190 [(set (match_dup 0) (neg:P (ltu:P (match_dup 1) (match_dup 2)))) 14191 (parallel [(set (match_dup 4) 14192 (compare:CC (minus:P (match_dup 3) (match_dup 0)) 14193 (const_int 0))) 14194 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])] 14195 "") 14196 14197(define_insn "*neg_ltu<mode>" 14198 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") 14199 (neg:P (ltu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 14200 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))))] 14201 "" 14202 "@ 14203 subfc %0,%2,%1\;subfe %0,%0,%0 14204 addic %0,%1,%n2\;subfe %0,%0,%0" 14205 [(set_attr "type" "two") 14206 (set_attr "length" "8")]) 14207 14208(define_insn "*geu<mode>" 14209 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") 14210 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 14211 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")))] 14212 "" 14213 "@ 14214 subfc %0,%2,%1\;li %0,0\;adde %0,%0,%0 14215 addic %0,%1,%n2\;li %0,0\;adde %0,%0,%0" 14216 [(set_attr "type" "three") 14217 (set_attr "length" "12")]) 14218 14219(define_insn "*geu<mode>_compare" 14220 [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y") 14221 (compare:CC 14222 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") 14223 (match_operand:P 2 "reg_or_neg_short_operand" "r,P,r,P")) 14224 (const_int 0))) 14225 (set (match_operand:P 0 "gpc_reg_operand" "=r,r,r,r") 14226 (geu:P (match_dup 1) (match_dup 2)))] 14227 "" 14228 "@ 14229 subfc %0,%2,%1\;li %0,0\;adde. %0,%0,%0 14230 addic %0,%1,%n2\;li %0,0\;adde. %0,%0,%0 14231 # 14232 #" 14233 [(set_attr "type" "compare") 14234 (set_attr "length" "12,12,16,16")]) 14235 14236(define_split 14237 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 14238 (compare:CC 14239 (geu:P (match_operand:P 1 "gpc_reg_operand" "") 14240 (match_operand:P 2 "reg_or_neg_short_operand" "")) 14241 (const_int 0))) 14242 (set (match_operand:P 0 "gpc_reg_operand" "") 14243 (geu:P (match_dup 1) (match_dup 2)))] 14244 "reload_completed" 14245 [(set (match_dup 0) 14246 (geu:P (match_dup 1) (match_dup 2))) 14247 (set (match_dup 3) 14248 (compare:CC (match_dup 0) 14249 (const_int 0)))] 14250 "") 14251 14252(define_insn "*plus_geu<mode>" 14253 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r") 14254 (plus:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 14255 (match_operand:P 2 "reg_or_neg_short_operand" "r,P")) 14256 (match_operand:P 3 "gpc_reg_operand" "r,r")))] 14257 "" 14258 "@ 14259 subfc %0,%2,%1\;addze %0,%3 14260 addic %0,%1,%n2\;addze %0,%3" 14261 [(set_attr "type" "two") 14262 (set_attr "length" "8")]) 14263 14264(define_insn "" 14265 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 14266 (compare:CC 14267 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 14268 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 14269 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 14270 (const_int 0))) 14271 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 14272 "TARGET_32BIT" 14273 "@ 14274 subfc %4,%2,%1\;addze. %4,%3 14275 addic %4,%1,%n2\;addze. %4,%3 14276 # 14277 #" 14278 [(set_attr "type" "compare") 14279 (set_attr "length" "8,8,12,12")]) 14280 14281(define_split 14282 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 14283 (compare:CC 14284 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 14285 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 14286 (match_operand:SI 3 "gpc_reg_operand" "")) 14287 (const_int 0))) 14288 (clobber (match_scratch:SI 4 ""))] 14289 "TARGET_32BIT && reload_completed" 14290 [(set (match_dup 4) 14291 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) 14292 (match_dup 3))) 14293 (set (match_dup 0) 14294 (compare:CC (match_dup 4) 14295 (const_int 0)))] 14296 "") 14297 14298(define_insn "" 14299 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 14300 (compare:CC 14301 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 14302 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P")) 14303 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 14304 (const_int 0))) 14305 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 14306 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 14307 "TARGET_32BIT" 14308 "@ 14309 subfc %0,%2,%1\;addze. %0,%3 14310 addic %0,%1,%n2\;addze. %0,%3 14311 # 14312 #" 14313 [(set_attr "type" "compare") 14314 (set_attr "length" "8,8,12,12")]) 14315 14316(define_split 14317 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 14318 (compare:CC 14319 (plus:SI (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 14320 (match_operand:SI 2 "reg_or_neg_short_operand" "")) 14321 (match_operand:SI 3 "gpc_reg_operand" "")) 14322 (const_int 0))) 14323 (set (match_operand:SI 0 "gpc_reg_operand" "") 14324 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3)))] 14325 "TARGET_32BIT && reload_completed" 14326 [(set (match_dup 0) 14327 (plus:SI (geu:SI (match_dup 1) (match_dup 2)) (match_dup 3))) 14328 (set (match_dup 4) 14329 (compare:CC (match_dup 0) 14330 (const_int 0)))] 14331 "") 14332 14333(define_insn "*neg_geu<mode>" 14334 [(set (match_operand:P 0 "gpc_reg_operand" "=r,r") 14335 (neg:P (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 14336 (match_operand:P 2 "reg_or_short_operand" "r,I"))))] 14337 "" 14338 "@ 14339 subfc %0,%2,%1\;subfe %0,%0,%0\;nand %0,%0,%0 14340 subfic %0,%1,-1\;add%I2c %0,%0,%2\;subfe %0,%0,%0" 14341 [(set_attr "type" "three") 14342 (set_attr "length" "12")]) 14343 14344(define_insn "*and_neg_geu<mode>" 14345 [(set (match_operand:P 0 "gpc_reg_operand" "=&r,&r") 14346 (and:P (neg:P 14347 (geu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 14348 (match_operand:P 2 "reg_or_neg_short_operand" "r,P"))) 14349 (match_operand:P 3 "gpc_reg_operand" "r,r")))] 14350 "" 14351 "@ 14352 subfc %0,%2,%1\;subfe %0,%0,%0\;andc %0,%3,%0 14353 addic %0,%1,%n2\;subfe %0,%0,%0\;andc %0,%3,%0" 14354 [(set_attr "type" "three") 14355 (set_attr "length" "12")]) 14356 14357(define_insn "" 14358 [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y") 14359 (compare:CC 14360 (and:SI (neg:SI 14361 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 14362 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) 14363 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 14364 (const_int 0))) 14365 (clobber (match_scratch:SI 4 "=&r,&r,&r,&r"))] 14366 "TARGET_32BIT" 14367 "@ 14368 subfc %4,%2,%1\;subfe %4,%4,%4\;andc. %4,%3,%4 14369 addic %4,%1,%n2\;subfe %4,%4,%4\;andc. %4,%3,%4 14370 # 14371 #" 14372 [(set_attr "type" "compare") 14373 (set_attr "length" "12,12,16,16")]) 14374 14375(define_split 14376 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 14377 (compare:CC 14378 (and:SI (neg:SI 14379 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 14380 (match_operand:SI 2 "reg_or_neg_short_operand" ""))) 14381 (match_operand:SI 3 "gpc_reg_operand" "")) 14382 (const_int 0))) 14383 (clobber (match_scratch:SI 4 ""))] 14384 "TARGET_32BIT && reload_completed" 14385 [(set (match_dup 4) 14386 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) 14387 (match_dup 3))) 14388 (set (match_dup 0) 14389 (compare:CC (match_dup 4) 14390 (const_int 0)))] 14391 "") 14392 14393(define_insn "" 14394 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 14395 (compare:CC 14396 (and:SI (neg:SI 14397 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r") 14398 (match_operand:SI 2 "reg_or_neg_short_operand" "r,P,r,P"))) 14399 (match_operand:SI 3 "gpc_reg_operand" "r,r,r,r")) 14400 (const_int 0))) 14401 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r,&r,&r") 14402 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 14403 "TARGET_32BIT" 14404 "@ 14405 subfc %0,%2,%1\;subfe %0,%0,%0\;andc. %0,%3,%0 14406 addic %0,%1,%n2\;subfe %0,%0,%0\;andc. %0,%3,%0 14407 # 14408 #" 14409 [(set_attr "type" "compare") 14410 (set_attr "length" "12,12,16,16")]) 14411 14412(define_split 14413 [(set (match_operand:CC 4 "cc_reg_not_cr0_operand" "") 14414 (compare:CC 14415 (and:SI (neg:SI 14416 (geu:SI (match_operand:SI 1 "gpc_reg_operand" "") 14417 (match_operand:SI 2 "reg_or_neg_short_operand" ""))) 14418 (match_operand:SI 3 "gpc_reg_operand" "")) 14419 (const_int 0))) 14420 (set (match_operand:SI 0 "gpc_reg_operand" "") 14421 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3)))] 14422 "TARGET_32BIT && reload_completed" 14423 [(set (match_dup 0) 14424 (and:SI (neg:SI (geu:SI (match_dup 1) (match_dup 2))) (match_dup 3))) 14425 (set (match_dup 4) 14426 (compare:CC (match_dup 0) 14427 (const_int 0)))] 14428 "") 14429 14430(define_insn "*plus_gt0<mode>" 14431 [(set (match_operand:P 0 "gpc_reg_operand" "=&r") 14432 (plus:P (gt:P (match_operand:P 1 "gpc_reg_operand" "r") 14433 (const_int 0)) 14434 (match_operand:P 2 "gpc_reg_operand" "r")))] 14435 "" 14436 "addc %0,%1,%1\;subfe %0,%1,%0\;addze %0,%2" 14437 [(set_attr "type" "three") 14438 (set_attr "length" "12")]) 14439 14440(define_insn "" 14441 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 14442 (compare:CC 14443 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 14444 (const_int 0)) 14445 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 14446 (const_int 0))) 14447 (clobber (match_scratch:SI 3 "=&r,&r"))] 14448 "TARGET_32BIT" 14449 "@ 14450 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 14451 #" 14452 [(set_attr "type" "compare") 14453 (set_attr "length" "12,16")]) 14454 14455(define_split 14456 [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "") 14457 (compare:CC 14458 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 14459 (const_int 0)) 14460 (match_operand:SI 2 "gpc_reg_operand" "")) 14461 (const_int 0))) 14462 (clobber (match_scratch:SI 3 ""))] 14463 "TARGET_32BIT && reload_completed" 14464 [(set (match_dup 3) 14465 (plus:SI (gt:SI (match_dup 1) (const_int 0)) 14466 (match_dup 2))) 14467 (set (match_dup 0) 14468 (compare:CC (match_dup 3) 14469 (const_int 0)))] 14470 "") 14471 14472(define_insn "" 14473 [(set (match_operand:CC 0 "cc_reg_operand" "=x,?y") 14474 (compare:CC 14475 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 14476 (const_int 0)) 14477 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 14478 (const_int 0))) 14479 (clobber (match_scratch:DI 3 "=&r,&r"))] 14480 "TARGET_64BIT" 14481 "@ 14482 addc %3,%1,%1\;subfe %3,%1,%3\;addze. %3,%2 14483 #" 14484 [(set_attr "type" "compare") 14485 (set_attr "length" "12,16")]) 14486 14487(define_split 14488 [(set (match_operand:CC 0 "cc_reg_not_micro_cr0_operand" "") 14489 (compare:CC 14490 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 14491 (const_int 0)) 14492 (match_operand:DI 2 "gpc_reg_operand" "")) 14493 (const_int 0))) 14494 (clobber (match_scratch:DI 3 ""))] 14495 "TARGET_64BIT && reload_completed" 14496 [(set (match_dup 3) 14497 (plus:DI (gt:DI (match_dup 1) (const_int 0)) 14498 (match_dup 2))) 14499 (set (match_dup 0) 14500 (compare:CC (match_dup 3) 14501 (const_int 0)))] 14502 "") 14503 14504(define_insn "" 14505 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 14506 (compare:CC 14507 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r") 14508 (const_int 0)) 14509 (match_operand:SI 2 "gpc_reg_operand" "r,r")) 14510 (const_int 0))) 14511 (set (match_operand:SI 0 "gpc_reg_operand" "=&r,&r") 14512 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] 14513 "TARGET_32BIT" 14514 "@ 14515 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 14516 #" 14517 [(set_attr "type" "compare") 14518 (set_attr "length" "12,16")]) 14519 14520(define_split 14521 [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "") 14522 (compare:CC 14523 (plus:SI (gt:SI (match_operand:SI 1 "gpc_reg_operand" "") 14524 (const_int 0)) 14525 (match_operand:SI 2 "gpc_reg_operand" "")) 14526 (const_int 0))) 14527 (set (match_operand:SI 0 "gpc_reg_operand" "") 14528 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2)))] 14529 "TARGET_32BIT && reload_completed" 14530 [(set (match_dup 0) 14531 (plus:SI (gt:SI (match_dup 1) (const_int 0)) (match_dup 2))) 14532 (set (match_dup 3) 14533 (compare:CC (match_dup 0) 14534 (const_int 0)))] 14535 "") 14536 14537(define_insn "" 14538 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 14539 (compare:CC 14540 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "r,r") 14541 (const_int 0)) 14542 (match_operand:DI 2 "gpc_reg_operand" "r,r")) 14543 (const_int 0))) 14544 (set (match_operand:DI 0 "gpc_reg_operand" "=&r,&r") 14545 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] 14546 "TARGET_64BIT" 14547 "@ 14548 addc %0,%1,%1\;subfe %0,%1,%0\;addze. %0,%2 14549 #" 14550 [(set_attr "type" "compare") 14551 (set_attr "length" "12,16")]) 14552 14553(define_split 14554 [(set (match_operand:CC 3 "cc_reg_not_micro_cr0_operand" "") 14555 (compare:CC 14556 (plus:DI (gt:DI (match_operand:DI 1 "gpc_reg_operand" "") 14557 (const_int 0)) 14558 (match_operand:DI 2 "gpc_reg_operand" "")) 14559 (const_int 0))) 14560 (set (match_operand:DI 0 "gpc_reg_operand" "") 14561 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2)))] 14562 "TARGET_64BIT && reload_completed" 14563 [(set (match_dup 0) 14564 (plus:DI (gt:DI (match_dup 1) (const_int 0)) (match_dup 2))) 14565 (set (match_dup 3) 14566 (compare:CC (match_dup 0) 14567 (const_int 0)))] 14568 "") 14569 14570(define_insn_and_split "*gtu<mode>" 14571 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 14572 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") 14573 (match_operand:P 2 "reg_or_short_operand" "rI")))] 14574 "" 14575 "#" 14576 "" 14577 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) 14578 (set (match_dup 0) (neg:P (match_dup 0)))] 14579 "") 14580 14581(define_insn_and_split "*gtu<mode>_compare" 14582 [(set (match_operand:CC 3 "cc_reg_operand" "=x,?y") 14583 (compare:CC 14584 (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r") 14585 (match_operand:P 2 "reg_or_short_operand" "rI,rI")) 14586 (const_int 0))) 14587 (set (match_operand:P 0 "gpc_reg_operand" "=r,r") 14588 (gtu:P (match_dup 1) (match_dup 2)))] 14589 "" 14590 "#" 14591 "" 14592 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) 14593 (parallel [(set (match_dup 3) 14594 (compare:CC (neg:P (match_dup 0)) (const_int 0))) 14595 (set (match_dup 0) (neg:P (match_dup 0)))])] 14596 "") 14597 14598(define_insn_and_split "*plus_gtu<mode>" 14599 [(set (match_operand:P 0 "gpc_reg_operand" "=&r") 14600 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") 14601 (match_operand:P 2 "reg_or_short_operand" "rI")) 14602 (match_operand:P 3 "reg_or_short_operand" "rI")))] 14603 "" 14604 "#" 14605 "&& !reg_overlap_mentioned_p (operands[0], operands[3])" 14606 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) 14607 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))] 14608 "") 14609 14610(define_insn_and_split "*plus_gtu<mode>_compare" 14611 [(set (match_operand:CC 4 "cc_reg_operand" "=x,x,?y,?y") 14612 (compare:CC 14613 (plus:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r,r,r,r") 14614 (match_operand:P 2 "reg_or_short_operand" "I,r,I,r")) 14615 (match_operand:P 3 "gpc_reg_operand" "r,r,r,r")) 14616 (const_int 0))) 14617 (set (match_operand:P 0 "gpc_reg_operand" "=&r,&r,&r,&r") 14618 (plus:P (gtu:P (match_dup 1) (match_dup 2)) (match_dup 3)))] 14619 "" 14620 "#" 14621 "&& !reg_overlap_mentioned_p (operands[0], operands[3])" 14622 [(set (match_dup 0) (neg:P (gtu:P (match_dup 1) (match_dup 2)))) 14623 (parallel [(set (match_dup 4) 14624 (compare:CC (minus:P (match_dup 3) (match_dup 0)) 14625 (const_int 0))) 14626 (set (match_dup 0) (minus:P (match_dup 3) (match_dup 0)))])] 14627 "") 14628 14629(define_insn "*neg_gtu<mode>" 14630 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 14631 (neg:P (gtu:P (match_operand:P 1 "gpc_reg_operand" "r") 14632 (match_operand:P 2 "reg_or_short_operand" "rI"))))] 14633 "" 14634 "subf%I2c %0,%1,%2\;subfe %0,%0,%0" 14635 [(set_attr "type" "two") 14636 (set_attr "length" "8")]) 14637 14638 14639;; Define both directions of branch and return. If we need a reload 14640;; register, we'd rather use CR0 since it is much easier to copy a 14641;; register CC value to there. 14642 14643(define_insn "" 14644 [(set (pc) 14645 (if_then_else (match_operator 1 "branch_comparison_operator" 14646 [(match_operand 2 14647 "cc_reg_operand" "y") 14648 (const_int 0)]) 14649 (label_ref (match_operand 0 "" "")) 14650 (pc)))] 14651 "" 14652 "* 14653{ 14654 return output_cbranch (operands[1], \"%l0\", 0, insn); 14655}" 14656 [(set_attr "type" "branch")]) 14657 14658(define_insn "" 14659 [(set (pc) 14660 (if_then_else (match_operator 0 "branch_comparison_operator" 14661 [(match_operand 1 14662 "cc_reg_operand" "y") 14663 (const_int 0)]) 14664 (any_return) 14665 (pc)))] 14666 "<return_pred>" 14667 "* 14668{ 14669 return output_cbranch (operands[0], NULL, 0, insn); 14670}" 14671 [(set_attr "type" "jmpreg") 14672 (set_attr "length" "4")]) 14673 14674(define_insn "" 14675 [(set (pc) 14676 (if_then_else (match_operator 1 "branch_comparison_operator" 14677 [(match_operand 2 14678 "cc_reg_operand" "y") 14679 (const_int 0)]) 14680 (pc) 14681 (label_ref (match_operand 0 "" ""))))] 14682 "" 14683 "* 14684{ 14685 return output_cbranch (operands[1], \"%l0\", 1, insn); 14686}" 14687 [(set_attr "type" "branch")]) 14688 14689(define_insn "" 14690 [(set (pc) 14691 (if_then_else (match_operator 0 "branch_comparison_operator" 14692 [(match_operand 1 14693 "cc_reg_operand" "y") 14694 (const_int 0)]) 14695 (pc) 14696 (any_return)))] 14697 "<return_pred>" 14698 "* 14699{ 14700 return output_cbranch (operands[0], NULL, 1, insn); 14701}" 14702 [(set_attr "type" "jmpreg") 14703 (set_attr "length" "4")]) 14704 14705;; Logic on condition register values. 14706 14707; This pattern matches things like 14708; (set (reg:CCEQ 68) (compare:CCEQ (ior:SI (gt:SI (reg:CCFP 68) (const_int 0)) 14709; (eq:SI (reg:CCFP 68) (const_int 0))) 14710; (const_int 1))) 14711; which are generated by the branch logic. 14712; Prefer destructive operations where BT = BB (for crXX BT,BA,BB) 14713 14714(define_insn "*cceq_ior_compare" 14715 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") 14716 (compare:CCEQ (match_operator:SI 1 "boolean_operator" 14717 [(match_operator:SI 2 14718 "branch_positive_comparison_operator" 14719 [(match_operand 3 14720 "cc_reg_operand" "y,y") 14721 (const_int 0)]) 14722 (match_operator:SI 4 14723 "branch_positive_comparison_operator" 14724 [(match_operand 5 14725 "cc_reg_operand" "0,y") 14726 (const_int 0)])]) 14727 (const_int 1)))] 14728 "" 14729 "cr%q1 %E0,%j2,%j4" 14730 [(set_attr "type" "cr_logical,delayed_cr")]) 14731 14732; Why is the constant -1 here, but 1 in the previous pattern? 14733; Because ~1 has all but the low bit set. 14734(define_insn "" 14735 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") 14736 (compare:CCEQ (match_operator:SI 1 "boolean_or_operator" 14737 [(not:SI (match_operator:SI 2 14738 "branch_positive_comparison_operator" 14739 [(match_operand 3 14740 "cc_reg_operand" "y,y") 14741 (const_int 0)])) 14742 (match_operator:SI 4 14743 "branch_positive_comparison_operator" 14744 [(match_operand 5 14745 "cc_reg_operand" "0,y") 14746 (const_int 0)])]) 14747 (const_int -1)))] 14748 "" 14749 "cr%q1 %E0,%j2,%j4" 14750 [(set_attr "type" "cr_logical,delayed_cr")]) 14751 14752(define_insn "*cceq_rev_compare" 14753 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y,?y") 14754 (compare:CCEQ (match_operator:SI 1 14755 "branch_positive_comparison_operator" 14756 [(match_operand 2 14757 "cc_reg_operand" "0,y") 14758 (const_int 0)]) 14759 (const_int 0)))] 14760 "" 14761 "crnot %E0,%j1" 14762 [(set_attr "type" "cr_logical,delayed_cr")]) 14763 14764;; If we are comparing the result of two comparisons, this can be done 14765;; using creqv or crxor. 14766 14767(define_insn_and_split "" 14768 [(set (match_operand:CCEQ 0 "cc_reg_operand" "=y") 14769 (compare:CCEQ (match_operator 1 "branch_comparison_operator" 14770 [(match_operand 2 "cc_reg_operand" "y") 14771 (const_int 0)]) 14772 (match_operator 3 "branch_comparison_operator" 14773 [(match_operand 4 "cc_reg_operand" "y") 14774 (const_int 0)])))] 14775 "" 14776 "#" 14777 "" 14778 [(set (match_dup 0) (compare:CCEQ (xor:SI (match_dup 1) (match_dup 3)) 14779 (match_dup 5)))] 14780 " 14781{ 14782 int positive_1, positive_2; 14783 14784 positive_1 = branch_positive_comparison_operator (operands[1], 14785 GET_MODE (operands[1])); 14786 positive_2 = branch_positive_comparison_operator (operands[3], 14787 GET_MODE (operands[3])); 14788 14789 if (! positive_1) 14790 operands[1] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[2]), 14791 GET_CODE (operands[1])), 14792 SImode, 14793 operands[2], const0_rtx); 14794 else if (GET_MODE (operands[1]) != SImode) 14795 operands[1] = gen_rtx_fmt_ee (GET_CODE (operands[1]), SImode, 14796 operands[2], const0_rtx); 14797 14798 if (! positive_2) 14799 operands[3] = gen_rtx_fmt_ee (rs6000_reverse_condition (GET_MODE (operands[4]), 14800 GET_CODE (operands[3])), 14801 SImode, 14802 operands[4], const0_rtx); 14803 else if (GET_MODE (operands[3]) != SImode) 14804 operands[3] = gen_rtx_fmt_ee (GET_CODE (operands[3]), SImode, 14805 operands[4], const0_rtx); 14806 14807 if (positive_1 == positive_2) 14808 { 14809 operands[1] = gen_rtx_NOT (SImode, operands[1]); 14810 operands[5] = constm1_rtx; 14811 } 14812 else 14813 { 14814 operands[5] = const1_rtx; 14815 } 14816}") 14817 14818;; Unconditional branch and return. 14819 14820(define_insn "jump" 14821 [(set (pc) 14822 (label_ref (match_operand 0 "" "")))] 14823 "" 14824 "b %l0" 14825 [(set_attr "type" "branch")]) 14826 14827(define_insn "<return_str>return" 14828 [(any_return)] 14829 "<return_pred>" 14830 "blr" 14831 [(set_attr "type" "jmpreg")]) 14832 14833(define_expand "indirect_jump" 14834 [(set (pc) (match_operand 0 "register_operand" ""))]) 14835 14836(define_insn "*indirect_jump<mode>" 14837 [(set (pc) (match_operand:P 0 "register_operand" "c,*l"))] 14838 "" 14839 "@ 14840 bctr 14841 blr" 14842 [(set_attr "type" "jmpreg")]) 14843 14844;; Table jump for switch statements: 14845(define_expand "tablejump" 14846 [(use (match_operand 0 "" "")) 14847 (use (label_ref (match_operand 1 "" "")))] 14848 "" 14849 " 14850{ 14851 if (TARGET_32BIT) 14852 emit_jump_insn (gen_tablejumpsi (operands[0], operands[1])); 14853 else 14854 emit_jump_insn (gen_tablejumpdi (operands[0], operands[1])); 14855 DONE; 14856}") 14857 14858(define_expand "tablejumpsi" 14859 [(set (match_dup 3) 14860 (plus:SI (match_operand:SI 0 "" "") 14861 (match_dup 2))) 14862 (parallel [(set (pc) (match_dup 3)) 14863 (use (label_ref (match_operand 1 "" "")))])] 14864 "TARGET_32BIT" 14865 " 14866{ operands[0] = force_reg (SImode, operands[0]); 14867 operands[2] = force_reg (SImode, gen_rtx_LABEL_REF (SImode, operands[1])); 14868 operands[3] = gen_reg_rtx (SImode); 14869}") 14870 14871(define_expand "tablejumpdi" 14872 [(set (match_dup 4) 14873 (sign_extend:DI (match_operand:SI 0 "lwa_operand" ""))) 14874 (set (match_dup 3) 14875 (plus:DI (match_dup 4) 14876 (match_dup 2))) 14877 (parallel [(set (pc) (match_dup 3)) 14878 (use (label_ref (match_operand 1 "" "")))])] 14879 "TARGET_64BIT" 14880 " 14881{ operands[2] = force_reg (DImode, gen_rtx_LABEL_REF (DImode, operands[1])); 14882 operands[3] = gen_reg_rtx (DImode); 14883 operands[4] = gen_reg_rtx (DImode); 14884}") 14885 14886(define_insn "*tablejump<mode>_internal1" 14887 [(set (pc) 14888 (match_operand:P 0 "register_operand" "c,*l")) 14889 (use (label_ref (match_operand 1 "" "")))] 14890 "" 14891 "@ 14892 bctr 14893 blr" 14894 [(set_attr "type" "jmpreg")]) 14895 14896(define_insn "nop" 14897 [(const_int 0)] 14898 "" 14899 "nop") 14900 14901(define_insn "group_ending_nop" 14902 [(unspec [(const_int 0)] UNSPEC_GRP_END_NOP)] 14903 "" 14904 "* 14905{ 14906 if (rs6000_cpu_attr == CPU_POWER6) 14907 return \"ori 1,1,0\"; 14908 return \"ori 2,2,0\"; 14909}") 14910 14911;; Define the subtract-one-and-jump insns, starting with the template 14912;; so loop.c knows what to generate. 14913 14914(define_expand "doloop_end" 14915 [(use (match_operand 0 "" "")) ; loop pseudo 14916 (use (match_operand 1 "" "")) ; iterations; zero if unknown 14917 (use (match_operand 2 "" "")) ; max iterations 14918 (use (match_operand 3 "" "")) ; loop level 14919 (use (match_operand 4 "" "")) ; label 14920 (use (match_operand 5 "" ""))] ; flag: 1 if loop entered at top, else 0 14921 "" 14922 " 14923{ 14924 /* Only use this on innermost loops. */ 14925 if (INTVAL (operands[3]) > 1) 14926 FAIL; 14927 if (TARGET_64BIT) 14928 { 14929 if (GET_MODE (operands[0]) != DImode) 14930 FAIL; 14931 emit_jump_insn (gen_ctrdi (operands[0], operands[4])); 14932 } 14933 else 14934 { 14935 if (GET_MODE (operands[0]) != SImode) 14936 FAIL; 14937 emit_jump_insn (gen_ctrsi (operands[0], operands[4])); 14938 } 14939 DONE; 14940}") 14941 14942(define_expand "ctr<mode>" 14943 [(parallel [(set (pc) 14944 (if_then_else (ne (match_operand:P 0 "register_operand" "") 14945 (const_int 1)) 14946 (label_ref (match_operand 1 "" "")) 14947 (pc))) 14948 (set (match_dup 0) 14949 (plus:P (match_dup 0) 14950 (const_int -1))) 14951 (clobber (match_scratch:CC 2 "")) 14952 (clobber (match_scratch:P 3 ""))])] 14953 "" 14954 "") 14955 14956;; We need to be able to do this for any operand, including MEM, or we 14957;; will cause reload to blow up since we don't allow output reloads on 14958;; JUMP_INSNs. 14959;; For the length attribute to be calculated correctly, the 14960;; label MUST be operand 0. 14961 14962(define_insn "*ctr<mode>_internal1" 14963 [(set (pc) 14964 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r") 14965 (const_int 1)) 14966 (label_ref (match_operand 0 "" "")) 14967 (pc))) 14968 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l") 14969 (plus:P (match_dup 1) 14970 (const_int -1))) 14971 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14972 (clobber (match_scratch:P 4 "=X,X,&r,r"))] 14973 "" 14974 "* 14975{ 14976 if (which_alternative != 0) 14977 return \"#\"; 14978 else if (get_attr_length (insn) == 4) 14979 return \"bdnz %l0\"; 14980 else 14981 return \"bdz $+8\;b %l0\"; 14982}" 14983 [(set_attr "type" "branch") 14984 (set_attr "length" "*,12,16,16")]) 14985 14986(define_insn "*ctr<mode>_internal2" 14987 [(set (pc) 14988 (if_then_else (ne (match_operand:P 1 "register_operand" "c,*r,*r,*r") 14989 (const_int 1)) 14990 (pc) 14991 (label_ref (match_operand 0 "" "")))) 14992 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l") 14993 (plus:P (match_dup 1) 14994 (const_int -1))) 14995 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 14996 (clobber (match_scratch:P 4 "=X,X,&r,r"))] 14997 "" 14998 "* 14999{ 15000 if (which_alternative != 0) 15001 return \"#\"; 15002 else if (get_attr_length (insn) == 4) 15003 return \"bdz %l0\"; 15004 else 15005 return \"bdnz $+8\;b %l0\"; 15006}" 15007 [(set_attr "type" "branch") 15008 (set_attr "length" "*,12,16,16")]) 15009 15010;; Similar but use EQ 15011 15012(define_insn "*ctr<mode>_internal5" 15013 [(set (pc) 15014 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r") 15015 (const_int 1)) 15016 (label_ref (match_operand 0 "" "")) 15017 (pc))) 15018 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l") 15019 (plus:P (match_dup 1) 15020 (const_int -1))) 15021 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 15022 (clobber (match_scratch:P 4 "=X,X,&r,r"))] 15023 "" 15024 "* 15025{ 15026 if (which_alternative != 0) 15027 return \"#\"; 15028 else if (get_attr_length (insn) == 4) 15029 return \"bdz %l0\"; 15030 else 15031 return \"bdnz $+8\;b %l0\"; 15032}" 15033 [(set_attr "type" "branch") 15034 (set_attr "length" "*,12,16,16")]) 15035 15036(define_insn "*ctr<mode>_internal6" 15037 [(set (pc) 15038 (if_then_else (eq (match_operand:P 1 "register_operand" "c,*r,*r,*r") 15039 (const_int 1)) 15040 (pc) 15041 (label_ref (match_operand 0 "" "")))) 15042 (set (match_operand:P 2 "nonimmediate_operand" "=1,*r,m,*c*l") 15043 (plus:P (match_dup 1) 15044 (const_int -1))) 15045 (clobber (match_scratch:CC 3 "=X,&x,&x,&x")) 15046 (clobber (match_scratch:P 4 "=X,X,&r,r"))] 15047 "" 15048 "* 15049{ 15050 if (which_alternative != 0) 15051 return \"#\"; 15052 else if (get_attr_length (insn) == 4) 15053 return \"bdnz %l0\"; 15054 else 15055 return \"bdz $+8\;b %l0\"; 15056}" 15057 [(set_attr "type" "branch") 15058 (set_attr "length" "*,12,16,16")]) 15059 15060;; Now the splitters if we could not allocate the CTR register 15061 15062(define_split 15063 [(set (pc) 15064 (if_then_else (match_operator 2 "comparison_operator" 15065 [(match_operand:P 1 "gpc_reg_operand" "") 15066 (const_int 1)]) 15067 (match_operand 5 "" "") 15068 (match_operand 6 "" ""))) 15069 (set (match_operand:P 0 "gpc_reg_operand" "") 15070 (plus:P (match_dup 1) (const_int -1))) 15071 (clobber (match_scratch:CC 3 "")) 15072 (clobber (match_scratch:P 4 ""))] 15073 "reload_completed" 15074 [(parallel [(set (match_dup 3) 15075 (compare:CC (plus:P (match_dup 1) 15076 (const_int -1)) 15077 (const_int 0))) 15078 (set (match_dup 0) 15079 (plus:P (match_dup 1) 15080 (const_int -1)))]) 15081 (set (pc) (if_then_else (match_dup 7) 15082 (match_dup 5) 15083 (match_dup 6)))] 15084 " 15085{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, 15086 operands[3], const0_rtx); }") 15087 15088(define_split 15089 [(set (pc) 15090 (if_then_else (match_operator 2 "comparison_operator" 15091 [(match_operand:P 1 "gpc_reg_operand" "") 15092 (const_int 1)]) 15093 (match_operand 5 "" "") 15094 (match_operand 6 "" ""))) 15095 (set (match_operand:P 0 "nonimmediate_operand" "") 15096 (plus:P (match_dup 1) (const_int -1))) 15097 (clobber (match_scratch:CC 3 "")) 15098 (clobber (match_scratch:P 4 ""))] 15099 "reload_completed && ! gpc_reg_operand (operands[0], SImode)" 15100 [(parallel [(set (match_dup 3) 15101 (compare:CC (plus:P (match_dup 1) 15102 (const_int -1)) 15103 (const_int 0))) 15104 (set (match_dup 4) 15105 (plus:P (match_dup 1) 15106 (const_int -1)))]) 15107 (set (match_dup 0) 15108 (match_dup 4)) 15109 (set (pc) (if_then_else (match_dup 7) 15110 (match_dup 5) 15111 (match_dup 6)))] 15112 " 15113{ operands[7] = gen_rtx_fmt_ee (GET_CODE (operands[2]), VOIDmode, 15114 operands[3], const0_rtx); }") 15115 15116(define_insn "trap" 15117 [(trap_if (const_int 1) (const_int 0))] 15118 "" 15119 "trap" 15120 [(set_attr "type" "trap")]) 15121 15122(define_expand "ctrap<mode>4" 15123 [(trap_if (match_operator 0 "ordered_comparison_operator" 15124 [(match_operand:GPR 1 "register_operand") 15125 (match_operand:GPR 2 "reg_or_short_operand")]) 15126 (match_operand 3 "zero_constant" ""))] 15127 "" 15128 "") 15129 15130(define_insn "" 15131 [(trap_if (match_operator 0 "ordered_comparison_operator" 15132 [(match_operand:GPR 1 "register_operand" "r") 15133 (match_operand:GPR 2 "reg_or_short_operand" "rI")]) 15134 (const_int 0))] 15135 "" 15136 "t<wd>%V0%I2 %1,%2" 15137 [(set_attr "type" "trap")]) 15138 15139;; Insns related to generating the function prologue and epilogue. 15140 15141(define_expand "prologue" 15142 [(use (const_int 0))] 15143 "" 15144{ 15145 rs6000_emit_prologue (); 15146 if (!TARGET_SCHED_PROLOG) 15147 emit_insn (gen_blockage ()); 15148 DONE; 15149}) 15150 15151(define_insn "*movesi_from_cr_one" 15152 [(match_parallel 0 "mfcr_operation" 15153 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 15154 (unspec:SI [(match_operand:CC 2 "cc_reg_operand" "y") 15155 (match_operand 3 "immediate_operand" "n")] 15156 UNSPEC_MOVESI_FROM_CR))])] 15157 "TARGET_MFCRF" 15158 "* 15159{ 15160 int mask = 0; 15161 int i; 15162 for (i = 0; i < XVECLEN (operands[0], 0); i++) 15163 { 15164 mask = INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); 15165 operands[4] = GEN_INT (mask); 15166 output_asm_insn (\"mfcr %1,%4\", operands); 15167 } 15168 return \"\"; 15169}" 15170 [(set_attr "type" "mfcrf")]) 15171 15172(define_insn "movesi_from_cr" 15173 [(set (match_operand:SI 0 "gpc_reg_operand" "=r") 15174 (unspec:SI [(reg:CC CR0_REGNO) (reg:CC CR1_REGNO) 15175 (reg:CC CR2_REGNO) (reg:CC CR3_REGNO) 15176 (reg:CC CR4_REGNO) (reg:CC CR5_REGNO) 15177 (reg:CC CR6_REGNO) (reg:CC CR7_REGNO)] 15178 UNSPEC_MOVESI_FROM_CR))] 15179 "" 15180 "mfcr %0" 15181 [(set_attr "type" "mfcr")]) 15182 15183(define_insn "*crsave" 15184 [(match_parallel 0 "crsave_operation" 15185 [(set (match_operand:SI 1 "memory_operand" "=m") 15186 (match_operand:SI 2 "gpc_reg_operand" "r"))])] 15187 "" 15188 "stw %2,%1" 15189 [(set_attr "type" "store")]) 15190 15191(define_insn "*stmw" 15192 [(match_parallel 0 "stmw_operation" 15193 [(set (match_operand:SI 1 "memory_operand" "=m") 15194 (match_operand:SI 2 "gpc_reg_operand" "r"))])] 15195 "TARGET_MULTIPLE" 15196 "stmw %2,%1" 15197 [(set_attr "type" "store_ux")]) 15198 15199; The following comment applies to: 15200; save_gpregs_* 15201; save_fpregs_* 15202; restore_gpregs* 15203; return_and_restore_gpregs* 15204; return_and_restore_fpregs* 15205; return_and_restore_fpregs_aix* 15206; 15207; The out-of-line save / restore functions expects one input argument. 15208; Since those are not standard call_insn's, we must avoid using 15209; MATCH_OPERAND for that argument. That way the register rename 15210; optimization will not try to rename this register. 15211; Each pattern is repeated for each possible register number used in 15212; various ABIs (r11, r1, and for some functions r12) 15213 15214(define_insn "*save_gpregs_<mode>_r11" 15215 [(match_parallel 0 "any_parallel_operand" 15216 [(clobber (reg:P 65)) 15217 (use (match_operand:P 1 "symbol_ref_operand" "s")) 15218 (use (reg:P 11)) 15219 (set (match_operand:P 2 "memory_operand" "=m") 15220 (match_operand:P 3 "gpc_reg_operand" "r"))])] 15221 "" 15222 "bl %1" 15223 [(set_attr "type" "branch") 15224 (set_attr "length" "4")]) 15225 15226(define_insn "*save_gpregs_<mode>_r12" 15227 [(match_parallel 0 "any_parallel_operand" 15228 [(clobber (reg:P 65)) 15229 (use (match_operand:P 1 "symbol_ref_operand" "s")) 15230 (use (reg:P 12)) 15231 (set (match_operand:P 2 "memory_operand" "=m") 15232 (match_operand:P 3 "gpc_reg_operand" "r"))])] 15233 "" 15234 "bl %1" 15235 [(set_attr "type" "branch") 15236 (set_attr "length" "4")]) 15237 15238(define_insn "*save_gpregs_<mode>_r1" 15239 [(match_parallel 0 "any_parallel_operand" 15240 [(clobber (reg:P 65)) 15241 (use (match_operand:P 1 "symbol_ref_operand" "s")) 15242 (use (reg:P 1)) 15243 (set (match_operand:P 2 "memory_operand" "=m") 15244 (match_operand:P 3 "gpc_reg_operand" "r"))])] 15245 "" 15246 "bl %1" 15247 [(set_attr "type" "branch") 15248 (set_attr "length" "4")]) 15249 15250(define_insn "*save_fpregs_<mode>_r11" 15251 [(match_parallel 0 "any_parallel_operand" 15252 [(clobber (reg:P 65)) 15253 (use (match_operand:P 1 "symbol_ref_operand" "s")) 15254 (use (reg:P 11)) 15255 (set (match_operand:DF 2 "memory_operand" "=m") 15256 (match_operand:DF 3 "gpc_reg_operand" "d"))])] 15257 "" 15258 "bl %1" 15259 [(set_attr "type" "branch") 15260 (set_attr "length" "4")]) 15261 15262(define_insn "*save_fpregs_<mode>_r12" 15263 [(match_parallel 0 "any_parallel_operand" 15264 [(clobber (reg:P 65)) 15265 (use (match_operand:P 1 "symbol_ref_operand" "s")) 15266 (use (reg:P 12)) 15267 (set (match_operand:DF 2 "memory_operand" "=m") 15268 (match_operand:DF 3 "gpc_reg_operand" "d"))])] 15269 "" 15270 "bl %1" 15271 [(set_attr "type" "branch") 15272 (set_attr "length" "4")]) 15273 15274(define_insn "*save_fpregs_<mode>_r1" 15275 [(match_parallel 0 "any_parallel_operand" 15276 [(clobber (reg:P 65)) 15277 (use (match_operand:P 1 "symbol_ref_operand" "s")) 15278 (use (reg:P 1)) 15279 (set (match_operand:DF 2 "memory_operand" "=m") 15280 (match_operand:DF 3 "gpc_reg_operand" "d"))])] 15281 "" 15282 "bl %1" 15283 [(set_attr "type" "branch") 15284 (set_attr "length" "4")]) 15285 15286; This is to explain that changes to the stack pointer should 15287; not be moved over loads from or stores to stack memory. 15288(define_insn "stack_tie" 15289 [(match_parallel 0 "tie_operand" 15290 [(set (mem:BLK (reg 1)) (const_int 0))])] 15291 "" 15292 "" 15293 [(set_attr "length" "0")]) 15294 15295(define_expand "epilogue" 15296 [(use (const_int 0))] 15297 "" 15298{ 15299 if (!TARGET_SCHED_PROLOG) 15300 emit_insn (gen_blockage ()); 15301 rs6000_emit_epilogue (FALSE); 15302 DONE; 15303}) 15304 15305; On some processors, doing the mtcrf one CC register at a time is 15306; faster (like on the 604e). On others, doing them all at once is 15307; faster; for instance, on the 601 and 750. 15308 15309(define_expand "movsi_to_cr_one" 15310 [(set (match_operand:CC 0 "cc_reg_operand" "") 15311 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "") 15312 (match_dup 2)] UNSPEC_MOVESI_TO_CR))] 15313 "" 15314 "operands[2] = GEN_INT (1 << (75 - REGNO (operands[0])));") 15315 15316(define_insn "*movsi_to_cr" 15317 [(match_parallel 0 "mtcrf_operation" 15318 [(set (match_operand:CC 1 "cc_reg_operand" "=y") 15319 (unspec:CC [(match_operand:SI 2 "gpc_reg_operand" "r") 15320 (match_operand 3 "immediate_operand" "n")] 15321 UNSPEC_MOVESI_TO_CR))])] 15322 "" 15323 "* 15324{ 15325 int mask = 0; 15326 int i; 15327 for (i = 0; i < XVECLEN (operands[0], 0); i++) 15328 mask |= INTVAL (XVECEXP (SET_SRC (XVECEXP (operands[0], 0, i)), 0, 1)); 15329 operands[4] = GEN_INT (mask); 15330 return \"mtcrf %4,%2\"; 15331}" 15332 [(set_attr "type" "mtcr")]) 15333 15334(define_insn "*mtcrfsi" 15335 [(set (match_operand:CC 0 "cc_reg_operand" "=y") 15336 (unspec:CC [(match_operand:SI 1 "gpc_reg_operand" "r") 15337 (match_operand 2 "immediate_operand" "n")] 15338 UNSPEC_MOVESI_TO_CR))] 15339 "GET_CODE (operands[0]) == REG 15340 && CR_REGNO_P (REGNO (operands[0])) 15341 && GET_CODE (operands[2]) == CONST_INT 15342 && INTVAL (operands[2]) == 1 << (75 - REGNO (operands[0]))" 15343 "mtcrf %R0,%1" 15344 [(set_attr "type" "mtcr")]) 15345 15346; The load-multiple instructions have similar properties. 15347; Note that "load_multiple" is a name known to the machine-independent 15348; code that actually corresponds to the PowerPC load-string. 15349 15350(define_insn "*lmw" 15351 [(match_parallel 0 "lmw_operation" 15352 [(set (match_operand:SI 1 "gpc_reg_operand" "=r") 15353 (match_operand:SI 2 "memory_operand" "m"))])] 15354 "TARGET_MULTIPLE" 15355 "lmw %1,%2" 15356 [(set_attr "type" "load_ux") 15357 (set_attr "cell_micro" "always")]) 15358 15359(define_insn "*return_internal_<mode>" 15360 [(simple_return) 15361 (use (match_operand:P 0 "register_operand" "lc"))] 15362 "" 15363 "b%T0" 15364 [(set_attr "type" "jmpreg")]) 15365 15366; FIXME: This would probably be somewhat simpler if the Cygnus sibcall 15367; stuff was in GCC. Oh, and "any_parallel_operand" is a bit flexible... 15368 15369; The following comment applies to: 15370; save_gpregs_* 15371; save_fpregs_* 15372; restore_gpregs* 15373; return_and_restore_gpregs* 15374; return_and_restore_fpregs* 15375; return_and_restore_fpregs_aix* 15376; 15377; The out-of-line save / restore functions expects one input argument. 15378; Since those are not standard call_insn's, we must avoid using 15379; MATCH_OPERAND for that argument. That way the register rename 15380; optimization will not try to rename this register. 15381; Each pattern is repeated for each possible register number used in 15382; various ABIs (r11, r1, and for some functions r12) 15383 15384(define_insn "*restore_gpregs_<mode>_r11" 15385 [(match_parallel 0 "any_parallel_operand" 15386 [(clobber (match_operand:P 1 "register_operand" "=l")) 15387 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15388 (use (reg:P 11)) 15389 (set (match_operand:P 3 "gpc_reg_operand" "=r") 15390 (match_operand:P 4 "memory_operand" "m"))])] 15391 "" 15392 "bl %2" 15393 [(set_attr "type" "branch") 15394 (set_attr "length" "4")]) 15395 15396(define_insn "*restore_gpregs_<mode>_r12" 15397 [(match_parallel 0 "any_parallel_operand" 15398 [(clobber (match_operand:P 1 "register_operand" "=l")) 15399 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15400 (use (reg:P 12)) 15401 (set (match_operand:P 3 "gpc_reg_operand" "=r") 15402 (match_operand:P 4 "memory_operand" "m"))])] 15403 "" 15404 "bl %2" 15405 [(set_attr "type" "branch") 15406 (set_attr "length" "4")]) 15407 15408(define_insn "*restore_gpregs_<mode>_r1" 15409 [(match_parallel 0 "any_parallel_operand" 15410 [(clobber (match_operand:P 1 "register_operand" "=l")) 15411 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15412 (use (reg:P 1)) 15413 (set (match_operand:P 3 "gpc_reg_operand" "=r") 15414 (match_operand:P 4 "memory_operand" "m"))])] 15415 "" 15416 "bl %2" 15417 [(set_attr "type" "branch") 15418 (set_attr "length" "4")]) 15419 15420(define_insn "*return_and_restore_gpregs_<mode>_r11" 15421 [(match_parallel 0 "any_parallel_operand" 15422 [(return) 15423 (clobber (match_operand:P 1 "register_operand" "=l")) 15424 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15425 (use (reg:P 11)) 15426 (set (match_operand:P 3 "gpc_reg_operand" "=r") 15427 (match_operand:P 4 "memory_operand" "m"))])] 15428 "" 15429 "b %2" 15430 [(set_attr "type" "branch") 15431 (set_attr "length" "4")]) 15432 15433(define_insn "*return_and_restore_gpregs_<mode>_r12" 15434 [(match_parallel 0 "any_parallel_operand" 15435 [(return) 15436 (clobber (match_operand:P 1 "register_operand" "=l")) 15437 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15438 (use (reg:P 12)) 15439 (set (match_operand:P 3 "gpc_reg_operand" "=r") 15440 (match_operand:P 4 "memory_operand" "m"))])] 15441 "" 15442 "b %2" 15443 [(set_attr "type" "branch") 15444 (set_attr "length" "4")]) 15445 15446(define_insn "*return_and_restore_gpregs_<mode>_r1" 15447 [(match_parallel 0 "any_parallel_operand" 15448 [(return) 15449 (clobber (match_operand:P 1 "register_operand" "=l")) 15450 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15451 (use (reg:P 1)) 15452 (set (match_operand:P 3 "gpc_reg_operand" "=r") 15453 (match_operand:P 4 "memory_operand" "m"))])] 15454 "" 15455 "b %2" 15456 [(set_attr "type" "branch") 15457 (set_attr "length" "4")]) 15458 15459(define_insn "*return_and_restore_fpregs_<mode>_r11" 15460 [(match_parallel 0 "any_parallel_operand" 15461 [(return) 15462 (clobber (match_operand:P 1 "register_operand" "=l")) 15463 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15464 (use (reg:P 11)) 15465 (set (match_operand:DF 3 "gpc_reg_operand" "=d") 15466 (match_operand:DF 4 "memory_operand" "m"))])] 15467 "" 15468 "b %2" 15469 [(set_attr "type" "branch") 15470 (set_attr "length" "4")]) 15471 15472(define_insn "*return_and_restore_fpregs_<mode>_r12" 15473 [(match_parallel 0 "any_parallel_operand" 15474 [(return) 15475 (clobber (match_operand:P 1 "register_operand" "=l")) 15476 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15477 (use (reg:P 12)) 15478 (set (match_operand:DF 3 "gpc_reg_operand" "=d") 15479 (match_operand:DF 4 "memory_operand" "m"))])] 15480 "" 15481 "b %2" 15482 [(set_attr "type" "branch") 15483 (set_attr "length" "4")]) 15484 15485(define_insn "*return_and_restore_fpregs_<mode>_r1" 15486 [(match_parallel 0 "any_parallel_operand" 15487 [(return) 15488 (clobber (match_operand:P 1 "register_operand" "=l")) 15489 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15490 (use (reg:P 1)) 15491 (set (match_operand:DF 3 "gpc_reg_operand" "=d") 15492 (match_operand:DF 4 "memory_operand" "m"))])] 15493 "" 15494 "b %2" 15495 [(set_attr "type" "branch") 15496 (set_attr "length" "4")]) 15497 15498(define_insn "*return_and_restore_fpregs_aix_<mode>_r11" 15499 [(match_parallel 0 "any_parallel_operand" 15500 [(return) 15501 (use (match_operand:P 1 "register_operand" "l")) 15502 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15503 (use (reg:P 11)) 15504 (set (match_operand:DF 3 "gpc_reg_operand" "=d") 15505 (match_operand:DF 4 "memory_operand" "m"))])] 15506 "" 15507 "b %2" 15508 [(set_attr "type" "branch") 15509 (set_attr "length" "4")]) 15510 15511(define_insn "*return_and_restore_fpregs_aix_<mode>_r1" 15512 [(match_parallel 0 "any_parallel_operand" 15513 [(return) 15514 (use (match_operand:P 1 "register_operand" "l")) 15515 (use (match_operand:P 2 "symbol_ref_operand" "s")) 15516 (use (reg:P 1)) 15517 (set (match_operand:DF 3 "gpc_reg_operand" "=d") 15518 (match_operand:DF 4 "memory_operand" "m"))])] 15519 "" 15520 "b %2" 15521 [(set_attr "type" "branch") 15522 (set_attr "length" "4")]) 15523 15524; This is used in compiling the unwind routines. 15525(define_expand "eh_return" 15526 [(use (match_operand 0 "general_operand" ""))] 15527 "" 15528 " 15529{ 15530 if (TARGET_32BIT) 15531 emit_insn (gen_eh_set_lr_si (operands[0])); 15532 else 15533 emit_insn (gen_eh_set_lr_di (operands[0])); 15534 DONE; 15535}") 15536 15537; We can't expand this before we know where the link register is stored. 15538(define_insn "eh_set_lr_<mode>" 15539 [(unspec_volatile [(match_operand:P 0 "register_operand" "r")] 15540 UNSPECV_EH_RR) 15541 (clobber (match_scratch:P 1 "=&b"))] 15542 "" 15543 "#") 15544 15545(define_split 15546 [(unspec_volatile [(match_operand 0 "register_operand" "")] UNSPECV_EH_RR) 15547 (clobber (match_scratch 1 ""))] 15548 "reload_completed" 15549 [(const_int 0)] 15550 " 15551{ 15552 rs6000_emit_eh_reg_restore (operands[0], operands[1]); 15553 DONE; 15554}") 15555 15556(define_insn "prefetch" 15557 [(prefetch (match_operand 0 "indexed_or_indirect_address" "a") 15558 (match_operand:SI 1 "const_int_operand" "n") 15559 (match_operand:SI 2 "const_int_operand" "n"))] 15560 "" 15561 "* 15562{ 15563 if (GET_CODE (operands[0]) == REG) 15564 return INTVAL (operands[1]) ? \"dcbtst 0,%0\" : \"dcbt 0,%0\"; 15565 return INTVAL (operands[1]) ? \"dcbtst %a0\" : \"dcbt %a0\"; 15566}" 15567 [(set_attr "type" "load")]) 15568 15569(define_insn "bpermd_<mode>" 15570 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 15571 (unspec:P [(match_operand:P 1 "gpc_reg_operand" "r") 15572 (match_operand:P 2 "gpc_reg_operand" "r")] UNSPEC_BPERM))] 15573 "TARGET_POPCNTD" 15574 "bpermd %0,%1,%2" 15575 [(set_attr "type" "popcnt")]) 15576 15577 15578;; Builtin fma support. Handle 15579;; Note that the conditions for expansion are in the FMA_F iterator. 15580 15581(define_expand "fma<mode>4" 15582 [(set (match_operand:FMA_F 0 "register_operand" "") 15583 (fma:FMA_F 15584 (match_operand:FMA_F 1 "register_operand" "") 15585 (match_operand:FMA_F 2 "register_operand" "") 15586 (match_operand:FMA_F 3 "register_operand" "")))] 15587 "" 15588 "") 15589 15590(define_insn "*fma<mode>4_fpr" 15591 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>") 15592 (fma:SFDF 15593 (match_operand:SFDF 1 "gpc_reg_operand" "%<Ff>,<Fv>,<Fv>") 15594 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0") 15595 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))] 15596 "TARGET_<MODE>_FPR" 15597 "@ 15598 fmadd<Ftrad> %0,%1,%2,%3 15599 xsmadda<Fvsx> %x0,%x1,%x2 15600 xsmaddm<Fvsx> %x0,%x1,%x3" 15601 [(set_attr "type" "fp") 15602 (set_attr "fp_type" "fp_maddsub_<Fs>")]) 15603 15604; Altivec only has fma and nfms. 15605(define_expand "fms<mode>4" 15606 [(set (match_operand:FMA_F 0 "register_operand" "") 15607 (fma:FMA_F 15608 (match_operand:FMA_F 1 "register_operand" "") 15609 (match_operand:FMA_F 2 "register_operand" "") 15610 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" ""))))] 15611 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" 15612 "") 15613 15614(define_insn "*fms<mode>4_fpr" 15615 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>") 15616 (fma:SFDF 15617 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>") 15618 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0") 15619 (neg:SFDF (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))] 15620 "TARGET_<MODE>_FPR" 15621 "@ 15622 fmsub<Ftrad> %0,%1,%2,%3 15623 xsmsuba<Fvsx> %x0,%x1,%x2 15624 xsmsubm<Fvsx> %x0,%x1,%x3" 15625 [(set_attr "type" "fp") 15626 (set_attr "fp_type" "fp_maddsub_<Fs>")]) 15627 15628;; If signed zeros are ignored, -(a * b - c) = -a * b + c. 15629(define_expand "fnma<mode>4" 15630 [(set (match_operand:FMA_F 0 "register_operand" "") 15631 (neg:FMA_F 15632 (fma:FMA_F 15633 (match_operand:FMA_F 1 "register_operand" "") 15634 (match_operand:FMA_F 2 "register_operand" "") 15635 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))] 15636 "!HONOR_SIGNED_ZEROS (<MODE>mode)" 15637 "") 15638 15639;; If signed zeros are ignored, -(a * b + c) = -a * b - c. 15640(define_expand "fnms<mode>4" 15641 [(set (match_operand:FMA_F 0 "register_operand" "") 15642 (neg:FMA_F 15643 (fma:FMA_F 15644 (match_operand:FMA_F 1 "register_operand" "") 15645 (match_operand:FMA_F 2 "register_operand" "") 15646 (match_operand:FMA_F 3 "register_operand" ""))))] 15647 "!HONOR_SIGNED_ZEROS (<MODE>mode) && !VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" 15648 "") 15649 15650; Not an official optab name, but used from builtins. 15651(define_expand "nfma<mode>4" 15652 [(set (match_operand:FMA_F 0 "register_operand" "") 15653 (neg:FMA_F 15654 (fma:FMA_F 15655 (match_operand:FMA_F 1 "register_operand" "") 15656 (match_operand:FMA_F 2 "register_operand" "") 15657 (match_operand:FMA_F 3 "register_operand" ""))))] 15658 "!VECTOR_UNIT_ALTIVEC_P (<MODE>mode)" 15659 "") 15660 15661(define_insn "*nfma<mode>4_fpr" 15662 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>") 15663 (neg:SFDF 15664 (fma:SFDF 15665 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>") 15666 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0") 15667 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>"))))] 15668 "TARGET_<MODE>_FPR" 15669 "@ 15670 fnmadd<Ftrad> %0,%1,%2,%3 15671 xsnmadda<Fvsx> %x0,%x1,%x2 15672 xsnmaddm<Fvsx> %x0,%x1,%x3" 15673 [(set_attr "type" "fp") 15674 (set_attr "fp_type" "fp_maddsub_<Fs>")]) 15675 15676; Not an official optab name, but used from builtins. 15677(define_expand "nfms<mode>4" 15678 [(set (match_operand:FMA_F 0 "register_operand" "") 15679 (neg:FMA_F 15680 (fma:FMA_F 15681 (match_operand:FMA_F 1 "register_operand" "") 15682 (match_operand:FMA_F 2 "register_operand" "") 15683 (neg:FMA_F (match_operand:FMA_F 3 "register_operand" "")))))] 15684 "" 15685 "") 15686 15687(define_insn "*nfmssf4_fpr" 15688 [(set (match_operand:SFDF 0 "gpc_reg_operand" "=<Ff>,<Fv>,<Fv>") 15689 (neg:SFDF 15690 (fma:SFDF 15691 (match_operand:SFDF 1 "gpc_reg_operand" "<Ff>,<Fv>,<Fv>") 15692 (match_operand:SFDF 2 "gpc_reg_operand" "<Ff>,<Fv>,0") 15693 (neg:SFDF 15694 (match_operand:SFDF 3 "gpc_reg_operand" "<Ff>,0,<Fv>")))))] 15695 "TARGET_<MODE>_FPR" 15696 "@ 15697 fnmsub<Ftrad> %0,%1,%2,%3 15698 xsnmsuba<Fvsx> %x0,%x1,%x2 15699 xsnmsubm<Fvsx> %x0,%x1,%x3" 15700 [(set_attr "type" "fp") 15701 (set_attr "fp_type" "fp_maddsub_<Fs>")]) 15702 15703 15704(define_expand "rs6000_get_timebase" 15705 [(use (match_operand:DI 0 "gpc_reg_operand" ""))] 15706 "" 15707{ 15708 if (TARGET_POWERPC64) 15709 emit_insn (gen_rs6000_mftb_di (operands[0])); 15710 else 15711 emit_insn (gen_rs6000_get_timebase_ppc32 (operands[0])); 15712 DONE; 15713}) 15714 15715(define_insn "rs6000_get_timebase_ppc32" 15716 [(set (match_operand:DI 0 "gpc_reg_operand" "=r") 15717 (unspec_volatile:DI [(const_int 0)] UNSPECV_MFTB)) 15718 (clobber (match_scratch:SI 1 "=r")) 15719 (clobber (match_scratch:CC 2 "=y"))] 15720 "!TARGET_POWERPC64" 15721{ 15722 if (WORDS_BIG_ENDIAN) 15723 if (TARGET_MFCRF) 15724 { 15725 return "mfspr %0,269\;" 15726 "mfspr %L0,268\;" 15727 "mfspr %1,269\;" 15728 "cmpw %2,%0,%1\;" 15729 "bne- %2,$-16"; 15730 } 15731 else 15732 { 15733 return "mftbu %0\;" 15734 "mftb %L0\;" 15735 "mftbu %1\;" 15736 "cmpw %2,%0,%1\;" 15737 "bne- %2,$-16"; 15738 } 15739 else 15740 if (TARGET_MFCRF) 15741 { 15742 return "mfspr %L0,269\;" 15743 "mfspr %0,268\;" 15744 "mfspr %1,269\;" 15745 "cmpw %2,%L0,%1\;" 15746 "bne- %2,$-16"; 15747 } 15748 else 15749 { 15750 return "mftbu %L0\;" 15751 "mftb %0\;" 15752 "mftbu %1\;" 15753 "cmpw %2,%L0,%1\;" 15754 "bne- %2,$-16"; 15755 } 15756}) 15757 15758(define_insn "rs6000_mftb_<mode>" 15759 [(set (match_operand:P 0 "gpc_reg_operand" "=r") 15760 (unspec_volatile:P [(const_int 0)] UNSPECV_MFTB))] 15761 "" 15762{ 15763 if (TARGET_MFCRF) 15764 return "mfspr %0,268"; 15765 else 15766 return "mftb %0"; 15767}) 15768 15769 15770;; Power8 fusion support for fusing an addis instruction with a D-form load of 15771;; a GPR. The addis instruction must be adjacent to the load, and use the same 15772;; register that is being loaded. The fused ops must be physically adjacent. 15773 15774;; Find cases where the addis that feeds into a load instruction is either used 15775;; once or is the same as the target register, and replace it with the fusion 15776;; insn 15777 15778(define_peephole2 15779 [(set (match_operand:P 0 "base_reg_operand" "") 15780 (match_operand:P 1 "fusion_gpr_addis" "")) 15781 (set (match_operand:INT1 2 "base_reg_operand" "") 15782 (match_operand:INT1 3 "fusion_gpr_mem_load" ""))] 15783 "TARGET_P8_FUSION 15784 && fusion_gpr_load_p (operands[0], operands[1], operands[2], 15785 operands[3])" 15786 [(const_int 0)] 15787{ 15788 expand_fusion_gpr_load (operands); 15789 DONE; 15790}) 15791 15792;; Fusion insn, created by the define_peephole2 above (and eventually by 15793;; reload) 15794 15795(define_insn "fusion_gpr_load_<mode>" 15796 [(set (match_operand:INT1 0 "base_reg_operand" "=&b") 15797 (unspec:INT1 [(match_operand:INT1 1 "fusion_gpr_mem_combo" "")] 15798 UNSPEC_FUSION_GPR))] 15799 "TARGET_P8_FUSION" 15800{ 15801 return emit_fusion_gpr_load (operands[0], operands[1]); 15802} 15803 [(set_attr "type" "load") 15804 (set_attr "length" "8")]) 15805 15806 15807;; Miscellaneous ISA 2.06 (power7) instructions 15808(define_insn "addg6s" 15809 [(set (match_operand:SI 0 "register_operand" "=r") 15810 (unspec:SI [(match_operand:SI 1 "register_operand" "r") 15811 (match_operand:SI 2 "register_operand" "r")] 15812 UNSPEC_ADDG6S))] 15813 "TARGET_POPCNTD" 15814 "addg6s %0,%1,%2" 15815 [(set_attr "type" "integer") 15816 (set_attr "length" "4")]) 15817 15818(define_insn "cdtbcd" 15819 [(set (match_operand:SI 0 "register_operand" "=r") 15820 (unspec:SI [(match_operand:SI 1 "register_operand" "r")] 15821 UNSPEC_CDTBCD))] 15822 "TARGET_POPCNTD" 15823 "cdtbcd %0,%1" 15824 [(set_attr "type" "integer") 15825 (set_attr "length" "4")]) 15826 15827(define_insn "cbcdtd" 15828 [(set (match_operand:SI 0 "register_operand" "=r") 15829 (unspec:SI [(match_operand:SI 1 "register_operand" "r")] 15830 UNSPEC_CBCDTD))] 15831 "TARGET_POPCNTD" 15832 "cbcdtd %0,%1" 15833 [(set_attr "type" "integer") 15834 (set_attr "length" "4")]) 15835 15836(define_int_iterator UNSPEC_DIV_EXTEND [UNSPEC_DIVE 15837 UNSPEC_DIVEO 15838 UNSPEC_DIVEU 15839 UNSPEC_DIVEUO]) 15840 15841(define_int_attr div_extend [(UNSPEC_DIVE "e") 15842 (UNSPEC_DIVEO "eo") 15843 (UNSPEC_DIVEU "eu") 15844 (UNSPEC_DIVEUO "euo")]) 15845 15846(define_insn "div<div_extend>_<mode>" 15847 [(set (match_operand:GPR 0 "register_operand" "=r") 15848 (unspec:GPR [(match_operand:GPR 1 "register_operand" "r") 15849 (match_operand:GPR 2 "register_operand" "r")] 15850 UNSPEC_DIV_EXTEND))] 15851 "TARGET_POPCNTD" 15852 "div<wd><div_extend> %0,%1,%2" 15853 [(set_attr "type" "<idiv_ldiv>")]) 15854 15855 15856;; Pack/unpack 128-bit floating point types that take 2 scalar registers 15857 15858; Type of the 64-bit part when packing/unpacking 128-bit floating point types 15859(define_mode_attr FP128_64 [(TF "DF") (TD "DI")]) 15860 15861(define_expand "unpack<mode>" 15862 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "") 15863 (unspec:<FP128_64> 15864 [(match_operand:FMOVE128 1 "register_operand" "") 15865 (match_operand:QI 2 "const_0_to_1_operand" "")] 15866 UNSPEC_UNPACK_128BIT))] 15867 "" 15868 "") 15869 15870(define_insn_and_split "unpack<mode>_dm" 15871 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m,d,r,m") 15872 (unspec:<FP128_64> 15873 [(match_operand:FMOVE128 1 "register_operand" "d,d,r,d,r") 15874 (match_operand:QI 2 "const_0_to_1_operand" "i,i,i,i,i")] 15875 UNSPEC_UNPACK_128BIT))] 15876 "TARGET_POWERPC64 && TARGET_DIRECT_MOVE" 15877 "#" 15878 "&& reload_completed" 15879 [(set (match_dup 0) (match_dup 3))] 15880{ 15881 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]); 15882 15883 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno) 15884 { 15885 emit_note (NOTE_INSN_DELETED); 15886 DONE; 15887 } 15888 15889 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno); 15890} 15891 [(set_attr "type" "fp,fpstore,mffgpr,mftgpr,store") 15892 (set_attr "length" "4")]) 15893 15894(define_insn_and_split "unpack<mode>_nodm" 15895 [(set (match_operand:<FP128_64> 0 "nonimmediate_operand" "=d,m") 15896 (unspec:<FP128_64> 15897 [(match_operand:FMOVE128 1 "register_operand" "d,d") 15898 (match_operand:QI 2 "const_0_to_1_operand" "i,i")] 15899 UNSPEC_UNPACK_128BIT))] 15900 "!TARGET_POWERPC64 || !TARGET_DIRECT_MOVE" 15901 "#" 15902 "&& reload_completed" 15903 [(set (match_dup 0) (match_dup 3))] 15904{ 15905 unsigned fp_regno = REGNO (operands[1]) + UINTVAL (operands[2]); 15906 15907 if (REG_P (operands[0]) && REGNO (operands[0]) == fp_regno) 15908 { 15909 emit_note (NOTE_INSN_DELETED); 15910 DONE; 15911 } 15912 15913 operands[3] = gen_rtx_REG (<FP128_64>mode, fp_regno); 15914} 15915 [(set_attr "type" "fp,fpstore") 15916 (set_attr "length" "4")]) 15917 15918(define_insn_and_split "pack<mode>" 15919 [(set (match_operand:FMOVE128 0 "register_operand" "=d,&d") 15920 (unspec:FMOVE128 15921 [(match_operand:<FP128_64> 1 "register_operand" "0,d") 15922 (match_operand:<FP128_64> 2 "register_operand" "d,d")] 15923 UNSPEC_PACK_128BIT))] 15924 "" 15925 "@ 15926 fmr %L0,%2 15927 #" 15928 "&& reload_completed && REGNO (operands[0]) != REGNO (operands[1])" 15929 [(set (match_dup 3) (match_dup 1)) 15930 (set (match_dup 4) (match_dup 2))] 15931{ 15932 unsigned dest_hi = REGNO (operands[0]); 15933 unsigned dest_lo = dest_hi + 1; 15934 15935 gcc_assert (!IN_RANGE (REGNO (operands[1]), dest_hi, dest_lo)); 15936 gcc_assert (!IN_RANGE (REGNO (operands[2]), dest_hi, dest_lo)); 15937 15938 operands[3] = gen_rtx_REG (<FP128_64>mode, dest_hi); 15939 operands[4] = gen_rtx_REG (<FP128_64>mode, dest_lo); 15940} 15941 [(set_attr "type" "fp,fp") 15942 (set_attr "length" "4,8")]) 15943 15944(define_insn "unpackv1ti" 15945 [(set (match_operand:DI 0 "register_operand" "=d,d") 15946 (unspec:DI [(match_operand:V1TI 1 "register_operand" "0,wa") 15947 (match_operand:QI 2 "const_0_to_1_operand" "O,i")] 15948 UNSPEC_UNPACK_128BIT))] 15949 "TARGET_VSX" 15950{ 15951 if (REGNO (operands[0]) == REGNO (operands[1]) && INTVAL (operands[2]) == 0) 15952 return ASM_COMMENT_START " xxpermdi to same register"; 15953 15954 operands[3] = GEN_INT (INTVAL (operands[2]) == 0 ? 0 : 3); 15955 return "xxpermdi %x0,%x1,%x1,%3"; 15956} 15957 [(set_attr "type" "vecperm") 15958 (set_attr "length" "4")]) 15959 15960(define_insn "packv1ti" 15961 [(set (match_operand:V1TI 0 "register_operand" "=wa") 15962 (unspec:V1TI 15963 [(match_operand:DI 1 "register_operand" "d") 15964 (match_operand:DI 2 "register_operand" "d")] 15965 UNSPEC_PACK_128BIT))] 15966 "TARGET_VSX" 15967 "xxpermdi %x0,%x1,%x2,0" 15968 [(set_attr "type" "vecperm") 15969 (set_attr "length" "4")]) 15970 15971 15972 15973(include "sync.md") 15974(include "vector.md") 15975(include "vsx.md") 15976(include "altivec.md") 15977(include "spe.md") 15978(include "dfp.md") 15979(include "paired.md") 15980(include "crypto.md") 15981(include "htm.md") 15982