1 /* Definitions of target machine for GNU compiler, for IBM RS/6000. 2 Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 4 2010, 2011 5 Free Software Foundation, Inc. 6 Contributed by Richard Kenner (kenner@vlsi1.ultra.nyu.edu) 7 8 This file is part of GCC. 9 10 GCC is free software; you can redistribute it and/or modify it 11 under the terms of the GNU General Public License as published 12 by the Free Software Foundation; either version 3, or (at your 13 option) any later version. 14 15 GCC is distributed in the hope that it will be useful, but WITHOUT 16 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 17 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 18 License for more details. 19 20 Under Section 7 of GPL version 3, you are granted additional 21 permissions described in the GCC Runtime Library Exception, version 22 3.1, as published by the Free Software Foundation. 23 24 You should have received a copy of the GNU General Public License and 25 a copy of the GCC Runtime Library Exception along with this program; 26 see the files COPYING3 and COPYING.RUNTIME respectively. If not, see 27 <http://www.gnu.org/licenses/>. */ 28 29 /* Note that some other tm.h files include this one and then override 30 many of the definitions. */ 31 32 /* Definitions for the object file format. These are set at 33 compile-time. */ 34 35 #define OBJECT_XCOFF 1 36 #define OBJECT_ELF 2 37 #define OBJECT_PEF 3 38 #define OBJECT_MACHO 4 39 40 #define TARGET_ELF (TARGET_OBJECT_FORMAT == OBJECT_ELF) 41 #define TARGET_XCOFF (TARGET_OBJECT_FORMAT == OBJECT_XCOFF) 42 #define TARGET_MACOS (TARGET_OBJECT_FORMAT == OBJECT_PEF) 43 #define TARGET_MACHO (TARGET_OBJECT_FORMAT == OBJECT_MACHO) 44 45 #ifndef TARGET_AIX 46 #define TARGET_AIX 0 47 #endif 48 49 /* Control whether function entry points use a "dot" symbol when 50 ABI_AIX. */ 51 #define DOT_SYMBOLS 1 52 53 /* Default string to use for cpu if not specified. */ 54 #ifndef TARGET_CPU_DEFAULT 55 #define TARGET_CPU_DEFAULT ((char *)0) 56 #endif 57 58 /* If configured for PPC405, support PPC405CR Erratum77. */ 59 #ifdef CONFIG_PPC405CR 60 #define PPC405_ERRATUM77 (rs6000_cpu == PROCESSOR_PPC405) 61 #else 62 #define PPC405_ERRATUM77 0 63 #endif 64 65 #ifndef TARGET_PAIRED_FLOAT 66 #define TARGET_PAIRED_FLOAT 0 67 #endif 68 69 #ifdef HAVE_AS_POPCNTB 70 #define ASM_CPU_POWER5_SPEC "-mpower5" 71 #else 72 #define ASM_CPU_POWER5_SPEC "-mpower4" 73 #endif 74 75 #ifdef HAVE_AS_DFP 76 #define ASM_CPU_POWER6_SPEC "-mpower6 -maltivec" 77 #else 78 #define ASM_CPU_POWER6_SPEC "-mpower4 -maltivec" 79 #endif 80 81 #ifdef HAVE_AS_POPCNTD 82 #define ASM_CPU_POWER7_SPEC "-mpower7" 83 #else 84 #define ASM_CPU_POWER7_SPEC "-mpower4 -maltivec" 85 #endif 86 87 #ifdef HAVE_AS_DCI 88 #define ASM_CPU_476_SPEC "-m476" 89 #else 90 #define ASM_CPU_476_SPEC "-mpower4" 91 #endif 92 93 /* Common ASM definitions used by ASM_SPEC among the various targets for 94 handling -mcpu=xxx switches. There is a parallel list in driver-rs6000.c to 95 provide the default assembler options if the user uses -mcpu=native, so if 96 you make changes here, make them also there. */ 97 #define ASM_CPU_SPEC \ 98 "%{!mcpu*: \ 99 %{mpower: %{!mpower2: -mpwr}} \ 100 %{mpower2: -mpwrx} \ 101 %{mpowerpc64*: -mppc64} \ 102 %{!mpowerpc64*: %{mpowerpc*: -mppc}} \ 103 %{mno-power: %{!mpowerpc*: -mcom}} \ 104 %{!mno-power: %{!mpower*: %(asm_default)}}} \ 105 %{mcpu=native: %(asm_cpu_native)} \ 106 %{mcpu=common: -mcom} \ 107 %{mcpu=cell: -mcell} \ 108 %{mcpu=power: -mpwr} \ 109 %{mcpu=power2: -mpwrx} \ 110 %{mcpu=power3: -mppc64} \ 111 %{mcpu=power4: -mpower4} \ 112 %{mcpu=power5: %(asm_cpu_power5)} \ 113 %{mcpu=power5+: %(asm_cpu_power5)} \ 114 %{mcpu=power6: %(asm_cpu_power6) -maltivec} \ 115 %{mcpu=power6x: %(asm_cpu_power6) -maltivec} \ 116 %{mcpu=power7: %(asm_cpu_power7)} \ 117 %{mcpu=a2: -ma2} \ 118 %{mcpu=powerpc: -mppc} \ 119 %{mcpu=rios: -mpwr} \ 120 %{mcpu=rios1: -mpwr} \ 121 %{mcpu=rios2: -mpwrx} \ 122 %{mcpu=rsc: -mpwr} \ 123 %{mcpu=rsc1: -mpwr} \ 124 %{mcpu=rs64a: -mppc64} \ 125 %{mcpu=401: -mppc} \ 126 %{mcpu=403: -m403} \ 127 %{mcpu=405: -m405} \ 128 %{mcpu=405fp: -m405} \ 129 %{mcpu=440: -m440} \ 130 %{mcpu=440fp: -m440} \ 131 %{mcpu=464: -m440} \ 132 %{mcpu=464fp: -m440} \ 133 %{mcpu=476: %(asm_cpu_476)} \ 134 %{mcpu=476fp: %(asm_cpu_476)} \ 135 %{mcpu=505: -mppc} \ 136 %{mcpu=601: -m601} \ 137 %{mcpu=602: -mppc} \ 138 %{mcpu=603: -mppc} \ 139 %{mcpu=603e: -mppc} \ 140 %{mcpu=ec603e: -mppc} \ 141 %{mcpu=604: -mppc} \ 142 %{mcpu=604e: -mppc} \ 143 %{mcpu=620: -mppc64} \ 144 %{mcpu=630: -mppc64} \ 145 %{mcpu=740: -mppc} \ 146 %{mcpu=750: -mppc} \ 147 %{mcpu=G3: -mppc} \ 148 %{mcpu=7400: -mppc -maltivec} \ 149 %{mcpu=7450: -mppc -maltivec} \ 150 %{mcpu=G4: -mppc -maltivec} \ 151 %{mcpu=801: -mppc} \ 152 %{mcpu=821: -mppc} \ 153 %{mcpu=823: -mppc} \ 154 %{mcpu=860: -mppc} \ 155 %{mcpu=970: -mpower4 -maltivec} \ 156 %{mcpu=G5: -mpower4 -maltivec} \ 157 %{mcpu=8540: -me500} \ 158 %{mcpu=8548: -me500} \ 159 %{mcpu=e300c2: -me300} \ 160 %{mcpu=e300c3: -me300} \ 161 %{mcpu=e500mc: -me500mc} \ 162 %{mcpu=e500mc64: -me500mc64} \ 163 %{maltivec: -maltivec} \ 164 -many" 165 166 #define CPP_DEFAULT_SPEC "" 167 168 #define ASM_DEFAULT_SPEC "" 169 170 /* This macro defines names of additional specifications to put in the specs 171 that can be used in various specifications like CC1_SPEC. Its definition 172 is an initializer with a subgrouping for each command option. 173 174 Each subgrouping contains a string constant, that defines the 175 specification name, and a string constant that used by the GCC driver 176 program. 177 178 Do not define this macro if it does not need to do anything. */ 179 180 #define SUBTARGET_EXTRA_SPECS 181 182 #define EXTRA_SPECS \ 183 { "cpp_default", CPP_DEFAULT_SPEC }, \ 184 { "asm_cpu", ASM_CPU_SPEC }, \ 185 { "asm_cpu_native", ASM_CPU_NATIVE_SPEC }, \ 186 { "asm_default", ASM_DEFAULT_SPEC }, \ 187 { "cc1_cpu", CC1_CPU_SPEC }, \ 188 { "asm_cpu_power5", ASM_CPU_POWER5_SPEC }, \ 189 { "asm_cpu_power6", ASM_CPU_POWER6_SPEC }, \ 190 { "asm_cpu_power7", ASM_CPU_POWER7_SPEC }, \ 191 { "asm_cpu_476", ASM_CPU_476_SPEC }, \ 192 SUBTARGET_EXTRA_SPECS 193 194 /* -mcpu=native handling only makes sense with compiler running on 195 an PowerPC chip. If changing this condition, also change 196 the condition in driver-rs6000.c. */ 197 #if defined(__powerpc__) || defined(__POWERPC__) || defined(_AIX) 198 /* In driver-rs6000.c. */ 199 extern const char *host_detect_local_cpu (int argc, const char **argv); 200 #define EXTRA_SPEC_FUNCTIONS \ 201 { "local_cpu_detect", host_detect_local_cpu }, 202 #define HAVE_LOCAL_CPU_DETECT 203 #define ASM_CPU_NATIVE_SPEC "%:local_cpu_detect(asm)" 204 205 #else 206 #define ASM_CPU_NATIVE_SPEC "%(asm_default)" 207 #endif 208 209 #ifndef CC1_CPU_SPEC 210 #ifdef HAVE_LOCAL_CPU_DETECT 211 #define CC1_CPU_SPEC \ 212 "%{mcpu=native:%<mcpu=native %:local_cpu_detect(cpu)} \ 213 %{mtune=native:%<mtune=native %:local_cpu_detect(tune)}" 214 #else 215 #define CC1_CPU_SPEC "" 216 #endif 217 #endif 218 219 /* Architecture type. */ 220 221 /* Define TARGET_MFCRF if the target assembler does not support the 222 optional field operand for mfcr. */ 223 224 #ifndef HAVE_AS_MFCRF 225 #undef TARGET_MFCRF 226 #define TARGET_MFCRF 0 227 #endif 228 229 /* Define TARGET_POPCNTB if the target assembler does not support the 230 popcount byte instruction. */ 231 232 #ifndef HAVE_AS_POPCNTB 233 #undef TARGET_POPCNTB 234 #define TARGET_POPCNTB 0 235 #endif 236 237 /* Define TARGET_FPRND if the target assembler does not support the 238 fp rounding instructions. */ 239 240 #ifndef HAVE_AS_FPRND 241 #undef TARGET_FPRND 242 #define TARGET_FPRND 0 243 #endif 244 245 /* Define TARGET_CMPB if the target assembler does not support the 246 cmpb instruction. */ 247 248 #ifndef HAVE_AS_CMPB 249 #undef TARGET_CMPB 250 #define TARGET_CMPB 0 251 #endif 252 253 /* Define TARGET_MFPGPR if the target assembler does not support the 254 mffpr and mftgpr instructions. */ 255 256 #ifndef HAVE_AS_MFPGPR 257 #undef TARGET_MFPGPR 258 #define TARGET_MFPGPR 0 259 #endif 260 261 /* Define TARGET_DFP if the target assembler does not support decimal 262 floating point instructions. */ 263 #ifndef HAVE_AS_DFP 264 #undef TARGET_DFP 265 #define TARGET_DFP 0 266 #endif 267 268 /* Define TARGET_POPCNTD if the target assembler does not support the 269 popcount word and double word instructions. */ 270 271 #ifndef HAVE_AS_POPCNTD 272 #undef TARGET_POPCNTD 273 #define TARGET_POPCNTD 0 274 #endif 275 276 /* Define TARGET_LWSYNC_INSTRUCTION if the assembler knows about lwsync. If 277 not, generate the lwsync code as an integer constant. */ 278 #ifdef HAVE_AS_LWSYNC 279 #define TARGET_LWSYNC_INSTRUCTION 1 280 #else 281 #define TARGET_LWSYNC_INSTRUCTION 0 282 #endif 283 284 /* Define TARGET_TLS_MARKERS if the target assembler does not support 285 arg markers for __tls_get_addr calls. */ 286 #ifndef HAVE_AS_TLS_MARKERS 287 #undef TARGET_TLS_MARKERS 288 #define TARGET_TLS_MARKERS 0 289 #else 290 #define TARGET_TLS_MARKERS tls_markers 291 #endif 292 293 #ifndef TARGET_SECURE_PLT 294 #define TARGET_SECURE_PLT 0 295 #endif 296 297 #define TARGET_32BIT (! TARGET_64BIT) 298 299 #ifndef HAVE_AS_TLS 300 #define HAVE_AS_TLS 0 301 #endif 302 303 /* Return 1 for a symbol ref for a thread-local storage symbol. */ 304 #define RS6000_SYMBOL_REF_TLS_P(RTX) \ 305 (GET_CODE (RTX) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (RTX) != 0) 306 307 #ifdef IN_LIBGCC2 308 /* For libgcc2 we make sure this is a compile time constant */ 309 #if defined (__64BIT__) || defined (__powerpc64__) || defined (__ppc64__) 310 #undef TARGET_POWERPC64 311 #define TARGET_POWERPC64 1 312 #else 313 #undef TARGET_POWERPC64 314 #define TARGET_POWERPC64 0 315 #endif 316 #else 317 /* The option machinery will define this. */ 318 #endif 319 320 #define TARGET_DEFAULT (MASK_POWER | MASK_MULTIPLE | MASK_STRING) 321 322 /* Processor type. Order must match cpu attribute in MD file. */ 323 enum processor_type 324 { 325 PROCESSOR_RIOS1, 326 PROCESSOR_RIOS2, 327 PROCESSOR_RS64A, 328 PROCESSOR_MPCCORE, 329 PROCESSOR_PPC403, 330 PROCESSOR_PPC405, 331 PROCESSOR_PPC440, 332 PROCESSOR_PPC476, 333 PROCESSOR_PPC601, 334 PROCESSOR_PPC603, 335 PROCESSOR_PPC604, 336 PROCESSOR_PPC604e, 337 PROCESSOR_PPC620, 338 PROCESSOR_PPC630, 339 PROCESSOR_PPC750, 340 PROCESSOR_PPC7400, 341 PROCESSOR_PPC7450, 342 PROCESSOR_PPC8540, 343 PROCESSOR_PPCE300C2, 344 PROCESSOR_PPCE300C3, 345 PROCESSOR_PPCE500MC, 346 PROCESSOR_PPCE500MC64, 347 PROCESSOR_POWER4, 348 PROCESSOR_POWER5, 349 PROCESSOR_POWER6, 350 PROCESSOR_POWER7, 351 PROCESSOR_CELL, 352 PROCESSOR_PPCA2 353 }; 354 355 /* FPU operations supported. 356 Each use of TARGET_SINGLE_FLOAT or TARGET_DOUBLE_FLOAT must 357 also test TARGET_HARD_FLOAT. */ 358 #define TARGET_SINGLE_FLOAT 1 359 #define TARGET_DOUBLE_FLOAT 1 360 #define TARGET_SINGLE_FPU 0 361 #define TARGET_SIMPLE_FPU 0 362 #define TARGET_XILINX_FPU 0 363 364 extern enum processor_type rs6000_cpu; 365 366 /* Recast the processor type to the cpu attribute. */ 367 #define rs6000_cpu_attr ((enum attr_cpu)rs6000_cpu) 368 369 /* Define generic processor types based upon current deployment. */ 370 #define PROCESSOR_COMMON PROCESSOR_PPC601 371 #define PROCESSOR_POWER PROCESSOR_RIOS1 372 #define PROCESSOR_POWERPC PROCESSOR_PPC604 373 #define PROCESSOR_POWERPC64 PROCESSOR_RS64A 374 375 /* Define the default processor. This is overridden by other tm.h files. */ 376 #define PROCESSOR_DEFAULT PROCESSOR_RIOS1 377 #define PROCESSOR_DEFAULT64 PROCESSOR_RS64A 378 379 /* FP processor type. */ 380 enum fpu_type_t 381 { 382 FPU_NONE, /* No FPU */ 383 FPU_SF_LITE, /* Limited Single Precision FPU */ 384 FPU_DF_LITE, /* Limited Double Precision FPU */ 385 FPU_SF_FULL, /* Full Single Precision FPU */ 386 FPU_DF_FULL /* Full Double Single Precision FPU */ 387 }; 388 389 extern enum fpu_type_t fpu_type; 390 391 /* Specify the dialect of assembler to use. New mnemonics is dialect one 392 and the old mnemonics are dialect zero. */ 393 #define ASSEMBLER_DIALECT (TARGET_NEW_MNEMONICS ? 1 : 0) 394 395 /* Types of costly dependences. */ 396 enum rs6000_dependence_cost 397 { 398 max_dep_latency = 1000, 399 no_dep_costly, 400 all_deps_costly, 401 true_store_to_load_dep_costly, 402 store_to_load_dep_costly 403 }; 404 405 /* Types of nop insertion schemes in sched target hook sched_finish. */ 406 enum rs6000_nop_insertion 407 { 408 sched_finish_regroup_exact = 1000, 409 sched_finish_pad_groups, 410 sched_finish_none 411 }; 412 413 /* Dispatch group termination caused by an insn. */ 414 enum group_termination 415 { 416 current_group, 417 previous_group 418 }; 419 420 /* rs6000_select[0] is reserved for the default cpu defined via --with-cpu */ 421 struct rs6000_cpu_select 422 { 423 const char *string; 424 const char *name; 425 int set_tune_p; 426 int set_arch_p; 427 }; 428 429 extern struct rs6000_cpu_select rs6000_select[]; 430 431 /* Debug support */ 432 extern const char *rs6000_debug_name; /* Name for -mdebug-xxxx option */ 433 extern int rs6000_debug_stack; /* debug stack applications */ 434 extern int rs6000_debug_arg; /* debug argument handling */ 435 extern int rs6000_debug_reg; /* debug register handling */ 436 extern int rs6000_debug_addr; /* debug memory addressing */ 437 extern int rs6000_debug_cost; /* debug rtx_costs */ 438 439 #define TARGET_DEBUG_STACK rs6000_debug_stack 440 #define TARGET_DEBUG_ARG rs6000_debug_arg 441 #define TARGET_DEBUG_REG rs6000_debug_reg 442 #define TARGET_DEBUG_ADDR rs6000_debug_addr 443 #define TARGET_DEBUG_COST rs6000_debug_cost 444 445 extern const char *rs6000_traceback_name; /* Type of traceback table. */ 446 447 /* These are separate from target_flags because we've run out of bits 448 there. */ 449 extern int rs6000_long_double_type_size; 450 extern int rs6000_ieeequad; 451 extern int rs6000_altivec_abi; 452 extern int rs6000_spe_abi; 453 extern int rs6000_spe; 454 extern int rs6000_float_gprs; 455 extern int rs6000_alignment_flags; 456 extern const char *rs6000_sched_insert_nops_str; 457 extern enum rs6000_nop_insertion rs6000_sched_insert_nops; 458 extern int rs6000_xilinx_fpu; 459 460 /* Describe which vector unit to use for a given machine mode. */ 461 enum rs6000_vector { 462 VECTOR_NONE, /* Type is not a vector or not supported */ 463 VECTOR_ALTIVEC, /* Use altivec for vector processing */ 464 VECTOR_VSX, /* Use VSX for vector processing */ 465 VECTOR_PAIRED, /* Use paired floating point for vectors */ 466 VECTOR_SPE, /* Use SPE for vector processing */ 467 VECTOR_OTHER /* Some other vector unit */ 468 }; 469 470 extern enum rs6000_vector rs6000_vector_unit[]; 471 472 #define VECTOR_UNIT_NONE_P(MODE) \ 473 (rs6000_vector_unit[(MODE)] == VECTOR_NONE) 474 475 #define VECTOR_UNIT_VSX_P(MODE) \ 476 (rs6000_vector_unit[(MODE)] == VECTOR_VSX) 477 478 #define VECTOR_UNIT_ALTIVEC_P(MODE) \ 479 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC) 480 481 #define VECTOR_UNIT_ALTIVEC_OR_VSX_P(MODE) \ 482 (rs6000_vector_unit[(MODE)] == VECTOR_ALTIVEC \ 483 || rs6000_vector_unit[(MODE)] == VECTOR_VSX) 484 485 /* Describe whether to use VSX loads or Altivec loads. For now, just use the 486 same unit as the vector unit we are using, but we may want to migrate to 487 using VSX style loads even for types handled by altivec. */ 488 extern enum rs6000_vector rs6000_vector_mem[]; 489 490 #define VECTOR_MEM_NONE_P(MODE) \ 491 (rs6000_vector_mem[(MODE)] == VECTOR_NONE) 492 493 #define VECTOR_MEM_VSX_P(MODE) \ 494 (rs6000_vector_mem[(MODE)] == VECTOR_VSX) 495 496 #define VECTOR_MEM_ALTIVEC_P(MODE) \ 497 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC) 498 499 #define VECTOR_MEM_ALTIVEC_OR_VSX_P(MODE) \ 500 (rs6000_vector_mem[(MODE)] == VECTOR_ALTIVEC \ 501 || rs6000_vector_mem[(MODE)] == VECTOR_VSX) 502 503 /* Return the alignment of a given vector type, which is set based on the 504 vector unit use. VSX for instance can load 32 or 64 bit aligned words 505 without problems, while Altivec requires 128-bit aligned vectors. */ 506 extern int rs6000_vector_align[]; 507 508 #define VECTOR_ALIGN(MODE) \ 509 ((rs6000_vector_align[(MODE)] != 0) \ 510 ? rs6000_vector_align[(MODE)] \ 511 : (int)GET_MODE_BITSIZE ((MODE))) 512 513 /* Alignment options for fields in structures for sub-targets following 514 AIX-like ABI. 515 ALIGN_POWER word-aligns FP doubles (default AIX ABI). 516 ALIGN_NATURAL doubleword-aligns FP doubles (align to object size). 517 518 Override the macro definitions when compiling libobjc to avoid undefined 519 reference to rs6000_alignment_flags due to library's use of GCC alignment 520 macros which use the macros below. */ 521 522 #ifndef IN_TARGET_LIBS 523 #define MASK_ALIGN_POWER 0x00000000 524 #define MASK_ALIGN_NATURAL 0x00000001 525 #define TARGET_ALIGN_NATURAL (rs6000_alignment_flags & MASK_ALIGN_NATURAL) 526 #else 527 #define TARGET_ALIGN_NATURAL 0 528 #endif 529 530 #define TARGET_LONG_DOUBLE_128 (rs6000_long_double_type_size == 128) 531 #define TARGET_IEEEQUAD rs6000_ieeequad 532 #define TARGET_ALTIVEC_ABI rs6000_altivec_abi 533 #define TARGET_LDBRX (TARGET_POPCNTD || rs6000_cpu == PROCESSOR_CELL) 534 535 #define TARGET_SPE_ABI 0 536 #define TARGET_SPE 0 537 #define TARGET_E500 0 538 #define TARGET_ISEL64 (TARGET_ISEL && TARGET_POWERPC64) 539 #define TARGET_FPRS 1 540 #define TARGET_E500_SINGLE 0 541 #define TARGET_E500_DOUBLE 0 542 #define CHECK_E500_OPTIONS do { } while (0) 543 544 /* E500 processors only support plain "sync", not lwsync. */ 545 #define TARGET_NO_LWSYNC TARGET_E500 546 547 /* Sometimes certain combinations of command options do not make sense 548 on a particular target machine. You can define a macro 549 `OVERRIDE_OPTIONS' to take account of this. This macro, if 550 defined, is executed once just after all the command options have 551 been parsed. 552 553 Do not use this macro to turn on various extra optimizations for 554 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. 555 556 On the RS/6000 this is used to define the target cpu type. */ 557 558 #define OVERRIDE_OPTIONS rs6000_override_options (TARGET_CPU_DEFAULT) 559 560 /* Define this to change the optimizations performed by default. */ 561 #define OPTIMIZATION_OPTIONS(LEVEL,SIZE) optimization_options(LEVEL,SIZE) 562 563 /* Show we can debug even without a frame pointer. */ 564 #define CAN_DEBUG_WITHOUT_FP 565 566 /* Target pragma. */ 567 #define REGISTER_TARGET_PRAGMAS() do { \ 568 c_register_pragma (0, "longcall", rs6000_pragma_longcall); \ 569 targetm.resolve_overloaded_builtin = altivec_resolve_overloaded_builtin; \ 570 } while (0) 571 572 /* Target #defines. */ 573 #define TARGET_CPU_CPP_BUILTINS() \ 574 rs6000_cpu_cpp_builtins (pfile) 575 576 /* This is used by rs6000_cpu_cpp_builtins to indicate the byte order 577 we're compiling for. Some configurations may need to override it. */ 578 #define RS6000_CPU_CPP_ENDIAN_BUILTINS() \ 579 do \ 580 { \ 581 if (BYTES_BIG_ENDIAN) \ 582 { \ 583 builtin_define ("__BIG_ENDIAN__"); \ 584 builtin_define ("_BIG_ENDIAN"); \ 585 builtin_assert ("machine=bigendian"); \ 586 } \ 587 else \ 588 { \ 589 builtin_define ("__LITTLE_ENDIAN__"); \ 590 builtin_define ("_LITTLE_ENDIAN"); \ 591 builtin_assert ("machine=littleendian"); \ 592 } \ 593 } \ 594 while (0) 595 596 /* Target machine storage layout. */ 597 598 /* Define this macro if it is advisable to hold scalars in registers 599 in a wider mode than that declared by the program. In such cases, 600 the value is constrained to be within the bounds of the declared 601 type, but kept valid in the wider mode. The signedness of the 602 extension may differ from that of the type. */ 603 604 #define PROMOTE_MODE(MODE,UNSIGNEDP,TYPE) \ 605 if (GET_MODE_CLASS (MODE) == MODE_INT \ 606 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 607 (MODE) = TARGET_32BIT ? SImode : DImode; 608 609 /* Define this if most significant bit is lowest numbered 610 in instructions that operate on numbered bit-fields. */ 611 /* That is true on RS/6000. */ 612 #define BITS_BIG_ENDIAN 1 613 614 /* Define this if most significant byte of a word is the lowest numbered. */ 615 /* That is true on RS/6000. */ 616 #define BYTES_BIG_ENDIAN 1 617 618 /* Define this if most significant word of a multiword number is lowest 619 numbered. 620 621 For RS/6000 we can decide arbitrarily since there are no machine 622 instructions for them. Might as well be consistent with bits and bytes. */ 623 #define WORDS_BIG_ENDIAN 1 624 625 #define MAX_BITS_PER_WORD 64 626 627 /* Width of a word, in units (bytes). */ 628 #define UNITS_PER_WORD (! TARGET_POWERPC64 ? 4 : 8) 629 #ifdef IN_LIBGCC2 630 #define MIN_UNITS_PER_WORD UNITS_PER_WORD 631 #else 632 #define MIN_UNITS_PER_WORD 4 633 #endif 634 #define UNITS_PER_FP_WORD 8 635 #define UNITS_PER_ALTIVEC_WORD 16 636 #define UNITS_PER_VSX_WORD 16 637 #define UNITS_PER_SPE_WORD 8 638 #define UNITS_PER_PAIRED_WORD 8 639 640 /* Type used for ptrdiff_t, as a string used in a declaration. */ 641 #define PTRDIFF_TYPE "int" 642 643 /* Type used for size_t, as a string used in a declaration. */ 644 #define SIZE_TYPE "long unsigned int" 645 646 /* Type used for wchar_t, as a string used in a declaration. */ 647 #define WCHAR_TYPE "short unsigned int" 648 649 /* Width of wchar_t in bits. */ 650 #define WCHAR_TYPE_SIZE 16 651 652 /* A C expression for the size in bits of the type `short' on the 653 target machine. If you don't define this, the default is half a 654 word. (If this would be less than one storage unit, it is 655 rounded up to one unit.) */ 656 #define SHORT_TYPE_SIZE 16 657 658 /* A C expression for the size in bits of the type `int' on the 659 target machine. If you don't define this, the default is one 660 word. */ 661 #define INT_TYPE_SIZE 32 662 663 /* A C expression for the size in bits of the type `long' on the 664 target machine. If you don't define this, the default is one 665 word. */ 666 #define LONG_TYPE_SIZE (TARGET_32BIT ? 32 : 64) 667 668 /* A C expression for the size in bits of the type `long long' on the 669 target machine. If you don't define this, the default is two 670 words. */ 671 #define LONG_LONG_TYPE_SIZE 64 672 673 /* A C expression for the size in bits of the type `float' on the 674 target machine. If you don't define this, the default is one 675 word. */ 676 #define FLOAT_TYPE_SIZE 32 677 678 /* A C expression for the size in bits of the type `double' on the 679 target machine. If you don't define this, the default is two 680 words. */ 681 #define DOUBLE_TYPE_SIZE 64 682 683 /* A C expression for the size in bits of the type `long double' on 684 the target machine. If you don't define this, the default is two 685 words. */ 686 #define LONG_DOUBLE_TYPE_SIZE rs6000_long_double_type_size 687 688 /* Define this to set long double type size to use in libgcc2.c, which can 689 not depend on target_flags. */ 690 #ifdef __LONG_DOUBLE_128__ 691 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 128 692 #else 693 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 694 #endif 695 696 /* Work around rs6000_long_double_type_size dependency in ada/targtyps.c. */ 697 #define WIDEST_HARDWARE_FP_SIZE 64 698 699 /* Width in bits of a pointer. 700 See also the macro `Pmode' defined below. */ 701 extern unsigned rs6000_pointer_size; 702 #define POINTER_SIZE rs6000_pointer_size 703 704 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 705 #define PARM_BOUNDARY (TARGET_32BIT ? 32 : 64) 706 707 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 708 #define STACK_BOUNDARY \ 709 ((TARGET_32BIT && !TARGET_ALTIVEC && !TARGET_ALTIVEC_ABI && !TARGET_VSX) \ 710 ? 64 : 128) 711 712 /* Allocation boundary (in *bits*) for the code of a function. */ 713 #define FUNCTION_BOUNDARY 32 714 715 /* No data type wants to be aligned rounder than this. */ 716 #define BIGGEST_ALIGNMENT 128 717 718 /* A C expression to compute the alignment for a variables in the 719 local store. TYPE is the data type, and ALIGN is the alignment 720 that the object would ordinarily have. */ 721 #define LOCAL_ALIGNMENT(TYPE, ALIGN) \ 722 DATA_ALIGNMENT (TYPE, ALIGN) 723 724 /* Alignment of field after `int : 0' in a structure. */ 725 #define EMPTY_FIELD_BOUNDARY 32 726 727 /* Every structure's size must be a multiple of this. */ 728 #define STRUCTURE_SIZE_BOUNDARY 8 729 730 /* Return 1 if a structure or array containing FIELD should be 731 accessed using `BLKMODE'. 732 733 For the SPE, simd types are V2SI, and gcc can be tempted to put the 734 entire thing in a DI and use subregs to access the internals. 735 store_bit_field() will force (subreg:DI (reg:V2SI x))'s to the 736 back-end. Because a single GPR can hold a V2SI, but not a DI, the 737 best thing to do is set structs to BLKmode and avoid Severe Tire 738 Damage. 739 740 On e500 v2, DF and DI modes suffer from the same anomaly. DF can 741 fit into 1, whereas DI still needs two. */ 742 #define MEMBER_TYPE_FORCES_BLK(FIELD, MODE) \ 743 ((TARGET_SPE && TREE_CODE (TREE_TYPE (FIELD)) == VECTOR_TYPE) \ 744 || (TARGET_E500_DOUBLE && (MODE) == DFmode)) 745 746 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 747 #define PCC_BITFIELD_TYPE_MATTERS 1 748 749 /* Make strings word-aligned so strcpy from constants will be faster. 750 Make vector constants quadword aligned. */ 751 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 752 (TREE_CODE (EXP) == STRING_CST \ 753 && (STRICT_ALIGNMENT || !optimize_size) \ 754 && (ALIGN) < BITS_PER_WORD \ 755 ? BITS_PER_WORD \ 756 : (ALIGN)) 757 758 /* Make arrays of chars word-aligned for the same reasons. 759 Align vectors to 128 bits. Align SPE vectors and E500 v2 doubles to 760 64 bits. */ 761 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 762 (TREE_CODE (TYPE) == VECTOR_TYPE \ 763 ? (((TARGET_SPE && SPE_VECTOR_MODE (TYPE_MODE (TYPE))) \ 764 || (TARGET_PAIRED_FLOAT && PAIRED_VECTOR_MODE (TYPE_MODE (TYPE)))) \ 765 ? 64 : 128) \ 766 : ((TARGET_E500_DOUBLE \ 767 && TREE_CODE (TYPE) == REAL_TYPE \ 768 && TYPE_MODE (TYPE) == DFmode) \ 769 ? 64 \ 770 : (TREE_CODE (TYPE) == ARRAY_TYPE \ 771 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 772 && (ALIGN) < BITS_PER_WORD) ? BITS_PER_WORD : (ALIGN))) 773 774 /* Nonzero if move instructions will actually fail to work 775 when given unaligned data. */ 776 #define STRICT_ALIGNMENT 0 777 778 /* Define this macro to be the value 1 if unaligned accesses have a cost 779 many times greater than aligned accesses, for example if they are 780 emulated in a trap handler. */ 781 /* Altivec vector memory instructions simply ignore the low bits; SPE vector 782 memory instructions trap on unaligned accesses; VSX memory instructions are 783 aligned to 4 or 8 bytes. */ 784 #define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) \ 785 (STRICT_ALIGNMENT \ 786 || (((MODE) == SFmode || (MODE) == DFmode || (MODE) == TFmode \ 787 || (MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode \ 788 || (MODE) == DImode) \ 789 && (ALIGN) < 32) \ 790 || (VECTOR_MODE_P ((MODE)) && (((int)(ALIGN)) < VECTOR_ALIGN (MODE)))) 791 792 793 /* Standard register usage. */ 794 795 /* Number of actual hardware registers. 796 The hardware registers are assigned numbers for the compiler 797 from 0 to just below FIRST_PSEUDO_REGISTER. 798 All registers that the compiler knows about must be given numbers, 799 even those that are not normally considered general registers. 800 801 RS/6000 has 32 fixed-point registers, 32 floating-point registers, 802 an MQ register, a count register, a link register, and 8 condition 803 register fields, which we view here as separate registers. AltiVec 804 adds 32 vector registers and a VRsave register. 805 806 In addition, the difference between the frame and argument pointers is 807 a function of the number of registers saved, so we need to have a 808 register for AP that will later be eliminated in favor of SP or FP. 809 This is a normal register, but it is fixed. 810 811 We also create a pseudo register for float/int conversions, that will 812 really represent the memory location used. It is represented here as 813 a register, in order to work around problems in allocating stack storage 814 in inline functions. 815 816 Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame 817 pointer, which is eventually eliminated in favor of SP or FP. */ 818 819 #define FIRST_PSEUDO_REGISTER 114 820 821 /* This must be included for pre gcc 3.0 glibc compatibility. */ 822 #define PRE_GCC3_DWARF_FRAME_REGISTERS 77 823 824 /* Add 32 dwarf columns for synthetic SPE registers. */ 825 #define DWARF_FRAME_REGISTERS ((FIRST_PSEUDO_REGISTER - 1) + 32) 826 827 /* The SPE has an additional 32 synthetic registers, with DWARF debug 828 info numbering for these registers starting at 1200. While eh_frame 829 register numbering need not be the same as the debug info numbering, 830 we choose to number these regs for eh_frame at 1200 too. This allows 831 future versions of the rs6000 backend to add hard registers and 832 continue to use the gcc hard register numbering for eh_frame. If the 833 extra SPE registers in eh_frame were numbered starting from the 834 current value of FIRST_PSEUDO_REGISTER, then if FIRST_PSEUDO_REGISTER 835 changed we'd need to introduce a mapping in DWARF_FRAME_REGNUM to 836 avoid invalidating older SPE eh_frame info. 837 838 We must map them here to avoid huge unwinder tables mostly consisting 839 of unused space. */ 840 #define DWARF_REG_TO_UNWIND_COLUMN(r) \ 841 ((r) > 1200 ? ((r) - 1200 + FIRST_PSEUDO_REGISTER - 1) : (r)) 842 843 /* Use standard DWARF numbering for DWARF debugging information. */ 844 #define DBX_REGISTER_NUMBER(REGNO) rs6000_dbx_register_number (REGNO) 845 846 /* Use gcc hard register numbering for eh_frame. */ 847 #define DWARF_FRAME_REGNUM(REGNO) (REGNO) 848 849 /* Map register numbers held in the call frame info that gcc has 850 collected using DWARF_FRAME_REGNUM to those that should be output in 851 .debug_frame and .eh_frame. We continue to use gcc hard reg numbers 852 for .eh_frame, but use the numbers mandated by the various ABIs for 853 .debug_frame. rs6000_emit_prologue has translated any combination of 854 CR2, CR3, CR4 saves to a save of CR2. The actual code emitted saves 855 the whole of CR, so we map CR2_REGNO to the DWARF reg for CR. */ 856 #define DWARF2_FRAME_REG_OUT(REGNO, FOR_EH) \ 857 ((FOR_EH) ? (REGNO) \ 858 : (REGNO) == CR2_REGNO ? 64 \ 859 : DBX_REGISTER_NUMBER (REGNO)) 860 861 /* 1 for registers that have pervasive standard uses 862 and are not available for the register allocator. 863 864 On RS/6000, r1 is used for the stack. On Darwin, r2 is available 865 as a local register; for all other OS's r2 is the TOC pointer. 866 867 cr5 is not supposed to be used. 868 869 On System V implementations, r13 is fixed and not available for use. */ 870 871 #define FIXED_REGISTERS \ 872 {0, 1, FIXED_R2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, FIXED_R13, 0, 0, \ 873 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 874 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 875 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 876 0, 0, 0, 1, 0, 0, 0, 0, 0, 1, 0, 0, 1, \ 877 /* AltiVec registers. */ \ 878 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 879 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 880 1, 1 \ 881 , 1, 1, 1 \ 882 } 883 884 /* 1 for registers not available across function calls. 885 These must include the FIXED_REGISTERS and also any 886 registers that can be used without being saved. 887 The latter must include the registers where values are returned 888 and the register where structure-value addresses are passed. 889 Aside from that, you can include as many other registers as you like. */ 890 891 #define CALL_USED_REGISTERS \ 892 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 893 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 894 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 895 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 896 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 897 /* AltiVec registers. */ \ 898 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 899 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 900 1, 1 \ 901 , 1, 1, 1 \ 902 } 903 904 /* Like `CALL_USED_REGISTERS' except this macro doesn't require that 905 the entire set of `FIXED_REGISTERS' be included. 906 (`CALL_USED_REGISTERS' must be a superset of `FIXED_REGISTERS'). 907 This macro is optional. If not specified, it defaults to the value 908 of `CALL_USED_REGISTERS'. */ 909 910 #define CALL_REALLY_USED_REGISTERS \ 911 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, FIXED_R13, 0, 0, \ 912 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 913 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 0, 0, \ 914 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 915 1, 1, 1, 1, 1, 1, 0, 0, 0, 1, 1, 1, 1, \ 916 /* AltiVec registers. */ \ 917 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 918 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, \ 919 0, 0 \ 920 , 0, 0, 0 \ 921 } 922 923 #define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1) 924 925 #define FIRST_SAVED_ALTIVEC_REGNO (FIRST_ALTIVEC_REGNO+20) 926 #define FIRST_SAVED_FP_REGNO (14+32) 927 #define FIRST_SAVED_GP_REGNO 13 928 929 /* List the order in which to allocate registers. Each register must be 930 listed once, even those in FIXED_REGISTERS. 931 932 We allocate in the following order: 933 fp0 (not saved or used for anything) 934 fp13 - fp2 (not saved; incoming fp arg registers) 935 fp1 (not saved; return value) 936 fp31 - fp14 (saved; order given to save least number) 937 cr7, cr6 (not saved or special) 938 cr1 (not saved, but used for FP operations) 939 cr0 (not saved, but used for arithmetic operations) 940 cr4, cr3, cr2 (saved) 941 r0 (not saved; cannot be base reg) 942 r9 (not saved; best for TImode) 943 r11, r10, r8-r4 (not saved; highest used first to make less conflict) 944 r3 (not saved; return value register) 945 r31 - r13 (saved; order given to save least number) 946 r12 (not saved; if used for DImode or DFmode would use r13) 947 mq (not saved; best to use it if we can) 948 ctr (not saved; when we have the choice ctr is better) 949 lr (saved) 950 cr5, r1, r2, ap, xer (fixed) 951 v0 - v1 (not saved or used for anything) 952 v13 - v3 (not saved; incoming vector arg registers) 953 v2 (not saved; incoming vector arg reg; return value) 954 v19 - v14 (not saved or used for anything) 955 v31 - v20 (saved; order given to save least number) 956 vrsave, vscr (fixed) 957 spe_acc, spefscr (fixed) 958 sfp (fixed) 959 */ 960 961 #if FIXED_R2 == 1 962 #define MAYBE_R2_AVAILABLE 963 #define MAYBE_R2_FIXED 2, 964 #else 965 #define MAYBE_R2_AVAILABLE 2, 966 #define MAYBE_R2_FIXED 967 #endif 968 969 #define REG_ALLOC_ORDER \ 970 {32, \ 971 45, 44, 43, 42, 41, 40, 39, 38, 37, 36, 35, 34, \ 972 33, \ 973 63, 62, 61, 60, 59, 58, 57, 56, 55, 54, 53, 52, 51, \ 974 50, 49, 48, 47, 46, \ 975 75, 74, 69, 68, 72, 71, 70, \ 976 0, MAYBE_R2_AVAILABLE \ 977 9, 11, 10, 8, 7, 6, 5, 4, \ 978 3, \ 979 31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \ 980 18, 17, 16, 15, 14, 13, 12, \ 981 64, 66, 65, \ 982 73, 1, MAYBE_R2_FIXED 67, 76, \ 983 /* AltiVec registers. */ \ 984 77, 78, \ 985 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, 80, \ 986 79, \ 987 96, 95, 94, 93, 92, 91, \ 988 108, 107, 106, 105, 104, 103, 102, 101, 100, 99, 98, 97, \ 989 109, 110, \ 990 111, 112, 113 \ 991 } 992 993 /* True if register is floating-point. */ 994 #define FP_REGNO_P(N) ((N) >= 32 && (N) <= 63) 995 996 /* True if register is a condition register. */ 997 #define CR_REGNO_P(N) ((N) >= CR0_REGNO && (N) <= CR7_REGNO) 998 999 /* True if register is a condition register, but not cr0. */ 1000 #define CR_REGNO_NOT_CR0_P(N) ((N) >= CR1_REGNO && (N) <= CR7_REGNO) 1001 1002 /* True if register is an integer register. */ 1003 #define INT_REGNO_P(N) \ 1004 ((N) <= 31 || (N) == ARG_POINTER_REGNUM || (N) == FRAME_POINTER_REGNUM) 1005 1006 /* SPE SIMD registers are just the GPRs. */ 1007 #define SPE_SIMD_REGNO_P(N) ((N) <= 31) 1008 1009 /* PAIRED SIMD registers are just the FPRs. */ 1010 #define PAIRED_SIMD_REGNO_P(N) ((N) >= 32 && (N) <= 63) 1011 1012 /* True if register is the XER register. */ 1013 #define XER_REGNO_P(N) ((N) == XER_REGNO) 1014 1015 /* True if register is an AltiVec register. */ 1016 #define ALTIVEC_REGNO_P(N) ((N) >= FIRST_ALTIVEC_REGNO && (N) <= LAST_ALTIVEC_REGNO) 1017 1018 /* True if register is a VSX register. */ 1019 #define VSX_REGNO_P(N) (FP_REGNO_P (N) || ALTIVEC_REGNO_P (N)) 1020 1021 /* Alternate name for any vector register supporting floating point, no matter 1022 which instruction set(s) are available. */ 1023 #define VFLOAT_REGNO_P(N) \ 1024 (ALTIVEC_REGNO_P (N) || (TARGET_VSX && FP_REGNO_P (N))) 1025 1026 /* Alternate name for any vector register supporting integer, no matter which 1027 instruction set(s) are available. */ 1028 #define VINT_REGNO_P(N) ALTIVEC_REGNO_P (N) 1029 1030 /* Alternate name for any vector register supporting logical operations, no 1031 matter which instruction set(s) are available. */ 1032 #define VLOGICAL_REGNO_P(N) VFLOAT_REGNO_P (N) 1033 1034 /* Return number of consecutive hard regs needed starting at reg REGNO 1035 to hold something of mode MODE. */ 1036 1037 #define HARD_REGNO_NREGS(REGNO, MODE) rs6000_hard_regno_nregs[(MODE)][(REGNO)] 1038 1039 /* When setting up caller-save slots (MODE == VOIDmode) ensure we allocate 1040 enough space to account for vectors in FP regs. */ 1041 #define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE) \ 1042 (TARGET_VSX \ 1043 && ((MODE) == VOIDmode || ALTIVEC_OR_VSX_VECTOR_MODE (MODE)) \ 1044 && FP_REGNO_P (REGNO) \ 1045 ? V2DFmode \ 1046 : choose_hard_reg_mode ((REGNO), (NREGS), false)) 1047 1048 #define HARD_REGNO_CALL_PART_CLOBBERED(REGNO, MODE) \ 1049 (((TARGET_32BIT && TARGET_POWERPC64 \ 1050 && (GET_MODE_SIZE (MODE) > 4) \ 1051 && INT_REGNO_P (REGNO)) ? 1 : 0) \ 1052 || (TARGET_VSX && FP_REGNO_P (REGNO) \ 1053 && GET_MODE_SIZE (MODE) > 8)) 1054 1055 #define VSX_VECTOR_MODE(MODE) \ 1056 ((MODE) == V4SFmode \ 1057 || (MODE) == V2DFmode) \ 1058 1059 #define ALTIVEC_VECTOR_MODE(MODE) \ 1060 ((MODE) == V16QImode \ 1061 || (MODE) == V8HImode \ 1062 || (MODE) == V4SFmode \ 1063 || (MODE) == V4SImode) 1064 1065 #define ALTIVEC_OR_VSX_VECTOR_MODE(MODE) \ 1066 (ALTIVEC_VECTOR_MODE (MODE) || VSX_VECTOR_MODE (MODE) \ 1067 || (MODE) == V2DImode) 1068 1069 #define SPE_VECTOR_MODE(MODE) \ 1070 ((MODE) == V4HImode \ 1071 || (MODE) == V2SFmode \ 1072 || (MODE) == V1DImode \ 1073 || (MODE) == V2SImode) 1074 1075 #define PAIRED_VECTOR_MODE(MODE) \ 1076 ((MODE) == V2SFmode) 1077 1078 #define UNITS_PER_SIMD_WORD(MODE) \ 1079 (TARGET_VSX ? UNITS_PER_VSX_WORD \ 1080 : (TARGET_ALTIVEC ? UNITS_PER_ALTIVEC_WORD \ 1081 : (TARGET_SPE ? UNITS_PER_SPE_WORD \ 1082 : (TARGET_PAIRED_FLOAT ? UNITS_PER_PAIRED_WORD \ 1083 : UNITS_PER_WORD)))) 1084 1085 /* Value is TRUE if hard register REGNO can hold a value of 1086 machine-mode MODE. */ 1087 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1088 rs6000_hard_regno_mode_ok_p[(int)(MODE)][REGNO] 1089 1090 /* Value is 1 if it is a good idea to tie two pseudo registers 1091 when one has mode MODE1 and one has mode MODE2. 1092 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1093 for any hard reg, then this must be 0 for correct output. */ 1094 #define MODES_TIEABLE_P(MODE1, MODE2) \ 1095 (SCALAR_FLOAT_MODE_P (MODE1) \ 1096 ? SCALAR_FLOAT_MODE_P (MODE2) \ 1097 : SCALAR_FLOAT_MODE_P (MODE2) \ 1098 ? SCALAR_FLOAT_MODE_P (MODE1) \ 1099 : GET_MODE_CLASS (MODE1) == MODE_CC \ 1100 ? GET_MODE_CLASS (MODE2) == MODE_CC \ 1101 : GET_MODE_CLASS (MODE2) == MODE_CC \ 1102 ? GET_MODE_CLASS (MODE1) == MODE_CC \ 1103 : SPE_VECTOR_MODE (MODE1) \ 1104 ? SPE_VECTOR_MODE (MODE2) \ 1105 : SPE_VECTOR_MODE (MODE2) \ 1106 ? SPE_VECTOR_MODE (MODE1) \ 1107 : ALTIVEC_VECTOR_MODE (MODE1) \ 1108 ? ALTIVEC_VECTOR_MODE (MODE2) \ 1109 : ALTIVEC_VECTOR_MODE (MODE2) \ 1110 ? ALTIVEC_VECTOR_MODE (MODE1) \ 1111 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ 1112 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ 1113 : ALTIVEC_OR_VSX_VECTOR_MODE (MODE2) \ 1114 ? ALTIVEC_OR_VSX_VECTOR_MODE (MODE1) \ 1115 : 1) 1116 1117 /* Post-reload, we can't use any new AltiVec registers, as we already 1118 emitted the vrsave mask. */ 1119 1120 #define HARD_REGNO_RENAME_OK(SRC, DST) \ 1121 (! ALTIVEC_REGNO_P (DST) || df_regs_ever_live_p (DST)) 1122 1123 /* A C expression returning the cost of moving data from a register of class 1124 CLASS1 to one of CLASS2. */ 1125 1126 #define REGISTER_MOVE_COST rs6000_register_move_cost 1127 1128 /* A C expressions returning the cost of moving data of MODE from a register to 1129 or from memory. */ 1130 1131 #define MEMORY_MOVE_COST rs6000_memory_move_cost 1132 1133 /* Specify the cost of a branch insn; roughly the number of extra insns that 1134 should be added to avoid a branch. 1135 1136 Set this to 3 on the RS/6000 since that is roughly the average cost of an 1137 unscheduled conditional branch. */ 1138 1139 #define BRANCH_COST(speed_p, predictable_p) 3 1140 1141 /* Override BRANCH_COST heuristic which empirically produces worse 1142 performance for removing short circuiting from the logical ops. */ 1143 1144 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1145 1146 /* A fixed register used at epilogue generation to address SPE registers 1147 with negative offsets. The 64-bit load/store instructions on the SPE 1148 only take positive offsets (and small ones at that), so we need to 1149 reserve a register for consing up negative offsets. */ 1150 1151 #define FIXED_SCRATCH 0 1152 1153 /* Define this macro to change register usage conditional on target 1154 flags. */ 1155 1156 #define CONDITIONAL_REGISTER_USAGE rs6000_conditional_register_usage () 1157 1158 /* Specify the registers used for certain standard purposes. 1159 The values of these macros are register numbers. */ 1160 1161 /* RS/6000 pc isn't overloaded on a register that the compiler knows about. */ 1162 /* #define PC_REGNUM */ 1163 1164 /* Register to use for pushing function arguments. */ 1165 #define STACK_POINTER_REGNUM 1 1166 1167 /* Base register for access to local variables of the function. */ 1168 #define HARD_FRAME_POINTER_REGNUM 31 1169 1170 /* Base register for access to local variables of the function. */ 1171 #define FRAME_POINTER_REGNUM 113 1172 1173 /* Base register for access to arguments of the function. */ 1174 #define ARG_POINTER_REGNUM 67 1175 1176 /* Place to put static chain when calling a function that requires it. */ 1177 #define STATIC_CHAIN_REGNUM 11 1178 1179 1180 /* Define the classes of registers for register constraints in the 1181 machine description. Also define ranges of constants. 1182 1183 One of the classes must always be named ALL_REGS and include all hard regs. 1184 If there is more than one class, another class must be named NO_REGS 1185 and contain no registers. 1186 1187 The name GENERAL_REGS must be the name of a class (or an alias for 1188 another name such as ALL_REGS). This is the class of registers 1189 that is allowed by "g" or "r" in a register constraint. 1190 Also, registers outside this class are allocated only when 1191 instructions express preferences for them. 1192 1193 The classes must be numbered in nondecreasing order; that is, 1194 a larger-numbered class must never be contained completely 1195 in a smaller-numbered class. 1196 1197 For any two classes, it is very desirable that there be another 1198 class that represents their union. */ 1199 1200 /* The RS/6000 has three types of registers, fixed-point, floating-point, and 1201 condition registers, plus three special registers, MQ, CTR, and the link 1202 register. AltiVec adds a vector register class. VSX registers overlap the 1203 FPR registers and the Altivec registers. 1204 1205 However, r0 is special in that it cannot be used as a base register. 1206 So make a class for registers valid as base registers. 1207 1208 Also, cr0 is the only condition code register that can be used in 1209 arithmetic insns, so make a separate class for it. */ 1210 1211 enum reg_class 1212 { 1213 NO_REGS, 1214 BASE_REGS, 1215 GENERAL_REGS, 1216 FLOAT_REGS, 1217 ALTIVEC_REGS, 1218 VSX_REGS, 1219 VRSAVE_REGS, 1220 VSCR_REGS, 1221 SPE_ACC_REGS, 1222 SPEFSCR_REGS, 1223 NON_SPECIAL_REGS, 1224 MQ_REGS, 1225 LINK_REGS, 1226 CTR_REGS, 1227 LINK_OR_CTR_REGS, 1228 SPECIAL_REGS, 1229 SPEC_OR_GEN_REGS, 1230 CR0_REGS, 1231 CR_REGS, 1232 NON_FLOAT_REGS, 1233 XER_REGS, 1234 ALL_REGS, 1235 LIM_REG_CLASSES 1236 }; 1237 1238 #define N_REG_CLASSES (int) LIM_REG_CLASSES 1239 1240 /* Give names of register classes as strings for dump file. */ 1241 1242 #define REG_CLASS_NAMES \ 1243 { \ 1244 "NO_REGS", \ 1245 "BASE_REGS", \ 1246 "GENERAL_REGS", \ 1247 "FLOAT_REGS", \ 1248 "ALTIVEC_REGS", \ 1249 "VSX_REGS", \ 1250 "VRSAVE_REGS", \ 1251 "VSCR_REGS", \ 1252 "SPE_ACC_REGS", \ 1253 "SPEFSCR_REGS", \ 1254 "NON_SPECIAL_REGS", \ 1255 "MQ_REGS", \ 1256 "LINK_REGS", \ 1257 "CTR_REGS", \ 1258 "LINK_OR_CTR_REGS", \ 1259 "SPECIAL_REGS", \ 1260 "SPEC_OR_GEN_REGS", \ 1261 "CR0_REGS", \ 1262 "CR_REGS", \ 1263 "NON_FLOAT_REGS", \ 1264 "XER_REGS", \ 1265 "ALL_REGS" \ 1266 } 1267 1268 /* Define which registers fit in which classes. 1269 This is an initializer for a vector of HARD_REG_SET 1270 of length N_REG_CLASSES. */ 1271 1272 #define REG_CLASS_CONTENTS \ 1273 { \ 1274 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1275 { 0xfffffffe, 0x00000000, 0x00000008, 0x00020000 }, /* BASE_REGS */ \ 1276 { 0xffffffff, 0x00000000, 0x00000008, 0x00020000 }, /* GENERAL_REGS */ \ 1277 { 0x00000000, 0xffffffff, 0x00000000, 0x00000000 }, /* FLOAT_REGS */ \ 1278 { 0x00000000, 0x00000000, 0xffffe000, 0x00001fff }, /* ALTIVEC_REGS */ \ 1279 { 0x00000000, 0xffffffff, 0xffffe000, 0x00001fff }, /* VSX_REGS */ \ 1280 { 0x00000000, 0x00000000, 0x00000000, 0x00002000 }, /* VRSAVE_REGS */ \ 1281 { 0x00000000, 0x00000000, 0x00000000, 0x00004000 }, /* VSCR_REGS */ \ 1282 { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, /* SPE_ACC_REGS */ \ 1283 { 0x00000000, 0x00000000, 0x00000000, 0x00010000 }, /* SPEFSCR_REGS */ \ 1284 { 0xffffffff, 0xffffffff, 0x00000008, 0x00020000 }, /* NON_SPECIAL_REGS */ \ 1285 { 0x00000000, 0x00000000, 0x00000001, 0x00000000 }, /* MQ_REGS */ \ 1286 { 0x00000000, 0x00000000, 0x00000002, 0x00000000 }, /* LINK_REGS */ \ 1287 { 0x00000000, 0x00000000, 0x00000004, 0x00000000 }, /* CTR_REGS */ \ 1288 { 0x00000000, 0x00000000, 0x00000006, 0x00000000 }, /* LINK_OR_CTR_REGS */ \ 1289 { 0x00000000, 0x00000000, 0x00000007, 0x00002000 }, /* SPECIAL_REGS */ \ 1290 { 0xffffffff, 0x00000000, 0x0000000f, 0x00022000 }, /* SPEC_OR_GEN_REGS */ \ 1291 { 0x00000000, 0x00000000, 0x00000010, 0x00000000 }, /* CR0_REGS */ \ 1292 { 0x00000000, 0x00000000, 0x00000ff0, 0x00000000 }, /* CR_REGS */ \ 1293 { 0xffffffff, 0x00000000, 0x0000efff, 0x00020000 }, /* NON_FLOAT_REGS */ \ 1294 { 0x00000000, 0x00000000, 0x00001000, 0x00000000 }, /* XER_REGS */ \ 1295 { 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff } /* ALL_REGS */ \ 1296 } 1297 1298 /* The following macro defines cover classes for Integrated Register 1299 Allocator. Cover classes is a set of non-intersected register 1300 classes covering all hard registers used for register allocation 1301 purpose. Any move between two registers of a cover class should be 1302 cheaper than load or store of the registers. The macro value is 1303 array of register classes with LIM_REG_CLASSES used as the end 1304 marker. 1305 1306 We need two IRA_COVER_CLASSES, one for pre-VSX, and the other for VSX to 1307 account for the Altivec and Floating registers being subsets of the VSX 1308 register set. */ 1309 1310 #define IRA_COVER_CLASSES_PRE_VSX \ 1311 { \ 1312 GENERAL_REGS, SPECIAL_REGS, FLOAT_REGS, ALTIVEC_REGS, /* VSX_REGS, */ \ 1313 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \ 1314 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \ 1315 CR_REGS, XER_REGS, LIM_REG_CLASSES \ 1316 } 1317 1318 #define IRA_COVER_CLASSES_VSX \ 1319 { \ 1320 GENERAL_REGS, SPECIAL_REGS, /* FLOAT_REGS, ALTIVEC_REGS, */ VSX_REGS, \ 1321 /* VRSAVE_REGS,*/ VSCR_REGS, SPE_ACC_REGS, SPEFSCR_REGS, \ 1322 /* MQ_REGS, LINK_REGS, CTR_REGS, */ \ 1323 CR_REGS, XER_REGS, LIM_REG_CLASSES \ 1324 } 1325 1326 /* The same information, inverted: 1327 Return the class number of the smallest class containing 1328 reg number REGNO. This could be a conditional expression 1329 or could index an array. */ 1330 1331 extern enum reg_class rs6000_regno_regclass[FIRST_PSEUDO_REGISTER]; 1332 1333 #if ENABLE_CHECKING 1334 #define REGNO_REG_CLASS(REGNO) \ 1335 (gcc_assert (IN_RANGE ((REGNO), 0, FIRST_PSEUDO_REGISTER-1)), \ 1336 rs6000_regno_regclass[(REGNO)]) 1337 1338 #else 1339 #define REGNO_REG_CLASS(REGNO) rs6000_regno_regclass[(REGNO)] 1340 #endif 1341 1342 /* Register classes for various constraints that are based on the target 1343 switches. */ 1344 enum r6000_reg_class_enum { 1345 RS6000_CONSTRAINT_d, /* fpr registers for double values */ 1346 RS6000_CONSTRAINT_f, /* fpr registers for single values */ 1347 RS6000_CONSTRAINT_v, /* Altivec registers */ 1348 RS6000_CONSTRAINT_wa, /* Any VSX register */ 1349 RS6000_CONSTRAINT_wd, /* VSX register for V2DF */ 1350 RS6000_CONSTRAINT_wf, /* VSX register for V4SF */ 1351 RS6000_CONSTRAINT_ws, /* VSX register for DF */ 1352 RS6000_CONSTRAINT_MAX 1353 }; 1354 1355 extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX]; 1356 1357 /* The class value for index registers, and the one for base regs. */ 1358 #define INDEX_REG_CLASS GENERAL_REGS 1359 #define BASE_REG_CLASS BASE_REGS 1360 1361 /* Return whether a given register class can hold VSX objects. */ 1362 #define VSX_REG_CLASS_P(CLASS) \ 1363 ((CLASS) == VSX_REGS || (CLASS) == FLOAT_REGS || (CLASS) == ALTIVEC_REGS) 1364 1365 /* Given an rtx X being reloaded into a reg required to be 1366 in class CLASS, return the class of reg to actually use. 1367 In general this is just CLASS; but on some machines 1368 in some cases it is preferable to use a more restrictive class. 1369 1370 On the RS/6000, we have to return NO_REGS when we want to reload a 1371 floating-point CONST_DOUBLE to force it to be copied to memory. 1372 1373 We also don't want to reload integer values into floating-point 1374 registers if we can at all help it. In fact, this can 1375 cause reload to die, if it tries to generate a reload of CTR 1376 into a FP register and discovers it doesn't have the memory location 1377 required. 1378 1379 ??? Would it be a good idea to have reload do the converse, that is 1380 try to reload floating modes into FP registers if possible? 1381 */ 1382 1383 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 1384 rs6000_preferred_reload_class_ptr (X, CLASS) 1385 1386 /* Return the register class of a scratch register needed to copy IN into 1387 or out of a register in CLASS in MODE. If it can be done directly, 1388 NO_REGS is returned. */ 1389 1390 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,IN) \ 1391 rs6000_secondary_reload_class_ptr (CLASS, MODE, IN) 1392 1393 /* If we are copying between FP or AltiVec registers and anything 1394 else, we need a memory location. The exception is when we are 1395 targeting ppc64 and the move to/from fpr to gpr instructions 1396 are available.*/ 1397 1398 #define SECONDARY_MEMORY_NEEDED(CLASS1,CLASS2,MODE) \ 1399 rs6000_secondary_memory_needed_ptr (CLASS1, CLASS2, MODE) 1400 1401 /* For cpus that cannot load/store SDmode values from the 64-bit 1402 FP registers without using a full 64-bit load/store, we need 1403 to allocate a full 64-bit stack slot for them. */ 1404 1405 #define SECONDARY_MEMORY_NEEDED_RTX(MODE) \ 1406 rs6000_secondary_memory_needed_rtx (MODE) 1407 1408 /* Return the maximum number of consecutive registers 1409 needed to represent mode MODE in a register of class CLASS. 1410 1411 On RS/6000, this is the size of MODE in words, except in the FP regs, where 1412 a single reg is enough for two words, unless we have VSX, where the FP 1413 registers can hold 128 bits. */ 1414 #define CLASS_MAX_NREGS(CLASS, MODE) rs6000_class_max_nregs[(MODE)][(CLASS)] 1415 1416 /* Return nonzero if for CLASS a mode change from FROM to TO is invalid. */ 1417 1418 #define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1419 rs6000_cannot_change_mode_class_ptr (FROM, TO, CLASS) 1420 1421 /* Stack layout; function entry, exit and calling. */ 1422 1423 /* Enumeration to give which calling sequence to use. */ 1424 enum rs6000_abi { 1425 ABI_NONE, 1426 ABI_AIX, /* IBM's AIX */ 1427 ABI_V4, /* System V.4/eabi */ 1428 ABI_DARWIN /* Apple's Darwin (OS X kernel) */ 1429 }; 1430 1431 extern enum rs6000_abi rs6000_current_abi; /* available for use by subtarget */ 1432 1433 /* Define this if pushing a word on the stack 1434 makes the stack pointer a smaller address. */ 1435 #define STACK_GROWS_DOWNWARD 1436 1437 /* Offsets recorded in opcodes are a multiple of this alignment factor. */ 1438 #define DWARF_CIE_DATA_ALIGNMENT (-((int) (TARGET_32BIT ? 4 : 8))) 1439 1440 /* Define this to nonzero if the nominal address of the stack frame 1441 is at the high-address end of the local variables; 1442 that is, each additional local variable allocated 1443 goes at a more negative offset in the frame. 1444 1445 On the RS/6000, we grow upwards, from the area after the outgoing 1446 arguments. */ 1447 #define FRAME_GROWS_DOWNWARD (flag_stack_protect != 0) 1448 1449 /* Size of the outgoing register save area */ 1450 #define RS6000_REG_SAVE ((DEFAULT_ABI == ABI_AIX \ 1451 || DEFAULT_ABI == ABI_DARWIN) \ 1452 ? (TARGET_64BIT ? 64 : 32) \ 1453 : 0) 1454 1455 /* Size of the fixed area on the stack */ 1456 #define RS6000_SAVE_AREA \ 1457 (((DEFAULT_ABI == ABI_AIX || DEFAULT_ABI == ABI_DARWIN) ? 24 : 8) \ 1458 << (TARGET_64BIT ? 1 : 0)) 1459 1460 /* MEM representing address to save the TOC register */ 1461 #define RS6000_SAVE_TOC gen_rtx_MEM (Pmode, \ 1462 plus_constant (stack_pointer_rtx, \ 1463 (TARGET_32BIT ? 20 : 40))) 1464 1465 /* Align an address */ 1466 #define RS6000_ALIGN(n,a) (((n) + (a) - 1) & ~((a) - 1)) 1467 1468 /* Offset within stack frame to start allocating local variables at. 1469 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1470 first local allocated. Otherwise, it is the offset to the BEGINNING 1471 of the first local allocated. 1472 1473 On the RS/6000, the frame pointer is the same as the stack pointer, 1474 except for dynamic allocations. So we start after the fixed area and 1475 outgoing parameter area. */ 1476 1477 #define STARTING_FRAME_OFFSET \ 1478 (FRAME_GROWS_DOWNWARD \ 1479 ? 0 \ 1480 : (RS6000_ALIGN (crtl->outgoing_args_size, \ 1481 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1482 + RS6000_SAVE_AREA)) 1483 1484 /* Offset from the stack pointer register to an item dynamically 1485 allocated on the stack, e.g., by `alloca'. 1486 1487 The default value for this macro is `STACK_POINTER_OFFSET' plus the 1488 length of the outgoing arguments. The default is correct for most 1489 machines. See `function.c' for details. */ 1490 #define STACK_DYNAMIC_OFFSET(FUNDECL) \ 1491 (RS6000_ALIGN (crtl->outgoing_args_size, \ 1492 (TARGET_ALTIVEC || TARGET_VSX) ? 16 : 8) \ 1493 + (STACK_POINTER_OFFSET)) 1494 1495 /* If we generate an insn to push BYTES bytes, 1496 this says how many the stack pointer really advances by. 1497 On RS/6000, don't define this because there are no push insns. */ 1498 /* #define PUSH_ROUNDING(BYTES) */ 1499 1500 /* Offset of first parameter from the argument pointer register value. 1501 On the RS/6000, we define the argument pointer to the start of the fixed 1502 area. */ 1503 #define FIRST_PARM_OFFSET(FNDECL) RS6000_SAVE_AREA 1504 1505 /* Offset from the argument pointer register value to the top of 1506 stack. This is different from FIRST_PARM_OFFSET because of the 1507 register save area. */ 1508 #define ARG_POINTER_CFA_OFFSET(FNDECL) 0 1509 1510 /* Define this if stack space is still allocated for a parameter passed 1511 in a register. The value is the number of bytes allocated to this 1512 area. */ 1513 #define REG_PARM_STACK_SPACE(FNDECL) RS6000_REG_SAVE 1514 1515 /* Define this if the above stack space is to be considered part of the 1516 space allocated by the caller. */ 1517 #define OUTGOING_REG_PARM_STACK_SPACE(FNTYPE) 1 1518 1519 /* This is the difference between the logical top of stack and the actual sp. 1520 1521 For the RS/6000, sp points past the fixed area. */ 1522 #define STACK_POINTER_OFFSET RS6000_SAVE_AREA 1523 1524 /* Define this if the maximum size of all the outgoing args is to be 1525 accumulated and pushed during the prologue. The amount can be 1526 found in the variable crtl->outgoing_args_size. */ 1527 #define ACCUMULATE_OUTGOING_ARGS 1 1528 1529 /* Value is the number of bytes of arguments automatically 1530 popped when returning from a subroutine call. 1531 FUNDECL is the declaration node of the function (as a tree), 1532 FUNTYPE is the data type of the function (as a tree), 1533 or for a library call it is an identifier node for the subroutine name. 1534 SIZE is the number of bytes of arguments passed on the stack. */ 1535 1536 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) 0 1537 1538 /* Define how to find the value returned by a library function 1539 assuming the value has mode MODE. */ 1540 1541 #define LIBCALL_VALUE(MODE) rs6000_libcall_value ((MODE)) 1542 1543 /* DRAFT_V4_STRUCT_RET defaults off. */ 1544 #define DRAFT_V4_STRUCT_RET 0 1545 1546 /* Let TARGET_RETURN_IN_MEMORY control what happens. */ 1547 #define DEFAULT_PCC_STRUCT_RETURN 0 1548 1549 /* Mode of stack savearea. 1550 FUNCTION is VOIDmode because calling convention maintains SP. 1551 BLOCK needs Pmode for SP. 1552 NONLOCAL needs twice Pmode to maintain both backchain and SP. */ 1553 #define STACK_SAVEAREA_MODE(LEVEL) \ 1554 (LEVEL == SAVE_FUNCTION ? VOIDmode \ 1555 : LEVEL == SAVE_NONLOCAL ? (TARGET_32BIT ? DImode : TImode) : Pmode) 1556 1557 /* Minimum and maximum general purpose registers used to hold arguments. */ 1558 #define GP_ARG_MIN_REG 3 1559 #define GP_ARG_MAX_REG 10 1560 #define GP_ARG_NUM_REG (GP_ARG_MAX_REG - GP_ARG_MIN_REG + 1) 1561 1562 /* Minimum and maximum floating point registers used to hold arguments. */ 1563 #define FP_ARG_MIN_REG 33 1564 #define FP_ARG_AIX_MAX_REG 45 1565 #define FP_ARG_V4_MAX_REG 40 1566 #define FP_ARG_MAX_REG ((DEFAULT_ABI == ABI_AIX \ 1567 || DEFAULT_ABI == ABI_DARWIN) \ 1568 ? FP_ARG_AIX_MAX_REG : FP_ARG_V4_MAX_REG) 1569 #define FP_ARG_NUM_REG (FP_ARG_MAX_REG - FP_ARG_MIN_REG + 1) 1570 1571 /* Minimum and maximum AltiVec registers used to hold arguments. */ 1572 #define ALTIVEC_ARG_MIN_REG (FIRST_ALTIVEC_REGNO + 2) 1573 #define ALTIVEC_ARG_MAX_REG (ALTIVEC_ARG_MIN_REG + 11) 1574 #define ALTIVEC_ARG_NUM_REG (ALTIVEC_ARG_MAX_REG - ALTIVEC_ARG_MIN_REG + 1) 1575 1576 /* Return registers */ 1577 #define GP_ARG_RETURN GP_ARG_MIN_REG 1578 #define FP_ARG_RETURN FP_ARG_MIN_REG 1579 #define ALTIVEC_ARG_RETURN (FIRST_ALTIVEC_REGNO + 2) 1580 1581 /* Flags for the call/call_value rtl operations set up by function_arg */ 1582 #define CALL_NORMAL 0x00000000 /* no special processing */ 1583 /* Bits in 0x00000001 are unused. */ 1584 #define CALL_V4_CLEAR_FP_ARGS 0x00000002 /* V.4, no FP args passed */ 1585 #define CALL_V4_SET_FP_ARGS 0x00000004 /* V.4, FP args were passed */ 1586 #define CALL_LONG 0x00000008 /* always call indirect */ 1587 #define CALL_LIBCALL 0x00000010 /* libcall */ 1588 1589 /* We don't have prologue and epilogue functions to save/restore 1590 everything for most ABIs. */ 1591 #define WORLD_SAVE_P(INFO) 0 1592 1593 /* 1 if N is a possible register number for a function value 1594 as seen by the caller. 1595 1596 On RS/6000, this is r3, fp1, and v2 (for AltiVec). */ 1597 #define FUNCTION_VALUE_REGNO_P(N) \ 1598 ((N) == GP_ARG_RETURN \ 1599 || ((N) == FP_ARG_RETURN && TARGET_HARD_FLOAT && TARGET_FPRS) \ 1600 || ((N) == ALTIVEC_ARG_RETURN && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI)) 1601 1602 /* 1 if N is a possible register number for function argument passing. 1603 On RS/6000, these are r3-r10 and fp1-fp13. 1604 On AltiVec, v2 - v13 are used for passing vectors. */ 1605 #define FUNCTION_ARG_REGNO_P(N) \ 1606 ((unsigned) (N) - GP_ARG_MIN_REG < GP_ARG_NUM_REG \ 1607 || ((unsigned) (N) - ALTIVEC_ARG_MIN_REG < ALTIVEC_ARG_NUM_REG \ 1608 && TARGET_ALTIVEC && TARGET_ALTIVEC_ABI) \ 1609 || ((unsigned) (N) - FP_ARG_MIN_REG < FP_ARG_NUM_REG \ 1610 && TARGET_HARD_FLOAT && TARGET_FPRS)) 1611 1612 /* Define a data type for recording info about an argument list 1613 during the scan of that argument list. This data type should 1614 hold all necessary information about the function itself 1615 and about the args processed so far, enough to enable macros 1616 such as FUNCTION_ARG to determine where the next arg should go. 1617 1618 On the RS/6000, this is a structure. The first element is the number of 1619 total argument words, the second is used to store the next 1620 floating-point register number, and the third says how many more args we 1621 have prototype types for. 1622 1623 For ABI_V4, we treat these slightly differently -- `sysv_gregno' is 1624 the next available GP register, `fregno' is the next available FP 1625 register, and `words' is the number of words used on the stack. 1626 1627 The varargs/stdarg support requires that this structure's size 1628 be a multiple of sizeof(int). */ 1629 1630 typedef struct rs6000_args 1631 { 1632 int words; /* # words used for passing GP registers */ 1633 int fregno; /* next available FP register */ 1634 int vregno; /* next available AltiVec register */ 1635 int nargs_prototype; /* # args left in the current prototype */ 1636 int prototype; /* Whether a prototype was defined */ 1637 int stdarg; /* Whether function is a stdarg function. */ 1638 int call_cookie; /* Do special things for this call */ 1639 int sysv_gregno; /* next available GP register */ 1640 int intoffset; /* running offset in struct (darwin64) */ 1641 int use_stack; /* any part of struct on stack (darwin64) */ 1642 int named; /* false for varargs params */ 1643 } CUMULATIVE_ARGS; 1644 1645 /* Initialize a variable CUM of type CUMULATIVE_ARGS 1646 for a call to a function whose data type is FNTYPE. 1647 For a library call, FNTYPE is 0. */ 1648 1649 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 1650 init_cumulative_args (&CUM, FNTYPE, LIBNAME, FALSE, FALSE, N_NAMED_ARGS) 1651 1652 /* Similar, but when scanning the definition of a procedure. We always 1653 set NARGS_PROTOTYPE large so we never return an EXPR_LIST. */ 1654 1655 #define INIT_CUMULATIVE_INCOMING_ARGS(CUM, FNTYPE, LIBNAME) \ 1656 init_cumulative_args (&CUM, FNTYPE, LIBNAME, TRUE, FALSE, 1000) 1657 1658 /* Like INIT_CUMULATIVE_ARGS' but only used for outgoing libcalls. */ 1659 1660 #define INIT_CUMULATIVE_LIBCALL_ARGS(CUM, MODE, LIBNAME) \ 1661 init_cumulative_args (&CUM, NULL_TREE, LIBNAME, FALSE, TRUE, 0) 1662 1663 /* Update the data in CUM to advance over an argument 1664 of mode MODE and data type TYPE. 1665 (TYPE is null for libcalls where that information may not be available.) */ 1666 1667 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1668 function_arg_advance (&CUM, MODE, TYPE, NAMED, 0) 1669 1670 /* Determine where to put an argument to a function. 1671 Value is zero to push the argument on the stack, 1672 or a hard register in which to store the argument. 1673 1674 MODE is the argument's machine mode. 1675 TYPE is the data type of the argument (as a tree). 1676 This is null for libcalls where that information may 1677 not be available. 1678 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1679 the preceding args and about the function being called. 1680 NAMED is nonzero if this argument is a named parameter 1681 (otherwise it is an extra parameter matching an ellipsis). 1682 1683 On RS/6000 the first eight words of non-FP are normally in registers 1684 and the rest are pushed. The first 13 FP args are in registers. 1685 1686 If this is floating-point and no prototype is specified, we use 1687 both an FP and integer register (or possibly FP reg and stack). Library 1688 functions (when TYPE is zero) always have the proper types for args, 1689 so we can pass the FP value just in one register. emit_library_function 1690 doesn't support EXPR_LIST anyway. */ 1691 1692 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1693 function_arg (&CUM, MODE, TYPE, NAMED) 1694 1695 /* If defined, a C expression which determines whether, and in which 1696 direction, to pad out an argument with extra space. The value 1697 should be of type `enum direction': either `upward' to pad above 1698 the argument, `downward' to pad below, or `none' to inhibit 1699 padding. */ 1700 1701 #define FUNCTION_ARG_PADDING(MODE, TYPE) function_arg_padding (MODE, TYPE) 1702 1703 /* If defined, a C expression that gives the alignment boundary, in bits, 1704 of an argument with the specified mode and type. If it is not defined, 1705 PARM_BOUNDARY is used for all arguments. */ 1706 1707 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 1708 function_arg_boundary (MODE, TYPE) 1709 1710 #define PAD_VARARGS_DOWN \ 1711 (FUNCTION_ARG_PADDING (TYPE_MODE (type), type) == downward) 1712 1713 /* Output assembler code to FILE to increment profiler label # LABELNO 1714 for profiling a function entry. */ 1715 1716 #define FUNCTION_PROFILER(FILE, LABELNO) \ 1717 output_function_profiler ((FILE), (LABELNO)); 1718 1719 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1720 the stack pointer does not matter. No definition is equivalent to 1721 always zero. 1722 1723 On the RS/6000, this is nonzero because we can restore the stack from 1724 its backpointer, which we maintain. */ 1725 #define EXIT_IGNORE_STACK 1 1726 1727 /* Define this macro as a C expression that is nonzero for registers 1728 that are used by the epilogue or the return' pattern. The stack 1729 and frame pointer registers are already be assumed to be used as 1730 needed. */ 1731 1732 #define EPILOGUE_USES(REGNO) \ 1733 ((reload_completed && (REGNO) == LR_REGNO) \ 1734 || (TARGET_ALTIVEC && (REGNO) == VRSAVE_REGNO) \ 1735 || (crtl->calls_eh_return \ 1736 && TARGET_AIX \ 1737 && (REGNO) == 2)) 1738 1739 1740 /* Length in units of the trampoline for entering a nested function. */ 1741 1742 #define TRAMPOLINE_SIZE rs6000_trampoline_size () 1743 1744 /* Definitions for __builtin_return_address and __builtin_frame_address. 1745 __builtin_return_address (0) should give link register (65), enable 1746 this. */ 1747 /* This should be uncommented, so that the link register is used, but 1748 currently this would result in unmatched insns and spilling fixed 1749 registers so we'll leave it for another day. When these problems are 1750 taken care of one additional fetch will be necessary in RETURN_ADDR_RTX. 1751 (mrs) */ 1752 /* #define RETURN_ADDR_IN_PREVIOUS_FRAME */ 1753 1754 /* Number of bytes into the frame return addresses can be found. See 1755 rs6000_stack_info in rs6000.c for more information on how the different 1756 abi's store the return address. */ 1757 #define RETURN_ADDRESS_OFFSET \ 1758 ((DEFAULT_ABI == ABI_AIX \ 1759 || DEFAULT_ABI == ABI_DARWIN) ? (TARGET_32BIT ? 8 : 16) : \ 1760 (DEFAULT_ABI == ABI_V4) ? 4 : \ 1761 (internal_error ("RETURN_ADDRESS_OFFSET not supported"), 0)) 1762 1763 /* The current return address is in link register (65). The return address 1764 of anything farther back is accessed normally at an offset of 8 from the 1765 frame pointer. */ 1766 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 1767 (rs6000_return_addr (COUNT, FRAME)) 1768 1769 1770 /* Definitions for register eliminations. 1771 1772 We have two registers that can be eliminated on the RS/6000. First, the 1773 frame pointer register can often be eliminated in favor of the stack 1774 pointer register. Secondly, the argument pointer register can always be 1775 eliminated; it is replaced with either the stack or frame pointer. 1776 1777 In addition, we use the elimination mechanism to see if r30 is needed 1778 Initially we assume that it isn't. If it is, we spill it. This is done 1779 by making it an eliminable register. We replace it with itself so that 1780 if it isn't needed, then existing uses won't be modified. */ 1781 1782 /* This is an array of structures. Each structure initializes one pair 1783 of eliminable registers. The "from" register number is given first, 1784 followed by "to". Eliminations of the same "from" register are listed 1785 in order of preference. */ 1786 #define ELIMINABLE_REGS \ 1787 {{ HARD_FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1788 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1789 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1790 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM}, \ 1791 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM}, \ 1792 { RS6000_PIC_OFFSET_TABLE_REGNUM, RS6000_PIC_OFFSET_TABLE_REGNUM } } 1793 1794 /* Define the offset between two registers, one to be eliminated, and the other 1795 its replacement, at the start of a routine. */ 1796 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1797 ((OFFSET) = rs6000_initial_elimination_offset(FROM, TO)) 1798 1799 /* Addressing modes, and classification of registers for them. */ 1800 1801 #define HAVE_PRE_DECREMENT 1 1802 #define HAVE_PRE_INCREMENT 1 1803 #define HAVE_PRE_MODIFY_DISP 1 1804 #define HAVE_PRE_MODIFY_REG 1 1805 1806 /* Macros to check register numbers against specific register classes. */ 1807 1808 /* These assume that REGNO is a hard or pseudo reg number. 1809 They give nonzero only if REGNO is a hard reg of the suitable class 1810 or a pseudo reg currently allocated to a suitable hard reg. 1811 Since they use reg_renumber, they are safe only once reg_renumber 1812 has been allocated, which happens in local-alloc.c. */ 1813 1814 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 1815 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1816 ? (REGNO) <= 31 || (REGNO) == 67 \ 1817 || (REGNO) == FRAME_POINTER_REGNUM \ 1818 : (reg_renumber[REGNO] >= 0 \ 1819 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1820 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1821 1822 #define REGNO_OK_FOR_BASE_P(REGNO) \ 1823 ((REGNO) < FIRST_PSEUDO_REGISTER \ 1824 ? ((REGNO) > 0 && (REGNO) <= 31) || (REGNO) == 67 \ 1825 || (REGNO) == FRAME_POINTER_REGNUM \ 1826 : (reg_renumber[REGNO] > 0 \ 1827 && (reg_renumber[REGNO] <= 31 || reg_renumber[REGNO] == 67 \ 1828 || reg_renumber[REGNO] == FRAME_POINTER_REGNUM))) 1829 1830 /* Nonzero if X is a hard reg that can be used as an index 1831 or if it is a pseudo reg in the non-strict case. */ 1832 #define INT_REG_OK_FOR_INDEX_P(X, STRICT) \ 1833 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1834 || REGNO_OK_FOR_INDEX_P (REGNO (X))) 1835 1836 /* Nonzero if X is a hard reg that can be used as a base reg 1837 or if it is a pseudo reg in the non-strict case. */ 1838 #define INT_REG_OK_FOR_BASE_P(X, STRICT) \ 1839 ((!(STRICT) && REGNO (X) >= FIRST_PSEUDO_REGISTER) \ 1840 || REGNO_OK_FOR_BASE_P (REGNO (X))) 1841 1842 1843 /* Maximum number of registers that can appear in a valid memory address. */ 1844 1845 #define MAX_REGS_PER_ADDRESS 2 1846 1847 /* Recognize any constant value that is a valid address. */ 1848 1849 #define CONSTANT_ADDRESS_P(X) \ 1850 (GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 1851 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 1852 || GET_CODE (X) == HIGH) 1853 1854 /* Nonzero if the constant value X is a legitimate general operand. 1855 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1856 1857 On the RS/6000, all integer constants are acceptable, most won't be valid 1858 for particular insns, though. Only easy FP constants are 1859 acceptable. */ 1860 1861 #define LEGITIMATE_CONSTANT_P(X) \ 1862 (((GET_CODE (X) != CONST_DOUBLE \ 1863 && GET_CODE (X) != CONST_VECTOR) \ 1864 || GET_MODE (X) == VOIDmode \ 1865 || (TARGET_POWERPC64 && GET_MODE (X) == DImode) \ 1866 || easy_fp_constant (X, GET_MODE (X)) \ 1867 || easy_vector_constant (X, GET_MODE (X))) \ 1868 && !rs6000_tls_referenced_p (X)) 1869 1870 #define EASY_VECTOR_15(n) ((n) >= -16 && (n) <= 15) 1871 #define EASY_VECTOR_15_ADD_SELF(n) (!EASY_VECTOR_15((n)) \ 1872 && EASY_VECTOR_15((n) >> 1) \ 1873 && ((n) & 1) == 0) 1874 1875 #define EASY_VECTOR_MSB(n,mode) \ 1876 (((unsigned HOST_WIDE_INT)n) == \ 1877 ((((unsigned HOST_WIDE_INT)GET_MODE_MASK (mode)) + 1) >> 1)) 1878 1879 1880 /* Try a machine-dependent way of reloading an illegitimate address 1881 operand. If we find one, push the reload and jump to WIN. This 1882 macro is used in only one place: `find_reloads_address' in reload.c. 1883 1884 Implemented on rs6000 by rs6000_legitimize_reload_address. 1885 Note that (X) is evaluated twice; this is safe in current usage. */ 1886 1887 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 1888 do { \ 1889 int win; \ 1890 (X) = rs6000_legitimize_reload_address_ptr ((X), (MODE), (OPNUM), \ 1891 (int)(TYPE), (IND_LEVELS), &win); \ 1892 if ( win ) \ 1893 goto WIN; \ 1894 } while (0) 1895 1896 /* Go to LABEL if ADDR (a legitimate address expression) 1897 has an effect that depends on the machine mode it is used for. */ 1898 1899 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR,LABEL) \ 1900 do { \ 1901 if (rs6000_mode_dependent_address_ptr (ADDR)) \ 1902 goto LABEL; \ 1903 } while (0) 1904 1905 #define FIND_BASE_TERM rs6000_find_base_term 1906 1907 /* The register number of the register used to address a table of 1908 static data addresses in memory. In some cases this register is 1909 defined by a processor's "application binary interface" (ABI). 1910 When this macro is defined, RTL is generated for this register 1911 once, as with the stack pointer and frame pointer registers. If 1912 this macro is not defined, it is up to the machine-dependent files 1913 to allocate such a register (if necessary). */ 1914 1915 #define RS6000_PIC_OFFSET_TABLE_REGNUM 30 1916 #define PIC_OFFSET_TABLE_REGNUM (flag_pic ? RS6000_PIC_OFFSET_TABLE_REGNUM : INVALID_REGNUM) 1917 1918 #define TOC_REGISTER (TARGET_MINIMAL_TOC ? RS6000_PIC_OFFSET_TABLE_REGNUM : 2) 1919 1920 /* Define this macro if the register defined by 1921 `PIC_OFFSET_TABLE_REGNUM' is clobbered by calls. Do not define 1922 this macro if `PIC_OFFSET_TABLE_REGNUM' is not defined. */ 1923 1924 /* #define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED */ 1925 1926 /* A C expression that is nonzero if X is a legitimate immediate 1927 operand on the target machine when generating position independent 1928 code. You can assume that X satisfies `CONSTANT_P', so you need 1929 not check this. You can also assume FLAG_PIC is true, so you need 1930 not check it either. You need not define this macro if all 1931 constants (including `SYMBOL_REF') can be immediate operands when 1932 generating position independent code. */ 1933 1934 /* #define LEGITIMATE_PIC_OPERAND_P (X) */ 1935 1936 /* Define this if some processing needs to be done immediately before 1937 emitting code for an insn. */ 1938 1939 #define FINAL_PRESCAN_INSN(INSN,OPERANDS,NOPERANDS) \ 1940 rs6000_final_prescan_insn (INSN, OPERANDS, NOPERANDS) 1941 1942 /* Specify the machine mode that this machine uses 1943 for the index in the tablejump instruction. */ 1944 #define CASE_VECTOR_MODE SImode 1945 1946 /* Define as C expression which evaluates to nonzero if the tablejump 1947 instruction expects the table to contain offsets from the address of the 1948 table. 1949 Do not define this if the table should contain absolute addresses. */ 1950 #define CASE_VECTOR_PC_RELATIVE 1 1951 1952 /* Define this as 1 if `char' should by default be signed; else as 0. */ 1953 #define DEFAULT_SIGNED_CHAR 0 1954 1955 /* This flag, if defined, says the same insns that convert to a signed fixnum 1956 also convert validly to an unsigned one. */ 1957 1958 /* #define FIXUNS_TRUNC_LIKE_FIX_TRUNC */ 1959 1960 /* An integer expression for the size in bits of the largest integer machine 1961 mode that should actually be used. */ 1962 1963 /* Allow pairs of registers to be used, which is the intent of the default. */ 1964 #define MAX_FIXED_MODE_SIZE GET_MODE_BITSIZE (TARGET_POWERPC64 ? TImode : DImode) 1965 1966 /* Max number of bytes we can move from memory to memory 1967 in one reasonably fast instruction. */ 1968 #define MOVE_MAX (! TARGET_POWERPC64 ? 4 : 8) 1969 #define MAX_MOVE_MAX 8 1970 1971 /* Nonzero if access to memory by bytes is no faster than for words. 1972 Also nonzero if doing byte operations (specifically shifts) in registers 1973 is undesirable. */ 1974 #define SLOW_BYTE_ACCESS 1 1975 1976 /* Define if operations between registers always perform the operation 1977 on the full register even if a narrower mode is specified. */ 1978 #define WORD_REGISTER_OPERATIONS 1979 1980 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1981 will either zero-extend or sign-extend. The value of this macro should 1982 be the code that says which one of the two operations is implicitly 1983 done, UNKNOWN if none. */ 1984 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1985 1986 /* Define if loading short immediate values into registers sign extends. */ 1987 #define SHORT_IMMEDIATES_SIGN_EXTEND 1988 1989 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1990 is done just by pretending it is already truncated. */ 1991 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1992 1993 /* The cntlzw and cntlzd instructions return 32 and 64 for input of zero. */ 1994 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) \ 1995 ((VALUE) = ((MODE) == SImode ? 32 : 64), 1) 1996 1997 /* The CTZ patterns return -1 for input of zero. */ 1998 #define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = -1, 1) 1999 2000 /* Specify the machine mode that pointers have. 2001 After generation of rtl, the compiler makes no further distinction 2002 between pointers and any other objects of this machine mode. */ 2003 extern unsigned rs6000_pmode; 2004 #define Pmode ((enum machine_mode)rs6000_pmode) 2005 2006 /* Supply definition of STACK_SIZE_MODE for allocate_dynamic_stack_space. */ 2007 #define STACK_SIZE_MODE (TARGET_32BIT ? SImode : DImode) 2008 2009 /* Mode of a function address in a call instruction (for indexing purposes). 2010 Doesn't matter on RS/6000. */ 2011 #define FUNCTION_MODE SImode 2012 2013 /* Define this if addresses of constant functions 2014 shouldn't be put through pseudo regs where they can be cse'd. 2015 Desirable on machines where ordinary constants are expensive 2016 but a CALL with constant address is cheap. */ 2017 #define NO_FUNCTION_CSE 2018 2019 /* Define this to be nonzero if shift instructions ignore all but the low-order 2020 few bits. 2021 2022 The sle and sre instructions which allow SHIFT_COUNT_TRUNCATED 2023 have been dropped from the PowerPC architecture. */ 2024 2025 #define SHIFT_COUNT_TRUNCATED (TARGET_POWER ? 1 : 0) 2026 2027 /* Adjust the length of an INSN. LENGTH is the currently-computed length and 2028 should be adjusted to reflect any required changes. This macro is used when 2029 there is some systematic length adjustment required that would be difficult 2030 to express in the length attribute. */ 2031 2032 /* #define ADJUST_INSN_LENGTH(X,LENGTH) */ 2033 2034 /* Given a comparison code (EQ, NE, etc.) and the first operand of a 2035 COMPARE, return the mode to be used for the comparison. For 2036 floating-point, CCFPmode should be used. CCUNSmode should be used 2037 for unsigned comparisons. CCEQmode should be used when we are 2038 doing an inequality comparison on the result of a 2039 comparison. CCmode should be used in all other cases. */ 2040 2041 #define SELECT_CC_MODE(OP,X,Y) \ 2042 (SCALAR_FLOAT_MODE_P (GET_MODE (X)) ? CCFPmode \ 2043 : (OP) == GTU || (OP) == LTU || (OP) == GEU || (OP) == LEU ? CCUNSmode \ 2044 : (((OP) == EQ || (OP) == NE) && COMPARISON_P (X) \ 2045 ? CCEQmode : CCmode)) 2046 2047 /* Can the condition code MODE be safely reversed? This is safe in 2048 all cases on this port, because at present it doesn't use the 2049 trapping FP comparisons (fcmpo). */ 2050 #define REVERSIBLE_CC_MODE(MODE) 1 2051 2052 /* Given a condition code and a mode, return the inverse condition. */ 2053 #define REVERSE_CONDITION(CODE, MODE) rs6000_reverse_condition (MODE, CODE) 2054 2055 2056 /* Control the assembler format that we output. */ 2057 2058 /* A C string constant describing how to begin a comment in the target 2059 assembler language. The compiler assumes that the comment will end at 2060 the end of the line. */ 2061 #define ASM_COMMENT_START " #" 2062 2063 /* Flag to say the TOC is initialized */ 2064 extern int toc_initialized; 2065 2066 /* Macro to output a special constant pool entry. Go to WIN if we output 2067 it. Otherwise, it is written the usual way. 2068 2069 On the RS/6000, toc entries are handled this way. */ 2070 2071 #define ASM_OUTPUT_SPECIAL_POOL_ENTRY(FILE, X, MODE, ALIGN, LABELNO, WIN) \ 2072 { if (ASM_OUTPUT_SPECIAL_POOL_ENTRY_P (X, MODE)) \ 2073 { \ 2074 output_toc (FILE, X, LABELNO, MODE); \ 2075 goto WIN; \ 2076 } \ 2077 } 2078 2079 #ifdef HAVE_GAS_WEAK 2080 #define RS6000_WEAK 1 2081 #else 2082 #define RS6000_WEAK 0 2083 #endif 2084 2085 #if RS6000_WEAK 2086 /* Used in lieu of ASM_WEAKEN_LABEL. */ 2087 #define ASM_WEAKEN_DECL(FILE, DECL, NAME, VAL) \ 2088 do \ 2089 { \ 2090 fputs ("\t.weak\t", (FILE)); \ 2091 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2092 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2093 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2094 { \ 2095 if (TARGET_XCOFF) \ 2096 fputs ("[DS]", (FILE)); \ 2097 fputs ("\n\t.weak\t.", (FILE)); \ 2098 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2099 } \ 2100 fputc ('\n', (FILE)); \ 2101 if (VAL) \ 2102 { \ 2103 ASM_OUTPUT_DEF ((FILE), (NAME), (VAL)); \ 2104 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2105 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2106 { \ 2107 fputs ("\t.set\t.", (FILE)); \ 2108 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2109 fputs (",.", (FILE)); \ 2110 RS6000_OUTPUT_BASENAME ((FILE), (VAL)); \ 2111 fputc ('\n', (FILE)); \ 2112 } \ 2113 } \ 2114 } \ 2115 while (0) 2116 #endif 2117 2118 #if HAVE_GAS_WEAKREF 2119 #define ASM_OUTPUT_WEAKREF(FILE, DECL, NAME, VALUE) \ 2120 do \ 2121 { \ 2122 fputs ("\t.weakref\t", (FILE)); \ 2123 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2124 fputs (", ", (FILE)); \ 2125 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2126 if ((DECL) && TREE_CODE (DECL) == FUNCTION_DECL \ 2127 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2128 { \ 2129 fputs ("\n\t.weakref\t.", (FILE)); \ 2130 RS6000_OUTPUT_BASENAME ((FILE), (NAME)); \ 2131 fputs (", .", (FILE)); \ 2132 RS6000_OUTPUT_BASENAME ((FILE), (VALUE)); \ 2133 } \ 2134 fputc ('\n', (FILE)); \ 2135 } while (0) 2136 #endif 2137 2138 /* This implements the `alias' attribute. */ 2139 #undef ASM_OUTPUT_DEF_FROM_DECLS 2140 #define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL, TARGET) \ 2141 do \ 2142 { \ 2143 const char *alias = XSTR (XEXP (DECL_RTL (DECL), 0), 0); \ 2144 const char *name = IDENTIFIER_POINTER (TARGET); \ 2145 if (TREE_CODE (DECL) == FUNCTION_DECL \ 2146 && DEFAULT_ABI == ABI_AIX && DOT_SYMBOLS) \ 2147 { \ 2148 if (TREE_PUBLIC (DECL)) \ 2149 { \ 2150 if (!RS6000_WEAK || !DECL_WEAK (DECL)) \ 2151 { \ 2152 fputs ("\t.globl\t.", FILE); \ 2153 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2154 putc ('\n', FILE); \ 2155 } \ 2156 } \ 2157 else if (TARGET_XCOFF) \ 2158 { \ 2159 fputs ("\t.lglobl\t.", FILE); \ 2160 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2161 putc ('\n', FILE); \ 2162 } \ 2163 fputs ("\t.set\t.", FILE); \ 2164 RS6000_OUTPUT_BASENAME (FILE, alias); \ 2165 fputs (",.", FILE); \ 2166 RS6000_OUTPUT_BASENAME (FILE, name); \ 2167 fputc ('\n', FILE); \ 2168 } \ 2169 ASM_OUTPUT_DEF (FILE, alias, name); \ 2170 } \ 2171 while (0) 2172 2173 #define TARGET_ASM_FILE_START rs6000_file_start 2174 2175 /* Output to assembler file text saying following lines 2176 may contain character constants, extra white space, comments, etc. */ 2177 2178 #define ASM_APP_ON "" 2179 2180 /* Output to assembler file text saying following lines 2181 no longer contain unusual constructs. */ 2182 2183 #define ASM_APP_OFF "" 2184 2185 /* How to refer to registers in assembler output. 2186 This sequence is indexed by compiler's hard-register-number (see above). */ 2187 2188 extern char rs6000_reg_names[][8]; /* register names (0 vs. %r0). */ 2189 2190 #define REGISTER_NAMES \ 2191 { \ 2192 &rs6000_reg_names[ 0][0], /* r0 */ \ 2193 &rs6000_reg_names[ 1][0], /* r1 */ \ 2194 &rs6000_reg_names[ 2][0], /* r2 */ \ 2195 &rs6000_reg_names[ 3][0], /* r3 */ \ 2196 &rs6000_reg_names[ 4][0], /* r4 */ \ 2197 &rs6000_reg_names[ 5][0], /* r5 */ \ 2198 &rs6000_reg_names[ 6][0], /* r6 */ \ 2199 &rs6000_reg_names[ 7][0], /* r7 */ \ 2200 &rs6000_reg_names[ 8][0], /* r8 */ \ 2201 &rs6000_reg_names[ 9][0], /* r9 */ \ 2202 &rs6000_reg_names[10][0], /* r10 */ \ 2203 &rs6000_reg_names[11][0], /* r11 */ \ 2204 &rs6000_reg_names[12][0], /* r12 */ \ 2205 &rs6000_reg_names[13][0], /* r13 */ \ 2206 &rs6000_reg_names[14][0], /* r14 */ \ 2207 &rs6000_reg_names[15][0], /* r15 */ \ 2208 &rs6000_reg_names[16][0], /* r16 */ \ 2209 &rs6000_reg_names[17][0], /* r17 */ \ 2210 &rs6000_reg_names[18][0], /* r18 */ \ 2211 &rs6000_reg_names[19][0], /* r19 */ \ 2212 &rs6000_reg_names[20][0], /* r20 */ \ 2213 &rs6000_reg_names[21][0], /* r21 */ \ 2214 &rs6000_reg_names[22][0], /* r22 */ \ 2215 &rs6000_reg_names[23][0], /* r23 */ \ 2216 &rs6000_reg_names[24][0], /* r24 */ \ 2217 &rs6000_reg_names[25][0], /* r25 */ \ 2218 &rs6000_reg_names[26][0], /* r26 */ \ 2219 &rs6000_reg_names[27][0], /* r27 */ \ 2220 &rs6000_reg_names[28][0], /* r28 */ \ 2221 &rs6000_reg_names[29][0], /* r29 */ \ 2222 &rs6000_reg_names[30][0], /* r30 */ \ 2223 &rs6000_reg_names[31][0], /* r31 */ \ 2224 \ 2225 &rs6000_reg_names[32][0], /* fr0 */ \ 2226 &rs6000_reg_names[33][0], /* fr1 */ \ 2227 &rs6000_reg_names[34][0], /* fr2 */ \ 2228 &rs6000_reg_names[35][0], /* fr3 */ \ 2229 &rs6000_reg_names[36][0], /* fr4 */ \ 2230 &rs6000_reg_names[37][0], /* fr5 */ \ 2231 &rs6000_reg_names[38][0], /* fr6 */ \ 2232 &rs6000_reg_names[39][0], /* fr7 */ \ 2233 &rs6000_reg_names[40][0], /* fr8 */ \ 2234 &rs6000_reg_names[41][0], /* fr9 */ \ 2235 &rs6000_reg_names[42][0], /* fr10 */ \ 2236 &rs6000_reg_names[43][0], /* fr11 */ \ 2237 &rs6000_reg_names[44][0], /* fr12 */ \ 2238 &rs6000_reg_names[45][0], /* fr13 */ \ 2239 &rs6000_reg_names[46][0], /* fr14 */ \ 2240 &rs6000_reg_names[47][0], /* fr15 */ \ 2241 &rs6000_reg_names[48][0], /* fr16 */ \ 2242 &rs6000_reg_names[49][0], /* fr17 */ \ 2243 &rs6000_reg_names[50][0], /* fr18 */ \ 2244 &rs6000_reg_names[51][0], /* fr19 */ \ 2245 &rs6000_reg_names[52][0], /* fr20 */ \ 2246 &rs6000_reg_names[53][0], /* fr21 */ \ 2247 &rs6000_reg_names[54][0], /* fr22 */ \ 2248 &rs6000_reg_names[55][0], /* fr23 */ \ 2249 &rs6000_reg_names[56][0], /* fr24 */ \ 2250 &rs6000_reg_names[57][0], /* fr25 */ \ 2251 &rs6000_reg_names[58][0], /* fr26 */ \ 2252 &rs6000_reg_names[59][0], /* fr27 */ \ 2253 &rs6000_reg_names[60][0], /* fr28 */ \ 2254 &rs6000_reg_names[61][0], /* fr29 */ \ 2255 &rs6000_reg_names[62][0], /* fr30 */ \ 2256 &rs6000_reg_names[63][0], /* fr31 */ \ 2257 \ 2258 &rs6000_reg_names[64][0], /* mq */ \ 2259 &rs6000_reg_names[65][0], /* lr */ \ 2260 &rs6000_reg_names[66][0], /* ctr */ \ 2261 &rs6000_reg_names[67][0], /* ap */ \ 2262 \ 2263 &rs6000_reg_names[68][0], /* cr0 */ \ 2264 &rs6000_reg_names[69][0], /* cr1 */ \ 2265 &rs6000_reg_names[70][0], /* cr2 */ \ 2266 &rs6000_reg_names[71][0], /* cr3 */ \ 2267 &rs6000_reg_names[72][0], /* cr4 */ \ 2268 &rs6000_reg_names[73][0], /* cr5 */ \ 2269 &rs6000_reg_names[74][0], /* cr6 */ \ 2270 &rs6000_reg_names[75][0], /* cr7 */ \ 2271 \ 2272 &rs6000_reg_names[76][0], /* xer */ \ 2273 \ 2274 &rs6000_reg_names[77][0], /* v0 */ \ 2275 &rs6000_reg_names[78][0], /* v1 */ \ 2276 &rs6000_reg_names[79][0], /* v2 */ \ 2277 &rs6000_reg_names[80][0], /* v3 */ \ 2278 &rs6000_reg_names[81][0], /* v4 */ \ 2279 &rs6000_reg_names[82][0], /* v5 */ \ 2280 &rs6000_reg_names[83][0], /* v6 */ \ 2281 &rs6000_reg_names[84][0], /* v7 */ \ 2282 &rs6000_reg_names[85][0], /* v8 */ \ 2283 &rs6000_reg_names[86][0], /* v9 */ \ 2284 &rs6000_reg_names[87][0], /* v10 */ \ 2285 &rs6000_reg_names[88][0], /* v11 */ \ 2286 &rs6000_reg_names[89][0], /* v12 */ \ 2287 &rs6000_reg_names[90][0], /* v13 */ \ 2288 &rs6000_reg_names[91][0], /* v14 */ \ 2289 &rs6000_reg_names[92][0], /* v15 */ \ 2290 &rs6000_reg_names[93][0], /* v16 */ \ 2291 &rs6000_reg_names[94][0], /* v17 */ \ 2292 &rs6000_reg_names[95][0], /* v18 */ \ 2293 &rs6000_reg_names[96][0], /* v19 */ \ 2294 &rs6000_reg_names[97][0], /* v20 */ \ 2295 &rs6000_reg_names[98][0], /* v21 */ \ 2296 &rs6000_reg_names[99][0], /* v22 */ \ 2297 &rs6000_reg_names[100][0], /* v23 */ \ 2298 &rs6000_reg_names[101][0], /* v24 */ \ 2299 &rs6000_reg_names[102][0], /* v25 */ \ 2300 &rs6000_reg_names[103][0], /* v26 */ \ 2301 &rs6000_reg_names[104][0], /* v27 */ \ 2302 &rs6000_reg_names[105][0], /* v28 */ \ 2303 &rs6000_reg_names[106][0], /* v29 */ \ 2304 &rs6000_reg_names[107][0], /* v30 */ \ 2305 &rs6000_reg_names[108][0], /* v31 */ \ 2306 &rs6000_reg_names[109][0], /* vrsave */ \ 2307 &rs6000_reg_names[110][0], /* vscr */ \ 2308 &rs6000_reg_names[111][0], /* spe_acc */ \ 2309 &rs6000_reg_names[112][0], /* spefscr */ \ 2310 &rs6000_reg_names[113][0], /* sfp */ \ 2311 } 2312 2313 /* Table of additional register names to use in user input. */ 2314 2315 #define ADDITIONAL_REGISTER_NAMES \ 2316 {{"r0", 0}, {"r1", 1}, {"r2", 2}, {"r3", 3}, \ 2317 {"r4", 4}, {"r5", 5}, {"r6", 6}, {"r7", 7}, \ 2318 {"r8", 8}, {"r9", 9}, {"r10", 10}, {"r11", 11}, \ 2319 {"r12", 12}, {"r13", 13}, {"r14", 14}, {"r15", 15}, \ 2320 {"r16", 16}, {"r17", 17}, {"r18", 18}, {"r19", 19}, \ 2321 {"r20", 20}, {"r21", 21}, {"r22", 22}, {"r23", 23}, \ 2322 {"r24", 24}, {"r25", 25}, {"r26", 26}, {"r27", 27}, \ 2323 {"r28", 28}, {"r29", 29}, {"r30", 30}, {"r31", 31}, \ 2324 {"fr0", 32}, {"fr1", 33}, {"fr2", 34}, {"fr3", 35}, \ 2325 {"fr4", 36}, {"fr5", 37}, {"fr6", 38}, {"fr7", 39}, \ 2326 {"fr8", 40}, {"fr9", 41}, {"fr10", 42}, {"fr11", 43}, \ 2327 {"fr12", 44}, {"fr13", 45}, {"fr14", 46}, {"fr15", 47}, \ 2328 {"fr16", 48}, {"fr17", 49}, {"fr18", 50}, {"fr19", 51}, \ 2329 {"fr20", 52}, {"fr21", 53}, {"fr22", 54}, {"fr23", 55}, \ 2330 {"fr24", 56}, {"fr25", 57}, {"fr26", 58}, {"fr27", 59}, \ 2331 {"fr28", 60}, {"fr29", 61}, {"fr30", 62}, {"fr31", 63}, \ 2332 {"v0", 77}, {"v1", 78}, {"v2", 79}, {"v3", 80}, \ 2333 {"v4", 81}, {"v5", 82}, {"v6", 83}, {"v7", 84}, \ 2334 {"v8", 85}, {"v9", 86}, {"v10", 87}, {"v11", 88}, \ 2335 {"v12", 89}, {"v13", 90}, {"v14", 91}, {"v15", 92}, \ 2336 {"v16", 93}, {"v17", 94}, {"v18", 95}, {"v19", 96}, \ 2337 {"v20", 97}, {"v21", 98}, {"v22", 99}, {"v23", 100}, \ 2338 {"v24", 101},{"v25", 102},{"v26", 103},{"v27", 104}, \ 2339 {"v28", 105},{"v29", 106},{"v30", 107},{"v31", 108}, \ 2340 {"vrsave", 109}, {"vscr", 110}, \ 2341 {"spe_acc", 111}, {"spefscr", 112}, \ 2342 /* no additional names for: mq, lr, ctr, ap */ \ 2343 {"cr0", 68}, {"cr1", 69}, {"cr2", 70}, {"cr3", 71}, \ 2344 {"cr4", 72}, {"cr5", 73}, {"cr6", 74}, {"cr7", 75}, \ 2345 {"cc", 68}, {"sp", 1}, {"toc", 2}, \ 2346 /* VSX registers overlaid on top of FR, Altivec registers */ \ 2347 {"vs0", 32}, {"vs1", 33}, {"vs2", 34}, {"vs3", 35}, \ 2348 {"vs4", 36}, {"vs5", 37}, {"vs6", 38}, {"vs7", 39}, \ 2349 {"vs8", 40}, {"vs9", 41}, {"vs10", 42}, {"vs11", 43}, \ 2350 {"vs12", 44}, {"vs13", 45}, {"vs14", 46}, {"vs15", 47}, \ 2351 {"vs16", 48}, {"vs17", 49}, {"vs18", 50}, {"vs19", 51}, \ 2352 {"vs20", 52}, {"vs21", 53}, {"vs22", 54}, {"vs23", 55}, \ 2353 {"vs24", 56}, {"vs25", 57}, {"vs26", 58}, {"vs27", 59}, \ 2354 {"vs28", 60}, {"vs29", 61}, {"vs30", 62}, {"vs31", 63}, \ 2355 {"vs32", 77}, {"vs33", 78}, {"vs34", 79}, {"vs35", 80}, \ 2356 {"vs36", 81}, {"vs37", 82}, {"vs38", 83}, {"vs39", 84}, \ 2357 {"vs40", 85}, {"vs41", 86}, {"vs42", 87}, {"vs43", 88}, \ 2358 {"vs44", 89}, {"vs45", 90}, {"vs46", 91}, {"vs47", 92}, \ 2359 {"vs48", 93}, {"vs49", 94}, {"vs50", 95}, {"vs51", 96}, \ 2360 {"vs52", 97}, {"vs53", 98}, {"vs54", 99}, {"vs55", 100}, \ 2361 {"vs56", 101},{"vs57", 102},{"vs58", 103},{"vs59", 104}, \ 2362 {"vs60", 105},{"vs61", 106},{"vs62", 107},{"vs63", 108} } 2363 2364 /* Text to write out after a CALL that may be replaced by glue code by 2365 the loader. This depends on the AIX version. */ 2366 #define RS6000_CALL_GLUE "cror 31,31,31" 2367 2368 /* This is how to output an element of a case-vector that is relative. */ 2369 2370 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 2371 do { char buf[100]; \ 2372 fputs ("\t.long ", FILE); \ 2373 ASM_GENERATE_INTERNAL_LABEL (buf, "L", VALUE); \ 2374 assemble_name (FILE, buf); \ 2375 putc ('-', FILE); \ 2376 ASM_GENERATE_INTERNAL_LABEL (buf, "L", REL); \ 2377 assemble_name (FILE, buf); \ 2378 putc ('\n', FILE); \ 2379 } while (0) 2380 2381 /* This is how to output an assembler line 2382 that says to advance the location counter 2383 to a multiple of 2**LOG bytes. */ 2384 2385 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 2386 if ((LOG) != 0) \ 2387 fprintf (FILE, "\t.align %d\n", (LOG)) 2388 2389 /* Pick up the return address upon entry to a procedure. Used for 2390 dwarf2 unwind information. This also enables the table driven 2391 mechanism. */ 2392 2393 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNO) 2394 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNO) 2395 2396 /* Describe how we implement __builtin_eh_return. */ 2397 #define EH_RETURN_DATA_REGNO(N) ((N) < 4 ? (N) + 3 : INVALID_REGNUM) 2398 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 10) 2399 2400 /* Print operand X (an rtx) in assembler syntax to file FILE. 2401 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2402 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2403 2404 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 2405 2406 /* Define which CODE values are valid. */ 2407 2408 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2409 ((CODE) == '.' || (CODE) == '&') 2410 2411 /* Print a memory address as an operand to reference that memory location. */ 2412 2413 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 2414 2415 #define OUTPUT_ADDR_CONST_EXTRA(STREAM, X, FAIL) \ 2416 do \ 2417 if (!rs6000_output_addr_const_extra (STREAM, X)) \ 2418 goto FAIL; \ 2419 while (0) 2420 2421 /* uncomment for disabling the corresponding default options */ 2422 /* #define MACHINE_no_sched_interblock */ 2423 /* #define MACHINE_no_sched_speculative */ 2424 /* #define MACHINE_no_sched_speculative_load */ 2425 2426 /* General flags. */ 2427 extern int flag_pic; 2428 extern int optimize; 2429 extern int flag_expensive_optimizations; 2430 extern int frame_pointer_needed; 2431 2432 /* Classification of the builtin functions to properly set the declaration tree 2433 flags. */ 2434 enum rs6000_btc 2435 { 2436 RS6000_BTC_MISC, /* assume builtin can do anything */ 2437 RS6000_BTC_CONST, /* builtin is a 'const' function. */ 2438 RS6000_BTC_PURE, /* builtin is a 'pure' function. */ 2439 RS6000_BTC_FP_PURE /* builtin is 'pure' if rounding math. */ 2440 }; 2441 2442 /* Convenience macros to document the instruction type. */ 2443 #define RS6000_BTC_MEM RS6000_BTC_MISC /* load/store touches memory */ 2444 #define RS6000_BTC_SAT RS6000_BTC_MISC /* VMX saturate sets VSCR register */ 2445 2446 #undef RS6000_BUILTIN 2447 #undef RS6000_BUILTIN_EQUATE 2448 #define RS6000_BUILTIN(NAME, TYPE) NAME, 2449 #define RS6000_BUILTIN_EQUATE(NAME, VALUE) NAME = VALUE, 2450 2451 enum rs6000_builtins 2452 { 2453 #include "rs6000-builtin.def" 2454 2455 RS6000_BUILTIN_COUNT 2456 }; 2457 2458 #undef RS6000_BUILTIN 2459 #undef RS6000_BUILTIN_EQUATE 2460 2461 enum rs6000_builtin_type_index 2462 { 2463 RS6000_BTI_NOT_OPAQUE, 2464 RS6000_BTI_opaque_V2SI, 2465 RS6000_BTI_opaque_V2SF, 2466 RS6000_BTI_opaque_p_V2SI, 2467 RS6000_BTI_opaque_V4SI, 2468 RS6000_BTI_V16QI, 2469 RS6000_BTI_V2SI, 2470 RS6000_BTI_V2SF, 2471 RS6000_BTI_V2DI, 2472 RS6000_BTI_V2DF, 2473 RS6000_BTI_V4HI, 2474 RS6000_BTI_V4SI, 2475 RS6000_BTI_V4SF, 2476 RS6000_BTI_V8HI, 2477 RS6000_BTI_unsigned_V16QI, 2478 RS6000_BTI_unsigned_V8HI, 2479 RS6000_BTI_unsigned_V4SI, 2480 RS6000_BTI_unsigned_V2DI, 2481 RS6000_BTI_bool_char, /* __bool char */ 2482 RS6000_BTI_bool_short, /* __bool short */ 2483 RS6000_BTI_bool_int, /* __bool int */ 2484 RS6000_BTI_bool_long, /* __bool long */ 2485 RS6000_BTI_pixel, /* __pixel */ 2486 RS6000_BTI_bool_V16QI, /* __vector __bool char */ 2487 RS6000_BTI_bool_V8HI, /* __vector __bool short */ 2488 RS6000_BTI_bool_V4SI, /* __vector __bool int */ 2489 RS6000_BTI_bool_V2DI, /* __vector __bool long */ 2490 RS6000_BTI_pixel_V8HI, /* __vector __pixel */ 2491 RS6000_BTI_long, /* long_integer_type_node */ 2492 RS6000_BTI_unsigned_long, /* long_unsigned_type_node */ 2493 RS6000_BTI_long_long, /* long_long_integer_type_node */ 2494 RS6000_BTI_unsigned_long_long, /* long_long_unsigned_type_node */ 2495 RS6000_BTI_INTQI, /* intQI_type_node */ 2496 RS6000_BTI_UINTQI, /* unsigned_intQI_type_node */ 2497 RS6000_BTI_INTHI, /* intHI_type_node */ 2498 RS6000_BTI_UINTHI, /* unsigned_intHI_type_node */ 2499 RS6000_BTI_INTSI, /* intSI_type_node */ 2500 RS6000_BTI_UINTSI, /* unsigned_intSI_type_node */ 2501 RS6000_BTI_INTDI, /* intDI_type_node */ 2502 RS6000_BTI_UINTDI, /* unsigned_intDI_type_node */ 2503 RS6000_BTI_float, /* float_type_node */ 2504 RS6000_BTI_double, /* double_type_node */ 2505 RS6000_BTI_void, /* void_type_node */ 2506 RS6000_BTI_MAX 2507 }; 2508 2509 2510 #define opaque_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SI]) 2511 #define opaque_V2SF_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V2SF]) 2512 #define opaque_p_V2SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_p_V2SI]) 2513 #define opaque_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_opaque_V4SI]) 2514 #define V16QI_type_node (rs6000_builtin_types[RS6000_BTI_V16QI]) 2515 #define V2DI_type_node (rs6000_builtin_types[RS6000_BTI_V2DI]) 2516 #define V2DF_type_node (rs6000_builtin_types[RS6000_BTI_V2DF]) 2517 #define V2SI_type_node (rs6000_builtin_types[RS6000_BTI_V2SI]) 2518 #define V2SF_type_node (rs6000_builtin_types[RS6000_BTI_V2SF]) 2519 #define V4HI_type_node (rs6000_builtin_types[RS6000_BTI_V4HI]) 2520 #define V4SI_type_node (rs6000_builtin_types[RS6000_BTI_V4SI]) 2521 #define V4SF_type_node (rs6000_builtin_types[RS6000_BTI_V4SF]) 2522 #define V8HI_type_node (rs6000_builtin_types[RS6000_BTI_V8HI]) 2523 #define unsigned_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V16QI]) 2524 #define unsigned_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V8HI]) 2525 #define unsigned_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V4SI]) 2526 #define unsigned_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_unsigned_V2DI]) 2527 #define bool_char_type_node (rs6000_builtin_types[RS6000_BTI_bool_char]) 2528 #define bool_short_type_node (rs6000_builtin_types[RS6000_BTI_bool_short]) 2529 #define bool_int_type_node (rs6000_builtin_types[RS6000_BTI_bool_int]) 2530 #define bool_long_type_node (rs6000_builtin_types[RS6000_BTI_bool_long]) 2531 #define pixel_type_node (rs6000_builtin_types[RS6000_BTI_pixel]) 2532 #define bool_V16QI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V16QI]) 2533 #define bool_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V8HI]) 2534 #define bool_V4SI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V4SI]) 2535 #define bool_V2DI_type_node (rs6000_builtin_types[RS6000_BTI_bool_V2DI]) 2536 #define pixel_V8HI_type_node (rs6000_builtin_types[RS6000_BTI_pixel_V8HI]) 2537 2538 #define long_long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long_long]) 2539 #define long_long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long_long]) 2540 #define long_integer_type_internal_node (rs6000_builtin_types[RS6000_BTI_long]) 2541 #define long_unsigned_type_internal_node (rs6000_builtin_types[RS6000_BTI_unsigned_long]) 2542 #define intQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTQI]) 2543 #define uintQI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTQI]) 2544 #define intHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTHI]) 2545 #define uintHI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTHI]) 2546 #define intSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTSI]) 2547 #define uintSI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTSI]) 2548 #define intDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_INTDI]) 2549 #define uintDI_type_internal_node (rs6000_builtin_types[RS6000_BTI_UINTDI]) 2550 #define float_type_internal_node (rs6000_builtin_types[RS6000_BTI_float]) 2551 #define double_type_internal_node (rs6000_builtin_types[RS6000_BTI_double]) 2552 #define void_type_internal_node (rs6000_builtin_types[RS6000_BTI_void]) 2553 2554 extern GTY(()) tree rs6000_builtin_types[RS6000_BTI_MAX]; 2555 extern GTY(()) tree rs6000_builtin_decls[RS6000_BUILTIN_COUNT]; 2556 2557