1 /* Subroutines for the C front end on the PowerPC architecture. 2 Copyright (C) 2002-2019 Free Software Foundation, Inc. 3 4 Contributed by Zack Weinberg <zack@codesourcery.com> 5 and Paolo Bonzini <bonzini@gnu.org> 6 7 This file is part of GCC. 8 9 GCC is free software; you can redistribute it and/or modify it 10 under the terms of the GNU General Public License as published 11 by the Free Software Foundation; either version 3, or (at your 12 option) any later version. 13 14 GCC is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with GCC; see the file COPYING3. If not see 21 <http://www.gnu.org/licenses/>. */ 22 23 #define IN_TARGET_CODE 1 24 25 #include "config.h" 26 #include "system.h" 27 #include "coretypes.h" 28 #include "target.h" 29 #include "c-family/c-common.h" 30 #include "memmodel.h" 31 #include "tm_p.h" 32 #include "stringpool.h" 33 #include "stor-layout.h" 34 #include "c-family/c-pragma.h" 35 #include "langhooks.h" 36 #include "c/c-tree.h" 37 38 39 40 /* Handle the machine specific pragma longcall. Its syntax is 41 42 # pragma longcall ( TOGGLE ) 43 44 where TOGGLE is either 0 or 1. 45 46 rs6000_default_long_calls is set to the value of TOGGLE, changing 47 whether or not new function declarations receive a longcall 48 attribute by default. */ 49 50 #define SYNTAX_ERROR(gmsgid) do { \ 51 warning (OPT_Wpragmas, gmsgid); \ 52 warning (OPT_Wpragmas, "ignoring malformed #pragma longcall"); \ 53 return; \ 54 } while (0) 55 56 void 57 rs6000_pragma_longcall (cpp_reader *pfile ATTRIBUTE_UNUSED) 58 { 59 tree x, n; 60 61 /* If we get here, generic code has already scanned the directive 62 leader and the word "longcall". */ 63 64 if (pragma_lex (&x) != CPP_OPEN_PAREN) 65 SYNTAX_ERROR ("missing open paren"); 66 if (pragma_lex (&n) != CPP_NUMBER) 67 SYNTAX_ERROR ("missing number"); 68 if (pragma_lex (&x) != CPP_CLOSE_PAREN) 69 SYNTAX_ERROR ("missing close paren"); 70 71 if (n != integer_zero_node && n != integer_one_node) 72 SYNTAX_ERROR ("number must be 0 or 1"); 73 74 if (pragma_lex (&x) != CPP_EOF) 75 warning (OPT_Wpragmas, "junk at end of #pragma longcall"); 76 77 rs6000_default_long_calls = (n == integer_one_node); 78 } 79 80 /* Handle defining many CPP flags based on TARGET_xxx. As a general 81 policy, rather than trying to guess what flags a user might want a 82 #define for, it's better to define a flag for everything. */ 83 84 #define builtin_define(TXT) cpp_define (pfile, TXT) 85 #define builtin_assert(TXT) cpp_assert (pfile, TXT) 86 87 /* Keep the AltiVec keywords handy for fast comparisons. */ 88 static GTY(()) tree __vector_keyword; 89 static GTY(()) tree vector_keyword; 90 static GTY(()) tree __pixel_keyword; 91 static GTY(()) tree pixel_keyword; 92 static GTY(()) tree __bool_keyword; 93 static GTY(()) tree bool_keyword; 94 static GTY(()) tree _Bool_keyword; 95 static GTY(()) tree __int128_type; 96 static GTY(()) tree __uint128_type; 97 98 /* Preserved across calls. */ 99 static tree expand_bool_pixel; 100 101 static cpp_hashnode * 102 altivec_categorize_keyword (const cpp_token *tok) 103 { 104 if (tok->type == CPP_NAME) 105 { 106 cpp_hashnode *ident = tok->val.node.node; 107 108 if (ident == C_CPP_HASHNODE (vector_keyword)) 109 return C_CPP_HASHNODE (__vector_keyword); 110 111 if (ident == C_CPP_HASHNODE (pixel_keyword)) 112 return C_CPP_HASHNODE (__pixel_keyword); 113 114 if (ident == C_CPP_HASHNODE (bool_keyword)) 115 return C_CPP_HASHNODE (__bool_keyword); 116 117 if (ident == C_CPP_HASHNODE (_Bool_keyword)) 118 return C_CPP_HASHNODE (__bool_keyword); 119 120 return ident; 121 } 122 123 return 0; 124 } 125 126 static void 127 init_vector_keywords (void) 128 { 129 /* Keywords without two leading underscores are context-sensitive, and hence 130 implemented as conditional macros, controlled by the 131 rs6000_macro_to_expand() function below. If we have ISA 2.07 64-bit 132 support, record the __int128_t and __uint128_t types. */ 133 134 __vector_keyword = get_identifier ("__vector"); 135 C_CPP_HASHNODE (__vector_keyword)->flags |= NODE_CONDITIONAL; 136 137 __pixel_keyword = get_identifier ("__pixel"); 138 C_CPP_HASHNODE (__pixel_keyword)->flags |= NODE_CONDITIONAL; 139 140 __bool_keyword = get_identifier ("__bool"); 141 C_CPP_HASHNODE (__bool_keyword)->flags |= NODE_CONDITIONAL; 142 143 vector_keyword = get_identifier ("vector"); 144 C_CPP_HASHNODE (vector_keyword)->flags |= NODE_CONDITIONAL; 145 146 pixel_keyword = get_identifier ("pixel"); 147 C_CPP_HASHNODE (pixel_keyword)->flags |= NODE_CONDITIONAL; 148 149 bool_keyword = get_identifier ("bool"); 150 C_CPP_HASHNODE (bool_keyword)->flags |= NODE_CONDITIONAL; 151 152 _Bool_keyword = get_identifier ("_Bool"); 153 C_CPP_HASHNODE (_Bool_keyword)->flags |= NODE_CONDITIONAL; 154 155 if (TARGET_VADDUQM) 156 { 157 __int128_type = get_identifier ("__int128_t"); 158 __uint128_type = get_identifier ("__uint128_t"); 159 } 160 } 161 162 /* Helper function to find out which RID_INT_N_* code is the one for 163 __int128, if any. Returns RID_MAX+1 if none apply, which is safe 164 (for our purposes, since we always expect to have __int128) to 165 compare against. */ 166 static int 167 rid_int128(void) 168 { 169 int i; 170 171 for (i = 0; i < NUM_INT_N_ENTS; i ++) 172 if (int_n_enabled_p[i] 173 && int_n_data[i].bitsize == 128) 174 return RID_INT_N_0 + i; 175 176 return RID_MAX + 1; 177 } 178 179 /* Called to decide whether a conditional macro should be expanded. 180 Since we have exactly one such macro (i.e, 'vector'), we do not 181 need to examine the 'tok' parameter. */ 182 183 static cpp_hashnode * 184 rs6000_macro_to_expand (cpp_reader *pfile, const cpp_token *tok) 185 { 186 cpp_hashnode *expand_this = tok->val.node.node; 187 cpp_hashnode *ident; 188 189 /* If the current machine does not have altivec, don't look for the 190 keywords. */ 191 if (!TARGET_ALTIVEC) 192 return NULL; 193 194 ident = altivec_categorize_keyword (tok); 195 196 if (ident != expand_this) 197 expand_this = NULL; 198 199 if (ident == C_CPP_HASHNODE (__vector_keyword)) 200 { 201 int idx = 0; 202 do 203 tok = cpp_peek_token (pfile, idx++); 204 while (tok->type == CPP_PADDING); 205 ident = altivec_categorize_keyword (tok); 206 207 if (ident == C_CPP_HASHNODE (__pixel_keyword)) 208 { 209 expand_this = C_CPP_HASHNODE (__vector_keyword); 210 expand_bool_pixel = __pixel_keyword; 211 } 212 else if (ident == C_CPP_HASHNODE (__bool_keyword)) 213 { 214 expand_this = C_CPP_HASHNODE (__vector_keyword); 215 expand_bool_pixel = __bool_keyword; 216 } 217 /* The boost libraries have code with Iterator::vector vector in it. If 218 we allow the normal handling, this module will be called recursively, 219 and the vector will be skipped.; */ 220 else if (ident && (ident != C_CPP_HASHNODE (__vector_keyword))) 221 { 222 enum rid rid_code = (enum rid)(ident->rid_code); 223 bool is_macro = cpp_macro_p (ident); 224 225 /* If there is a function-like macro, check if it is going to be 226 invoked with or without arguments. Without following ( treat 227 it like non-macro, otherwise the following cpp_get_token eats 228 what should be preserved. */ 229 if (is_macro && cpp_fun_like_macro_p (ident)) 230 { 231 int idx2 = idx; 232 do 233 tok = cpp_peek_token (pfile, idx2++); 234 while (tok->type == CPP_PADDING); 235 if (tok->type != CPP_OPEN_PAREN) 236 is_macro = false; 237 } 238 239 if (is_macro) 240 { 241 do 242 (void) cpp_get_token (pfile); 243 while (--idx > 0); 244 do 245 tok = cpp_peek_token (pfile, idx++); 246 while (tok->type == CPP_PADDING); 247 ident = altivec_categorize_keyword (tok); 248 if (ident == C_CPP_HASHNODE (__pixel_keyword)) 249 { 250 expand_this = C_CPP_HASHNODE (__vector_keyword); 251 expand_bool_pixel = __pixel_keyword; 252 rid_code = RID_MAX; 253 } 254 else if (ident == C_CPP_HASHNODE (__bool_keyword)) 255 { 256 expand_this = C_CPP_HASHNODE (__vector_keyword); 257 expand_bool_pixel = __bool_keyword; 258 rid_code = RID_MAX; 259 } 260 else if (ident) 261 rid_code = (enum rid)(ident->rid_code); 262 } 263 264 if (rid_code == RID_UNSIGNED || rid_code == RID_LONG 265 || rid_code == RID_SHORT || rid_code == RID_SIGNED 266 || rid_code == RID_INT || rid_code == RID_CHAR 267 || rid_code == RID_FLOAT 268 || (rid_code == RID_DOUBLE && TARGET_VSX) 269 || (rid_code == rid_int128 () && TARGET_VADDUQM)) 270 { 271 expand_this = C_CPP_HASHNODE (__vector_keyword); 272 /* If the next keyword is bool or pixel, it 273 will need to be expanded as well. */ 274 do 275 tok = cpp_peek_token (pfile, idx++); 276 while (tok->type == CPP_PADDING); 277 ident = altivec_categorize_keyword (tok); 278 279 if (ident == C_CPP_HASHNODE (__pixel_keyword)) 280 expand_bool_pixel = __pixel_keyword; 281 else if (ident == C_CPP_HASHNODE (__bool_keyword)) 282 expand_bool_pixel = __bool_keyword; 283 else 284 { 285 /* Try two tokens down, too. */ 286 do 287 tok = cpp_peek_token (pfile, idx++); 288 while (tok->type == CPP_PADDING); 289 ident = altivec_categorize_keyword (tok); 290 if (ident == C_CPP_HASHNODE (__pixel_keyword)) 291 expand_bool_pixel = __pixel_keyword; 292 else if (ident == C_CPP_HASHNODE (__bool_keyword)) 293 expand_bool_pixel = __bool_keyword; 294 } 295 } 296 297 /* Support vector __int128_t, but we don't need to worry about bool 298 or pixel on this type. */ 299 else if (TARGET_VADDUQM 300 && (ident == C_CPP_HASHNODE (__int128_type) 301 || ident == C_CPP_HASHNODE (__uint128_type))) 302 expand_this = C_CPP_HASHNODE (__vector_keyword); 303 } 304 } 305 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__pixel_keyword)) 306 { 307 expand_this = C_CPP_HASHNODE (__pixel_keyword); 308 expand_bool_pixel = 0; 309 } 310 else if (expand_bool_pixel && ident == C_CPP_HASHNODE (__bool_keyword)) 311 { 312 expand_this = C_CPP_HASHNODE (__bool_keyword); 313 expand_bool_pixel = 0; 314 } 315 316 return expand_this; 317 } 318 319 320 /* Define or undefine a single macro. */ 321 322 static void 323 rs6000_define_or_undefine_macro (bool define_p, const char *name) 324 { 325 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) 326 fprintf (stderr, "#%s %s\n", (define_p) ? "define" : "undef", name); 327 328 if (define_p) 329 cpp_define (parse_in, name); 330 else 331 cpp_undef (parse_in, name); 332 } 333 334 /* Define or undefine macros based on the current target. If the user does 335 #pragma GCC target, we need to adjust the macros dynamically. Note, some of 336 the options needed for builtins have been moved to separate variables, so 337 have both the target flags and the builtin flags as arguments. */ 338 339 void 340 rs6000_target_modify_macros (bool define_p, HOST_WIDE_INT flags, 341 HOST_WIDE_INT bu_mask) 342 { 343 if (TARGET_DEBUG_BUILTIN || TARGET_DEBUG_TARGET) 344 fprintf (stderr, 345 "rs6000_target_modify_macros (%s, " HOST_WIDE_INT_PRINT_HEX 346 ", " HOST_WIDE_INT_PRINT_HEX ")\n", 347 (define_p) ? "define" : "undef", 348 flags, bu_mask); 349 350 /* Each of the flags mentioned below controls whether certain 351 preprocessor macros will be automatically defined when 352 preprocessing source files for compilation by this compiler. 353 While most of these flags can be enabled or disabled 354 explicitly by specifying certain command-line options when 355 invoking the compiler, there are also many ways in which these 356 flags are enabled or disabled implicitly, based on compiler 357 defaults, configuration choices, and on the presence of certain 358 related command-line options. Many, but not all, of these 359 implicit behaviors can be found in file "rs6000.c", the 360 rs6000_option_override_internal() function. 361 362 In general, each of the flags may be automatically enabled in 363 any of the following conditions: 364 365 1. If no -mcpu target is specified on the command line and no 366 --with-cpu target is specified to the configure command line 367 and the TARGET_DEFAULT macro for this default cpu host 368 includes the flag, and the flag has not been explicitly disabled 369 by command-line options. 370 371 2. If the target specified with -mcpu=target on the command line, or 372 in the absence of a -mcpu=target command-line option, if the 373 target specified using --with-cpu=target on the configure 374 command line, is disqualified because the associated binary 375 tools (e.g. the assembler) lack support for the requested cpu, 376 and the TARGET_DEFAULT macro for this default cpu host 377 includes the flag, and the flag has not been explicitly disabled 378 by command-line options. 379 380 3. If either of the above two conditions apply except that the 381 TARGET_DEFAULT macro is defined to equal zero, and 382 TARGET_POWERPC64 and 383 a) BYTES_BIG_ENDIAN and the flag to be enabled is either 384 MASK_PPC_GFXOPT or MASK_POWERPC64 (flags for "powerpc64" 385 target), or 386 b) !BYTES_BIG_ENDIAN and the flag to be enabled is either 387 MASK_POWERPC64 or it is one of the flags included in 388 ISA_2_7_MASKS_SERVER (flags for "powerpc64le" target). 389 390 4. If a cpu has been requested with a -mcpu=target command-line option 391 and this cpu has not been disqualified due to shortcomings of the 392 binary tools, and the set of flags associated with the requested cpu 393 include the flag to be enabled. See rs6000-cpus.def for macro 394 definitions that represent various ABI standards 395 (e.g. ISA_2_1_MASKS, ISA_3_0_MASKS_SERVER) and for a list of 396 the specific flags that are associated with each of the cpu 397 choices that can be specified as the target of a -mcpu=target 398 compile option, or as the the target of a --with-cpu=target 399 configure option. Target flags that are specified in either 400 of these two ways are considered "implicit" since the flags 401 are not mentioned specifically by name. 402 403 Additional documentation describing behavior specific to 404 particular flags is provided below, immediately preceding the 405 use of each relevant flag. 406 407 5. If there is no -mcpu=target command-line option, and the cpu 408 requested by a --with-cpu=target command-line option has not 409 been disqualified due to shortcomings of the binary tools, and 410 the set of flags associated with the specified target include 411 the flag to be enabled. See the notes immediately above for a 412 summary of the flags associated with particular cpu 413 definitions. */ 414 415 /* rs6000_isa_flags based options. */ 416 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC"); 417 if ((flags & OPTION_MASK_PPC_GPOPT) != 0) 418 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCSQ"); 419 if ((flags & OPTION_MASK_PPC_GFXOPT) != 0) 420 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPCGR"); 421 if ((flags & OPTION_MASK_POWERPC64) != 0) 422 rs6000_define_or_undefine_macro (define_p, "_ARCH_PPC64"); 423 if ((flags & OPTION_MASK_MFCRF) != 0) 424 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR4"); 425 if ((flags & OPTION_MASK_POPCNTB) != 0) 426 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5"); 427 if ((flags & OPTION_MASK_FPRND) != 0) 428 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR5X"); 429 if ((flags & OPTION_MASK_CMPB) != 0) 430 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6"); 431 if ((flags & OPTION_MASK_MFPGPR) != 0) 432 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR6X"); 433 if ((flags & OPTION_MASK_POPCNTD) != 0) 434 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR7"); 435 /* Note that the OPTION_MASK_DIRECT_MOVE flag is automatically 436 turned on in the following condition: 437 1. TARGET_P8_VECTOR is enabled and OPTION_MASK_DIRECT_MOVE is not 438 explicitly disabled. 439 Hereafter, the OPTION_MASK_DIRECT_MOVE flag is considered to 440 have been turned on explicitly. 441 Note that the OPTION_MASK_DIRECT_MOVE flag is automatically 442 turned off in any of the following conditions: 443 1. TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX is explicitly 444 disabled and OPTION_MASK_DIRECT_MOVE was not explicitly 445 enabled. 446 2. TARGET_VSX is off. */ 447 if ((flags & OPTION_MASK_DIRECT_MOVE) != 0) 448 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR8"); 449 if ((flags & OPTION_MASK_MODULO) != 0) 450 rs6000_define_or_undefine_macro (define_p, "_ARCH_PWR9"); 451 if ((flags & OPTION_MASK_SOFT_FLOAT) != 0) 452 rs6000_define_or_undefine_macro (define_p, "_SOFT_FLOAT"); 453 if ((flags & OPTION_MASK_RECIP_PRECISION) != 0) 454 rs6000_define_or_undefine_macro (define_p, "__RECIP_PRECISION__"); 455 /* Note that the OPTION_MASK_ALTIVEC flag is automatically turned on 456 in any of the following conditions: 457 1. The operating system is Darwin and it is configured for 64 458 bit. (See darwin_rs6000_override_options.) 459 2. The operating system is Darwin and the operating system 460 version is 10.5 or higher and the user has not explicitly 461 disabled ALTIVEC by specifying -mcpu=G3 or -mno-altivec and 462 the compiler is not producing code for integration within the 463 kernel. (See darwin_rs6000_override_options.) 464 Note that the OPTION_MASK_ALTIVEC flag is automatically turned 465 off in any of the following conditions: 466 1. The operating system does not support saving of AltiVec 467 registers (OS_MISSING_ALTIVEC). 468 2. If an inner context (as introduced by 469 __attribute__((__target__())) or #pragma GCC target() 470 requests a target that normally enables the 471 OPTION_MASK_ALTIVEC flag but the outer-most "main target" 472 does not support the rs6000_altivec_abi, this flag is 473 turned off for the inner context unless OPTION_MASK_ALTIVEC 474 was explicitly enabled for the inner context. */ 475 if ((flags & OPTION_MASK_ALTIVEC) != 0) 476 { 477 const char *vec_str = (define_p) ? "__VEC__=10206" : "__VEC__"; 478 rs6000_define_or_undefine_macro (define_p, "__ALTIVEC__"); 479 rs6000_define_or_undefine_macro (define_p, vec_str); 480 481 /* Define this when supporting context-sensitive keywords. */ 482 if (!flag_iso) 483 rs6000_define_or_undefine_macro (define_p, "__APPLE_ALTIVEC__"); 484 } 485 /* Note that the OPTION_MASK_VSX flag is automatically turned on in 486 the following conditions: 487 1. TARGET_P8_VECTOR is explicitly turned on and the OPTION_MASK_VSX 488 was not explicitly turned off. Hereafter, the OPTION_MASK_VSX 489 flag is considered to have been explicitly turned on. 490 Note that the OPTION_MASK_VSX flag is automatically turned off in 491 the following conditions: 492 1. The operating system does not support saving of AltiVec 493 registers (OS_MISSING_ALTIVEC). 494 2. If the option TARGET_HARD_FLOAT is turned off. Hereafter, the 495 OPTION_MASK_VSX flag is considered to have been turned off 496 explicitly. 497 3. If TARGET_AVOID_XFORM is turned on explicitly at the outermost 498 compilation context, or if it is turned on by any means in an 499 inner compilation context. Hereafter, the OPTION_MASK_VSX 500 flag is considered to have been turned off explicitly. 501 4. If TARGET_ALTIVEC was explicitly disabled. Hereafter, the 502 OPTION_MASK_VSX flag is considered to have been turned off 503 explicitly. 504 5. If an inner context (as introduced by 505 __attribute__((__target__())) or #pragma GCC target() 506 requests a target that normally enables the 507 OPTION_MASK_VSX flag but the outer-most "main target" 508 does not support the rs6000_altivec_abi, this flag is 509 turned off for the inner context unless OPTION_MASK_VSX 510 was explicitly enabled for the inner context. */ 511 if ((flags & OPTION_MASK_VSX) != 0) 512 rs6000_define_or_undefine_macro (define_p, "__VSX__"); 513 if ((flags & OPTION_MASK_HTM) != 0) 514 { 515 rs6000_define_or_undefine_macro (define_p, "__HTM__"); 516 /* Tell the user that our HTM insn patterns act as memory barriers. */ 517 rs6000_define_or_undefine_macro (define_p, "__TM_FENCE__"); 518 } 519 /* Note that the OPTION_MASK_P8_VECTOR flag is automatically turned 520 on in the following conditions: 521 1. TARGET_P9_VECTOR is explicitly turned on and 522 OPTION_MASK_P8_VECTOR is not explicitly turned off. 523 Hereafter, the OPTION_MASK_P8_VECTOR flag is considered to 524 have been turned off explicitly. 525 Note that the OPTION_MASK_P8_VECTOR flag is automatically turned 526 off in the following conditions: 527 1. If any of TARGET_HARD_FLOAT, TARGET_ALTIVEC, or TARGET_VSX 528 were turned off explicitly and OPTION_MASK_P8_VECTOR flag was 529 not turned on explicitly. 530 2. If TARGET_ALTIVEC is turned off. Hereafter, the 531 OPTION_MASK_P8_VECTOR flag is considered to have been turned off 532 explicitly. 533 3. If TARGET_VSX is turned off and OPTION_MASK_P8_VECTOR was not 534 explicitly enabled. If TARGET_VSX is explicitly enabled, the 535 OPTION_MASK_P8_VECTOR flag is hereafter also considered to 536 have been turned off explicitly. */ 537 if ((flags & OPTION_MASK_P8_VECTOR) != 0) 538 rs6000_define_or_undefine_macro (define_p, "__POWER8_VECTOR__"); 539 /* Note that the OPTION_MASK_P9_VECTOR flag is automatically turned 540 off in the following conditions: 541 1. If TARGET_P8_VECTOR is turned off and OPTION_MASK_P9_VECTOR is 542 not turned on explicitly. Hereafter, if OPTION_MASK_P8_VECTOR 543 was turned on explicitly, the OPTION_MASK_P9_VECTOR flag is 544 also considered to have been turned off explicitly. 545 Note that the OPTION_MASK_P9_VECTOR is automatically turned on 546 in the following conditions: 547 1. If TARGET_P9_MINMAX was turned on explicitly. 548 Hereafter, THE OPTION_MASK_P9_VECTOR flag is considered to 549 have been turned on explicitly. */ 550 if ((flags & OPTION_MASK_P9_VECTOR) != 0) 551 rs6000_define_or_undefine_macro (define_p, "__POWER9_VECTOR__"); 552 /* Note that the OPTION_MASK_QUAD_MEMORY flag is automatically 553 turned off in the following conditions: 554 1. If TARGET_POWERPC64 is turned off. 555 2. If WORDS_BIG_ENDIAN is false (non-atomic quad memory 556 load/store are disabled on little endian). */ 557 if ((flags & OPTION_MASK_QUAD_MEMORY) != 0) 558 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY__"); 559 /* Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is automatically 560 turned off in the following conditions: 561 1. If TARGET_POWERPC64 is turned off. 562 Note that the OPTION_MASK_QUAD_MEMORY_ATOMIC flag is 563 automatically turned on in the following conditions: 564 1. If TARGET_QUAD_MEMORY and this flag was not explicitly 565 disabled. */ 566 if ((flags & OPTION_MASK_QUAD_MEMORY_ATOMIC) != 0) 567 rs6000_define_or_undefine_macro (define_p, "__QUAD_MEMORY_ATOMIC__"); 568 /* Note that the OPTION_MASK_CRYPTO flag is automatically turned off 569 in the following conditions: 570 1. If any of TARGET_HARD_FLOAT or TARGET_ALTIVEC or TARGET_VSX 571 are turned off explicitly and OPTION_MASK_CRYPTO is not turned 572 on explicitly. 573 2. If TARGET_ALTIVEC is turned off. */ 574 if ((flags & OPTION_MASK_CRYPTO) != 0) 575 rs6000_define_or_undefine_macro (define_p, "__CRYPTO__"); 576 if ((flags & OPTION_MASK_FLOAT128_KEYWORD) != 0) 577 { 578 rs6000_define_or_undefine_macro (define_p, "__FLOAT128__"); 579 if (define_p) 580 rs6000_define_or_undefine_macro (true, "__float128=__ieee128"); 581 else 582 rs6000_define_or_undefine_macro (false, "__float128"); 583 } 584 /* OPTION_MASK_FLOAT128_HARDWARE can be turned on if -mcpu=power9 is used or 585 via the target attribute/pragma. */ 586 if ((flags & OPTION_MASK_FLOAT128_HW) != 0) 587 rs6000_define_or_undefine_macro (define_p, "__FLOAT128_HARDWARE__"); 588 589 /* options from the builtin masks. */ 590 /* Note that RS6000_BTM_CELL is enabled only if (rs6000_cpu == 591 PROCESSOR_CELL) (e.g. -mcpu=cell). */ 592 if ((bu_mask & RS6000_BTM_CELL) != 0) 593 rs6000_define_or_undefine_macro (define_p, "__PPU__"); 594 } 595 596 void 597 rs6000_cpu_cpp_builtins (cpp_reader *pfile) 598 { 599 /* Define all of the common macros. */ 600 rs6000_target_modify_macros (true, rs6000_isa_flags, 601 rs6000_builtin_mask_calculate ()); 602 603 if (TARGET_FRE) 604 builtin_define ("__RECIP__"); 605 if (TARGET_FRES) 606 builtin_define ("__RECIPF__"); 607 if (TARGET_FRSQRTE) 608 builtin_define ("__RSQRTE__"); 609 if (TARGET_FRSQRTES) 610 builtin_define ("__RSQRTEF__"); 611 if (TARGET_FLOAT128_TYPE) 612 builtin_define ("__FLOAT128_TYPE__"); 613 #ifdef TARGET_LIBC_PROVIDES_HWCAP_IN_TCB 614 builtin_define ("__BUILTIN_CPU_SUPPORTS__"); 615 #endif 616 617 if (TARGET_EXTRA_BUILTINS && cpp_get_options (pfile)->lang != CLK_ASM) 618 { 619 /* Define the AltiVec syntactic elements. */ 620 builtin_define ("__vector=__attribute__((altivec(vector__)))"); 621 builtin_define ("__pixel=__attribute__((altivec(pixel__))) unsigned short"); 622 builtin_define ("__bool=__attribute__((altivec(bool__))) unsigned"); 623 624 if (!flag_iso) 625 { 626 builtin_define ("vector=vector"); 627 builtin_define ("pixel=pixel"); 628 builtin_define ("bool=bool"); 629 builtin_define ("_Bool=_Bool"); 630 init_vector_keywords (); 631 632 /* Enable context-sensitive macros. */ 633 cpp_get_callbacks (pfile)->macro_to_expand = rs6000_macro_to_expand; 634 } 635 } 636 if (!TARGET_HARD_FLOAT) 637 builtin_define ("_SOFT_DOUBLE"); 638 /* Used by lwarx/stwcx. errata work-around. */ 639 if (rs6000_cpu == PROCESSOR_PPC405) 640 builtin_define ("__PPC405__"); 641 /* Used by libstdc++. */ 642 if (TARGET_NO_LWSYNC) 643 builtin_define ("__NO_LWSYNC__"); 644 645 if (TARGET_EXTRA_BUILTINS) 646 { 647 /* For the VSX builtin functions identical to Altivec functions, just map 648 the altivec builtin into the vsx version (the altivec functions 649 generate VSX code if -mvsx). */ 650 builtin_define ("__builtin_vsx_xxland=__builtin_vec_and"); 651 builtin_define ("__builtin_vsx_xxlandc=__builtin_vec_andc"); 652 builtin_define ("__builtin_vsx_xxlnor=__builtin_vec_nor"); 653 builtin_define ("__builtin_vsx_xxlor=__builtin_vec_or"); 654 builtin_define ("__builtin_vsx_xxlxor=__builtin_vec_xor"); 655 builtin_define ("__builtin_vsx_xxsel=__builtin_vec_sel"); 656 builtin_define ("__builtin_vsx_vperm=__builtin_vec_perm"); 657 658 /* Also map the a and m versions of the multiply/add instructions to the 659 builtin for people blindly going off the instruction manual. */ 660 builtin_define ("__builtin_vsx_xvmaddadp=__builtin_vsx_xvmadddp"); 661 builtin_define ("__builtin_vsx_xvmaddmdp=__builtin_vsx_xvmadddp"); 662 builtin_define ("__builtin_vsx_xvmaddasp=__builtin_vsx_xvmaddsp"); 663 builtin_define ("__builtin_vsx_xvmaddmsp=__builtin_vsx_xvmaddsp"); 664 builtin_define ("__builtin_vsx_xvmsubadp=__builtin_vsx_xvmsubdp"); 665 builtin_define ("__builtin_vsx_xvmsubmdp=__builtin_vsx_xvmsubdp"); 666 builtin_define ("__builtin_vsx_xvmsubasp=__builtin_vsx_xvmsubsp"); 667 builtin_define ("__builtin_vsx_xvmsubmsp=__builtin_vsx_xvmsubsp"); 668 builtin_define ("__builtin_vsx_xvnmaddadp=__builtin_vsx_xvnmadddp"); 669 builtin_define ("__builtin_vsx_xvnmaddmdp=__builtin_vsx_xvnmadddp"); 670 builtin_define ("__builtin_vsx_xvnmaddasp=__builtin_vsx_xvnmaddsp"); 671 builtin_define ("__builtin_vsx_xvnmaddmsp=__builtin_vsx_xvnmaddsp"); 672 builtin_define ("__builtin_vsx_xvnmsubadp=__builtin_vsx_xvnmsubdp"); 673 builtin_define ("__builtin_vsx_xvnmsubmdp=__builtin_vsx_xvnmsubdp"); 674 builtin_define ("__builtin_vsx_xvnmsubasp=__builtin_vsx_xvnmsubsp"); 675 builtin_define ("__builtin_vsx_xvnmsubmsp=__builtin_vsx_xvnmsubsp"); 676 } 677 678 /* Map the old _Float128 'q' builtins into the new 'f128' builtins. */ 679 if (TARGET_FLOAT128_TYPE) 680 { 681 builtin_define ("__builtin_fabsq=__builtin_fabsf128"); 682 builtin_define ("__builtin_copysignq=__builtin_copysignf128"); 683 builtin_define ("__builtin_nanq=__builtin_nanf128"); 684 builtin_define ("__builtin_nansq=__builtin_nansf128"); 685 builtin_define ("__builtin_infq=__builtin_inff128"); 686 builtin_define ("__builtin_huge_valq=__builtin_huge_valf128"); 687 } 688 689 /* Tell users they can use __builtin_bswap{16,64}. */ 690 builtin_define ("__HAVE_BSWAP__"); 691 692 /* May be overridden by target configuration. */ 693 RS6000_CPU_CPP_ENDIAN_BUILTINS(); 694 695 if (TARGET_LONG_DOUBLE_128) 696 { 697 builtin_define ("__LONG_DOUBLE_128__"); 698 builtin_define ("__LONGDOUBLE128"); 699 700 if (TARGET_IEEEQUAD) 701 { 702 /* Older versions of GLIBC used __attribute__((__KC__)) to create the 703 IEEE 128-bit floating point complex type for C++ (which does not 704 support _Float128 _Complex). If the default for long double is 705 IEEE 128-bit mode, the library would need to use 706 __attribute__((__TC__)) instead. Defining __KF__ and __KC__ 707 is a stop-gap to build with the older libraries, until we 708 get an updated library. */ 709 builtin_define ("__LONG_DOUBLE_IEEE128__"); 710 builtin_define ("__KF__=__TF__"); 711 builtin_define ("__KC__=__TC__"); 712 } 713 else 714 builtin_define ("__LONG_DOUBLE_IBM128__"); 715 } 716 717 switch (TARGET_CMODEL) 718 { 719 /* Deliberately omit __CMODEL_SMALL__ since that was the default 720 before --mcmodel support was added. */ 721 case CMODEL_MEDIUM: 722 builtin_define ("__CMODEL_MEDIUM__"); 723 break; 724 case CMODEL_LARGE: 725 builtin_define ("__CMODEL_LARGE__"); 726 break; 727 default: 728 break; 729 } 730 731 switch (rs6000_current_abi) 732 { 733 case ABI_V4: 734 builtin_define ("_CALL_SYSV"); 735 break; 736 case ABI_AIX: 737 builtin_define ("_CALL_AIXDESC"); 738 builtin_define ("_CALL_AIX"); 739 builtin_define ("_CALL_ELF=1"); 740 break; 741 case ABI_ELFv2: 742 builtin_define ("_CALL_ELF=2"); 743 break; 744 case ABI_DARWIN: 745 builtin_define ("_CALL_DARWIN"); 746 break; 747 default: 748 break; 749 } 750 751 /* Vector element order. */ 752 if (BYTES_BIG_ENDIAN) 753 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_BIG_ENDIAN__"); 754 else 755 builtin_define ("__VEC_ELEMENT_REG_ORDER__=__ORDER_LITTLE_ENDIAN__"); 756 757 /* Let the compiled code know if 'f' class registers will not be available. */ 758 if (TARGET_SOFT_FLOAT) 759 builtin_define ("__NO_FPRS__"); 760 761 /* Whether aggregates passed by value are aligned to a 16 byte boundary 762 if their alignment is 16 bytes or larger. */ 763 if ((TARGET_MACHO && rs6000_darwin64_abi) 764 || DEFAULT_ABI == ABI_ELFv2 765 || (DEFAULT_ABI == ABI_AIX && !rs6000_compat_align_parm)) 766 builtin_define ("__STRUCT_PARM_ALIGN__=16"); 767 } 768 769 770 struct altivec_builtin_types 771 { 772 enum rs6000_builtins code; 773 enum rs6000_builtins overloaded_code; 774 signed char ret_type; 775 signed char op1; 776 signed char op2; 777 signed char op3; 778 }; 779 780 const struct altivec_builtin_types altivec_overloaded_builtins[] = { 781 /* Unary AltiVec/VSX builtins. */ 782 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V16QI, 783 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 784 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V8HI, 785 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 786 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SI, 787 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 788 { ALTIVEC_BUILTIN_VEC_ABS, P8V_BUILTIN_ABS_V2DI, 789 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 790 { ALTIVEC_BUILTIN_VEC_ABS, ALTIVEC_BUILTIN_ABS_V4SF, 791 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 792 { ALTIVEC_BUILTIN_VEC_ABS, VSX_BUILTIN_XVABSDP, 793 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 794 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V16QI, 795 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 796 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V8HI, 797 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 798 { ALTIVEC_BUILTIN_VEC_ABSS, ALTIVEC_BUILTIN_ABSS_V4SI, 799 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 800 { ALTIVEC_BUILTIN_VEC_CEIL, ALTIVEC_BUILTIN_VRFIP, 801 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 802 { ALTIVEC_BUILTIN_VEC_CEIL, VSX_BUILTIN_XVRDPIP, 803 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 804 { ALTIVEC_BUILTIN_VEC_EXPTE, ALTIVEC_BUILTIN_VEXPTEFP, 805 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 806 { ALTIVEC_BUILTIN_VEC_FLOOR, VSX_BUILTIN_XVRDPIM, 807 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 808 { ALTIVEC_BUILTIN_VEC_FLOOR, ALTIVEC_BUILTIN_VRFIM, 809 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 810 { ALTIVEC_BUILTIN_VEC_LOGE, ALTIVEC_BUILTIN_VLOGEFP, 811 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 812 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 813 RS6000_BTI_void, RS6000_BTI_V4SI, 0, 0 }, 814 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 815 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, 0, 0 }, 816 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 817 RS6000_BTI_void, RS6000_BTI_bool_V4SI, 0, 0 }, 818 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 819 RS6000_BTI_void, RS6000_BTI_V8HI, 0, 0 }, 820 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 821 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, 0, 0 }, 822 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 823 RS6000_BTI_void, RS6000_BTI_bool_V8HI, 0, 0 }, 824 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 825 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, 0, 0 }, 826 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 827 RS6000_BTI_void, RS6000_BTI_V16QI, 0, 0 }, 828 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 829 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 0, 0 }, 830 { ALTIVEC_BUILTIN_VEC_MTVSCR, ALTIVEC_BUILTIN_MTVSCR, 831 RS6000_BTI_void, RS6000_BTI_bool_V16QI, 0, 0 }, 832 { ALTIVEC_BUILTIN_VEC_RE, ALTIVEC_BUILTIN_VREFP, 833 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 834 { ALTIVEC_BUILTIN_VEC_RE, VSX_BUILTIN_XVREDP, 835 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 836 { ALTIVEC_BUILTIN_VEC_ROUND, ALTIVEC_BUILTIN_VRFIN, 837 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 838 { ALTIVEC_BUILTIN_VEC_ROUND, VSX_BUILTIN_XVRDPI, 839 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 840 { ALTIVEC_BUILTIN_VEC_RECIP, ALTIVEC_BUILTIN_VRECIPFP, 841 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 842 { ALTIVEC_BUILTIN_VEC_RECIP, VSX_BUILTIN_RECIP_V2DF, 843 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 844 { ALTIVEC_BUILTIN_VEC_RSQRT, ALTIVEC_BUILTIN_VRSQRTFP, 845 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 846 { ALTIVEC_BUILTIN_VEC_RSQRT, VSX_BUILTIN_RSQRT_2DF, 847 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 848 { ALTIVEC_BUILTIN_VEC_RSQRTE, ALTIVEC_BUILTIN_VRSQRTEFP, 849 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 850 { ALTIVEC_BUILTIN_VEC_RSQRTE, VSX_BUILTIN_XVRSQRTEDP, 851 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 852 { ALTIVEC_BUILTIN_VEC_TRUNC, ALTIVEC_BUILTIN_VRFIZ, 853 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 854 { ALTIVEC_BUILTIN_VEC_TRUNC, VSX_BUILTIN_XVRDPIZ, 855 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 856 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, 857 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 858 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSB, 859 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 860 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, 861 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 862 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHSH, 863 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 864 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, 865 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 866 { ALTIVEC_BUILTIN_VEC_UNPACKH, P8V_BUILTIN_VUPKHSW, 867 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 868 { ALTIVEC_BUILTIN_VEC_UNPACKH, ALTIVEC_BUILTIN_VUPKHPX, 869 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 870 { ALTIVEC_BUILTIN_VEC_UNPACKH, VSX_BUILTIN_DOUBLEH_V4SF, 871 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 872 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, 873 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 874 { ALTIVEC_BUILTIN_VEC_VUPKHSH, ALTIVEC_BUILTIN_VUPKHSH, 875 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 876 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, 877 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 878 { ALTIVEC_BUILTIN_VEC_VUPKHSH, P8V_BUILTIN_VUPKHSW, 879 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 880 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, 881 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 882 { ALTIVEC_BUILTIN_VEC_VUPKHPX, ALTIVEC_BUILTIN_VUPKHPX, 883 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 884 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, 885 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 886 { ALTIVEC_BUILTIN_VEC_VUPKHSB, ALTIVEC_BUILTIN_VUPKHSB, 887 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 888 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, 889 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 890 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSB, 891 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 892 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLPX, 893 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 894 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, 895 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 896 { ALTIVEC_BUILTIN_VEC_UNPACKL, ALTIVEC_BUILTIN_VUPKLSH, 897 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 898 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, 899 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 900 { ALTIVEC_BUILTIN_VEC_UNPACKL, P8V_BUILTIN_VUPKLSW, 901 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 902 { ALTIVEC_BUILTIN_VEC_UNPACKL, VSX_BUILTIN_DOUBLEL_V4SF, 903 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 904 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, 905 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 906 { ALTIVEC_BUILTIN_VEC_VUPKLPX, ALTIVEC_BUILTIN_VUPKLPX, 907 RS6000_BTI_unsigned_V4SI, RS6000_BTI_pixel_V8HI, 0, 0 }, 908 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, 909 RS6000_BTI_V4SI, RS6000_BTI_V8HI, 0, 0 }, 910 { ALTIVEC_BUILTIN_VEC_VUPKLSH, ALTIVEC_BUILTIN_VUPKLSH, 911 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V8HI, 0, 0 }, 912 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, 913 RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0, 0 }, 914 { ALTIVEC_BUILTIN_VEC_VUPKLSB, ALTIVEC_BUILTIN_VUPKLSB, 915 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V16QI, 0, 0 }, 916 917 /* Binary AltiVec/VSX builtins. */ 918 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 919 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 920 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 921 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 922 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 923 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 924 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 925 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 926 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 927 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 928 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUBM, 929 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 930 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 931 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 932 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 933 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 934 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 935 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 936 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 937 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 938 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 939 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 940 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUHM, 941 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 942 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 943 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 944 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 945 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 946 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 947 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 948 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 949 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 950 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 951 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 952 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDUWM, 953 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 954 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 955 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 956 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 957 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 958 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 959 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 960 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 961 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 962 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 963 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 964 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUDM, 965 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 966 { ALTIVEC_BUILTIN_VEC_ADD, ALTIVEC_BUILTIN_VADDFP, 967 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 968 { ALTIVEC_BUILTIN_VEC_ADD, VSX_BUILTIN_XVADDDP, 969 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 970 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, 971 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 972 { ALTIVEC_BUILTIN_VEC_ADD, P8V_BUILTIN_VADDUQM, 973 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 974 RS6000_BTI_unsigned_V1TI, 0 }, 975 { ALTIVEC_BUILTIN_VEC_VADDFP, ALTIVEC_BUILTIN_VADDFP, 976 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 977 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 978 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 979 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 980 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 981 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 982 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 983 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 984 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 985 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 986 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 987 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 988 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 989 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 990 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 991 { ALTIVEC_BUILTIN_VEC_VADDUWM, ALTIVEC_BUILTIN_VADDUWM, 992 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 993 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 994 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 995 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 996 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 997 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 998 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 999 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 1000 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1001 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 1002 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1003 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 1004 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1005 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 1006 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1007 { ALTIVEC_BUILTIN_VEC_VADDUHM, ALTIVEC_BUILTIN_VADDUHM, 1008 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1009 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 1010 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1011 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 1012 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1013 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 1014 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 1015 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 1016 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1017 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 1018 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1019 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 1020 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1021 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 1022 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1023 { ALTIVEC_BUILTIN_VEC_VADDUBM, ALTIVEC_BUILTIN_VADDUBM, 1024 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1025 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, 1026 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1027 { ALTIVEC_BUILTIN_VEC_ADDC, ALTIVEC_BUILTIN_VADDCUW, 1028 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 1029 RS6000_BTI_unsigned_V4SI, 0 }, 1030 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, 1031 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 1032 RS6000_BTI_unsigned_V1TI, 0 }, 1033 { ALTIVEC_BUILTIN_VEC_ADDC, P8V_BUILTIN_VADDCUQ, 1034 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 1035 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, 1036 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 1037 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 1038 { ALTIVEC_BUILTIN_VEC_ADDEC, P8V_BUILTIN_VADDECUQ, 1039 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 1040 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, 1041 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1042 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, 1043 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1044 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUBS, 1045 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1046 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, 1047 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1048 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, 1049 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1050 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSBS, 1051 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1052 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, 1053 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1054 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, 1055 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1056 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUHS, 1057 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1058 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, 1059 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1060 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, 1061 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1062 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSHS, 1063 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1064 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, 1065 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1066 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, 1067 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1068 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDUWS, 1069 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1070 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, 1071 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1072 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, 1073 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1074 { ALTIVEC_BUILTIN_VEC_ADDS, ALTIVEC_BUILTIN_VADDSWS, 1075 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1076 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, 1077 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1078 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, 1079 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1080 { ALTIVEC_BUILTIN_VEC_VADDSWS, ALTIVEC_BUILTIN_VADDSWS, 1081 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1082 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 1083 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1084 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 1085 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 1086 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 1087 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1088 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 1089 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1090 { ALTIVEC_BUILTIN_VEC_VADDUWS, ALTIVEC_BUILTIN_VADDUWS, 1091 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1092 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, 1093 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1094 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, 1095 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1096 { ALTIVEC_BUILTIN_VEC_VADDSHS, ALTIVEC_BUILTIN_VADDSHS, 1097 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1098 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 1099 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1100 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 1101 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 1102 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 1103 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1104 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 1105 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1106 { ALTIVEC_BUILTIN_VEC_VADDUHS, ALTIVEC_BUILTIN_VADDUHS, 1107 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1108 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, 1109 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1110 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, 1111 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1112 { ALTIVEC_BUILTIN_VEC_VADDSBS, ALTIVEC_BUILTIN_VADDSBS, 1113 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1114 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 1115 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1116 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 1117 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 1118 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 1119 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1120 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 1121 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1122 { ALTIVEC_BUILTIN_VEC_VADDUBS, ALTIVEC_BUILTIN_VADDUBS, 1123 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1124 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1125 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1126 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1127 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 1128 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1129 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 1130 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1131 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1132 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1133 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 1134 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1135 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 1136 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1137 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1138 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1139 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1140 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1141 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1142 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1143 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1144 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1145 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1146 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1147 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1148 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1149 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1150 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1151 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1152 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1153 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1154 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1155 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1156 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1157 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1158 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1159 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1160 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1161 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1162 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1163 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1164 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1165 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1166 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1167 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1168 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1169 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1170 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1171 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1172 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1173 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1174 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1175 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1176 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1177 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1178 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1179 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1180 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1181 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1182 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1183 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1184 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1185 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1186 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1187 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1188 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1189 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1190 { ALTIVEC_BUILTIN_VEC_AND, ALTIVEC_BUILTIN_VAND, 1191 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1192 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1193 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1194 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1195 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 1196 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1197 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 1198 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1199 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1200 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1201 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 1202 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1203 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 1204 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1205 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1206 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1207 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1208 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1209 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1210 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1211 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1212 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1213 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1214 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1215 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1216 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1217 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1218 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1219 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1220 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1221 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1222 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1223 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1224 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1225 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1226 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1227 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1228 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1229 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1230 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1231 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1232 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1233 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1234 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1235 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1236 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1237 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1238 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1239 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1240 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1241 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1242 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1243 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1244 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1245 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1246 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1247 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1248 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1249 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1250 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1251 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1252 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1253 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1254 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1255 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1256 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1257 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1258 { ALTIVEC_BUILTIN_VEC_ANDC, ALTIVEC_BUILTIN_VANDC, 1259 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1260 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUB, 1261 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1262 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSB, 1263 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1264 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUH, 1265 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1266 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSH, 1267 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1268 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGUW, 1269 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1270 { ALTIVEC_BUILTIN_VEC_AVG, ALTIVEC_BUILTIN_VAVGSW, 1271 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1272 { ALTIVEC_BUILTIN_VEC_VAVGSW, ALTIVEC_BUILTIN_VAVGSW, 1273 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1274 { ALTIVEC_BUILTIN_VEC_VAVGUW, ALTIVEC_BUILTIN_VAVGUW, 1275 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1276 { ALTIVEC_BUILTIN_VEC_VAVGSH, ALTIVEC_BUILTIN_VAVGSH, 1277 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1278 { ALTIVEC_BUILTIN_VEC_VAVGUH, ALTIVEC_BUILTIN_VAVGUH, 1279 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1280 { ALTIVEC_BUILTIN_VEC_VAVGSB, ALTIVEC_BUILTIN_VAVGSB, 1281 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1282 { ALTIVEC_BUILTIN_VEC_VAVGUB, ALTIVEC_BUILTIN_VAVGUB, 1283 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1284 { ALTIVEC_BUILTIN_VEC_CMPB, ALTIVEC_BUILTIN_VCMPBFP, 1285 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1286 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, 1287 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1288 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, 1289 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1290 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUB, 1291 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1292 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, 1293 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1294 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, 1295 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1296 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUH, 1297 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1298 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, 1299 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1300 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, 1301 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1302 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQUW, 1303 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1304 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, 1305 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1306 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, 1307 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1308 { ALTIVEC_BUILTIN_VEC_CMPEQ, P8V_BUILTIN_VCMPEQUD, 1309 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1310 { ALTIVEC_BUILTIN_VEC_CMPEQ, ALTIVEC_BUILTIN_VCMPEQFP, 1311 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1312 { ALTIVEC_BUILTIN_VEC_CMPEQ, VSX_BUILTIN_XVCMPEQDP, 1313 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1314 { ALTIVEC_BUILTIN_VEC_VCMPEQFP, ALTIVEC_BUILTIN_VCMPEQFP, 1315 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1316 1317 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, 1318 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1319 { ALTIVEC_BUILTIN_VEC_VCMPEQUW, ALTIVEC_BUILTIN_VCMPEQUW, 1320 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1321 1322 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, 1323 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1324 { ALTIVEC_BUILTIN_VEC_VCMPEQUH, ALTIVEC_BUILTIN_VCMPEQUH, 1325 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1326 1327 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, 1328 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1329 { ALTIVEC_BUILTIN_VEC_VCMPEQUB, ALTIVEC_BUILTIN_VCMPEQUB, 1330 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1331 1332 { ALTIVEC_BUILTIN_VEC_CMPGE, ALTIVEC_BUILTIN_VCMPGEFP, 1333 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1334 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_XVCMPGEDP, 1335 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1336 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_16QI, 1337 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0}, 1338 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U16QI, 1339 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 1340 RS6000_BTI_unsigned_V16QI, 0}, 1341 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_8HI, 1342 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0}, 1343 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U8HI, 1344 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 1345 RS6000_BTI_unsigned_V8HI, 0}, 1346 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_4SI, 1347 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0}, 1348 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U4SI, 1349 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 1350 RS6000_BTI_unsigned_V4SI, 0}, 1351 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_2DI, 1352 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0}, 1353 { ALTIVEC_BUILTIN_VEC_CMPGE, VSX_BUILTIN_CMPGE_U2DI, 1354 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 1355 RS6000_BTI_unsigned_V2DI, 0}, 1356 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUB, 1357 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1358 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSB, 1359 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1360 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUH, 1361 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1362 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSH, 1363 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1364 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTUW, 1365 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1366 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTSW, 1367 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1368 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTUD, 1369 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1370 { ALTIVEC_BUILTIN_VEC_CMPGT, P8V_BUILTIN_VCMPGTSD, 1371 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1372 { ALTIVEC_BUILTIN_VEC_CMPGT, ALTIVEC_BUILTIN_VCMPGTFP, 1373 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1374 { ALTIVEC_BUILTIN_VEC_CMPGT, VSX_BUILTIN_XVCMPGTDP, 1375 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1376 { ALTIVEC_BUILTIN_VEC_VCMPGTFP, ALTIVEC_BUILTIN_VCMPGTFP, 1377 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1378 { ALTIVEC_BUILTIN_VEC_VCMPGTSW, ALTIVEC_BUILTIN_VCMPGTSW, 1379 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1380 { ALTIVEC_BUILTIN_VEC_VCMPGTUW, ALTIVEC_BUILTIN_VCMPGTUW, 1381 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1382 { ALTIVEC_BUILTIN_VEC_VCMPGTSH, ALTIVEC_BUILTIN_VCMPGTSH, 1383 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1384 { ALTIVEC_BUILTIN_VEC_VCMPGTUH, ALTIVEC_BUILTIN_VCMPGTUH, 1385 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1386 { ALTIVEC_BUILTIN_VEC_VCMPGTSB, ALTIVEC_BUILTIN_VCMPGTSB, 1387 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1388 { ALTIVEC_BUILTIN_VEC_VCMPGTUB, ALTIVEC_BUILTIN_VCMPGTUB, 1389 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1390 { ALTIVEC_BUILTIN_VEC_CMPLE, ALTIVEC_BUILTIN_VCMPGEFP, 1391 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1392 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_XVCMPGEDP, 1393 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1394 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_16QI, 1395 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0}, 1396 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U16QI, 1397 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 1398 RS6000_BTI_unsigned_V16QI, 0}, 1399 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_8HI, 1400 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0}, 1401 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U8HI, 1402 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 1403 RS6000_BTI_unsigned_V8HI, 0}, 1404 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_4SI, 1405 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0}, 1406 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U4SI, 1407 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 1408 RS6000_BTI_unsigned_V4SI, 0}, 1409 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_2DI, 1410 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0}, 1411 { ALTIVEC_BUILTIN_VEC_CMPLE, VSX_BUILTIN_CMPLE_U2DI, 1412 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 1413 RS6000_BTI_unsigned_V2DI, 0}, 1414 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUB, 1415 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1416 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSB, 1417 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1418 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUH, 1419 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1420 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSH, 1421 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1422 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTUW, 1423 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1424 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTSW, 1425 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1426 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTUD, 1427 RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1428 { ALTIVEC_BUILTIN_VEC_CMPLT, P8V_BUILTIN_VCMPGTSD, 1429 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1430 { ALTIVEC_BUILTIN_VEC_CMPLT, ALTIVEC_BUILTIN_VCMPGTFP, 1431 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1432 { ALTIVEC_BUILTIN_VEC_CMPLT, VSX_BUILTIN_XVCMPGTDP, 1433 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1434 { ALTIVEC_BUILTIN_VEC_COPYSIGN, VSX_BUILTIN_CPSGNDP, 1435 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1436 { ALTIVEC_BUILTIN_VEC_COPYSIGN, ALTIVEC_BUILTIN_COPYSIGN_V4SF, 1437 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1438 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFUX, 1439 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 1440 { ALTIVEC_BUILTIN_VEC_CTF, ALTIVEC_BUILTIN_VCFSX, 1441 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 1442 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVSXDDP_SCALE, 1443 RS6000_BTI_V2DF, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0}, 1444 { ALTIVEC_BUILTIN_VEC_CTF, VSX_BUILTIN_XVCVUXDDP_SCALE, 1445 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0}, 1446 { ALTIVEC_BUILTIN_VEC_VCFSX, ALTIVEC_BUILTIN_VCFSX, 1447 RS6000_BTI_V4SF, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 1448 { ALTIVEC_BUILTIN_VEC_VCFUX, ALTIVEC_BUILTIN_VCFUX, 1449 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 1450 { ALTIVEC_BUILTIN_VEC_CTS, ALTIVEC_BUILTIN_VCTSXS, 1451 RS6000_BTI_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 1452 { ALTIVEC_BUILTIN_VEC_CTS, VSX_BUILTIN_XVCVDPSXDS_SCALE, 1453 RS6000_BTI_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 1454 { ALTIVEC_BUILTIN_VEC_CTU, ALTIVEC_BUILTIN_VCTUXS, 1455 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 1456 { ALTIVEC_BUILTIN_VEC_CTU, VSX_BUILTIN_XVCVDPUXDS_SCALE, 1457 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 1458 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVSP, 1459 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1460 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_XVDIVDP, 1461 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1462 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_DIV_V2DI, 1463 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1464 { VSX_BUILTIN_VEC_DIV, VSX_BUILTIN_UDIV_V2DI, 1465 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1466 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVSXDDP, 1467 RS6000_BTI_V2DF, RS6000_BTI_V2DI, 0, 0 }, 1468 { VSX_BUILTIN_VEC_DOUBLE, VSX_BUILTIN_XVCVUXDDP, 1469 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0, 0 }, 1470 1471 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SI, 1472 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, 1473 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_UNS_DOUBLEE_V4SI, 1474 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1475 { VSX_BUILTIN_VEC_DOUBLEE, VSX_BUILTIN_DOUBLEE_V4SF, 1476 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 1477 1478 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SI, 1479 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, 1480 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_UNS_DOUBLEO_V4SI, 1481 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1482 { VSX_BUILTIN_VEC_DOUBLEO, VSX_BUILTIN_DOUBLEO_V4SF, 1483 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 1484 1485 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SI, 1486 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, 1487 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_UNS_DOUBLEH_V4SI, 1488 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1489 { VSX_BUILTIN_VEC_DOUBLEH, VSX_BUILTIN_DOUBLEH_V4SF, 1490 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 1491 1492 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SI, 1493 RS6000_BTI_V2DF, RS6000_BTI_V4SI, 0, 0 }, 1494 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_UNS_DOUBLEL_V4SI, 1495 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1496 { VSX_BUILTIN_VEC_DOUBLEL, VSX_BUILTIN_DOUBLEL_V4SF, 1497 RS6000_BTI_V2DF, RS6000_BTI_V4SF, 0, 0 }, 1498 1499 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVSXWSP_V4SF, 1500 RS6000_BTI_V4SF, RS6000_BTI_V4SI, 0, 0 }, 1501 { VSX_BUILTIN_VEC_FLOAT, VSX_BUILTIN_XVCVUXWSP_V4SF, 1502 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0, 0 }, 1503 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DF, 1504 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1505 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_FLOAT2_V2DI, 1506 RS6000_BTI_V4SF, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1507 { P8V_BUILTIN_VEC_FLOAT2, P8V_BUILTIN_UNS_FLOAT2_V2DI, 1508 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 1509 RS6000_BTI_unsigned_V2DI, 0 }, 1510 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DF, 1511 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, 1512 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_FLOATE_V2DI, 1513 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, 1514 { VSX_BUILTIN_VEC_FLOATE, VSX_BUILTIN_UNS_FLOATE_V2DI, 1515 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, 1516 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DF, 1517 RS6000_BTI_V4SF, RS6000_BTI_V2DF, 0, 0 }, 1518 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_FLOATO_V2DI, 1519 RS6000_BTI_V4SF, RS6000_BTI_V2DI, 0, 0 }, 1520 { VSX_BUILTIN_VEC_FLOATO, VSX_BUILTIN_UNS_FLOATO_V2DI, 1521 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V2DI, 0, 0 }, 1522 1523 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, 1524 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 }, 1525 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, 1526 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V1TI, 0 }, 1527 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, 1528 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, 1529 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V1TI, 1530 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, 1531 1532 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, 1533 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 1534 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DF, 1535 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1536 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1537 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 1538 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1539 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1540 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1541 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1542 ~RS6000_BTI_unsigned_V2DI, 0 }, 1543 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1544 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1545 ~RS6000_BTI_unsigned_long_long, 0 }, 1546 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V2DI, 1547 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 1548 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, 1549 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1550 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SF, 1551 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1552 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1553 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1554 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1555 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1556 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1557 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1558 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1559 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1560 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1561 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1562 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1563 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1564 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V4SI, 1565 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1566 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1567 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1568 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1569 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1570 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1571 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1572 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1573 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1574 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1575 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1576 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V8HI, 1577 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1578 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1579 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1580 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1581 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1582 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1583 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1584 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1585 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1586 { ALTIVEC_BUILTIN_VEC_LD, ALTIVEC_BUILTIN_LVX_V16QI, 1587 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1588 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, 1589 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1590 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEBX, 1591 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1592 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, 1593 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1594 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEHX, 1595 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1596 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1597 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1598 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1599 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1600 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1601 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1602 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1603 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1604 { ALTIVEC_BUILTIN_VEC_LDE, ALTIVEC_BUILTIN_LVEWX, 1605 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1606 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1607 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1608 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1609 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1610 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1611 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1612 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1613 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1614 { ALTIVEC_BUILTIN_VEC_LVEWX, ALTIVEC_BUILTIN_LVEWX, 1615 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1616 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, 1617 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1618 { ALTIVEC_BUILTIN_VEC_LVEHX, ALTIVEC_BUILTIN_LVEHX, 1619 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1620 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, 1621 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1622 { ALTIVEC_BUILTIN_VEC_LVEBX, ALTIVEC_BUILTIN_LVEBX, 1623 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1624 1625 /* vector float vec_ldl (int, vector float *); 1626 vector float vec_ldl (int, float *); */ 1627 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, 1628 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1629 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SF, 1630 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1631 1632 /* vector bool int vec_ldl (int, vector bool int *); 1633 vector bool int vec_ldl (int, bool int *); 1634 vector int vec_ldl (int, vector int *); 1635 vector int vec_ldl (int, int *); 1636 vector unsigned int vec_ldl (int, vector unsigned int *); 1637 vector unsigned int vec_ldl (int, unsigned int *); */ 1638 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1639 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1640 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1641 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_int, 0 }, 1642 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1643 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1644 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1645 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1646 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1647 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1648 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V4SI, 1649 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1650 1651 /* vector bool short vec_ldl (int, vector bool short *); 1652 vector bool short vec_ldl (int, bool short *); 1653 vector pixel vec_ldl (int, vector pixel *); 1654 vector short vec_ldl (int, vector short *); 1655 vector short vec_ldl (int, short *); 1656 vector unsigned short vec_ldl (int, vector unsigned short *); 1657 vector unsigned short vec_ldl (int, unsigned short *); */ 1658 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1659 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1660 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1661 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_short, 0 }, 1662 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1663 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1664 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1665 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1666 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1667 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1668 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1669 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1670 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V8HI, 1671 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1672 1673 /* vector bool char vec_ldl (int, vector bool char *); 1674 vector bool char vec_ldl (int, bool char *); 1675 vector char vec_ldl (int, vector char *); 1676 vector char vec_ldl (int, char *); 1677 vector unsigned char vec_ldl (int, vector unsigned char *); 1678 vector unsigned char vec_ldl (int, unsigned char *); */ 1679 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1680 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1681 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1682 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_char, 0 }, 1683 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1684 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1685 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1686 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1687 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1688 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1689 ~RS6000_BTI_unsigned_V16QI, 0 }, 1690 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V16QI, 1691 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1692 1693 /* vector double vec_ldl (int, vector double *); 1694 vector double vec_ldl (int, double *); */ 1695 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, 1696 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 1697 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DF, 1698 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1699 1700 /* vector long long vec_ldl (int, vector long long *); 1701 vector long long vec_ldl (int, long long *); 1702 vector unsigned long long vec_ldl (int, vector unsigned long long *); 1703 vector unsigned long long vec_ldl (int, unsigned long long *); 1704 vector bool long long vec_ldl (int, vector bool long long *); 1705 vector bool long long vec_ldl (int, bool long long *); */ 1706 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1707 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 1708 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1709 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1710 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1711 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1712 ~RS6000_BTI_unsigned_V2DI, 0 }, 1713 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1714 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 1715 ~RS6000_BTI_unsigned_long_long, 0 }, 1716 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1717 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 1718 { ALTIVEC_BUILTIN_VEC_LDL, ALTIVEC_BUILTIN_LVXL_V2DI, 1719 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_long_long, 0 }, 1720 1721 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1722 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1723 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1724 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1725 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1726 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1727 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1728 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1729 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1730 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1731 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1732 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1733 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1734 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1735 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1736 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1737 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1738 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1739 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1740 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1741 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1742 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, 1743 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1744 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, 1745 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1746 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1747 { ALTIVEC_BUILTIN_VEC_LVSL, ALTIVEC_BUILTIN_LVSL, 1748 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1749 ~RS6000_BTI_unsigned_long_long, 0 }, 1750 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1751 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1752 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1753 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1754 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1755 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1756 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1757 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1758 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1759 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1760 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1761 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1762 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1763 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long, 0 }, 1764 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1765 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 1766 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1767 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1768 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1769 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 1770 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1771 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, 1772 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1773 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, 1774 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1775 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 1776 { ALTIVEC_BUILTIN_VEC_LVSR, ALTIVEC_BUILTIN_LVSR, 1777 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 1778 ~RS6000_BTI_unsigned_long_long, 0 }, 1779 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1780 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1781 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1782 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1783 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1784 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1785 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1786 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1787 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1788 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1789 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1790 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1791 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1792 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1793 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1794 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1795 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1796 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1797 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1798 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1799 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1800 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1801 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1802 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1803 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1804 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1805 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1806 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1807 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1808 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1809 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1810 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1811 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1812 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1813 { ALTIVEC_BUILTIN_VEC_LVLX, ALTIVEC_BUILTIN_LVLX, 1814 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1815 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1816 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1817 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1818 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1819 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1820 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1821 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1822 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1823 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1824 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1825 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1826 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1827 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1828 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1829 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1830 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1831 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1832 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1833 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1834 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1835 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1836 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1837 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1838 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1839 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1840 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1841 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1842 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1843 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1844 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1845 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1846 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1847 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1848 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1849 { ALTIVEC_BUILTIN_VEC_LVLXL, ALTIVEC_BUILTIN_LVLXL, 1850 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1851 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1852 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1853 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1854 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1855 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1856 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1857 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1858 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1859 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1860 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1861 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1862 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1863 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1864 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1865 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1866 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1867 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1868 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1869 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1870 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1871 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1872 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1873 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1874 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1875 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1876 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1877 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1878 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1879 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1880 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1881 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1882 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1883 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1884 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1885 { ALTIVEC_BUILTIN_VEC_LVRX, ALTIVEC_BUILTIN_LVRX, 1886 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1887 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1888 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 1889 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1890 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 1891 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1892 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 1893 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1894 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 1895 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1896 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 1897 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1898 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 1899 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1900 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 1901 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1902 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 1903 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1904 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 1905 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1906 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 1907 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1908 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 1909 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1910 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 1911 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1912 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 1913 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1914 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 1915 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1916 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 1917 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1918 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 1919 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1920 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI, 0 }, 1921 { ALTIVEC_BUILTIN_VEC_LVRXL, ALTIVEC_BUILTIN_LVRXL, 1922 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 1923 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, 1924 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1925 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, 1926 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1927 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUB, 1928 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 1929 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, 1930 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 1931 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, 1932 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 1933 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSB, 1934 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 1935 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, 1936 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1937 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, 1938 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1939 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUH, 1940 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 1941 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, 1942 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1943 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, 1944 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1945 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSH, 1946 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1947 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, 1948 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1949 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, 1950 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1951 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXUW, 1952 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1953 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, 1954 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1955 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, 1956 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1957 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXSW, 1958 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1959 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, 1960 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1961 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, 1962 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1963 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXUD, 1964 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 1965 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, 1966 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 1967 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, 1968 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 1969 { ALTIVEC_BUILTIN_VEC_MAX, P8V_BUILTIN_VMAXSD, 1970 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 1971 { ALTIVEC_BUILTIN_VEC_MAX, ALTIVEC_BUILTIN_VMAXFP, 1972 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1973 { ALTIVEC_BUILTIN_VEC_MAX, VSX_BUILTIN_XVMAXDP, 1974 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 1975 { ALTIVEC_BUILTIN_VEC_VMAXFP, ALTIVEC_BUILTIN_VMAXFP, 1976 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 1977 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, 1978 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 1979 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, 1980 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 1981 { ALTIVEC_BUILTIN_VEC_VMAXSW, ALTIVEC_BUILTIN_VMAXSW, 1982 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1983 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1984 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1985 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1986 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 1987 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1988 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1989 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1990 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 1991 { ALTIVEC_BUILTIN_VEC_VMAXUW, ALTIVEC_BUILTIN_VMAXUW, 1992 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 1993 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, 1994 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 1995 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, 1996 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 1997 { ALTIVEC_BUILTIN_VEC_VMAXSH, ALTIVEC_BUILTIN_VMAXSH, 1998 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 1999 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 2000 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2001 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 2002 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 2003 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 2004 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2005 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 2006 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2007 { ALTIVEC_BUILTIN_VEC_VMAXUH, ALTIVEC_BUILTIN_VMAXUH, 2008 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2009 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, 2010 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2011 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, 2012 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2013 { ALTIVEC_BUILTIN_VEC_VMAXSB, ALTIVEC_BUILTIN_VMAXSB, 2014 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2015 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 2016 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2017 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 2018 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2019 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 2020 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2021 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 2022 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2023 { ALTIVEC_BUILTIN_VEC_VMAXUB, ALTIVEC_BUILTIN_VMAXUB, 2024 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2025 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, 2026 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2027 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, 2028 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2029 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHB, 2030 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2031 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 2032 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2033 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 2034 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 2035 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 2036 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2037 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHH, 2038 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2039 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 2040 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2041 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 2042 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2043 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 2044 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2045 { ALTIVEC_BUILTIN_VEC_MERGEH, ALTIVEC_BUILTIN_VMRGHW, 2046 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2047 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DF, 2048 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2049 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 2050 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2051 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 2052 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2053 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 2054 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 2055 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 2056 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2057 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 2058 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2059 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 2060 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2061 { ALTIVEC_BUILTIN_VEC_MERGEH, VSX_BUILTIN_VEC_MERGEH_V2DI, 2062 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2063 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 2064 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2065 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 2066 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2067 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 2068 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2069 { ALTIVEC_BUILTIN_VEC_VMRGHW, ALTIVEC_BUILTIN_VMRGHW, 2070 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2071 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 2072 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2073 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 2074 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 2075 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 2076 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2077 { ALTIVEC_BUILTIN_VEC_VMRGHH, ALTIVEC_BUILTIN_VMRGHH, 2078 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2079 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, 2080 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2081 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, 2082 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2083 { ALTIVEC_BUILTIN_VEC_VMRGHB, ALTIVEC_BUILTIN_VMRGHB, 2084 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2085 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, 2086 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2087 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, 2088 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2089 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLB, 2090 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2091 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 2092 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2093 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 2094 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 2095 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 2096 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2097 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLH, 2098 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2099 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 2100 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2101 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 2102 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2103 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 2104 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2105 { ALTIVEC_BUILTIN_VEC_MERGEL, ALTIVEC_BUILTIN_VMRGLW, 2106 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2107 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DF, 2108 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2109 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 2110 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2111 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 2112 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2113 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 2114 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 2115 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 2116 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2117 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 2118 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2119 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 2120 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2121 { ALTIVEC_BUILTIN_VEC_MERGEL, VSX_BUILTIN_VEC_MERGEL_V2DI, 2122 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2123 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 2124 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2125 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 2126 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2127 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 2128 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2129 { ALTIVEC_BUILTIN_VEC_VMRGLW, ALTIVEC_BUILTIN_VMRGLW, 2130 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2131 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 2132 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2133 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 2134 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, 0 }, 2135 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 2136 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2137 { ALTIVEC_BUILTIN_VEC_VMRGLH, ALTIVEC_BUILTIN_VMRGLH, 2138 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2139 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, 2140 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2141 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, 2142 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2143 { ALTIVEC_BUILTIN_VEC_VMRGLB, ALTIVEC_BUILTIN_VMRGLB, 2144 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2145 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, 2146 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2147 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, 2148 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2149 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUB, 2150 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2151 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, 2152 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2153 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, 2154 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2155 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSB, 2156 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2157 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, 2158 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2159 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, 2160 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2161 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUH, 2162 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2163 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, 2164 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2165 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, 2166 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2167 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSH, 2168 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2169 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, 2170 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2171 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, 2172 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2173 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINUW, 2174 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2175 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, 2176 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2177 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, 2178 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2179 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINSW, 2180 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2181 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, 2182 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2183 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, 2184 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2185 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINUD, 2186 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2187 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, 2188 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 2189 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, 2190 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2191 { ALTIVEC_BUILTIN_VEC_MIN, P8V_BUILTIN_VMINSD, 2192 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2193 { ALTIVEC_BUILTIN_VEC_MIN, ALTIVEC_BUILTIN_VMINFP, 2194 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2195 { ALTIVEC_BUILTIN_VEC_MIN, VSX_BUILTIN_XVMINDP, 2196 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2197 { ALTIVEC_BUILTIN_VEC_VMINFP, ALTIVEC_BUILTIN_VMINFP, 2198 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2199 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, 2200 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2201 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, 2202 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2203 { ALTIVEC_BUILTIN_VEC_VMINSW, ALTIVEC_BUILTIN_VMINSW, 2204 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2205 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 2206 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2207 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 2208 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 2209 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 2210 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2211 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 2212 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2213 { ALTIVEC_BUILTIN_VEC_VMINUW, ALTIVEC_BUILTIN_VMINUW, 2214 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2215 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, 2216 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2217 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, 2218 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2219 { ALTIVEC_BUILTIN_VEC_VMINSH, ALTIVEC_BUILTIN_VMINSH, 2220 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2221 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, 2222 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2223 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, 2224 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2225 { ALTIVEC_BUILTIN_VEC_VMINSB, ALTIVEC_BUILTIN_VMINSB, 2226 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2227 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 2228 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2229 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 2230 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 2231 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 2232 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2233 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 2234 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2235 { ALTIVEC_BUILTIN_VEC_VMINUH, ALTIVEC_BUILTIN_VMINUH, 2236 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2237 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 2238 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2239 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 2240 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2241 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 2242 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2243 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 2244 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2245 { ALTIVEC_BUILTIN_VEC_VMINUB, ALTIVEC_BUILTIN_VMINUB, 2246 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2247 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUB, 2248 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2249 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESB, 2250 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2251 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULEUH, 2252 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2253 { ALTIVEC_BUILTIN_VEC_MULE, ALTIVEC_BUILTIN_VMULESH, 2254 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2255 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULESW, 2256 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2257 { ALTIVEC_BUILTIN_VEC_MULE, P8V_BUILTIN_VMULEUW, 2258 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, 2259 RS6000_BTI_unsigned_V4SI, 0 }, 2260 { ALTIVEC_BUILTIN_VEC_VMULEUB, ALTIVEC_BUILTIN_VMULEUB, 2261 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2262 { ALTIVEC_BUILTIN_VEC_VMULESB, ALTIVEC_BUILTIN_VMULESB, 2263 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2264 { ALTIVEC_BUILTIN_VEC_VMULEUH, ALTIVEC_BUILTIN_VMULEUH, 2265 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2266 { ALTIVEC_BUILTIN_VEC_VMULESH, ALTIVEC_BUILTIN_VMULESH, 2267 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2268 { ALTIVEC_BUILTIN_VEC_VMULEUW, P8V_BUILTIN_VMULEUW, 2269 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2270 { ALTIVEC_BUILTIN_VEC_VMULESW, P8V_BUILTIN_VMULESW, 2271 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2272 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUB, 2273 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2274 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSB, 2275 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2276 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOUH, 2277 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2278 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOSW, 2279 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2280 { ALTIVEC_BUILTIN_VEC_MULO, P8V_BUILTIN_VMULOUW, 2281 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, 2282 RS6000_BTI_unsigned_V4SI, 0 }, 2283 { ALTIVEC_BUILTIN_VEC_MULO, ALTIVEC_BUILTIN_VMULOSH, 2284 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2285 { ALTIVEC_BUILTIN_VEC_VMULOSH, ALTIVEC_BUILTIN_VMULOSH, 2286 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2287 { ALTIVEC_BUILTIN_VEC_VMULOUH, ALTIVEC_BUILTIN_VMULOUH, 2288 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2289 { ALTIVEC_BUILTIN_VEC_VMULOSB, ALTIVEC_BUILTIN_VMULOSB, 2290 RS6000_BTI_V8HI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2291 { ALTIVEC_BUILTIN_VEC_VMULOUB, ALTIVEC_BUILTIN_VMULOUB, 2292 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2293 { ALTIVEC_BUILTIN_VEC_VMULOUW, P8V_BUILTIN_VMULOUW, 2294 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2295 { ALTIVEC_BUILTIN_VEC_VMULOSW, P8V_BUILTIN_VMULOSW, 2296 RS6000_BTI_V2DI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2297 2298 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V16QI, 2299 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 2300 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V8HI, 2301 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 2302 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SI, 2303 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 2304 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V2DI, 2305 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 2306 { ALTIVEC_BUILTIN_VEC_NABS, ALTIVEC_BUILTIN_NABS_V4SF, 2307 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2308 { ALTIVEC_BUILTIN_VEC_NABS, VSX_BUILTIN_XVNABSDP, 2309 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2310 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRDPI, 2311 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2312 { ALTIVEC_BUILTIN_VEC_NEARBYINT, VSX_BUILTIN_XVRSPI, 2313 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2314 2315 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2316 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2317 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2318 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2319 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2320 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2321 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2322 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2323 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2324 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 2325 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2326 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2327 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2328 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2329 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2330 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2331 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2332 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2333 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2334 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2335 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2336 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2337 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2338 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2339 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2340 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2341 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2342 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2343 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2344 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2345 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2346 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2347 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2348 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2349 { ALTIVEC_BUILTIN_VEC_NOR, ALTIVEC_BUILTIN_VNOR, 2350 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2351 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2352 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2353 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2354 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 2355 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2356 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 2357 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2358 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2359 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2360 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 2361 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2362 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 2363 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2364 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2365 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2366 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2367 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2368 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 2369 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2370 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2371 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2372 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2373 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2374 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2375 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2376 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2377 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2378 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2379 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2380 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2381 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2382 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2383 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2384 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2385 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2386 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2387 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2388 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2389 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2390 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2391 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2392 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2393 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2394 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2395 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2396 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2397 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2398 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2399 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2400 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2401 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2402 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2403 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2404 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2405 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2406 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2407 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2408 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2409 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2410 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2411 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2412 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2413 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2414 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2415 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2416 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2417 { ALTIVEC_BUILTIN_VEC_OR, ALTIVEC_BUILTIN_VOR, 2418 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2419 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, 2420 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2421 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, 2422 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2423 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUHUM, 2424 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2425 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, 2426 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2427 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, 2428 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2429 { ALTIVEC_BUILTIN_VEC_PACK, ALTIVEC_BUILTIN_VPKUWUM, 2430 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2431 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 2432 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2433 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 2434 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2435 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_VPKUDUM, 2436 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 2437 { ALTIVEC_BUILTIN_VEC_PACK, P8V_BUILTIN_FLOAT2_V2DF, 2438 RS6000_BTI_V4SF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 2439 2440 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V16QI, 2441 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 2442 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V8HI, 2443 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 2444 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SI, 2445 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 2446 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DI, 2447 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 2448 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V4SF, 2449 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2450 { P8V_BUILTIN_VEC_NEG, P8V_BUILTIN_NEG_V2DF, 2451 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2452 2453 { P9V_BUILTIN_VEC_CONVERT_4F32_8I16, P9V_BUILTIN_CONVERT_4F32_8I16, 2454 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 2455 2456 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI, 2457 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2458 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V16QI, 2459 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2460 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI, 2461 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2462 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V8HI, 2463 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2464 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI, 2465 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2466 { P9V_BUILTIN_VEC_VFIRSTMATCHINDEX, P9V_BUILTIN_VFIRSTMATCHINDEX_V4SI, 2467 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2468 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI, 2469 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2470 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V16QI, 2471 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2472 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI, 2473 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2474 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V8HI, 2475 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2476 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI, 2477 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2478 { P9V_BUILTIN_VEC_VFIRSTMATCHOREOSINDEX, P9V_BUILTIN_VFIRSTMATCHOREOSINDEX_V4SI, 2479 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2480 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI, 2481 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2482 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V16QI, 2483 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2484 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI, 2485 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2486 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V8HI, 2487 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2488 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI, 2489 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2490 { P9V_BUILTIN_VEC_VFIRSTMISMATCHINDEX, P9V_BUILTIN_VFIRSTMISMATCHINDEX_V4SI, 2491 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2492 2493 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2494 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, 2495 RS6000_BTI_UINTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2496 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2497 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V16QI, RS6000_BTI_UINTSI, 2498 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2499 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2500 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI, 2501 RS6000_BTI_UINTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2502 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2503 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V8HI, 2504 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2505 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2506 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI, 2507 RS6000_BTI_UINTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2508 { P9V_BUILTIN_VEC_VFIRSTMISMATCHOREOSINDEX, 2509 P9V_BUILTIN_VFIRSTMISMATCHOREOSINDEX_V4SI, 2510 RS6000_BTI_UINTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2511 2512 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2513 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2514 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2515 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2516 { ALTIVEC_BUILTIN_VEC_VPKUWUM, ALTIVEC_BUILTIN_VPKUWUM, 2517 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2518 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, 2519 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2520 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, 2521 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2522 { ALTIVEC_BUILTIN_VEC_VPKUHUM, ALTIVEC_BUILTIN_VPKUHUM, 2523 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2524 { ALTIVEC_BUILTIN_VEC_PACKPX, ALTIVEC_BUILTIN_VPKPX, 2525 RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2526 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUHUS, 2527 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2528 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSHSS, 2529 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2530 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKUWUS, 2531 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2532 { ALTIVEC_BUILTIN_VEC_PACKS, ALTIVEC_BUILTIN_VPKSWSS, 2533 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2534 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKUDUS, 2535 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2536 { ALTIVEC_BUILTIN_VEC_PACKS, P8V_BUILTIN_VPKSDSS, 2537 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2538 { ALTIVEC_BUILTIN_VEC_VPKSWSS, ALTIVEC_BUILTIN_VPKSWSS, 2539 RS6000_BTI_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2540 { ALTIVEC_BUILTIN_VEC_VPKUWUS, ALTIVEC_BUILTIN_VPKUWUS, 2541 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2542 { ALTIVEC_BUILTIN_VEC_VPKSHSS, ALTIVEC_BUILTIN_VPKSHSS, 2543 RS6000_BTI_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2544 { ALTIVEC_BUILTIN_VEC_VPKUHUS, ALTIVEC_BUILTIN_VPKUHUS, 2545 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2546 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUHUS, 2547 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2548 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSHUS, 2549 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2550 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKUWUS, 2551 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2552 { ALTIVEC_BUILTIN_VEC_PACKSU, ALTIVEC_BUILTIN_VPKSWUS, 2553 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2554 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKSDUS, 2555 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 2556 { ALTIVEC_BUILTIN_VEC_PACKSU, P8V_BUILTIN_VPKUDUS, 2557 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2558 { ALTIVEC_BUILTIN_VEC_VPKSWUS, ALTIVEC_BUILTIN_VPKSWUS, 2559 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2560 { ALTIVEC_BUILTIN_VEC_VPKSHUS, ALTIVEC_BUILTIN_VPKSHUS, 2561 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2562 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRDPIC, 2563 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2564 { ALTIVEC_BUILTIN_VEC_RINT, VSX_BUILTIN_XVRSPIC, 2565 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2566 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB, 2567 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2568 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLB, 2569 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2570 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH, 2571 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2572 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLH, 2573 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2574 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, 2575 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2576 { ALTIVEC_BUILTIN_VEC_RL, ALTIVEC_BUILTIN_VRLW, 2577 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2578 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, 2579 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2580 { ALTIVEC_BUILTIN_VEC_RL, P8V_BUILTIN_VRLD, 2581 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2582 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, 2583 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2584 { ALTIVEC_BUILTIN_VEC_VRLW, ALTIVEC_BUILTIN_VRLW, 2585 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2586 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH, 2587 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2588 { ALTIVEC_BUILTIN_VEC_VRLH, ALTIVEC_BUILTIN_VRLH, 2589 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2590 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB, 2591 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2592 { ALTIVEC_BUILTIN_VEC_VRLB, ALTIVEC_BUILTIN_VRLB, 2593 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2594 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLWMI, 2595 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 2596 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 2597 { P9V_BUILTIN_VEC_RLMI, P9V_BUILTIN_VRLDMI, 2598 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 2599 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 2600 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLWNM, 2601 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 2602 RS6000_BTI_unsigned_V4SI, 0 }, 2603 { P9V_BUILTIN_VEC_RLNM, P9V_BUILTIN_VRLDNM, 2604 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 2605 RS6000_BTI_unsigned_V2DI, 0 }, 2606 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB, 2607 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2608 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLB, 2609 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2610 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH, 2611 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2612 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLH, 2613 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2614 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, 2615 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2616 { ALTIVEC_BUILTIN_VEC_SL, ALTIVEC_BUILTIN_VSLW, 2617 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2618 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, 2619 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2620 { ALTIVEC_BUILTIN_VEC_SL, P8V_BUILTIN_VSLD, 2621 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2622 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTDP, 2623 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 2624 { ALTIVEC_BUILTIN_VEC_SQRT, VSX_BUILTIN_XVSQRTSP, 2625 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 2626 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW, 2627 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2628 { ALTIVEC_BUILTIN_VEC_VSLW, ALTIVEC_BUILTIN_VSLW, 2629 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2630 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH, 2631 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2632 { ALTIVEC_BUILTIN_VEC_VSLH, ALTIVEC_BUILTIN_VSLH, 2633 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2634 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB, 2635 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2636 { ALTIVEC_BUILTIN_VEC_VSLB, ALTIVEC_BUILTIN_VSLB, 2637 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2638 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2639 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2640 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2641 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2642 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2643 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2644 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2645 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2646 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2647 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2648 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2649 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2650 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2651 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2652 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2653 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2654 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2655 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2656 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2657 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2658 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2659 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2660 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2661 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2662 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2663 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2664 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2665 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2666 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2667 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2668 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2669 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2670 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2671 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2672 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2673 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2674 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2675 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2676 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2677 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2678 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2679 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2680 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2681 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2682 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2683 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2684 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2685 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2686 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2687 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2688 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2689 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2690 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2691 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2692 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2693 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2694 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2695 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2696 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2697 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2698 2699 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2700 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2701 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2702 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2703 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2704 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2705 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2706 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2707 { ALTIVEC_BUILTIN_VEC_SLL, ALTIVEC_BUILTIN_VSL, 2708 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V8HI, 0 }, 2709 2710 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2711 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, 2712 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2713 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, 2714 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2715 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 }, 2716 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2717 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2718 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2719 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 }, 2720 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2721 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2722 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2723 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 }, 2724 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2725 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2726 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2727 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 }, 2728 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2729 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2730 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2731 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 }, 2732 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2733 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2734 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2735 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2736 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2737 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2738 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2739 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2740 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2741 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2742 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2743 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 }, 2744 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2745 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2746 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2747 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 }, 2748 { ALTIVEC_BUILTIN_VEC_SLO, ALTIVEC_BUILTIN_VSLO, 2749 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2750 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, 2751 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 }, 2752 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, 2753 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, 2754 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTB, 2755 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 }, 2756 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2757 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 }, 2758 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2759 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 }, 2760 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2761 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 }, 2762 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTH, 2763 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 }, 2764 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2765 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 2766 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2767 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 2768 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2769 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 2770 { ALTIVEC_BUILTIN_VEC_SPLAT, ALTIVEC_BUILTIN_VSPLTW, 2771 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, 2772 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DF, 2773 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 2774 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, 2775 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 0 }, 2776 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, 2777 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 0 }, 2778 { ALTIVEC_BUILTIN_VEC_SPLAT, VSX_BUILTIN_XXSPLTD_V2DI, 2779 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 0 }, 2780 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2781 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 2782 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2783 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI, 0 }, 2784 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2785 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 0 }, 2786 { ALTIVEC_BUILTIN_VEC_VSPLTW, ALTIVEC_BUILTIN_VSPLTW, 2787 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 0 }, 2788 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2789 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI, 0 }, 2790 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2791 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 0 }, 2792 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2793 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 0 }, 2794 { ALTIVEC_BUILTIN_VEC_VSPLTH, ALTIVEC_BUILTIN_VSPLTH, 2795 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 0 }, 2796 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, 2797 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI, 0 }, 2798 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, 2799 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, 2800 { ALTIVEC_BUILTIN_VEC_VSPLTB, ALTIVEC_BUILTIN_VSPLTB, 2801 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 0 }, 2802 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB, 2803 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2804 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRB, 2805 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2806 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH, 2807 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2808 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRH, 2809 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2810 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, 2811 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2812 { ALTIVEC_BUILTIN_VEC_SR, ALTIVEC_BUILTIN_VSRW, 2813 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2814 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, 2815 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2816 { ALTIVEC_BUILTIN_VEC_SR, P8V_BUILTIN_VSRD, 2817 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2818 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, 2819 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2820 { ALTIVEC_BUILTIN_VEC_VSRW, ALTIVEC_BUILTIN_VSRW, 2821 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2822 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH, 2823 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2824 { ALTIVEC_BUILTIN_VEC_VSRH, ALTIVEC_BUILTIN_VSRH, 2825 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2826 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB, 2827 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2828 { ALTIVEC_BUILTIN_VEC_VSRB, ALTIVEC_BUILTIN_VSRB, 2829 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2830 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB, 2831 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2832 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAB, 2833 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2834 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH, 2835 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2836 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAH, 2837 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2838 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, 2839 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2840 { ALTIVEC_BUILTIN_VEC_SRA, ALTIVEC_BUILTIN_VSRAW, 2841 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2842 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, 2843 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2844 { ALTIVEC_BUILTIN_VEC_SRA, P8V_BUILTIN_VSRAD, 2845 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 2846 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, 2847 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2848 { ALTIVEC_BUILTIN_VEC_VSRAW, ALTIVEC_BUILTIN_VSRAW, 2849 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2850 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH, 2851 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2852 { ALTIVEC_BUILTIN_VEC_VSRAH, ALTIVEC_BUILTIN_VSRAH, 2853 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2854 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB, 2855 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2856 { ALTIVEC_BUILTIN_VEC_VSRAB, ALTIVEC_BUILTIN_VSRAB, 2857 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2858 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2859 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2860 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2861 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2862 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2863 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2864 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2865 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2866 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2867 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2868 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2869 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2870 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2871 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2872 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2873 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V8HI, 0 }, 2874 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2875 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2876 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2877 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2878 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2879 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2880 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2881 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2882 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2883 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2884 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2885 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2886 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2887 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2888 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2889 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2890 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2891 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2892 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2893 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2894 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2895 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V4SI, 0 }, 2896 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2897 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2898 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2899 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2900 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2901 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2902 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2903 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2904 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2905 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2906 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2907 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2908 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2909 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2910 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2911 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2912 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2913 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 2914 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2915 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V8HI, 0 }, 2916 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2917 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2918 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2919 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2920 { ALTIVEC_BUILTIN_VEC_SRL, ALTIVEC_BUILTIN_VSR, 2921 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2922 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2923 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V16QI, 0 }, 2924 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2925 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI, 0 }, 2926 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2927 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V16QI, 0 }, 2928 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2929 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2930 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2931 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V16QI, 0 }, 2932 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2933 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, 0 }, 2934 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2935 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V16QI, 0 }, 2936 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2937 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2938 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2939 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V16QI, 0 }, 2940 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2941 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2942 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2943 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_V16QI, 0 }, 2944 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2945 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI, 0 }, 2946 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2947 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2948 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2949 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2950 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2951 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 2952 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2953 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2954 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2955 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V16QI, 0 }, 2956 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2957 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2958 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2959 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V16QI, 0 }, 2960 { ALTIVEC_BUILTIN_VEC_SRO, ALTIVEC_BUILTIN_VSRO, 2961 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 0 }, 2962 2963 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2964 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 2965 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2966 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2967 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2968 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 2969 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2970 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2971 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2972 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 2973 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUBM, 2974 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 2975 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2976 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 2977 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2978 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2979 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2980 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 2981 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2982 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2983 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2984 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 2985 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUHM, 2986 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 2987 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2988 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 2989 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2990 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2991 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2992 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 2993 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2994 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2995 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2996 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 2997 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBUWM, 2998 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 2999 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 3000 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 3001 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 3002 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3003 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 3004 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 3005 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 3006 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 3007 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 3008 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3009 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUDM, 3010 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 3011 { ALTIVEC_BUILTIN_VEC_SUB, ALTIVEC_BUILTIN_VSUBFP, 3012 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 3013 { ALTIVEC_BUILTIN_VEC_SUB, VSX_BUILTIN_XVSUBDP, 3014 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 3015 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, 3016 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 3017 { ALTIVEC_BUILTIN_VEC_SUB, P8V_BUILTIN_VSUBUQM, 3018 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 3019 RS6000_BTI_unsigned_V1TI, 0 }, 3020 { ALTIVEC_BUILTIN_VEC_VSUBFP, ALTIVEC_BUILTIN_VSUBFP, 3021 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 3022 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 3023 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 3024 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 3025 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3026 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 3027 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3028 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 3029 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3030 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 3031 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3032 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 3033 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3034 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 3035 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 3036 { ALTIVEC_BUILTIN_VEC_VSUBUWM, ALTIVEC_BUILTIN_VSUBUWM, 3037 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3038 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 3039 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 3040 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 3041 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3042 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 3043 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 3044 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 3045 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3046 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 3047 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 3048 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 3049 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3050 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 3051 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3052 { ALTIVEC_BUILTIN_VEC_VSUBUHM, ALTIVEC_BUILTIN_VSUBUHM, 3053 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3054 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 3055 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 3056 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 3057 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3058 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 3059 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 3060 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 3061 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3062 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 3063 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 3064 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 3065 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3066 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 3067 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3068 { ALTIVEC_BUILTIN_VEC_VSUBUBM, ALTIVEC_BUILTIN_VSUBUBM, 3069 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3070 3071 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW, 3072 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3073 { ALTIVEC_BUILTIN_VEC_SUBC, ALTIVEC_BUILTIN_VSUBCUW, 3074 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3075 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ, 3076 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 3077 RS6000_BTI_unsigned_V1TI, 0 }, 3078 { ALTIVEC_BUILTIN_VEC_SUBC, P8V_BUILTIN_VSUBCUQ, 3079 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 3080 3081 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, 3082 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3083 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, 3084 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3085 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUBS, 3086 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3087 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, 3088 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 3089 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, 3090 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3091 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSBS, 3092 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 3093 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, 3094 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3095 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, 3096 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3097 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUHS, 3098 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3099 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, 3100 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 3101 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, 3102 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3103 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSHS, 3104 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 3105 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, 3106 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3107 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, 3108 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3109 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBUWS, 3110 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3111 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, 3112 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 3113 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, 3114 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3115 { ALTIVEC_BUILTIN_VEC_SUBS, ALTIVEC_BUILTIN_VSUBSWS, 3116 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3117 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, 3118 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3119 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, 3120 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 3121 { ALTIVEC_BUILTIN_VEC_VSUBSWS, ALTIVEC_BUILTIN_VSUBSWS, 3122 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3123 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 3124 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3125 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 3126 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0 }, 3127 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 3128 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3129 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 3130 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3131 { ALTIVEC_BUILTIN_VEC_VSUBUWS, ALTIVEC_BUILTIN_VSUBUWS, 3132 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3133 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, 3134 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 3135 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, 3136 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 3137 { ALTIVEC_BUILTIN_VEC_VSUBSHS, ALTIVEC_BUILTIN_VSUBSHS, 3138 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3139 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 3140 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3141 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 3142 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0 }, 3143 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 3144 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3145 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 3146 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3147 { ALTIVEC_BUILTIN_VEC_VSUBUHS, ALTIVEC_BUILTIN_VSUBUHS, 3148 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3149 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, 3150 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 3151 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, 3152 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 3153 { ALTIVEC_BUILTIN_VEC_VSUBSBS, ALTIVEC_BUILTIN_VSUBSBS, 3154 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3155 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 3156 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3157 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 3158 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0 }, 3159 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 3160 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3161 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 3162 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3163 { ALTIVEC_BUILTIN_VEC_VSUBUBS, ALTIVEC_BUILTIN_VSUBUBS, 3164 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3165 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4UBS, 3166 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 3167 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SBS, 3168 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 }, 3169 { ALTIVEC_BUILTIN_VEC_SUM4S, ALTIVEC_BUILTIN_VSUM4SHS, 3170 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 }, 3171 { ALTIVEC_BUILTIN_VEC_VSUM4SHS, ALTIVEC_BUILTIN_VSUM4SHS, 3172 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V4SI, 0 }, 3173 { ALTIVEC_BUILTIN_VEC_VSUM4SBS, ALTIVEC_BUILTIN_VSUM4SBS, 3174 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_V4SI, 0 }, 3175 { ALTIVEC_BUILTIN_VEC_VSUM4UBS, ALTIVEC_BUILTIN_VSUM4UBS, 3176 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 0 }, 3177 { ALTIVEC_BUILTIN_VEC_SUM2S, ALTIVEC_BUILTIN_VSUM2SWS, 3178 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3179 { ALTIVEC_BUILTIN_VEC_SUMS, ALTIVEC_BUILTIN_VSUMSWS, 3180 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3181 3182 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF, 3183 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 3184 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DF, 3185 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 3186 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI, 3187 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, 3188 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI, 3189 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_V1TI, 0 }, 3190 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V1TI, 3191 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, 3192 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 3193 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 3194 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 3195 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 3196 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 3197 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_INTDI, 0 }, 3198 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 3199 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3200 ~RS6000_BTI_unsigned_V2DI, 0 }, 3201 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 3202 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3203 ~RS6000_BTI_unsigned_long_long, 0 }, 3204 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVD2X_V2DI, 3205 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTDI, 0 }, 3206 3207 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF, 3208 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 3209 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SF, 3210 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 3211 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, 3212 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 3213 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, 3214 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 3215 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, 3216 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 3217 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V4SI, 3218 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 3219 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, 3220 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 3221 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, 3222 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 3223 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, 3224 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 3225 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V8HI, 3226 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 3227 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, 3228 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 3229 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, 3230 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 3231 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, 3232 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3233 ~RS6000_BTI_unsigned_V16QI, 0 }, 3234 { VSX_BUILTIN_VEC_XL, VSX_BUILTIN_LXVW4X_V16QI, 3235 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 3236 3237 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF, 3238 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 3239 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DF, 3240 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 3241 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI, 3242 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, 3243 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V1TI, 3244 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, 3245 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, 3246 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 3247 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, 3248 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 3249 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, 3250 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3251 ~RS6000_BTI_unsigned_V2DI, 0 }, 3252 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V2DI, 3253 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3254 ~RS6000_BTI_unsigned_long_long, 0 }, 3255 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF, 3256 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 3257 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SF, 3258 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 3259 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, 3260 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 3261 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, 3262 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 3263 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, 3264 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI, 0 }, 3265 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V4SI, 3266 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 3267 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, 3268 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 3269 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, 3270 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 3271 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, 3272 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI, 0 }, 3273 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V8HI, 3274 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 3275 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, 3276 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 3277 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, 3278 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 3279 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, 3280 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 3281 ~RS6000_BTI_unsigned_V16QI, 0 }, 3282 { VSX_BUILTIN_VEC_XL_BE, VSX_BUILTIN_LD_ELEMREV_V16QI, 3283 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 3284 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3285 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 3286 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3287 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, 0 }, 3288 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3289 RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, 0 }, 3290 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3291 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 3292 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3293 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, 0 }, 3294 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3295 RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, 0 }, 3296 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3297 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 3298 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3299 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3300 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3301 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 3302 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3303 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 3304 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3305 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3306 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3307 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 3308 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3309 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 3310 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3311 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3312 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3313 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 3314 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3315 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3316 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3317 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 3318 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3319 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3320 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3321 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 0 }, 3322 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3323 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 3324 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3325 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3326 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3327 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 3328 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3329 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3330 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3331 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 3332 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3333 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3334 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3335 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 0 }, 3336 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3337 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0 }, 3338 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3339 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 3340 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3341 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3342 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3343 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3344 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3345 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 3346 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3347 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3348 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3349 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 0 }, 3350 { ALTIVEC_BUILTIN_VEC_XOR, ALTIVEC_BUILTIN_VXOR, 3351 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0 }, 3352 3353 /* Ternary AltiVec/VSX builtins. */ 3354 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3355 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3356 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3357 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3358 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3359 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3360 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3361 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3362 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3363 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3364 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3365 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3366 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3367 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3368 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3369 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3370 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3371 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3372 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3373 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3374 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3375 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3376 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3377 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3378 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3379 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3380 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3381 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3382 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3383 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3384 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3385 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3386 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3387 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3388 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3389 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3390 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3391 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3392 { ALTIVEC_BUILTIN_VEC_DST, ALTIVEC_BUILTIN_DST, 3393 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3394 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3395 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3396 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3397 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3398 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3399 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3400 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3401 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3402 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3403 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3404 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3405 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3406 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3407 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3408 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3409 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3410 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3411 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3412 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3413 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3414 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3415 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3416 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3417 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3418 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3419 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3420 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3421 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3422 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3423 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3424 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3425 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3426 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3427 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3428 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3429 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3430 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3431 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3432 { ALTIVEC_BUILTIN_VEC_DSTST, ALTIVEC_BUILTIN_DSTST, 3433 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3434 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3435 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3436 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3437 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3438 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3439 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3440 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3441 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3442 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3443 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3444 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3445 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3446 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3447 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3448 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3449 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3450 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3451 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3452 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3453 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3454 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3455 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3456 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3457 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3458 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3459 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3460 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3461 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3462 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3463 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3464 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3465 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3466 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3467 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3468 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3469 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3470 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3471 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3472 { ALTIVEC_BUILTIN_VEC_DSTSTT, ALTIVEC_BUILTIN_DSTSTT, 3473 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3474 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3475 RS6000_BTI_void, ~RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3476 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3477 RS6000_BTI_void, ~RS6000_BTI_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3478 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3479 RS6000_BTI_void, ~RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3480 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3481 RS6000_BTI_void, ~RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3482 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3483 RS6000_BTI_void, ~RS6000_BTI_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3484 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3485 RS6000_BTI_void, ~RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3486 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3487 RS6000_BTI_void, ~RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3488 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3489 RS6000_BTI_void, ~RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3490 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3491 RS6000_BTI_void, ~RS6000_BTI_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3492 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3493 RS6000_BTI_void, ~RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3494 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3495 RS6000_BTI_void, ~RS6000_BTI_V4SF, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3496 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3497 RS6000_BTI_void, ~RS6000_BTI_UINTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3498 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3499 RS6000_BTI_void, ~RS6000_BTI_INTQI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3500 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3501 RS6000_BTI_void, ~RS6000_BTI_UINTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3502 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3503 RS6000_BTI_void, ~RS6000_BTI_INTHI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3504 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3505 RS6000_BTI_void, ~RS6000_BTI_UINTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3506 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3507 RS6000_BTI_void, ~RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3508 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3509 RS6000_BTI_void, ~RS6000_BTI_unsigned_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3510 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3511 RS6000_BTI_void, ~RS6000_BTI_long, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3512 { ALTIVEC_BUILTIN_VEC_DSTT, ALTIVEC_BUILTIN_DSTT, 3513 RS6000_BTI_void, ~RS6000_BTI_float, RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 3514 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMADDFP, 3515 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3516 { ALTIVEC_BUILTIN_VEC_MADD, VSX_BUILTIN_XVMADDDP, 3517 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3518 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, 3519 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3520 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, 3521 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3522 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, 3523 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3524 { ALTIVEC_BUILTIN_VEC_MADD, ALTIVEC_BUILTIN_VMLADDUHM, 3525 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3526 { ALTIVEC_BUILTIN_VEC_MADDS, ALTIVEC_BUILTIN_VMHADDSHS, 3527 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3528 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 3529 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3530 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 3531 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3532 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 3533 RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3534 { ALTIVEC_BUILTIN_VEC_MLADD, ALTIVEC_BUILTIN_VMLADDUHM, 3535 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3536 { ALTIVEC_BUILTIN_VEC_MRADDS, ALTIVEC_BUILTIN_VMHRADDSHS, 3537 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 3538 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBSP, 3539 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3540 { VSX_BUILTIN_VEC_MSUB, VSX_BUILTIN_XVMSUBDP, 3541 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3542 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUBM, 3543 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI }, 3544 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMMBM, 3545 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI }, 3546 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMUHM, 3547 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 3548 { ALTIVEC_BUILTIN_VEC_MSUM, ALTIVEC_BUILTIN_VMSUMSHM, 3549 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 3550 { ALTIVEC_BUILTIN_VEC_VMSUMSHM, ALTIVEC_BUILTIN_VMSUMSHM, 3551 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 3552 { ALTIVEC_BUILTIN_VEC_VMSUMUHM, ALTIVEC_BUILTIN_VMSUMUHM, 3553 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 3554 { ALTIVEC_BUILTIN_VEC_VMSUMMBM, ALTIVEC_BUILTIN_VMSUMMBM, 3555 RS6000_BTI_V4SI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI }, 3556 { ALTIVEC_BUILTIN_VEC_VMSUMUBM, ALTIVEC_BUILTIN_VMSUMUBM, 3557 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI }, 3558 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMUHS, 3559 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 3560 { ALTIVEC_BUILTIN_VEC_MSUMS, ALTIVEC_BUILTIN_VMSUMSHS, 3561 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 3562 { ALTIVEC_BUILTIN_VEC_VMSUMSHS, ALTIVEC_BUILTIN_VMSUMSHS, 3563 RS6000_BTI_V4SI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V4SI }, 3564 { ALTIVEC_BUILTIN_VEC_VMSUMUHS, ALTIVEC_BUILTIN_VMSUMUHS, 3565 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V4SI }, 3566 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDSP, 3567 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3568 { VSX_BUILTIN_VEC_NMADD, VSX_BUILTIN_XVNMADDDP, 3569 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3570 { ALTIVEC_BUILTIN_VEC_NMSUB, ALTIVEC_BUILTIN_VNMSUBFP, 3571 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3572 { ALTIVEC_BUILTIN_VEC_NMSUB, VSX_BUILTIN_XVNMSUBDP, 3573 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3574 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DF, 3575 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V16QI }, 3576 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, 3577 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V16QI }, 3578 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, 3579 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI }, 3580 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_2DI, 3581 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 3582 RS6000_BTI_unsigned_V16QI }, 3583 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SF, 3584 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V16QI }, 3585 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, 3586 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V16QI }, 3587 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, 3588 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V16QI }, 3589 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_4SI, 3590 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V16QI }, 3591 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 3592 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V16QI }, 3593 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 3594 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI }, 3595 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 3596 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V16QI }, 3597 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_8HI, 3598 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_unsigned_V16QI }, 3599 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3600 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI }, 3601 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3602 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3603 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3604 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3605 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3606 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3607 { ALTIVEC_BUILTIN_VEC_PERM, ALTIVEC_BUILTIN_VPERM_16QI, 3608 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 3609 3610 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR, 3611 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 3612 RS6000_BTI_bool_V16QI }, 3613 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR, 3614 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 3615 { P8V_BUILTIN_VEC_VPERMXOR, P8V_BUILTIN_VPERMXOR, 3616 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3617 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3618 3619 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3620 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_bool_V2DI }, 3621 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3622 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI }, 3623 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3624 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DI }, 3625 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DF, 3626 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 3627 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3628 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 3629 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3630 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI }, 3631 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3632 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 3633 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3634 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 3635 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3636 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 3637 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3638 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI }, 3639 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3640 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 3641 RS6000_BTI_bool_V2DI }, 3642 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_2DI, 3643 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 3644 RS6000_BTI_unsigned_V2DI }, 3645 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, 3646 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_bool_V4SI }, 3647 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SF, 3648 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI }, 3649 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3650 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 3651 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3652 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SI }, 3653 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3654 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 3655 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3656 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_unsigned_V4SI }, 3657 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3658 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 3659 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3660 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 3661 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3662 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, 3663 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_4SI, 3664 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 3665 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3666 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 3667 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3668 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_unsigned_V8HI }, 3669 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3670 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 3671 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3672 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 3673 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3674 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI }, 3675 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_8HI, 3676 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 3677 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3678 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 3679 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3680 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_unsigned_V16QI }, 3681 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3682 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 3683 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3684 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 3685 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3686 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 3687 { ALTIVEC_BUILTIN_VEC_SEL, ALTIVEC_BUILTIN_VSEL_16QI, 3688 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 3689 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SF, 3690 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, 3691 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3692 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, 3693 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3694 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI }, 3695 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_4SI, 3696 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI }, 3697 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3698 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, 3699 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3700 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI }, 3701 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3702 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI }, 3703 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_8HI, 3704 RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI }, 3705 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3706 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, 3707 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3708 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, 3709 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_16QI, 3710 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI }, 3711 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DF, 3712 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, 3713 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, 3714 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI }, 3715 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, 3716 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, 3717 { ALTIVEC_BUILTIN_VEC_SLD, ALTIVEC_BUILTIN_VSLDOI_2DI, 3718 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI }, 3719 3720 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, 3721 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 3722 RS6000_BTI_INTSI }, 3723 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_16QI, 3724 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 3725 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, 3726 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, 3727 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 3728 RS6000_BTI_INTSI }, 3729 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_8HI, 3730 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 3731 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI }, 3732 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, 3733 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 3734 RS6000_BTI_INTSI }, 3735 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_4SI, 3736 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 3737 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI }, 3738 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, 3739 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 3740 RS6000_BTI_INTSI }, 3741 { ALTIVEC_BUILTIN_VEC_SLDW, VSX_BUILTIN_XXSLDWI_2DI, 3742 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 3743 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI }, 3744 3745 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, 3746 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3747 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DF, 3748 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 3749 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3750 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3751 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3752 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long }, 3753 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3754 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3755 ~RS6000_BTI_unsigned_V2DI }, 3756 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3757 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3758 ~RS6000_BTI_unsigned_long_long }, 3759 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3760 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3761 ~RS6000_BTI_bool_V2DI }, 3762 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3763 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3764 ~RS6000_BTI_long_long }, 3765 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V2DI, 3766 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3767 ~RS6000_BTI_unsigned_long_long }, 3768 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, 3769 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3770 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SF, 3771 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3772 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3773 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3774 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3775 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3776 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3777 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3778 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3779 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3780 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3781 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3782 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3783 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3784 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V4SI, 3785 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3786 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3787 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3788 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3789 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3790 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3791 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3792 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3793 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3794 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3795 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3796 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3797 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3798 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3799 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3800 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3801 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3802 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3803 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3804 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3805 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3806 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3807 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3808 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3809 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3810 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3811 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3812 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V16QI, 3813 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3814 { ALTIVEC_BUILTIN_VEC_ST, ALTIVEC_BUILTIN_STVX_V8HI, 3815 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3816 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3817 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3818 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3819 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3820 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3821 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3822 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEBX, 3823 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3824 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3825 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3826 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3827 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3828 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3829 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3830 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3831 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3832 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3833 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3834 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEHX, 3835 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3836 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3837 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3838 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3839 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3840 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3841 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3842 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3843 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3844 { ALTIVEC_BUILTIN_VEC_STE, ALTIVEC_BUILTIN_STVEWX, 3845 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3846 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3847 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3848 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3849 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3850 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3851 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3852 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3853 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3854 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3855 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3856 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3857 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3858 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3859 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3860 { ALTIVEC_BUILTIN_VEC_STVEWX, ALTIVEC_BUILTIN_STVEWX, 3861 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3862 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3863 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3864 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3865 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3866 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3867 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3868 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3869 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3870 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3871 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3872 { ALTIVEC_BUILTIN_VEC_STVEHX, ALTIVEC_BUILTIN_STVEHX, 3873 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3874 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3875 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3876 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3877 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3878 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3879 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3880 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3881 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3882 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3883 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3884 { ALTIVEC_BUILTIN_VEC_STVEBX, ALTIVEC_BUILTIN_STVEBX, 3885 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_void }, 3886 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, 3887 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3888 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SF, 3889 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3890 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3891 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3892 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3893 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3894 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3895 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3896 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3897 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3898 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3899 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3900 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3901 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3902 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V4SI, 3903 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3904 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3905 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3906 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3907 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3908 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3909 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3910 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3911 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3912 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3913 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3914 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3915 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3916 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3917 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3918 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3919 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3920 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3921 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3922 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3923 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3924 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3925 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3926 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3927 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3928 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3929 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3930 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V16QI, 3931 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3932 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V8HI, 3933 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3934 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, 3935 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 3936 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DF, 3937 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 3938 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, 3939 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 3940 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, 3941 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 3942 ~RS6000_BTI_unsigned_V2DI }, 3943 { ALTIVEC_BUILTIN_VEC_STL, ALTIVEC_BUILTIN_STVXL_V2DI, 3944 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 3945 ~RS6000_BTI_bool_V2DI }, 3946 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3947 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3948 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3949 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3950 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3951 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3952 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3953 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3954 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3955 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3956 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3957 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3958 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3959 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3960 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3961 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3962 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3963 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 3964 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3965 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 3966 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3967 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 3968 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3969 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 3970 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3971 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 3972 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3973 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 3974 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3975 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 3976 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3977 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 3978 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3979 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 3980 { ALTIVEC_BUILTIN_VEC_STVLX, ALTIVEC_BUILTIN_STVLX, 3981 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 3982 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3983 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 3984 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3985 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 3986 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3987 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 3988 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3989 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 3990 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3991 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 3992 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3993 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 3994 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3995 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 3996 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3997 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 3998 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 3999 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 4000 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 4001 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 4002 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 4003 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 4004 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 4005 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 4006 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 4007 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 4008 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 4009 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 4010 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 4011 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 4012 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 4013 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 4014 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 4015 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 4016 { ALTIVEC_BUILTIN_VEC_STVLXL, ALTIVEC_BUILTIN_STVLXL, 4017 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 4018 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4019 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 4020 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4021 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 4022 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4023 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 4024 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4025 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 4026 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4027 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 4028 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4029 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 4030 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4031 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 4032 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4033 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 4034 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4035 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 4036 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4037 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 4038 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4039 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 4040 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4041 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 4042 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4043 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 4044 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4045 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 4046 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4047 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 4048 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4049 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 4050 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4051 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 4052 { ALTIVEC_BUILTIN_VEC_STVRX, ALTIVEC_BUILTIN_STVRX, 4053 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 4054 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4055 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 4056 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4057 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 4058 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4059 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 4060 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4061 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 4062 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4063 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 4064 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4065 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 4066 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4067 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 4068 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4069 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 4070 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4071 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 4072 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4073 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 4074 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4075 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 4076 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4077 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 4078 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4079 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 4080 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4081 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 4082 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4083 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 4084 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4085 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 4086 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4087 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 4088 { ALTIVEC_BUILTIN_VEC_STVRXL, ALTIVEC_BUILTIN_STVRXL, 4089 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 4090 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF, 4091 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 4092 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DF, 4093 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 4094 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, 4095 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 4096 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, 4097 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long }, 4098 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, RS6000_BTI_void, 4099 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long }, 4100 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, 4101 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 4102 ~RS6000_BTI_unsigned_V2DI }, 4103 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVD2X_V2DI, 4104 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 4105 ~RS6000_BTI_bool_V2DI }, 4106 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF, 4107 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 4108 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SF, 4109 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 4110 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 4111 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 4112 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 4113 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 4114 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 4115 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V4SI }, 4116 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 4117 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 4118 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 4119 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI }, 4120 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 4121 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI }, 4122 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V4SI, 4123 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 4124 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 4125 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 4126 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 4127 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 4128 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 4129 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V8HI }, 4130 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 4131 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 4132 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 4133 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI }, 4134 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 4135 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI }, 4136 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 4137 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 4138 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 4139 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 4140 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 4141 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 4142 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 4143 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_V16QI }, 4144 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 4145 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 4146 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 4147 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI }, 4148 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 4149 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI }, 4150 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V16QI, 4151 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 4152 { VSX_BUILTIN_VEC_XST, VSX_BUILTIN_STXVW4X_V8HI, 4153 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI }, 4154 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF, 4155 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 4156 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DF, 4157 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 4158 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI, 4159 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI }, 4160 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V1TI, 4161 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI }, 4162 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, 4163 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 4164 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, 4165 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, 4166 ~RS6000_BTI_long_long }, 4167 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, 4168 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 4169 ~RS6000_BTI_unsigned_V2DI }, 4170 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V2DI, 4171 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 4172 ~RS6000_BTI_unsigned_long_long }, 4173 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF, 4174 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 4175 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SF, 4176 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 4177 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, 4178 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 4179 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, 4180 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 4181 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, 4182 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 4183 ~RS6000_BTI_unsigned_V4SI }, 4184 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V4SI, 4185 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 4186 ~RS6000_BTI_UINTSI }, 4187 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, 4188 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 4189 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, 4190 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 4191 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, 4192 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 4193 ~RS6000_BTI_unsigned_V8HI }, 4194 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V8HI, 4195 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 4196 ~RS6000_BTI_UINTHI }, 4197 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, 4198 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 4199 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, 4200 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 4201 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, 4202 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 4203 ~RS6000_BTI_unsigned_V16QI }, 4204 { VSX_BUILTIN_VEC_XST_BE, VSX_BUILTIN_ST_ELEMREV_V16QI, 4205 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 4206 ~RS6000_BTI_UINTQI }, 4207 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, 4208 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, 4209 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_16QI, 4210 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4211 RS6000_BTI_INTSI }, 4212 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, 4213 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, 4214 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_8HI, 4215 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4216 RS6000_BTI_INTSI }, 4217 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, 4218 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, 4219 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SI, 4220 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4221 RS6000_BTI_INTSI }, 4222 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, 4223 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, 4224 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DI, 4225 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4226 RS6000_BTI_INTSI }, 4227 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_4SF, 4228 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, 4229 { VSX_BUILTIN_VEC_XXSLDWI, VSX_BUILTIN_XXSLDWI_2DF, 4230 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, 4231 4232 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DF, 4233 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_INTSI }, 4234 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, 4235 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_INTSI }, 4236 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_2DI, 4237 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4238 RS6000_BTI_INTSI }, 4239 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SF, 4240 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_INTSI }, 4241 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, 4242 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_INTSI }, 4243 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_4SI, 4244 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4245 RS6000_BTI_INTSI }, 4246 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, 4247 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_INTSI }, 4248 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_8HI, 4249 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4250 RS6000_BTI_INTSI }, 4251 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, 4252 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_INTSI }, 4253 { VSX_BUILTIN_VEC_XXPERMDI, VSX_BUILTIN_XXPERMDI_16QI, 4254 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4255 RS6000_BTI_INTSI }, 4256 4257 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, 4258 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF, 0 }, 4259 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DF, 4260 RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double, 0 }, 4261 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4262 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI, 0 }, 4263 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4264 RS6000_BTI_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_INTTI, 0 }, 4265 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4266 RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_long_long, 0 }, 4267 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4268 RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTTI, 0 }, 4269 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4270 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 4271 ~RS6000_BTI_unsigned_V2DI, 0 }, 4272 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4273 RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_unsigned_long_long, 0 }, 4274 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVD2X_V2DI, 4275 RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V2DI, 0 }, 4276 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, 4277 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF, 0 }, 4278 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SF, 4279 RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float, 0 }, 4280 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 4281 RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V4SI, 0 }, 4282 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 4283 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI, 0 }, 4284 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 4285 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI, 0 }, 4286 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 4287 RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_long, 0 }, 4288 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 4289 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 4290 ~RS6000_BTI_unsigned_V4SI, 0 }, 4291 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 4292 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTSI, 0 }, 4293 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V4SI, 4294 RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 4295 ~RS6000_BTI_unsigned_long, 0 }, 4296 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 4297 RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V8HI, 0 }, 4298 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 4299 RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_pixel_V8HI, 0 }, 4300 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 4301 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI, 0 }, 4302 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 4303 RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI, 0 }, 4304 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 4305 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 4306 ~RS6000_BTI_unsigned_V8HI, 0 }, 4307 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V8HI, 4308 RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTHI, 0 }, 4309 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 4310 RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_bool_V16QI, 0 }, 4311 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 4312 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI, 0 }, 4313 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 4314 RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI, 0 }, 4315 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 4316 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 4317 ~RS6000_BTI_unsigned_V16QI, 0 }, 4318 { VSX_BUILTIN_VEC_LD, VSX_BUILTIN_LXVW4X_V16QI, 4319 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_UINTQI, 0 }, 4320 4321 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, 4322 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_V2DF }, 4323 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DF, 4324 RS6000_BTI_void, RS6000_BTI_V2DF, RS6000_BTI_INTSI, ~RS6000_BTI_double }, 4325 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 4326 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTDI, 4327 ~RS6000_BTI_long_long }, 4328 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 4329 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTDI, 4330 ~RS6000_BTI_unsigned_long_long }, 4331 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI, 4332 RS6000_BTI_void, RS6000_BTI_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_INTTI }, 4333 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V1TI, 4334 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, RS6000_BTI_INTDI, ~RS6000_BTI_UINTTI }, 4335 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 4336 RS6000_BTI_void, RS6000_BTI_V2DI, RS6000_BTI_INTSI, ~RS6000_BTI_V2DI }, 4337 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 4338 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, RS6000_BTI_INTSI, 4339 ~RS6000_BTI_unsigned_V2DI }, 4340 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVD2X_V2DI, 4341 RS6000_BTI_void, RS6000_BTI_bool_V2DI, RS6000_BTI_INTSI, 4342 ~RS6000_BTI_bool_V2DI }, 4343 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, 4344 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_V4SF }, 4345 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SF, 4346 RS6000_BTI_void, RS6000_BTI_V4SF, RS6000_BTI_INTSI, ~RS6000_BTI_float }, 4347 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 4348 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_V4SI }, 4349 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 4350 RS6000_BTI_void, RS6000_BTI_V4SI, RS6000_BTI_INTSI, ~RS6000_BTI_INTSI }, 4351 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 4352 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 4353 ~RS6000_BTI_unsigned_V4SI }, 4354 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 4355 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, RS6000_BTI_INTSI, 4356 ~RS6000_BTI_UINTSI }, 4357 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 4358 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 4359 ~RS6000_BTI_bool_V4SI }, 4360 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 4361 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 4362 ~RS6000_BTI_UINTSI }, 4363 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V4SI, 4364 RS6000_BTI_void, RS6000_BTI_bool_V4SI, RS6000_BTI_INTSI, 4365 ~RS6000_BTI_INTSI }, 4366 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 4367 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_V8HI }, 4368 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 4369 RS6000_BTI_void, RS6000_BTI_V8HI, RS6000_BTI_INTSI, ~RS6000_BTI_INTHI }, 4370 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 4371 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 4372 ~RS6000_BTI_unsigned_V8HI }, 4373 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 4374 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, RS6000_BTI_INTSI, 4375 ~RS6000_BTI_UINTHI }, 4376 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 4377 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 4378 ~RS6000_BTI_bool_V8HI }, 4379 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 4380 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 4381 ~RS6000_BTI_UINTHI }, 4382 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V8HI, 4383 RS6000_BTI_void, RS6000_BTI_bool_V8HI, RS6000_BTI_INTSI, 4384 ~RS6000_BTI_INTHI }, 4385 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 4386 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_V16QI }, 4387 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 4388 RS6000_BTI_void, RS6000_BTI_V16QI, RS6000_BTI_INTSI, ~RS6000_BTI_INTQI }, 4389 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 4390 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 4391 ~RS6000_BTI_unsigned_V16QI }, 4392 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 4393 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 4394 ~RS6000_BTI_UINTQI }, 4395 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 4396 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 4397 ~RS6000_BTI_bool_V16QI }, 4398 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 4399 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 4400 ~RS6000_BTI_UINTQI }, 4401 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 4402 RS6000_BTI_void, RS6000_BTI_bool_V16QI, RS6000_BTI_INTSI, 4403 ~RS6000_BTI_INTQI }, 4404 { VSX_BUILTIN_VEC_ST, VSX_BUILTIN_STXVW4X_V16QI, 4405 RS6000_BTI_void, RS6000_BTI_pixel_V8HI, RS6000_BTI_INTSI, 4406 ~RS6000_BTI_pixel_V8HI }, 4407 4408 /* Predicates. */ 4409 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 4410 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 4411 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 4412 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 4413 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 4414 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 4415 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 4416 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, 4417 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 4418 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 4419 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 4420 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 4421 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 4422 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 4423 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 4424 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 4425 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 4426 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 4427 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 4428 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 4429 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 4430 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, 4431 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 4432 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 4433 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 4434 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 4435 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 4436 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 4437 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 4438 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 4439 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 4440 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, 4441 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 4442 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 4443 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 4444 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 4445 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, 4446 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, 4447 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, 4448 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 4449 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTUD_P, 4450 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 4451 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, 4452 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, 4453 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, 4454 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 4455 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, P8V_BUILTIN_VCMPGTSD_P, 4456 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 4457 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, ALTIVEC_BUILTIN_VCMPGTFP_P, 4458 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 4459 { ALTIVEC_BUILTIN_VEC_VCMPGT_P, VSX_BUILTIN_XVCMPGTDP_P, 4460 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 4461 4462 4463 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4464 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 4465 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4466 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 4467 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4468 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 4469 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4470 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, 4471 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4472 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 4473 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4474 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 4475 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUB_P, 4476 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI }, 4477 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4478 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 4479 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4480 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 4481 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4482 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 4483 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4484 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 4485 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4486 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, 4487 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4488 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 4489 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4490 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI }, 4491 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUH_P, 4492 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, RS6000_BTI_pixel_V8HI }, 4493 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4494 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 4495 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4496 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 4497 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4498 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 4499 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4500 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, 4501 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4502 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 4503 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4504 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 4505 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQUW_P, 4506 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI }, 4507 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4508 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, 4509 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4510 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 4511 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4512 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 4513 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4514 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, 4515 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4516 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 4517 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4518 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 4519 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, P8V_BUILTIN_VCMPEQUD_P, 4520 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI }, 4521 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, ALTIVEC_BUILTIN_VCMPEQFP_P, 4522 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 4523 { ALTIVEC_BUILTIN_VEC_VCMPEQ_P, VSX_BUILTIN_XVCMPEQDP_P, 4524 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 4525 4526 4527 /* cmpge is the same as cmpgt for all cases except floating point. 4528 There is further code to deal with this special case in 4529 altivec_build_resolved_builtin. */ 4530 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 4531 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI }, 4532 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 4533 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI }, 4534 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUB_P, 4535 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 4536 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 4537 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI }, 4538 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 4539 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI }, 4540 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSB_P, 4541 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 4542 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 4543 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI }, 4544 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 4545 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI }, 4546 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUH_P, 4547 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 4548 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 4549 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 4550 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 4551 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI }, 4552 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSH_P, 4553 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI }, 4554 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 4555 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI }, 4556 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 4557 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI }, 4558 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTUW_P, 4559 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 4560 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 4561 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI }, 4562 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 4563 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI }, 4564 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGTSW_P, 4565 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 4566 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, 4567 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI }, 4568 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, 4569 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI }, 4570 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTUD_P, 4571 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 4572 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, 4573 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI }, 4574 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, 4575 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI }, 4576 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, P8V_BUILTIN_VCMPGTSD_P, 4577 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI }, 4578 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, ALTIVEC_BUILTIN_VCMPGEFP_P, 4579 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF }, 4580 { ALTIVEC_BUILTIN_VEC_VCMPGE_P, VSX_BUILTIN_XVCMPGEDP_P, 4581 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF }, 4582 4583 /* Power8 vector overloaded functions. */ 4584 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4585 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 4586 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4587 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4588 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4589 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4590 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4591 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4592 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4593 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 4594 RS6000_BTI_unsigned_V16QI, 0 }, 4595 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4596 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4597 RS6000_BTI_bool_V16QI, 0 }, 4598 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V16QI, 4599 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4600 RS6000_BTI_unsigned_V16QI, 0 }, 4601 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4602 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 4603 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4604 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4605 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4606 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 4607 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4608 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4609 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4610 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 4611 RS6000_BTI_unsigned_V8HI, 0 }, 4612 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4613 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4614 RS6000_BTI_bool_V8HI, 0 }, 4615 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V8HI, 4616 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4617 RS6000_BTI_unsigned_V8HI, 0 }, 4618 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4619 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 4620 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4621 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4622 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4623 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4624 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4625 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4626 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4627 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 4628 RS6000_BTI_unsigned_V4SI, 0 }, 4629 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4630 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4631 RS6000_BTI_bool_V4SI, 0 }, 4632 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SI, 4633 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4634 RS6000_BTI_unsigned_V4SI, 0 }, 4635 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4636 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4637 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4638 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4639 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4640 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4641 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4642 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4643 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4644 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 4645 RS6000_BTI_unsigned_V2DI, 0 }, 4646 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4647 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4648 RS6000_BTI_bool_V2DI, 0 }, 4649 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DI, 4650 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4651 RS6000_BTI_unsigned_V2DI, 0 }, 4652 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V4SF, 4653 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 4654 { P8V_BUILTIN_VEC_EQV, P8V_BUILTIN_EQV_V2DF, 4655 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 4656 4657 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4658 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 4659 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4660 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4661 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4662 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4663 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4664 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 4665 RS6000_BTI_unsigned_V16QI, 0 }, 4666 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4667 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4668 RS6000_BTI_bool_V16QI, 0 }, 4669 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4670 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4671 RS6000_BTI_unsigned_V16QI, 0 }, 4672 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V16QI, 4673 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4674 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4675 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 4676 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4677 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4678 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4679 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 4680 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4681 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 4682 RS6000_BTI_unsigned_V8HI, 0 }, 4683 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4684 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4685 RS6000_BTI_bool_V8HI, 0 }, 4686 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4687 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4688 RS6000_BTI_unsigned_V8HI, 0 }, 4689 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V8HI, 4690 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4691 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4692 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 4693 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4694 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4695 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4696 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4697 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4698 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 4699 RS6000_BTI_unsigned_V4SI, 0 }, 4700 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4701 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4702 RS6000_BTI_bool_V4SI, 0 }, 4703 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4704 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4705 RS6000_BTI_unsigned_V4SI, 0 }, 4706 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SI, 4707 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4708 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4709 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4710 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4711 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4712 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4713 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4714 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4715 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 4716 RS6000_BTI_unsigned_V2DI, 0 }, 4717 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4718 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4719 RS6000_BTI_bool_V2DI, 0 }, 4720 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4721 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4722 RS6000_BTI_unsigned_V2DI, 0 }, 4723 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DI, 4724 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4725 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V4SF, 4726 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 4727 { P8V_BUILTIN_VEC_NAND, P8V_BUILTIN_NAND_V2DF, 4728 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 4729 4730 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4731 RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 0 }, 4732 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4733 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4734 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4735 RS6000_BTI_V16QI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4736 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4737 RS6000_BTI_unsigned_V16QI, RS6000_BTI_bool_V16QI, 4738 RS6000_BTI_unsigned_V16QI, 0 }, 4739 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4740 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4741 RS6000_BTI_bool_V16QI, 0 }, 4742 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4743 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4744 RS6000_BTI_unsigned_V16QI, 0 }, 4745 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V16QI, 4746 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0 }, 4747 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4748 RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 0 }, 4749 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4750 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4751 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4752 RS6000_BTI_V8HI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 4753 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4754 RS6000_BTI_unsigned_V8HI, RS6000_BTI_bool_V8HI, 4755 RS6000_BTI_unsigned_V8HI, 0 }, 4756 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4757 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4758 RS6000_BTI_bool_V8HI, 0 }, 4759 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4760 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4761 RS6000_BTI_unsigned_V8HI, 0 }, 4762 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V8HI, 4763 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0 }, 4764 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4765 RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 0 }, 4766 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4767 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4768 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4769 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 4770 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4771 RS6000_BTI_unsigned_V4SI, RS6000_BTI_bool_V4SI, 4772 RS6000_BTI_unsigned_V4SI, 0 }, 4773 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4774 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4775 RS6000_BTI_bool_V4SI, 0 }, 4776 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4777 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4778 RS6000_BTI_unsigned_V4SI, 0 }, 4779 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SI, 4780 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 4781 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4782 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4783 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4784 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4785 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4786 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4787 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4788 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 4789 RS6000_BTI_unsigned_V2DI, 0 }, 4790 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4791 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4792 RS6000_BTI_bool_V2DI, 0 }, 4793 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4794 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4795 RS6000_BTI_unsigned_V2DI, 0 }, 4796 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DI, 4797 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4798 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V4SF, 4799 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 4800 { P8V_BUILTIN_VEC_ORC, P8V_BUILTIN_ORC_V2DF, 4801 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 4802 4803 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, 4804 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 4805 { P8V_BUILTIN_VEC_VADDCUQ, P8V_BUILTIN_VADDCUQ, 4806 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4807 RS6000_BTI_unsigned_V1TI, 0 }, 4808 4809 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4810 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 4811 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4812 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4813 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4814 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 4815 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4816 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4817 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4818 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 4819 { P8V_BUILTIN_VEC_VADDUDM, P8V_BUILTIN_VADDUDM, 4820 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 4821 4822 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, 4823 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 4824 { P8V_BUILTIN_VEC_VADDUQM, P8V_BUILTIN_VADDUQM, 4825 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 4826 RS6000_BTI_unsigned_V1TI, 0 }, 4827 4828 { P9V_BUILTIN_VEC_VBPERM, P9V_BUILTIN_VBPERMD, 4829 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4830 RS6000_BTI_unsigned_V16QI, 0 }, 4831 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ, 4832 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI, 4833 RS6000_BTI_unsigned_V16QI, 0 }, 4834 { P9V_BUILTIN_VEC_VBPERM, P8V_BUILTIN_VBPERMQ2, 4835 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4836 RS6000_BTI_unsigned_V16QI, 0 }, 4837 4838 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 4839 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 4840 RS6000_BTI_unsigned_V16QI, 0 }, 4841 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 4842 RS6000_BTI_V2DI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 4843 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 4844 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, 4845 RS6000_BTI_unsigned_V16QI, 0 }, 4846 { P8V_BUILTIN_VEC_VBPERMQ, P8V_BUILTIN_VBPERMQ, 4847 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V1TI, 4848 RS6000_BTI_unsigned_V16QI, 0 }, 4849 4850 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, 4851 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4852 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZB, 4853 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4854 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, 4855 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4856 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZH, 4857 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4858 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, 4859 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4860 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZW, 4861 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4862 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, 4863 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4864 { P8V_BUILTIN_VEC_VCLZ, P8V_BUILTIN_VCLZD, 4865 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4866 4867 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, 4868 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4869 { P8V_BUILTIN_VEC_VCLZB, P8V_BUILTIN_VCLZB, 4870 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4871 4872 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, 4873 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4874 { P8V_BUILTIN_VEC_VCLZH, P8V_BUILTIN_VCLZH, 4875 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4876 4877 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, 4878 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4879 { P8V_BUILTIN_VEC_VCLZW, P8V_BUILTIN_VCLZW, 4880 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4881 4882 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, 4883 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4884 { P8V_BUILTIN_VEC_VCLZD, P8V_BUILTIN_VCLZD, 4885 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4886 4887 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_TD, 4888 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4889 { P9_BUILTIN_DFP_TSTSFI_LT, MISC_BUILTIN_TSTSFI_LT_DD, 4890 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4891 4892 { P9_BUILTIN_DFP_TSTSFI_LT_TD, MISC_BUILTIN_TSTSFI_LT_TD, 4893 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4894 { P9_BUILTIN_DFP_TSTSFI_LT_DD, MISC_BUILTIN_TSTSFI_LT_DD, 4895 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4896 4897 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_TD, 4898 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4899 { P9_BUILTIN_DFP_TSTSFI_EQ, MISC_BUILTIN_TSTSFI_EQ_DD, 4900 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4901 4902 { P9_BUILTIN_DFP_TSTSFI_EQ_TD, MISC_BUILTIN_TSTSFI_EQ_TD, 4903 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4904 { P9_BUILTIN_DFP_TSTSFI_EQ_DD, MISC_BUILTIN_TSTSFI_EQ_DD, 4905 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4906 4907 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_TD, 4908 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4909 { P9_BUILTIN_DFP_TSTSFI_GT, MISC_BUILTIN_TSTSFI_GT_DD, 4910 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4911 4912 { P9_BUILTIN_DFP_TSTSFI_GT_TD, MISC_BUILTIN_TSTSFI_GT_TD, 4913 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4914 { P9_BUILTIN_DFP_TSTSFI_GT_DD, MISC_BUILTIN_TSTSFI_GT_DD, 4915 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4916 4917 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_TD, 4918 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4919 { P9_BUILTIN_DFP_TSTSFI_OV, MISC_BUILTIN_TSTSFI_OV_DD, 4920 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4921 4922 { P9_BUILTIN_DFP_TSTSFI_OV_TD, MISC_BUILTIN_TSTSFI_OV_TD, 4923 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat128, 0 }, 4924 { P9_BUILTIN_DFP_TSTSFI_OV_DD, MISC_BUILTIN_TSTSFI_OV_DD, 4925 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, RS6000_BTI_dfloat64, 0 }, 4926 4927 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, 4928 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4929 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZB, 4930 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4931 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH, 4932 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4933 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZH, 4934 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4935 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW, 4936 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4937 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZW, 4938 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4939 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD, 4940 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4941 { P9V_BUILTIN_VEC_VCTZ, P9V_BUILTIN_VCTZD, 4942 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4943 4944 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB, 4945 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 4946 { P9V_BUILTIN_VEC_VCTZB, P9V_BUILTIN_VCTZB, 4947 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 4948 4949 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH, 4950 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 4951 { P9V_BUILTIN_VEC_VCTZH, P9V_BUILTIN_VCTZH, 4952 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 4953 4954 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW, 4955 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 4956 { P9V_BUILTIN_VEC_VCTZW, P9V_BUILTIN_VCTZW, 4957 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 4958 4959 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD, 4960 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 4961 { P9V_BUILTIN_VEC_VCTZD, P9V_BUILTIN_VCTZD, 4962 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 4963 4964 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUB, 4965 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4966 RS6000_BTI_unsigned_V16QI, 0 }, 4967 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUH, 4968 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4969 RS6000_BTI_unsigned_V8HI, 0 }, 4970 { P9V_BUILTIN_VEC_VADU, P9V_BUILTIN_VADUW, 4971 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4972 RS6000_BTI_unsigned_V4SI, 0 }, 4973 4974 { P9V_BUILTIN_VEC_VADUB, P9V_BUILTIN_VADUB, 4975 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 4976 RS6000_BTI_unsigned_V16QI, 0 }, 4977 4978 { P9V_BUILTIN_VEC_VADUH, P9V_BUILTIN_VADUH, 4979 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 4980 RS6000_BTI_unsigned_V8HI, 0 }, 4981 4982 { P9V_BUILTIN_VEC_VADUW, P9V_BUILTIN_VADUW, 4983 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 4984 RS6000_BTI_unsigned_V4SI, 0 }, 4985 4986 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESSP, 4987 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 4988 { P9V_BUILTIN_VEC_VES, P9V_BUILTIN_VESDP, 4989 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 4990 4991 { P9V_BUILTIN_VEC_VESSP, P9V_BUILTIN_VESSP, 4992 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 4993 { P9V_BUILTIN_VEC_VESDP, P9V_BUILTIN_VESDP, 4994 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 4995 4996 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEESP, 4997 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 4998 { P9V_BUILTIN_VEC_VEE, P9V_BUILTIN_VEEDP, 4999 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 5000 5001 { P9V_BUILTIN_VEC_VEESP, P9V_BUILTIN_VEESP, 5002 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 5003 { P9V_BUILTIN_VEC_VEEDP, P9V_BUILTIN_VEEDP, 5004 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 5005 5006 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCSP, 5007 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 5008 { P9V_BUILTIN_VEC_VTDC, P9V_BUILTIN_VTDCDP, 5009 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 5010 5011 { P9V_BUILTIN_VEC_VTDCSP, P9V_BUILTIN_VTDCSP, 5012 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SF, RS6000_BTI_INTSI, 0 }, 5013 { P9V_BUILTIN_VEC_VTDCDP, P9V_BUILTIN_VTDCDP, 5014 RS6000_BTI_bool_V2DI, RS6000_BTI_V2DF, RS6000_BTI_INTSI, 0 }, 5015 5016 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP, 5017 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 5018 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIESP, 5019 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 }, 5020 5021 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP, 5022 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5023 { P9V_BUILTIN_VEC_VIE, P9V_BUILTIN_VIEDP, 5024 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 }, 5025 5026 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP, 5027 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0 }, 5028 { P9V_BUILTIN_VEC_VIESP, P9V_BUILTIN_VIESP, 5029 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_unsigned_V4SI, 0 }, 5030 5031 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP, 5032 RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5033 { P9V_BUILTIN_VEC_VIEDP, P9V_BUILTIN_VIEDP, 5034 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_unsigned_V2DI, 0 }, 5035 5036 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCSP, 5037 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 }, 5038 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCDP, 5039 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, 5040 { P9V_BUILTIN_VEC_VSTDC, P9V_BUILTIN_VSTDCQP, 5041 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, 5042 5043 { P9V_BUILTIN_VEC_VSTDCSP, P9V_BUILTIN_VSTDCSP, 5044 RS6000_BTI_bool_int, RS6000_BTI_float, RS6000_BTI_INTSI, 0 }, 5045 { P9V_BUILTIN_VEC_VSTDCDP, P9V_BUILTIN_VSTDCDP, 5046 RS6000_BTI_bool_int, RS6000_BTI_double, RS6000_BTI_INTSI, 0 }, 5047 { P9V_BUILTIN_VEC_VSTDCQP, P9V_BUILTIN_VSTDCQP, 5048 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, RS6000_BTI_INTSI, 0 }, 5049 5050 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNSP, 5051 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, 5052 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNDP, 5053 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, 5054 { P9V_BUILTIN_VEC_VSTDCN, P9V_BUILTIN_VSTDCNQP, 5055 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, 5056 5057 { P9V_BUILTIN_VEC_VSTDCNSP, P9V_BUILTIN_VSTDCNSP, 5058 RS6000_BTI_bool_int, RS6000_BTI_float, 0, 0 }, 5059 { P9V_BUILTIN_VEC_VSTDCNDP, P9V_BUILTIN_VSTDCNDP, 5060 RS6000_BTI_bool_int, RS6000_BTI_double, 0, 0 }, 5061 { P9V_BUILTIN_VEC_VSTDCNQP, P9V_BUILTIN_VSTDCNQP, 5062 RS6000_BTI_bool_int, RS6000_BTI_ieee128_float, 0, 0 }, 5063 5064 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEDP, 5065 RS6000_BTI_UINTSI, RS6000_BTI_double, 0, 0 }, 5066 { P9V_BUILTIN_VEC_VSEEDP, P9V_BUILTIN_VSEEQP, 5067 RS6000_BTI_UINTDI, RS6000_BTI_ieee128_float, 0, 0 }, 5068 5069 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESDP, 5070 RS6000_BTI_UINTDI, RS6000_BTI_double, 0, 0 }, 5071 { P9V_BUILTIN_VEC_VSESDP, P9V_BUILTIN_VSESQP, 5072 RS6000_BTI_UINTTI, RS6000_BTI_ieee128_float, 0, 0 }, 5073 5074 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDP, 5075 RS6000_BTI_double, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 }, 5076 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEDPF, 5077 RS6000_BTI_double, RS6000_BTI_double, RS6000_BTI_UINTDI, 0 }, 5078 5079 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQP, 5080 RS6000_BTI_ieee128_float, RS6000_BTI_UINTTI, RS6000_BTI_UINTDI, 0 }, 5081 { P9V_BUILTIN_VEC_VSIEDP, P9V_BUILTIN_VSIEQPF, 5082 RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, RS6000_BTI_UINTDI, 0 }, 5083 5084 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEDPGT, 5085 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, 5086 { P9V_BUILTIN_VEC_VSCEGT, P9V_BUILTIN_VSCEQPGT, 5087 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, 5088 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEDPLT, 5089 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, 5090 { P9V_BUILTIN_VEC_VSCELT, P9V_BUILTIN_VSCEQPLT, 5091 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, 5092 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEDPEQ, 5093 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, 5094 { P9V_BUILTIN_VEC_VSCEEQ, P9V_BUILTIN_VSCEQPEQ, 5095 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, 5096 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEDPUO, 5097 RS6000_BTI_INTSI, RS6000_BTI_double, RS6000_BTI_double, 0 }, 5098 { P9V_BUILTIN_VEC_VSCEUO, P9V_BUILTIN_VSCEQPUO, 5099 RS6000_BTI_INTSI, RS6000_BTI_ieee128_float, RS6000_BTI_ieee128_float, 0 }, 5100 5101 { P9V_BUILTIN_VEC_XL_LEN_R, P9V_BUILTIN_XL_LEN_R, 5102 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, 5103 RS6000_BTI_unsigned_long_long, 0 }, 5104 5105 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5106 RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, 5107 RS6000_BTI_unsigned_long_long, 0 }, 5108 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5109 RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, 5110 RS6000_BTI_unsigned_long_long, 0 }, 5111 5112 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5113 RS6000_BTI_V4SI, ~RS6000_BTI_INTSI, 5114 RS6000_BTI_unsigned_long_long, 0 }, 5115 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5116 RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI, 5117 RS6000_BTI_unsigned_long_long, 0 }, 5118 5119 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5120 RS6000_BTI_V1TI, ~RS6000_BTI_INTTI, 5121 RS6000_BTI_unsigned_long_long, 0 }, 5122 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5123 RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI, 5124 RS6000_BTI_unsigned_long_long, 0 }, 5125 5126 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5127 RS6000_BTI_V2DI, ~RS6000_BTI_long_long, 5128 RS6000_BTI_unsigned_long_long, 0 }, 5129 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5130 RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long, 5131 RS6000_BTI_unsigned_long_long, 0 }, 5132 5133 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5134 RS6000_BTI_V8HI, ~RS6000_BTI_INTHI, 5135 RS6000_BTI_unsigned_long_long, 0 }, 5136 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5137 RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI, 5138 RS6000_BTI_unsigned_long_long, 0 }, 5139 5140 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5141 RS6000_BTI_V2DF, ~RS6000_BTI_double, 5142 RS6000_BTI_unsigned_long_long, 0 }, 5143 { P9V_BUILTIN_VEC_LXVL, P9V_BUILTIN_LXVL, 5144 RS6000_BTI_V4SF, ~RS6000_BTI_float, 5145 RS6000_BTI_unsigned_long_long, 0 }, 5146 /* At an appropriate future time, add support for the 5147 RS6000_BTI_Float16 (exact name to be determined) type here. */ 5148 5149 { P9V_BUILTIN_VEC_XST_LEN_R, P9V_BUILTIN_XST_LEN_R, 5150 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, 5151 ~RS6000_BTI_UINTQI, RS6000_BTI_unsigned_long_long}, 5152 5153 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5154 RS6000_BTI_void, RS6000_BTI_V16QI, ~RS6000_BTI_INTQI, 5155 RS6000_BTI_unsigned_long_long }, 5156 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5157 RS6000_BTI_void, RS6000_BTI_unsigned_V16QI, ~RS6000_BTI_UINTQI, 5158 RS6000_BTI_unsigned_long_long }, 5159 5160 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5161 RS6000_BTI_void, RS6000_BTI_V4SI, ~RS6000_BTI_INTSI, 5162 RS6000_BTI_unsigned_long_long }, 5163 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5164 RS6000_BTI_void, RS6000_BTI_unsigned_V4SI, ~RS6000_BTI_UINTSI, 5165 RS6000_BTI_unsigned_long_long }, 5166 5167 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5168 RS6000_BTI_void, RS6000_BTI_V1TI, ~RS6000_BTI_INTTI, 5169 RS6000_BTI_unsigned_long_long }, 5170 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5171 RS6000_BTI_void, RS6000_BTI_unsigned_V1TI, ~RS6000_BTI_UINTTI, 5172 RS6000_BTI_unsigned_long_long }, 5173 5174 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5175 RS6000_BTI_void, RS6000_BTI_V2DI, ~RS6000_BTI_long_long, 5176 RS6000_BTI_unsigned_long_long }, 5177 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5178 RS6000_BTI_void, RS6000_BTI_unsigned_V2DI, ~RS6000_BTI_unsigned_long_long, 5179 RS6000_BTI_unsigned_long_long }, 5180 5181 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5182 RS6000_BTI_void, RS6000_BTI_V8HI, ~RS6000_BTI_INTHI, 5183 RS6000_BTI_unsigned_long_long }, 5184 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5185 RS6000_BTI_void, RS6000_BTI_unsigned_V8HI, ~RS6000_BTI_UINTHI, 5186 RS6000_BTI_unsigned_long_long }, 5187 5188 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5189 RS6000_BTI_void, RS6000_BTI_V2DF, ~RS6000_BTI_double, 5190 RS6000_BTI_unsigned_long_long }, 5191 { P9V_BUILTIN_VEC_STXVL, P9V_BUILTIN_STXVL, 5192 RS6000_BTI_void, RS6000_BTI_V4SF, ~RS6000_BTI_float, 5193 RS6000_BTI_unsigned_long_long }, 5194 /* At an appropriate future time, add support for the 5195 RS6000_BTI_Float16 (exact name to be determined) type here. */ 5196 5197 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, 5198 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 5199 RS6000_BTI_bool_V16QI, 0 }, 5200 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, 5201 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 5202 RS6000_BTI_V16QI, 0 }, 5203 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEB, 5204 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 5205 RS6000_BTI_unsigned_V16QI, 0 }, 5206 5207 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH, 5208 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 5209 RS6000_BTI_bool_V8HI, 0 }, 5210 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH, 5211 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 5212 RS6000_BTI_V8HI, 0 }, 5213 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEH, 5214 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 5215 RS6000_BTI_unsigned_V8HI, 0 }, 5216 5217 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, 5218 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 5219 RS6000_BTI_bool_V4SI, 0 }, 5220 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, 5221 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 5222 RS6000_BTI_V4SI, 0 }, 5223 { ALTIVEC_BUILTIN_VEC_CMPNE, P9V_BUILTIN_CMPNEW, 5224 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 5225 RS6000_BTI_unsigned_V4SI, 0 }, 5226 5227 /* The following 2 entries have been deprecated. */ 5228 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 5229 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 5230 RS6000_BTI_unsigned_V16QI, 0 }, 5231 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 5232 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 5233 RS6000_BTI_bool_V16QI, 0 }, 5234 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 5235 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 5236 RS6000_BTI_unsigned_V16QI, 0 }, 5237 5238 /* The following 2 entries have been deprecated. */ 5239 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 5240 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 5241 RS6000_BTI_V16QI, 0 }, 5242 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 5243 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 5244 RS6000_BTI_bool_V16QI, 0 }, 5245 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 5246 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 5247 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEB_P, 5248 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 5249 RS6000_BTI_bool_V16QI, 0 }, 5250 5251 /* The following 2 entries have been deprecated. */ 5252 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 5253 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 5254 RS6000_BTI_unsigned_V8HI, 0 }, 5255 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 5256 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 5257 RS6000_BTI_bool_V8HI, 0 }, 5258 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 5259 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 5260 RS6000_BTI_unsigned_V8HI, 0 }, 5261 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 5262 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 5263 5264 /* The following 2 entries have been deprecated. */ 5265 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 5266 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 5267 RS6000_BTI_V8HI, 0 }, 5268 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 5269 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 5270 RS6000_BTI_bool_V8HI, 0 }, 5271 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 5272 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 5273 RS6000_BTI_bool_V8HI, 0 }, 5274 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEH_P, 5275 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, 5276 RS6000_BTI_pixel_V8HI, 0 }, 5277 5278 /* The following 2 entries have been deprecated. */ 5279 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 5280 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 5281 RS6000_BTI_unsigned_V4SI, 0 }, 5282 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 5283 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 5284 RS6000_BTI_bool_V4SI, 0 }, 5285 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 5286 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 5287 RS6000_BTI_unsigned_V4SI, 0 }, 5288 5289 /* The following 2 entries have been deprecated. */ 5290 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 5291 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 5292 RS6000_BTI_V4SI, 0 }, 5293 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 5294 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 5295 RS6000_BTI_bool_V4SI, 0 }, 5296 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 5297 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 5298 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEW_P, 5299 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 5300 RS6000_BTI_bool_V4SI, 0 }, 5301 5302 /* The following 2 entries have been deprecated. */ 5303 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 5304 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 5305 RS6000_BTI_unsigned_V2DI, 0 }, 5306 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 5307 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 5308 RS6000_BTI_bool_V2DI, 0 }, 5309 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 5310 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 5311 RS6000_BTI_unsigned_V2DI, 0 5312 }, 5313 5314 /* The following 2 entries have been deprecated. */ 5315 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 5316 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 5317 RS6000_BTI_V2DI, 0 }, 5318 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 5319 RS6000_BTI_INTSI, RS6000_BTI_V2DI, 5320 RS6000_BTI_bool_V2DI, 0 }, 5321 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 5322 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5323 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNED_P, 5324 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 5325 RS6000_BTI_bool_V2DI, 0 }, 5326 5327 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEFP_P, 5328 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 5329 { P9V_BUILTIN_VEC_VCMPNE_P, P9V_BUILTIN_VCMPNEDP_P, 5330 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 5331 5332 /* The following 2 entries have been deprecated. */ 5333 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 5334 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 5335 RS6000_BTI_unsigned_V16QI, 0 }, 5336 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 5337 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 5338 RS6000_BTI_bool_V16QI, 0 }, 5339 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 5340 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 5341 RS6000_BTI_unsigned_V16QI, 0 }, 5342 5343 /* The following 2 entries have been deprecated. */ 5344 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 5345 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 5346 RS6000_BTI_V16QI, 0 }, 5347 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 5348 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 5349 RS6000_BTI_bool_V16QI, 0 }, 5350 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 5351 RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0 }, 5352 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEB_P, 5353 RS6000_BTI_INTSI, RS6000_BTI_bool_V16QI, 5354 RS6000_BTI_bool_V16QI, 0 }, 5355 5356 /* The following 2 entries have been deprecated. */ 5357 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 5358 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 5359 RS6000_BTI_unsigned_V8HI, 0 }, 5360 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 5361 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 5362 RS6000_BTI_bool_V8HI, 0 }, 5363 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 5364 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 5365 RS6000_BTI_unsigned_V8HI, 0 }, 5366 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 5367 RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0 }, 5368 5369 /* The following 2 entries have been deprecated. */ 5370 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 5371 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 5372 RS6000_BTI_V8HI, 0 }, 5373 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 5374 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 5375 RS6000_BTI_bool_V8HI, 0 }, 5376 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 5377 RS6000_BTI_INTSI, RS6000_BTI_bool_V8HI, 5378 RS6000_BTI_bool_V8HI, 0 }, 5379 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEH_P, 5380 RS6000_BTI_INTSI, RS6000_BTI_pixel_V8HI, 5381 RS6000_BTI_pixel_V8HI, 0 }, 5382 5383 /* The following 2 entries have been deprecated. */ 5384 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 5385 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 5386 RS6000_BTI_unsigned_V4SI, 0 }, 5387 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 5388 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 5389 RS6000_BTI_bool_V4SI, 0 }, 5390 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 5391 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 5392 RS6000_BTI_unsigned_V4SI, 0 }, 5393 5394 /* The following 2 entries have been deprecated. */ 5395 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 5396 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 5397 RS6000_BTI_V4SI, 0 }, 5398 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 5399 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 5400 RS6000_BTI_bool_V4SI, 0 }, 5401 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 5402 RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 5403 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEW_P, 5404 RS6000_BTI_INTSI, RS6000_BTI_bool_V4SI, 5405 RS6000_BTI_bool_V4SI, 0 }, 5406 5407 /* The following 2 entries have been deprecated. */ 5408 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 5409 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 5410 RS6000_BTI_unsigned_V2DI, 0 }, 5411 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 5412 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 5413 RS6000_BTI_bool_V2DI, 0 }, 5414 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 5415 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V2DI, 5416 RS6000_BTI_unsigned_V2DI, 0 5417 }, 5418 5419 /* The following 2 entries have been deprecated. */ 5420 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 5421 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 5422 RS6000_BTI_V2DI, 0 }, 5423 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 5424 RS6000_BTI_INTSI, RS6000_BTI_V2DI, 5425 RS6000_BTI_bool_V2DI, 0 }, 5426 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 5427 RS6000_BTI_INTSI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5428 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAED_P, 5429 RS6000_BTI_INTSI, RS6000_BTI_bool_V2DI, 5430 RS6000_BTI_bool_V2DI, 0 }, 5431 5432 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEFP_P, 5433 RS6000_BTI_INTSI, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 5434 { P9V_BUILTIN_VEC_VCMPAE_P, P9V_BUILTIN_VCMPAEDP_P, 5435 RS6000_BTI_INTSI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 5436 5437 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P, 5438 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 5439 RS6000_BTI_unsigned_V16QI }, 5440 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZB_P, 5441 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V16QI, RS6000_BTI_V16QI }, 5442 5443 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P, 5444 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V8HI, 5445 RS6000_BTI_unsigned_V8HI }, 5446 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZH_P, 5447 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V8HI, RS6000_BTI_V8HI }, 5448 5449 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P, 5450 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_unsigned_V4SI, 5451 RS6000_BTI_unsigned_V4SI }, 5452 { P9V_BUILTIN_VEC_VCMPNEZ_P, P9V_BUILTIN_VCMPNEZW_P, 5453 RS6000_BTI_INTSI, RS6000_BTI_INTSI, RS6000_BTI_V4SI, RS6000_BTI_V4SI }, 5454 5455 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB, 5456 RS6000_BTI_bool_V16QI, RS6000_BTI_V16QI, 5457 RS6000_BTI_V16QI, 0 }, 5458 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZB, 5459 RS6000_BTI_bool_V16QI, RS6000_BTI_unsigned_V16QI, 5460 RS6000_BTI_unsigned_V16QI, 0 }, 5461 5462 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH, 5463 RS6000_BTI_bool_V8HI, RS6000_BTI_V8HI, 5464 RS6000_BTI_V8HI, 0 }, 5465 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZH, 5466 RS6000_BTI_bool_V8HI, RS6000_BTI_unsigned_V8HI, 5467 RS6000_BTI_unsigned_V8HI, 0 }, 5468 5469 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW, 5470 RS6000_BTI_bool_V4SI, RS6000_BTI_V4SI, 5471 RS6000_BTI_V4SI, 0 }, 5472 { P9V_BUILTIN_VEC_CMPNEZ, P9V_BUILTIN_CMPNEZW, 5473 RS6000_BTI_bool_V4SI, RS6000_BTI_unsigned_V4SI, 5474 RS6000_BTI_unsigned_V4SI, 0 }, 5475 5476 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI, 5477 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, 5478 { P9V_BUILTIN_VEC_VCLZLSBB, P9V_BUILTIN_VCLZLSBB_V16QI, 5479 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5480 5481 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI, 5482 RS6000_BTI_INTSI, RS6000_BTI_V16QI, 0, 0 }, 5483 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V16QI, 5484 RS6000_BTI_INTSI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5485 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V8HI, 5486 RS6000_BTI_INTSI, RS6000_BTI_V8HI, 0, 0 }, 5487 { P9V_BUILTIN_VEC_VCTZLSBB, P9V_BUILTIN_VCTZLSBB_V4SI, 5488 RS6000_BTI_INTSI, RS6000_BTI_V4SI, 0, 0 }, 5489 5490 { P9V_BUILTIN_VEC_EXTRACT4B, P9V_BUILTIN_EXTRACT4B, 5491 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI, 0 }, 5492 5493 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTH, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTH, 5494 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5495 { P9V_BUILTIN_VEC_VEXTRACT_FP_FROM_SHORTL, P9V_BUILTIN_VEXTRACT_FP_FROM_SHORTL, 5496 RS6000_BTI_V4SF, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5497 5498 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX, 5499 RS6000_BTI_INTQI, RS6000_BTI_UINTSI, 5500 RS6000_BTI_V16QI, 0 }, 5501 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUBLX, 5502 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 5503 RS6000_BTI_unsigned_V16QI, 0 }, 5504 5505 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX, 5506 RS6000_BTI_INTHI, RS6000_BTI_UINTSI, 5507 RS6000_BTI_V8HI, 0 }, 5508 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUHLX, 5509 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI, 5510 RS6000_BTI_unsigned_V8HI, 0 }, 5511 5512 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, 5513 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, 5514 RS6000_BTI_V4SI, 0 }, 5515 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, 5516 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 5517 RS6000_BTI_unsigned_V4SI, 0 }, 5518 { P9V_BUILTIN_VEC_VEXTULX, P9V_BUILTIN_VEXTUWLX, 5519 RS6000_BTI_float, RS6000_BTI_UINTSI, 5520 RS6000_BTI_V4SF, 0 }, 5521 5522 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX, 5523 RS6000_BTI_INTQI, RS6000_BTI_UINTSI, 5524 RS6000_BTI_V16QI, 0 }, 5525 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUBRX, 5526 RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 5527 RS6000_BTI_unsigned_V16QI, 0 }, 5528 5529 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX, 5530 RS6000_BTI_INTHI, RS6000_BTI_UINTSI, 5531 RS6000_BTI_V8HI, 0 }, 5532 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUHRX, 5533 RS6000_BTI_UINTHI, RS6000_BTI_UINTSI, 5534 RS6000_BTI_unsigned_V8HI, 0 }, 5535 5536 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, 5537 RS6000_BTI_INTSI, RS6000_BTI_UINTSI, 5538 RS6000_BTI_V4SI, 0 }, 5539 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, 5540 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 5541 RS6000_BTI_unsigned_V4SI, 0 }, 5542 { P9V_BUILTIN_VEC_VEXTURX, P9V_BUILTIN_VEXTUWRX, 5543 RS6000_BTI_float, RS6000_BTI_UINTSI, 5544 RS6000_BTI_V4SF, 0 }, 5545 5546 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, 5547 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5548 { P8V_BUILTIN_VEC_VGBBD, P8V_BUILTIN_VGBBD, 5549 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5550 5551 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B, 5552 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V4SI, 5553 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, 5554 { P9V_BUILTIN_VEC_INSERT4B, P9V_BUILTIN_INSERT4B, 5555 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V4SI, 5556 RS6000_BTI_unsigned_V16QI, RS6000_BTI_INTSI }, 5557 5558 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, 5559 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 5560 { P8V_BUILTIN_VEC_VADDECUQ, P8V_BUILTIN_VADDECUQ, 5561 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5562 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 5563 5564 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, 5565 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 5566 { P8V_BUILTIN_VEC_VADDEUQM, P8V_BUILTIN_VADDEUQM, 5567 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5568 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 5569 5570 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, 5571 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 5572 { P8V_BUILTIN_VEC_VSUBECUQ, P8V_BUILTIN_VSUBECUQ, 5573 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5574 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 5575 5576 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, 5577 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI }, 5578 { P8V_BUILTIN_VEC_VSUBEUQM, P8V_BUILTIN_VSUBEUQM, 5579 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5580 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI }, 5581 5582 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, 5583 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 5584 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, 5585 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5586 { P8V_BUILTIN_VEC_VMINSD, P8V_BUILTIN_VMINSD, 5587 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5588 5589 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, 5590 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 5591 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, 5592 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5593 { P8V_BUILTIN_VEC_VMAXSD, P8V_BUILTIN_VMAXSD, 5594 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5595 5596 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, 5597 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 5598 RS6000_BTI_unsigned_V2DI, 0 }, 5599 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, 5600 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5601 RS6000_BTI_bool_V2DI, 0 }, 5602 { P8V_BUILTIN_VEC_VMINUD, P8V_BUILTIN_VMINUD, 5603 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5604 RS6000_BTI_unsigned_V2DI, 0 }, 5605 5606 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 5607 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 5608 RS6000_BTI_unsigned_V2DI, 0 }, 5609 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 5610 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5611 RS6000_BTI_bool_V2DI, 0 }, 5612 { P8V_BUILTIN_VEC_VMAXUD, P8V_BUILTIN_VMAXUD, 5613 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5614 RS6000_BTI_unsigned_V2DI, 0 }, 5615 5616 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI, 5617 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5618 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI, 5619 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5620 RS6000_BTI_unsigned_V2DI, 0 }, 5621 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DI, 5622 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5623 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SF, 5624 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 5625 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V2DF, 5626 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 5627 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, 5628 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 5629 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, 5630 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5631 RS6000_BTI_unsigned_V4SI, 0 }, 5632 { P8V_BUILTIN_VEC_VMRGEW, P8V_BUILTIN_VMRGEW_V4SI, 5633 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 5634 5635 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI, 5636 RS6000_BTI_V4SI, RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0 }, 5637 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI, 5638 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5639 RS6000_BTI_unsigned_V4SI, 0 }, 5640 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SI, 5641 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0 }, 5642 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI, 5643 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5644 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI, 5645 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5646 RS6000_BTI_unsigned_V2DI, 0 }, 5647 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DI, 5648 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5649 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V2DF, 5650 RS6000_BTI_V2DF, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 5651 { P8V_BUILTIN_VEC_VMRGOW, P8V_BUILTIN_VMRGOW_V4SF, 5652 RS6000_BTI_V4SF, RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0 }, 5653 5654 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMB, 5655 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V16QI, 5656 RS6000_BTI_unsigned_V16QI, 0 }, 5657 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMH, 5658 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V8HI, 5659 RS6000_BTI_unsigned_V8HI, 0 }, 5660 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMW, 5661 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V4SI, 5662 RS6000_BTI_unsigned_V4SI, 0 }, 5663 { P8V_BUILTIN_VEC_VPMSUM, P8V_BUILTIN_VPMSUMD, 5664 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V2DI, 5665 RS6000_BTI_unsigned_V2DI, 0 }, 5666 5667 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, 5668 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5669 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTB, 5670 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5671 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, 5672 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5673 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTH, 5674 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5675 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, 5676 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5677 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTW, 5678 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5679 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, 5680 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5681 { P8V_BUILTIN_VEC_VPOPCNT, P8V_BUILTIN_VPOPCNTD, 5682 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5683 5684 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, 5685 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5686 { P8V_BUILTIN_VEC_VPOPCNTB, P8V_BUILTIN_VPOPCNTB, 5687 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5688 5689 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB, 5690 RS6000_BTI_unsigned_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5691 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUB, 5692 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5693 5694 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH, 5695 RS6000_BTI_unsigned_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5696 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUH, 5697 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5698 5699 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW, 5700 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5701 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUW, 5702 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5703 5704 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD, 5705 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5706 { P8V_BUILTIN_VEC_VPOPCNTU, P8V_BUILTIN_VPOPCNTUD, 5707 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5708 5709 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, 5710 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5711 { P8V_BUILTIN_VEC_VPOPCNTH, P8V_BUILTIN_VPOPCNTH, 5712 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5713 5714 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, 5715 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5716 { P8V_BUILTIN_VEC_VPOPCNTW, P8V_BUILTIN_VPOPCNTW, 5717 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5718 5719 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, 5720 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5721 { P8V_BUILTIN_VEC_VPOPCNTD, P8V_BUILTIN_VPOPCNTD, 5722 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5723 5724 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW, 5725 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5726 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBW, 5727 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5728 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD, 5729 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5730 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBD, 5731 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5732 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, 5733 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, 5734 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, 5735 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, 5736 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, 5737 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 }, 5738 { P9V_BUILTIN_VEC_VPRTYB, P9V_BUILTIN_VPRTYBQ, 5739 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 }, 5740 5741 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW, 5742 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5743 { P9V_BUILTIN_VEC_VPRTYBW, P9V_BUILTIN_VPRTYBW, 5744 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5745 5746 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD, 5747 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5748 { P9V_BUILTIN_VEC_VPRTYBD, P9V_BUILTIN_VPRTYBD, 5749 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5750 5751 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, 5752 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, 5753 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, 5754 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, 5755 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, 5756 RS6000_BTI_INTTI, RS6000_BTI_INTTI, 0, 0 }, 5757 { P9V_BUILTIN_VEC_VPRTYBQ, P9V_BUILTIN_VPRTYBQ, 5758 RS6000_BTI_UINTTI, RS6000_BTI_UINTTI, 0, 0 }, 5759 5760 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW, 5761 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5762 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBW, 5763 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5764 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD, 5765 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5766 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBD, 5767 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5768 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ, 5769 RS6000_BTI_unsigned_V1TI, RS6000_BTI_V1TI, 0, 0 }, 5770 { P9V_BUILTIN_VEC_VPARITY_LSBB, P9V_BUILTIN_VPRTYBQ, 5771 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, 5772 5773 { P9_BUILTIN_CMPRB, P9_BUILTIN_SCALAR_CMPRB, 5774 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 }, 5775 { P9_BUILTIN_CMPRB2, P9_BUILTIN_SCALAR_CMPRB2, 5776 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTSI, 0 }, 5777 { P9_BUILTIN_CMPEQB, P9_BUILTIN_SCALAR_CMPEQB, 5778 RS6000_BTI_INTSI, RS6000_BTI_UINTQI, RS6000_BTI_UINTDI, 0 }, 5779 5780 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, 5781 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5782 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, 5783 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5784 { P8V_BUILTIN_VEC_VPKUDUM, P8V_BUILTIN_VPKUDUM, 5785 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5786 5787 { P8V_BUILTIN_VEC_VPKSDSS, P8V_BUILTIN_VPKSDSS, 5788 RS6000_BTI_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5789 5790 { P8V_BUILTIN_VEC_VPKUDUS, P8V_BUILTIN_VPKUDUS, 5791 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5792 5793 { P8V_BUILTIN_VEC_VPKSDUS, P8V_BUILTIN_VPKSDUS, 5794 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5795 5796 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, 5797 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5798 { P8V_BUILTIN_VEC_VRLD, P8V_BUILTIN_VRLD, 5799 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5800 5801 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, 5802 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5803 { P8V_BUILTIN_VEC_VSLD, P8V_BUILTIN_VSLD, 5804 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5805 5806 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, 5807 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5808 { P8V_BUILTIN_VEC_VSRD, P8V_BUILTIN_VSRD, 5809 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5810 5811 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, 5812 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5813 { P8V_BUILTIN_VEC_VSRAD, P8V_BUILTIN_VSRAD, 5814 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5815 5816 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, 5817 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 5818 { P8V_BUILTIN_VEC_VSUBCUQ, P8V_BUILTIN_VSUBCUQ, 5819 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5820 RS6000_BTI_unsigned_V1TI, 0 }, 5821 5822 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5823 RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_V2DI, 0 }, 5824 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5825 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5826 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5827 RS6000_BTI_V2DI, RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0 }, 5828 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5829 RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5830 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5831 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_bool_V2DI, 0 }, 5832 { P8V_BUILTIN_VEC_VSUBUDM, P8V_BUILTIN_VSUBUDM, 5833 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0 }, 5834 5835 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, 5836 RS6000_BTI_V1TI, RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0 }, 5837 { P8V_BUILTIN_VEC_VSUBUQM, P8V_BUILTIN_VSUBUQM, 5838 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 5839 RS6000_BTI_unsigned_V1TI, 0 }, 5840 5841 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB_32, 5842 RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, RS6000_BTI_UINTSI, 0 }, 5843 { P6_OV_BUILTIN_CMPB, P6_BUILTIN_CMPB, 5844 RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, RS6000_BTI_UINTDI, 0 }, 5845 5846 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, 5847 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 5848 { P8V_BUILTIN_VEC_VUPKHSW, P8V_BUILTIN_VUPKHSW, 5849 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 5850 5851 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, 5852 RS6000_BTI_V2DI, RS6000_BTI_V4SI, 0, 0 }, 5853 { P8V_BUILTIN_VEC_VUPKLSW, P8V_BUILTIN_VUPKLSW, 5854 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V4SI, 0, 0 }, 5855 5856 { P9V_BUILTIN_VEC_VSLV, P9V_BUILTIN_VSLV, 5857 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 5858 RS6000_BTI_unsigned_V16QI, 0 }, 5859 { P9V_BUILTIN_VEC_VSRV, P9V_BUILTIN_VSRV, 5860 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 5861 RS6000_BTI_unsigned_V16QI, 0 }, 5862 5863 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI, 5864 RS6000_BTI_V1TI, RS6000_BTI_V1TI, 0, 0 }, 5865 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V1TI, 5866 RS6000_BTI_unsigned_V1TI, RS6000_BTI_unsigned_V1TI, 0, 0 }, 5867 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI, 5868 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 }, 5869 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI, 5870 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5871 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DI, 5872 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5873 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI, 5874 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 }, 5875 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI, 5876 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5877 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SI, 5878 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5879 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI, 5880 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 }, 5881 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI, 5882 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5883 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V8HI, 5884 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5885 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI, 5886 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 }, 5887 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI, 5888 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5889 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V16QI, 5890 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5891 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V2DF, 5892 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 5893 { P8V_BUILTIN_VEC_REVB, P8V_BUILTIN_REVB_V4SF, 5894 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 5895 5896 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, 5897 RS6000_BTI_V2DI, RS6000_BTI_V2DI, 0, 0 }, 5898 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, 5899 RS6000_BTI_V4SI, RS6000_BTI_V4SI, 0, 0 }, 5900 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, 5901 RS6000_BTI_V8HI, RS6000_BTI_V8HI, 0, 0 }, 5902 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, 5903 RS6000_BTI_V16QI, RS6000_BTI_V16QI, 0, 0 }, 5904 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, 5905 RS6000_BTI_bool_V2DI, RS6000_BTI_bool_V2DI, 0, 0 }, 5906 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, 5907 RS6000_BTI_bool_V4SI, RS6000_BTI_bool_V4SI, 0, 0 }, 5908 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, 5909 RS6000_BTI_bool_V8HI, RS6000_BTI_bool_V8HI, 0, 0 }, 5910 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, 5911 RS6000_BTI_bool_V16QI, RS6000_BTI_bool_V16QI, 0, 0 }, 5912 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DF, 5913 RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0, 0 }, 5914 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SF, 5915 RS6000_BTI_V4SF, RS6000_BTI_V4SF, 0, 0 }, 5916 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V2DI, 5917 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 0, 0 }, 5918 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V4SI, 5919 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 0, 0 }, 5920 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V8HI, 5921 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 0, 0 }, 5922 { ALTIVEC_BUILTIN_VEC_VREVE, ALTIVEC_BUILTIN_VREVE_V16QI, 5923 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 0, 0 }, 5924 5925 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V4SF, 5926 RS6000_BTI_V4SI, RS6000_BTI_V4SF, 0, 0 }, 5927 { VSX_BUILTIN_VEC_VSIGNED, VSX_BUILTIN_VEC_VSIGNED_V2DF, 5928 RS6000_BTI_V2DI, RS6000_BTI_V2DF, 0, 0 }, 5929 { VSX_BUILTIN_VEC_VSIGNEDE, VSX_BUILTIN_VEC_VSIGNEDE_V2DF, 5930 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5931 { VSX_BUILTIN_VEC_VSIGNEDO, VSX_BUILTIN_VEC_VSIGNEDO_V2DF, 5932 RS6000_BTI_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5933 { P8V_BUILTIN_VEC_VSIGNED2, P8V_BUILTIN_VEC_VSIGNED2_V2DF, 5934 RS6000_BTI_V4SI, RS6000_BTI_V2DF, RS6000_BTI_V2DF, 0 }, 5935 5936 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V4SF, 5937 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V4SF, 0, 0 }, 5938 { VSX_BUILTIN_VEC_VUNSIGNED, VSX_BUILTIN_VEC_VUNSIGNED_V2DF, 5939 RS6000_BTI_unsigned_V2DI, RS6000_BTI_V2DF, 0, 0 }, 5940 { VSX_BUILTIN_VEC_VUNSIGNEDE, VSX_BUILTIN_VEC_VUNSIGNEDE_V2DF, 5941 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5942 { VSX_BUILTIN_VEC_VUNSIGNEDO, VSX_BUILTIN_VEC_VUNSIGNEDO_V2DF, 5943 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 0, 0 }, 5944 { P8V_BUILTIN_VEC_VUNSIGNED2, P8V_BUILTIN_VEC_VUNSIGNED2_V2DF, 5945 RS6000_BTI_unsigned_V4SI, RS6000_BTI_V2DF, 5946 RS6000_BTI_V2DF, 0 }, 5947 5948 /* Crypto builtins. */ 5949 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V16QI, 5950 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 5951 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI }, 5952 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V8HI, 5953 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 5954 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI }, 5955 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V4SI, 5956 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5957 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI }, 5958 { CRYPTO_BUILTIN_VPERMXOR, CRYPTO_BUILTIN_VPERMXOR_V2DI, 5959 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5960 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI }, 5961 5962 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMB, 5963 RS6000_BTI_unsigned_V16QI, RS6000_BTI_unsigned_V16QI, 5964 RS6000_BTI_unsigned_V16QI, 0 }, 5965 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMH, 5966 RS6000_BTI_unsigned_V8HI, RS6000_BTI_unsigned_V8HI, 5967 RS6000_BTI_unsigned_V8HI, 0 }, 5968 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMW, 5969 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5970 RS6000_BTI_unsigned_V4SI, 0 }, 5971 { CRYPTO_BUILTIN_VPMSUM, CRYPTO_BUILTIN_VPMSUMD, 5972 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5973 RS6000_BTI_unsigned_V2DI, 0 }, 5974 5975 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAW, 5976 RS6000_BTI_unsigned_V4SI, RS6000_BTI_unsigned_V4SI, 5977 RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 5978 { CRYPTO_BUILTIN_VSHASIGMA, CRYPTO_BUILTIN_VSHASIGMAD, 5979 RS6000_BTI_unsigned_V2DI, RS6000_BTI_unsigned_V2DI, 5980 RS6000_BTI_INTSI, RS6000_BTI_INTSI }, 5981 5982 { (enum rs6000_builtins) 0, (enum rs6000_builtins) 0, 0, 0, 0, 0 } 5983 }; 5984 5985 5986 /* Convert a type stored into a struct altivec_builtin_types as ID, 5987 into a tree. The types are in rs6000_builtin_types: negative values 5988 create a pointer type for the type associated to ~ID. Note it is 5989 a logical NOT, rather than a negation, otherwise you cannot represent 5990 a pointer type for ID 0. */ 5991 5992 static inline tree 5993 rs6000_builtin_type (int id) 5994 { 5995 tree t; 5996 t = rs6000_builtin_types[id < 0 ? ~id : id]; 5997 return id < 0 ? build_pointer_type (t) : t; 5998 } 5999 6000 /* Check whether the type of an argument, T, is compatible with a type ID 6001 stored into a struct altivec_builtin_types. Integer types are considered 6002 compatible; otherwise, the language hook lang_hooks.types_compatible_p makes 6003 the decision. Also allow long double and _Float128 to be compatible if 6004 -mabi=ieeelongdouble. */ 6005 6006 static inline bool 6007 is_float128_p (tree t) 6008 { 6009 return (t == float128_type_node 6010 || (TARGET_IEEEQUAD 6011 && TARGET_LONG_DOUBLE_128 6012 && t == long_double_type_node)); 6013 } 6014 6015 static inline bool 6016 rs6000_builtin_type_compatible (tree t, int id) 6017 { 6018 tree builtin_type; 6019 builtin_type = rs6000_builtin_type (id); 6020 if (t == error_mark_node) 6021 return false; 6022 if (INTEGRAL_TYPE_P (t) && INTEGRAL_TYPE_P (builtin_type)) 6023 return true; 6024 else if (TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128 6025 && is_float128_p (t) && is_float128_p (builtin_type)) 6026 return true; 6027 else 6028 return lang_hooks.types_compatible_p (t, builtin_type); 6029 } 6030 6031 6032 /* In addition to calling fold_convert for EXPR of type TYPE, also 6033 call c_fully_fold to remove any C_MAYBE_CONST_EXPRs that could be 6034 hiding there (PR47197). */ 6035 6036 static tree 6037 fully_fold_convert (tree type, tree expr) 6038 { 6039 tree result = fold_convert (type, expr); 6040 bool maybe_const = true; 6041 6042 if (!c_dialect_cxx ()) 6043 result = c_fully_fold (result, false, &maybe_const); 6044 6045 return result; 6046 } 6047 6048 /* Build a tree for a function call to an Altivec non-overloaded builtin. 6049 The overloaded builtin that matched the types and args is described 6050 by DESC. The N arguments are given in ARGS, respectively. 6051 6052 Actually the only thing it does is calling fold_convert on ARGS, with 6053 a small exception for vec_{all,any}_{ge,le} predicates. */ 6054 6055 static tree 6056 altivec_build_resolved_builtin (tree *args, int n, 6057 const struct altivec_builtin_types *desc) 6058 { 6059 tree impl_fndecl = rs6000_builtin_decls[desc->overloaded_code]; 6060 tree ret_type = rs6000_builtin_type (desc->ret_type); 6061 tree argtypes = TYPE_ARG_TYPES (TREE_TYPE (impl_fndecl)); 6062 tree arg_type[3]; 6063 tree call; 6064 6065 int i; 6066 for (i = 0; i < n; i++) 6067 arg_type[i] = TREE_VALUE (argtypes), argtypes = TREE_CHAIN (argtypes); 6068 6069 /* The AltiVec overloading implementation is overall gross, but this 6070 is particularly disgusting. The vec_{all,any}_{ge,le} builtins 6071 are completely different for floating-point vs. integer vector 6072 types, because the former has vcmpgefp, but the latter should use 6073 vcmpgtXX. 6074 6075 In practice, the second and third arguments are swapped, and the 6076 condition (LT vs. EQ, which is recognizable by bit 1 of the first 6077 argument) is reversed. Patch the arguments here before building 6078 the resolved CALL_EXPR. */ 6079 if (desc->code == ALTIVEC_BUILTIN_VEC_VCMPGE_P 6080 && desc->overloaded_code != ALTIVEC_BUILTIN_VCMPGEFP_P 6081 && desc->overloaded_code != VSX_BUILTIN_XVCMPGEDP_P) 6082 { 6083 tree t; 6084 t = args[2], args[2] = args[1], args[1] = t; 6085 t = arg_type[2], arg_type[2] = arg_type[1], arg_type[1] = t; 6086 6087 args[0] = fold_build2 (BIT_XOR_EXPR, TREE_TYPE (args[0]), args[0], 6088 build_int_cst (NULL_TREE, 2)); 6089 } 6090 6091 switch (n) 6092 { 6093 case 0: 6094 call = build_call_expr (impl_fndecl, 0); 6095 break; 6096 case 1: 6097 call = build_call_expr (impl_fndecl, 1, 6098 fully_fold_convert (arg_type[0], args[0])); 6099 break; 6100 case 2: 6101 call = build_call_expr (impl_fndecl, 2, 6102 fully_fold_convert (arg_type[0], args[0]), 6103 fully_fold_convert (arg_type[1], args[1])); 6104 break; 6105 case 3: 6106 call = build_call_expr (impl_fndecl, 3, 6107 fully_fold_convert (arg_type[0], args[0]), 6108 fully_fold_convert (arg_type[1], args[1]), 6109 fully_fold_convert (arg_type[2], args[2])); 6110 break; 6111 default: 6112 gcc_unreachable (); 6113 } 6114 return fold_convert (ret_type, call); 6115 } 6116 6117 /* Implementation of the resolve_overloaded_builtin target hook, to 6118 support Altivec's overloaded builtins. */ 6119 6120 tree 6121 altivec_resolve_overloaded_builtin (location_t loc, tree fndecl, 6122 void *passed_arglist) 6123 { 6124 vec<tree, va_gc> *arglist = static_cast<vec<tree, va_gc> *> (passed_arglist); 6125 unsigned int nargs = vec_safe_length (arglist); 6126 enum rs6000_builtins fcode 6127 = (enum rs6000_builtins)DECL_FUNCTION_CODE (fndecl); 6128 tree fnargs = TYPE_ARG_TYPES (TREE_TYPE (fndecl)); 6129 tree types[3], args[3]; 6130 const struct altivec_builtin_types *desc; 6131 unsigned int n; 6132 6133 if (!rs6000_overloaded_builtin_p (fcode)) 6134 return NULL_TREE; 6135 6136 if (TARGET_DEBUG_BUILTIN) 6137 fprintf (stderr, "altivec_resolve_overloaded_builtin, code = %4d, %s\n", 6138 (int)fcode, IDENTIFIER_POINTER (DECL_NAME (fndecl))); 6139 6140 /* vec_lvsl and vec_lvsr are deprecated for use with LE element order. */ 6141 if (fcode == ALTIVEC_BUILTIN_VEC_LVSL && !BYTES_BIG_ENDIAN) 6142 warning (OPT_Wdeprecated, 6143 "vec_lvsl is deprecated for little endian; use " 6144 "assignment for unaligned loads and stores"); 6145 else if (fcode == ALTIVEC_BUILTIN_VEC_LVSR && !BYTES_BIG_ENDIAN) 6146 warning (OPT_Wdeprecated, 6147 "vec_lvsr is deprecated for little endian; use " 6148 "assignment for unaligned loads and stores"); 6149 6150 if (fcode == ALTIVEC_BUILTIN_VEC_MUL) 6151 { 6152 /* vec_mul needs to be special cased because there are no instructions 6153 for it for the {un}signed char, {un}signed short, and {un}signed int 6154 types. */ 6155 if (nargs != 2) 6156 { 6157 error ("builtin %qs only accepts 2 arguments", "vec_mul"); 6158 return error_mark_node; 6159 } 6160 6161 tree arg0 = (*arglist)[0]; 6162 tree arg0_type = TREE_TYPE (arg0); 6163 tree arg1 = (*arglist)[1]; 6164 tree arg1_type = TREE_TYPE (arg1); 6165 6166 /* Both arguments must be vectors and the types must be compatible. */ 6167 if (TREE_CODE (arg0_type) != VECTOR_TYPE) 6168 goto bad; 6169 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)) 6170 goto bad; 6171 6172 switch (TYPE_MODE (TREE_TYPE (arg0_type))) 6173 { 6174 case E_QImode: 6175 case E_HImode: 6176 case E_SImode: 6177 case E_DImode: 6178 case E_TImode: 6179 { 6180 /* For scalar types just use a multiply expression. */ 6181 return fold_build2_loc (loc, MULT_EXPR, TREE_TYPE (arg0), arg0, 6182 fold_convert (TREE_TYPE (arg0), arg1)); 6183 } 6184 case E_SFmode: 6185 { 6186 /* For floats use the xvmulsp instruction directly. */ 6187 tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULSP]; 6188 return build_call_expr (call, 2, arg0, arg1); 6189 } 6190 case E_DFmode: 6191 { 6192 /* For doubles use the xvmuldp instruction directly. */ 6193 tree call = rs6000_builtin_decls[VSX_BUILTIN_XVMULDP]; 6194 return build_call_expr (call, 2, arg0, arg1); 6195 } 6196 /* Other types are errors. */ 6197 default: 6198 goto bad; 6199 } 6200 } 6201 6202 if (fcode == ALTIVEC_BUILTIN_VEC_CMPNE) 6203 { 6204 /* vec_cmpne needs to be special cased because there are no instructions 6205 for it (prior to power 9). */ 6206 if (nargs != 2) 6207 { 6208 error ("builtin %qs only accepts 2 arguments", "vec_cmpne"); 6209 return error_mark_node; 6210 } 6211 6212 tree arg0 = (*arglist)[0]; 6213 tree arg0_type = TREE_TYPE (arg0); 6214 tree arg1 = (*arglist)[1]; 6215 tree arg1_type = TREE_TYPE (arg1); 6216 6217 /* Both arguments must be vectors and the types must be compatible. */ 6218 if (TREE_CODE (arg0_type) != VECTOR_TYPE) 6219 goto bad; 6220 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type)) 6221 goto bad; 6222 6223 /* Power9 instructions provide the most efficient implementation of 6224 ALTIVEC_BUILTIN_VEC_CMPNE if the mode is not DImode or TImode 6225 or SFmode or DFmode. */ 6226 if (!TARGET_P9_VECTOR 6227 || (TYPE_MODE (TREE_TYPE (arg0_type)) == DImode) 6228 || (TYPE_MODE (TREE_TYPE (arg0_type)) == TImode) 6229 || (TYPE_MODE (TREE_TYPE (arg0_type)) == SFmode) 6230 || (TYPE_MODE (TREE_TYPE (arg0_type)) == DFmode)) 6231 { 6232 switch (TYPE_MODE (TREE_TYPE (arg0_type))) 6233 { 6234 /* vec_cmpneq (va, vb) == vec_nor (vec_cmpeq (va, vb), 6235 vec_cmpeq (va, vb)). */ 6236 /* Note: vec_nand also works but opt changes vec_nand's 6237 to vec_nor's anyway. */ 6238 case E_QImode: 6239 case E_HImode: 6240 case E_SImode: 6241 case E_DImode: 6242 case E_TImode: 6243 case E_SFmode: 6244 case E_DFmode: 6245 { 6246 /* call = vec_cmpeq (va, vb) 6247 result = vec_nor (call, call). */ 6248 vec<tree, va_gc> *params = make_tree_vector (); 6249 vec_safe_push (params, arg0); 6250 vec_safe_push (params, arg1); 6251 tree call = altivec_resolve_overloaded_builtin 6252 (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_CMPEQ], 6253 params); 6254 /* Use save_expr to ensure that operands used more than once 6255 that may have side effects (like calls) are only evaluated 6256 once. */ 6257 call = save_expr (call); 6258 params = make_tree_vector (); 6259 vec_safe_push (params, call); 6260 vec_safe_push (params, call); 6261 return altivec_resolve_overloaded_builtin 6262 (loc, rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_NOR], params); 6263 } 6264 /* Other types are errors. */ 6265 default: 6266 goto bad; 6267 } 6268 } 6269 /* else, fall through and process the Power9 alternative below */ 6270 } 6271 6272 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE 6273 || fcode == ALTIVEC_BUILTIN_VEC_SUBE) 6274 { 6275 /* vec_adde needs to be special cased because there is no instruction 6276 for the {un}signed int version. */ 6277 if (nargs != 3) 6278 { 6279 const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDE ? 6280 "vec_adde": "vec_sube"; 6281 error ("builtin %qs only accepts 3 arguments", name); 6282 return error_mark_node; 6283 } 6284 6285 tree arg0 = (*arglist)[0]; 6286 tree arg0_type = TREE_TYPE (arg0); 6287 tree arg1 = (*arglist)[1]; 6288 tree arg1_type = TREE_TYPE (arg1); 6289 tree arg2 = (*arglist)[2]; 6290 tree arg2_type = TREE_TYPE (arg2); 6291 6292 /* All 3 arguments must be vectors of (signed or unsigned) (int or 6293 __int128) and the types must be compatible. */ 6294 if (TREE_CODE (arg0_type) != VECTOR_TYPE) 6295 goto bad; 6296 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type) 6297 || !lang_hooks.types_compatible_p (arg1_type, arg2_type)) 6298 goto bad; 6299 6300 switch (TYPE_MODE (TREE_TYPE (arg0_type))) 6301 { 6302 /* For {un}signed ints, 6303 vec_adde (va, vb, carryv) == vec_add (vec_add (va, vb), 6304 vec_and (carryv, 1)). 6305 vec_sube (va, vb, carryv) == vec_sub (vec_sub (va, vb), 6306 vec_and (carryv, 1)). */ 6307 case E_SImode: 6308 { 6309 tree add_sub_builtin; 6310 6311 vec<tree, va_gc> *params = make_tree_vector (); 6312 vec_safe_push (params, arg0); 6313 vec_safe_push (params, arg1); 6314 6315 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE) 6316 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD]; 6317 else 6318 add_sub_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB]; 6319 6320 tree call = altivec_resolve_overloaded_builtin (loc, 6321 add_sub_builtin, 6322 params); 6323 tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1); 6324 tree ones_vector = build_vector_from_val (arg0_type, const1); 6325 tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type, 6326 arg2, ones_vector); 6327 params = make_tree_vector (); 6328 vec_safe_push (params, call); 6329 vec_safe_push (params, and_expr); 6330 return altivec_resolve_overloaded_builtin (loc, add_sub_builtin, 6331 params); 6332 } 6333 /* For {un}signed __int128s use the vaddeuqm instruction 6334 directly. */ 6335 case E_TImode: 6336 { 6337 tree bii; 6338 6339 if (fcode == ALTIVEC_BUILTIN_VEC_ADDE) 6340 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDEUQM]; 6341 6342 else 6343 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBEUQM]; 6344 6345 return altivec_resolve_overloaded_builtin (loc, bii, arglist); 6346 } 6347 6348 /* Types other than {un}signed int and {un}signed __int128 6349 are errors. */ 6350 default: 6351 goto bad; 6352 } 6353 } 6354 6355 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC 6356 || fcode == ALTIVEC_BUILTIN_VEC_SUBEC) 6357 { 6358 /* vec_addec and vec_subec needs to be special cased because there is 6359 no instruction for the {un}signed int version. */ 6360 if (nargs != 3) 6361 { 6362 const char *name = fcode == ALTIVEC_BUILTIN_VEC_ADDEC ? 6363 "vec_addec": "vec_subec"; 6364 error ("builtin %qs only accepts 3 arguments", name); 6365 return error_mark_node; 6366 } 6367 6368 tree arg0 = (*arglist)[0]; 6369 tree arg0_type = TREE_TYPE (arg0); 6370 tree arg1 = (*arglist)[1]; 6371 tree arg1_type = TREE_TYPE (arg1); 6372 tree arg2 = (*arglist)[2]; 6373 tree arg2_type = TREE_TYPE (arg2); 6374 6375 /* All 3 arguments must be vectors of (signed or unsigned) (int or 6376 __int128) and the types must be compatible. */ 6377 if (TREE_CODE (arg0_type) != VECTOR_TYPE) 6378 goto bad; 6379 if (!lang_hooks.types_compatible_p (arg0_type, arg1_type) 6380 || !lang_hooks.types_compatible_p (arg1_type, arg2_type)) 6381 goto bad; 6382 6383 switch (TYPE_MODE (TREE_TYPE (arg0_type))) 6384 { 6385 /* For {un}signed ints, 6386 vec_addec (va, vb, carryv) == 6387 vec_or (vec_addc (va, vb), 6388 vec_addc (vec_add (va, vb), 6389 vec_and (carryv, 0x1))). */ 6390 case E_SImode: 6391 { 6392 /* Use save_expr to ensure that operands used more than once 6393 that may have side effects (like calls) are only evaluated 6394 once. */ 6395 tree as_builtin; 6396 tree as_c_builtin; 6397 6398 arg0 = save_expr (arg0); 6399 arg1 = save_expr (arg1); 6400 vec<tree, va_gc> *params = make_tree_vector (); 6401 vec_safe_push (params, arg0); 6402 vec_safe_push (params, arg1); 6403 6404 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC) 6405 as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADDC]; 6406 else 6407 as_c_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUBC]; 6408 6409 tree call1 = altivec_resolve_overloaded_builtin (loc, as_c_builtin, 6410 params); 6411 params = make_tree_vector (); 6412 vec_safe_push (params, arg0); 6413 vec_safe_push (params, arg1); 6414 6415 6416 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC) 6417 as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_ADD]; 6418 else 6419 as_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_SUB]; 6420 6421 tree call2 = altivec_resolve_overloaded_builtin (loc, as_builtin, 6422 params); 6423 tree const1 = build_int_cstu (TREE_TYPE (arg0_type), 1); 6424 tree ones_vector = build_vector_from_val (arg0_type, const1); 6425 tree and_expr = fold_build2_loc (loc, BIT_AND_EXPR, arg0_type, 6426 arg2, ones_vector); 6427 params = make_tree_vector (); 6428 vec_safe_push (params, call2); 6429 vec_safe_push (params, and_expr); 6430 call2 = altivec_resolve_overloaded_builtin (loc, as_c_builtin, 6431 params); 6432 params = make_tree_vector (); 6433 vec_safe_push (params, call1); 6434 vec_safe_push (params, call2); 6435 tree or_builtin = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_OR]; 6436 return altivec_resolve_overloaded_builtin (loc, or_builtin, 6437 params); 6438 } 6439 /* For {un}signed __int128s use the vaddecuq/vsubbecuq 6440 instructions. */ 6441 case E_TImode: 6442 { 6443 tree bii; 6444 6445 if (fcode == ALTIVEC_BUILTIN_VEC_ADDEC) 6446 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VADDECUQ]; 6447 6448 else 6449 bii = rs6000_builtin_decls[P8V_BUILTIN_VEC_VSUBECUQ]; 6450 6451 return altivec_resolve_overloaded_builtin (loc, bii, arglist); 6452 } 6453 /* Types other than {un}signed int and {un}signed __int128 6454 are errors. */ 6455 default: 6456 goto bad; 6457 } 6458 } 6459 6460 /* For now treat vec_splats and vec_promote as the same. */ 6461 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS 6462 || fcode == ALTIVEC_BUILTIN_VEC_PROMOTE) 6463 { 6464 tree type, arg; 6465 int size; 6466 int i; 6467 bool unsigned_p; 6468 vec<constructor_elt, va_gc> *vec; 6469 const char *name = fcode == ALTIVEC_BUILTIN_VEC_SPLATS ? "vec_splats": "vec_promote"; 6470 6471 if (fcode == ALTIVEC_BUILTIN_VEC_SPLATS && nargs != 1) 6472 { 6473 error ("builtin %qs only accepts 1 argument", name); 6474 return error_mark_node; 6475 } 6476 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE && nargs != 2) 6477 { 6478 error ("builtin %qs only accepts 2 arguments", name); 6479 return error_mark_node; 6480 } 6481 /* Ignore promote's element argument. */ 6482 if (fcode == ALTIVEC_BUILTIN_VEC_PROMOTE 6483 && !INTEGRAL_TYPE_P (TREE_TYPE ((*arglist)[1]))) 6484 goto bad; 6485 6486 arg = (*arglist)[0]; 6487 type = TREE_TYPE (arg); 6488 if (!SCALAR_FLOAT_TYPE_P (type) 6489 && !INTEGRAL_TYPE_P (type)) 6490 goto bad; 6491 unsigned_p = TYPE_UNSIGNED (type); 6492 switch (TYPE_MODE (type)) 6493 { 6494 case E_TImode: 6495 type = (unsigned_p ? unsigned_V1TI_type_node : V1TI_type_node); 6496 size = 1; 6497 break; 6498 case E_DImode: 6499 type = (unsigned_p ? unsigned_V2DI_type_node : V2DI_type_node); 6500 size = 2; 6501 break; 6502 case E_SImode: 6503 type = (unsigned_p ? unsigned_V4SI_type_node : V4SI_type_node); 6504 size = 4; 6505 break; 6506 case E_HImode: 6507 type = (unsigned_p ? unsigned_V8HI_type_node : V8HI_type_node); 6508 size = 8; 6509 break; 6510 case E_QImode: 6511 type = (unsigned_p ? unsigned_V16QI_type_node : V16QI_type_node); 6512 size = 16; 6513 break; 6514 case E_SFmode: type = V4SF_type_node; size = 4; break; 6515 case E_DFmode: type = V2DF_type_node; size = 2; break; 6516 default: 6517 goto bad; 6518 } 6519 arg = save_expr (fold_convert (TREE_TYPE (type), arg)); 6520 vec_alloc (vec, size); 6521 for(i = 0; i < size; i++) 6522 { 6523 constructor_elt elt = {NULL_TREE, arg}; 6524 vec->quick_push (elt); 6525 } 6526 return build_constructor (type, vec); 6527 } 6528 6529 /* For now use pointer tricks to do the extraction, unless we are on VSX 6530 extracting a double from a constant offset. */ 6531 if (fcode == ALTIVEC_BUILTIN_VEC_EXTRACT) 6532 { 6533 tree arg1; 6534 tree arg1_type; 6535 tree arg2; 6536 tree arg1_inner_type; 6537 tree decl, stmt; 6538 tree innerptrtype; 6539 machine_mode mode; 6540 6541 /* No second argument. */ 6542 if (nargs != 2) 6543 { 6544 error ("builtin %qs only accepts 2 arguments", "vec_extract"); 6545 return error_mark_node; 6546 } 6547 6548 arg2 = (*arglist)[1]; 6549 arg1 = (*arglist)[0]; 6550 arg1_type = TREE_TYPE (arg1); 6551 6552 if (TREE_CODE (arg1_type) != VECTOR_TYPE) 6553 goto bad; 6554 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) 6555 goto bad; 6556 6557 /* See if we can optimize vec_extracts with the current VSX instruction 6558 set. */ 6559 mode = TYPE_MODE (arg1_type); 6560 if (VECTOR_MEM_VSX_P (mode)) 6561 6562 { 6563 tree call = NULL_TREE; 6564 int nunits = GET_MODE_NUNITS (mode); 6565 6566 arg2 = fold_for_warn (arg2); 6567 6568 /* If the second argument is an integer constant, generate 6569 the built-in code if we can. We need 64-bit and direct 6570 move to extract the small integer vectors. */ 6571 if (TREE_CODE (arg2) == INTEGER_CST) 6572 { 6573 wide_int selector = wi::to_wide (arg2); 6574 selector = wi::umod_trunc (selector, nunits); 6575 arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector); 6576 switch (mode) 6577 { 6578 default: 6579 break; 6580 6581 case E_V1TImode: 6582 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V1TI]; 6583 break; 6584 6585 case E_V2DFmode: 6586 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF]; 6587 break; 6588 6589 case E_V2DImode: 6590 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI]; 6591 break; 6592 6593 case E_V4SFmode: 6594 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF]; 6595 break; 6596 6597 case E_V4SImode: 6598 if (TARGET_DIRECT_MOVE_64BIT) 6599 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI]; 6600 break; 6601 6602 case E_V8HImode: 6603 if (TARGET_DIRECT_MOVE_64BIT) 6604 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI]; 6605 break; 6606 6607 case E_V16QImode: 6608 if (TARGET_DIRECT_MOVE_64BIT) 6609 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI]; 6610 break; 6611 } 6612 } 6613 6614 /* If the second argument is variable, we can optimize it if we are 6615 generating 64-bit code on a machine with direct move. */ 6616 else if (TREE_CODE (arg2) != INTEGER_CST && TARGET_DIRECT_MOVE_64BIT) 6617 { 6618 switch (mode) 6619 { 6620 default: 6621 break; 6622 6623 case E_V2DFmode: 6624 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DF]; 6625 break; 6626 6627 case E_V2DImode: 6628 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_EXT_V2DI]; 6629 break; 6630 6631 case E_V4SFmode: 6632 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SF]; 6633 break; 6634 6635 case E_V4SImode: 6636 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V4SI]; 6637 break; 6638 6639 case E_V8HImode: 6640 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V8HI]; 6641 break; 6642 6643 case E_V16QImode: 6644 call = rs6000_builtin_decls[ALTIVEC_BUILTIN_VEC_EXT_V16QI]; 6645 break; 6646 } 6647 } 6648 6649 if (call) 6650 { 6651 tree result = build_call_expr (call, 2, arg1, arg2); 6652 /* Coerce the result to vector element type. May be no-op. */ 6653 arg1_inner_type = TREE_TYPE (arg1_type); 6654 result = fold_convert (arg1_inner_type, result); 6655 return result; 6656 } 6657 } 6658 6659 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2). */ 6660 arg1_inner_type = TREE_TYPE (arg1_type); 6661 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2, 6662 build_int_cst (TREE_TYPE (arg2), 6663 TYPE_VECTOR_SUBPARTS (arg1_type) 6664 - 1), 0); 6665 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type); 6666 DECL_EXTERNAL (decl) = 0; 6667 TREE_PUBLIC (decl) = 0; 6668 DECL_CONTEXT (decl) = current_function_decl; 6669 TREE_USED (decl) = 1; 6670 TREE_TYPE (decl) = arg1_type; 6671 TREE_READONLY (decl) = TYPE_READONLY (arg1_type); 6672 if (c_dialect_cxx ()) 6673 { 6674 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1, 6675 NULL_TREE, NULL_TREE); 6676 SET_EXPR_LOCATION (stmt, loc); 6677 } 6678 else 6679 { 6680 DECL_INITIAL (decl) = arg1; 6681 stmt = build1 (DECL_EXPR, arg1_type, decl); 6682 TREE_ADDRESSABLE (decl) = 1; 6683 SET_EXPR_LOCATION (stmt, loc); 6684 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt); 6685 } 6686 6687 innerptrtype = build_pointer_type (arg1_inner_type); 6688 6689 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); 6690 stmt = convert (innerptrtype, stmt); 6691 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); 6692 stmt = build_indirect_ref (loc, stmt, RO_NULL); 6693 6694 /* PR83660: We mark this as having side effects so that 6695 downstream in fold_build_cleanup_point_expr () it will get a 6696 CLEANUP_POINT_EXPR. If it does not we can run into an ICE 6697 later in gimplify_cleanup_point_expr (). Potentially this 6698 causes missed optimization because the actually is no side 6699 effect. */ 6700 if (c_dialect_cxx ()) 6701 TREE_SIDE_EFFECTS (stmt) = 1; 6702 6703 return stmt; 6704 } 6705 6706 /* For now use pointer tricks to do the insertion, unless we are on VSX 6707 inserting a double to a constant offset.. */ 6708 if (fcode == ALTIVEC_BUILTIN_VEC_INSERT) 6709 { 6710 tree arg0; 6711 tree arg1; 6712 tree arg2; 6713 tree arg1_type; 6714 tree arg1_inner_type; 6715 tree decl, stmt; 6716 tree innerptrtype; 6717 machine_mode mode; 6718 6719 /* No second or third arguments. */ 6720 if (nargs != 3) 6721 { 6722 error ("builtin %qs only accepts 3 arguments", "vec_insert"); 6723 return error_mark_node; 6724 } 6725 6726 arg0 = (*arglist)[0]; 6727 arg1 = (*arglist)[1]; 6728 arg1_type = TREE_TYPE (arg1); 6729 arg2 = fold_for_warn ((*arglist)[2]); 6730 6731 if (TREE_CODE (arg1_type) != VECTOR_TYPE) 6732 goto bad; 6733 if (!INTEGRAL_TYPE_P (TREE_TYPE (arg2))) 6734 goto bad; 6735 6736 /* If we can use the VSX xxpermdi instruction, use that for insert. */ 6737 mode = TYPE_MODE (arg1_type); 6738 if ((mode == V2DFmode || mode == V2DImode) && VECTOR_UNIT_VSX_P (mode) 6739 && TREE_CODE (arg2) == INTEGER_CST) 6740 { 6741 wide_int selector = wi::to_wide (arg2); 6742 selector = wi::umod_trunc (selector, 2); 6743 tree call = NULL_TREE; 6744 6745 arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector); 6746 if (mode == V2DFmode) 6747 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DF]; 6748 else if (mode == V2DImode) 6749 call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V2DI]; 6750 6751 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types 6752 reversed. */ 6753 if (call) 6754 return build_call_expr (call, 3, arg1, arg0, arg2); 6755 } 6756 else if (mode == V1TImode && VECTOR_UNIT_VSX_P (mode) 6757 && TREE_CODE (arg2) == INTEGER_CST) 6758 { 6759 tree call = rs6000_builtin_decls[VSX_BUILTIN_VEC_SET_V1TI]; 6760 wide_int selector = wi::zero(32); 6761 6762 arg2 = wide_int_to_tree (TREE_TYPE (arg2), selector); 6763 /* Note, __builtin_vec_insert_<xxx> has vector and scalar types 6764 reversed. */ 6765 return build_call_expr (call, 3, arg1, arg0, arg2); 6766 } 6767 6768 /* Build *(((arg1_inner_type*)&(vector type){arg1})+arg2) = arg0. */ 6769 arg1_inner_type = TREE_TYPE (arg1_type); 6770 if (TYPE_VECTOR_SUBPARTS (arg1_type) == 1) 6771 arg2 = build_int_cst (TREE_TYPE (arg2), 0); 6772 else 6773 arg2 = build_binary_op (loc, BIT_AND_EXPR, arg2, 6774 build_int_cst (TREE_TYPE (arg2), 6775 TYPE_VECTOR_SUBPARTS (arg1_type) 6776 - 1), 0); 6777 decl = build_decl (loc, VAR_DECL, NULL_TREE, arg1_type); 6778 DECL_EXTERNAL (decl) = 0; 6779 TREE_PUBLIC (decl) = 0; 6780 DECL_CONTEXT (decl) = current_function_decl; 6781 TREE_USED (decl) = 1; 6782 TREE_TYPE (decl) = arg1_type; 6783 TREE_READONLY (decl) = TYPE_READONLY (arg1_type); 6784 if (c_dialect_cxx ()) 6785 { 6786 stmt = build4 (TARGET_EXPR, arg1_type, decl, arg1, 6787 NULL_TREE, NULL_TREE); 6788 SET_EXPR_LOCATION (stmt, loc); 6789 } 6790 else 6791 { 6792 DECL_INITIAL (decl) = arg1; 6793 stmt = build1 (DECL_EXPR, arg1_type, decl); 6794 TREE_ADDRESSABLE (decl) = 1; 6795 SET_EXPR_LOCATION (stmt, loc); 6796 stmt = build1 (COMPOUND_LITERAL_EXPR, arg1_type, stmt); 6797 } 6798 6799 innerptrtype = build_pointer_type (arg1_inner_type); 6800 6801 stmt = build_unary_op (loc, ADDR_EXPR, stmt, 0); 6802 stmt = convert (innerptrtype, stmt); 6803 stmt = build_binary_op (loc, PLUS_EXPR, stmt, arg2, 1); 6804 stmt = build_indirect_ref (loc, stmt, RO_NULL); 6805 stmt = build2 (MODIFY_EXPR, TREE_TYPE (stmt), stmt, 6806 convert (TREE_TYPE (stmt), arg0)); 6807 stmt = build2 (COMPOUND_EXPR, arg1_type, stmt, decl); 6808 return stmt; 6809 } 6810 6811 for (n = 0; 6812 !VOID_TYPE_P (TREE_VALUE (fnargs)) && n < nargs; 6813 fnargs = TREE_CHAIN (fnargs), n++) 6814 { 6815 tree decl_type = TREE_VALUE (fnargs); 6816 tree arg = (*arglist)[n]; 6817 tree type; 6818 6819 if (arg == error_mark_node) 6820 return error_mark_node; 6821 6822 if (n >= 3) 6823 abort (); 6824 6825 arg = default_conversion (arg); 6826 6827 /* The C++ front-end converts float * to const void * using 6828 NOP_EXPR<const void *> (NOP_EXPR<void *> (x)). */ 6829 type = TREE_TYPE (arg); 6830 if (POINTER_TYPE_P (type) 6831 && TREE_CODE (arg) == NOP_EXPR 6832 && lang_hooks.types_compatible_p (TREE_TYPE (arg), 6833 const_ptr_type_node) 6834 && lang_hooks.types_compatible_p (TREE_TYPE (TREE_OPERAND (arg, 0)), 6835 ptr_type_node)) 6836 { 6837 arg = TREE_OPERAND (arg, 0); 6838 type = TREE_TYPE (arg); 6839 } 6840 6841 /* Remove the const from the pointers to simplify the overload 6842 matching further down. */ 6843 if (POINTER_TYPE_P (decl_type) 6844 && POINTER_TYPE_P (type) 6845 && TYPE_QUALS (TREE_TYPE (type)) != 0) 6846 { 6847 if (TYPE_READONLY (TREE_TYPE (type)) 6848 && !TYPE_READONLY (TREE_TYPE (decl_type))) 6849 warning (0, "passing arg %d of %qE discards qualifiers from " 6850 "pointer target type", n + 1, fndecl); 6851 type = build_pointer_type (build_qualified_type (TREE_TYPE (type), 6852 0)); 6853 arg = fold_convert (type, arg); 6854 } 6855 6856 args[n] = arg; 6857 types[n] = type; 6858 } 6859 6860 /* If the number of arguments did not match the prototype, return NULL 6861 and the generic code will issue the appropriate error message. */ 6862 if (!VOID_TYPE_P (TREE_VALUE (fnargs)) || n < nargs) 6863 return NULL; 6864 6865 if (n == 0) 6866 abort (); 6867 6868 if (fcode == ALTIVEC_BUILTIN_VEC_STEP) 6869 { 6870 if (TREE_CODE (types[0]) != VECTOR_TYPE) 6871 goto bad; 6872 6873 return build_int_cst (NULL_TREE, TYPE_VECTOR_SUBPARTS (types[0])); 6874 } 6875 6876 { 6877 bool unsupported_builtin = false; 6878 enum rs6000_builtins overloaded_code; 6879 tree result = NULL; 6880 for (desc = altivec_overloaded_builtins; 6881 desc->code && desc->code != fcode; desc++) 6882 continue; 6883 6884 /* Need to special case __builtin_cmp because the overloaded forms 6885 of this function take (unsigned int, unsigned int) or (unsigned 6886 long long int, unsigned long long int). Since C conventions 6887 allow the respective argument types to be implicitly coerced into 6888 each other, the default handling does not provide adequate 6889 discrimination between the desired forms of the function. */ 6890 if (fcode == P6_OV_BUILTIN_CMPB) 6891 { 6892 machine_mode arg1_mode = TYPE_MODE (types[0]); 6893 machine_mode arg2_mode = TYPE_MODE (types[1]); 6894 6895 if (nargs != 2) 6896 { 6897 error ("builtin %qs only accepts 2 arguments", "__builtin_cmpb"); 6898 return error_mark_node; 6899 } 6900 6901 /* If any supplied arguments are wider than 32 bits, resolve to 6902 64-bit variant of built-in function. */ 6903 if ((GET_MODE_PRECISION (arg1_mode) > 32) 6904 || (GET_MODE_PRECISION (arg2_mode) > 32)) 6905 { 6906 /* Assure all argument and result types are compatible with 6907 the built-in function represented by P6_BUILTIN_CMPB. */ 6908 overloaded_code = P6_BUILTIN_CMPB; 6909 } 6910 else 6911 { 6912 /* Assure all argument and result types are compatible with 6913 the built-in function represented by P6_BUILTIN_CMPB_32. */ 6914 overloaded_code = P6_BUILTIN_CMPB_32; 6915 } 6916 6917 while (desc->code && desc->code == fcode 6918 && desc->overloaded_code != overloaded_code) 6919 desc++; 6920 6921 if (desc->code && (desc->code == fcode) 6922 && rs6000_builtin_type_compatible (types[0], desc->op1) 6923 && rs6000_builtin_type_compatible (types[1], desc->op2)) 6924 { 6925 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) 6926 { 6927 result = altivec_build_resolved_builtin (args, n, desc); 6928 /* overloaded_code is set above */ 6929 if (!rs6000_builtin_is_supported_p (overloaded_code)) 6930 unsupported_builtin = true; 6931 else 6932 return result; 6933 } 6934 else 6935 unsupported_builtin = true; 6936 } 6937 } 6938 else if (fcode == P9V_BUILTIN_VEC_VSIEDP) 6939 { 6940 machine_mode arg1_mode = TYPE_MODE (types[0]); 6941 6942 if (nargs != 2) 6943 { 6944 error ("builtin %qs only accepts 2 arguments", 6945 "scalar_insert_exp"); 6946 return error_mark_node; 6947 } 6948 6949 /* If supplied first argument is wider than 64 bits, resolve to 6950 128-bit variant of built-in function. */ 6951 if (GET_MODE_PRECISION (arg1_mode) > 64) 6952 { 6953 /* If first argument is of float variety, choose variant 6954 that expects __ieee128 argument. Otherwise, expect 6955 __int128 argument. */ 6956 if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT) 6957 overloaded_code = P9V_BUILTIN_VSIEQPF; 6958 else 6959 overloaded_code = P9V_BUILTIN_VSIEQP; 6960 } 6961 else 6962 { 6963 /* If first argument is of float variety, choose variant 6964 that expects double argument. Otherwise, expect 6965 long long int argument. */ 6966 if (GET_MODE_CLASS (arg1_mode) == MODE_FLOAT) 6967 overloaded_code = P9V_BUILTIN_VSIEDPF; 6968 else 6969 overloaded_code = P9V_BUILTIN_VSIEDP; 6970 } 6971 while (desc->code && desc->code == fcode 6972 && desc->overloaded_code != overloaded_code) 6973 desc++; 6974 6975 if (desc->code && (desc->code == fcode) 6976 && rs6000_builtin_type_compatible (types[0], desc->op1) 6977 && rs6000_builtin_type_compatible (types[1], desc->op2)) 6978 { 6979 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) 6980 { 6981 result = altivec_build_resolved_builtin (args, n, desc); 6982 /* overloaded_code is set above. */ 6983 if (!rs6000_builtin_is_supported_p (overloaded_code)) 6984 unsupported_builtin = true; 6985 else 6986 return result; 6987 } 6988 else 6989 unsupported_builtin = true; 6990 } 6991 } 6992 else 6993 { 6994 /* For arguments after the last, we have RS6000_BTI_NOT_OPAQUE in 6995 the opX fields. */ 6996 for (; desc->code == fcode; desc++) 6997 { 6998 if ((desc->op1 == RS6000_BTI_NOT_OPAQUE 6999 || rs6000_builtin_type_compatible (types[0], desc->op1)) 7000 && (desc->op2 == RS6000_BTI_NOT_OPAQUE 7001 || rs6000_builtin_type_compatible (types[1], desc->op2)) 7002 && (desc->op3 == RS6000_BTI_NOT_OPAQUE 7003 || rs6000_builtin_type_compatible (types[2], desc->op3))) 7004 { 7005 if (rs6000_builtin_decls[desc->overloaded_code] != NULL_TREE) 7006 { 7007 result = altivec_build_resolved_builtin (args, n, desc); 7008 if (!rs6000_builtin_is_supported_p (desc->overloaded_code)) 7009 { 7010 /* Allow loop to continue in case a different 7011 definition is supported. */ 7012 overloaded_code = desc->overloaded_code; 7013 unsupported_builtin = true; 7014 } 7015 else 7016 return result; 7017 } 7018 else 7019 unsupported_builtin = true; 7020 } 7021 } 7022 } 7023 7024 if (unsupported_builtin) 7025 { 7026 const char *name = rs6000_overloaded_builtin_name (fcode); 7027 if (result != NULL) 7028 { 7029 const char *internal_name 7030 = rs6000_overloaded_builtin_name (overloaded_code); 7031 /* An error message making reference to the name of the 7032 non-overloaded function has already been issued. Add 7033 clarification of the previous message. */ 7034 rich_location richloc (line_table, input_location); 7035 inform (&richloc, "builtin %qs requires builtin %qs", 7036 name, internal_name); 7037 } 7038 else 7039 error ("builtin function %qs not supported in this compiler " 7040 "configuration", name); 7041 /* If an error-representing result tree was returned from 7042 altivec_build_resolved_builtin above, use it. */ 7043 return (result != NULL) ? result : error_mark_node; 7044 } 7045 } 7046 bad: 7047 { 7048 const char *name = rs6000_overloaded_builtin_name (fcode); 7049 error ("invalid parameter combination for AltiVec intrinsic %qs", name); 7050 return error_mark_node; 7051 } 7052 } 7053