1;; Scheduling description for IBM Power4 and PowerPC 970 processors. 2;; Copyright (C) 2003-2013 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 3, or (at your 9;; option) any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Sources: IBM Red Book and White Paper on POWER4 21 22;; The POWER4 has 2 iu, 2 fpu, 2 lsu per engine (2 engines per chip). 23;; Instructions that update more than one register get broken into two 24;; (split) or more internal ops. The chip can issue up to 5 25;; internal ops per cycle. 26 27(define_automaton "power4iu,power4fpu,power4vec,power4misc") 28 29(define_cpu_unit "iu1_power4,iu2_power4" "power4iu") 30(define_cpu_unit "lsu1_power4,lsu2_power4" "power4misc") 31(define_cpu_unit "fpu1_power4,fpu2_power4" "power4fpu") 32(define_cpu_unit "bpu_power4,cru_power4" "power4misc") 33(define_cpu_unit "vec_power4,vecperm_power4" "power4vec") 34(define_cpu_unit "du1_power4,du2_power4,du3_power4,du4_power4,du5_power4" 35 "power4misc") 36 37(define_reservation "lsq_power4" 38 "(du1_power4,lsu1_power4)\ 39 |(du2_power4,lsu2_power4)\ 40 |(du3_power4,lsu2_power4)\ 41 |(du4_power4,lsu1_power4)") 42 43(define_reservation "lsuq_power4" 44 "((du1_power4+du2_power4,lsu1_power4)\ 45 |(du2_power4+du3_power4,lsu2_power4)\ 46 |(du3_power4+du4_power4,lsu2_power4))\ 47 +(nothing,iu2_power4|nothing,iu1_power4)") 48 49(define_reservation "iq_power4" 50 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 51 (iu1_power4|iu2_power4)") 52 53(define_reservation "fpq_power4" 54 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 55 (fpu1_power4|fpu2_power4)") 56 57(define_reservation "vq_power4" 58 "(du1_power4,vec_power4)\ 59 |(du2_power4,vec_power4)\ 60 |(du3_power4,vec_power4)\ 61 |(du4_power4,vec_power4)") 62 63(define_reservation "vpq_power4" 64 "(du1_power4,vecperm_power4)\ 65 |(du2_power4,vecperm_power4)\ 66 |(du3_power4,vecperm_power4)\ 67 |(du4_power4,vecperm_power4)") 68 69 70; Dispatch slots are allocated in order conforming to program order. 71(absence_set "du1_power4" "du2_power4,du3_power4,du4_power4,du5_power4") 72(absence_set "du2_power4" "du3_power4,du4_power4,du5_power4") 73(absence_set "du3_power4" "du4_power4,du5_power4") 74(absence_set "du4_power4" "du5_power4") 75 76 77; Load/store 78(define_insn_reservation "power4-load" 4 ; 3 79 (and (eq_attr "type" "load") 80 (eq_attr "cpu" "power4")) 81 "lsq_power4") 82 83(define_insn_reservation "power4-load-ext" 5 84 (and (eq_attr "type" "load_ext") 85 (eq_attr "cpu" "power4")) 86 "(du1_power4+du2_power4,lsu1_power4\ 87 |du2_power4+du3_power4,lsu2_power4\ 88 |du3_power4+du4_power4,lsu2_power4),\ 89 nothing,nothing,\ 90 (iu2_power4|iu1_power4)") 91 92(define_insn_reservation "power4-load-ext-update" 5 93 (and (eq_attr "type" "load_ext_u") 94 (eq_attr "cpu" "power4")) 95 "du1_power4+du2_power4+du3_power4+du4_power4,\ 96 lsu1_power4+iu2_power4,nothing,nothing,iu2_power4") 97 98(define_insn_reservation "power4-load-ext-update-indexed" 5 99 (and (eq_attr "type" "load_ext_ux") 100 (eq_attr "cpu" "power4")) 101 "du1_power4+du2_power4+du3_power4+du4_power4,\ 102 iu1_power4,lsu2_power4+iu1_power4,nothing,nothing,iu2_power4") 103 104(define_insn_reservation "power4-load-update-indexed" 3 105 (and (eq_attr "type" "load_ux") 106 (eq_attr "cpu" "power4")) 107 "du1_power4+du2_power4+du3_power4+du4_power4,\ 108 iu1_power4,lsu2_power4+iu2_power4") 109 110(define_insn_reservation "power4-load-update" 4 ; 3 111 (and (eq_attr "type" "load_u") 112 (eq_attr "cpu" "power4")) 113 "lsuq_power4") 114 115(define_insn_reservation "power4-fpload" 6 ; 5 116 (and (eq_attr "type" "fpload") 117 (eq_attr "cpu" "power4")) 118 "lsq_power4") 119 120(define_insn_reservation "power4-fpload-update" 6 ; 5 121 (and (eq_attr "type" "fpload_u,fpload_ux") 122 (eq_attr "cpu" "power4")) 123 "lsuq_power4") 124 125(define_insn_reservation "power4-vecload" 6 ; 5 126 (and (eq_attr "type" "vecload") 127 (eq_attr "cpu" "power4")) 128 "lsq_power4") 129 130(define_insn_reservation "power4-store" 12 131 (and (eq_attr "type" "store") 132 (eq_attr "cpu" "power4")) 133 "((du1_power4,lsu1_power4)\ 134 |(du2_power4,lsu2_power4)\ 135 |(du3_power4,lsu2_power4)\ 136 |(du4_power4,lsu1_power4)),\ 137 (iu1_power4|iu2_power4)") 138 139(define_insn_reservation "power4-store-update" 12 140 (and (eq_attr "type" "store_u") 141 (eq_attr "cpu" "power4")) 142 "((du1_power4+du2_power4,lsu1_power4)\ 143 |(du2_power4+du3_power4,lsu2_power4)\ 144 |(du3_power4+du4_power4,lsu2_power4))+\ 145 ((nothing,iu1_power4,iu2_power4)\ 146 |(nothing,iu2_power4,iu2_power4)\ 147 |(nothing,iu2_power4,iu1_power4))") 148 149(define_insn_reservation "power4-store-update-indexed" 12 150 (and (eq_attr "type" "store_ux") 151 (eq_attr "cpu" "power4")) 152 "du1_power4+du2_power4+du3_power4+du4_power4,\ 153 iu1_power4,lsu2_power4+iu2_power4,iu2_power4") 154 155(define_insn_reservation "power4-fpstore" 12 156 (and (eq_attr "type" "fpstore") 157 (eq_attr "cpu" "power4")) 158 "((du1_power4,lsu1_power4)\ 159 |(du2_power4,lsu2_power4)\ 160 |(du3_power4,lsu2_power4)\ 161 |(du4_power4,lsu1_power4)),\ 162 (fpu1_power4|fpu2_power4)") 163 164(define_insn_reservation "power4-fpstore-update" 12 165 (and (eq_attr "type" "fpstore_u,fpstore_ux") 166 (eq_attr "cpu" "power4")) 167 "((du1_power4+du2_power4,lsu1_power4)\ 168 |(du2_power4+du3_power4,lsu2_power4)\ 169 |(du3_power4+du4_power4,lsu2_power4))\ 170 +(nothing,(iu1_power4|iu2_power4),(fpu1_power4|fpu2_power4))") 171 172(define_insn_reservation "power4-vecstore" 12 173 (and (eq_attr "type" "vecstore") 174 (eq_attr "cpu" "power4")) 175 "(du1_power4,lsu1_power4,vec_power4)\ 176 |(du2_power4,lsu2_power4,vec_power4)\ 177 |(du3_power4,lsu2_power4,vec_power4)\ 178 |(du4_power4,lsu1_power4,vec_power4)") 179 180(define_insn_reservation "power4-llsc" 11 181 (and (eq_attr "type" "load_l,store_c,sync") 182 (eq_attr "cpu" "power4")) 183 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4") 184 185 186; Integer latency is 2 cycles 187(define_insn_reservation "power4-integer" 2 188 (and (eq_attr "type" "integer,insert_dword,shift,trap,\ 189 var_shift_rotate,cntlz,exts,isel") 190 (eq_attr "cpu" "power4")) 191 "iq_power4") 192 193(define_insn_reservation "power4-two" 2 194 (and (eq_attr "type" "two") 195 (eq_attr "cpu" "power4")) 196 "((du1_power4+du2_power4)\ 197 |(du2_power4+du3_power4)\ 198 |(du3_power4+du4_power4)\ 199 |(du4_power4+du1_power4)),\ 200 ((iu1_power4,nothing,iu2_power4)\ 201 |(iu2_power4,nothing,iu2_power4)\ 202 |(iu2_power4,nothing,iu1_power4)\ 203 |(iu1_power4,nothing,iu1_power4))") 204 205(define_insn_reservation "power4-three" 2 206 (and (eq_attr "type" "three") 207 (eq_attr "cpu" "power4")) 208 "(du1_power4+du2_power4+du3_power4|du2_power4+du3_power4+du4_power4\ 209 |du3_power4+du4_power4+du1_power4|du4_power4+du1_power4+du2_power4),\ 210 ((iu1_power4,nothing,iu2_power4,nothing,iu2_power4)\ 211 |(iu2_power4,nothing,iu2_power4,nothing,iu1_power4)\ 212 |(iu2_power4,nothing,iu1_power4,nothing,iu1_power4)\ 213 |(iu1_power4,nothing,iu1_power4,nothing,iu2_power4))") 214 215(define_insn_reservation "power4-insert" 4 216 (and (eq_attr "type" "insert_word") 217 (eq_attr "cpu" "power4")) 218 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ 219 ((iu1_power4,nothing,iu2_power4)\ 220 |(iu2_power4,nothing,iu2_power4)\ 221 |(iu2_power4,nothing,iu1_power4))") 222 223(define_insn_reservation "power4-cmp" 3 224 (and (eq_attr "type" "cmp,fast_compare") 225 (eq_attr "cpu" "power4")) 226 "iq_power4") 227 228(define_insn_reservation "power4-compare" 2 229 (and (eq_attr "type" "compare,delayed_compare,var_delayed_compare") 230 (eq_attr "cpu" "power4")) 231 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ 232 ((iu1_power4,iu2_power4)\ 233 |(iu2_power4,iu2_power4)\ 234 |(iu2_power4,iu1_power4))") 235 236(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 237 238(define_insn_reservation "power4-lmul-cmp" 7 239 (and (eq_attr "type" "lmul_compare") 240 (eq_attr "cpu" "power4")) 241 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ 242 ((iu1_power4*6,iu2_power4)\ 243 |(iu2_power4*6,iu2_power4)\ 244 |(iu2_power4*6,iu1_power4))") 245 246(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 247 248(define_insn_reservation "power4-imul-cmp" 5 249 (and (eq_attr "type" "imul_compare") 250 (eq_attr "cpu" "power4")) 251 "(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\ 252 ((iu1_power4*4,iu2_power4)\ 253 |(iu2_power4*4,iu2_power4)\ 254 |(iu2_power4*4,iu1_power4))") 255 256(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 257 258(define_insn_reservation "power4-lmul" 7 259 (and (eq_attr "type" "lmul") 260 (eq_attr "cpu" "power4")) 261 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 262 (iu1_power4*6|iu2_power4*6)") 263 264(define_insn_reservation "power4-imul" 5 265 (and (eq_attr "type" "imul") 266 (eq_attr "cpu" "power4")) 267 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 268 (iu1_power4*4|iu2_power4*4)") 269 270(define_insn_reservation "power4-imul3" 4 271 (and (eq_attr "type" "imul2,imul3") 272 (eq_attr "cpu" "power4")) 273 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 274 (iu1_power4*3|iu2_power4*3)") 275 276 277; SPR move only executes in first IU. 278; Integer division only executes in second IU. 279(define_insn_reservation "power4-idiv" 36 280 (and (eq_attr "type" "idiv") 281 (eq_attr "cpu" "power4")) 282 "du1_power4+du2_power4,iu2_power4*35") 283 284(define_insn_reservation "power4-ldiv" 68 285 (and (eq_attr "type" "ldiv") 286 (eq_attr "cpu" "power4")) 287 "du1_power4+du2_power4,iu2_power4*67") 288 289 290(define_insn_reservation "power4-mtjmpr" 3 291 (and (eq_attr "type" "mtjmpr,mfjmpr") 292 (eq_attr "cpu" "power4")) 293 "du1_power4,bpu_power4") 294 295 296; Branches take dispatch Slot 4. The presence_sets prevent other insn from 297; grabbing previous dispatch slots once this is assigned. 298(define_insn_reservation "power4-branch" 2 299 (and (eq_attr "type" "jmpreg,branch") 300 (eq_attr "cpu" "power4")) 301 "(du5_power4\ 302 |du4_power4+du5_power4\ 303 |du3_power4+du4_power4+du5_power4\ 304 |du2_power4+du3_power4+du4_power4+du5_power4\ 305 |du1_power4+du2_power4+du3_power4+du4_power4+du5_power4),bpu_power4") 306 307 308; Condition Register logical ops are split if non-destructive (RT != RB) 309(define_insn_reservation "power4-crlogical" 2 310 (and (eq_attr "type" "cr_logical") 311 (eq_attr "cpu" "power4")) 312 "du1_power4,cru_power4") 313 314(define_insn_reservation "power4-delayedcr" 4 315 (and (eq_attr "type" "delayed_cr") 316 (eq_attr "cpu" "power4")) 317 "du1_power4+du2_power4,cru_power4,cru_power4") 318 319; 4 mfcrf (each 3 cyc, 1/cyc) + 3 fxu 320(define_insn_reservation "power4-mfcr" 6 321 (and (eq_attr "type" "mfcr") 322 (eq_attr "cpu" "power4")) 323 "du1_power4+du2_power4+du3_power4+du4_power4,\ 324 du1_power4+du2_power4+du3_power4+du4_power4+cru_power4,\ 325 cru_power4,cru_power4,cru_power4") 326 327; mfcrf (1 field) 328(define_insn_reservation "power4-mfcrf" 3 329 (and (eq_attr "type" "mfcrf") 330 (eq_attr "cpu" "power4")) 331 "du1_power4,cru_power4") 332 333; mtcrf (1 field) 334(define_insn_reservation "power4-mtcr" 4 335 (and (eq_attr "type" "mtcr") 336 (eq_attr "cpu" "power4")) 337 "du1_power4,iu1_power4") 338 339; Basic FP latency is 6 cycles 340(define_insn_reservation "power4-fp" 6 341 (and (eq_attr "type" "fp,dmul") 342 (eq_attr "cpu" "power4")) 343 "fpq_power4") 344 345(define_insn_reservation "power4-fpcompare" 5 346 (and (eq_attr "type" "fpcompare") 347 (eq_attr "cpu" "power4")) 348 "fpq_power4") 349 350(define_insn_reservation "power4-sdiv" 33 351 (and (eq_attr "type" "sdiv,ddiv") 352 (eq_attr "cpu" "power4")) 353 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 354 (fpu1_power4*28|fpu2_power4*28)") 355 356(define_insn_reservation "power4-sqrt" 40 357 (and (eq_attr "type" "ssqrt,dsqrt") 358 (eq_attr "cpu" "power4")) 359 "(du1_power4|du2_power4|du3_power4|du4_power4),\ 360 (fpu1_power4*35|fpu2_power4*35)") 361 362(define_insn_reservation "power4-isync" 2 363 (and (eq_attr "type" "isync") 364 (eq_attr "cpu" "power4")) 365 "du1_power4+du2_power4+du3_power4+du4_power4,lsu1_power4") 366 367 368; VMX 369(define_insn_reservation "power4-vecsimple" 2 370 (and (eq_attr "type" "vecsimple") 371 (eq_attr "cpu" "power4")) 372 "vq_power4") 373 374(define_insn_reservation "power4-veccomplex" 5 375 (and (eq_attr "type" "veccomplex") 376 (eq_attr "cpu" "power4")) 377 "vq_power4") 378 379; vecfp compare 380(define_insn_reservation "power4-veccmp" 8 381 (and (eq_attr "type" "veccmp") 382 (eq_attr "cpu" "power4")) 383 "vq_power4") 384 385(define_insn_reservation "power4-vecfloat" 8 386 (and (eq_attr "type" "vecfloat") 387 (eq_attr "cpu" "power4")) 388 "vq_power4") 389 390(define_insn_reservation "power4-vecperm" 2 391 (and (eq_attr "type" "vecperm") 392 (eq_attr "cpu" "power4")) 393 "vpq_power4") 394 395(define_bypass 4 "power4-vecload" "power4-vecperm") 396 397(define_bypass 3 "power4-vecsimple" "power4-vecperm") 398(define_bypass 6 "power4-veccomplex" "power4-vecperm") 399(define_bypass 3 "power4-vecperm" 400 "power4-vecsimple,power4-veccomplex,power4-vecfloat") 401(define_bypass 9 "power4-vecfloat" "power4-vecperm") 402 403(define_bypass 5 "power4-vecsimple,power4-veccomplex" 404 "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf") 405 406(define_bypass 4 "power4-vecsimple,power4-vecperm" "power4-vecstore") 407(define_bypass 7 "power4-veccomplex" "power4-vecstore") 408(define_bypass 10 "power4-vecfloat" "power4-vecstore") 409