xref: /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/rs6000/htm.md (revision b83ebeba7f767758d2778bb0f9d7a76534253621)
1;; Hardware Transactional Memory (HTM) patterns.
2;; Copyright (C) 2013-2015 Free Software Foundation, Inc.
3;; Contributed by Peter Bergner <bergner@vnet.ibm.com>.
4
5;; This file is part of GCC.
6
7;; GCC is free software; you can redistribute it and/or modify it
8;; under the terms of the GNU General Public License as published
9;; by the Free Software Foundation; either version 3, or (at your
10;; option) any later version.
11
12;; GCC is distributed in the hope that it will be useful, but WITHOUT
13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14;; or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
15;; License for more details.
16
17;; You should have received a copy of the GNU General Public License
18;; along with GCC; see the file COPYING3.  If not see
19;; <http://www.gnu.org/licenses/>.
20
21(define_constants
22  [(TFHAR_SPR		128)
23   (TFIAR_SPR		129)
24   (TEXASR_SPR		130)
25   (TEXASRU_SPR		131)
26   (MAX_HTM_OPERANDS	4)
27  ])
28
29;;
30;; UNSPEC_VOLATILE usage
31;;
32
33(define_c_enum "unspecv"
34  [UNSPECV_HTM_TABORT
35   UNSPECV_HTM_TABORTXC
36   UNSPECV_HTM_TABORTXCI
37   UNSPECV_HTM_TBEGIN
38   UNSPECV_HTM_TCHECK
39   UNSPECV_HTM_TEND
40   UNSPECV_HTM_TRECHKPT
41   UNSPECV_HTM_TRECLAIM
42   UNSPECV_HTM_TSR
43   UNSPECV_HTM_TTEST
44   UNSPECV_HTM_MFSPR
45   UNSPECV_HTM_MTSPR
46  ])
47
48
49(define_insn "tabort"
50  [(set (match_operand:CC 1 "cc_reg_operand" "=x")
51	(unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
52			    UNSPECV_HTM_TABORT))]
53  "TARGET_HTM"
54  "tabort. %0"
55  [(set_attr "type" "htm")
56   (set_attr "length" "4")])
57
58(define_insn "tabort<wd>c"
59  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
60	(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
61			     (match_operand:GPR 1 "gpc_reg_operand" "r")
62			     (match_operand:GPR 2 "gpc_reg_operand" "r")]
63			    UNSPECV_HTM_TABORTXC))]
64  "TARGET_HTM"
65  "tabort<wd>c. %0,%1,%2"
66  [(set_attr "type" "htm")
67   (set_attr "length" "4")])
68
69(define_insn "tabort<wd>ci"
70  [(set (match_operand:CC 3 "cc_reg_operand" "=x")
71	(unspec_volatile:CC [(match_operand 0 "u5bit_cint_operand" "n")
72			     (match_operand:GPR 1 "gpc_reg_operand" "r")
73			     (match_operand 2 "s5bit_cint_operand" "n")]
74			    UNSPECV_HTM_TABORTXCI))]
75  "TARGET_HTM"
76  "tabort<wd>ci. %0,%1,%2"
77  [(set_attr "type" "htm")
78   (set_attr "length" "4")])
79
80(define_insn "tbegin"
81  [(set (match_operand:CC 1 "cc_reg_operand" "=x")
82	(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
83			    UNSPECV_HTM_TBEGIN))]
84  "TARGET_HTM"
85  "tbegin. %0"
86  [(set_attr "type" "htm")
87   (set_attr "length" "4")])
88
89(define_insn "tcheck"
90  [(set (match_operand:CC 0 "cc_reg_operand" "=y")
91	(unspec_volatile:CC [(const_int 0)]
92			    UNSPECV_HTM_TCHECK))]
93  "TARGET_HTM"
94  "tcheck %0"
95  [(set_attr "type" "htm")
96   (set_attr "length" "4")])
97
98(define_insn "tend"
99  [(set (match_operand:CC 1 "cc_reg_operand" "=x")
100	(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
101			    UNSPECV_HTM_TEND))]
102  "TARGET_HTM"
103  "tend. %0"
104  [(set_attr "type" "htm")
105   (set_attr "length" "4")])
106
107(define_insn "trechkpt"
108  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
109	(unspec_volatile:CC [(const_int 0)]
110			    UNSPECV_HTM_TRECHKPT))]
111  "TARGET_HTM"
112  "trechkpt."
113  [(set_attr "type" "htm")
114   (set_attr "length" "4")])
115
116(define_insn "treclaim"
117  [(set (match_operand:CC 1 "cc_reg_operand" "=x")
118	(unspec_volatile:CC [(match_operand:SI 0 "gpc_reg_operand" "r")]
119			    UNSPECV_HTM_TRECLAIM))]
120  "TARGET_HTM"
121  "treclaim. %0"
122  [(set_attr "type" "htm")
123   (set_attr "length" "4")])
124
125(define_insn "tsr"
126  [(set (match_operand:CC 1 "cc_reg_operand" "=x")
127	(unspec_volatile:CC [(match_operand 0 "const_0_to_1_operand" "n")]
128			    UNSPECV_HTM_TSR))]
129  "TARGET_HTM"
130  "tsr. %0"
131  [(set_attr "type" "htm")
132   (set_attr "length" "4")])
133
134(define_insn "ttest"
135  [(set (match_operand:CC 0 "cc_reg_operand" "=x")
136	(unspec_volatile:CC [(const_int 0)]
137			    UNSPECV_HTM_TTEST))]
138  "TARGET_HTM"
139  "tabortwci. 0,1,0"
140  [(set_attr "type" "htm")
141   (set_attr "length" "4")])
142
143(define_insn "htm_mfspr_<mode>"
144  [(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
145        (unspec_volatile:GPR [(match_operand 1 "u10bit_cint_operand" "n")
146			      (match_operand:GPR 2 "htm_spr_reg_operand" "")]
147			     UNSPECV_HTM_MFSPR))]
148  "TARGET_HTM"
149  "mfspr %0,%1";
150  [(set_attr "type" "htm")
151   (set_attr "length" "4")])
152
153(define_insn "htm_mtspr_<mode>"
154  [(set (match_operand:GPR 2 "htm_spr_reg_operand" "")
155        (unspec_volatile:GPR [(match_operand:GPR 0 "gpc_reg_operand" "r")
156			      (match_operand 1 "u10bit_cint_operand" "n")]
157			     UNSPECV_HTM_MTSPR))]
158  "TARGET_HTM"
159  "mtspr %1,%0";
160  [(set_attr "type" "htm")
161   (set_attr "length" "4")])
162