1;; Pipeline description for Motorola PowerPC e500mc core. 2;; Copyright (C) 2008-2013 Free Software Foundation, Inc. 3;; Contributed by Edmar Wienskoski (edmar@freescale.com) 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20;; 21;; e500mc 32-bit SU(2), LSU, FPU, BPU 22;; Max issue 3 insns/clock cycle (includes 1 branch) 23;; FP is half clocked, timings of other instructions are as in the e500v2. 24 25(define_automaton "e500mc_most,e500mc_long,e500mc_retire") 26(define_cpu_unit "e500mc_decode_0,e500mc_decode_1" "e500mc_most") 27(define_cpu_unit "e500mc_issue_0,e500mc_issue_1" "e500mc_most") 28(define_cpu_unit "e500mc_retire_0,e500mc_retire_1" "e500mc_retire") 29 30;; SU. 31(define_cpu_unit "e500mc_su0_stage0,e500mc_su1_stage0" "e500mc_most") 32 33;; MU. 34(define_cpu_unit "e500mc_mu_stage0,e500mc_mu_stage1" "e500mc_most") 35(define_cpu_unit "e500mc_mu_stage2,e500mc_mu_stage3" "e500mc_most") 36 37;; Non-pipelined division. 38(define_cpu_unit "e500mc_mu_div" "e500mc_long") 39 40;; LSU. 41(define_cpu_unit "e500mc_lsu" "e500mc_most") 42 43;; FPU. 44(define_cpu_unit "e500mc_fpu" "e500mc_most") 45 46;; Branch unit. 47(define_cpu_unit "e500mc_bu" "e500mc_most") 48 49;; The following units are used to make the automata deterministic. 50(define_cpu_unit "present_e500mc_decode_0" "e500mc_most") 51(define_cpu_unit "present_e500mc_issue_0" "e500mc_most") 52(define_cpu_unit "present_e500mc_retire_0" "e500mc_retire") 53(define_cpu_unit "present_e500mc_su0_stage0" "e500mc_most") 54 55;; The following sets to make automata deterministic when option ndfa is used. 56(presence_set "present_e500mc_decode_0" "e500mc_decode_0") 57(presence_set "present_e500mc_issue_0" "e500mc_issue_0") 58(presence_set "present_e500mc_retire_0" "e500mc_retire_0") 59(presence_set "present_e500mc_su0_stage0" "e500mc_su0_stage0") 60 61;; Some useful abbreviations. 62(define_reservation "e500mc_decode" 63 "e500mc_decode_0|e500mc_decode_1+present_e500mc_decode_0") 64(define_reservation "e500mc_issue" 65 "e500mc_issue_0|e500mc_issue_1+present_e500mc_issue_0") 66(define_reservation "e500mc_retire" 67 "e500mc_retire_0|e500mc_retire_1+present_e500mc_retire_0") 68(define_reservation "e500mc_su_stage0" 69 "e500mc_su0_stage0|e500mc_su1_stage0+present_e500mc_su0_stage0") 70 71;; Simple SU insns. 72(define_insn_reservation "e500mc_su" 1 73 (and (eq_attr "type" "integer,insert_word,insert_dword,cmp,compare,\ 74 delayed_compare,var_delayed_compare,fast_compare,\ 75 shift,trap,var_shift_rotate,cntlz,exts,isel") 76 (eq_attr "cpu" "ppce500mc")) 77 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire") 78 79(define_insn_reservation "e500mc_two" 1 80 (and (eq_attr "type" "two") 81 (eq_attr "cpu" "ppce500mc")) 82 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\ 83 e500mc_issue+e500mc_su_stage0+e500mc_retire") 84 85(define_insn_reservation "e500mc_three" 1 86 (and (eq_attr "type" "three") 87 (eq_attr "cpu" "ppce500mc")) 88 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire,\ 89 e500mc_issue+e500mc_su_stage0+e500mc_retire,\ 90 e500mc_issue+e500mc_su_stage0+e500mc_retire") 91 92;; Multiply. 93(define_insn_reservation "e500mc_multiply" 4 94 (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 95 (eq_attr "cpu" "ppce500mc")) 96 "e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\ 97 e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire") 98 99;; Divide. We use the average latency time here. 100(define_insn_reservation "e500mc_divide" 14 101 (and (eq_attr "type" "idiv") 102 (eq_attr "cpu" "ppce500mc")) 103 "e500mc_decode,e500mc_issue+e500mc_mu_stage0+e500mc_mu_div,\ 104 e500mc_mu_div*13") 105 106;; Branch. 107(define_insn_reservation "e500mc_branch" 1 108 (and (eq_attr "type" "jmpreg,branch,isync") 109 (eq_attr "cpu" "ppce500mc")) 110 "e500mc_decode,e500mc_bu,e500mc_retire") 111 112;; CR logical. 113(define_insn_reservation "e500mc_cr_logical" 1 114 (and (eq_attr "type" "cr_logical,delayed_cr") 115 (eq_attr "cpu" "ppce500mc")) 116 "e500mc_decode,e500mc_bu,e500mc_retire") 117 118;; Mfcr. 119(define_insn_reservation "e500mc_mfcr" 1 120 (and (eq_attr "type" "mfcr") 121 (eq_attr "cpu" "ppce500mc")) 122 "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire") 123 124;; Mtcrf. 125(define_insn_reservation "e500mc_mtcrf" 1 126 (and (eq_attr "type" "mtcr") 127 (eq_attr "cpu" "ppce500mc")) 128 "e500mc_decode,e500mc_issue+e500mc_su1_stage0+e500mc_retire") 129 130;; Mtjmpr. 131(define_insn_reservation "e500mc_mtjmpr" 1 132 (and (eq_attr "type" "mtjmpr,mfjmpr") 133 (eq_attr "cpu" "ppce500mc")) 134 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire") 135 136;; Brinc. 137(define_insn_reservation "e500mc_brinc" 1 138 (and (eq_attr "type" "brinc") 139 (eq_attr "cpu" "ppce500mc")) 140 "e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire") 141 142;; Loads. 143(define_insn_reservation "e500mc_load" 3 144 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u,\ 145 load_l,sync") 146 (eq_attr "cpu" "ppce500mc")) 147 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") 148 149(define_insn_reservation "e500mc_fpload" 4 150 (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 151 (eq_attr "cpu" "ppce500mc")) 152 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing*2,e500mc_retire") 153 154;; Stores. 155(define_insn_reservation "e500mc_store" 3 156 (and (eq_attr "type" "store,store_ux,store_u,store_c") 157 (eq_attr "cpu" "ppce500mc")) 158 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") 159 160(define_insn_reservation "e500mc_fpstore" 3 161 (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") 162 (eq_attr "cpu" "ppce500mc")) 163 "e500mc_decode,e500mc_issue+e500mc_lsu,nothing,e500mc_retire") 164 165;; The following ignores the retire unit to avoid a large automata. 166 167;; Simple FP. 168(define_insn_reservation "e500mc_simple_float" 8 169 (and (eq_attr "type" "fpsimple") 170 (eq_attr "cpu" "ppce500mc")) 171 "e500mc_decode,e500mc_issue+e500mc_fpu") 172; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire") 173 174;; FP. 175(define_insn_reservation "e500mc_float" 8 176 (and (eq_attr "type" "fp") 177 (eq_attr "cpu" "ppce500mc")) 178 "e500mc_decode,e500mc_issue+e500mc_fpu") 179; "e500mc_decode,e500mc_issue+e500mc_fpu,nothing*6,e500mc_retire") 180 181(define_insn_reservation "e500mc_fpcompare" 8 182 (and (eq_attr "type" "fpcompare") 183 (eq_attr "cpu" "ppce500mc")) 184 "e500mc_decode,e500mc_issue+e500mc_fpu") 185 186(define_insn_reservation "e500mc_dmul" 10 187 (and (eq_attr "type" "dmul") 188 (eq_attr "cpu" "ppce500mc")) 189 "e500mc_decode,e500mc_issue+e500mc_fpu") 190 191;; FP divides are not pipelined. 192(define_insn_reservation "e500mc_sdiv" 36 193 (and (eq_attr "type" "sdiv") 194 (eq_attr "cpu" "ppce500mc")) 195 "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*35") 196 197(define_insn_reservation "e500mc_ddiv" 66 198 (and (eq_attr "type" "ddiv") 199 (eq_attr "cpu" "ppce500mc")) 200 "e500mc_decode,e500mc_issue+e500mc_fpu,e500mc_fpu*65") 201