1;; Pipeline description for Motorola PowerPC e300c3 core. 2;; Copyright (C) 2008-2013 Free Software Foundation, Inc. 3;; Contributed by Edmar Wienskoski (edmar@freescale.com) 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_automaton "ppce300c3_most,ppce300c3_long,ppce300c3_retire") 22(define_cpu_unit "ppce300c3_decode_0,ppce300c3_decode_1" "ppce300c3_most") 23 24;; We don't simulate general issue queue (GIC). If we have SU insn 25;; and then SU1 insn, they can not be issued on the same cycle 26;; (although SU1 insn and then SU insn can be issued) because the SU 27;; insn will go to SU1 from GIC0 entry. Fortunately, the first cycle 28;; multipass insn scheduling will find the situation and issue the SU1 29;; insn and then the SU insn. 30(define_cpu_unit "ppce300c3_issue_0,ppce300c3_issue_1" "ppce300c3_most") 31 32;; We could describe completion buffers slots in combination with the 33;; retirement units and the order of completion but the result 34;; automaton would behave in the same way because we can not describe 35;; real latency time with taking in order completion into account. 36;; Actually we could define the real latency time by querying reserved 37;; automaton units but the current scheduler uses latency time before 38;; issuing insns and making any reservations. 39;; 40;; So our description is aimed to achieve a insn schedule in which the 41;; insns would not wait in the completion buffer. 42(define_cpu_unit "ppce300c3_retire_0,ppce300c3_retire_1" "ppce300c3_retire") 43 44;; Branch unit: 45(define_cpu_unit "ppce300c3_bu" "ppce300c3_most") 46 47;; IU: 48(define_cpu_unit "ppce300c3_iu0_stage0,ppce300c3_iu1_stage0" "ppce300c3_most") 49 50;; IU: This used to describe non-pipelined division. 51(define_cpu_unit "ppce300c3_mu_div" "ppce300c3_long") 52 53;; SRU: 54(define_cpu_unit "ppce300c3_sru_stage0" "ppce300c3_most") 55 56;; Here we simplified LSU unit description not describing the stages. 57(define_cpu_unit "ppce300c3_lsu" "ppce300c3_most") 58 59;; FPU: 60(define_cpu_unit "ppce300c3_fpu" "ppce300c3_most") 61 62;; The following units are used to make automata deterministic 63(define_cpu_unit "present_ppce300c3_decode_0" "ppce300c3_most") 64(define_cpu_unit "present_ppce300c3_issue_0" "ppce300c3_most") 65(define_cpu_unit "present_ppce300c3_retire_0" "ppce300c3_retire") 66(define_cpu_unit "present_ppce300c3_iu0_stage0" "ppce300c3_most") 67 68;; The following sets to make automata deterministic when option ndfa is used. 69(presence_set "present_ppce300c3_decode_0" "ppce300c3_decode_0") 70(presence_set "present_ppce300c3_issue_0" "ppce300c3_issue_0") 71(presence_set "present_ppce300c3_retire_0" "ppce300c3_retire_0") 72(presence_set "present_ppce300c3_iu0_stage0" "ppce300c3_iu0_stage0") 73 74;; Some useful abbreviations. 75(define_reservation "ppce300c3_decode" 76 "ppce300c3_decode_0|ppce300c3_decode_1+present_ppce300c3_decode_0") 77(define_reservation "ppce300c3_issue" 78 "ppce300c3_issue_0|ppce300c3_issue_1+present_ppce300c3_issue_0") 79(define_reservation "ppce300c3_retire" 80 "ppce300c3_retire_0|ppce300c3_retire_1+present_ppce300c3_retire_0") 81(define_reservation "ppce300c3_iu_stage0" 82 "ppce300c3_iu0_stage0|ppce300c3_iu1_stage0+present_ppce300c3_iu0_stage0") 83 84;; Compares can be executed either one of the IU or SRU 85(define_insn_reservation "ppce300c3_cmp" 1 86 (and (eq_attr "type" "cmp,compare,delayed_compare,fast_compare") 87 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 88 "ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \ 89 +ppce300c3_retire") 90 91;; Other one cycle IU insns 92(define_insn_reservation "ppce300c3_iu" 1 93 (and (eq_attr "type" "integer,insert_word,isel") 94 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 95 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire") 96 97;; Branch. Actually this latency time is not used by the scheduler. 98(define_insn_reservation "ppce300c3_branch" 1 99 (and (eq_attr "type" "jmpreg,branch") 100 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 101 "ppce300c3_decode,ppce300c3_bu,ppce300c3_retire") 102 103;; Multiply is non-pipelined but can be executed in any IU 104(define_insn_reservation "ppce300c3_multiply" 2 105 (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 106 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 107 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \ 108 ppce300c3_iu_stage0+ppce300c3_retire") 109 110;; Divide. We use the average latency time here. We omit reserving a 111;; retire unit because of the result automata will be huge. 112(define_insn_reservation "ppce300c3_divide" 20 113 (and (eq_attr "type" "idiv") 114 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 115 "ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_mu_div,\ 116 ppce300c3_mu_div*19") 117 118;; CR logical 119(define_insn_reservation "ppce300c3_cr_logical" 1 120 (and (eq_attr "type" "cr_logical,delayed_cr") 121 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 122 "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") 123 124;; Mfcr 125(define_insn_reservation "ppce300c3_mfcr" 1 126 (and (eq_attr "type" "mfcr") 127 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 128 "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") 129 130;; Mtcrf 131(define_insn_reservation "ppce300c3_mtcrf" 1 132 (and (eq_attr "type" "mtcr") 133 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 134 "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") 135 136;; Mtjmpr 137(define_insn_reservation "ppce300c3_mtjmpr" 1 138 (and (eq_attr "type" "mtjmpr,mfjmpr") 139 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 140 "ppce300c3_decode,ppce300c3_issue+ppce300c3_sru_stage0+ppce300c3_retire") 141 142;; Float point instructions 143(define_insn_reservation "ppce300c3_fpcompare" 3 144 (and (eq_attr "type" "fpcompare") 145 (eq_attr "cpu" "ppce300c3")) 146 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") 147 148(define_insn_reservation "ppce300c3_fp" 3 149 (and (eq_attr "type" "fp") 150 (eq_attr "cpu" "ppce300c3")) 151 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,nothing,ppce300c3_retire") 152 153(define_insn_reservation "ppce300c3_dmul" 4 154 (and (eq_attr "type" "dmul") 155 (eq_attr "cpu" "ppce300c3")) 156 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu,nothing,ppce300c3_retire") 157 158; Divides are not pipelined 159(define_insn_reservation "ppce300c3_sdiv" 18 160 (and (eq_attr "type" "sdiv") 161 (eq_attr "cpu" "ppce300c3")) 162 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*17") 163 164(define_insn_reservation "ppce300c3_ddiv" 33 165 (and (eq_attr "type" "ddiv") 166 (eq_attr "cpu" "ppce300c3")) 167 "ppce300c3_decode,ppce300c3_issue+ppce300c3_fpu,ppce300c3_fpu*32") 168 169;; Loads 170(define_insn_reservation "ppce300c3_load" 2 171 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") 172 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 173 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") 174 175(define_insn_reservation "ppce300c3_fpload" 2 176 (and (eq_attr "type" "fpload,fpload_ux,fpload_u") 177 (eq_attr "cpu" "ppce300c3")) 178 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") 179 180;; Stores. 181(define_insn_reservation "ppce300c3_store" 2 182 (and (eq_attr "type" "store,store_ux,store_u") 183 (ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3"))) 184 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") 185 186(define_insn_reservation "ppce300c3_fpstore" 2 187 (and (eq_attr "type" "fpstore,fpstore_ux,fpstore_u") 188 (eq_attr "cpu" "ppce300c3")) 189 "ppce300c3_decode,ppce300c3_issue+ppce300c3_lsu,ppce300c3_retire") 190