1;; Constraint definitions for RS6000 2;; Copyright (C) 2006-2019 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5;; 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10;; 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15;; 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;; Available constraint letters: e k q t u A B C D S T 21 22;; Register constraints 23 24(define_register_constraint "f" "rs6000_constraints[RS6000_CONSTRAINT_f]" 25 "@internal") 26 27(define_register_constraint "d" "rs6000_constraints[RS6000_CONSTRAINT_d]" 28 "@internal") 29 30(define_register_constraint "b" "BASE_REGS" 31 "@internal") 32 33(define_register_constraint "h" "SPECIAL_REGS" 34 "@internal") 35 36(define_register_constraint "c" "CTR_REGS" 37 "@internal") 38 39(define_register_constraint "l" "LINK_REGS" 40 "@internal") 41 42(define_register_constraint "v" "ALTIVEC_REGS" 43 "@internal") 44 45(define_register_constraint "x" "CR0_REGS" 46 "@internal") 47 48(define_register_constraint "y" "CR_REGS" 49 "@internal") 50 51(define_register_constraint "z" "CA_REGS" 52 "@internal") 53 54;; Use w as a prefix to add VSX modes 55;; any VSX register 56(define_register_constraint "wa" "rs6000_constraints[RS6000_CONSTRAINT_wa]" 57 "Any VSX register if the -mvsx option was used or NO_REGS.") 58 59(define_register_constraint "wb" "rs6000_constraints[RS6000_CONSTRAINT_wb]" 60 "Altivec register if the -mpower9-dform option was used or NO_REGS.") 61 62;; NOTE: For compatibility, "wc" is reserved to represent individual CR bits. 63;; It is currently used for that purpose in LLVM. 64 65(define_register_constraint "wd" "rs6000_constraints[RS6000_CONSTRAINT_wd]" 66 "VSX vector register to hold vector double data or NO_REGS.") 67 68(define_register_constraint "we" "rs6000_constraints[RS6000_CONSTRAINT_we]" 69 "VSX register if the -mpower9-vector -m64 options were used or NO_REGS.") 70 71(define_register_constraint "wf" "rs6000_constraints[RS6000_CONSTRAINT_wf]" 72 "VSX vector register to hold vector float data or NO_REGS.") 73 74(define_register_constraint "wg" "rs6000_constraints[RS6000_CONSTRAINT_wg]" 75 "If -mmfpgpr was used, a floating point register or NO_REGS.") 76 77(define_register_constraint "wh" "rs6000_constraints[RS6000_CONSTRAINT_wh]" 78 "Floating point register if direct moves are available, or NO_REGS.") 79 80(define_register_constraint "wi" "rs6000_constraints[RS6000_CONSTRAINT_wi]" 81 "FP or VSX register to hold 64-bit integers for VSX insns or NO_REGS.") 82 83(define_register_constraint "wj" "rs6000_constraints[RS6000_CONSTRAINT_wj]" 84 "FP or VSX register to hold 64-bit integers for direct moves or NO_REGS.") 85 86(define_register_constraint "wk" "rs6000_constraints[RS6000_CONSTRAINT_wk]" 87 "FP or VSX register to hold 64-bit doubles for direct moves or NO_REGS.") 88 89(define_register_constraint "wl" "rs6000_constraints[RS6000_CONSTRAINT_wl]" 90 "Floating point register if the LFIWAX instruction is enabled or NO_REGS.") 91 92(define_register_constraint "wm" "rs6000_constraints[RS6000_CONSTRAINT_wm]" 93 "VSX register if direct move instructions are enabled, or NO_REGS.") 94 95;; NO_REGs register constraint, used to merge mov{sd,sf}, since movsd can use 96;; direct move directly, and movsf can't to move between the register sets. 97;; There is a mode_attr that resolves to wm for SDmode and wn for SFmode 98(define_register_constraint "wn" "NO_REGS" "No register (NO_REGS).") 99 100(define_register_constraint "wo" "rs6000_constraints[RS6000_CONSTRAINT_wo]" 101 "VSX register if the -mpower9-vector option was used or NO_REGS.") 102 103(define_register_constraint "wp" "rs6000_constraints[RS6000_CONSTRAINT_wp]" 104 "VSX register to use for IEEE 128-bit fp TFmode, or NO_REGS.") 105 106(define_register_constraint "wq" "rs6000_constraints[RS6000_CONSTRAINT_wq]" 107 "VSX register to use for IEEE 128-bit fp KFmode, or NO_REGS.") 108 109(define_register_constraint "wr" "rs6000_constraints[RS6000_CONSTRAINT_wr]" 110 "General purpose register if 64-bit instructions are enabled or NO_REGS.") 111 112(define_register_constraint "ws" "rs6000_constraints[RS6000_CONSTRAINT_ws]" 113 "VSX vector register to hold scalar double values or NO_REGS.") 114 115(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]" 116 "VSX vector register to hold 128 bit integer or NO_REGS.") 117 118(define_register_constraint "wu" "rs6000_constraints[RS6000_CONSTRAINT_wu]" 119 "Altivec register to use for float/32-bit int loads/stores or NO_REGS.") 120 121(define_register_constraint "wv" "rs6000_constraints[RS6000_CONSTRAINT_wv]" 122 "Altivec register to use for double loads/stores or NO_REGS.") 123 124(define_register_constraint "ww" "rs6000_constraints[RS6000_CONSTRAINT_ww]" 125 "FP or VSX register to perform float operations under -mvsx or NO_REGS.") 126 127(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]" 128 "Floating point register if the STFIWX instruction is enabled or NO_REGS.") 129 130(define_register_constraint "wy" "rs6000_constraints[RS6000_CONSTRAINT_wy]" 131 "FP or VSX register to perform ISA 2.07 float ops or NO_REGS.") 132 133(define_register_constraint "wz" "rs6000_constraints[RS6000_CONSTRAINT_wz]" 134 "Floating point register if the LFIWZX instruction is enabled or NO_REGS.") 135 136(define_register_constraint "wA" "rs6000_constraints[RS6000_CONSTRAINT_wA]" 137 "BASE_REGS if 64-bit instructions are enabled or NO_REGS.") 138 139;; wB needs ISA 2.07 VUPKHSW 140(define_constraint "wB" 141 "Signed 5-bit constant integer that can be loaded into an altivec register." 142 (and (match_code "const_int") 143 (and (match_test "TARGET_P8_VECTOR") 144 (match_operand 0 "s5bit_cint_operand")))) 145 146(define_constraint "wD" 147 "Int constant that is the element number of the 64-bit scalar in a vector." 148 (and (match_code "const_int") 149 (match_test "TARGET_VSX && (ival == VECTOR_ELEMENT_SCALAR_64BIT)"))) 150 151(define_constraint "wE" 152 "Vector constant that can be loaded with the XXSPLTIB instruction." 153 (match_test "xxspltib_constant_nosplit (op, mode)")) 154 155;; Extended fusion store 156(define_memory_constraint "wF" 157 "Memory operand suitable for power8 GPR load fusion" 158 (match_operand 0 "fusion_addis_mem_combo_load")) 159 160(define_register_constraint "wH" "rs6000_constraints[RS6000_CONSTRAINT_wH]" 161 "Altivec register to hold 32-bit integers or NO_REGS.") 162 163(define_register_constraint "wI" "rs6000_constraints[RS6000_CONSTRAINT_wI]" 164 "FPR register to hold 32-bit integers or NO_REGS.") 165 166(define_register_constraint "wJ" "rs6000_constraints[RS6000_CONSTRAINT_wJ]" 167 "FPR register to hold 8/16-bit integers or NO_REGS.") 168 169(define_register_constraint "wK" "rs6000_constraints[RS6000_CONSTRAINT_wK]" 170 "Altivec register to hold 8/16-bit integers or NO_REGS.") 171 172(define_constraint "wL" 173 "Int constant that is the element number mfvsrld accesses in a vector." 174 (and (match_code "const_int") 175 (and (match_test "TARGET_DIRECT_MOVE_128") 176 (match_test "(ival == VECTOR_ELEMENT_MFVSRLD_64BIT)")))) 177 178;; Generate the XXORC instruction to set a register to all 1's 179(define_constraint "wM" 180 "Match vector constant with all 1's if the XXLORC instruction is available" 181 (and (match_test "TARGET_P8_VECTOR") 182 (match_operand 0 "all_ones_constant"))) 183 184;; ISA 3.0 vector d-form addresses 185(define_memory_constraint "wO" 186 "Memory operand suitable for the ISA 3.0 vector d-form instructions." 187 (match_operand 0 "vsx_quad_dform_memory_operand")) 188 189;; Lq/stq validates the address for load/store quad 190(define_memory_constraint "wQ" 191 "Memory operand suitable for the load/store quad instructions" 192 (match_operand 0 "quad_memory_operand")) 193 194(define_constraint "wS" 195 "Vector constant that can be loaded with XXSPLTIB & sign extension." 196 (match_test "xxspltib_constant_split (op, mode)")) 197 198;; ISA 3.0 DS-form instruction that has the bottom 2 bits 0 and no update form. 199;; Used by LXSD/STXSD/LXSSP/STXSSP. In contrast to "Y", the multiple-of-four 200;; offset is enforced for 32-bit too. 201(define_memory_constraint "wY" 202 "Offsettable memory operand, with bottom 2 bits 0" 203 (and (match_code "mem") 204 (not (match_test "update_address_mem (op, mode)")) 205 (match_test "mem_operand_ds_form (op, mode)"))) 206 207;; Altivec style load/store that ignores the bottom bits of the address 208(define_memory_constraint "wZ" 209 "Indexed or indirect memory operand, ignoring the bottom 4 bits" 210 (match_operand 0 "altivec_indexed_or_indirect_operand")) 211 212;; Integer constraints 213 214(define_constraint "I" 215 "A signed 16-bit constant" 216 (and (match_code "const_int") 217 (match_test "((unsigned HOST_WIDE_INT) ival + 0x8000) < 0x10000"))) 218 219(define_constraint "J" 220 "high-order 16 bits nonzero" 221 (and (match_code "const_int") 222 (match_test "(ival & (~ (unsigned HOST_WIDE_INT) 0xffff0000)) == 0"))) 223 224(define_constraint "K" 225 "low-order 16 bits nonzero" 226 (and (match_code "const_int") 227 (match_test "(ival & (~ (HOST_WIDE_INT) 0xffff)) == 0"))) 228 229(define_constraint "L" 230 "signed 16-bit constant shifted left 16 bits" 231 (and (match_code "const_int") 232 (match_test "((ival & 0xffff) == 0 233 && (ival >> 31 == -1 || ival >> 31 == 0))"))) 234 235(define_constraint "M" 236 "constant greater than 31" 237 (and (match_code "const_int") 238 (match_test "ival > 31"))) 239 240(define_constraint "N" 241 "positive constant that is an exact power of two" 242 (and (match_code "const_int") 243 (match_test "ival > 0 && exact_log2 (ival) >= 0"))) 244 245(define_constraint "O" 246 "constant zero" 247 (and (match_code "const_int") 248 (match_test "ival == 0"))) 249 250(define_constraint "P" 251 "constant whose negation is signed 16-bit constant" 252 (and (match_code "const_int") 253 (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000"))) 254 255;; Floating-point constraints. These two are defined so that insn 256;; length attributes can be calculated exactly. 257 258(define_constraint "G" 259 "Constant that can be copied into GPR with two insns for DF/DD 260 and one for SF/SD." 261 (and (match_code "const_double") 262 (match_test "num_insns_constant (op, mode) 263 == (mode == SFmode || mode == SDmode ? 1 : 2)"))) 264 265(define_constraint "H" 266 "DF/DD constant that takes three insns." 267 (and (match_code "const_double") 268 (match_test "num_insns_constant (op, mode) == 3"))) 269 270;; Memory constraints 271 272(define_memory_constraint "es" 273 "A ``stable'' memory operand; that is, one which does not include any 274automodification of the base register. Unlike @samp{m}, this constraint 275can be used in @code{asm} statements that might access the operand 276several times, or that might not access it at all." 277 (and (match_code "mem") 278 (match_test "GET_RTX_CLASS (GET_CODE (XEXP (op, 0))) != RTX_AUTOINC"))) 279 280(define_memory_constraint "Q" 281 "Memory operand that is an offset from a register (it is usually better 282to use @samp{m} or @samp{es} in @code{asm} statements)" 283 (and (match_code "mem") 284 (match_test "REG_P (XEXP (op, 0))"))) 285 286(define_memory_constraint "Y" 287 "memory operand for 8 byte and 16 byte gpr load/store" 288 (and (match_code "mem") 289 (match_test "mem_operand_gpr (op, mode)"))) 290 291(define_memory_constraint "Z" 292 "Memory operand that is an indexed or indirect from a register (it is 293usually better to use @samp{m} or @samp{es} in @code{asm} statements)" 294 (match_operand 0 "indexed_or_indirect_operand")) 295 296;; Address constraints 297 298(define_address_constraint "a" 299 "Indexed or indirect address operand" 300 (match_operand 0 "indexed_or_indirect_address")) 301 302(define_constraint "R" 303 "AIX TOC entry" 304 (match_test "legitimate_constant_pool_address_p (op, QImode, false)")) 305 306;; General constraints 307 308(define_constraint "U" 309 "V.4 small data reference" 310 (and (match_test "DEFAULT_ABI == ABI_V4") 311 (match_test "small_data_operand (op, mode)"))) 312 313(define_constraint "W" 314 "vector constant that does not require memory" 315 (match_operand 0 "easy_vector_constant")) 316 317(define_constraint "j" 318 "Zero vector constant" 319 (match_test "op == const0_rtx || op == CONST0_RTX (mode)")) 320