1;; Scheduling description for PowerPC A2 processors. 2;; Copyright (C) 2009 Free Software Foundation, Inc. 3;; Contributed by Ben Elliston (bje@au.ibm.com) 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_automaton "ppca2") 22 23;; CPU units 24 25;; The multiplier pipeline. 26(define_cpu_unit "mult" "ppca2") 27 28;; The auxillary processor unit (FP/vector unit). 29(define_cpu_unit "axu" "ppca2") 30 31;; D.4.6 32;; Some peculiarities for certain SPRs 33 34(define_insn_reservation "ppca2-mfcr" 1 35 (and (eq_attr "type" "mfcr") 36 (eq_attr "cpu" "ppca2")) 37 "nothing") 38 39(define_insn_reservation "ppca2-mfjmpr" 5 40 (and (eq_attr "type" "mfjmpr") 41 (eq_attr "cpu" "ppca2")) 42 "nothing") 43 44(define_insn_reservation "ppca2-mtjmpr" 5 45 (and (eq_attr "type" "mtjmpr") 46 (eq_attr "cpu" "ppca2")) 47 "nothing") 48 49;; D.4.8 50(define_insn_reservation "ppca2-imul" 1 51 (and (eq_attr "type" "imul,imul2,imul3,imul_compare") 52 (eq_attr "cpu" "ppca2")) 53 "nothing") 54 55;; FIXME: latency and multiplier reservation for 64-bit multiply? 56(define_insn_reservation "ppca2-lmul" 6 57 (and (eq_attr "type" "lmul,lmul_compare") 58 (eq_attr "cpu" "ppca2")) 59 "mult*3") 60 61;; D.4.9 62(define_insn_reservation "ppca2-idiv" 32 63 (and (eq_attr "type" "idiv") 64 (eq_attr "cpu" "ppca2")) 65 "mult*32") 66 67(define_insn_reservation "ppca2-ldiv" 65 68 (and (eq_attr "type" "ldiv") 69 (eq_attr "cpu" "ppca2")) 70 "mult*65") 71 72;; D.4.13 73(define_insn_reservation "ppca2-load" 5 74 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,load_ux,load_u") 75 (eq_attr "cpu" "ppca2")) 76 "nothing") 77 78;; D.8.1 79(define_insn_reservation "ppca2-fp" 6 80 (and (eq_attr "type" "fp") ;; Ignore fpsimple insn types (SPE only). 81 (eq_attr "cpu" "ppca2")) 82 "axu") 83 84;; D.8.4 85(define_insn_reservation "ppca2-fp-load" 6 86 (and (eq_attr "type" "fpload,fpload_u,fpload_ux") 87 (eq_attr "cpu" "ppca2")) 88 "axu") 89 90;; D.8.5 91(define_insn_reservation "ppca2-fp-store" 2 92 (and (eq_attr "type" "fpstore,fpstore_u,fpstore_ux") 93 (eq_attr "cpu" "ppca2")) 94 "axu") 95 96;; D.8.6 97(define_insn_reservation "ppca2-fpcompare" 5 98 (and (eq_attr "type" "fpcompare") 99 (eq_attr "cpu" "ppca2")) 100 "axu") 101 102;; D.8.7 103;; 104;; Instructions from the same thread succeeding the floating-point 105;; divide cannot be executed until the floating-point divide has 106;; completed. Since there is nothing else we can do, this thread will 107;; just have to stall. 108 109(define_insn_reservation "ppca2-ddiv" 72 110 (and (eq_attr "type" "ddiv") 111 (eq_attr "cpu" "ppca2")) 112 "axu") 113 114(define_insn_reservation "ppca2-sdiv" 59 115 (and (eq_attr "type" "sdiv") 116 (eq_attr "cpu" "ppca2")) 117 "axu") 118 119;; D.8.8 120;; 121;; Instructions from the same thread succeeding the floating-point 122;; divide cannot be executed until the floating-point divide has 123;; completed. Since there is nothing else we can do, this thread will 124;; just have to stall. 125 126(define_insn_reservation "ppca2-dsqrt" 69 127 (and (eq_attr "type" "dsqrt") 128 (eq_attr "cpu" "ppca2")) 129 "axu") 130 131(define_insn_reservation "ppca2-ssqrt" 65 132 (and (eq_attr "type" "ssqrt") 133 (eq_attr "cpu" "ppca2")) 134 "axu") 135