1;; Scheduling description for Motorola PowerPC 750 and PowerPC 7400 processors. 2;; Copyright (C) 2003-2013 Free Software Foundation, Inc. 3;; 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify it 7;; under the terms of the GNU General Public License as published 8;; by the Free Software Foundation; either version 3, or (at your 9;; option) any later version. 10 11;; GCC is distributed in the hope that it will be useful, but WITHOUT 12;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14;; License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20(define_automaton "ppc7xx,ppc7xxfp") 21(define_cpu_unit "iu1_7xx,iu2_7xx" "ppc7xx") 22(define_cpu_unit "fpu_7xx" "ppc7xxfp") 23(define_cpu_unit "lsu_7xx,bpu_7xx,sru_7xx" "ppc7xx") 24(define_cpu_unit "du1_7xx,du2_7xx" "ppc7xx") 25(define_cpu_unit "veccmplx_7xx,vecperm_7xx,vdu_7xx" "ppc7xx") 26 27;; PPC740/PPC750/PPC7400 32-bit 2xIU, LSU, SRU, FPU, BPU 28;; IU1 can perform all integer operations 29;; IU2 can perform all integer operations except imul and idiv 30;; LSU 2 stage pipelined 31;; FPU 3 stage pipelined 32;; Max issue 3 insns/clock cycle (includes 1 branch) 33;; In-order execution 34 35 36;; The PPC750 user's manual recommends that to reduce branch mispredictions, 37;; the insn that sets CR bits should be separated from the branch insn 38;; that evaluates them. There is no advantage have more than 10 cycles 39;; of separation. 40;; This could be artificially achieved by exaggerating the latency of 41;; compare insns but at the expense of a poorer schedule. 42 43;; Branches go straight to the BPU. All other insns are handled 44;; by a dispatch unit which can issue a max of 2 insns per cycle. 45(define_reservation "ppc750_du" "du1_7xx|du2_7xx") 46(define_reservation "ppc7400_vec_du" "vdu_7xx") 47 48(define_insn_reservation "ppc750-load" 2 49 (and (eq_attr "type" "load,load_ext,load_ext_u,load_ext_ux,\ 50 load_ux,load_u,fpload,fpload_ux,fpload_u,\ 51 vecload,load_l") 52 (eq_attr "cpu" "ppc750,ppc7400")) 53 "ppc750_du,lsu_7xx") 54 55(define_insn_reservation "ppc750-store" 2 56 (and (eq_attr "type" "store,store_ux,store_u,\ 57 fpstore,fpstore_ux,fpstore_u,vecstore") 58 (eq_attr "cpu" "ppc750,ppc7400")) 59 "ppc750_du,lsu_7xx") 60 61(define_insn_reservation "ppc750-storec" 8 62 (and (eq_attr "type" "store_c") 63 (eq_attr "cpu" "ppc750,ppc7400")) 64 "ppc750_du,lsu_7xx") 65 66(define_insn_reservation "ppc750-integer" 1 67 (and (eq_attr "type" "integer,insert_word,insert_dword,shift,\ 68 trap,var_shift_rotate,cntlz,exts,isel") 69 (eq_attr "cpu" "ppc750,ppc7400")) 70 "ppc750_du,iu1_7xx|iu2_7xx") 71 72(define_insn_reservation "ppc750-two" 1 73 (and (eq_attr "type" "two") 74 (eq_attr "cpu" "ppc750,ppc7400")) 75 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx") 76 77(define_insn_reservation "ppc750-three" 1 78 (and (eq_attr "type" "three") 79 (eq_attr "cpu" "ppc750,ppc7400")) 80 "ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx") 81 82(define_insn_reservation "ppc750-imul" 4 83 (and (eq_attr "type" "imul,imul_compare") 84 (eq_attr "cpu" "ppc750,ppc7400")) 85 "ppc750_du,iu1_7xx*4") 86 87(define_insn_reservation "ppc750-imul2" 3 88 (and (eq_attr "type" "imul2") 89 (eq_attr "cpu" "ppc750,ppc7400")) 90 "ppc750_du,iu1_7xx*2") 91 92(define_insn_reservation "ppc750-imul3" 2 93 (and (eq_attr "type" "imul3") 94 (eq_attr "cpu" "ppc750,ppc7400")) 95 "ppc750_du,iu1_7xx") 96 97(define_insn_reservation "ppc750-idiv" 19 98 (and (eq_attr "type" "idiv") 99 (eq_attr "cpu" "ppc750,ppc7400")) 100 "ppc750_du,iu1_7xx*19") 101 102(define_insn_reservation "ppc750-compare" 2 103 (and (eq_attr "type" "cmp,fast_compare,compare,delayed_compare,\ 104 var_delayed_compare") 105 (eq_attr "cpu" "ppc750,ppc7400")) 106 "ppc750_du,(iu1_7xx|iu2_7xx)") 107 108(define_insn_reservation "ppc750-fpcompare" 2 109 (and (eq_attr "type" "fpcompare") 110 (eq_attr "cpu" "ppc750,ppc7400")) 111 "ppc750_du,fpu_7xx") 112 113(define_insn_reservation "ppc750-fp" 3 114 (and (eq_attr "type" "fp") 115 (eq_attr "cpu" "ppc750,ppc7400")) 116 "ppc750_du,fpu_7xx") 117 118(define_insn_reservation "ppc750-dmul" 4 119 (and (eq_attr "type" "dmul") 120 (eq_attr "cpu" "ppc750")) 121 "ppc750_du,fpu_7xx*2") 122 123(define_insn_reservation "ppc7400-dmul" 3 124 (and (eq_attr "type" "dmul") 125 (eq_attr "cpu" "ppc7400")) 126 "ppc750_du,fpu_7xx") 127 128; Divides are not pipelined 129(define_insn_reservation "ppc750-sdiv" 17 130 (and (eq_attr "type" "sdiv") 131 (eq_attr "cpu" "ppc750,ppc7400")) 132 "ppc750_du,fpu_7xx*17") 133 134(define_insn_reservation "ppc750-ddiv" 31 135 (and (eq_attr "type" "ddiv") 136 (eq_attr "cpu" "ppc750,ppc7400")) 137 "ppc750_du,fpu_7xx*31") 138 139(define_insn_reservation "ppc750-mfcr" 2 140 (and (eq_attr "type" "mfcr,mtcr") 141 (eq_attr "cpu" "ppc750,ppc7400")) 142 "ppc750_du,iu1_7xx") 143 144(define_insn_reservation "ppc750-crlogical" 3 145 (and (eq_attr "type" "cr_logical,delayed_cr") 146 (eq_attr "cpu" "ppc750,ppc7400")) 147 "nothing,sru_7xx*2") 148 149(define_insn_reservation "ppc750-mtjmpr" 2 150 (and (eq_attr "type" "mtjmpr,isync,sync") 151 (eq_attr "cpu" "ppc750,ppc7400")) 152 "nothing,sru_7xx*2") 153 154(define_insn_reservation "ppc750-mfjmpr" 3 155 (and (eq_attr "type" "mfjmpr") 156 (eq_attr "cpu" "ppc750,ppc7400")) 157 "nothing,sru_7xx*2") 158 159(define_insn_reservation "ppc750-jmpreg" 1 160 (and (eq_attr "type" "jmpreg,branch,isync") 161 (eq_attr "cpu" "ppc750,ppc7400")) 162 "nothing,bpu_7xx") 163 164;; Altivec 165(define_insn_reservation "ppc7400-vecsimple" 1 166 (and (eq_attr "type" "vecsimple,veccmp") 167 (eq_attr "cpu" "ppc7400")) 168 "ppc750_du,ppc7400_vec_du,veccmplx_7xx") 169 170(define_insn_reservation "ppc7400-veccomplex" 4 171 (and (eq_attr "type" "veccomplex") 172 (eq_attr "cpu" "ppc7400")) 173 "ppc750_du,ppc7400_vec_du,veccmplx_7xx") 174 175(define_insn_reservation "ppc7400-vecfloat" 4 176 (and (eq_attr "type" "vecfloat") 177 (eq_attr "cpu" "ppc7400")) 178 "ppc750_du,ppc7400_vec_du,veccmplx_7xx") 179 180(define_insn_reservation "ppc7400-vecperm" 2 181 (and (eq_attr "type" "vecperm") 182 (eq_attr "cpu" "ppc7400")) 183 "ppc750_du,ppc7400_vec_du,vecperm_7xx") 184 185