1;; Machine Description for Renesas RL78 processors 2;; Copyright (C) 2011-2015 Free Software Foundation, Inc. 3;; Contributed by Red Hat. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; The insns in this file correspond to the actual opcodes the RL78 22;; can issue with real registers. All insns in here should be 23;; conditional on rl78_real_insns_ok() returning true, and should 24;; allow virtual registers in their predicates - the reorg pass that 25;; allocates physical registers uses the constraints to select 26;; registers, but insns with virtual registers MUST match one of these 27;; patterns - other than the constraints - so that the operand info is 28;; properly set up for the alloc pass. 29 30;; This attribute reflects how the insn alters the Z flag, 31;; based upon the value of the it's output. The default is NO 32;; for no change, but other possibilities are UPDATE_Z if it changes 33;; the Z flag and CLOBBER if the state of the flag is indeterminate. 34;; The CY and AC flags are not set in the same way as the Z flag, so 35;; their values are not tracked. 36(define_attr "update_Z" "no,update_Z,clobber" (const_string "no")) 37 38;;---------- Moving ------------------------ 39 40(define_insn "movqi_to_es" 41 [(set (reg:QI ES_REG) 42 (match_operand:QI 0 "register_operand" "a"))] 43 "" 44 "mov\tes, %0" 45) 46 47(define_insn "movqi_from_es" 48 [(set (match_operand:QI 0 "register_operand" "=a") 49 (reg:QI ES_REG))] 50 "" 51 "mov\t%0, es" 52) 53 54(define_insn "movqi_cs" 55 [(set (reg:QI CS_REG) 56 (match_operand:QI 0 "register_operand" "a"))] 57 "" 58 "mov\tcs, %0" 59) 60 61(define_insn "*movqi_real" 62 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=Rv,RaxbcWab,RaxbcWab,a, bcx,R, WabWd2WhlWh1WhbWbcWs1v, bcx,WsaWsf") 63 (match_operand 1 "rl78_general_operand" "0,K, M, RInt8sJvWabWdeWd2WhlWh1WhbWbcWs1,Wab,aInt8J,a, R, i"))] 64 "rl78_real_insns_ok ()" 65 "@ 66 ; mov\t%0, %1 67 oneb\t%0 68 clrb\t%0 69 mov\t%0, %1 70 mov\t%0, %1 71 mov\t%0, %1 72 mov\t%0, %1 73 mov\t%0, %S1 74 mov\t%0, %1" 75) 76 77(define_insn "*movhi_real" 78 [(set (match_operand:HI 0 "rl78_nonimmediate_operand" "=Rv,AB,AB,RSv,A,BDTvSWabWd2WdeWhlWh1WbcWs1, BDT,ABDT,v") 79 (match_operand:HI 1 "rl78_general_operand" " 0,K, M, i, BDTvSWabWd2WdeWh1WhlWbcWs1,A, BDT,vS, ABDT"))] 80 "rl78_real_insns_ok ()" 81 "@ 82 ; movw\t%0, %1 83 onew\t%0 84 clrw\t%0 85 movw\t%0, %1 86 movw\t%0, %1 87 movw\t%0, %1 88 movw\t%0, %S1 89 movw\t%0, %1 90 movw\t%0, %1" 91) 92 93;;---------- Conversions ------------------------ 94 95(define_insn "*zero_extendqihi2_real" 96 [(set (match_operand:HI 0 "nonimmediate_operand" "=Rv,A") 97 (zero_extend:HI (match_operand:QI 1 "general_operand" "0,a")))] 98 "rl78_real_insns_ok ()" 99 "@ 100 mov\t%Q0, #0 101 mov\tx, a \;mov\ta, #0" 102 ) 103 104(define_insn "*extendqihi2_real" 105 [(set (match_operand:HI 0 "nonimmediate_operand" "=A,A") 106 (sign_extend:HI (match_operand:QI 1 "general_operand" "x,a")))] 107 "rl78_real_insns_ok ()" 108 "@ 109 shlw\t%0, 8 \;sarw\t%0, 8 110 sarw\t%0, 8" 111 ) 112 113;;---------- Arithmetic ------------------------ 114 115(define_insn "*addqi3_real" 116 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=RvWabWhlWh1Wsa,RvWabWhlWh1Wsa,a,*bcdehl,Wsa") 117 (plus:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0,0") 118 (match_operand:QI 2 "rl78_general_operand" "K,L,RWhlWh1Wabi,a,i"))) 119 ] 120 "rl78_real_insns_ok ()" 121 "@ 122 inc\t%p0 123 dec\t%p0 124 add\t%0, %2 125 add\t%0, %2 126 add\t%0, %2" 127 [(set (attr "update_Z") (const_string "update_Z"))] 128) 129 130(define_insn "*addhi3_real" 131 [(set (match_operand:HI 0 "rl78_nonimmediate_operand" "=vABDTWhlWh1WabWsa,vABDTWhlWh1WabWsa,v,v,A,S,S,A") 132 (plus:HI (match_operand:HI 1 "rl78_general_operand" "%0,0,0,0,0,0,0,S") 133 (match_operand:HI 2 "" "K,L,N,O,RWh1WhlWabiv,Int8Qs8,J,Ri"))) 134 ] 135 "rl78_real_insns_ok ()" 136 "@ 137 incw\t%p0 138 decw\t%p0 139 incw\t%0 \;incw\t%0 140 decw\t%0 \;decw\t%0 141 addw\t%0, %p2 142 addw\t%0, %2 143 subw\t%0, %m2 144 movw\t%0, %1 \;addw\t%0, %2" 145 [(set_attr "update_Z" "*,*,*,*,update_Z,update_Z,update_Z,update_Z")] 146) 147 148(define_insn "*addqihi3a_real" 149 [(set (match_operand:HI 0 "register_operand" "=R") 150 (plus:HI (zero_extend:HI (match_operand:QI 1 "register_operand" "R")) 151 (match_operand:HI 2 "register_operand" "0"))) 152 ] 153 "rl78_real_insns_ok ()" 154 "add\t%q0, %q1 \;addc\t%Q0, #0" 155 [(set (attr "update_Z") (const_string "update_Z"))] 156) 157 158(define_insn "*subqi3_real" 159 [(set (match_operand:QI 0 "nonimmediate_operand" "=a,R,v") 160 (minus:QI (match_operand:QI 1 "general_operand" "0,0,0") 161 (match_operand:QI 2 "rl78_general_operand" "RiWabWhbWh1Whl,a,i"))) 162 ] 163 "rl78_real_insns_ok ()" 164 "sub\t%0, %2" 165 [(set (attr "update_Z") (const_string "update_Z"))] 166) 167 168(define_insn "*subhi3_real" 169 [(set (match_operand:HI 0 "nonimmediate_operand" "=A,S") 170 (minus:HI (match_operand:HI 1 "general_operand" "0,0") 171 (match_operand:HI 2 "rl78_general_operand" "iBDTWabWh1v,i"))) 172 ] 173 "rl78_real_insns_ok ()" 174 "subw\t%0, %2" 175 [(set (attr "update_Z") (const_string "update_Z"))] 176) 177 178(define_insn "*umulhi3_shift_real" 179 [(set (match_operand:HI 0 "register_operand" "=A,A") 180 (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "0,0") 181 (match_operand:HI 2 "rl78_24_operand" "N,i")))] 182 "rl78_real_insns_ok ()" 183 "@ 184 shlw\t%0, 1 185 shlw\t%0, 2" 186) 187 188(define_insn "*umulqihi3_real" 189 [(set (match_operand:HI 0 "nonimmediate_operand" "=A") 190 (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%a")) 191 (zero_extend:HI (match_operand:QI 2 "general_operand" "x"))))] 192 "rl78_real_insns_ok ()" 193 "mulu\t%2" 194) 195 196(define_insn "*andqi3_real" 197 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=Wsf,A,R,vWsa") 198 (and:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0") 199 (match_operand:QI 2 "rl78_general_operand" "IBqi,iRvWabWhbWh1Whl,A,i"))) 200 ] 201 "rl78_real_insns_ok ()" 202 "@ 203 clr1\t%0.%B2 204 and\t%0, %2 205 and\t%0, %2 206 and\t%0, %2" 207 [(set_attr "update_Z" "*,update_Z,update_Z,update_Z")] 208) 209 210(define_insn "*iorqi3_real" 211 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=Wsf,A,R,vWsa") 212 (ior:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0,0") 213 (match_operand:QI 2 "rl78_general_operand" "Ibqi,iRvWabWhbWh1Whl,A,i"))) 214 ] 215 "rl78_real_insns_ok ()" 216 "@ 217 set1\t%0.%B2 218 or\t%0, %2 219 or\t%0, %2 220 or\t%0, %2" 221 [(set_attr "update_Z" "*,update_Z,update_Z,update_Z")] 222) 223 224(define_insn "*xorqi3_real" 225 [(set (match_operand:QI 0 "rl78_nonimmediate_operand" "=A,R,vWsa") 226 (xor:QI (match_operand:QI 1 "rl78_general_operand" "%0,0,0") 227 (match_operand 2 "rl78_general_operand" "iRvWabWhbWh1Whl,A,i"))) 228 ] 229 "rl78_real_insns_ok ()" 230 "xor\t%0, %2" 231 [(set (attr "update_Z") (const_string "update_Z"))] 232) 233 234;;---------- Shifts ------------------------ 235 236(define_insn "*ashlqi3_real" 237 [(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a") 238 (ashift:QI (match_operand:QI 1 "general_operand" "0,0,0") 239 (match_operand:QI 2 "general_operand" "Int3,bc,dehl"))) 240 ] 241 "rl78_real_insns_ok ()" 242 "@ 243 shl\t%0, %u2 244 cmp0 %2\; bz $2f\; 1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2: 245 inc %2\;dec %2\;bz $2f\;1: shl\t%0, 1 \;dec %2 \;bnz $1b\;2:" 246 [(set_attr "update_Z" "*,clobber,clobber")] 247) 248 249(define_insn "*ashlhi3_real" 250 [(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A") 251 (ashift:HI (match_operand:HI 1 "general_operand" "0,0,0") 252 (match_operand:QI 2 "general_operand" "P,bc,dehl"))) 253 ] 254 "rl78_real_insns_ok ()" 255 "@ 256 shlw\t%0, %u2 257 cmp0 %2\; bz $2f\; 1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2: 258 inc %2\;dec %2\;bz $2f\;1: shlw\t%0, 1 \;dec %2 \;bnz $1b\;2:" 259 [(set_attr "update_Z" "*,clobber,clobber")] 260) 261 262;;---------- 263 264(define_insn "*ashrqi3_real" 265 [(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a") 266 (ashiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0") 267 (match_operand:QI 2 "general_operand" "Int3,bc,dehl"))) 268 ] 269 "rl78_real_insns_ok ()" 270 "@ 271 sar\t%0, %u2 272 cmp0 %2\; bz $2f\; 1: sar\t%0, 1 \;dec %2 \;bnz $1b\;2: 273 inc %2\;dec %2\;bz $2f\;1: sar\t%0, 1\;dec %2 \;bnz $1b\;2:" 274 [(set_attr "update_Z" "*,clobber,clobber")] 275) 276 277(define_insn "*ashrhi3_real" 278 [(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A") 279 (ashiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0") 280 (match_operand:QI 2 "general_operand" "P,bc,dehl"))) 281 ] 282 "rl78_real_insns_ok ()" 283 "@ 284 sarw\t%0, %u2 285 cmp0 %2\; bz $2f\; 1: sarw\t%0, 1 \;dec %2 \;bnz $1b\;2: 286 inc %2\;dec %2\;bz $2f\;1: sarw\t%0, 1\;dec %2\;bnz $1b\;2:" 287 [(set_attr "update_Z" "*,clobber,clobber")] 288) 289 290;;---------- 291 292(define_insn "*lshrqi3_real" 293 [(set (match_operand:QI 0 "nonimmediate_operand" "=abc,a,a") 294 (lshiftrt:QI (match_operand:QI 1 "general_operand" "0,0,0") 295 (match_operand:QI 2 "general_operand" "Int3,bc,dehl"))) 296 ] 297 "rl78_real_insns_ok ()" 298 "@ 299 shr\t%0, %u2 300 cmp0 %2\; bz $2f\; 1: shr\t%0, 1 \;dec %2 \;bnz $1b\;2: 301 inc %2\;dec %2\;bz $2f\;1: shr\t%0, 1\;dec %2\;bnz $1b\;2:" 302 [(set_attr "update_Z" "*,clobber,clobber")] 303) 304 305(define_insn "*lshrhi3_real" 306 [(set (match_operand:HI 0 "nonimmediate_operand" "=AB,A,A") 307 (lshiftrt:HI (match_operand:HI 1 "general_operand" "0,0,0") 308 (match_operand:QI 2 "general_operand" "P,bc,dehl"))) 309 ] 310 "rl78_real_insns_ok ()" 311 "@ 312 shrw\t%0, %u2 313 cmp0 %2\; bz $2f\; 1: shrw\t%0, 1 \;dec %2 \;bnz $1b\;2: 314 inc %2\;dec %2\;bz $2f\;1: shrw\t%0, 1\;dec %2\;bnz $1b\;2:" 315 [(set_attr "update_Z" "*,clobber,clobber")] 316) 317 318;;---------- Branching ------------------------ 319 320(define_insn "*indirect_jump_real" 321 [(set (pc) 322 (match_operand:HI 0 "nonimmediate_operand" "A"))] 323 "rl78_real_insns_ok ()" 324 "br\t%0" 325) 326 327(define_insn "jump" 328 [(set (pc) 329 (label_ref (match_operand 0 "" "")))] 330 "" 331 ;; $rel8, $!rel16, !abs16, !!abs20 332 "br\t!!%0" 333) 334 335(define_insn "*call_real" 336 [(call (match_operand:HI 0 "memory_operand" "Wab,Wca") 337 (match_operand 1 "" ""))] 338 "rl78_real_insns_ok ()" 339 "@ 340 call\t!!%A0 341 call\t%A0" 342 [(set (attr "update_Z") (const_string "clobber"))] 343 ) 344 345(define_insn "*call_value_real" 346 [(set (match_operand 0 "register_operand" "=v,v") 347 (call (match_operand:HI 1 "memory_operand" "Wab,Wca") 348 (match_operand 2 "" "")))] 349 "rl78_real_insns_ok ()" 350 "@ 351 call\t!!%A1 352 call\t%A1" 353 [(set (attr "update_Z") (const_string "clobber"))] 354 ) 355 356(define_insn "*cbranchqi4_real_signed" 357 [(set (pc) (if_then_else 358 (match_operator 0 "rl78_cmp_operator_signed" 359 [(match_operand:QI 1 "general_operand" "A,A,A,A,Wsa") 360 (match_operand:QI 2 "general_operand" "M,ISqi,i,v,i")]) 361 (label_ref (match_operand 3 "" "")) 362 (pc)))] 363 "rl78_real_insns_ok ()" 364 { 365 gcc_assert (GET_CODE (operands[0]) != EQ && GET_CODE (operands[0]) != NE); 366 367 switch (which_alternative) 368 { 369 case 0: return "cmp0\t%1\; xor1\tCY, %1.7\; sk%C0\; br\t!!%3"; 370 case 1: return "cmp\t%1, %2\; xor1\tCY, %1.7\; not1\tCY\; sk%C0\; br\t!!%3"; 371 case 4: 372 case 2: return "cmp\t%1, %2\; xor1\tCY, %1.7\; sk%C0\; br\t!!%3"; 373 case 3: return "cmp\t%1, %2\; xor1\tCY, %1.7\; xor1\tCY, %2.7\; sk%C0\; br\t!!%3"; 374 default: gcc_unreachable (); 375 } 376 } 377 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: flags are set based on %1 vs %2 378 ) 379 380(define_insn "*cbranchqi4_real" 381 [(set (pc) (if_then_else 382 (match_operator 0 "rl78_cmp_operator_real" 383 [(match_operand:QI 1 "rl78_general_operand" "Wabvaxbc,a, vWsaWab,bcdehl") 384 (match_operand:QI 2 "rl78_general_operand" "M, iRvWabWhlWh1Whb,i,a")]) 385 (label_ref (match_operand 3 "" "")) 386 (pc)))] 387 "rl78_real_insns_ok ()" 388 { 389 if (which_alternative == 0) 390 { 391 if (rl78_flags_already_set (operands[0], operands[1])) 392 return "sk%C0\; br\t!!%3\; # zero-comparison eliminated"; 393 else 394 return "cmp0\t%1\; sk%C0\; br\t!!%3"; 395 } 396 return "cmp\t%1, %2\; sk%C0\; br\t!!%3"; 397 } 398 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: alt 0: flags are set based on %1 vs %2 399 ) 400 401(define_insn "*cbranchhi4_real_signed" 402 [(set (pc) (if_then_else 403 (match_operator 0 "rl78_cmp_operator_signed" 404 [(match_operand:HI 1 "general_operand" "A,A,A,vR") 405 (match_operand:HI 2 "general_operand" "IShi,i,v,1")]) 406 (label_ref (match_operand 3)) 407 (pc)))] 408 "rl78_real_insns_ok ()" 409 "@ 410 cmpw\t%1, %2\; xor1\tCY, %Q1.7\; not1\tCY\; sk%C0\; br\t!!%3 411 cmpw\t%1, %2\; xor1\tCY, %Q1.7\; sk%C0\; br\t!!%3 412 cmpw\t%1, %2\; xor1\tCY, %Q1.7\; xor1\tCY, %Q2.7\; sk%C0\; br\t!!%3 413 %z0\t!!%3" 414 [(set_attr "update_Z" "clobber,clobber,clobber,*")] 415 ) 416 417(define_insn "cbranchhi4_real" 418 [(set (pc) (if_then_else 419 (match_operator 0 "rl78_cmp_operator_real" 420 [(match_operand:HI 1 "general_operand" "A,A,vR") 421 (match_operand:HI 2 "rl78_general_operand" "M,iBDTvWabWhlWh1,1")]) 422 (label_ref (match_operand 3 "" "")) 423 (pc)))] 424 "rl78_real_insns_ok ()" 425 { 426 switch (which_alternative) 427 { 428 case 0: 429 if (rl78_flags_already_set (operands[0], operands[1])) 430 return "sk%C0\; br\t!!%3\; # cmpw eliminated"; 431 /* else fall through. */ 432 case 1: 433 return "cmpw\t%1, %2\; sk%C0\; br\t!!%3"; 434 case 2: 435 return "%z0\t!!%3"; 436 default: 437 gcc_unreachable (); 438 } 439 } 440 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: Z might be set based on %1 vs %2 441 ) 442 443(define_insn "cbranchhi4_real_inverted" 444 [(set (pc) (if_then_else 445 (match_operator 0 "rl78_cmp_operator_real" 446 [(match_operand:HI 1 "general_operand" "A,A") 447 (match_operand:HI 2 "rl78_general_operand" "M,iBDTvWabWhlWh1")]) 448 (pc) 449 (label_ref (match_operand 3 "" ""))))] 450 "rl78_real_insns_ok ()" 451 { 452 if (which_alternative == 0 && rl78_flags_already_set (operands[0], operands[1])) 453 return "sk%C0\; br\t!!%3\; # inverted cmpw eliminated"; 454 else 455 return "cmpw\t%1, %2\; sk%C0\; br\t!!%3"; 456 } 457 [(set (attr "update_Z") (const_string "clobber"))] ;; FIXME: flags are set based on %1 vs %2 458 ) 459 460(define_insn "*cbranchsi4_real_lt" 461 [(set (pc) (if_then_else 462 (lt (match_operand:SI 0 "rl78_general_operand" "U,vWabWhlWh1") 463 (const_int 0)) 464 (label_ref (match_operand 1 "" "")) 465 (pc))) 466 (clobber (reg:HI AX_REG)) 467 ] 468 "rl78_real_insns_ok ()" 469 "@ 470 mov\ta, %E0\; mov1\tCY, a.7\; sknc\; br\t!!%1 471 mov1\tCY, %E0.7\; sknc\; br\t!!%1" 472 ) 473 474(define_insn "*cbranchsi4_real_ge" 475 [(set (pc) (if_then_else 476 (ge (match_operand:SI 0 "rl78_general_operand" "U,vWabWhlWh1") 477 (const_int 0)) 478 (label_ref (match_operand 1 "" "")) 479 (pc))) 480 (clobber (reg:HI AX_REG)) 481 ] 482 "rl78_real_insns_ok ()" 483 "@ 484 mov\ta, %E0\; mov1\tCY, a.7\; skc\; br\t!!%1 485 mov1\tCY, %E0.7\; skc\; br\t!!%1" 486 ) 487 488(define_insn "*cbranchsi4_real_signed" 489 [(set (pc) (if_then_else 490 (match_operator 0 "rl78_cmp_operator_signed" 491 [(match_operand:SI 1 "general_operand" "vU,vU,vU,i,i") 492 (match_operand:SI 2 "nonmemory_operand" "ISsi,i,v,S,v")]) 493 (label_ref (match_operand 3 "" "")) 494 (pc))) 495 (clobber (reg:HI AX_REG)) 496 ] 497 "rl78_real_insns_ok ()" 498 "@ 499 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; not1\tCY\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3 500 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3 501 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; xor1\tCY, %E2.7\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3 502 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; not1\tCY\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%0\; br\t!!%3 503 movw\tax, %H1\; cmpw\tax, %H2\; xor1\tCY, a.7\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%0\; br\t!!%3" 504 [(set (attr "update_Z") (const_string "clobber"))] 505 ) 506 507(define_insn "*cbranchsi4_real" 508 [(set (pc) (if_then_else 509 (match_operator 0 "rl78_cmp_operator_real" 510 [(match_operand:SI 1 "general_operand" "vUi") 511 (match_operand:SI 2 "general_operand" "iWhlWh1v")]) 512 (label_ref (match_operand 3 "" "")) 513 (pc))) 514 (clobber (reg:HI AX_REG)) 515 ] 516 "rl78_real_insns_ok ()" 517 "movw\tax, %H1\; cmpw\tax, %H2\; movw\tax, %h1\; sknz\; cmpw\tax, %h2\; sk%C0\; br\t!!%3" 518 [(set (attr "update_Z") (const_string "clobber"))] 519 ) 520 521;; Peephole to match: 522;; 523;; (set (mem (sp)) (ax)) 524;; (set (ax) (mem (sp))) 525;; or: 526;; (set (mem (plus (sp) (const)) (ax)) 527;; (set (ax) (mem (plus (sp) (const)))) 528;; 529;; which can be generated as the last instruction of the conversion 530;; of one virtual insn into a real insn and the first instruction of 531;; the conversion of the following virtual insn. 532 533(define_peephole2 534 [(set (match_operand:HI 0 "rl78_stack_based_mem") 535 (reg:HI AX_REG)) 536 (set (reg:HI AX_REG) 537 (match_dup 0))] 538 "" 539 [(set (match_dup 0) (reg:HI AX_REG))] 540 ) 541 542;; Bit test and branch insns. 543 544;; NOTE: These patterns will work for bits in other places, not just A. 545 546(define_insn "bf" 547 [(set (pc) 548 (if_then_else (eq (and (reg:QI A_REG) 549 (match_operand 0 "immediate_operand" "n")) 550 (const_int 0)) 551 (label_ref (match_operand 1 "" "")) 552 (pc)))] 553 "" 554 "bf\tA.%B0, $%1" 555 [(set (attr "update_Z") (const_string "clobber"))] 556) 557 558(define_insn "bt" 559 [(set (pc) 560 (if_then_else (ne (and (reg:QI A_REG) 561 (match_operand 0 "immediate_operand" "n")) 562 (const_int 0)) 563 (label_ref (match_operand 1 "" "")) 564 (pc)))] 565 "" 566 "bt\tA.%B0, $%1" 567 [(set (attr "update_Z") (const_string "clobber"))] 568) 569 570;; NOTE: These peepholes are fragile. They rely upon GCC generating 571;; a specific sequence on insns, based upon examination of test code. 572;; Improvements to GCC or using code other than the test code can result 573;; in the peephole not matching and the optimization being missed. 574 575(define_peephole2 576 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 577 (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 578 (set (pc) (if_then_else (eq (match_dup 0) (const_int 0)) 579 (label_ref (match_operand 2 "")) 580 (pc)))] 581 "peep2_regno_dead_p (3, REGNO (operands[0])) 582 && exact_log2 (INTVAL (operands[1])) >= 0" 583 [(set (pc) (if_then_else (eq (and (reg:QI A_REG) (match_dup 1)) (const_int 0)) 584 (label_ref (match_dup 2)) 585 (pc)))] 586 ) 587 588(define_peephole2 589 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 590 (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 591 (set (pc) (if_then_else (ne (match_dup 0) (const_int 0)) 592 (label_ref (match_operand 2 "")) 593 (pc)))] 594 "peep2_regno_dead_p (3, REGNO (operands[0])) 595 && exact_log2 (INTVAL (operands[1])) >= 0" 596 [(set (pc) (if_then_else (ne (and (reg:QI A_REG) (match_dup 1)) (const_int 0)) 597 (label_ref (match_dup 2)) 598 (pc)))] 599 ) 600 601;; Eliminate needless register copies. 602(define_peephole2 603 [(set (match_operand:HI 0 "register_operand") (match_operand:HI 1 "register_operand")) 604 (set (match_operand:HI 2 "register_operand") (match_dup 0))] 605 "peep2_regno_dead_p (2, REGNO (operands[0])) 606 && (REGNO (operands[1]) < 8 || REGNO (operands[2]) < 8)" 607 [(set (match_dup 2) (match_dup 1))] 608 ) 609 610;; Eliminate needless register copying when performing bit manipulations. 611(define_peephole2 612 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 613 (set (match_dup 0) (ior:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 614 (set (reg:QI A_REG) (match_dup 0))] 615 "peep2_regno_dead_p (3, REGNO (operands[0]))" 616 [(set (reg:QI A_REG) (ior:QI (reg:QI A_REG) (match_dup 1)))] 617 ) 618 619(define_peephole2 620 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 621 (set (match_dup 0) (xor:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 622 (set (reg:QI A_REG) (match_dup 0))] 623 "peep2_regno_dead_p (3, REGNO (operands[0]))" 624 [(set (reg:QI A_REG) (xor:QI (reg:QI A_REG) (match_dup 1)))] 625 ) 626 627(define_peephole2 628 [(set (match_operand:QI 0 "register_operand") (reg:QI A_REG)) 629 (set (match_dup 0) (and:QI (match_dup 0) (match_operand 1 "immediate_operand"))) 630 (set (reg:QI A_REG) (match_dup 0))] 631 "peep2_regno_dead_p (3, REGNO (operands[0]))" 632 [(set (reg:QI A_REG) (and:QI (reg:QI A_REG) (match_dup 1)))] 633 ) 634 635(define_insn "*negandhi3_real" 636 [(set (match_operand:HI 0 "register_operand" "=A") 637 (and:HI (neg:HI (match_operand:HI 1 "register_operand" "0")) 638 (match_operand:HI 2 "immediate_operand" "n"))) 639 ] 640 "rl78_real_insns_ok ()" 641 "xor a, #0xff @ xch a, x @ xor a, #0xff @ xch a, x @ addw ax, #1 @ and a, %Q2 @ xch a, x @ and a, %q2 @ xch a, x" 642 [(set (attr "update_Z") (const_string "clobber"))] 643) 644