1(define_automaton "sifive_7") 2 3;; Sifive 7 Series Base Core 4;; This has two pipelines, A (Address) and B (Branch). 5;; Loads, stores, and FP <-> integer moves use the A-pipe. 6;; Branches, MUL/DIV, and FP ops use the B-pipe. 7;; Integer ALU ops can use either pipe. 8 9(define_cpu_unit "sifive_7_A" "sifive_7") 10(define_cpu_unit "sifive_7_B" "sifive_7") 11 12(define_cpu_unit "sifive_7_idiv" "sifive_7") 13(define_cpu_unit "sifive_7_fpu" "sifive_7") 14 15(define_insn_reservation "sifive_7_load" 3 16 (and (eq_attr "tune" "sifive_7") 17 (eq_attr "type" "load")) 18 "sifive_7_A") 19 20(define_insn_reservation "sifive_7_fpload" 2 21 (and (eq_attr "tune" "sifive_7") 22 (eq_attr "type" "fpload")) 23 "sifive_7_A") 24 25(define_insn_reservation "sifive_7_store" 1 26 (and (eq_attr "tune" "sifive_7") 27 (eq_attr "type" "store")) 28 "sifive_7_A") 29 30(define_insn_reservation "sifive_7_fpstore" 1 31 (and (eq_attr "tune" "sifive_7") 32 (eq_attr "type" "fpstore")) 33 "sifive_7_A") 34 35(define_insn_reservation "sifive_7_branch" 1 36 (and (eq_attr "tune" "sifive_7") 37 (eq_attr "type" "branch")) 38 "sifive_7_B") 39 40(define_insn_reservation "sifive_7_jump" 1 41 (and (eq_attr "tune" "sifive_7") 42 (eq_attr "type" "jump,call")) 43 "sifive_7_B") 44 45(define_insn_reservation "sifive_7_mul" 3 46 (and (eq_attr "tune" "sifive_7") 47 (eq_attr "type" "imul")) 48 "sifive_7_B") 49 50(define_insn_reservation "sifive_7_div" 16 51 (and (eq_attr "tune" "sifive_7") 52 (eq_attr "type" "idiv")) 53 "sifive_7_B,sifive_7_idiv*15") 54 55(define_insn_reservation "sifive_7_alu" 2 56 (and (eq_attr "tune" "sifive_7") 57 (eq_attr "type" "unknown,arith,shift,slt,multi,logical,move")) 58 "sifive_7_A|sifive_7_B") 59 60(define_insn_reservation "sifive_7_load_immediate" 1 61 (and (eq_attr "tune" "sifive_7") 62 (eq_attr "type" "nop,const,auipc")) 63 "sifive_7_A|sifive_7_B") 64 65(define_insn_reservation "sifive_7_sfma" 5 66 (and (eq_attr "tune" "sifive_7") 67 (and (eq_attr "type" "fadd,fmul,fmadd") 68 (eq_attr "mode" "SF"))) 69 "sifive_7_B") 70 71(define_insn_reservation "sifive_7_dfma" 7 72 (and (eq_attr "tune" "sifive_7") 73 (and (eq_attr "type" "fadd,fmul,fmadd") 74 (eq_attr "mode" "DF"))) 75 "sifive_7_B") 76 77(define_insn_reservation "sifive_7_fp_other" 3 78 (and (eq_attr "tune" "sifive_7") 79 (eq_attr "type" "fcvt,fcmp,fmove")) 80 "sifive_7_B") 81 82(define_insn_reservation "sifive_7_fdiv_s" 27 83 (and (eq_attr "tune" "sifive_7") 84 (eq_attr "type" "fdiv,fsqrt") 85 (eq_attr "mode" "SF")) 86 "sifive_7_B,sifive_7_fpu*26") 87 88(define_insn_reservation "sifive_7_fdiv_d" 56 89 (and (eq_attr "tune" "sifive_7") 90 (eq_attr "type" "fdiv,fsqrt") 91 (eq_attr "mode" "DF")) 92 "sifive_7_B,sifive_7_fpu*55") 93 94(define_insn_reservation "sifive_7_i2f" 3 95 (and (eq_attr "tune" "sifive_7") 96 (eq_attr "type" "mtc")) 97 "sifive_7_A") 98 99(define_insn_reservation "sifive_7_f2i" 3 100 (and (eq_attr "tune" "sifive_7") 101 (eq_attr "type" "mfc")) 102 "sifive_7_A") 103 104(define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i" 105 "sifive_7_alu,sifive_7_branch") 106 107(define_bypass 1 "sifive_7_load,sifive_7_alu,sifive_7_mul,sifive_7_f2i" 108 "sifive_7_store" "riscv_store_data_bypass_p") 109 110(define_bypass 2 "sifive_7_i2f" 111 "sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_s,sifive_7_fdiv_d") 112 113(define_bypass 2 "sifive_7_fp_other" 114 "sifive_7_sfma,sifive_7_dfma,sifive_7_fp_other,sifive_7_fdiv_s,sifive_7_fdiv_d") 115 116(define_bypass 2 "sifive_7_fp_other" 117 "sifive_7_alu,sifive_7_branch") 118 119(define_bypass 2 "sifive_7_fp_other" 120 "sifive_7_store" "riscv_store_data_bypass_p") 121