1 /* Subroutines used for code generation for RISC-V. 2 Copyright (C) 2011-2019 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman (andrew@sifive.com). 4 Based on MIPS target for GNU compiler. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #define IN_TARGET_CODE 1 23 24 #define INCLUDE_STRING 25 #include "config.h" 26 #include "system.h" 27 #include "coretypes.h" 28 #include "tm.h" 29 #include "rtl.h" 30 #include "regs.h" 31 #include "insn-config.h" 32 #include "insn-attr.h" 33 #include "recog.h" 34 #include "output.h" 35 #include "alias.h" 36 #include "tree.h" 37 #include "stringpool.h" 38 #include "attribs.h" 39 #include "varasm.h" 40 #include "stor-layout.h" 41 #include "calls.h" 42 #include "function.h" 43 #include "explow.h" 44 #include "memmodel.h" 45 #include "emit-rtl.h" 46 #include "reload.h" 47 #include "tm_p.h" 48 #include "target.h" 49 #include "target-def.h" 50 #include "basic-block.h" 51 #include "expr.h" 52 #include "optabs.h" 53 #include "bitmap.h" 54 #include "df.h" 55 #include "diagnostic.h" 56 #include "builtins.h" 57 #include "predict.h" 58 59 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ 60 #define UNSPEC_ADDRESS_P(X) \ 61 (GET_CODE (X) == UNSPEC \ 62 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ 63 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) 64 65 /* Extract the symbol or label from UNSPEC wrapper X. */ 66 #define UNSPEC_ADDRESS(X) \ 67 XVECEXP (X, 0, 0) 68 69 /* Extract the symbol type from UNSPEC wrapper X. */ 70 #define UNSPEC_ADDRESS_TYPE(X) \ 71 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) 72 73 /* True if bit BIT is set in VALUE. */ 74 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0) 75 76 /* Classifies an address. 77 78 ADDRESS_REG 79 A natural register + offset address. The register satisfies 80 riscv_valid_base_register_p and the offset is a const_arith_operand. 81 82 ADDRESS_LO_SUM 83 A LO_SUM rtx. The first operand is a valid base register and 84 the second operand is a symbolic address. 85 86 ADDRESS_CONST_INT 87 A signed 16-bit constant address. 88 89 ADDRESS_SYMBOLIC: 90 A constant symbolic address. */ 91 enum riscv_address_type { 92 ADDRESS_REG, 93 ADDRESS_LO_SUM, 94 ADDRESS_CONST_INT, 95 ADDRESS_SYMBOLIC 96 }; 97 98 /* Information about a function's frame layout. */ 99 struct GTY(()) riscv_frame_info { 100 /* The size of the frame in bytes. */ 101 HOST_WIDE_INT total_size; 102 103 /* Bit X is set if the function saves or restores GPR X. */ 104 unsigned int mask; 105 106 /* Likewise FPR X. */ 107 unsigned int fmask; 108 109 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */ 110 unsigned save_libcall_adjustment; 111 112 /* Offsets of fixed-point and floating-point save areas from frame bottom */ 113 HOST_WIDE_INT gp_sp_offset; 114 HOST_WIDE_INT fp_sp_offset; 115 116 /* Offset of virtual frame pointer from stack pointer/frame bottom */ 117 HOST_WIDE_INT frame_pointer_offset; 118 119 /* Offset of hard frame pointer from stack pointer/frame bottom */ 120 HOST_WIDE_INT hard_frame_pointer_offset; 121 122 /* The offset of arg_pointer_rtx from the bottom of the frame. */ 123 HOST_WIDE_INT arg_pointer_offset; 124 }; 125 126 enum riscv_privilege_levels { 127 UNKNOWN_MODE, USER_MODE, SUPERVISOR_MODE, MACHINE_MODE 128 }; 129 130 struct GTY(()) machine_function { 131 /* The number of extra stack bytes taken up by register varargs. 132 This area is allocated by the callee at the very top of the frame. */ 133 int varargs_size; 134 135 /* True if current function is a naked function. */ 136 bool naked_p; 137 138 /* True if current function is an interrupt function. */ 139 bool interrupt_handler_p; 140 /* For an interrupt handler, indicates the privilege level. */ 141 enum riscv_privilege_levels interrupt_mode; 142 143 /* True if attributes on current function have been checked. */ 144 bool attributes_checked_p; 145 146 /* The current frame information, calculated by riscv_compute_frame_info. */ 147 struct riscv_frame_info frame; 148 }; 149 150 /* Information about a single argument. */ 151 struct riscv_arg_info { 152 /* True if the argument is at least partially passed on the stack. */ 153 bool stack_p; 154 155 /* The number of integer registers allocated to this argument. */ 156 unsigned int num_gprs; 157 158 /* The offset of the first register used, provided num_gprs is nonzero. 159 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */ 160 unsigned int gpr_offset; 161 162 /* The number of floating-point registers allocated to this argument. */ 163 unsigned int num_fprs; 164 165 /* The offset of the first register used, provided num_fprs is nonzero. */ 166 unsigned int fpr_offset; 167 }; 168 169 /* Information about an address described by riscv_address_type. 170 171 ADDRESS_CONST_INT 172 No fields are used. 173 174 ADDRESS_REG 175 REG is the base register and OFFSET is the constant offset. 176 177 ADDRESS_LO_SUM 178 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE 179 is the type of symbol it references. 180 181 ADDRESS_SYMBOLIC 182 SYMBOL_TYPE is the type of symbol that the address references. */ 183 struct riscv_address_info { 184 enum riscv_address_type type; 185 rtx reg; 186 rtx offset; 187 enum riscv_symbol_type symbol_type; 188 }; 189 190 /* One stage in a constant building sequence. These sequences have 191 the form: 192 193 A = VALUE[0] 194 A = A CODE[1] VALUE[1] 195 A = A CODE[2] VALUE[2] 196 ... 197 198 where A is an accumulator, each CODE[i] is a binary rtl operation 199 and each VALUE[i] is a constant integer. CODE[0] is undefined. */ 200 struct riscv_integer_op { 201 enum rtx_code code; 202 unsigned HOST_WIDE_INT value; 203 }; 204 205 /* The largest number of operations needed to load an integer constant. 206 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */ 207 #define RISCV_MAX_INTEGER_OPS 8 208 209 /* Costs of various operations on the different architectures. */ 210 211 struct riscv_tune_info 212 { 213 unsigned short fp_add[2]; 214 unsigned short fp_mul[2]; 215 unsigned short fp_div[2]; 216 unsigned short int_mul[2]; 217 unsigned short int_div[2]; 218 unsigned short issue_rate; 219 unsigned short branch_cost; 220 unsigned short memory_cost; 221 bool slow_unaligned_access; 222 }; 223 224 /* Information about one CPU we know about. */ 225 struct riscv_cpu_info { 226 /* This CPU's canonical name. */ 227 const char *name; 228 229 /* Which automaton to use for tuning. */ 230 enum riscv_microarchitecture_type microarchitecture; 231 232 /* Tuning parameters for this CPU. */ 233 const struct riscv_tune_info *tune_info; 234 }; 235 236 /* Global variables for machine-dependent things. */ 237 238 /* Whether unaligned accesses execute very slowly. */ 239 bool riscv_slow_unaligned_access_p; 240 241 /* Stack alignment to assume/maintain. */ 242 unsigned riscv_stack_boundary; 243 244 /* If non-zero, this is an offset to be added to SP to redefine the CFA 245 when restoring the FP register from the stack. Only valid when generating 246 the epilogue. */ 247 static int epilogue_cfa_sp_offset; 248 249 /* Which tuning parameters to use. */ 250 static const struct riscv_tune_info *tune_info; 251 252 /* Which automaton to use for tuning. */ 253 enum riscv_microarchitecture_type riscv_microarchitecture; 254 255 /* Index R is the smallest register class that contains register R. */ 256 const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { 257 GR_REGS, GR_REGS, GR_REGS, GR_REGS, 258 GR_REGS, GR_REGS, SIBCALL_REGS, SIBCALL_REGS, 259 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, 260 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, 261 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, 262 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, 263 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, 264 SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, 265 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 266 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 267 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 268 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 269 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 270 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 271 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 272 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 273 FRAME_REGS, FRAME_REGS, 274 }; 275 276 /* Costs to use when optimizing for rocket. */ 277 static const struct riscv_tune_info rocket_tune_info = { 278 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ 279 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ 280 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ 281 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ 282 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ 283 1, /* issue_rate */ 284 3, /* branch_cost */ 285 5, /* memory_cost */ 286 true, /* slow_unaligned_access */ 287 }; 288 289 /* Costs to use when optimizing for Sifive 7 Series. */ 290 static const struct riscv_tune_info sifive_7_tune_info = { 291 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ 292 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ 293 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ 294 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ 295 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ 296 2, /* issue_rate */ 297 4, /* branch_cost */ 298 3, /* memory_cost */ 299 true, /* slow_unaligned_access */ 300 }; 301 302 /* Costs to use when optimizing for size. */ 303 static const struct riscv_tune_info optimize_size_tune_info = { 304 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */ 305 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */ 306 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */ 307 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */ 308 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */ 309 1, /* issue_rate */ 310 1, /* branch_cost */ 311 2, /* memory_cost */ 312 false, /* slow_unaligned_access */ 313 }; 314 315 static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); 316 static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); 317 318 /* Defining target-specific uses of __attribute__. */ 319 static const struct attribute_spec riscv_attribute_table[] = 320 { 321 /* Syntax: { name, min_len, max_len, decl_required, type_required, 322 function_type_required, affects_type_identity, handler, 323 exclude } */ 324 325 /* The attribute telling no prologue/epilogue. */ 326 { "naked", 0, 0, true, false, false, false, 327 riscv_handle_fndecl_attribute, NULL }, 328 /* This attribute generates prologue/epilogue for interrupt handlers. */ 329 { "interrupt", 0, 1, false, true, true, false, 330 riscv_handle_type_attribute, NULL }, 331 332 /* The last attribute spec is set to be NULL. */ 333 { NULL, 0, 0, false, false, false, false, NULL, NULL } 334 }; 335 336 /* A table describing all the processors GCC knows about. */ 337 static const struct riscv_cpu_info riscv_cpu_info_table[] = { 338 { "rocket", generic, &rocket_tune_info }, 339 { "sifive-3-series", generic, &rocket_tune_info }, 340 { "sifive-5-series", generic, &rocket_tune_info }, 341 { "sifive-7-series", sifive_7, &sifive_7_tune_info }, 342 { "size", generic, &optimize_size_tune_info }, 343 }; 344 345 /* Return the riscv_cpu_info entry for the given name string. */ 346 347 static const struct riscv_cpu_info * 348 riscv_parse_cpu (const char *cpu_string) 349 { 350 for (unsigned i = 0; i < ARRAY_SIZE (riscv_cpu_info_table); i++) 351 if (strcmp (riscv_cpu_info_table[i].name, cpu_string) == 0) 352 return riscv_cpu_info_table + i; 353 354 error ("unknown cpu %qs for %<-mtune%>", cpu_string); 355 return riscv_cpu_info_table; 356 } 357 358 /* Helper function for riscv_build_integer; arguments are as for 359 riscv_build_integer. */ 360 361 static int 362 riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], 363 HOST_WIDE_INT value, machine_mode mode) 364 { 365 HOST_WIDE_INT low_part = CONST_LOW_PART (value); 366 int cost = RISCV_MAX_INTEGER_OPS + 1, alt_cost; 367 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; 368 369 if (SMALL_OPERAND (value) || LUI_OPERAND (value)) 370 { 371 /* Simply ADDI or LUI. */ 372 codes[0].code = UNKNOWN; 373 codes[0].value = value; 374 return 1; 375 } 376 377 /* End with ADDI. When constructing HImode constants, do not generate any 378 intermediate value that is not itself a valid HImode constant. The 379 XORI case below will handle those remaining HImode constants. */ 380 if (low_part != 0 381 && (mode != HImode 382 || value - low_part <= ((1 << (GET_MODE_BITSIZE (HImode) - 1)) - 1))) 383 { 384 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value - low_part, mode); 385 if (alt_cost < cost) 386 { 387 alt_codes[alt_cost-1].code = PLUS; 388 alt_codes[alt_cost-1].value = low_part; 389 memcpy (codes, alt_codes, sizeof (alt_codes)); 390 cost = alt_cost; 391 } 392 } 393 394 /* End with XORI. */ 395 if (cost > 2 && (low_part < 0 || mode == HImode)) 396 { 397 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value ^ low_part, mode); 398 if (alt_cost < cost) 399 { 400 alt_codes[alt_cost-1].code = XOR; 401 alt_codes[alt_cost-1].value = low_part; 402 memcpy (codes, alt_codes, sizeof (alt_codes)); 403 cost = alt_cost; 404 } 405 } 406 407 /* Eliminate trailing zeros and end with SLLI. */ 408 if (cost > 2 && (value & 1) == 0) 409 { 410 int shift = ctz_hwi (value); 411 unsigned HOST_WIDE_INT x = value; 412 x = sext_hwi (x >> shift, HOST_BITS_PER_WIDE_INT - shift); 413 414 /* Don't eliminate the lower 12 bits if LUI might apply. */ 415 if (shift > IMM_BITS && !SMALL_OPERAND (x) && LUI_OPERAND (x << IMM_BITS)) 416 shift -= IMM_BITS, x <<= IMM_BITS; 417 418 alt_cost = 1 + riscv_build_integer_1 (alt_codes, x, mode); 419 if (alt_cost < cost) 420 { 421 alt_codes[alt_cost-1].code = ASHIFT; 422 alt_codes[alt_cost-1].value = shift; 423 memcpy (codes, alt_codes, sizeof (alt_codes)); 424 cost = alt_cost; 425 } 426 } 427 428 gcc_assert (cost <= RISCV_MAX_INTEGER_OPS); 429 return cost; 430 } 431 432 /* Fill CODES with a sequence of rtl operations to load VALUE. 433 Return the number of operations needed. */ 434 435 static int 436 riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value, 437 machine_mode mode) 438 { 439 int cost = riscv_build_integer_1 (codes, value, mode); 440 441 /* Eliminate leading zeros and end with SRLI. */ 442 if (value > 0 && cost > 2) 443 { 444 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; 445 int alt_cost, shift = clz_hwi (value); 446 HOST_WIDE_INT shifted_val; 447 448 /* Try filling trailing bits with 1s. */ 449 shifted_val = (value << shift) | ((((HOST_WIDE_INT) 1) << shift) - 1); 450 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode); 451 if (alt_cost < cost) 452 { 453 alt_codes[alt_cost-1].code = LSHIFTRT; 454 alt_codes[alt_cost-1].value = shift; 455 memcpy (codes, alt_codes, sizeof (alt_codes)); 456 cost = alt_cost; 457 } 458 459 /* Try filling trailing bits with 0s. */ 460 shifted_val = value << shift; 461 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode); 462 if (alt_cost < cost) 463 { 464 alt_codes[alt_cost-1].code = LSHIFTRT; 465 alt_codes[alt_cost-1].value = shift; 466 memcpy (codes, alt_codes, sizeof (alt_codes)); 467 cost = alt_cost; 468 } 469 } 470 471 return cost; 472 } 473 474 /* Return the cost of constructing VAL in the event that a scratch 475 register is available. */ 476 477 static int 478 riscv_split_integer_cost (HOST_WIDE_INT val) 479 { 480 int cost; 481 unsigned HOST_WIDE_INT loval = sext_hwi (val, 32); 482 unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); 483 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 484 485 cost = 2 + riscv_build_integer (codes, loval, VOIDmode); 486 if (loval != hival) 487 cost += riscv_build_integer (codes, hival, VOIDmode); 488 489 return cost; 490 } 491 492 /* Return the cost of constructing the integer constant VAL. */ 493 494 static int 495 riscv_integer_cost (HOST_WIDE_INT val) 496 { 497 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 498 return MIN (riscv_build_integer (codes, val, VOIDmode), 499 riscv_split_integer_cost (val)); 500 } 501 502 /* Try to split a 64b integer into 32b parts, then reassemble. */ 503 504 static rtx 505 riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) 506 { 507 unsigned HOST_WIDE_INT loval = sext_hwi (val, 32); 508 unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); 509 rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); 510 511 riscv_move_integer (hi, hi, hival, FALSE); 512 riscv_move_integer (lo, lo, loval, FALSE); 513 514 hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); 515 hi = force_reg (mode, hi); 516 517 return gen_rtx_fmt_ee (PLUS, mode, hi, lo); 518 } 519 520 /* Return true if X is a thread-local symbol. */ 521 522 static bool 523 riscv_tls_symbol_p (const_rtx x) 524 { 525 return SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0; 526 } 527 528 /* Return true if symbol X binds locally. */ 529 530 static bool 531 riscv_symbol_binds_local_p (const_rtx x) 532 { 533 if (SYMBOL_REF_P (x)) 534 return (SYMBOL_REF_DECL (x) 535 ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) 536 : SYMBOL_REF_LOCAL_P (x)); 537 else 538 return false; 539 } 540 541 /* Return the method that should be used to access SYMBOL_REF or 542 LABEL_REF X. */ 543 544 static enum riscv_symbol_type 545 riscv_classify_symbol (const_rtx x) 546 { 547 if (riscv_tls_symbol_p (x)) 548 return SYMBOL_TLS; 549 550 if (GET_CODE (x) == SYMBOL_REF && flag_pic && !riscv_symbol_binds_local_p (x)) 551 return SYMBOL_GOT_DISP; 552 553 return riscv_cmodel == CM_MEDLOW ? SYMBOL_ABSOLUTE : SYMBOL_PCREL; 554 } 555 556 /* Classify the base of symbolic expression X. */ 557 558 enum riscv_symbol_type 559 riscv_classify_symbolic_expression (rtx x) 560 { 561 rtx offset; 562 563 split_const (x, &x, &offset); 564 if (UNSPEC_ADDRESS_P (x)) 565 return UNSPEC_ADDRESS_TYPE (x); 566 567 return riscv_classify_symbol (x); 568 } 569 570 /* Return true if X is a symbolic constant. If it is, store the type of 571 the symbol in *SYMBOL_TYPE. */ 572 573 bool 574 riscv_symbolic_constant_p (rtx x, enum riscv_symbol_type *symbol_type) 575 { 576 rtx offset; 577 578 split_const (x, &x, &offset); 579 if (UNSPEC_ADDRESS_P (x)) 580 { 581 *symbol_type = UNSPEC_ADDRESS_TYPE (x); 582 x = UNSPEC_ADDRESS (x); 583 } 584 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) 585 *symbol_type = riscv_classify_symbol (x); 586 else 587 return false; 588 589 if (offset == const0_rtx) 590 return true; 591 592 /* Nonzero offsets are only valid for references that don't use the GOT. */ 593 switch (*symbol_type) 594 { 595 case SYMBOL_ABSOLUTE: 596 case SYMBOL_PCREL: 597 case SYMBOL_TLS_LE: 598 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */ 599 return sext_hwi (INTVAL (offset), 32) == INTVAL (offset); 600 601 default: 602 return false; 603 } 604 } 605 606 /* Returns the number of instructions necessary to reference a symbol. */ 607 608 static int riscv_symbol_insns (enum riscv_symbol_type type) 609 { 610 switch (type) 611 { 612 case SYMBOL_TLS: return 0; /* Depends on the TLS model. */ 613 case SYMBOL_ABSOLUTE: return 2; /* LUI + the reference. */ 614 case SYMBOL_PCREL: return 2; /* AUIPC + the reference. */ 615 case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference. */ 616 case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference. */ 617 default: gcc_unreachable (); 618 } 619 } 620 621 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ 622 623 static bool 624 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 625 { 626 return riscv_const_insns (x) > 0; 627 } 628 629 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ 630 631 static bool 632 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 633 { 634 enum riscv_symbol_type type; 635 rtx base, offset; 636 637 /* There is no assembler syntax for expressing an address-sized 638 high part. */ 639 if (GET_CODE (x) == HIGH) 640 return true; 641 642 split_const (x, &base, &offset); 643 if (riscv_symbolic_constant_p (base, &type)) 644 { 645 /* As an optimization, don't spill symbolic constants that are as 646 cheap to rematerialize as to access in the constant pool. */ 647 if (SMALL_OPERAND (INTVAL (offset)) && riscv_symbol_insns (type) > 0) 648 return true; 649 650 /* As an optimization, avoid needlessly generate dynamic relocations. */ 651 if (flag_pic) 652 return true; 653 } 654 655 /* TLS symbols must be computed by riscv_legitimize_move. */ 656 if (tls_referenced_p (x)) 657 return true; 658 659 return false; 660 } 661 662 /* Return true if register REGNO is a valid base register for mode MODE. 663 STRICT_P is true if REG_OK_STRICT is in effect. */ 664 665 int 666 riscv_regno_mode_ok_for_base_p (int regno, 667 machine_mode mode ATTRIBUTE_UNUSED, 668 bool strict_p) 669 { 670 if (!HARD_REGISTER_NUM_P (regno)) 671 { 672 if (!strict_p) 673 return true; 674 regno = reg_renumber[regno]; 675 } 676 677 /* These fake registers will be eliminated to either the stack or 678 hard frame pointer, both of which are usually valid base registers. 679 Reload deals with the cases where the eliminated form isn't valid. */ 680 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) 681 return true; 682 683 return GP_REG_P (regno); 684 } 685 686 /* Return true if X is a valid base register for mode MODE. 687 STRICT_P is true if REG_OK_STRICT is in effect. */ 688 689 static bool 690 riscv_valid_base_register_p (rtx x, machine_mode mode, bool strict_p) 691 { 692 if (!strict_p && GET_CODE (x) == SUBREG) 693 x = SUBREG_REG (x); 694 695 return (REG_P (x) 696 && riscv_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); 697 } 698 699 /* Return true if, for every base register BASE_REG, (plus BASE_REG X) 700 can address a value of mode MODE. */ 701 702 static bool 703 riscv_valid_offset_p (rtx x, machine_mode mode) 704 { 705 /* Check that X is a signed 12-bit number. */ 706 if (!const_arith_operand (x, Pmode)) 707 return false; 708 709 /* We may need to split multiword moves, so make sure that every word 710 is accessible. */ 711 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 712 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) 713 return false; 714 715 return true; 716 } 717 718 /* Should a symbol of type SYMBOL_TYPE should be split in two? */ 719 720 bool 721 riscv_split_symbol_type (enum riscv_symbol_type symbol_type) 722 { 723 if (symbol_type == SYMBOL_TLS_LE) 724 return true; 725 726 if (!TARGET_EXPLICIT_RELOCS) 727 return false; 728 729 return symbol_type == SYMBOL_ABSOLUTE || symbol_type == SYMBOL_PCREL; 730 } 731 732 /* Return true if a LO_SUM can address a value of mode MODE when the 733 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which 734 is used when the mode is BLKmode. */ 735 736 static bool 737 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode, 738 rtx x) 739 { 740 int align, size; 741 742 /* Check that symbols of type SYMBOL_TYPE can be used to access values 743 of mode MODE. */ 744 if (riscv_symbol_insns (sym_type) == 0) 745 return false; 746 747 /* Check that there is a known low-part relocation. */ 748 if (!riscv_split_symbol_type (sym_type)) 749 return false; 750 751 /* We can't tell size or alignment when we have BLKmode, so try extracing a 752 decl from the symbol if possible. */ 753 if (mode == BLKmode) 754 { 755 rtx offset; 756 757 /* Extract the symbol from the LO_SUM operand, if any. */ 758 split_const (x, &x, &offset); 759 760 /* Might be a CODE_LABEL. We can compute align but not size for that, 761 so don't bother trying to handle it. */ 762 if (!SYMBOL_REF_P (x)) 763 return false; 764 765 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */ 766 align = (SYMBOL_REF_DECL (x) 767 ? DECL_ALIGN (SYMBOL_REF_DECL (x)) 768 : 1); 769 size = (SYMBOL_REF_DECL (x) && DECL_SIZE (SYMBOL_REF_DECL (x)) 770 ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x))) 771 : 2*BITS_PER_WORD); 772 } 773 else 774 { 775 align = GET_MODE_ALIGNMENT (mode); 776 size = GET_MODE_BITSIZE (mode); 777 } 778 779 /* We may need to split multiword moves, so make sure that each word 780 can be accessed without inducing a carry. */ 781 if (size > BITS_PER_WORD 782 && (!TARGET_STRICT_ALIGN || size > align)) 783 return false; 784 785 return true; 786 } 787 788 /* Return true if X is a valid address for machine mode MODE. If it is, 789 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in 790 effect. */ 791 792 static bool 793 riscv_classify_address (struct riscv_address_info *info, rtx x, 794 machine_mode mode, bool strict_p) 795 { 796 switch (GET_CODE (x)) 797 { 798 case REG: 799 case SUBREG: 800 info->type = ADDRESS_REG; 801 info->reg = x; 802 info->offset = const0_rtx; 803 return riscv_valid_base_register_p (info->reg, mode, strict_p); 804 805 case PLUS: 806 info->type = ADDRESS_REG; 807 info->reg = XEXP (x, 0); 808 info->offset = XEXP (x, 1); 809 return (riscv_valid_base_register_p (info->reg, mode, strict_p) 810 && riscv_valid_offset_p (info->offset, mode)); 811 812 case LO_SUM: 813 info->type = ADDRESS_LO_SUM; 814 info->reg = XEXP (x, 0); 815 info->offset = XEXP (x, 1); 816 /* We have to trust the creator of the LO_SUM to do something vaguely 817 sane. Target-independent code that creates a LO_SUM should also 818 create and verify the matching HIGH. Target-independent code that 819 adds an offset to a LO_SUM must prove that the offset will not 820 induce a carry. Failure to do either of these things would be 821 a bug, and we are not required to check for it here. The RISC-V 822 backend itself should only create LO_SUMs for valid symbolic 823 constants, with the high part being either a HIGH or a copy 824 of _gp. */ 825 info->symbol_type 826 = riscv_classify_symbolic_expression (info->offset); 827 return (riscv_valid_base_register_p (info->reg, mode, strict_p) 828 && riscv_valid_lo_sum_p (info->symbol_type, mode, info->offset)); 829 830 case CONST_INT: 831 /* Small-integer addresses don't occur very often, but they 832 are legitimate if x0 is a valid base register. */ 833 info->type = ADDRESS_CONST_INT; 834 return SMALL_OPERAND (INTVAL (x)); 835 836 default: 837 return false; 838 } 839 } 840 841 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ 842 843 static bool 844 riscv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) 845 { 846 struct riscv_address_info addr; 847 848 return riscv_classify_address (&addr, x, mode, strict_p); 849 } 850 851 /* Return the number of instructions needed to load or store a value 852 of mode MODE at address X. Return 0 if X isn't valid for MODE. 853 Assume that multiword moves may need to be split into word moves 854 if MIGHT_SPLIT_P, otherwise assume that a single load or store is 855 enough. */ 856 857 int 858 riscv_address_insns (rtx x, machine_mode mode, bool might_split_p) 859 { 860 struct riscv_address_info addr; 861 int n = 1; 862 863 if (!riscv_classify_address (&addr, x, mode, false)) 864 { 865 /* This could be a pattern from the pic.md file. In which case we want 866 this address to always have a cost of 3 to make it as expensive as the 867 most expensive symbol. This prevents constant propagation from 868 preferring symbols over register plus offset. */ 869 return 3; 870 } 871 872 /* BLKmode is used for single unaligned loads and stores and should 873 not count as a multiword mode. */ 874 if (mode != BLKmode && might_split_p) 875 n += (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 876 877 if (addr.type == ADDRESS_LO_SUM) 878 n += riscv_symbol_insns (addr.symbol_type) - 1; 879 880 return n; 881 } 882 883 /* Return the number of instructions needed to load constant X. 884 Return 0 if X isn't a valid constant. */ 885 886 int 887 riscv_const_insns (rtx x) 888 { 889 enum riscv_symbol_type symbol_type; 890 rtx offset; 891 892 switch (GET_CODE (x)) 893 { 894 case HIGH: 895 if (!riscv_symbolic_constant_p (XEXP (x, 0), &symbol_type) 896 || !riscv_split_symbol_type (symbol_type)) 897 return 0; 898 899 /* This is simply an LUI. */ 900 return 1; 901 902 case CONST_INT: 903 { 904 int cost = riscv_integer_cost (INTVAL (x)); 905 /* Force complicated constants to memory. */ 906 return cost < 4 ? cost : 0; 907 } 908 909 case CONST_DOUBLE: 910 case CONST_VECTOR: 911 /* We can use x0 to load floating-point zero. */ 912 return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; 913 914 case CONST: 915 /* See if we can refer to X directly. */ 916 if (riscv_symbolic_constant_p (x, &symbol_type)) 917 return riscv_symbol_insns (symbol_type); 918 919 /* Otherwise try splitting the constant into a base and offset. */ 920 split_const (x, &x, &offset); 921 if (offset != 0) 922 { 923 int n = riscv_const_insns (x); 924 if (n != 0) 925 return n + riscv_integer_cost (INTVAL (offset)); 926 } 927 return 0; 928 929 case SYMBOL_REF: 930 case LABEL_REF: 931 return riscv_symbol_insns (riscv_classify_symbol (x)); 932 933 default: 934 return 0; 935 } 936 } 937 938 /* X is a doubleword constant that can be handled by splitting it into 939 two words and loading each word separately. Return the number of 940 instructions required to do this. */ 941 942 int 943 riscv_split_const_insns (rtx x) 944 { 945 unsigned int low, high; 946 947 low = riscv_const_insns (riscv_subword (x, false)); 948 high = riscv_const_insns (riscv_subword (x, true)); 949 gcc_assert (low > 0 && high > 0); 950 return low + high; 951 } 952 953 /* Return the number of instructions needed to implement INSN, 954 given that it loads from or stores to MEM. */ 955 956 int 957 riscv_load_store_insns (rtx mem, rtx_insn *insn) 958 { 959 machine_mode mode; 960 bool might_split_p; 961 rtx set; 962 963 gcc_assert (MEM_P (mem)); 964 mode = GET_MODE (mem); 965 966 /* Try to prove that INSN does not need to be split. */ 967 might_split_p = true; 968 if (GET_MODE_BITSIZE (mode) <= 32) 969 might_split_p = false; 970 else if (GET_MODE_BITSIZE (mode) == 64) 971 { 972 set = single_set (insn); 973 if (set && !riscv_split_64bit_move_p (SET_DEST (set), SET_SRC (set))) 974 might_split_p = false; 975 } 976 977 return riscv_address_insns (XEXP (mem, 0), mode, might_split_p); 978 } 979 980 /* Emit a move from SRC to DEST. Assume that the move expanders can 981 handle all moves if !can_create_pseudo_p (). The distinction is 982 important because, unlike emit_move_insn, the move expanders know 983 how to force Pmode objects into the constant pool even when the 984 constant pool address is not itself legitimate. */ 985 986 rtx 987 riscv_emit_move (rtx dest, rtx src) 988 { 989 return (can_create_pseudo_p () 990 ? emit_move_insn (dest, src) 991 : emit_move_insn_1 (dest, src)); 992 } 993 994 /* Emit an instruction of the form (set TARGET SRC). */ 995 996 static rtx 997 riscv_emit_set (rtx target, rtx src) 998 { 999 emit_insn (gen_rtx_SET (target, src)); 1000 return target; 1001 } 1002 1003 /* Emit an instruction of the form (set DEST (CODE X Y)). */ 1004 1005 static rtx 1006 riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y) 1007 { 1008 return riscv_emit_set (dest, gen_rtx_fmt_ee (code, GET_MODE (dest), x, y)); 1009 } 1010 1011 /* Compute (CODE X Y) and store the result in a new register 1012 of mode MODE. Return that new register. */ 1013 1014 static rtx 1015 riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y) 1016 { 1017 return riscv_emit_binary (code, gen_reg_rtx (mode), x, y); 1018 } 1019 1020 /* Copy VALUE to a register and return that register. If new pseudos 1021 are allowed, copy it into a new register, otherwise use DEST. */ 1022 1023 static rtx 1024 riscv_force_temporary (rtx dest, rtx value, bool in_splitter) 1025 { 1026 /* We can't call gen_reg_rtx from a splitter, because this might realloc 1027 the regno_reg_rtx array, which would invalidate reg rtx pointers in the 1028 combine undo buffer. */ 1029 if (can_create_pseudo_p () && !in_splitter) 1030 return force_reg (Pmode, value); 1031 else 1032 { 1033 riscv_emit_move (dest, value); 1034 return dest; 1035 } 1036 } 1037 1038 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, 1039 then add CONST_INT OFFSET to the result. */ 1040 1041 static rtx 1042 riscv_unspec_address_offset (rtx base, rtx offset, 1043 enum riscv_symbol_type symbol_type) 1044 { 1045 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), 1046 UNSPEC_ADDRESS_FIRST + symbol_type); 1047 if (offset != const0_rtx) 1048 base = gen_rtx_PLUS (Pmode, base, offset); 1049 return gen_rtx_CONST (Pmode, base); 1050 } 1051 1052 /* Return an UNSPEC address with underlying address ADDRESS and symbol 1053 type SYMBOL_TYPE. */ 1054 1055 rtx 1056 riscv_unspec_address (rtx address, enum riscv_symbol_type symbol_type) 1057 { 1058 rtx base, offset; 1059 1060 split_const (address, &base, &offset); 1061 return riscv_unspec_address_offset (base, offset, symbol_type); 1062 } 1063 1064 /* If OP is an UNSPEC address, return the address to which it refers, 1065 otherwise return OP itself. */ 1066 1067 static rtx 1068 riscv_strip_unspec_address (rtx op) 1069 { 1070 rtx base, offset; 1071 1072 split_const (op, &base, &offset); 1073 if (UNSPEC_ADDRESS_P (base)) 1074 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset)); 1075 return op; 1076 } 1077 1078 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the 1079 high part to BASE and return the result. Just return BASE otherwise. 1080 TEMP is as for riscv_force_temporary. 1081 1082 The returned expression can be used as the first operand to a LO_SUM. */ 1083 1084 static rtx 1085 riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type) 1086 { 1087 addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type)); 1088 return riscv_force_temporary (temp, addr, FALSE); 1089 } 1090 1091 /* Load an entry from the GOT for a TLS GD access. */ 1092 1093 static rtx riscv_got_load_tls_gd (rtx dest, rtx sym) 1094 { 1095 if (Pmode == DImode) 1096 return gen_got_load_tls_gddi (dest, sym); 1097 else 1098 return gen_got_load_tls_gdsi (dest, sym); 1099 } 1100 1101 /* Load an entry from the GOT for a TLS IE access. */ 1102 1103 static rtx riscv_got_load_tls_ie (rtx dest, rtx sym) 1104 { 1105 if (Pmode == DImode) 1106 return gen_got_load_tls_iedi (dest, sym); 1107 else 1108 return gen_got_load_tls_iesi (dest, sym); 1109 } 1110 1111 /* Add in the thread pointer for a TLS LE access. */ 1112 1113 static rtx riscv_tls_add_tp_le (rtx dest, rtx base, rtx sym) 1114 { 1115 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); 1116 if (Pmode == DImode) 1117 return gen_tls_add_tp_ledi (dest, base, tp, sym); 1118 else 1119 return gen_tls_add_tp_lesi (dest, base, tp, sym); 1120 } 1121 1122 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise 1123 it appears in a MEM of that mode. Return true if ADDR is a legitimate 1124 constant in that context and can be split into high and low parts. 1125 If so, and if LOW_OUT is nonnull, emit the high part and store the 1126 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. 1127 1128 TEMP is as for riscv_force_temporary and is used to load the high 1129 part into a register. 1130 1131 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be 1132 a legitimize SET_SRC for an .md pattern, otherwise the low part 1133 is guaranteed to be a legitimate address for mode MODE. */ 1134 1135 bool 1136 riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out, 1137 bool in_splitter) 1138 { 1139 enum riscv_symbol_type symbol_type; 1140 1141 if ((GET_CODE (addr) == HIGH && mode == MAX_MACHINE_MODE) 1142 || !riscv_symbolic_constant_p (addr, &symbol_type) 1143 || riscv_symbol_insns (symbol_type) == 0 1144 || !riscv_split_symbol_type (symbol_type)) 1145 return false; 1146 1147 if (low_out) 1148 switch (symbol_type) 1149 { 1150 case SYMBOL_ABSOLUTE: 1151 { 1152 rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); 1153 high = riscv_force_temporary (temp, high, in_splitter); 1154 *low_out = gen_rtx_LO_SUM (Pmode, high, addr); 1155 } 1156 break; 1157 1158 case SYMBOL_PCREL: 1159 { 1160 static unsigned seqno; 1161 char buf[32]; 1162 rtx label; 1163 1164 ssize_t bytes = snprintf (buf, sizeof (buf), ".LA%u", seqno); 1165 gcc_assert ((size_t) bytes < sizeof (buf)); 1166 1167 label = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 1168 SYMBOL_REF_FLAGS (label) |= SYMBOL_FLAG_LOCAL; 1169 /* ??? Ugly hack to make weak symbols work. May need to change the 1170 RTL for the auipc and/or low patterns to get a better fix for 1171 this. */ 1172 if (! nonzero_address_p (addr)) 1173 SYMBOL_REF_WEAK (label) = 1; 1174 1175 if (temp == NULL) 1176 temp = gen_reg_rtx (Pmode); 1177 1178 if (Pmode == DImode) 1179 emit_insn (gen_auipcdi (temp, copy_rtx (addr), GEN_INT (seqno))); 1180 else 1181 emit_insn (gen_auipcsi (temp, copy_rtx (addr), GEN_INT (seqno))); 1182 1183 *low_out = gen_rtx_LO_SUM (Pmode, temp, label); 1184 1185 seqno++; 1186 } 1187 break; 1188 1189 default: 1190 gcc_unreachable (); 1191 } 1192 1193 return true; 1194 } 1195 1196 /* Return a legitimate address for REG + OFFSET. TEMP is as for 1197 riscv_force_temporary; it is only needed when OFFSET is not a 1198 SMALL_OPERAND. */ 1199 1200 static rtx 1201 riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) 1202 { 1203 if (!SMALL_OPERAND (offset)) 1204 { 1205 rtx high; 1206 1207 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. 1208 The addition inside the macro CONST_HIGH_PART may cause an 1209 overflow, so we need to force a sign-extension check. */ 1210 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); 1211 offset = CONST_LOW_PART (offset); 1212 high = riscv_force_temporary (temp, high, FALSE); 1213 reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg), 1214 FALSE); 1215 } 1216 return plus_constant (Pmode, reg, offset); 1217 } 1218 1219 /* The __tls_get_attr symbol. */ 1220 static GTY(()) rtx riscv_tls_symbol; 1221 1222 /* Return an instruction sequence that calls __tls_get_addr. SYM is 1223 the TLS symbol we are referencing and TYPE is the symbol type to use 1224 (either global dynamic or local dynamic). RESULT is an RTX for the 1225 return value location. */ 1226 1227 static rtx_insn * 1228 riscv_call_tls_get_addr (rtx sym, rtx result) 1229 { 1230 rtx a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST), func; 1231 rtx_insn *insn; 1232 1233 if (!riscv_tls_symbol) 1234 riscv_tls_symbol = init_one_libfunc ("__tls_get_addr"); 1235 func = gen_rtx_MEM (FUNCTION_MODE, riscv_tls_symbol); 1236 1237 start_sequence (); 1238 1239 emit_insn (riscv_got_load_tls_gd (a0, sym)); 1240 insn = emit_call_insn (gen_call_value (result, func, const0_rtx, NULL)); 1241 RTL_CONST_CALL_P (insn) = 1; 1242 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); 1243 insn = get_insns (); 1244 1245 end_sequence (); 1246 1247 return insn; 1248 } 1249 1250 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return 1251 its address. The return value will be both a valid address and a valid 1252 SET_SRC (either a REG or a LO_SUM). */ 1253 1254 static rtx 1255 riscv_legitimize_tls_address (rtx loc) 1256 { 1257 rtx dest, tp, tmp; 1258 enum tls_model model = SYMBOL_REF_TLS_MODEL (loc); 1259 1260 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */ 1261 if (!flag_pic) 1262 model = TLS_MODEL_LOCAL_EXEC; 1263 1264 switch (model) 1265 { 1266 case TLS_MODEL_LOCAL_DYNAMIC: 1267 /* Rely on section anchors for the optimization that LDM TLS 1268 provides. The anchor's address is loaded with GD TLS. */ 1269 case TLS_MODEL_GLOBAL_DYNAMIC: 1270 tmp = gen_rtx_REG (Pmode, GP_RETURN); 1271 dest = gen_reg_rtx (Pmode); 1272 emit_libcall_block (riscv_call_tls_get_addr (loc, tmp), dest, tmp, loc); 1273 break; 1274 1275 case TLS_MODEL_INITIAL_EXEC: 1276 /* la.tls.ie; tp-relative add */ 1277 tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); 1278 tmp = gen_reg_rtx (Pmode); 1279 emit_insn (riscv_got_load_tls_ie (tmp, loc)); 1280 dest = gen_reg_rtx (Pmode); 1281 emit_insn (gen_add3_insn (dest, tmp, tp)); 1282 break; 1283 1284 case TLS_MODEL_LOCAL_EXEC: 1285 tmp = riscv_unspec_offset_high (NULL, loc, SYMBOL_TLS_LE); 1286 dest = gen_reg_rtx (Pmode); 1287 emit_insn (riscv_tls_add_tp_le (dest, tmp, loc)); 1288 dest = gen_rtx_LO_SUM (Pmode, dest, 1289 riscv_unspec_address (loc, SYMBOL_TLS_LE)); 1290 break; 1291 1292 default: 1293 gcc_unreachable (); 1294 } 1295 return dest; 1296 } 1297 1298 /* If X is not a valid address for mode MODE, force it into a register. */ 1299 1300 static rtx 1301 riscv_force_address (rtx x, machine_mode mode) 1302 { 1303 if (!riscv_legitimate_address_p (mode, x, false)) 1304 x = force_reg (Pmode, x); 1305 return x; 1306 } 1307 1308 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can 1309 be legitimized in a way that the generic machinery might not expect, 1310 return a new address, otherwise return NULL. MODE is the mode of 1311 the memory being accessed. */ 1312 1313 static rtx 1314 riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, 1315 machine_mode mode) 1316 { 1317 rtx addr; 1318 1319 if (riscv_tls_symbol_p (x)) 1320 return riscv_legitimize_tls_address (x); 1321 1322 /* See if the address can split into a high part and a LO_SUM. */ 1323 if (riscv_split_symbol (NULL, x, mode, &addr, FALSE)) 1324 return riscv_force_address (addr, mode); 1325 1326 /* Handle BASE + OFFSET using riscv_add_offset. */ 1327 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) 1328 && INTVAL (XEXP (x, 1)) != 0) 1329 { 1330 rtx base = XEXP (x, 0); 1331 HOST_WIDE_INT offset = INTVAL (XEXP (x, 1)); 1332 1333 if (!riscv_valid_base_register_p (base, mode, false)) 1334 base = copy_to_mode_reg (Pmode, base); 1335 addr = riscv_add_offset (NULL, base, offset); 1336 return riscv_force_address (addr, mode); 1337 } 1338 1339 return x; 1340 } 1341 1342 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. */ 1343 1344 void 1345 riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, 1346 bool in_splitter) 1347 { 1348 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 1349 machine_mode mode; 1350 int i, num_ops; 1351 rtx x; 1352 1353 /* We can't call gen_reg_rtx from a splitter, because this might realloc 1354 the regno_reg_rtx array, which would invalidate reg rtx pointers in the 1355 combine undo buffer. */ 1356 bool can_create_pseudo = can_create_pseudo_p () && ! in_splitter; 1357 1358 mode = GET_MODE (dest); 1359 num_ops = riscv_build_integer (codes, value, mode); 1360 1361 if (can_create_pseudo && num_ops > 2 /* not a simple constant */ 1362 && num_ops >= riscv_split_integer_cost (value)) 1363 x = riscv_split_integer (value, mode); 1364 else 1365 { 1366 /* Apply each binary operation to X. */ 1367 x = GEN_INT (codes[0].value); 1368 1369 for (i = 1; i < num_ops; i++) 1370 { 1371 if (!can_create_pseudo) 1372 x = riscv_emit_set (temp, x); 1373 else 1374 x = force_reg (mode, x); 1375 1376 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); 1377 } 1378 } 1379 1380 riscv_emit_set (dest, x); 1381 } 1382 1383 /* Subroutine of riscv_legitimize_move. Move constant SRC into register 1384 DEST given that SRC satisfies immediate_operand but doesn't satisfy 1385 move_operand. */ 1386 1387 static void 1388 riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) 1389 { 1390 rtx base, offset; 1391 1392 /* Split moves of big integers into smaller pieces. */ 1393 if (splittable_const_int_operand (src, mode)) 1394 { 1395 riscv_move_integer (dest, dest, INTVAL (src), FALSE); 1396 return; 1397 } 1398 1399 /* Split moves of symbolic constants into high/low pairs. */ 1400 if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src, FALSE)) 1401 { 1402 riscv_emit_set (dest, src); 1403 return; 1404 } 1405 1406 /* Generate the appropriate access sequences for TLS symbols. */ 1407 if (riscv_tls_symbol_p (src)) 1408 { 1409 riscv_emit_move (dest, riscv_legitimize_tls_address (src)); 1410 return; 1411 } 1412 1413 /* If we have (const (plus symbol offset)), and that expression cannot 1414 be forced into memory, load the symbol first and add in the offset. Also 1415 prefer to do this even if the constant _can_ be forced into memory, as it 1416 usually produces better code. */ 1417 split_const (src, &base, &offset); 1418 if (offset != const0_rtx 1419 && (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ())) 1420 { 1421 base = riscv_force_temporary (dest, base, FALSE); 1422 riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset))); 1423 return; 1424 } 1425 1426 src = force_const_mem (mode, src); 1427 1428 /* When using explicit relocs, constant pool references are sometimes 1429 not legitimate addresses. */ 1430 riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0), FALSE); 1431 riscv_emit_move (dest, src); 1432 } 1433 1434 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent 1435 sequence that is valid. */ 1436 1437 bool 1438 riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) 1439 { 1440 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) 1441 { 1442 riscv_emit_move (dest, force_reg (mode, src)); 1443 return true; 1444 } 1445 1446 /* We need to deal with constants that would be legitimate 1447 immediate_operands but aren't legitimate move_operands. */ 1448 if (CONSTANT_P (src) && !move_operand (src, mode)) 1449 { 1450 riscv_legitimize_const_move (mode, dest, src); 1451 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); 1452 return true; 1453 } 1454 1455 /* RISC-V GCC may generate non-legitimate address due to we provide some 1456 pattern for optimize access PIC local symbol and it's make GCC generate 1457 unrecognizable instruction during optmizing. */ 1458 1459 if (MEM_P (dest) && !riscv_legitimate_address_p (mode, XEXP (dest, 0), 1460 reload_completed)) 1461 { 1462 XEXP (dest, 0) = riscv_force_address (XEXP (dest, 0), mode); 1463 } 1464 1465 if (MEM_P (src) && !riscv_legitimate_address_p (mode, XEXP (src, 0), 1466 reload_completed)) 1467 { 1468 XEXP (src, 0) = riscv_force_address (XEXP (src, 0), mode); 1469 } 1470 1471 return false; 1472 } 1473 1474 /* Return true if there is an instruction that implements CODE and accepts 1475 X as an immediate operand. */ 1476 1477 static int 1478 riscv_immediate_operand_p (int code, HOST_WIDE_INT x) 1479 { 1480 switch (code) 1481 { 1482 case ASHIFT: 1483 case ASHIFTRT: 1484 case LSHIFTRT: 1485 /* All shift counts are truncated to a valid constant. */ 1486 return true; 1487 1488 case AND: 1489 case IOR: 1490 case XOR: 1491 case PLUS: 1492 case LT: 1493 case LTU: 1494 /* These instructions take 12-bit signed immediates. */ 1495 return SMALL_OPERAND (x); 1496 1497 case LE: 1498 /* We add 1 to the immediate and use SLT. */ 1499 return SMALL_OPERAND (x + 1); 1500 1501 case LEU: 1502 /* Likewise SLTU, but reject the always-true case. */ 1503 return SMALL_OPERAND (x + 1) && x + 1 != 0; 1504 1505 case GE: 1506 case GEU: 1507 /* We can emulate an immediate of 1 by using GT/GTU against x0. */ 1508 return x == 1; 1509 1510 default: 1511 /* By default assume that x0 can be used for 0. */ 1512 return x == 0; 1513 } 1514 } 1515 1516 /* Return the cost of binary operation X, given that the instruction 1517 sequence for a word-sized or smaller operation takes SIGNLE_INSNS 1518 instructions and that the sequence of a double-word operation takes 1519 DOUBLE_INSNS instructions. */ 1520 1521 static int 1522 riscv_binary_cost (rtx x, int single_insns, int double_insns) 1523 { 1524 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) 1525 return COSTS_N_INSNS (double_insns); 1526 return COSTS_N_INSNS (single_insns); 1527 } 1528 1529 /* Return the cost of sign- or zero-extending OP. */ 1530 1531 static int 1532 riscv_extend_cost (rtx op, bool unsigned_p) 1533 { 1534 if (MEM_P (op)) 1535 return 0; 1536 1537 if (unsigned_p && GET_MODE (op) == QImode) 1538 /* We can use ANDI. */ 1539 return COSTS_N_INSNS (1); 1540 1541 if (!unsigned_p && GET_MODE (op) == SImode) 1542 /* We can use SEXT.W. */ 1543 return COSTS_N_INSNS (1); 1544 1545 /* We need to use a shift left and a shift right. */ 1546 return COSTS_N_INSNS (2); 1547 } 1548 1549 /* Implement TARGET_RTX_COSTS. */ 1550 1551 #define SINGLE_SHIFT_COST 1 1552 1553 static bool 1554 riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UNUSED, 1555 int *total, bool speed) 1556 { 1557 bool float_mode_p = FLOAT_MODE_P (mode); 1558 int cost; 1559 1560 switch (GET_CODE (x)) 1561 { 1562 case CONST_INT: 1563 if (riscv_immediate_operand_p (outer_code, INTVAL (x))) 1564 { 1565 *total = 0; 1566 return true; 1567 } 1568 /* Fall through. */ 1569 1570 case SYMBOL_REF: 1571 case LABEL_REF: 1572 case CONST_DOUBLE: 1573 case CONST: 1574 if ((cost = riscv_const_insns (x)) > 0) 1575 { 1576 /* If the constant is likely to be stored in a GPR, SETs of 1577 single-insn constants are as cheap as register sets; we 1578 never want to CSE them. */ 1579 if (cost == 1 && outer_code == SET) 1580 *total = 0; 1581 /* When we load a constant more than once, it usually is better 1582 to duplicate the last operation in the sequence than to CSE 1583 the constant itself. */ 1584 else if (outer_code == SET || GET_MODE (x) == VOIDmode) 1585 *total = COSTS_N_INSNS (1); 1586 } 1587 else /* The instruction will be fetched from the constant pool. */ 1588 *total = COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE)); 1589 return true; 1590 1591 case MEM: 1592 /* If the address is legitimate, return the number of 1593 instructions it needs. */ 1594 if ((cost = riscv_address_insns (XEXP (x, 0), mode, true)) > 0) 1595 { 1596 *total = COSTS_N_INSNS (cost + tune_info->memory_cost); 1597 return true; 1598 } 1599 /* Otherwise use the default handling. */ 1600 return false; 1601 1602 case NOT: 1603 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); 1604 return false; 1605 1606 case AND: 1607 case IOR: 1608 case XOR: 1609 /* Double-word operations use two single-word operations. */ 1610 *total = riscv_binary_cost (x, 1, 2); 1611 return false; 1612 1613 case ZERO_EXTRACT: 1614 /* This is an SImode shift. */ 1615 if (outer_code == SET 1616 && CONST_INT_P (XEXP (x, 1)) 1617 && CONST_INT_P (XEXP (x, 2)) 1618 && (INTVAL (XEXP (x, 2)) > 0) 1619 && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (x, 2)) == 32)) 1620 { 1621 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 1622 return true; 1623 } 1624 return false; 1625 1626 case ASHIFT: 1627 case ASHIFTRT: 1628 case LSHIFTRT: 1629 *total = riscv_binary_cost (x, SINGLE_SHIFT_COST, 1630 CONSTANT_P (XEXP (x, 1)) ? 4 : 9); 1631 return false; 1632 1633 case ABS: 1634 *total = COSTS_N_INSNS (float_mode_p ? 1 : 3); 1635 return false; 1636 1637 case LO_SUM: 1638 *total = set_src_cost (XEXP (x, 0), mode, speed); 1639 return true; 1640 1641 case LT: 1642 /* This is an SImode shift. */ 1643 if (outer_code == SET && GET_MODE (x) == DImode 1644 && GET_MODE (XEXP (x, 0)) == SImode) 1645 { 1646 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 1647 return true; 1648 } 1649 /* Fall through. */ 1650 case LTU: 1651 case LE: 1652 case LEU: 1653 case GT: 1654 case GTU: 1655 case GE: 1656 case GEU: 1657 case EQ: 1658 case NE: 1659 /* Branch comparisons have VOIDmode, so use the first operand's 1660 mode instead. */ 1661 mode = GET_MODE (XEXP (x, 0)); 1662 if (float_mode_p) 1663 *total = tune_info->fp_add[mode == DFmode]; 1664 else 1665 *total = riscv_binary_cost (x, 1, 3); 1666 return false; 1667 1668 case UNORDERED: 1669 case ORDERED: 1670 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */ 1671 mode = GET_MODE (XEXP (x, 0)); 1672 *total = tune_info->fp_add[mode == DFmode] + COSTS_N_INSNS (2); 1673 return false; 1674 1675 case UNEQ: 1676 case LTGT: 1677 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */ 1678 mode = GET_MODE (XEXP (x, 0)); 1679 *total = tune_info->fp_add[mode == DFmode] + COSTS_N_INSNS (3); 1680 return false; 1681 1682 case UNGE: 1683 case UNGT: 1684 case UNLE: 1685 case UNLT: 1686 /* FLT or FLE, but guarded by an FFLAGS read and write. */ 1687 mode = GET_MODE (XEXP (x, 0)); 1688 *total = tune_info->fp_add[mode == DFmode] + COSTS_N_INSNS (4); 1689 return false; 1690 1691 case MINUS: 1692 case PLUS: 1693 if (float_mode_p) 1694 *total = tune_info->fp_add[mode == DFmode]; 1695 else 1696 *total = riscv_binary_cost (x, 1, 4); 1697 return false; 1698 1699 case NEG: 1700 { 1701 rtx op = XEXP (x, 0); 1702 if (GET_CODE (op) == FMA && !HONOR_SIGNED_ZEROS (mode)) 1703 { 1704 *total = (tune_info->fp_mul[mode == DFmode] 1705 + set_src_cost (XEXP (op, 0), mode, speed) 1706 + set_src_cost (XEXP (op, 1), mode, speed) 1707 + set_src_cost (XEXP (op, 2), mode, speed)); 1708 return true; 1709 } 1710 } 1711 1712 if (float_mode_p) 1713 *total = tune_info->fp_add[mode == DFmode]; 1714 else 1715 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); 1716 return false; 1717 1718 case MULT: 1719 if (float_mode_p) 1720 *total = tune_info->fp_mul[mode == DFmode]; 1721 else if (!TARGET_MUL) 1722 /* Estimate the cost of a library call. */ 1723 *total = COSTS_N_INSNS (speed ? 32 : 6); 1724 else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) 1725 *total = 3 * tune_info->int_mul[0] + COSTS_N_INSNS (2); 1726 else if (!speed) 1727 *total = COSTS_N_INSNS (1); 1728 else 1729 *total = tune_info->int_mul[mode == DImode]; 1730 return false; 1731 1732 case DIV: 1733 case SQRT: 1734 case MOD: 1735 if (float_mode_p) 1736 { 1737 *total = tune_info->fp_div[mode == DFmode]; 1738 return false; 1739 } 1740 /* Fall through. */ 1741 1742 case UDIV: 1743 case UMOD: 1744 if (!TARGET_DIV) 1745 /* Estimate the cost of a library call. */ 1746 *total = COSTS_N_INSNS (speed ? 32 : 6); 1747 else if (speed) 1748 *total = tune_info->int_div[mode == DImode]; 1749 else 1750 *total = COSTS_N_INSNS (1); 1751 return false; 1752 1753 case ZERO_EXTEND: 1754 /* This is an SImode shift. */ 1755 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT) 1756 { 1757 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 1758 return true; 1759 } 1760 /* Fall through. */ 1761 case SIGN_EXTEND: 1762 *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND); 1763 return false; 1764 1765 case FLOAT: 1766 case UNSIGNED_FLOAT: 1767 case FIX: 1768 case FLOAT_EXTEND: 1769 case FLOAT_TRUNCATE: 1770 *total = tune_info->fp_add[mode == DFmode]; 1771 return false; 1772 1773 case FMA: 1774 *total = (tune_info->fp_mul[mode == DFmode] 1775 + set_src_cost (XEXP (x, 0), mode, speed) 1776 + set_src_cost (XEXP (x, 1), mode, speed) 1777 + set_src_cost (XEXP (x, 2), mode, speed)); 1778 return true; 1779 1780 case UNSPEC: 1781 if (XINT (x, 1) == UNSPEC_AUIPC) 1782 { 1783 /* Make AUIPC cheap to avoid spilling its result to the stack. */ 1784 *total = 1; 1785 return true; 1786 } 1787 return false; 1788 1789 default: 1790 return false; 1791 } 1792 } 1793 1794 /* Implement TARGET_ADDRESS_COST. */ 1795 1796 static int 1797 riscv_address_cost (rtx addr, machine_mode mode, 1798 addr_space_t as ATTRIBUTE_UNUSED, 1799 bool speed ATTRIBUTE_UNUSED) 1800 { 1801 return riscv_address_insns (addr, mode, false); 1802 } 1803 1804 /* Return one word of double-word value OP. HIGH_P is true to select the 1805 high part or false to select the low part. */ 1806 1807 rtx 1808 riscv_subword (rtx op, bool high_p) 1809 { 1810 unsigned int byte = high_p ? UNITS_PER_WORD : 0; 1811 machine_mode mode = GET_MODE (op); 1812 1813 if (mode == VOIDmode) 1814 mode = TARGET_64BIT ? TImode : DImode; 1815 1816 if (MEM_P (op)) 1817 return adjust_address (op, word_mode, byte); 1818 1819 if (REG_P (op)) 1820 gcc_assert (!FP_REG_RTX_P (op)); 1821 1822 return simplify_gen_subreg (word_mode, op, mode, byte); 1823 } 1824 1825 /* Return true if a 64-bit move from SRC to DEST should be split into two. */ 1826 1827 bool 1828 riscv_split_64bit_move_p (rtx dest, rtx src) 1829 { 1830 if (TARGET_64BIT) 1831 return false; 1832 1833 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case 1834 of zeroing an FPR with FCVT.D.W. */ 1835 if (TARGET_DOUBLE_FLOAT 1836 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) 1837 || (FP_REG_RTX_P (dest) && MEM_P (src)) 1838 || (FP_REG_RTX_P (src) && MEM_P (dest)) 1839 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) 1840 return false; 1841 1842 return true; 1843 } 1844 1845 /* Split a doubleword move from SRC to DEST. On 32-bit targets, 1846 this function handles 64-bit moves for which riscv_split_64bit_move_p 1847 holds. For 64-bit targets, this function handles 128-bit moves. */ 1848 1849 void 1850 riscv_split_doubleword_move (rtx dest, rtx src) 1851 { 1852 rtx low_dest; 1853 1854 /* The operation can be split into two normal moves. Decide in 1855 which order to do them. */ 1856 low_dest = riscv_subword (dest, false); 1857 if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src)) 1858 { 1859 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); 1860 riscv_emit_move (low_dest, riscv_subword (src, false)); 1861 } 1862 else 1863 { 1864 riscv_emit_move (low_dest, riscv_subword (src, false)); 1865 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); 1866 } 1867 } 1868 1869 /* Return the appropriate instructions to move SRC into DEST. Assume 1870 that SRC is operand 1 and DEST is operand 0. */ 1871 1872 const char * 1873 riscv_output_move (rtx dest, rtx src) 1874 { 1875 enum rtx_code dest_code, src_code; 1876 machine_mode mode; 1877 bool dbl_p; 1878 1879 dest_code = GET_CODE (dest); 1880 src_code = GET_CODE (src); 1881 mode = GET_MODE (dest); 1882 dbl_p = (GET_MODE_SIZE (mode) == 8); 1883 1884 if (dbl_p && riscv_split_64bit_move_p (dest, src)) 1885 return "#"; 1886 1887 if (dest_code == REG && GP_REG_P (REGNO (dest))) 1888 { 1889 if (src_code == REG && FP_REG_P (REGNO (src))) 1890 return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.s\t%0,%1"; 1891 1892 if (src_code == MEM) 1893 switch (GET_MODE_SIZE (mode)) 1894 { 1895 case 1: return "lbu\t%0,%1"; 1896 case 2: return "lhu\t%0,%1"; 1897 case 4: return "lw\t%0,%1"; 1898 case 8: return "ld\t%0,%1"; 1899 } 1900 1901 if (src_code == CONST_INT) 1902 return "li\t%0,%1"; 1903 1904 if (src_code == HIGH) 1905 return "lui\t%0,%h1"; 1906 1907 if (symbolic_operand (src, VOIDmode)) 1908 switch (riscv_classify_symbolic_expression (src)) 1909 { 1910 case SYMBOL_GOT_DISP: return "la\t%0,%1"; 1911 case SYMBOL_ABSOLUTE: return "lla\t%0,%1"; 1912 case SYMBOL_PCREL: return "lla\t%0,%1"; 1913 default: gcc_unreachable (); 1914 } 1915 } 1916 if ((src_code == REG && GP_REG_P (REGNO (src))) 1917 || (src == CONST0_RTX (mode))) 1918 { 1919 if (dest_code == REG) 1920 { 1921 if (GP_REG_P (REGNO (dest))) 1922 return "mv\t%0,%z1"; 1923 1924 if (FP_REG_P (REGNO (dest))) 1925 { 1926 if (!dbl_p) 1927 return "fmv.s.x\t%0,%z1"; 1928 if (TARGET_64BIT) 1929 return "fmv.d.x\t%0,%z1"; 1930 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */ 1931 gcc_assert (src == CONST0_RTX (mode)); 1932 return "fcvt.d.w\t%0,x0"; 1933 } 1934 } 1935 if (dest_code == MEM) 1936 switch (GET_MODE_SIZE (mode)) 1937 { 1938 case 1: return "sb\t%z1,%0"; 1939 case 2: return "sh\t%z1,%0"; 1940 case 4: return "sw\t%z1,%0"; 1941 case 8: return "sd\t%z1,%0"; 1942 } 1943 } 1944 if (src_code == REG && FP_REG_P (REGNO (src))) 1945 { 1946 if (dest_code == REG && FP_REG_P (REGNO (dest))) 1947 return dbl_p ? "fmv.d\t%0,%1" : "fmv.s\t%0,%1"; 1948 1949 if (dest_code == MEM) 1950 return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0"; 1951 } 1952 if (dest_code == REG && FP_REG_P (REGNO (dest))) 1953 { 1954 if (src_code == MEM) 1955 return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1"; 1956 } 1957 gcc_unreachable (); 1958 } 1959 1960 const char * 1961 riscv_output_return () 1962 { 1963 if (cfun->machine->naked_p) 1964 return ""; 1965 1966 return "ret"; 1967 } 1968 1969 1970 /* Return true if CMP1 is a suitable second operand for integer ordering 1971 test CODE. See also the *sCC patterns in riscv.md. */ 1972 1973 static bool 1974 riscv_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) 1975 { 1976 switch (code) 1977 { 1978 case GT: 1979 case GTU: 1980 return reg_or_0_operand (cmp1, VOIDmode); 1981 1982 case GE: 1983 case GEU: 1984 return cmp1 == const1_rtx; 1985 1986 case LT: 1987 case LTU: 1988 return arith_operand (cmp1, VOIDmode); 1989 1990 case LE: 1991 return sle_operand (cmp1, VOIDmode); 1992 1993 case LEU: 1994 return sleu_operand (cmp1, VOIDmode); 1995 1996 default: 1997 gcc_unreachable (); 1998 } 1999 } 2000 2001 /* Return true if *CMP1 (of mode MODE) is a valid second operand for 2002 integer ordering test *CODE, or if an equivalent combination can 2003 be formed by adjusting *CODE and *CMP1. When returning true, update 2004 *CODE and *CMP1 with the chosen code and operand, otherwise leave 2005 them alone. */ 2006 2007 static bool 2008 riscv_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, 2009 machine_mode mode) 2010 { 2011 HOST_WIDE_INT plus_one; 2012 2013 if (riscv_int_order_operand_ok_p (*code, *cmp1)) 2014 return true; 2015 2016 if (CONST_INT_P (*cmp1)) 2017 switch (*code) 2018 { 2019 case LE: 2020 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 2021 if (INTVAL (*cmp1) < plus_one) 2022 { 2023 *code = LT; 2024 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 2025 return true; 2026 } 2027 break; 2028 2029 case LEU: 2030 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 2031 if (plus_one != 0) 2032 { 2033 *code = LTU; 2034 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 2035 return true; 2036 } 2037 break; 2038 2039 default: 2040 break; 2041 } 2042 return false; 2043 } 2044 2045 /* Compare CMP0 and CMP1 using ordering test CODE and store the result 2046 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR 2047 is nonnull, it's OK to set TARGET to the inverse of the result and 2048 flip *INVERT_PTR instead. */ 2049 2050 static void 2051 riscv_emit_int_order_test (enum rtx_code code, bool *invert_ptr, 2052 rtx target, rtx cmp0, rtx cmp1) 2053 { 2054 machine_mode mode; 2055 2056 /* First see if there is a RISCV instruction that can do this operation. 2057 If not, try doing the same for the inverse operation. If that also 2058 fails, force CMP1 into a register and try again. */ 2059 mode = GET_MODE (cmp0); 2060 if (riscv_canonicalize_int_order_test (&code, &cmp1, mode)) 2061 riscv_emit_binary (code, target, cmp0, cmp1); 2062 else 2063 { 2064 enum rtx_code inv_code = reverse_condition (code); 2065 if (!riscv_canonicalize_int_order_test (&inv_code, &cmp1, mode)) 2066 { 2067 cmp1 = force_reg (mode, cmp1); 2068 riscv_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); 2069 } 2070 else if (invert_ptr == 0) 2071 { 2072 rtx inv_target = riscv_force_binary (GET_MODE (target), 2073 inv_code, cmp0, cmp1); 2074 riscv_emit_binary (XOR, target, inv_target, const1_rtx); 2075 } 2076 else 2077 { 2078 *invert_ptr = !*invert_ptr; 2079 riscv_emit_binary (inv_code, target, cmp0, cmp1); 2080 } 2081 } 2082 } 2083 2084 /* Return a register that is zero iff CMP0 and CMP1 are equal. 2085 The register will have the same mode as CMP0. */ 2086 2087 static rtx 2088 riscv_zero_if_equal (rtx cmp0, rtx cmp1) 2089 { 2090 if (cmp1 == const0_rtx) 2091 return cmp0; 2092 2093 return expand_binop (GET_MODE (cmp0), sub_optab, 2094 cmp0, cmp1, 0, 0, OPTAB_DIRECT); 2095 } 2096 2097 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */ 2098 2099 static void 2100 riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1) 2101 { 2102 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */ 2103 if (GET_MODE_SIZE (word_mode) > GET_MODE_SIZE (GET_MODE (*op0))) 2104 { 2105 /* It is more profitable to zero-extend QImode values. But not if the 2106 first operand has already been sign-extended, and the second one is 2107 is a constant or has already been sign-extended also. */ 2108 if (unsigned_condition (code) == code 2109 && (GET_MODE (*op0) == QImode 2110 && ! (GET_CODE (*op0) == SUBREG 2111 && SUBREG_PROMOTED_VAR_P (*op0) 2112 && SUBREG_PROMOTED_SIGNED_P (*op0) 2113 && (CONST_INT_P (*op1) 2114 || (GET_CODE (*op1) == SUBREG 2115 && SUBREG_PROMOTED_VAR_P (*op1) 2116 && SUBREG_PROMOTED_SIGNED_P (*op1)))))) 2117 { 2118 *op0 = gen_rtx_ZERO_EXTEND (word_mode, *op0); 2119 if (CONST_INT_P (*op1)) 2120 *op1 = GEN_INT ((uint8_t) INTVAL (*op1)); 2121 else 2122 *op1 = gen_rtx_ZERO_EXTEND (word_mode, *op1); 2123 } 2124 else 2125 { 2126 *op0 = gen_rtx_SIGN_EXTEND (word_mode, *op0); 2127 if (*op1 != const0_rtx) 2128 *op1 = gen_rtx_SIGN_EXTEND (word_mode, *op1); 2129 } 2130 } 2131 } 2132 2133 /* Convert a comparison into something that can be used in a branch. On 2134 entry, *OP0 and *OP1 are the values being compared and *CODE is the code 2135 used to compare them. Update them to describe the final comparison. */ 2136 2137 static void 2138 riscv_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1) 2139 { 2140 if (splittable_const_int_operand (*op1, VOIDmode)) 2141 { 2142 HOST_WIDE_INT rhs = INTVAL (*op1); 2143 2144 if (*code == EQ || *code == NE) 2145 { 2146 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */ 2147 if (SMALL_OPERAND (-rhs)) 2148 { 2149 *op0 = riscv_force_binary (GET_MODE (*op0), PLUS, *op0, 2150 GEN_INT (-rhs)); 2151 *op1 = const0_rtx; 2152 } 2153 } 2154 else 2155 { 2156 static const enum rtx_code mag_comparisons[][2] = { 2157 {LEU, LTU}, {GTU, GEU}, {LE, LT}, {GT, GE} 2158 }; 2159 2160 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */ 2161 for (size_t i = 0; i < ARRAY_SIZE (mag_comparisons); i++) 2162 { 2163 HOST_WIDE_INT new_rhs; 2164 bool increment = *code == mag_comparisons[i][0]; 2165 bool decrement = *code == mag_comparisons[i][1]; 2166 if (!increment && !decrement) 2167 continue; 2168 2169 new_rhs = rhs + (increment ? 1 : -1); 2170 if (riscv_integer_cost (new_rhs) < riscv_integer_cost (rhs) 2171 && (rhs < 0) == (new_rhs < 0)) 2172 { 2173 *op1 = GEN_INT (new_rhs); 2174 *code = mag_comparisons[i][increment]; 2175 } 2176 break; 2177 } 2178 } 2179 } 2180 2181 riscv_extend_comparands (*code, op0, op1); 2182 2183 *op0 = force_reg (word_mode, *op0); 2184 if (*op1 != const0_rtx) 2185 *op1 = force_reg (word_mode, *op1); 2186 } 2187 2188 /* Like riscv_emit_int_compare, but for floating-point comparisons. */ 2189 2190 static void 2191 riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1) 2192 { 2193 rtx tmp0, tmp1, cmp_op0 = *op0, cmp_op1 = *op1; 2194 enum rtx_code fp_code = *code; 2195 *code = NE; 2196 2197 switch (fp_code) 2198 { 2199 case UNORDERED: 2200 *code = EQ; 2201 /* Fall through. */ 2202 2203 case ORDERED: 2204 /* a == a && b == b */ 2205 tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0); 2206 tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1); 2207 *op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1); 2208 *op1 = const0_rtx; 2209 break; 2210 2211 case UNEQ: 2212 case LTGT: 2213 /* ordered(a, b) > (a == b) */ 2214 *code = fp_code == LTGT ? GTU : EQ; 2215 tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0); 2216 tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1); 2217 *op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1); 2218 *op1 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op1); 2219 break; 2220 2221 #define UNORDERED_COMPARISON(CODE, CMP) \ 2222 case CODE: \ 2223 *code = EQ; \ 2224 *op0 = gen_reg_rtx (word_mode); \ 2225 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \ 2226 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \ 2227 else if (GET_MODE (cmp_op0) == SFmode) \ 2228 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \ 2229 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \ 2230 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \ 2231 else if (GET_MODE (cmp_op0) == DFmode) \ 2232 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \ 2233 else \ 2234 gcc_unreachable (); \ 2235 *op1 = const0_rtx; \ 2236 break; 2237 2238 case UNLT: 2239 std::swap (cmp_op0, cmp_op1); 2240 gcc_fallthrough (); 2241 2242 UNORDERED_COMPARISON(UNGT, le) 2243 2244 case UNLE: 2245 std::swap (cmp_op0, cmp_op1); 2246 gcc_fallthrough (); 2247 2248 UNORDERED_COMPARISON(UNGE, lt) 2249 #undef UNORDERED_COMPARISON 2250 2251 case NE: 2252 fp_code = EQ; 2253 *code = EQ; 2254 /* Fall through. */ 2255 2256 case EQ: 2257 case LE: 2258 case LT: 2259 case GE: 2260 case GT: 2261 /* We have instructions for these cases. */ 2262 *op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1); 2263 *op1 = const0_rtx; 2264 break; 2265 2266 default: 2267 gcc_unreachable (); 2268 } 2269 } 2270 2271 /* CODE-compare OP0 and OP1. Store the result in TARGET. */ 2272 2273 void 2274 riscv_expand_int_scc (rtx target, enum rtx_code code, rtx op0, rtx op1) 2275 { 2276 riscv_extend_comparands (code, &op0, &op1); 2277 op0 = force_reg (word_mode, op0); 2278 2279 if (code == EQ || code == NE) 2280 { 2281 rtx zie = riscv_zero_if_equal (op0, op1); 2282 riscv_emit_binary (code, target, zie, const0_rtx); 2283 } 2284 else 2285 riscv_emit_int_order_test (code, 0, target, op0, op1); 2286 } 2287 2288 /* Like riscv_expand_int_scc, but for floating-point comparisons. */ 2289 2290 void 2291 riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1) 2292 { 2293 riscv_emit_float_compare (&code, &op0, &op1); 2294 2295 rtx cmp = riscv_force_binary (word_mode, code, op0, op1); 2296 riscv_emit_set (target, lowpart_subreg (SImode, cmp, word_mode)); 2297 } 2298 2299 /* Jump to LABEL if (CODE OP0 OP1) holds. */ 2300 2301 void 2302 riscv_expand_conditional_branch (rtx label, rtx_code code, rtx op0, rtx op1) 2303 { 2304 if (FLOAT_MODE_P (GET_MODE (op1))) 2305 riscv_emit_float_compare (&code, &op0, &op1); 2306 else 2307 riscv_emit_int_compare (&code, &op0, &op1); 2308 2309 rtx condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); 2310 emit_jump_insn (gen_condjump (condition, label)); 2311 } 2312 2313 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at 2314 least PARM_BOUNDARY bits of alignment, but will be given anything up 2315 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */ 2316 2317 static unsigned int 2318 riscv_function_arg_boundary (machine_mode mode, const_tree type) 2319 { 2320 unsigned int alignment; 2321 2322 /* Use natural alignment if the type is not aggregate data. */ 2323 if (type && !AGGREGATE_TYPE_P (type)) 2324 alignment = TYPE_ALIGN (TYPE_MAIN_VARIANT (type)); 2325 else 2326 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); 2327 2328 return MIN (PREFERRED_STACK_BOUNDARY, MAX (PARM_BOUNDARY, alignment)); 2329 } 2330 2331 /* If MODE represents an argument that can be passed or returned in 2332 floating-point registers, return the number of registers, else 0. */ 2333 2334 static unsigned 2335 riscv_pass_mode_in_fpr_p (machine_mode mode) 2336 { 2337 if (GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FP_ARG) 2338 { 2339 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 2340 return 1; 2341 2342 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 2343 return 2; 2344 } 2345 2346 return 0; 2347 } 2348 2349 typedef struct { 2350 const_tree type; 2351 HOST_WIDE_INT offset; 2352 } riscv_aggregate_field; 2353 2354 /* Identify subfields of aggregates that are candidates for passing in 2355 floating-point registers. */ 2356 2357 static int 2358 riscv_flatten_aggregate_field (const_tree type, 2359 riscv_aggregate_field fields[2], 2360 int n, HOST_WIDE_INT offset) 2361 { 2362 switch (TREE_CODE (type)) 2363 { 2364 case RECORD_TYPE: 2365 /* Can't handle incomplete types nor sizes that are not fixed. */ 2366 if (!COMPLETE_TYPE_P (type) 2367 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST 2368 || !tree_fits_uhwi_p (TYPE_SIZE (type))) 2369 return -1; 2370 2371 for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f)) 2372 if (TREE_CODE (f) == FIELD_DECL) 2373 { 2374 if (!TYPE_P (TREE_TYPE (f))) 2375 return -1; 2376 2377 HOST_WIDE_INT pos = offset + int_byte_position (f); 2378 n = riscv_flatten_aggregate_field (TREE_TYPE (f), fields, n, pos); 2379 if (n < 0) 2380 return -1; 2381 } 2382 return n; 2383 2384 case ARRAY_TYPE: 2385 { 2386 HOST_WIDE_INT n_elts; 2387 riscv_aggregate_field subfields[2]; 2388 tree index = TYPE_DOMAIN (type); 2389 tree elt_size = TYPE_SIZE_UNIT (TREE_TYPE (type)); 2390 int n_subfields = riscv_flatten_aggregate_field (TREE_TYPE (type), 2391 subfields, 0, offset); 2392 2393 /* Can't handle incomplete types nor sizes that are not fixed. */ 2394 if (n_subfields <= 0 2395 || !COMPLETE_TYPE_P (type) 2396 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST 2397 || !index 2398 || !TYPE_MAX_VALUE (index) 2399 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index)) 2400 || !TYPE_MIN_VALUE (index) 2401 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index)) 2402 || !tree_fits_uhwi_p (elt_size)) 2403 return -1; 2404 2405 n_elts = 1 + tree_to_uhwi (TYPE_MAX_VALUE (index)) 2406 - tree_to_uhwi (TYPE_MIN_VALUE (index)); 2407 gcc_assert (n_elts >= 0); 2408 2409 for (HOST_WIDE_INT i = 0; i < n_elts; i++) 2410 for (int j = 0; j < n_subfields; j++) 2411 { 2412 if (n >= 2) 2413 return -1; 2414 2415 fields[n] = subfields[j]; 2416 fields[n++].offset += i * tree_to_uhwi (elt_size); 2417 } 2418 2419 return n; 2420 } 2421 2422 case COMPLEX_TYPE: 2423 { 2424 /* Complex type need consume 2 field, so n must be 0. */ 2425 if (n != 0) 2426 return -1; 2427 2428 HOST_WIDE_INT elt_size = GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type))); 2429 2430 if (elt_size <= UNITS_PER_FP_ARG) 2431 { 2432 fields[0].type = TREE_TYPE (type); 2433 fields[0].offset = offset; 2434 fields[1].type = TREE_TYPE (type); 2435 fields[1].offset = offset + elt_size; 2436 2437 return 2; 2438 } 2439 2440 return -1; 2441 } 2442 2443 default: 2444 if (n < 2 2445 && ((SCALAR_FLOAT_TYPE_P (type) 2446 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FP_ARG) 2447 || (INTEGRAL_TYPE_P (type) 2448 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_WORD))) 2449 { 2450 fields[n].type = type; 2451 fields[n].offset = offset; 2452 return n + 1; 2453 } 2454 else 2455 return -1; 2456 } 2457 } 2458 2459 /* Identify candidate aggregates for passing in floating-point registers. 2460 Candidates have at most two fields after flattening. */ 2461 2462 static int 2463 riscv_flatten_aggregate_argument (const_tree type, 2464 riscv_aggregate_field fields[2]) 2465 { 2466 if (!type || TREE_CODE (type) != RECORD_TYPE) 2467 return -1; 2468 2469 return riscv_flatten_aggregate_field (type, fields, 0, 0); 2470 } 2471 2472 /* See whether TYPE is a record whose fields should be returned in one or 2473 two floating-point registers. If so, populate FIELDS accordingly. */ 2474 2475 static unsigned 2476 riscv_pass_aggregate_in_fpr_pair_p (const_tree type, 2477 riscv_aggregate_field fields[2]) 2478 { 2479 int n = riscv_flatten_aggregate_argument (type, fields); 2480 2481 for (int i = 0; i < n; i++) 2482 if (!SCALAR_FLOAT_TYPE_P (fields[i].type)) 2483 return 0; 2484 2485 return n > 0 ? n : 0; 2486 } 2487 2488 /* See whether TYPE is a record whose fields should be returned in one or 2489 floating-point register and one integer register. If so, populate 2490 FIELDS accordingly. */ 2491 2492 static bool 2493 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type, 2494 riscv_aggregate_field fields[2]) 2495 { 2496 unsigned num_int = 0, num_float = 0; 2497 int n = riscv_flatten_aggregate_argument (type, fields); 2498 2499 for (int i = 0; i < n; i++) 2500 { 2501 num_float += SCALAR_FLOAT_TYPE_P (fields[i].type); 2502 num_int += INTEGRAL_TYPE_P (fields[i].type); 2503 } 2504 2505 return num_int == 1 && num_float == 1; 2506 } 2507 2508 /* Return the representation of an argument passed or returned in an FPR 2509 when the value has mode VALUE_MODE and the type has TYPE_MODE. The 2510 two modes may be different for structures like: 2511 2512 struct __attribute__((packed)) foo { float f; } 2513 2514 where the SFmode value "f" is passed in REGNO but the struct itself 2515 has mode BLKmode. */ 2516 2517 static rtx 2518 riscv_pass_fpr_single (machine_mode type_mode, unsigned regno, 2519 machine_mode value_mode, 2520 HOST_WIDE_INT offset) 2521 { 2522 rtx x = gen_rtx_REG (value_mode, regno); 2523 2524 if (type_mode != value_mode) 2525 { 2526 x = gen_rtx_EXPR_LIST (VOIDmode, x, GEN_INT (offset)); 2527 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); 2528 } 2529 return x; 2530 } 2531 2532 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1. 2533 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and 2534 byte offset for the first value, likewise MODE2 and OFFSET2 for the 2535 second value. */ 2536 2537 static rtx 2538 riscv_pass_fpr_pair (machine_mode mode, unsigned regno1, 2539 machine_mode mode1, HOST_WIDE_INT offset1, 2540 unsigned regno2, machine_mode mode2, 2541 HOST_WIDE_INT offset2) 2542 { 2543 return gen_rtx_PARALLEL 2544 (mode, 2545 gen_rtvec (2, 2546 gen_rtx_EXPR_LIST (VOIDmode, 2547 gen_rtx_REG (mode1, regno1), 2548 GEN_INT (offset1)), 2549 gen_rtx_EXPR_LIST (VOIDmode, 2550 gen_rtx_REG (mode2, regno2), 2551 GEN_INT (offset2)))); 2552 } 2553 2554 /* Fill INFO with information about a single argument, and return an 2555 RTL pattern to pass or return the argument. CUM is the cumulative 2556 state for earlier arguments. MODE is the mode of this argument and 2557 TYPE is its type (if known). NAMED is true if this is a named 2558 (fixed) argument rather than a variable one. RETURN_P is true if 2559 returning the argument, or false if passing the argument. */ 2560 2561 static rtx 2562 riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, 2563 machine_mode mode, const_tree type, bool named, 2564 bool return_p) 2565 { 2566 unsigned num_bytes, num_words; 2567 unsigned fpr_base = return_p ? FP_RETURN : FP_ARG_FIRST; 2568 unsigned gpr_base = return_p ? GP_RETURN : GP_ARG_FIRST; 2569 unsigned alignment = riscv_function_arg_boundary (mode, type); 2570 2571 memset (info, 0, sizeof (*info)); 2572 info->gpr_offset = cum->num_gprs; 2573 info->fpr_offset = cum->num_fprs; 2574 2575 if (named) 2576 { 2577 riscv_aggregate_field fields[2]; 2578 unsigned fregno = fpr_base + info->fpr_offset; 2579 unsigned gregno = gpr_base + info->gpr_offset; 2580 2581 /* Pass one- or two-element floating-point aggregates in FPRs. */ 2582 if ((info->num_fprs = riscv_pass_aggregate_in_fpr_pair_p (type, fields)) 2583 && info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS) 2584 switch (info->num_fprs) 2585 { 2586 case 1: 2587 return riscv_pass_fpr_single (mode, fregno, 2588 TYPE_MODE (fields[0].type), 2589 fields[0].offset); 2590 2591 case 2: 2592 return riscv_pass_fpr_pair (mode, fregno, 2593 TYPE_MODE (fields[0].type), 2594 fields[0].offset, 2595 fregno + 1, 2596 TYPE_MODE (fields[1].type), 2597 fields[1].offset); 2598 2599 default: 2600 gcc_unreachable (); 2601 } 2602 2603 /* Pass real and complex floating-point numbers in FPRs. */ 2604 if ((info->num_fprs = riscv_pass_mode_in_fpr_p (mode)) 2605 && info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS) 2606 switch (GET_MODE_CLASS (mode)) 2607 { 2608 case MODE_FLOAT: 2609 return gen_rtx_REG (mode, fregno); 2610 2611 case MODE_COMPLEX_FLOAT: 2612 return riscv_pass_fpr_pair (mode, fregno, GET_MODE_INNER (mode), 0, 2613 fregno + 1, GET_MODE_INNER (mode), 2614 GET_MODE_UNIT_SIZE (mode)); 2615 2616 default: 2617 gcc_unreachable (); 2618 } 2619 2620 /* Pass structs with one float and one integer in an FPR and a GPR. */ 2621 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type, fields) 2622 && info->gpr_offset < MAX_ARGS_IN_REGISTERS 2623 && info->fpr_offset < MAX_ARGS_IN_REGISTERS) 2624 { 2625 info->num_gprs = 1; 2626 info->num_fprs = 1; 2627 2628 if (!SCALAR_FLOAT_TYPE_P (fields[0].type)) 2629 std::swap (fregno, gregno); 2630 2631 return riscv_pass_fpr_pair (mode, fregno, TYPE_MODE (fields[0].type), 2632 fields[0].offset, 2633 gregno, TYPE_MODE (fields[1].type), 2634 fields[1].offset); 2635 } 2636 } 2637 2638 /* Work out the size of the argument. */ 2639 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 2640 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 2641 2642 /* Doubleword-aligned varargs start on an even register boundary. */ 2643 if (!named && num_bytes != 0 && alignment > BITS_PER_WORD) 2644 info->gpr_offset += info->gpr_offset & 1; 2645 2646 /* Partition the argument between registers and stack. */ 2647 info->num_fprs = 0; 2648 info->num_gprs = MIN (num_words, MAX_ARGS_IN_REGISTERS - info->gpr_offset); 2649 info->stack_p = (num_words - info->num_gprs) != 0; 2650 2651 if (info->num_gprs || return_p) 2652 return gen_rtx_REG (mode, gpr_base + info->gpr_offset); 2653 2654 return NULL_RTX; 2655 } 2656 2657 /* Implement TARGET_FUNCTION_ARG. */ 2658 2659 static rtx 2660 riscv_function_arg (cumulative_args_t cum_v, machine_mode mode, 2661 const_tree type, bool named) 2662 { 2663 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2664 struct riscv_arg_info info; 2665 2666 if (mode == VOIDmode) 2667 return NULL; 2668 2669 return riscv_get_arg_info (&info, cum, mode, type, named, false); 2670 } 2671 2672 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */ 2673 2674 static void 2675 riscv_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, 2676 const_tree type, bool named) 2677 { 2678 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2679 struct riscv_arg_info info; 2680 2681 riscv_get_arg_info (&info, cum, mode, type, named, false); 2682 2683 /* Advance the register count. This has the effect of setting 2684 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned 2685 argument required us to skip the final GPR and pass the whole 2686 argument on the stack. */ 2687 cum->num_fprs = info.fpr_offset + info.num_fprs; 2688 cum->num_gprs = info.gpr_offset + info.num_gprs; 2689 } 2690 2691 /* Implement TARGET_ARG_PARTIAL_BYTES. */ 2692 2693 static int 2694 riscv_arg_partial_bytes (cumulative_args_t cum, 2695 machine_mode mode, tree type, bool named) 2696 { 2697 struct riscv_arg_info arg; 2698 2699 riscv_get_arg_info (&arg, get_cumulative_args (cum), mode, type, named, false); 2700 return arg.stack_p ? arg.num_gprs * UNITS_PER_WORD : 0; 2701 } 2702 2703 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls, 2704 VALTYPE is the return type and MODE is VOIDmode. For libcalls, 2705 VALTYPE is null and MODE is the mode of the return value. */ 2706 2707 rtx 2708 riscv_function_value (const_tree type, const_tree func, machine_mode mode) 2709 { 2710 struct riscv_arg_info info; 2711 CUMULATIVE_ARGS args; 2712 2713 if (type) 2714 { 2715 int unsigned_p = TYPE_UNSIGNED (type); 2716 2717 mode = TYPE_MODE (type); 2718 2719 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, 2720 return values, promote the mode here too. */ 2721 mode = promote_function_mode (type, mode, &unsigned_p, func, 1); 2722 } 2723 2724 memset (&args, 0, sizeof args); 2725 return riscv_get_arg_info (&info, &args, mode, type, true, true); 2726 } 2727 2728 /* Implement TARGET_PASS_BY_REFERENCE. */ 2729 2730 static bool 2731 riscv_pass_by_reference (cumulative_args_t cum_v, machine_mode mode, 2732 const_tree type, bool named) 2733 { 2734 HOST_WIDE_INT size = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 2735 struct riscv_arg_info info; 2736 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2737 2738 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we 2739 never pass variadic arguments in floating-point registers, so we can 2740 avoid the call to riscv_get_arg_info in this case. */ 2741 if (cum != NULL) 2742 { 2743 /* Don't pass by reference if we can use a floating-point register. */ 2744 riscv_get_arg_info (&info, cum, mode, type, named, false); 2745 if (info.num_fprs) 2746 return false; 2747 } 2748 2749 /* Pass by reference if the data do not fit in two integer registers. */ 2750 return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD); 2751 } 2752 2753 /* Implement TARGET_RETURN_IN_MEMORY. */ 2754 2755 static bool 2756 riscv_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) 2757 { 2758 CUMULATIVE_ARGS args; 2759 cumulative_args_t cum = pack_cumulative_args (&args); 2760 2761 /* The rules for returning in memory are the same as for passing the 2762 first named argument by reference. */ 2763 memset (&args, 0, sizeof args); 2764 return riscv_pass_by_reference (cum, TYPE_MODE (type), type, true); 2765 } 2766 2767 /* Implement TARGET_SETUP_INCOMING_VARARGS. */ 2768 2769 static void 2770 riscv_setup_incoming_varargs (cumulative_args_t cum, machine_mode mode, 2771 tree type, int *pretend_size ATTRIBUTE_UNUSED, 2772 int no_rtl) 2773 { 2774 CUMULATIVE_ARGS local_cum; 2775 int gp_saved; 2776 2777 /* The caller has advanced CUM up to, but not beyond, the last named 2778 argument. Advance a local copy of CUM past the last "real" named 2779 argument, to find out how many registers are left over. */ 2780 local_cum = *get_cumulative_args (cum); 2781 riscv_function_arg_advance (pack_cumulative_args (&local_cum), mode, type, 1); 2782 2783 /* Found out how many registers we need to save. */ 2784 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; 2785 2786 if (!no_rtl && gp_saved > 0) 2787 { 2788 rtx ptr = plus_constant (Pmode, virtual_incoming_args_rtx, 2789 REG_PARM_STACK_SPACE (cfun->decl) 2790 - gp_saved * UNITS_PER_WORD); 2791 rtx mem = gen_frame_mem (BLKmode, ptr); 2792 set_mem_alias_set (mem, get_varargs_alias_set ()); 2793 2794 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, 2795 mem, gp_saved); 2796 } 2797 if (REG_PARM_STACK_SPACE (cfun->decl) == 0) 2798 cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD; 2799 } 2800 2801 /* Handle an attribute requiring a FUNCTION_DECL; 2802 arguments as in struct attribute_spec.handler. */ 2803 static tree 2804 riscv_handle_fndecl_attribute (tree *node, tree name, 2805 tree args ATTRIBUTE_UNUSED, 2806 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) 2807 { 2808 if (TREE_CODE (*node) != FUNCTION_DECL) 2809 { 2810 warning (OPT_Wattributes, "%qE attribute only applies to functions", 2811 name); 2812 *no_add_attrs = true; 2813 } 2814 2815 return NULL_TREE; 2816 } 2817 2818 /* Verify type based attributes. NODE is the what the attribute is being 2819 applied to. NAME is the attribute name. ARGS are the attribute args. 2820 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if 2821 the attribute should be ignored. */ 2822 2823 static tree 2824 riscv_handle_type_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args, 2825 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) 2826 { 2827 /* Check for an argument. */ 2828 if (is_attribute_p ("interrupt", name)) 2829 { 2830 if (args) 2831 { 2832 tree cst = TREE_VALUE (args); 2833 const char *string; 2834 2835 if (TREE_CODE (cst) != STRING_CST) 2836 { 2837 warning (OPT_Wattributes, 2838 "%qE attribute requires a string argument", 2839 name); 2840 *no_add_attrs = true; 2841 return NULL_TREE; 2842 } 2843 2844 string = TREE_STRING_POINTER (cst); 2845 if (strcmp (string, "user") && strcmp (string, "supervisor") 2846 && strcmp (string, "machine")) 2847 { 2848 warning (OPT_Wattributes, 2849 "argument to %qE attribute is not \"user\", \"supervisor\", or \"machine\"", 2850 name); 2851 *no_add_attrs = true; 2852 } 2853 } 2854 } 2855 2856 return NULL_TREE; 2857 } 2858 2859 /* Return true if function TYPE is an interrupt function. */ 2860 static bool 2861 riscv_interrupt_type_p (tree type) 2862 { 2863 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL; 2864 } 2865 2866 /* Return true if FUNC is a naked function. */ 2867 static bool 2868 riscv_naked_function_p (tree func) 2869 { 2870 tree func_decl = func; 2871 if (func == NULL_TREE) 2872 func_decl = current_function_decl; 2873 return NULL_TREE != lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl)); 2874 } 2875 2876 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */ 2877 static bool 2878 riscv_allocate_stack_slots_for_args () 2879 { 2880 /* Naked functions should not allocate stack slots for arguments. */ 2881 return !riscv_naked_function_p (current_function_decl); 2882 } 2883 2884 /* Implement TARGET_WARN_FUNC_RETURN. */ 2885 static bool 2886 riscv_warn_func_return (tree decl) 2887 { 2888 /* Naked functions are implemented entirely in assembly, including the 2889 return sequence, so suppress warnings about this. */ 2890 return !riscv_naked_function_p (decl); 2891 } 2892 2893 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ 2894 2895 static void 2896 riscv_va_start (tree valist, rtx nextarg) 2897 { 2898 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size); 2899 std_expand_builtin_va_start (valist, nextarg); 2900 } 2901 2902 /* Make ADDR suitable for use as a call or sibcall target. */ 2903 2904 rtx 2905 riscv_legitimize_call_address (rtx addr) 2906 { 2907 if (!call_insn_operand (addr, VOIDmode)) 2908 { 2909 rtx reg = RISCV_PROLOGUE_TEMP (Pmode); 2910 riscv_emit_move (reg, addr); 2911 return reg; 2912 } 2913 return addr; 2914 } 2915 2916 /* Emit straight-line code to move LENGTH bytes from SRC to DEST. 2917 Assume that the areas do not overlap. */ 2918 2919 static void 2920 riscv_block_move_straight (rtx dest, rtx src, HOST_WIDE_INT length) 2921 { 2922 HOST_WIDE_INT offset, delta; 2923 unsigned HOST_WIDE_INT bits; 2924 int i; 2925 enum machine_mode mode; 2926 rtx *regs; 2927 2928 bits = MAX (BITS_PER_UNIT, 2929 MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest)))); 2930 2931 mode = mode_for_size (bits, MODE_INT, 0).require (); 2932 delta = bits / BITS_PER_UNIT; 2933 2934 /* Allocate a buffer for the temporary registers. */ 2935 regs = XALLOCAVEC (rtx, length / delta); 2936 2937 /* Load as many BITS-sized chunks as possible. Use a normal load if 2938 the source has enough alignment, otherwise use left/right pairs. */ 2939 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 2940 { 2941 regs[i] = gen_reg_rtx (mode); 2942 riscv_emit_move (regs[i], adjust_address (src, mode, offset)); 2943 } 2944 2945 /* Copy the chunks to the destination. */ 2946 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 2947 riscv_emit_move (adjust_address (dest, mode, offset), regs[i]); 2948 2949 /* Mop up any left-over bytes. */ 2950 if (offset < length) 2951 { 2952 src = adjust_address (src, BLKmode, offset); 2953 dest = adjust_address (dest, BLKmode, offset); 2954 move_by_pieces (dest, src, length - offset, 2955 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), RETURN_BEGIN); 2956 } 2957 } 2958 2959 /* Helper function for doing a loop-based block operation on memory 2960 reference MEM. Each iteration of the loop will operate on LENGTH 2961 bytes of MEM. 2962 2963 Create a new base register for use within the loop and point it to 2964 the start of MEM. Create a new memory reference that uses this 2965 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ 2966 2967 static void 2968 riscv_adjust_block_mem (rtx mem, HOST_WIDE_INT length, 2969 rtx *loop_reg, rtx *loop_mem) 2970 { 2971 *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); 2972 2973 /* Although the new mem does not refer to a known location, 2974 it does keep up to LENGTH bytes of alignment. */ 2975 *loop_mem = change_address (mem, BLKmode, *loop_reg); 2976 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); 2977 } 2978 2979 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER 2980 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that 2981 the memory regions do not overlap. */ 2982 2983 static void 2984 riscv_block_move_loop (rtx dest, rtx src, HOST_WIDE_INT length, 2985 HOST_WIDE_INT bytes_per_iter) 2986 { 2987 rtx label, src_reg, dest_reg, final_src, test; 2988 HOST_WIDE_INT leftover; 2989 2990 leftover = length % bytes_per_iter; 2991 length -= leftover; 2992 2993 /* Create registers and memory references for use within the loop. */ 2994 riscv_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); 2995 riscv_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); 2996 2997 /* Calculate the value that SRC_REG should have after the last iteration 2998 of the loop. */ 2999 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), 3000 0, 0, OPTAB_WIDEN); 3001 3002 /* Emit the start of the loop. */ 3003 label = gen_label_rtx (); 3004 emit_label (label); 3005 3006 /* Emit the loop body. */ 3007 riscv_block_move_straight (dest, src, bytes_per_iter); 3008 3009 /* Move on to the next block. */ 3010 riscv_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter)); 3011 riscv_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter)); 3012 3013 /* Emit the loop condition. */ 3014 test = gen_rtx_NE (VOIDmode, src_reg, final_src); 3015 if (Pmode == DImode) 3016 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label)); 3017 else 3018 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); 3019 3020 /* Mop up any left-over bytes. */ 3021 if (leftover) 3022 riscv_block_move_straight (dest, src, leftover); 3023 else 3024 emit_insn(gen_nop ()); 3025 } 3026 3027 /* Expand a movmemsi instruction, which copies LENGTH bytes from 3028 memory reference SRC to memory reference DEST. */ 3029 3030 bool 3031 riscv_expand_block_move (rtx dest, rtx src, rtx length) 3032 { 3033 if (CONST_INT_P (length)) 3034 { 3035 HOST_WIDE_INT factor, align; 3036 3037 align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD); 3038 factor = BITS_PER_WORD / align; 3039 3040 if (optimize_function_for_size_p (cfun) 3041 && INTVAL (length) * factor * UNITS_PER_WORD > MOVE_RATIO (false)) 3042 return false; 3043 3044 if (INTVAL (length) <= RISCV_MAX_MOVE_BYTES_STRAIGHT / factor) 3045 { 3046 riscv_block_move_straight (dest, src, INTVAL (length)); 3047 return true; 3048 } 3049 else if (optimize && align >= BITS_PER_WORD) 3050 { 3051 unsigned min_iter_words 3052 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD; 3053 unsigned iter_words = min_iter_words; 3054 HOST_WIDE_INT bytes = INTVAL (length), words = bytes / UNITS_PER_WORD; 3055 3056 /* Lengthen the loop body if it shortens the tail. */ 3057 for (unsigned i = min_iter_words; i < min_iter_words * 2 - 1; i++) 3058 { 3059 unsigned cur_cost = iter_words + words % iter_words; 3060 unsigned new_cost = i + words % i; 3061 if (new_cost <= cur_cost) 3062 iter_words = i; 3063 } 3064 3065 riscv_block_move_loop (dest, src, bytes, iter_words * UNITS_PER_WORD); 3066 return true; 3067 } 3068 } 3069 return false; 3070 } 3071 3072 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM 3073 in context CONTEXT. HI_RELOC indicates a high-part reloc. */ 3074 3075 static void 3076 riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) 3077 { 3078 const char *reloc; 3079 3080 switch (riscv_classify_symbolic_expression (op)) 3081 { 3082 case SYMBOL_ABSOLUTE: 3083 reloc = hi_reloc ? "%hi" : "%lo"; 3084 break; 3085 3086 case SYMBOL_PCREL: 3087 reloc = hi_reloc ? "%pcrel_hi" : "%pcrel_lo"; 3088 break; 3089 3090 case SYMBOL_TLS_LE: 3091 reloc = hi_reloc ? "%tprel_hi" : "%tprel_lo"; 3092 break; 3093 3094 default: 3095 output_operand_lossage ("invalid use of '%%%c'", hi_reloc ? 'h' : 'R'); 3096 return; 3097 } 3098 3099 fprintf (file, "%s(", reloc); 3100 output_addr_const (file, riscv_strip_unspec_address (op)); 3101 fputc (')', file); 3102 } 3103 3104 /* Return true if the .AQ suffix should be added to an AMO to implement the 3105 acquire portion of memory model MODEL. */ 3106 3107 static bool 3108 riscv_memmodel_needs_amo_acquire (enum memmodel model) 3109 { 3110 switch (model) 3111 { 3112 case MEMMODEL_ACQ_REL: 3113 case MEMMODEL_SEQ_CST: 3114 case MEMMODEL_SYNC_SEQ_CST: 3115 case MEMMODEL_ACQUIRE: 3116 case MEMMODEL_CONSUME: 3117 case MEMMODEL_SYNC_ACQUIRE: 3118 return true; 3119 3120 case MEMMODEL_RELEASE: 3121 case MEMMODEL_SYNC_RELEASE: 3122 case MEMMODEL_RELAXED: 3123 return false; 3124 3125 default: 3126 gcc_unreachable (); 3127 } 3128 } 3129 3130 /* Return true if a FENCE should be emitted to before a memory access to 3131 implement the release portion of memory model MODEL. */ 3132 3133 static bool 3134 riscv_memmodel_needs_release_fence (enum memmodel model) 3135 { 3136 switch (model) 3137 { 3138 case MEMMODEL_ACQ_REL: 3139 case MEMMODEL_SEQ_CST: 3140 case MEMMODEL_SYNC_SEQ_CST: 3141 case MEMMODEL_RELEASE: 3142 case MEMMODEL_SYNC_RELEASE: 3143 return true; 3144 3145 case MEMMODEL_ACQUIRE: 3146 case MEMMODEL_CONSUME: 3147 case MEMMODEL_SYNC_ACQUIRE: 3148 case MEMMODEL_RELAXED: 3149 return false; 3150 3151 default: 3152 gcc_unreachable (); 3153 } 3154 } 3155 3156 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 3157 3158 'h' Print the high-part relocation associated with OP, after stripping 3159 any outermost HIGH. 3160 'R' Print the low-part relocation associated with OP. 3161 'C' Print the integer branch condition for comparison OP. 3162 'A' Print the atomic operation suffix for memory model OP. 3163 'F' Print a FENCE if the memory model requires a release. 3164 'z' Print x0 if OP is zero, otherwise print OP normally. 3165 'i' Print i if the operand is not a register. */ 3166 3167 static void 3168 riscv_print_operand (FILE *file, rtx op, int letter) 3169 { 3170 machine_mode mode = GET_MODE (op); 3171 enum rtx_code code = GET_CODE (op); 3172 3173 switch (letter) 3174 { 3175 case 'h': 3176 if (code == HIGH) 3177 op = XEXP (op, 0); 3178 riscv_print_operand_reloc (file, op, true); 3179 break; 3180 3181 case 'R': 3182 riscv_print_operand_reloc (file, op, false); 3183 break; 3184 3185 case 'C': 3186 /* The RTL names match the instruction names. */ 3187 fputs (GET_RTX_NAME (code), file); 3188 break; 3189 3190 case 'A': 3191 if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) 3192 fputs (".aq", file); 3193 break; 3194 3195 case 'F': 3196 if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) 3197 fputs ("fence iorw,ow; ", file); 3198 break; 3199 3200 case 'i': 3201 if (code != REG) 3202 fputs ("i", file); 3203 break; 3204 3205 default: 3206 switch (code) 3207 { 3208 case REG: 3209 if (letter && letter != 'z') 3210 output_operand_lossage ("invalid use of '%%%c'", letter); 3211 fprintf (file, "%s", reg_names[REGNO (op)]); 3212 break; 3213 3214 case MEM: 3215 if (letter && letter != 'z') 3216 output_operand_lossage ("invalid use of '%%%c'", letter); 3217 else 3218 output_address (mode, XEXP (op, 0)); 3219 break; 3220 3221 default: 3222 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) 3223 fputs (reg_names[GP_REG_FIRST], file); 3224 else if (letter && letter != 'z') 3225 output_operand_lossage ("invalid use of '%%%c'", letter); 3226 else 3227 output_addr_const (file, riscv_strip_unspec_address (op)); 3228 break; 3229 } 3230 } 3231 } 3232 3233 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ 3234 3235 static void 3236 riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx x) 3237 { 3238 struct riscv_address_info addr; 3239 3240 if (riscv_classify_address (&addr, x, word_mode, true)) 3241 switch (addr.type) 3242 { 3243 case ADDRESS_REG: 3244 riscv_print_operand (file, addr.offset, 0); 3245 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 3246 return; 3247 3248 case ADDRESS_LO_SUM: 3249 riscv_print_operand_reloc (file, addr.offset, false); 3250 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 3251 return; 3252 3253 case ADDRESS_CONST_INT: 3254 output_addr_const (file, x); 3255 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); 3256 return; 3257 3258 case ADDRESS_SYMBOLIC: 3259 output_addr_const (file, riscv_strip_unspec_address (x)); 3260 return; 3261 } 3262 gcc_unreachable (); 3263 } 3264 3265 static bool 3266 riscv_size_ok_for_small_data_p (int size) 3267 { 3268 return g_switch_value && IN_RANGE (size, 1, g_switch_value); 3269 } 3270 3271 /* Return true if EXP should be placed in the small data section. */ 3272 3273 static bool 3274 riscv_in_small_data_p (const_tree x) 3275 { 3276 if (TREE_CODE (x) == STRING_CST || TREE_CODE (x) == FUNCTION_DECL) 3277 return false; 3278 3279 if (TREE_CODE (x) == VAR_DECL && DECL_SECTION_NAME (x)) 3280 { 3281 const char *sec = DECL_SECTION_NAME (x); 3282 return strcmp (sec, ".sdata") == 0 || strcmp (sec, ".sbss") == 0; 3283 } 3284 3285 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x))); 3286 } 3287 3288 /* Switch to the appropriate section for output of DECL. */ 3289 3290 static section * 3291 riscv_select_section (tree decl, int reloc, 3292 unsigned HOST_WIDE_INT align) 3293 { 3294 switch (categorize_decl_for_section (decl, reloc)) 3295 { 3296 case SECCAT_SRODATA: 3297 return get_named_section (decl, ".srodata", reloc); 3298 3299 default: 3300 return default_elf_select_section (decl, reloc, align); 3301 } 3302 } 3303 3304 /* Return a section for X, handling small data. */ 3305 3306 static section * 3307 riscv_elf_select_rtx_section (machine_mode mode, rtx x, 3308 unsigned HOST_WIDE_INT align) 3309 { 3310 section *s = default_elf_select_rtx_section (mode, x, align); 3311 3312 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode))) 3313 { 3314 if (strncmp (s->named.name, ".rodata.cst", strlen (".rodata.cst")) == 0) 3315 { 3316 /* Rename .rodata.cst* to .srodata.cst*. */ 3317 char *name = (char *) alloca (strlen (s->named.name) + 2); 3318 sprintf (name, ".s%s", s->named.name + 1); 3319 return get_section (name, s->named.common.flags, NULL); 3320 } 3321 3322 if (s == data_section) 3323 return sdata_section; 3324 } 3325 3326 return s; 3327 } 3328 3329 /* Make the last instruction frame-related and note that it performs 3330 the operation described by FRAME_PATTERN. */ 3331 3332 static void 3333 riscv_set_frame_expr (rtx frame_pattern) 3334 { 3335 rtx insn; 3336 3337 insn = get_last_insn (); 3338 RTX_FRAME_RELATED_P (insn) = 1; 3339 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, 3340 frame_pattern, 3341 REG_NOTES (insn)); 3342 } 3343 3344 /* Return a frame-related rtx that stores REG at MEM. 3345 REG must be a single register. */ 3346 3347 static rtx 3348 riscv_frame_set (rtx mem, rtx reg) 3349 { 3350 rtx set = gen_rtx_SET (mem, reg); 3351 RTX_FRAME_RELATED_P (set) = 1; 3352 return set; 3353 } 3354 3355 /* Return true if the current function must save register REGNO. */ 3356 3357 static bool 3358 riscv_save_reg_p (unsigned int regno) 3359 { 3360 bool call_saved = !global_regs[regno] && !call_used_regs[regno]; 3361 bool might_clobber = crtl->saves_all_registers 3362 || df_regs_ever_live_p (regno); 3363 3364 if (call_saved && might_clobber) 3365 return true; 3366 3367 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) 3368 return true; 3369 3370 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return) 3371 return true; 3372 3373 /* If this is an interrupt handler, then must save extra registers. */ 3374 if (cfun->machine->interrupt_handler_p) 3375 { 3376 /* zero register is always zero. */ 3377 if (regno == GP_REG_FIRST) 3378 return false; 3379 3380 /* The function will return the stack pointer to its original value. */ 3381 if (regno == STACK_POINTER_REGNUM) 3382 return false; 3383 3384 /* By convention, we assume that gp and tp are safe. */ 3385 if (regno == GP_REGNUM || regno == THREAD_POINTER_REGNUM) 3386 return false; 3387 3388 /* We must save every register used in this function. If this is not a 3389 leaf function, then we must save all temporary registers. */ 3390 if (df_regs_ever_live_p (regno) 3391 || (!crtl->is_leaf && call_used_regs[regno])) 3392 return true; 3393 } 3394 3395 return false; 3396 } 3397 3398 /* Determine whether to call GPR save/restore routines. */ 3399 static bool 3400 riscv_use_save_libcall (const struct riscv_frame_info *frame) 3401 { 3402 if (!TARGET_SAVE_RESTORE || crtl->calls_eh_return || frame_pointer_needed 3403 || cfun->machine->interrupt_handler_p) 3404 return false; 3405 3406 return frame->save_libcall_adjustment != 0; 3407 } 3408 3409 /* Determine which GPR save/restore routine to call. */ 3410 3411 static unsigned 3412 riscv_save_libcall_count (unsigned mask) 3413 { 3414 for (unsigned n = GP_REG_LAST; n > GP_REG_FIRST; n--) 3415 if (BITSET_P (mask, n)) 3416 return CALLEE_SAVED_REG_NUMBER (n) + 1; 3417 abort (); 3418 } 3419 3420 /* Populate the current function's riscv_frame_info structure. 3421 3422 RISC-V stack frames grown downward. High addresses are at the top. 3423 3424 +-------------------------------+ 3425 | | 3426 | incoming stack arguments | 3427 | | 3428 +-------------------------------+ <-- incoming stack pointer 3429 | | 3430 | callee-allocated save area | 3431 | for arguments that are | 3432 | split between registers and | 3433 | the stack | 3434 | | 3435 +-------------------------------+ <-- arg_pointer_rtx 3436 | | 3437 | callee-allocated save area | 3438 | for register varargs | 3439 | | 3440 +-------------------------------+ <-- hard_frame_pointer_rtx; 3441 | | stack_pointer_rtx + gp_sp_offset 3442 | GPR save area | + UNITS_PER_WORD 3443 | | 3444 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset 3445 | | + UNITS_PER_HWVALUE 3446 | FPR save area | 3447 | | 3448 +-------------------------------+ <-- frame_pointer_rtx (virtual) 3449 | | 3450 | local variables | 3451 | | 3452 P +-------------------------------+ 3453 | | 3454 | outgoing stack arguments | 3455 | | 3456 +-------------------------------+ <-- stack_pointer_rtx 3457 3458 Dynamic stack allocations such as alloca insert data at point P. 3459 They decrease stack_pointer_rtx but leave frame_pointer_rtx and 3460 hard_frame_pointer_rtx unchanged. */ 3461 3462 static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame); 3463 3464 static void 3465 riscv_compute_frame_info (void) 3466 { 3467 struct riscv_frame_info *frame; 3468 HOST_WIDE_INT offset; 3469 bool interrupt_save_t1 = false; 3470 unsigned int regno, i, num_x_saved = 0, num_f_saved = 0; 3471 3472 frame = &cfun->machine->frame; 3473 3474 /* In an interrupt function, if we have a large frame, then we need to 3475 save/restore t1. We check for this before clearing the frame struct. */ 3476 if (cfun->machine->interrupt_handler_p) 3477 { 3478 HOST_WIDE_INT step1 = riscv_first_stack_step (frame); 3479 if (! SMALL_OPERAND (frame->total_size - step1)) 3480 interrupt_save_t1 = true; 3481 } 3482 3483 memset (frame, 0, sizeof (*frame)); 3484 3485 if (!cfun->machine->naked_p) 3486 { 3487 /* Find out which GPRs we need to save. */ 3488 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 3489 if (riscv_save_reg_p (regno) 3490 || (interrupt_save_t1 && (regno == T1_REGNUM))) 3491 frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++; 3492 3493 /* If this function calls eh_return, we must also save and restore the 3494 EH data registers. */ 3495 if (crtl->calls_eh_return) 3496 for (i = 0; (regno = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++) 3497 frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++; 3498 3499 /* Find out which FPRs we need to save. This loop must iterate over 3500 the same space as its companion in riscv_for_each_saved_reg. */ 3501 if (TARGET_HARD_FLOAT) 3502 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 3503 if (riscv_save_reg_p (regno)) 3504 frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++; 3505 } 3506 3507 /* At the bottom of the frame are any outgoing stack arguments. */ 3508 offset = RISCV_STACK_ALIGN (crtl->outgoing_args_size); 3509 /* Next are local stack variables. */ 3510 offset += RISCV_STACK_ALIGN (get_frame_size ()); 3511 /* The virtual frame pointer points above the local variables. */ 3512 frame->frame_pointer_offset = offset; 3513 /* Next are the callee-saved FPRs. */ 3514 if (frame->fmask) 3515 offset += RISCV_STACK_ALIGN (num_f_saved * UNITS_PER_FP_REG); 3516 frame->fp_sp_offset = offset - UNITS_PER_FP_REG; 3517 /* Next are the callee-saved GPRs. */ 3518 if (frame->mask) 3519 { 3520 unsigned x_save_size = RISCV_STACK_ALIGN (num_x_saved * UNITS_PER_WORD); 3521 unsigned num_save_restore = 1 + riscv_save_libcall_count (frame->mask); 3522 3523 /* Only use save/restore routines if they don't alter the stack size. */ 3524 if (RISCV_STACK_ALIGN (num_save_restore * UNITS_PER_WORD) == x_save_size) 3525 { 3526 /* Libcall saves/restores 3 registers at once, so we need to 3527 allocate 12 bytes for callee-saved register. */ 3528 if (TARGET_RVE) 3529 x_save_size = 3 * UNITS_PER_WORD; 3530 3531 frame->save_libcall_adjustment = x_save_size; 3532 } 3533 3534 offset += x_save_size; 3535 } 3536 frame->gp_sp_offset = offset - UNITS_PER_WORD; 3537 /* The hard frame pointer points above the callee-saved GPRs. */ 3538 frame->hard_frame_pointer_offset = offset; 3539 /* Above the hard frame pointer is the callee-allocated varags save area. */ 3540 offset += RISCV_STACK_ALIGN (cfun->machine->varargs_size); 3541 /* Next is the callee-allocated area for pretend stack arguments. */ 3542 offset += RISCV_STACK_ALIGN (crtl->args.pretend_args_size); 3543 /* Arg pointer must be below pretend args, but must be above alignment 3544 padding. */ 3545 frame->arg_pointer_offset = offset - crtl->args.pretend_args_size; 3546 frame->total_size = offset; 3547 /* Next points the incoming stack pointer and any incoming arguments. */ 3548 3549 /* Only use save/restore routines when the GPRs are atop the frame. */ 3550 if (frame->hard_frame_pointer_offset != frame->total_size) 3551 frame->save_libcall_adjustment = 0; 3552 } 3553 3554 /* Make sure that we're not trying to eliminate to the wrong hard frame 3555 pointer. */ 3556 3557 static bool 3558 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 3559 { 3560 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); 3561 } 3562 3563 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer 3564 or argument pointer. TO is either the stack pointer or hard frame 3565 pointer. */ 3566 3567 HOST_WIDE_INT 3568 riscv_initial_elimination_offset (int from, int to) 3569 { 3570 HOST_WIDE_INT src, dest; 3571 3572 riscv_compute_frame_info (); 3573 3574 if (to == HARD_FRAME_POINTER_REGNUM) 3575 dest = cfun->machine->frame.hard_frame_pointer_offset; 3576 else if (to == STACK_POINTER_REGNUM) 3577 dest = 0; /* The stack pointer is the base of all offsets, hence 0. */ 3578 else 3579 gcc_unreachable (); 3580 3581 if (from == FRAME_POINTER_REGNUM) 3582 src = cfun->machine->frame.frame_pointer_offset; 3583 else if (from == ARG_POINTER_REGNUM) 3584 src = cfun->machine->frame.arg_pointer_offset; 3585 else 3586 gcc_unreachable (); 3587 3588 return src - dest; 3589 } 3590 3591 /* Implement RETURN_ADDR_RTX. We do not support moving back to a 3592 previous frame. */ 3593 3594 rtx 3595 riscv_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) 3596 { 3597 if (count != 0) 3598 return const0_rtx; 3599 3600 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); 3601 } 3602 3603 /* Emit code to change the current function's return address to 3604 ADDRESS. SCRATCH is available as a scratch register, if needed. 3605 ADDRESS and SCRATCH are both word-mode GPRs. */ 3606 3607 void 3608 riscv_set_return_address (rtx address, rtx scratch) 3609 { 3610 rtx slot_address; 3611 3612 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); 3613 slot_address = riscv_add_offset (scratch, stack_pointer_rtx, 3614 cfun->machine->frame.gp_sp_offset); 3615 riscv_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); 3616 } 3617 3618 /* A function to save or store a register. The first argument is the 3619 register and the second is the stack slot. */ 3620 typedef void (*riscv_save_restore_fn) (rtx, rtx); 3621 3622 /* Use FN to save or restore register REGNO. MODE is the register's 3623 mode and OFFSET is the offset of its save slot from the current 3624 stack pointer. */ 3625 3626 static void 3627 riscv_save_restore_reg (machine_mode mode, int regno, 3628 HOST_WIDE_INT offset, riscv_save_restore_fn fn) 3629 { 3630 rtx mem; 3631 3632 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, offset)); 3633 fn (gen_rtx_REG (mode, regno), mem); 3634 } 3635 3636 /* Call FN for each register that is saved by the current function. 3637 SP_OFFSET is the offset of the current stack pointer from the start 3638 of the frame. */ 3639 3640 static void 3641 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn, 3642 bool epilogue, bool maybe_eh_return) 3643 { 3644 HOST_WIDE_INT offset; 3645 3646 /* Save the link register and s-registers. */ 3647 offset = cfun->machine->frame.gp_sp_offset - sp_offset; 3648 for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 3649 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 3650 { 3651 bool handle_reg = TRUE; 3652 3653 /* If this is a normal return in a function that calls the eh_return 3654 builtin, then do not restore the eh return data registers as that 3655 would clobber the return value. But we do still need to save them 3656 in the prologue, and restore them for an exception return, so we 3657 need special handling here. */ 3658 if (epilogue && !maybe_eh_return && crtl->calls_eh_return) 3659 { 3660 unsigned int i, regnum; 3661 3662 for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; 3663 i++) 3664 if (regno == regnum) 3665 { 3666 handle_reg = FALSE; 3667 break; 3668 } 3669 } 3670 3671 if (handle_reg) 3672 riscv_save_restore_reg (word_mode, regno, offset, fn); 3673 offset -= UNITS_PER_WORD; 3674 } 3675 3676 /* This loop must iterate over the same space as its companion in 3677 riscv_compute_frame_info. */ 3678 offset = cfun->machine->frame.fp_sp_offset - sp_offset; 3679 for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 3680 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) 3681 { 3682 machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode; 3683 3684 riscv_save_restore_reg (mode, regno, offset, fn); 3685 offset -= GET_MODE_SIZE (mode); 3686 } 3687 } 3688 3689 /* Save register REG to MEM. Make the instruction frame-related. */ 3690 3691 static void 3692 riscv_save_reg (rtx reg, rtx mem) 3693 { 3694 riscv_emit_move (mem, reg); 3695 riscv_set_frame_expr (riscv_frame_set (mem, reg)); 3696 } 3697 3698 /* Restore register REG from MEM. */ 3699 3700 static void 3701 riscv_restore_reg (rtx reg, rtx mem) 3702 { 3703 rtx insn = riscv_emit_move (reg, mem); 3704 rtx dwarf = NULL_RTX; 3705 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 3706 3707 if (epilogue_cfa_sp_offset && REGNO (reg) == HARD_FRAME_POINTER_REGNUM) 3708 { 3709 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 3710 GEN_INT (epilogue_cfa_sp_offset)); 3711 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 3712 } 3713 3714 REG_NOTES (insn) = dwarf; 3715 RTX_FRAME_RELATED_P (insn) = 1; 3716 } 3717 3718 /* Return the code to invoke the GPR save routine. */ 3719 3720 const char * 3721 riscv_output_gpr_save (unsigned mask) 3722 { 3723 static char s[32]; 3724 unsigned n = riscv_save_libcall_count (mask); 3725 3726 ssize_t bytes = snprintf (s, sizeof (s), "call\tt0,__riscv_save_%u", n); 3727 gcc_assert ((size_t) bytes < sizeof (s)); 3728 3729 return s; 3730 } 3731 3732 /* For stack frames that can't be allocated with a single ADDI instruction, 3733 compute the best value to initially allocate. It must at a minimum 3734 allocate enough space to spill the callee-saved registers. If TARGET_RVC, 3735 try to pick a value that will allow compression of the register saves 3736 without adding extra instructions. */ 3737 3738 static HOST_WIDE_INT 3739 riscv_first_stack_step (struct riscv_frame_info *frame) 3740 { 3741 if (SMALL_OPERAND (frame->total_size)) 3742 return frame->total_size; 3743 3744 HOST_WIDE_INT min_first_step = 3745 RISCV_STACK_ALIGN (frame->total_size - frame->fp_sp_offset); 3746 HOST_WIDE_INT max_first_step = IMM_REACH / 2 - PREFERRED_STACK_BOUNDARY / 8; 3747 HOST_WIDE_INT min_second_step = frame->total_size - max_first_step; 3748 gcc_assert (min_first_step <= max_first_step); 3749 3750 /* As an optimization, use the least-significant bits of the total frame 3751 size, so that the second adjustment step is just LUI + ADD. */ 3752 if (!SMALL_OPERAND (min_second_step) 3753 && frame->total_size % IMM_REACH < IMM_REACH / 2 3754 && frame->total_size % IMM_REACH >= min_first_step) 3755 return frame->total_size % IMM_REACH; 3756 3757 if (TARGET_RVC) 3758 { 3759 /* If we need two subtracts, and one is small enough to allow compressed 3760 loads and stores, then put that one first. */ 3761 if (IN_RANGE (min_second_step, 0, 3762 (TARGET_64BIT ? SDSP_REACH : SWSP_REACH))) 3763 return MAX (min_second_step, min_first_step); 3764 3765 /* If we need LUI + ADDI + ADD for the second adjustment step, then start 3766 with the minimum first step, so that we can get compressed loads and 3767 stores. */ 3768 else if (!SMALL_OPERAND (min_second_step)) 3769 return min_first_step; 3770 } 3771 3772 return max_first_step; 3773 } 3774 3775 static rtx 3776 riscv_adjust_libcall_cfi_prologue () 3777 { 3778 rtx dwarf = NULL_RTX; 3779 rtx adjust_sp_rtx, reg, mem, insn; 3780 int saved_size = cfun->machine->frame.save_libcall_adjustment; 3781 int offset; 3782 3783 for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 3784 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 3785 { 3786 /* The save order is ra, s0, s1, s2 to s11. */ 3787 if (regno == RETURN_ADDR_REGNUM) 3788 offset = saved_size - UNITS_PER_WORD; 3789 else if (regno == S0_REGNUM) 3790 offset = saved_size - UNITS_PER_WORD * 2; 3791 else if (regno == S1_REGNUM) 3792 offset = saved_size - UNITS_PER_WORD * 3; 3793 else 3794 offset = saved_size - ((regno - S2_REGNUM + 4) * UNITS_PER_WORD); 3795 3796 reg = gen_rtx_REG (SImode, regno); 3797 mem = gen_frame_mem (SImode, plus_constant (Pmode, 3798 stack_pointer_rtx, 3799 offset)); 3800 3801 insn = gen_rtx_SET (mem, reg); 3802 dwarf = alloc_reg_note (REG_CFA_OFFSET, insn, dwarf); 3803 } 3804 3805 /* Debug info for adjust sp. */ 3806 adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, 3807 stack_pointer_rtx, GEN_INT (-saved_size)); 3808 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, 3809 dwarf); 3810 return dwarf; 3811 } 3812 3813 static void 3814 riscv_emit_stack_tie (void) 3815 { 3816 if (Pmode == SImode) 3817 emit_insn (gen_stack_tiesi (stack_pointer_rtx, hard_frame_pointer_rtx)); 3818 else 3819 emit_insn (gen_stack_tiedi (stack_pointer_rtx, hard_frame_pointer_rtx)); 3820 } 3821 3822 /* Expand the "prologue" pattern. */ 3823 3824 void 3825 riscv_expand_prologue (void) 3826 { 3827 struct riscv_frame_info *frame = &cfun->machine->frame; 3828 HOST_WIDE_INT size = frame->total_size; 3829 unsigned mask = frame->mask; 3830 rtx insn; 3831 3832 if (flag_stack_usage_info) 3833 current_function_static_stack_size = size; 3834 3835 if (cfun->machine->naked_p) 3836 return; 3837 3838 /* When optimizing for size, call a subroutine to save the registers. */ 3839 if (riscv_use_save_libcall (frame)) 3840 { 3841 rtx dwarf = NULL_RTX; 3842 dwarf = riscv_adjust_libcall_cfi_prologue (); 3843 3844 frame->mask = 0; /* Temporarily fib that we need not save GPRs. */ 3845 size -= frame->save_libcall_adjustment; 3846 insn = emit_insn (gen_gpr_save (GEN_INT (mask))); 3847 3848 RTX_FRAME_RELATED_P (insn) = 1; 3849 REG_NOTES (insn) = dwarf; 3850 } 3851 3852 /* Save the registers. */ 3853 if ((frame->mask | frame->fmask) != 0) 3854 { 3855 HOST_WIDE_INT step1 = MIN (size, riscv_first_stack_step (frame)); 3856 3857 insn = gen_add3_insn (stack_pointer_rtx, 3858 stack_pointer_rtx, 3859 GEN_INT (-step1)); 3860 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 3861 size -= step1; 3862 riscv_for_each_saved_reg (size, riscv_save_reg, false, false); 3863 } 3864 3865 frame->mask = mask; /* Undo the above fib. */ 3866 3867 /* Set up the frame pointer, if we're using one. */ 3868 if (frame_pointer_needed) 3869 { 3870 insn = gen_add3_insn (hard_frame_pointer_rtx, stack_pointer_rtx, 3871 GEN_INT (frame->hard_frame_pointer_offset - size)); 3872 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 3873 3874 riscv_emit_stack_tie (); 3875 } 3876 3877 /* Allocate the rest of the frame. */ 3878 if (size > 0) 3879 { 3880 if (SMALL_OPERAND (-size)) 3881 { 3882 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 3883 GEN_INT (-size)); 3884 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 3885 } 3886 else 3887 { 3888 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-size)); 3889 emit_insn (gen_add3_insn (stack_pointer_rtx, 3890 stack_pointer_rtx, 3891 RISCV_PROLOGUE_TEMP (Pmode))); 3892 3893 /* Describe the effect of the previous instructions. */ 3894 insn = plus_constant (Pmode, stack_pointer_rtx, -size); 3895 insn = gen_rtx_SET (stack_pointer_rtx, insn); 3896 riscv_set_frame_expr (insn); 3897 } 3898 } 3899 } 3900 3901 static rtx 3902 riscv_adjust_libcall_cfi_epilogue () 3903 { 3904 rtx dwarf = NULL_RTX; 3905 rtx adjust_sp_rtx, reg; 3906 int saved_size = cfun->machine->frame.save_libcall_adjustment; 3907 3908 /* Debug info for adjust sp. */ 3909 adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, 3910 stack_pointer_rtx, GEN_INT (saved_size)); 3911 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, 3912 dwarf); 3913 3914 for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 3915 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 3916 { 3917 reg = gen_rtx_REG (SImode, regno); 3918 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 3919 } 3920 3921 return dwarf; 3922 } 3923 3924 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern; 3925 style says which. */ 3926 3927 void 3928 riscv_expand_epilogue (int style) 3929 { 3930 /* Split the frame into two. STEP1 is the amount of stack we should 3931 deallocate before restoring the registers. STEP2 is the amount we 3932 should deallocate afterwards. 3933 3934 Start off by assuming that no registers need to be restored. */ 3935 struct riscv_frame_info *frame = &cfun->machine->frame; 3936 unsigned mask = frame->mask; 3937 HOST_WIDE_INT step1 = frame->total_size; 3938 HOST_WIDE_INT step2 = 0; 3939 bool use_restore_libcall = ((style == NORMAL_RETURN) 3940 && riscv_use_save_libcall (frame)); 3941 rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); 3942 rtx insn; 3943 3944 /* We need to add memory barrier to prevent read from deallocated stack. */ 3945 bool need_barrier_p = (get_frame_size () 3946 + cfun->machine->frame.arg_pointer_offset) != 0; 3947 3948 if (cfun->machine->naked_p) 3949 { 3950 gcc_assert (style == NORMAL_RETURN); 3951 3952 emit_jump_insn (gen_return ()); 3953 3954 return; 3955 } 3956 3957 if ((style == NORMAL_RETURN) && riscv_can_use_return_insn ()) 3958 { 3959 emit_jump_insn (gen_return ()); 3960 return; 3961 } 3962 3963 /* Reset the epilogue cfa info before starting to emit the epilogue. */ 3964 epilogue_cfa_sp_offset = 0; 3965 3966 /* Move past any dynamic stack allocations. */ 3967 if (cfun->calls_alloca) 3968 { 3969 /* Emit a barrier to prevent loads from a deallocated stack. */ 3970 riscv_emit_stack_tie (); 3971 need_barrier_p = false; 3972 3973 rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset); 3974 if (!SMALL_OPERAND (INTVAL (adjust))) 3975 { 3976 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); 3977 adjust = RISCV_PROLOGUE_TEMP (Pmode); 3978 } 3979 3980 insn = emit_insn ( 3981 gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, 3982 adjust)); 3983 3984 rtx dwarf = NULL_RTX; 3985 rtx cfa_adjust_value = gen_rtx_PLUS ( 3986 Pmode, hard_frame_pointer_rtx, 3987 GEN_INT (-frame->hard_frame_pointer_offset)); 3988 rtx cfa_adjust_rtx = gen_rtx_SET (stack_pointer_rtx, cfa_adjust_value); 3989 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, cfa_adjust_rtx, dwarf); 3990 RTX_FRAME_RELATED_P (insn) = 1; 3991 3992 REG_NOTES (insn) = dwarf; 3993 } 3994 3995 /* If we need to restore registers, deallocate as much stack as 3996 possible in the second step without going out of range. */ 3997 if ((frame->mask | frame->fmask) != 0) 3998 { 3999 step2 = riscv_first_stack_step (frame); 4000 step1 -= step2; 4001 } 4002 4003 /* Set TARGET to BASE + STEP1. */ 4004 if (step1 > 0) 4005 { 4006 /* Emit a barrier to prevent loads from a deallocated stack. */ 4007 riscv_emit_stack_tie (); 4008 need_barrier_p = false; 4009 4010 /* Get an rtx for STEP1 that we can add to BASE. */ 4011 rtx adjust = GEN_INT (step1); 4012 if (!SMALL_OPERAND (step1)) 4013 { 4014 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); 4015 adjust = RISCV_PROLOGUE_TEMP (Pmode); 4016 } 4017 4018 insn = emit_insn ( 4019 gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); 4020 4021 rtx dwarf = NULL_RTX; 4022 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 4023 GEN_INT (step2)); 4024 4025 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 4026 RTX_FRAME_RELATED_P (insn) = 1; 4027 4028 REG_NOTES (insn) = dwarf; 4029 } 4030 else if (frame_pointer_needed) 4031 { 4032 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring 4033 old value of FP. */ 4034 epilogue_cfa_sp_offset = step2; 4035 } 4036 4037 if (use_restore_libcall) 4038 frame->mask = 0; /* Temporarily fib that we need not save GPRs. */ 4039 4040 /* Restore the registers. */ 4041 riscv_for_each_saved_reg (frame->total_size - step2, riscv_restore_reg, 4042 true, style == EXCEPTION_RETURN); 4043 4044 if (use_restore_libcall) 4045 { 4046 frame->mask = mask; /* Undo the above fib. */ 4047 gcc_assert (step2 >= frame->save_libcall_adjustment); 4048 step2 -= frame->save_libcall_adjustment; 4049 } 4050 4051 if (need_barrier_p) 4052 riscv_emit_stack_tie (); 4053 4054 /* Deallocate the final bit of the frame. */ 4055 if (step2 > 0) 4056 { 4057 insn = emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 4058 GEN_INT (step2))); 4059 4060 rtx dwarf = NULL_RTX; 4061 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 4062 const0_rtx); 4063 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 4064 RTX_FRAME_RELATED_P (insn) = 1; 4065 4066 REG_NOTES (insn) = dwarf; 4067 } 4068 4069 if (use_restore_libcall) 4070 { 4071 rtx dwarf = riscv_adjust_libcall_cfi_epilogue (); 4072 insn = emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask)))); 4073 RTX_FRAME_RELATED_P (insn) = 1; 4074 REG_NOTES (insn) = dwarf; 4075 4076 emit_jump_insn (gen_gpr_restore_return (ra)); 4077 return; 4078 } 4079 4080 /* Add in the __builtin_eh_return stack adjustment. */ 4081 if ((style == EXCEPTION_RETURN) && crtl->calls_eh_return) 4082 emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 4083 EH_RETURN_STACKADJ_RTX)); 4084 4085 /* Return from interrupt. */ 4086 if (cfun->machine->interrupt_handler_p) 4087 { 4088 enum riscv_privilege_levels mode = cfun->machine->interrupt_mode; 4089 4090 gcc_assert (mode != UNKNOWN_MODE); 4091 4092 if (mode == MACHINE_MODE) 4093 emit_jump_insn (gen_riscv_mret ()); 4094 else if (mode == SUPERVISOR_MODE) 4095 emit_jump_insn (gen_riscv_sret ()); 4096 else 4097 emit_jump_insn (gen_riscv_uret ()); 4098 } 4099 else if (style != SIBCALL_RETURN) 4100 emit_jump_insn (gen_simple_return_internal (ra)); 4101 } 4102 4103 /* Implement EPILOGUE_USES. */ 4104 4105 bool 4106 riscv_epilogue_uses (unsigned int regno) 4107 { 4108 if (regno == RETURN_ADDR_REGNUM) 4109 return true; 4110 4111 if (epilogue_completed && cfun->machine->interrupt_handler_p) 4112 { 4113 /* An interrupt function restores temp regs, so we must indicate that 4114 they are live at function end. */ 4115 if (df_regs_ever_live_p (regno) 4116 || (!crtl->is_leaf && call_used_regs[regno])) 4117 return true; 4118 } 4119 4120 return false; 4121 } 4122 4123 /* Return nonzero if this function is known to have a null epilogue. 4124 This allows the optimizer to omit jumps to jumps if no stack 4125 was created. */ 4126 4127 bool 4128 riscv_can_use_return_insn (void) 4129 { 4130 return (reload_completed && cfun->machine->frame.total_size == 0 4131 && ! cfun->machine->interrupt_handler_p); 4132 } 4133 4134 /* Given that there exists at least one variable that is set (produced) 4135 by OUT_INSN and read (consumed) by IN_INSN, return true iff 4136 IN_INSN represents one or more memory store operations and none of 4137 the variables set by OUT_INSN is used by IN_INSN as the address of a 4138 store operation. If either IN_INSN or OUT_INSN does not represent 4139 a "single" RTL SET expression (as loosely defined by the 4140 implementation of the single_set function) or a PARALLEL with only 4141 SETs, CLOBBERs, and USEs inside, this function returns false. 4142 4143 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain 4144 conditions that result in assertion failures in the generic 4145 store_data_bypass_p function and returns FALSE in such cases. 4146 4147 This is required to make -msave-restore work with the sifive-7 4148 pipeline description. */ 4149 4150 bool 4151 riscv_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) 4152 { 4153 rtx out_set, in_set; 4154 rtx out_pat, in_pat; 4155 rtx out_exp, in_exp; 4156 int i, j; 4157 4158 in_set = single_set (in_insn); 4159 if (in_set) 4160 { 4161 if (MEM_P (SET_DEST (in_set))) 4162 { 4163 out_set = single_set (out_insn); 4164 if (!out_set) 4165 { 4166 out_pat = PATTERN (out_insn); 4167 if (GET_CODE (out_pat) == PARALLEL) 4168 { 4169 for (i = 0; i < XVECLEN (out_pat, 0); i++) 4170 { 4171 out_exp = XVECEXP (out_pat, 0, i); 4172 if ((GET_CODE (out_exp) == CLOBBER) 4173 || (GET_CODE (out_exp) == USE)) 4174 continue; 4175 else if (GET_CODE (out_exp) != SET) 4176 return false; 4177 } 4178 } 4179 } 4180 } 4181 } 4182 else 4183 { 4184 in_pat = PATTERN (in_insn); 4185 if (GET_CODE (in_pat) != PARALLEL) 4186 return false; 4187 4188 for (i = 0; i < XVECLEN (in_pat, 0); i++) 4189 { 4190 in_exp = XVECEXP (in_pat, 0, i); 4191 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE)) 4192 continue; 4193 else if (GET_CODE (in_exp) != SET) 4194 return false; 4195 4196 if (MEM_P (SET_DEST (in_exp))) 4197 { 4198 out_set = single_set (out_insn); 4199 if (!out_set) 4200 { 4201 out_pat = PATTERN (out_insn); 4202 if (GET_CODE (out_pat) != PARALLEL) 4203 return false; 4204 for (j = 0; j < XVECLEN (out_pat, 0); j++) 4205 { 4206 out_exp = XVECEXP (out_pat, 0, j); 4207 if ((GET_CODE (out_exp) == CLOBBER) 4208 || (GET_CODE (out_exp) == USE)) 4209 continue; 4210 else if (GET_CODE (out_exp) != SET) 4211 return false; 4212 } 4213 } 4214 } 4215 } 4216 } 4217 4218 return store_data_bypass_p (out_insn, in_insn); 4219 } 4220 4221 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. 4222 4223 When floating-point registers are wider than integer ones, moves between 4224 them must go through memory. */ 4225 4226 static bool 4227 riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1, 4228 reg_class_t class2) 4229 { 4230 return (GET_MODE_SIZE (mode) > UNITS_PER_WORD 4231 && (class1 == FP_REGS) != (class2 == FP_REGS)); 4232 } 4233 4234 /* Implement TARGET_REGISTER_MOVE_COST. */ 4235 4236 static int 4237 riscv_register_move_cost (machine_mode mode, 4238 reg_class_t from, reg_class_t to) 4239 { 4240 return riscv_secondary_memory_needed (mode, from, to) ? 8 : 2; 4241 } 4242 4243 /* Implement TARGET_HARD_REGNO_NREGS. */ 4244 4245 static unsigned int 4246 riscv_hard_regno_nregs (unsigned int regno, machine_mode mode) 4247 { 4248 if (FP_REG_P (regno)) 4249 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_REG - 1) / UNITS_PER_FP_REG; 4250 4251 /* All other registers are word-sized. */ 4252 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 4253 } 4254 4255 /* Implement TARGET_HARD_REGNO_MODE_OK. */ 4256 4257 static bool 4258 riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 4259 { 4260 unsigned int nregs = riscv_hard_regno_nregs (regno, mode); 4261 4262 if (GP_REG_P (regno)) 4263 { 4264 if (!GP_REG_P (regno + nregs - 1)) 4265 return false; 4266 } 4267 else if (FP_REG_P (regno)) 4268 { 4269 if (!FP_REG_P (regno + nregs - 1)) 4270 return false; 4271 4272 if (GET_MODE_CLASS (mode) != MODE_FLOAT 4273 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) 4274 return false; 4275 4276 /* Only use callee-saved registers if a potential callee is guaranteed 4277 to spill the requisite width. */ 4278 if (GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_REG 4279 || (!call_used_regs[regno] 4280 && GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_ARG)) 4281 return false; 4282 } 4283 else 4284 return false; 4285 4286 /* Require same callee-savedness for all registers. */ 4287 for (unsigned i = 1; i < nregs; i++) 4288 if (call_used_regs[regno] != call_used_regs[regno + i]) 4289 return false; 4290 4291 return true; 4292 } 4293 4294 /* Implement TARGET_MODES_TIEABLE_P. 4295 4296 Don't allow floating-point modes to be tied, since type punning of 4297 single-precision and double-precision is implementation defined. */ 4298 4299 static bool 4300 riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) 4301 { 4302 return (mode1 == mode2 4303 || !(GET_MODE_CLASS (mode1) == MODE_FLOAT 4304 && GET_MODE_CLASS (mode2) == MODE_FLOAT)); 4305 } 4306 4307 /* Implement CLASS_MAX_NREGS. */ 4308 4309 static unsigned char 4310 riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) 4311 { 4312 if (reg_class_subset_p (FP_REGS, rclass)) 4313 return riscv_hard_regno_nregs (FP_REG_FIRST, mode); 4314 4315 if (reg_class_subset_p (GR_REGS, rclass)) 4316 return riscv_hard_regno_nregs (GP_REG_FIRST, mode); 4317 4318 return 0; 4319 } 4320 4321 /* Implement TARGET_MEMORY_MOVE_COST. */ 4322 4323 static int 4324 riscv_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in) 4325 { 4326 return (tune_info->memory_cost 4327 + memory_move_secondary_cost (mode, rclass, in)); 4328 } 4329 4330 /* Return the number of instructions that can be issued per cycle. */ 4331 4332 static int 4333 riscv_issue_rate (void) 4334 { 4335 return tune_info->issue_rate; 4336 } 4337 4338 /* Auxiliary function to emit RISC-V ELF attribute. */ 4339 static void 4340 riscv_emit_attribute () 4341 { 4342 fprintf (asm_out_file, "\t.attribute arch, \"%s\"\n", 4343 riscv_arch_str ().c_str ()); 4344 4345 fprintf (asm_out_file, "\t.attribute unaligned_access, %d\n", 4346 TARGET_STRICT_ALIGN ? 0 : 1); 4347 4348 fprintf (asm_out_file, "\t.attribute stack_align, %d\n", 4349 riscv_stack_boundary / 8); 4350 } 4351 4352 /* Implement TARGET_ASM_FILE_START. */ 4353 4354 static void 4355 riscv_file_start (void) 4356 { 4357 default_file_start (); 4358 4359 /* Instruct GAS to generate position-[in]dependent code. */ 4360 fprintf (asm_out_file, "\t.option %spic\n", (flag_pic ? "" : "no")); 4361 4362 /* If the user specifies "-mno-relax" on the command line then disable linker 4363 relaxation in the assembler. */ 4364 if (! riscv_mrelax) 4365 fprintf (asm_out_file, "\t.option norelax\n"); 4366 4367 if (riscv_emit_attribute_p) 4368 riscv_emit_attribute (); 4369 } 4370 4371 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text 4372 in order to avoid duplicating too much logic from elsewhere. */ 4373 4374 static void 4375 riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 4376 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 4377 tree function) 4378 { 4379 rtx this_rtx, temp1, temp2, fnaddr; 4380 rtx_insn *insn; 4381 4382 /* Pretend to be a post-reload pass while generating rtl. */ 4383 reload_completed = 1; 4384 4385 /* Mark the end of the (empty) prologue. */ 4386 emit_note (NOTE_INSN_PROLOGUE_END); 4387 4388 /* Determine if we can use a sibcall to call FUNCTION directly. */ 4389 fnaddr = gen_rtx_MEM (FUNCTION_MODE, XEXP (DECL_RTL (function), 0)); 4390 4391 /* We need two temporary registers in some cases. */ 4392 temp1 = gen_rtx_REG (Pmode, RISCV_PROLOGUE_TEMP_REGNUM); 4393 temp2 = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); 4394 4395 /* Find out which register contains the "this" pointer. */ 4396 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 4397 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); 4398 else 4399 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); 4400 4401 /* Add DELTA to THIS_RTX. */ 4402 if (delta != 0) 4403 { 4404 rtx offset = GEN_INT (delta); 4405 if (!SMALL_OPERAND (delta)) 4406 { 4407 riscv_emit_move (temp1, offset); 4408 offset = temp1; 4409 } 4410 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); 4411 } 4412 4413 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ 4414 if (vcall_offset != 0) 4415 { 4416 rtx addr; 4417 4418 /* Set TEMP1 to *THIS_RTX. */ 4419 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); 4420 4421 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ 4422 addr = riscv_add_offset (temp2, temp1, vcall_offset); 4423 4424 /* Load the offset and add it to THIS_RTX. */ 4425 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); 4426 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); 4427 } 4428 4429 /* Jump to the target function. */ 4430 insn = emit_call_insn (gen_sibcall (fnaddr, const0_rtx, NULL, const0_rtx)); 4431 SIBLING_CALL_P (insn) = 1; 4432 4433 /* Run just enough of rest_of_compilation. This sequence was 4434 "borrowed" from alpha.c. */ 4435 insn = get_insns (); 4436 split_all_insns_noflow (); 4437 shorten_branches (insn); 4438 final_start_function (insn, file, 1); 4439 final (insn, file, 1); 4440 final_end_function (); 4441 4442 /* Clean up the vars set above. Note that final_end_function resets 4443 the global pointer for us. */ 4444 reload_completed = 0; 4445 } 4446 4447 /* Allocate a chunk of memory for per-function machine-dependent data. */ 4448 4449 static struct machine_function * 4450 riscv_init_machine_status (void) 4451 { 4452 return ggc_cleared_alloc<machine_function> (); 4453 } 4454 4455 /* Implement TARGET_OPTION_OVERRIDE. */ 4456 4457 static void 4458 riscv_option_override (void) 4459 { 4460 const struct riscv_cpu_info *cpu; 4461 4462 #ifdef SUBTARGET_OVERRIDE_OPTIONS 4463 SUBTARGET_OVERRIDE_OPTIONS; 4464 #endif 4465 4466 flag_pcc_struct_return = 0; 4467 4468 if (flag_pic) 4469 g_switch_value = 0; 4470 4471 /* The presence of the M extension implies that division instructions 4472 are present, so include them unless explicitly disabled. */ 4473 if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) 4474 target_flags |= MASK_DIV; 4475 else if (!TARGET_MUL && TARGET_DIV) 4476 error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension"); 4477 4478 /* Likewise floating-point division and square root. */ 4479 if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) 4480 target_flags |= MASK_FDIV; 4481 4482 /* Handle -mtune. */ 4483 cpu = riscv_parse_cpu (riscv_tune_string ? riscv_tune_string : 4484 RISCV_TUNE_STRING_DEFAULT); 4485 riscv_microarchitecture = cpu->microarchitecture; 4486 tune_info = optimize_size ? &optimize_size_tune_info : cpu->tune_info; 4487 4488 /* Use -mtune's setting for slow_unaligned_access, even when optimizing 4489 for size. For architectures that trap and emulate unaligned accesses, 4490 the performance cost is too great, even for -Os. Similarly, if 4491 -m[no-]strict-align is left unspecified, heed -mtune's advice. */ 4492 riscv_slow_unaligned_access_p = (cpu->tune_info->slow_unaligned_access 4493 || TARGET_STRICT_ALIGN); 4494 if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0 4495 && cpu->tune_info->slow_unaligned_access) 4496 target_flags |= MASK_STRICT_ALIGN; 4497 4498 /* If the user hasn't specified a branch cost, use the processor's 4499 default. */ 4500 if (riscv_branch_cost == 0) 4501 riscv_branch_cost = tune_info->branch_cost; 4502 4503 /* Function to allocate machine-dependent function status. */ 4504 init_machine_status = &riscv_init_machine_status; 4505 4506 if (flag_pic) 4507 riscv_cmodel = CM_PIC; 4508 4509 /* We get better code with explicit relocs for CM_MEDLOW, but 4510 worse code for the others (for now). Pick the best default. */ 4511 if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0) 4512 if (riscv_cmodel == CM_MEDLOW) 4513 target_flags |= MASK_EXPLICIT_RELOCS; 4514 4515 /* Require that the ISA supports the requested floating-point ABI. */ 4516 if (UNITS_PER_FP_ARG > (TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : 0)) 4517 error ("requested ABI requires %<-march%> to subsume the %qc extension", 4518 UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F')); 4519 4520 if (TARGET_RVE && riscv_abi != ABI_ILP32E) 4521 error ("rv32e requires ilp32e ABI"); 4522 4523 /* We do not yet support ILP32 on RV64. */ 4524 if (BITS_PER_WORD != POINTER_SIZE) 4525 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); 4526 4527 /* Validate -mpreferred-stack-boundary= value. */ 4528 riscv_stack_boundary = ABI_STACK_BOUNDARY; 4529 if (riscv_preferred_stack_boundary_arg) 4530 { 4531 int min = ctz_hwi (STACK_BOUNDARY / 8); 4532 int max = 8; 4533 4534 if (!IN_RANGE (riscv_preferred_stack_boundary_arg, min, max)) 4535 error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d", 4536 riscv_preferred_stack_boundary_arg, min, max); 4537 4538 riscv_stack_boundary = 8 << riscv_preferred_stack_boundary_arg; 4539 } 4540 4541 if (riscv_emit_attribute_p < 0) 4542 #ifdef HAVE_AS_RISCV_ATTRIBUTE 4543 riscv_emit_attribute_p = TARGET_RISCV_ATTRIBUTE; 4544 #else 4545 riscv_emit_attribute_p = 0; 4546 4547 if (riscv_emit_attribute_p) 4548 error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32" 4549 " [%<-mriscv-attribute%>]"); 4550 #endif 4551 } 4552 4553 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ 4554 4555 static void 4556 riscv_conditional_register_usage (void) 4557 { 4558 /* We have only x0~x15 on RV32E. */ 4559 if (TARGET_RVE) 4560 { 4561 for (int r = 16; r <= 31; r++) 4562 fixed_regs[r] = 1; 4563 } 4564 4565 if (riscv_abi == ABI_ILP32E) 4566 { 4567 for (int r = 16; r <= 31; r++) 4568 call_used_regs[r] = 1; 4569 } 4570 4571 if (!TARGET_HARD_FLOAT) 4572 { 4573 for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 4574 fixed_regs[regno] = call_used_regs[regno] = 1; 4575 } 4576 4577 /* In the soft-float ABI, there are no callee-saved FP registers. */ 4578 if (UNITS_PER_FP_ARG == 0) 4579 { 4580 for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 4581 call_used_regs[regno] = 1; 4582 } 4583 } 4584 4585 /* Return a register priority for hard reg REGNO. */ 4586 4587 static int 4588 riscv_register_priority (int regno) 4589 { 4590 /* Favor x8-x15/f8-f15 to improve the odds of RVC instruction selection. */ 4591 if (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15) 4592 || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15))) 4593 return 1; 4594 4595 return 0; 4596 } 4597 4598 /* Implement TARGET_TRAMPOLINE_INIT. */ 4599 4600 static void 4601 riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 4602 { 4603 rtx addr, end_addr, mem; 4604 uint32_t trampoline[4]; 4605 unsigned int i; 4606 HOST_WIDE_INT static_chain_offset, target_function_offset; 4607 4608 /* Work out the offsets of the pointers from the start of the 4609 trampoline code. */ 4610 gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE); 4611 4612 /* Get pointers to the beginning and end of the code block. */ 4613 addr = force_reg (Pmode, XEXP (m_tramp, 0)); 4614 end_addr = riscv_force_binary (Pmode, PLUS, addr, 4615 GEN_INT (TRAMPOLINE_CODE_SIZE)); 4616 4617 4618 if (Pmode == SImode) 4619 { 4620 chain_value = force_reg (Pmode, chain_value); 4621 4622 rtx target_function = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0)); 4623 /* lui t2, hi(chain) 4624 lui t1, hi(func) 4625 addi t2, t2, lo(chain) 4626 jr r1, lo(func) 4627 */ 4628 unsigned HOST_WIDE_INT lui_hi_chain_code, lui_hi_func_code; 4629 unsigned HOST_WIDE_INT lo_chain_code, lo_func_code; 4630 4631 rtx uimm_mask = force_reg (SImode, gen_int_mode (-IMM_REACH, SImode)); 4632 4633 /* 0xfff. */ 4634 rtx imm12_mask = gen_reg_rtx (SImode); 4635 emit_insn (gen_one_cmplsi2 (imm12_mask, uimm_mask)); 4636 4637 rtx fixup_value = force_reg (SImode, gen_int_mode (IMM_REACH/2, SImode)); 4638 4639 /* Gen lui t2, hi(chain). */ 4640 rtx hi_chain = riscv_force_binary (SImode, PLUS, chain_value, 4641 fixup_value); 4642 hi_chain = riscv_force_binary (SImode, AND, hi_chain, 4643 uimm_mask); 4644 lui_hi_chain_code = OPCODE_LUI | (STATIC_CHAIN_REGNUM << SHIFT_RD); 4645 rtx lui_hi_chain = riscv_force_binary (SImode, IOR, hi_chain, 4646 gen_int_mode (lui_hi_chain_code, SImode)); 4647 4648 mem = adjust_address (m_tramp, SImode, 0); 4649 riscv_emit_move (mem, lui_hi_chain); 4650 4651 /* Gen lui t1, hi(func). */ 4652 rtx hi_func = riscv_force_binary (SImode, PLUS, target_function, 4653 fixup_value); 4654 hi_func = riscv_force_binary (SImode, AND, hi_func, 4655 uimm_mask); 4656 lui_hi_func_code = OPCODE_LUI | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD); 4657 rtx lui_hi_func = riscv_force_binary (SImode, IOR, hi_func, 4658 gen_int_mode (lui_hi_func_code, SImode)); 4659 4660 mem = adjust_address (m_tramp, SImode, 1 * GET_MODE_SIZE (SImode)); 4661 riscv_emit_move (mem, lui_hi_func); 4662 4663 /* Gen addi t2, t2, lo(chain). */ 4664 rtx lo_chain = riscv_force_binary (SImode, AND, chain_value, 4665 imm12_mask); 4666 lo_chain = riscv_force_binary (SImode, ASHIFT, lo_chain, GEN_INT (20)); 4667 4668 lo_chain_code = OPCODE_ADDI 4669 | (STATIC_CHAIN_REGNUM << SHIFT_RD) 4670 | (STATIC_CHAIN_REGNUM << SHIFT_RS1); 4671 4672 rtx addi_lo_chain = riscv_force_binary (SImode, IOR, lo_chain, 4673 force_reg (SImode, GEN_INT (lo_chain_code))); 4674 4675 mem = adjust_address (m_tramp, SImode, 2 * GET_MODE_SIZE (SImode)); 4676 riscv_emit_move (mem, addi_lo_chain); 4677 4678 /* Gen jr r1, lo(func). */ 4679 rtx lo_func = riscv_force_binary (SImode, AND, target_function, 4680 imm12_mask); 4681 lo_func = riscv_force_binary (SImode, ASHIFT, lo_func, GEN_INT (20)); 4682 4683 lo_func_code = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1); 4684 4685 rtx jr_lo_func = riscv_force_binary (SImode, IOR, lo_func, 4686 force_reg (SImode, GEN_INT (lo_func_code))); 4687 4688 mem = adjust_address (m_tramp, SImode, 3 * GET_MODE_SIZE (SImode)); 4689 riscv_emit_move (mem, jr_lo_func); 4690 } 4691 else 4692 { 4693 static_chain_offset = TRAMPOLINE_CODE_SIZE; 4694 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); 4695 4696 /* auipc t2, 0 4697 l[wd] t1, target_function_offset(t2) 4698 l[wd] t2, static_chain_offset(t2) 4699 jr t1 4700 */ 4701 trampoline[0] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD); 4702 trampoline[1] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) 4703 | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD) 4704 | (STATIC_CHAIN_REGNUM << SHIFT_RS1) 4705 | (target_function_offset << SHIFT_IMM); 4706 trampoline[2] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) 4707 | (STATIC_CHAIN_REGNUM << SHIFT_RD) 4708 | (STATIC_CHAIN_REGNUM << SHIFT_RS1) 4709 | (static_chain_offset << SHIFT_IMM); 4710 trampoline[3] = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1); 4711 4712 /* Copy the trampoline code. */ 4713 for (i = 0; i < ARRAY_SIZE (trampoline); i++) 4714 { 4715 mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode)); 4716 riscv_emit_move (mem, gen_int_mode (trampoline[i], SImode)); 4717 } 4718 4719 /* Set up the static chain pointer field. */ 4720 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); 4721 riscv_emit_move (mem, chain_value); 4722 4723 /* Set up the target function field. */ 4724 mem = adjust_address (m_tramp, ptr_mode, target_function_offset); 4725 riscv_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); 4726 } 4727 4728 /* Flush the code part of the trampoline. */ 4729 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); 4730 emit_insn (gen_clear_cache (addr, end_addr)); 4731 } 4732 4733 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */ 4734 4735 static bool 4736 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, 4737 tree exp ATTRIBUTE_UNUSED) 4738 { 4739 /* Don't use sibcalls when use save-restore routine. */ 4740 if (TARGET_SAVE_RESTORE) 4741 return false; 4742 4743 /* Don't use sibcall for naked functions. */ 4744 if (cfun->machine->naked_p) 4745 return false; 4746 4747 /* Don't use sibcall for interrupt functions. */ 4748 if (cfun->machine->interrupt_handler_p) 4749 return false; 4750 4751 return true; 4752 } 4753 4754 /* Get the interrupt type, return UNKNOWN_MODE if it's not 4755 interrupt function. */ 4756 static enum riscv_privilege_levels 4757 riscv_get_interrupt_type (tree decl) 4758 { 4759 gcc_assert (decl != NULL_TREE); 4760 4761 if ((TREE_CODE(decl) != FUNCTION_DECL) 4762 || (!riscv_interrupt_type_p (TREE_TYPE (decl)))) 4763 return UNKNOWN_MODE; 4764 4765 tree attr_args 4766 = TREE_VALUE (lookup_attribute ("interrupt", 4767 TYPE_ATTRIBUTES (TREE_TYPE (decl)))); 4768 4769 if (attr_args && TREE_CODE (TREE_VALUE (attr_args)) != VOID_TYPE) 4770 { 4771 const char *string = TREE_STRING_POINTER (TREE_VALUE (attr_args)); 4772 4773 if (!strcmp (string, "user")) 4774 return USER_MODE; 4775 else if (!strcmp (string, "supervisor")) 4776 return SUPERVISOR_MODE; 4777 else /* Must be "machine". */ 4778 return MACHINE_MODE; 4779 } 4780 else 4781 /* Interrupt attributes are machine mode by default. */ 4782 return MACHINE_MODE; 4783 } 4784 4785 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */ 4786 /* Sanity cheching for above function attributes. */ 4787 static void 4788 riscv_set_current_function (tree decl) 4789 { 4790 if (decl == NULL_TREE 4791 || current_function_decl == NULL_TREE 4792 || current_function_decl == error_mark_node 4793 || ! cfun->machine 4794 || cfun->machine->attributes_checked_p) 4795 return; 4796 4797 cfun->machine->naked_p = riscv_naked_function_p (decl); 4798 cfun->machine->interrupt_handler_p 4799 = riscv_interrupt_type_p (TREE_TYPE (decl)); 4800 4801 if (cfun->machine->naked_p && cfun->machine->interrupt_handler_p) 4802 error ("function attributes %qs and %qs are mutually exclusive", 4803 "interrupt", "naked"); 4804 4805 if (cfun->machine->interrupt_handler_p) 4806 { 4807 tree ret = TREE_TYPE (TREE_TYPE (decl)); 4808 tree args = TYPE_ARG_TYPES (TREE_TYPE (decl)); 4809 4810 if (TREE_CODE (ret) != VOID_TYPE) 4811 error ("%qs function cannot return a value", "interrupt"); 4812 4813 if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE) 4814 error ("%qs function cannot have arguments", "interrupt"); 4815 4816 cfun->machine->interrupt_mode = riscv_get_interrupt_type (decl); 4817 4818 gcc_assert (cfun->machine->interrupt_mode != UNKNOWN_MODE); 4819 } 4820 4821 /* Don't print the above diagnostics more than once. */ 4822 cfun->machine->attributes_checked_p = 1; 4823 } 4824 4825 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */ 4826 static tree 4827 riscv_merge_decl_attributes (tree olddecl, tree newdecl) 4828 { 4829 tree combined_attrs; 4830 4831 enum riscv_privilege_levels old_interrupt_type 4832 = riscv_get_interrupt_type (olddecl); 4833 enum riscv_privilege_levels new_interrupt_type 4834 = riscv_get_interrupt_type (newdecl); 4835 4836 /* Check old and new has same interrupt type. */ 4837 if ((old_interrupt_type != UNKNOWN_MODE) 4838 && (new_interrupt_type != UNKNOWN_MODE) 4839 && (old_interrupt_type != new_interrupt_type)) 4840 error ("%qs function cannot have different interrupt type", "interrupt"); 4841 4842 /* Create combined attributes. */ 4843 combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), 4844 DECL_ATTRIBUTES (newdecl)); 4845 4846 return combined_attrs; 4847 } 4848 4849 /* Implement TARGET_CANNOT_COPY_INSN_P. */ 4850 4851 static bool 4852 riscv_cannot_copy_insn_p (rtx_insn *insn) 4853 { 4854 return recog_memoized (insn) >= 0 && get_attr_cannot_copy (insn); 4855 } 4856 4857 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */ 4858 4859 static bool 4860 riscv_slow_unaligned_access (machine_mode, unsigned int) 4861 { 4862 return riscv_slow_unaligned_access_p; 4863 } 4864 4865 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */ 4866 4867 static bool 4868 riscv_can_change_mode_class (machine_mode, machine_mode, reg_class_t rclass) 4869 { 4870 return !reg_classes_intersect_p (FP_REGS, rclass); 4871 } 4872 4873 4874 /* Implement TARGET_CONSTANT_ALIGNMENT. */ 4875 4876 static HOST_WIDE_INT 4877 riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align) 4878 { 4879 if (TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR) 4880 return MAX (align, BITS_PER_WORD); 4881 return align; 4882 } 4883 4884 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */ 4885 4886 /* This function is equivalent to default_promote_function_mode_always_promote 4887 except that it returns a promoted mode even if type is NULL_TREE. This is 4888 needed by libcalls which have no type (only a mode) such as fixed conversion 4889 routines that take a signed or unsigned char/short/int argument and convert 4890 it to a fixed type. */ 4891 4892 static machine_mode 4893 riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, 4894 machine_mode mode, 4895 int *punsignedp ATTRIBUTE_UNUSED, 4896 const_tree fntype ATTRIBUTE_UNUSED, 4897 int for_return ATTRIBUTE_UNUSED) 4898 { 4899 int unsignedp; 4900 4901 if (type != NULL_TREE) 4902 return promote_mode (type, mode, punsignedp); 4903 4904 unsignedp = *punsignedp; 4905 PROMOTE_MODE (mode, unsignedp, type); 4906 *punsignedp = unsignedp; 4907 return mode; 4908 } 4909 4910 /* Return nonzero if register FROM_REGNO can be renamed to register 4911 TO_REGNO. */ 4912 4913 bool 4914 riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED, 4915 unsigned to_regno) 4916 { 4917 /* Interrupt functions can only use registers that have already been 4918 saved by the prologue, even if they would normally be 4919 call-clobbered. */ 4920 return !cfun->machine->interrupt_handler_p || df_regs_ever_live_p (to_regno); 4921 } 4922 4923 /* Initialize the GCC target structure. */ 4924 #undef TARGET_ASM_ALIGNED_HI_OP 4925 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 4926 #undef TARGET_ASM_ALIGNED_SI_OP 4927 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 4928 #undef TARGET_ASM_ALIGNED_DI_OP 4929 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" 4930 4931 #undef TARGET_OPTION_OVERRIDE 4932 #define TARGET_OPTION_OVERRIDE riscv_option_override 4933 4934 #undef TARGET_LEGITIMIZE_ADDRESS 4935 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address 4936 4937 #undef TARGET_SCHED_ISSUE_RATE 4938 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate 4939 4940 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 4941 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall 4942 4943 #undef TARGET_SET_CURRENT_FUNCTION 4944 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function 4945 4946 #undef TARGET_REGISTER_MOVE_COST 4947 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost 4948 #undef TARGET_MEMORY_MOVE_COST 4949 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost 4950 #undef TARGET_RTX_COSTS 4951 #define TARGET_RTX_COSTS riscv_rtx_costs 4952 #undef TARGET_ADDRESS_COST 4953 #define TARGET_ADDRESS_COST riscv_address_cost 4954 4955 #undef TARGET_ASM_FILE_START 4956 #define TARGET_ASM_FILE_START riscv_file_start 4957 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 4958 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 4959 4960 #undef TARGET_EXPAND_BUILTIN_VA_START 4961 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start 4962 4963 #undef TARGET_PROMOTE_FUNCTION_MODE 4964 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode 4965 4966 #undef TARGET_RETURN_IN_MEMORY 4967 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory 4968 4969 #undef TARGET_ASM_OUTPUT_MI_THUNK 4970 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk 4971 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 4972 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true 4973 4974 #undef TARGET_PRINT_OPERAND 4975 #define TARGET_PRINT_OPERAND riscv_print_operand 4976 #undef TARGET_PRINT_OPERAND_ADDRESS 4977 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address 4978 4979 #undef TARGET_SETUP_INCOMING_VARARGS 4980 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs 4981 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS 4982 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args 4983 #undef TARGET_STRICT_ARGUMENT_NAMING 4984 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true 4985 #undef TARGET_MUST_PASS_IN_STACK 4986 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 4987 #undef TARGET_PASS_BY_REFERENCE 4988 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference 4989 #undef TARGET_ARG_PARTIAL_BYTES 4990 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes 4991 #undef TARGET_FUNCTION_ARG 4992 #define TARGET_FUNCTION_ARG riscv_function_arg 4993 #undef TARGET_FUNCTION_ARG_ADVANCE 4994 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance 4995 #undef TARGET_FUNCTION_ARG_BOUNDARY 4996 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary 4997 4998 /* The generic ELF target does not always have TLS support. */ 4999 #ifdef HAVE_AS_TLS 5000 #undef TARGET_HAVE_TLS 5001 #define TARGET_HAVE_TLS true 5002 #endif 5003 5004 #undef TARGET_CANNOT_FORCE_CONST_MEM 5005 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem 5006 5007 #undef TARGET_LEGITIMATE_CONSTANT_P 5008 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p 5009 5010 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P 5011 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true 5012 5013 #undef TARGET_LEGITIMATE_ADDRESS_P 5014 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p 5015 5016 #undef TARGET_CAN_ELIMINATE 5017 #define TARGET_CAN_ELIMINATE riscv_can_eliminate 5018 5019 #undef TARGET_CONDITIONAL_REGISTER_USAGE 5020 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage 5021 5022 #undef TARGET_CLASS_MAX_NREGS 5023 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs 5024 5025 #undef TARGET_TRAMPOLINE_INIT 5026 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init 5027 5028 #undef TARGET_IN_SMALL_DATA_P 5029 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p 5030 5031 #undef TARGET_HAVE_SRODATA_SECTION 5032 #define TARGET_HAVE_SRODATA_SECTION true 5033 5034 #undef TARGET_ASM_SELECT_SECTION 5035 #define TARGET_ASM_SELECT_SECTION riscv_select_section 5036 5037 #undef TARGET_ASM_SELECT_RTX_SECTION 5038 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section 5039 5040 #undef TARGET_MIN_ANCHOR_OFFSET 5041 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2) 5042 5043 #undef TARGET_MAX_ANCHOR_OFFSET 5044 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1) 5045 5046 #undef TARGET_REGISTER_PRIORITY 5047 #define TARGET_REGISTER_PRIORITY riscv_register_priority 5048 5049 #undef TARGET_CANNOT_COPY_INSN_P 5050 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p 5051 5052 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV 5053 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv 5054 5055 #undef TARGET_INIT_BUILTINS 5056 #define TARGET_INIT_BUILTINS riscv_init_builtins 5057 5058 #undef TARGET_BUILTIN_DECL 5059 #define TARGET_BUILTIN_DECL riscv_builtin_decl 5060 5061 #undef TARGET_EXPAND_BUILTIN 5062 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin 5063 5064 #undef TARGET_HARD_REGNO_NREGS 5065 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs 5066 #undef TARGET_HARD_REGNO_MODE_OK 5067 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok 5068 5069 #undef TARGET_MODES_TIEABLE_P 5070 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p 5071 5072 #undef TARGET_SLOW_UNALIGNED_ACCESS 5073 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access 5074 5075 #undef TARGET_SECONDARY_MEMORY_NEEDED 5076 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed 5077 5078 #undef TARGET_CAN_CHANGE_MODE_CLASS 5079 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class 5080 5081 #undef TARGET_CONSTANT_ALIGNMENT 5082 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment 5083 5084 #undef TARGET_MERGE_DECL_ATTRIBUTES 5085 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes 5086 5087 #undef TARGET_ATTRIBUTE_TABLE 5088 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table 5089 5090 #undef TARGET_WARN_FUNC_RETURN 5091 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return 5092 5093 /* The low bit is ignored by jump instructions so is safe to use. */ 5094 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS 5095 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1 5096 5097 struct gcc_target targetm = TARGET_INITIALIZER; 5098 5099 #include "gt-riscv.h" 5100