1 /* Subroutines used for code generation for RISC-V. 2 Copyright (C) 2011-2020 Free Software Foundation, Inc. 3 Contributed by Andrew Waterman (andrew@sifive.com). 4 Based on MIPS target for GNU compiler. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 #define IN_TARGET_CODE 1 23 24 #define INCLUDE_STRING 25 #include "config.h" 26 #include "system.h" 27 #include "coretypes.h" 28 #include "tm.h" 29 #include "rtl.h" 30 #include "regs.h" 31 #include "insn-config.h" 32 #include "insn-attr.h" 33 #include "recog.h" 34 #include "output.h" 35 #include "alias.h" 36 #include "tree.h" 37 #include "stringpool.h" 38 #include "attribs.h" 39 #include "varasm.h" 40 #include "stor-layout.h" 41 #include "calls.h" 42 #include "function.h" 43 #include "explow.h" 44 #include "memmodel.h" 45 #include "emit-rtl.h" 46 #include "reload.h" 47 #include "tm_p.h" 48 #include "target.h" 49 #include "target-def.h" 50 #include "basic-block.h" 51 #include "expr.h" 52 #include "optabs.h" 53 #include "bitmap.h" 54 #include "df.h" 55 #include "diagnostic.h" 56 #include "builtins.h" 57 #include "predict.h" 58 59 /* True if X is an UNSPEC wrapper around a SYMBOL_REF or LABEL_REF. */ 60 #define UNSPEC_ADDRESS_P(X) \ 61 (GET_CODE (X) == UNSPEC \ 62 && XINT (X, 1) >= UNSPEC_ADDRESS_FIRST \ 63 && XINT (X, 1) < UNSPEC_ADDRESS_FIRST + NUM_SYMBOL_TYPES) 64 65 /* Extract the symbol or label from UNSPEC wrapper X. */ 66 #define UNSPEC_ADDRESS(X) \ 67 XVECEXP (X, 0, 0) 68 69 /* Extract the symbol type from UNSPEC wrapper X. */ 70 #define UNSPEC_ADDRESS_TYPE(X) \ 71 ((enum riscv_symbol_type) (XINT (X, 1) - UNSPEC_ADDRESS_FIRST)) 72 73 /* True if bit BIT is set in VALUE. */ 74 #define BITSET_P(VALUE, BIT) (((VALUE) & (1ULL << (BIT))) != 0) 75 76 /* Classifies an address. 77 78 ADDRESS_REG 79 A natural register + offset address. The register satisfies 80 riscv_valid_base_register_p and the offset is a const_arith_operand. 81 82 ADDRESS_LO_SUM 83 A LO_SUM rtx. The first operand is a valid base register and 84 the second operand is a symbolic address. 85 86 ADDRESS_CONST_INT 87 A signed 16-bit constant address. 88 89 ADDRESS_SYMBOLIC: 90 A constant symbolic address. */ 91 enum riscv_address_type { 92 ADDRESS_REG, 93 ADDRESS_LO_SUM, 94 ADDRESS_CONST_INT, 95 ADDRESS_SYMBOLIC 96 }; 97 98 /* Information about a function's frame layout. */ 99 struct GTY(()) riscv_frame_info { 100 /* The size of the frame in bytes. */ 101 HOST_WIDE_INT total_size; 102 103 /* Bit X is set if the function saves or restores GPR X. */ 104 unsigned int mask; 105 106 /* Likewise FPR X. */ 107 unsigned int fmask; 108 109 /* How much the GPR save/restore routines adjust sp (or 0 if unused). */ 110 unsigned save_libcall_adjustment; 111 112 /* Offsets of fixed-point and floating-point save areas from frame bottom */ 113 HOST_WIDE_INT gp_sp_offset; 114 HOST_WIDE_INT fp_sp_offset; 115 116 /* Offset of virtual frame pointer from stack pointer/frame bottom */ 117 HOST_WIDE_INT frame_pointer_offset; 118 119 /* Offset of hard frame pointer from stack pointer/frame bottom */ 120 HOST_WIDE_INT hard_frame_pointer_offset; 121 122 /* The offset of arg_pointer_rtx from the bottom of the frame. */ 123 HOST_WIDE_INT arg_pointer_offset; 124 }; 125 126 enum riscv_privilege_levels { 127 UNKNOWN_MODE, USER_MODE, SUPERVISOR_MODE, MACHINE_MODE 128 }; 129 130 struct GTY(()) machine_function { 131 /* The number of extra stack bytes taken up by register varargs. 132 This area is allocated by the callee at the very top of the frame. */ 133 int varargs_size; 134 135 /* True if current function is a naked function. */ 136 bool naked_p; 137 138 /* True if current function is an interrupt function. */ 139 bool interrupt_handler_p; 140 /* For an interrupt handler, indicates the privilege level. */ 141 enum riscv_privilege_levels interrupt_mode; 142 143 /* True if attributes on current function have been checked. */ 144 bool attributes_checked_p; 145 146 /* The current frame information, calculated by riscv_compute_frame_info. */ 147 struct riscv_frame_info frame; 148 }; 149 150 /* Information about a single argument. */ 151 struct riscv_arg_info { 152 /* True if the argument is at least partially passed on the stack. */ 153 bool stack_p; 154 155 /* The number of integer registers allocated to this argument. */ 156 unsigned int num_gprs; 157 158 /* The offset of the first register used, provided num_gprs is nonzero. 159 If passed entirely on the stack, the value is MAX_ARGS_IN_REGISTERS. */ 160 unsigned int gpr_offset; 161 162 /* The number of floating-point registers allocated to this argument. */ 163 unsigned int num_fprs; 164 165 /* The offset of the first register used, provided num_fprs is nonzero. */ 166 unsigned int fpr_offset; 167 }; 168 169 /* Information about an address described by riscv_address_type. 170 171 ADDRESS_CONST_INT 172 No fields are used. 173 174 ADDRESS_REG 175 REG is the base register and OFFSET is the constant offset. 176 177 ADDRESS_LO_SUM 178 REG and OFFSET are the operands to the LO_SUM and SYMBOL_TYPE 179 is the type of symbol it references. 180 181 ADDRESS_SYMBOLIC 182 SYMBOL_TYPE is the type of symbol that the address references. */ 183 struct riscv_address_info { 184 enum riscv_address_type type; 185 rtx reg; 186 rtx offset; 187 enum riscv_symbol_type symbol_type; 188 }; 189 190 /* One stage in a constant building sequence. These sequences have 191 the form: 192 193 A = VALUE[0] 194 A = A CODE[1] VALUE[1] 195 A = A CODE[2] VALUE[2] 196 ... 197 198 where A is an accumulator, each CODE[i] is a binary rtl operation 199 and each VALUE[i] is a constant integer. CODE[0] is undefined. */ 200 struct riscv_integer_op { 201 enum rtx_code code; 202 unsigned HOST_WIDE_INT value; 203 }; 204 205 /* The largest number of operations needed to load an integer constant. 206 The worst case is LUI, ADDI, SLLI, ADDI, SLLI, ADDI, SLLI, ADDI. */ 207 #define RISCV_MAX_INTEGER_OPS 8 208 209 /* Costs of various operations on the different architectures. */ 210 211 struct riscv_tune_info 212 { 213 unsigned short fp_add[2]; 214 unsigned short fp_mul[2]; 215 unsigned short fp_div[2]; 216 unsigned short int_mul[2]; 217 unsigned short int_div[2]; 218 unsigned short issue_rate; 219 unsigned short branch_cost; 220 unsigned short memory_cost; 221 bool slow_unaligned_access; 222 }; 223 224 /* Information about one CPU we know about. */ 225 struct riscv_cpu_info { 226 /* This CPU's canonical name. */ 227 const char *name; 228 229 /* Which automaton to use for tuning. */ 230 enum riscv_microarchitecture_type microarchitecture; 231 232 /* Tuning parameters for this CPU. */ 233 const struct riscv_tune_info *tune_info; 234 }; 235 236 /* Global variables for machine-dependent things. */ 237 238 /* Whether unaligned accesses execute very slowly. */ 239 bool riscv_slow_unaligned_access_p; 240 241 /* Stack alignment to assume/maintain. */ 242 unsigned riscv_stack_boundary; 243 244 /* If non-zero, this is an offset to be added to SP to redefine the CFA 245 when restoring the FP register from the stack. Only valid when generating 246 the epilogue. */ 247 static int epilogue_cfa_sp_offset; 248 249 /* Which tuning parameters to use. */ 250 static const struct riscv_tune_info *tune_info; 251 252 /* Which automaton to use for tuning. */ 253 enum riscv_microarchitecture_type riscv_microarchitecture; 254 255 /* Index R is the smallest register class that contains register R. */ 256 const enum reg_class riscv_regno_to_class[FIRST_PSEUDO_REGISTER] = { 257 GR_REGS, GR_REGS, GR_REGS, GR_REGS, 258 GR_REGS, GR_REGS, SIBCALL_REGS, SIBCALL_REGS, 259 JALR_REGS, JALR_REGS, SIBCALL_REGS, SIBCALL_REGS, 260 SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, 261 SIBCALL_REGS, SIBCALL_REGS, JALR_REGS, JALR_REGS, 262 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, 263 JALR_REGS, JALR_REGS, JALR_REGS, JALR_REGS, 264 SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, SIBCALL_REGS, 265 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 266 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 267 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 268 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 269 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 270 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 271 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 272 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 273 FRAME_REGS, FRAME_REGS, 274 }; 275 276 /* Costs to use when optimizing for rocket. */ 277 static const struct riscv_tune_info rocket_tune_info = { 278 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ 279 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ 280 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ 281 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ 282 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ 283 1, /* issue_rate */ 284 3, /* branch_cost */ 285 5, /* memory_cost */ 286 true, /* slow_unaligned_access */ 287 }; 288 289 /* Costs to use when optimizing for Sifive 7 Series. */ 290 static const struct riscv_tune_info sifive_7_tune_info = { 291 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_add */ 292 {COSTS_N_INSNS (4), COSTS_N_INSNS (5)}, /* fp_mul */ 293 {COSTS_N_INSNS (20), COSTS_N_INSNS (20)}, /* fp_div */ 294 {COSTS_N_INSNS (4), COSTS_N_INSNS (4)}, /* int_mul */ 295 {COSTS_N_INSNS (6), COSTS_N_INSNS (6)}, /* int_div */ 296 2, /* issue_rate */ 297 4, /* branch_cost */ 298 3, /* memory_cost */ 299 true, /* slow_unaligned_access */ 300 }; 301 302 /* Costs to use when optimizing for size. */ 303 static const struct riscv_tune_info optimize_size_tune_info = { 304 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_add */ 305 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_mul */ 306 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* fp_div */ 307 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_mul */ 308 {COSTS_N_INSNS (1), COSTS_N_INSNS (1)}, /* int_div */ 309 1, /* issue_rate */ 310 1, /* branch_cost */ 311 2, /* memory_cost */ 312 false, /* slow_unaligned_access */ 313 }; 314 315 static tree riscv_handle_fndecl_attribute (tree *, tree, tree, int, bool *); 316 static tree riscv_handle_type_attribute (tree *, tree, tree, int, bool *); 317 318 /* Defining target-specific uses of __attribute__. */ 319 static const struct attribute_spec riscv_attribute_table[] = 320 { 321 /* Syntax: { name, min_len, max_len, decl_required, type_required, 322 function_type_required, affects_type_identity, handler, 323 exclude } */ 324 325 /* The attribute telling no prologue/epilogue. */ 326 { "naked", 0, 0, true, false, false, false, 327 riscv_handle_fndecl_attribute, NULL }, 328 /* This attribute generates prologue/epilogue for interrupt handlers. */ 329 { "interrupt", 0, 1, false, true, true, false, 330 riscv_handle_type_attribute, NULL }, 331 332 /* The last attribute spec is set to be NULL. */ 333 { NULL, 0, 0, false, false, false, false, NULL, NULL } 334 }; 335 336 /* Order for the CLOBBERs/USEs of gpr_save. */ 337 static const unsigned gpr_save_reg_order[] = { 338 INVALID_REGNUM, T0_REGNUM, T1_REGNUM, RETURN_ADDR_REGNUM, 339 S0_REGNUM, S1_REGNUM, S2_REGNUM, S3_REGNUM, S4_REGNUM, 340 S5_REGNUM, S6_REGNUM, S7_REGNUM, S8_REGNUM, S9_REGNUM, 341 S10_REGNUM, S11_REGNUM 342 }; 343 344 /* A table describing all the processors GCC knows about. */ 345 static const struct riscv_cpu_info riscv_cpu_info_table[] = { 346 { "rocket", generic, &rocket_tune_info }, 347 { "sifive-3-series", generic, &rocket_tune_info }, 348 { "sifive-5-series", generic, &rocket_tune_info }, 349 { "sifive-7-series", sifive_7, &sifive_7_tune_info }, 350 { "size", generic, &optimize_size_tune_info }, 351 }; 352 353 /* Return the riscv_cpu_info entry for the given name string. */ 354 355 static const struct riscv_cpu_info * 356 riscv_parse_cpu (const char *cpu_string) 357 { 358 for (unsigned i = 0; i < ARRAY_SIZE (riscv_cpu_info_table); i++) 359 if (strcmp (riscv_cpu_info_table[i].name, cpu_string) == 0) 360 return riscv_cpu_info_table + i; 361 362 error ("unknown cpu %qs for %<-mtune%>", cpu_string); 363 return riscv_cpu_info_table; 364 } 365 366 /* Helper function for riscv_build_integer; arguments are as for 367 riscv_build_integer. */ 368 369 static int 370 riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], 371 HOST_WIDE_INT value, machine_mode mode) 372 { 373 HOST_WIDE_INT low_part = CONST_LOW_PART (value); 374 int cost = RISCV_MAX_INTEGER_OPS + 1, alt_cost; 375 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; 376 377 if (SMALL_OPERAND (value) || LUI_OPERAND (value)) 378 { 379 /* Simply ADDI or LUI. */ 380 codes[0].code = UNKNOWN; 381 codes[0].value = value; 382 return 1; 383 } 384 385 /* End with ADDI. When constructing HImode constants, do not generate any 386 intermediate value that is not itself a valid HImode constant. The 387 XORI case below will handle those remaining HImode constants. */ 388 if (low_part != 0 389 && (mode != HImode 390 || value - low_part <= ((1 << (GET_MODE_BITSIZE (HImode) - 1)) - 1))) 391 { 392 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value - low_part, mode); 393 if (alt_cost < cost) 394 { 395 alt_codes[alt_cost-1].code = PLUS; 396 alt_codes[alt_cost-1].value = low_part; 397 memcpy (codes, alt_codes, sizeof (alt_codes)); 398 cost = alt_cost; 399 } 400 } 401 402 /* End with XORI. */ 403 if (cost > 2 && (low_part < 0 || mode == HImode)) 404 { 405 alt_cost = 1 + riscv_build_integer_1 (alt_codes, value ^ low_part, mode); 406 if (alt_cost < cost) 407 { 408 alt_codes[alt_cost-1].code = XOR; 409 alt_codes[alt_cost-1].value = low_part; 410 memcpy (codes, alt_codes, sizeof (alt_codes)); 411 cost = alt_cost; 412 } 413 } 414 415 /* Eliminate trailing zeros and end with SLLI. */ 416 if (cost > 2 && (value & 1) == 0) 417 { 418 int shift = ctz_hwi (value); 419 unsigned HOST_WIDE_INT x = value; 420 x = sext_hwi (x >> shift, HOST_BITS_PER_WIDE_INT - shift); 421 422 /* Don't eliminate the lower 12 bits if LUI might apply. */ 423 if (shift > IMM_BITS && !SMALL_OPERAND (x) && LUI_OPERAND (x << IMM_BITS)) 424 shift -= IMM_BITS, x <<= IMM_BITS; 425 426 alt_cost = 1 + riscv_build_integer_1 (alt_codes, x, mode); 427 if (alt_cost < cost) 428 { 429 alt_codes[alt_cost-1].code = ASHIFT; 430 alt_codes[alt_cost-1].value = shift; 431 memcpy (codes, alt_codes, sizeof (alt_codes)); 432 cost = alt_cost; 433 } 434 } 435 436 gcc_assert (cost <= RISCV_MAX_INTEGER_OPS); 437 return cost; 438 } 439 440 /* Fill CODES with a sequence of rtl operations to load VALUE. 441 Return the number of operations needed. */ 442 443 static int 444 riscv_build_integer (struct riscv_integer_op *codes, HOST_WIDE_INT value, 445 machine_mode mode) 446 { 447 int cost = riscv_build_integer_1 (codes, value, mode); 448 449 /* Eliminate leading zeros and end with SRLI. */ 450 if (value > 0 && cost > 2) 451 { 452 struct riscv_integer_op alt_codes[RISCV_MAX_INTEGER_OPS]; 453 int alt_cost, shift = clz_hwi (value); 454 HOST_WIDE_INT shifted_val; 455 456 /* Try filling trailing bits with 1s. */ 457 shifted_val = (value << shift) | ((((HOST_WIDE_INT) 1) << shift) - 1); 458 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode); 459 if (alt_cost < cost) 460 { 461 alt_codes[alt_cost-1].code = LSHIFTRT; 462 alt_codes[alt_cost-1].value = shift; 463 memcpy (codes, alt_codes, sizeof (alt_codes)); 464 cost = alt_cost; 465 } 466 467 /* Try filling trailing bits with 0s. */ 468 shifted_val = value << shift; 469 alt_cost = 1 + riscv_build_integer_1 (alt_codes, shifted_val, mode); 470 if (alt_cost < cost) 471 { 472 alt_codes[alt_cost-1].code = LSHIFTRT; 473 alt_codes[alt_cost-1].value = shift; 474 memcpy (codes, alt_codes, sizeof (alt_codes)); 475 cost = alt_cost; 476 } 477 } 478 479 return cost; 480 } 481 482 /* Return the cost of constructing VAL in the event that a scratch 483 register is available. */ 484 485 static int 486 riscv_split_integer_cost (HOST_WIDE_INT val) 487 { 488 int cost; 489 unsigned HOST_WIDE_INT loval = sext_hwi (val, 32); 490 unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); 491 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 492 493 cost = 2 + riscv_build_integer (codes, loval, VOIDmode); 494 if (loval != hival) 495 cost += riscv_build_integer (codes, hival, VOIDmode); 496 497 return cost; 498 } 499 500 /* Return the cost of constructing the integer constant VAL. */ 501 502 static int 503 riscv_integer_cost (HOST_WIDE_INT val) 504 { 505 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 506 return MIN (riscv_build_integer (codes, val, VOIDmode), 507 riscv_split_integer_cost (val)); 508 } 509 510 /* Try to split a 64b integer into 32b parts, then reassemble. */ 511 512 static rtx 513 riscv_split_integer (HOST_WIDE_INT val, machine_mode mode) 514 { 515 unsigned HOST_WIDE_INT loval = sext_hwi (val, 32); 516 unsigned HOST_WIDE_INT hival = sext_hwi ((val - loval) >> 32, 32); 517 rtx hi = gen_reg_rtx (mode), lo = gen_reg_rtx (mode); 518 519 riscv_move_integer (hi, hi, hival, mode, FALSE); 520 riscv_move_integer (lo, lo, loval, mode, FALSE); 521 522 hi = gen_rtx_fmt_ee (ASHIFT, mode, hi, GEN_INT (32)); 523 hi = force_reg (mode, hi); 524 525 return gen_rtx_fmt_ee (PLUS, mode, hi, lo); 526 } 527 528 /* Return true if X is a thread-local symbol. */ 529 530 static bool 531 riscv_tls_symbol_p (const_rtx x) 532 { 533 return SYMBOL_REF_P (x) && SYMBOL_REF_TLS_MODEL (x) != 0; 534 } 535 536 /* Return true if symbol X binds locally. */ 537 538 static bool 539 riscv_symbol_binds_local_p (const_rtx x) 540 { 541 if (SYMBOL_REF_P (x)) 542 return (SYMBOL_REF_DECL (x) 543 ? targetm.binds_local_p (SYMBOL_REF_DECL (x)) 544 : SYMBOL_REF_LOCAL_P (x)); 545 else 546 return false; 547 } 548 549 /* Return the method that should be used to access SYMBOL_REF or 550 LABEL_REF X. */ 551 552 static enum riscv_symbol_type 553 riscv_classify_symbol (const_rtx x) 554 { 555 if (riscv_tls_symbol_p (x)) 556 return SYMBOL_TLS; 557 558 if (GET_CODE (x) == SYMBOL_REF && flag_pic && !riscv_symbol_binds_local_p (x)) 559 return SYMBOL_GOT_DISP; 560 561 return riscv_cmodel == CM_MEDLOW ? SYMBOL_ABSOLUTE : SYMBOL_PCREL; 562 } 563 564 /* Classify the base of symbolic expression X. */ 565 566 enum riscv_symbol_type 567 riscv_classify_symbolic_expression (rtx x) 568 { 569 rtx offset; 570 571 split_const (x, &x, &offset); 572 if (UNSPEC_ADDRESS_P (x)) 573 return UNSPEC_ADDRESS_TYPE (x); 574 575 return riscv_classify_symbol (x); 576 } 577 578 /* Return true if X is a symbolic constant. If it is, store the type of 579 the symbol in *SYMBOL_TYPE. */ 580 581 bool 582 riscv_symbolic_constant_p (rtx x, enum riscv_symbol_type *symbol_type) 583 { 584 rtx offset; 585 586 split_const (x, &x, &offset); 587 if (UNSPEC_ADDRESS_P (x)) 588 { 589 *symbol_type = UNSPEC_ADDRESS_TYPE (x); 590 x = UNSPEC_ADDRESS (x); 591 } 592 else if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) 593 *symbol_type = riscv_classify_symbol (x); 594 else 595 return false; 596 597 if (offset == const0_rtx) 598 return true; 599 600 /* Nonzero offsets are only valid for references that don't use the GOT. */ 601 switch (*symbol_type) 602 { 603 case SYMBOL_ABSOLUTE: 604 case SYMBOL_PCREL: 605 case SYMBOL_TLS_LE: 606 /* GAS rejects offsets outside the range [-2^31, 2^31-1]. */ 607 return sext_hwi (INTVAL (offset), 32) == INTVAL (offset); 608 609 default: 610 return false; 611 } 612 } 613 614 /* Returns the number of instructions necessary to reference a symbol. */ 615 616 static int riscv_symbol_insns (enum riscv_symbol_type type) 617 { 618 switch (type) 619 { 620 case SYMBOL_TLS: return 0; /* Depends on the TLS model. */ 621 case SYMBOL_ABSOLUTE: return 2; /* LUI + the reference. */ 622 case SYMBOL_PCREL: return 2; /* AUIPC + the reference. */ 623 case SYMBOL_TLS_LE: return 3; /* LUI + ADD TP + the reference. */ 624 case SYMBOL_GOT_DISP: return 3; /* AUIPC + LD GOT + the reference. */ 625 default: gcc_unreachable (); 626 } 627 } 628 629 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ 630 631 static bool 632 riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 633 { 634 return riscv_const_insns (x) > 0; 635 } 636 637 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ 638 639 static bool 640 riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 641 { 642 enum riscv_symbol_type type; 643 rtx base, offset; 644 645 /* There is no assembler syntax for expressing an address-sized 646 high part. */ 647 if (GET_CODE (x) == HIGH) 648 return true; 649 650 split_const (x, &base, &offset); 651 if (riscv_symbolic_constant_p (base, &type)) 652 { 653 /* As an optimization, don't spill symbolic constants that are as 654 cheap to rematerialize as to access in the constant pool. */ 655 if (SMALL_OPERAND (INTVAL (offset)) && riscv_symbol_insns (type) > 0) 656 return true; 657 658 /* As an optimization, avoid needlessly generate dynamic relocations. */ 659 if (flag_pic) 660 return true; 661 } 662 663 /* TLS symbols must be computed by riscv_legitimize_move. */ 664 if (tls_referenced_p (x)) 665 return true; 666 667 return false; 668 } 669 670 /* Return true if register REGNO is a valid base register for mode MODE. 671 STRICT_P is true if REG_OK_STRICT is in effect. */ 672 673 int 674 riscv_regno_mode_ok_for_base_p (int regno, 675 machine_mode mode ATTRIBUTE_UNUSED, 676 bool strict_p) 677 { 678 if (!HARD_REGISTER_NUM_P (regno)) 679 { 680 if (!strict_p) 681 return true; 682 regno = reg_renumber[regno]; 683 } 684 685 /* These fake registers will be eliminated to either the stack or 686 hard frame pointer, both of which are usually valid base registers. 687 Reload deals with the cases where the eliminated form isn't valid. */ 688 if (regno == ARG_POINTER_REGNUM || regno == FRAME_POINTER_REGNUM) 689 return true; 690 691 return GP_REG_P (regno); 692 } 693 694 /* Return true if X is a valid base register for mode MODE. 695 STRICT_P is true if REG_OK_STRICT is in effect. */ 696 697 static bool 698 riscv_valid_base_register_p (rtx x, machine_mode mode, bool strict_p) 699 { 700 if (!strict_p && GET_CODE (x) == SUBREG) 701 x = SUBREG_REG (x); 702 703 return (REG_P (x) 704 && riscv_regno_mode_ok_for_base_p (REGNO (x), mode, strict_p)); 705 } 706 707 /* Return true if, for every base register BASE_REG, (plus BASE_REG X) 708 can address a value of mode MODE. */ 709 710 static bool 711 riscv_valid_offset_p (rtx x, machine_mode mode) 712 { 713 /* Check that X is a signed 12-bit number. */ 714 if (!const_arith_operand (x, Pmode)) 715 return false; 716 717 /* We may need to split multiword moves, so make sure that every word 718 is accessible. */ 719 if (GET_MODE_SIZE (mode) > UNITS_PER_WORD 720 && !SMALL_OPERAND (INTVAL (x) + GET_MODE_SIZE (mode) - UNITS_PER_WORD)) 721 return false; 722 723 return true; 724 } 725 726 /* Should a symbol of type SYMBOL_TYPE should be split in two? */ 727 728 bool 729 riscv_split_symbol_type (enum riscv_symbol_type symbol_type) 730 { 731 if (symbol_type == SYMBOL_TLS_LE) 732 return true; 733 734 if (!TARGET_EXPLICIT_RELOCS) 735 return false; 736 737 return symbol_type == SYMBOL_ABSOLUTE || symbol_type == SYMBOL_PCREL; 738 } 739 740 /* Return true if a LO_SUM can address a value of mode MODE when the 741 LO_SUM symbol has type SYM_TYPE. X is the LO_SUM second operand, which 742 is used when the mode is BLKmode. */ 743 744 static bool 745 riscv_valid_lo_sum_p (enum riscv_symbol_type sym_type, machine_mode mode, 746 rtx x) 747 { 748 int align, size; 749 750 /* Check that symbols of type SYMBOL_TYPE can be used to access values 751 of mode MODE. */ 752 if (riscv_symbol_insns (sym_type) == 0) 753 return false; 754 755 /* Check that there is a known low-part relocation. */ 756 if (!riscv_split_symbol_type (sym_type)) 757 return false; 758 759 /* We can't tell size or alignment when we have BLKmode, so try extracing a 760 decl from the symbol if possible. */ 761 if (mode == BLKmode) 762 { 763 rtx offset; 764 765 /* Extract the symbol from the LO_SUM operand, if any. */ 766 split_const (x, &x, &offset); 767 768 /* Might be a CODE_LABEL. We can compute align but not size for that, 769 so don't bother trying to handle it. */ 770 if (!SYMBOL_REF_P (x)) 771 return false; 772 773 /* Use worst case assumptions if we don't have a SYMBOL_REF_DECL. */ 774 align = (SYMBOL_REF_DECL (x) 775 ? DECL_ALIGN (SYMBOL_REF_DECL (x)) 776 : 1); 777 size = (SYMBOL_REF_DECL (x) && DECL_SIZE (SYMBOL_REF_DECL (x)) 778 ? tree_to_uhwi (DECL_SIZE (SYMBOL_REF_DECL (x))) 779 : 2*BITS_PER_WORD); 780 } 781 else 782 { 783 align = GET_MODE_ALIGNMENT (mode); 784 size = GET_MODE_BITSIZE (mode); 785 } 786 787 /* We may need to split multiword moves, so make sure that each word 788 can be accessed without inducing a carry. */ 789 if (size > BITS_PER_WORD 790 && (!TARGET_STRICT_ALIGN || size > align)) 791 return false; 792 793 return true; 794 } 795 796 /* Return true if X is a valid address for machine mode MODE. If it is, 797 fill in INFO appropriately. STRICT_P is true if REG_OK_STRICT is in 798 effect. */ 799 800 static bool 801 riscv_classify_address (struct riscv_address_info *info, rtx x, 802 machine_mode mode, bool strict_p) 803 { 804 switch (GET_CODE (x)) 805 { 806 case REG: 807 case SUBREG: 808 info->type = ADDRESS_REG; 809 info->reg = x; 810 info->offset = const0_rtx; 811 return riscv_valid_base_register_p (info->reg, mode, strict_p); 812 813 case PLUS: 814 info->type = ADDRESS_REG; 815 info->reg = XEXP (x, 0); 816 info->offset = XEXP (x, 1); 817 return (riscv_valid_base_register_p (info->reg, mode, strict_p) 818 && riscv_valid_offset_p (info->offset, mode)); 819 820 case LO_SUM: 821 info->type = ADDRESS_LO_SUM; 822 info->reg = XEXP (x, 0); 823 info->offset = XEXP (x, 1); 824 /* We have to trust the creator of the LO_SUM to do something vaguely 825 sane. Target-independent code that creates a LO_SUM should also 826 create and verify the matching HIGH. Target-independent code that 827 adds an offset to a LO_SUM must prove that the offset will not 828 induce a carry. Failure to do either of these things would be 829 a bug, and we are not required to check for it here. The RISC-V 830 backend itself should only create LO_SUMs for valid symbolic 831 constants, with the high part being either a HIGH or a copy 832 of _gp. */ 833 info->symbol_type 834 = riscv_classify_symbolic_expression (info->offset); 835 return (riscv_valid_base_register_p (info->reg, mode, strict_p) 836 && riscv_valid_lo_sum_p (info->symbol_type, mode, info->offset)); 837 838 case CONST_INT: 839 /* Small-integer addresses don't occur very often, but they 840 are legitimate if x0 is a valid base register. */ 841 info->type = ADDRESS_CONST_INT; 842 return SMALL_OPERAND (INTVAL (x)); 843 844 default: 845 return false; 846 } 847 } 848 849 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ 850 851 static bool 852 riscv_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) 853 { 854 struct riscv_address_info addr; 855 856 return riscv_classify_address (&addr, x, mode, strict_p); 857 } 858 859 /* Return the number of instructions needed to load or store a value 860 of mode MODE at address X. Return 0 if X isn't valid for MODE. 861 Assume that multiword moves may need to be split into word moves 862 if MIGHT_SPLIT_P, otherwise assume that a single load or store is 863 enough. */ 864 865 int 866 riscv_address_insns (rtx x, machine_mode mode, bool might_split_p) 867 { 868 struct riscv_address_info addr = {}; 869 int n = 1; 870 871 if (!riscv_classify_address (&addr, x, mode, false)) 872 { 873 /* This could be a pattern from the pic.md file. In which case we want 874 this address to always have a cost of 3 to make it as expensive as the 875 most expensive symbol. This prevents constant propagation from 876 preferring symbols over register plus offset. */ 877 return 3; 878 } 879 880 /* BLKmode is used for single unaligned loads and stores and should 881 not count as a multiword mode. */ 882 if (mode != BLKmode && might_split_p) 883 n += (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 884 885 if (addr.type == ADDRESS_LO_SUM) 886 n += riscv_symbol_insns (addr.symbol_type) - 1; 887 888 return n; 889 } 890 891 /* Return the number of instructions needed to load constant X. 892 Return 0 if X isn't a valid constant. */ 893 894 int 895 riscv_const_insns (rtx x) 896 { 897 enum riscv_symbol_type symbol_type; 898 rtx offset; 899 900 switch (GET_CODE (x)) 901 { 902 case HIGH: 903 if (!riscv_symbolic_constant_p (XEXP (x, 0), &symbol_type) 904 || !riscv_split_symbol_type (symbol_type)) 905 return 0; 906 907 /* This is simply an LUI. */ 908 return 1; 909 910 case CONST_INT: 911 { 912 int cost = riscv_integer_cost (INTVAL (x)); 913 /* Force complicated constants to memory. */ 914 return cost < 4 ? cost : 0; 915 } 916 917 case CONST_DOUBLE: 918 case CONST_VECTOR: 919 /* We can use x0 to load floating-point zero. */ 920 return x == CONST0_RTX (GET_MODE (x)) ? 1 : 0; 921 922 case CONST: 923 /* See if we can refer to X directly. */ 924 if (riscv_symbolic_constant_p (x, &symbol_type)) 925 return riscv_symbol_insns (symbol_type); 926 927 /* Otherwise try splitting the constant into a base and offset. */ 928 split_const (x, &x, &offset); 929 if (offset != 0) 930 { 931 int n = riscv_const_insns (x); 932 if (n != 0) 933 return n + riscv_integer_cost (INTVAL (offset)); 934 } 935 return 0; 936 937 case SYMBOL_REF: 938 case LABEL_REF: 939 return riscv_symbol_insns (riscv_classify_symbol (x)); 940 941 default: 942 return 0; 943 } 944 } 945 946 /* X is a doubleword constant that can be handled by splitting it into 947 two words and loading each word separately. Return the number of 948 instructions required to do this. */ 949 950 int 951 riscv_split_const_insns (rtx x) 952 { 953 unsigned int low, high; 954 955 low = riscv_const_insns (riscv_subword (x, false)); 956 high = riscv_const_insns (riscv_subword (x, true)); 957 gcc_assert (low > 0 && high > 0); 958 return low + high; 959 } 960 961 /* Return the number of instructions needed to implement INSN, 962 given that it loads from or stores to MEM. */ 963 964 int 965 riscv_load_store_insns (rtx mem, rtx_insn *insn) 966 { 967 machine_mode mode; 968 bool might_split_p; 969 rtx set; 970 971 gcc_assert (MEM_P (mem)); 972 mode = GET_MODE (mem); 973 974 /* Try to prove that INSN does not need to be split. */ 975 might_split_p = true; 976 if (GET_MODE_BITSIZE (mode) <= 32) 977 might_split_p = false; 978 else if (GET_MODE_BITSIZE (mode) == 64) 979 { 980 set = single_set (insn); 981 if (set && !riscv_split_64bit_move_p (SET_DEST (set), SET_SRC (set))) 982 might_split_p = false; 983 } 984 985 return riscv_address_insns (XEXP (mem, 0), mode, might_split_p); 986 } 987 988 /* Emit a move from SRC to DEST. Assume that the move expanders can 989 handle all moves if !can_create_pseudo_p (). The distinction is 990 important because, unlike emit_move_insn, the move expanders know 991 how to force Pmode objects into the constant pool even when the 992 constant pool address is not itself legitimate. */ 993 994 rtx 995 riscv_emit_move (rtx dest, rtx src) 996 { 997 return (can_create_pseudo_p () 998 ? emit_move_insn (dest, src) 999 : emit_move_insn_1 (dest, src)); 1000 } 1001 1002 /* Emit an instruction of the form (set TARGET SRC). */ 1003 1004 static rtx 1005 riscv_emit_set (rtx target, rtx src) 1006 { 1007 emit_insn (gen_rtx_SET (target, src)); 1008 return target; 1009 } 1010 1011 /* Emit an instruction of the form (set DEST (CODE X Y)). */ 1012 1013 static rtx 1014 riscv_emit_binary (enum rtx_code code, rtx dest, rtx x, rtx y) 1015 { 1016 return riscv_emit_set (dest, gen_rtx_fmt_ee (code, GET_MODE (dest), x, y)); 1017 } 1018 1019 /* Compute (CODE X Y) and store the result in a new register 1020 of mode MODE. Return that new register. */ 1021 1022 static rtx 1023 riscv_force_binary (machine_mode mode, enum rtx_code code, rtx x, rtx y) 1024 { 1025 return riscv_emit_binary (code, gen_reg_rtx (mode), x, y); 1026 } 1027 1028 /* Copy VALUE to a register and return that register. If new pseudos 1029 are allowed, copy it into a new register, otherwise use DEST. */ 1030 1031 static rtx 1032 riscv_force_temporary (rtx dest, rtx value, bool in_splitter) 1033 { 1034 /* We can't call gen_reg_rtx from a splitter, because this might realloc 1035 the regno_reg_rtx array, which would invalidate reg rtx pointers in the 1036 combine undo buffer. */ 1037 if (can_create_pseudo_p () && !in_splitter) 1038 return force_reg (Pmode, value); 1039 else 1040 { 1041 riscv_emit_move (dest, value); 1042 return dest; 1043 } 1044 } 1045 1046 /* Wrap symbol or label BASE in an UNSPEC address of type SYMBOL_TYPE, 1047 then add CONST_INT OFFSET to the result. */ 1048 1049 static rtx 1050 riscv_unspec_address_offset (rtx base, rtx offset, 1051 enum riscv_symbol_type symbol_type) 1052 { 1053 base = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, base), 1054 UNSPEC_ADDRESS_FIRST + symbol_type); 1055 if (offset != const0_rtx) 1056 base = gen_rtx_PLUS (Pmode, base, offset); 1057 return gen_rtx_CONST (Pmode, base); 1058 } 1059 1060 /* Return an UNSPEC address with underlying address ADDRESS and symbol 1061 type SYMBOL_TYPE. */ 1062 1063 rtx 1064 riscv_unspec_address (rtx address, enum riscv_symbol_type symbol_type) 1065 { 1066 rtx base, offset; 1067 1068 split_const (address, &base, &offset); 1069 return riscv_unspec_address_offset (base, offset, symbol_type); 1070 } 1071 1072 /* If OP is an UNSPEC address, return the address to which it refers, 1073 otherwise return OP itself. */ 1074 1075 static rtx 1076 riscv_strip_unspec_address (rtx op) 1077 { 1078 rtx base, offset; 1079 1080 split_const (op, &base, &offset); 1081 if (UNSPEC_ADDRESS_P (base)) 1082 op = plus_constant (Pmode, UNSPEC_ADDRESS (base), INTVAL (offset)); 1083 return op; 1084 } 1085 1086 /* If riscv_unspec_address (ADDR, SYMBOL_TYPE) is a 32-bit value, add the 1087 high part to BASE and return the result. Just return BASE otherwise. 1088 TEMP is as for riscv_force_temporary. 1089 1090 The returned expression can be used as the first operand to a LO_SUM. */ 1091 1092 static rtx 1093 riscv_unspec_offset_high (rtx temp, rtx addr, enum riscv_symbol_type symbol_type) 1094 { 1095 addr = gen_rtx_HIGH (Pmode, riscv_unspec_address (addr, symbol_type)); 1096 return riscv_force_temporary (temp, addr, FALSE); 1097 } 1098 1099 /* Load an entry from the GOT for a TLS GD access. */ 1100 1101 static rtx riscv_got_load_tls_gd (rtx dest, rtx sym) 1102 { 1103 if (Pmode == DImode) 1104 return gen_got_load_tls_gddi (dest, sym); 1105 else 1106 return gen_got_load_tls_gdsi (dest, sym); 1107 } 1108 1109 /* Load an entry from the GOT for a TLS IE access. */ 1110 1111 static rtx riscv_got_load_tls_ie (rtx dest, rtx sym) 1112 { 1113 if (Pmode == DImode) 1114 return gen_got_load_tls_iedi (dest, sym); 1115 else 1116 return gen_got_load_tls_iesi (dest, sym); 1117 } 1118 1119 /* Add in the thread pointer for a TLS LE access. */ 1120 1121 static rtx riscv_tls_add_tp_le (rtx dest, rtx base, rtx sym) 1122 { 1123 rtx tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); 1124 if (Pmode == DImode) 1125 return gen_tls_add_tp_ledi (dest, base, tp, sym); 1126 else 1127 return gen_tls_add_tp_lesi (dest, base, tp, sym); 1128 } 1129 1130 /* If MODE is MAX_MACHINE_MODE, ADDR appears as a move operand, otherwise 1131 it appears in a MEM of that mode. Return true if ADDR is a legitimate 1132 constant in that context and can be split into high and low parts. 1133 If so, and if LOW_OUT is nonnull, emit the high part and store the 1134 low part in *LOW_OUT. Leave *LOW_OUT unchanged otherwise. 1135 1136 TEMP is as for riscv_force_temporary and is used to load the high 1137 part into a register. 1138 1139 When MODE is MAX_MACHINE_MODE, the low part is guaranteed to be 1140 a legitimize SET_SRC for an .md pattern, otherwise the low part 1141 is guaranteed to be a legitimate address for mode MODE. */ 1142 1143 bool 1144 riscv_split_symbol (rtx temp, rtx addr, machine_mode mode, rtx *low_out, 1145 bool in_splitter) 1146 { 1147 enum riscv_symbol_type symbol_type; 1148 1149 if ((GET_CODE (addr) == HIGH && mode == MAX_MACHINE_MODE) 1150 || !riscv_symbolic_constant_p (addr, &symbol_type) 1151 || riscv_symbol_insns (symbol_type) == 0 1152 || !riscv_split_symbol_type (symbol_type)) 1153 return false; 1154 1155 if (low_out) 1156 switch (symbol_type) 1157 { 1158 case SYMBOL_ABSOLUTE: 1159 { 1160 rtx high = gen_rtx_HIGH (Pmode, copy_rtx (addr)); 1161 high = riscv_force_temporary (temp, high, in_splitter); 1162 *low_out = gen_rtx_LO_SUM (Pmode, high, addr); 1163 } 1164 break; 1165 1166 case SYMBOL_PCREL: 1167 { 1168 static unsigned seqno; 1169 char buf[32]; 1170 rtx label; 1171 1172 ssize_t bytes = snprintf (buf, sizeof (buf), ".LA%u", seqno); 1173 gcc_assert ((size_t) bytes < sizeof (buf)); 1174 1175 label = gen_rtx_SYMBOL_REF (Pmode, ggc_strdup (buf)); 1176 SYMBOL_REF_FLAGS (label) |= SYMBOL_FLAG_LOCAL; 1177 /* ??? Ugly hack to make weak symbols work. May need to change the 1178 RTL for the auipc and/or low patterns to get a better fix for 1179 this. */ 1180 if (! nonzero_address_p (addr)) 1181 SYMBOL_REF_WEAK (label) = 1; 1182 1183 if (temp == NULL) 1184 temp = gen_reg_rtx (Pmode); 1185 1186 if (Pmode == DImode) 1187 emit_insn (gen_auipcdi (temp, copy_rtx (addr), GEN_INT (seqno))); 1188 else 1189 emit_insn (gen_auipcsi (temp, copy_rtx (addr), GEN_INT (seqno))); 1190 1191 *low_out = gen_rtx_LO_SUM (Pmode, temp, label); 1192 1193 seqno++; 1194 } 1195 break; 1196 1197 default: 1198 gcc_unreachable (); 1199 } 1200 1201 return true; 1202 } 1203 1204 /* Return a legitimate address for REG + OFFSET. TEMP is as for 1205 riscv_force_temporary; it is only needed when OFFSET is not a 1206 SMALL_OPERAND. */ 1207 1208 static rtx 1209 riscv_add_offset (rtx temp, rtx reg, HOST_WIDE_INT offset) 1210 { 1211 if (!SMALL_OPERAND (offset)) 1212 { 1213 rtx high; 1214 1215 /* Leave OFFSET as a 16-bit offset and put the excess in HIGH. 1216 The addition inside the macro CONST_HIGH_PART may cause an 1217 overflow, so we need to force a sign-extension check. */ 1218 high = gen_int_mode (CONST_HIGH_PART (offset), Pmode); 1219 offset = CONST_LOW_PART (offset); 1220 high = riscv_force_temporary (temp, high, FALSE); 1221 reg = riscv_force_temporary (temp, gen_rtx_PLUS (Pmode, high, reg), 1222 FALSE); 1223 } 1224 return plus_constant (Pmode, reg, offset); 1225 } 1226 1227 /* The __tls_get_attr symbol. */ 1228 static GTY(()) rtx riscv_tls_symbol; 1229 1230 /* Return an instruction sequence that calls __tls_get_addr. SYM is 1231 the TLS symbol we are referencing and TYPE is the symbol type to use 1232 (either global dynamic or local dynamic). RESULT is an RTX for the 1233 return value location. */ 1234 1235 static rtx_insn * 1236 riscv_call_tls_get_addr (rtx sym, rtx result) 1237 { 1238 rtx a0 = gen_rtx_REG (Pmode, GP_ARG_FIRST), func; 1239 rtx_insn *insn; 1240 1241 if (!riscv_tls_symbol) 1242 riscv_tls_symbol = init_one_libfunc ("__tls_get_addr"); 1243 func = gen_rtx_MEM (FUNCTION_MODE, riscv_tls_symbol); 1244 1245 start_sequence (); 1246 1247 emit_insn (riscv_got_load_tls_gd (a0, sym)); 1248 insn = emit_call_insn (gen_call_value (result, func, const0_rtx, NULL)); 1249 RTL_CONST_CALL_P (insn) = 1; 1250 use_reg (&CALL_INSN_FUNCTION_USAGE (insn), a0); 1251 insn = get_insns (); 1252 1253 end_sequence (); 1254 1255 return insn; 1256 } 1257 1258 /* Generate the code to access LOC, a thread-local SYMBOL_REF, and return 1259 its address. The return value will be both a valid address and a valid 1260 SET_SRC (either a REG or a LO_SUM). */ 1261 1262 static rtx 1263 riscv_legitimize_tls_address (rtx loc) 1264 { 1265 rtx dest, tp, tmp; 1266 enum tls_model model = SYMBOL_REF_TLS_MODEL (loc); 1267 1268 #if 0 1269 /* TLS copy relocs are now deprecated and should not be used. */ 1270 /* Since we support TLS copy relocs, non-PIC TLS accesses may all use LE. */ 1271 if (!flag_pic) 1272 model = TLS_MODEL_LOCAL_EXEC; 1273 #endif 1274 1275 switch (model) 1276 { 1277 case TLS_MODEL_LOCAL_DYNAMIC: 1278 /* Rely on section anchors for the optimization that LDM TLS 1279 provides. The anchor's address is loaded with GD TLS. */ 1280 case TLS_MODEL_GLOBAL_DYNAMIC: 1281 tmp = gen_rtx_REG (Pmode, GP_RETURN); 1282 dest = gen_reg_rtx (Pmode); 1283 emit_libcall_block (riscv_call_tls_get_addr (loc, tmp), dest, tmp, loc); 1284 break; 1285 1286 case TLS_MODEL_INITIAL_EXEC: 1287 /* la.tls.ie; tp-relative add */ 1288 tp = gen_rtx_REG (Pmode, THREAD_POINTER_REGNUM); 1289 tmp = gen_reg_rtx (Pmode); 1290 emit_insn (riscv_got_load_tls_ie (tmp, loc)); 1291 dest = gen_reg_rtx (Pmode); 1292 emit_insn (gen_add3_insn (dest, tmp, tp)); 1293 break; 1294 1295 case TLS_MODEL_LOCAL_EXEC: 1296 tmp = riscv_unspec_offset_high (NULL, loc, SYMBOL_TLS_LE); 1297 dest = gen_reg_rtx (Pmode); 1298 emit_insn (riscv_tls_add_tp_le (dest, tmp, loc)); 1299 dest = gen_rtx_LO_SUM (Pmode, dest, 1300 riscv_unspec_address (loc, SYMBOL_TLS_LE)); 1301 break; 1302 1303 default: 1304 gcc_unreachable (); 1305 } 1306 return dest; 1307 } 1308 1309 /* If X is not a valid address for mode MODE, force it into a register. */ 1310 1311 static rtx 1312 riscv_force_address (rtx x, machine_mode mode) 1313 { 1314 if (!riscv_legitimate_address_p (mode, x, false)) 1315 x = force_reg (Pmode, x); 1316 return x; 1317 } 1318 1319 /* This function is used to implement LEGITIMIZE_ADDRESS. If X can 1320 be legitimized in a way that the generic machinery might not expect, 1321 return a new address, otherwise return NULL. MODE is the mode of 1322 the memory being accessed. */ 1323 1324 static rtx 1325 riscv_legitimize_address (rtx x, rtx oldx ATTRIBUTE_UNUSED, 1326 machine_mode mode) 1327 { 1328 rtx addr; 1329 1330 if (riscv_tls_symbol_p (x)) 1331 return riscv_legitimize_tls_address (x); 1332 1333 /* See if the address can split into a high part and a LO_SUM. */ 1334 if (riscv_split_symbol (NULL, x, mode, &addr, FALSE)) 1335 return riscv_force_address (addr, mode); 1336 1337 /* Handle BASE + OFFSET using riscv_add_offset. */ 1338 if (GET_CODE (x) == PLUS && CONST_INT_P (XEXP (x, 1)) 1339 && INTVAL (XEXP (x, 1)) != 0) 1340 { 1341 rtx base = XEXP (x, 0); 1342 HOST_WIDE_INT offset = INTVAL (XEXP (x, 1)); 1343 1344 if (!riscv_valid_base_register_p (base, mode, false)) 1345 base = copy_to_mode_reg (Pmode, base); 1346 addr = riscv_add_offset (NULL, base, offset); 1347 return riscv_force_address (addr, mode); 1348 } 1349 1350 return x; 1351 } 1352 1353 /* Load VALUE into DEST. TEMP is as for riscv_force_temporary. ORIG_MODE 1354 is the original src mode before promotion. */ 1355 1356 void 1357 riscv_move_integer (rtx temp, rtx dest, HOST_WIDE_INT value, 1358 machine_mode orig_mode, bool in_splitter) 1359 { 1360 struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS]; 1361 machine_mode mode; 1362 int i, num_ops; 1363 rtx x; 1364 1365 /* We can't call gen_reg_rtx from a splitter, because this might realloc 1366 the regno_reg_rtx array, which would invalidate reg rtx pointers in the 1367 combine undo buffer. */ 1368 bool can_create_pseudo = can_create_pseudo_p () && ! in_splitter; 1369 1370 mode = GET_MODE (dest); 1371 /* We use the original mode for the riscv_build_integer call, because HImode 1372 values are given special treatment. */ 1373 num_ops = riscv_build_integer (codes, value, orig_mode); 1374 1375 if (can_create_pseudo && num_ops > 2 /* not a simple constant */ 1376 && num_ops >= riscv_split_integer_cost (value)) 1377 x = riscv_split_integer (value, mode); 1378 else 1379 { 1380 /* Apply each binary operation to X. */ 1381 x = GEN_INT (codes[0].value); 1382 1383 for (i = 1; i < num_ops; i++) 1384 { 1385 if (!can_create_pseudo) 1386 x = riscv_emit_set (temp, x); 1387 else 1388 x = force_reg (mode, x); 1389 1390 x = gen_rtx_fmt_ee (codes[i].code, mode, x, GEN_INT (codes[i].value)); 1391 } 1392 } 1393 1394 riscv_emit_set (dest, x); 1395 } 1396 1397 /* Subroutine of riscv_legitimize_move. Move constant SRC into register 1398 DEST given that SRC satisfies immediate_operand but doesn't satisfy 1399 move_operand. */ 1400 1401 static void 1402 riscv_legitimize_const_move (machine_mode mode, rtx dest, rtx src) 1403 { 1404 rtx base, offset; 1405 1406 /* Split moves of big integers into smaller pieces. */ 1407 if (splittable_const_int_operand (src, mode)) 1408 { 1409 riscv_move_integer (dest, dest, INTVAL (src), mode, FALSE); 1410 return; 1411 } 1412 1413 /* Split moves of symbolic constants into high/low pairs. */ 1414 if (riscv_split_symbol (dest, src, MAX_MACHINE_MODE, &src, FALSE)) 1415 { 1416 riscv_emit_set (dest, src); 1417 return; 1418 } 1419 1420 /* Generate the appropriate access sequences for TLS symbols. */ 1421 if (riscv_tls_symbol_p (src)) 1422 { 1423 riscv_emit_move (dest, riscv_legitimize_tls_address (src)); 1424 return; 1425 } 1426 1427 /* If we have (const (plus symbol offset)), and that expression cannot 1428 be forced into memory, load the symbol first and add in the offset. Also 1429 prefer to do this even if the constant _can_ be forced into memory, as it 1430 usually produces better code. */ 1431 split_const (src, &base, &offset); 1432 if (offset != const0_rtx 1433 && (targetm.cannot_force_const_mem (mode, src) || can_create_pseudo_p ())) 1434 { 1435 base = riscv_force_temporary (dest, base, FALSE); 1436 riscv_emit_move (dest, riscv_add_offset (NULL, base, INTVAL (offset))); 1437 return; 1438 } 1439 1440 src = force_const_mem (mode, src); 1441 1442 /* When using explicit relocs, constant pool references are sometimes 1443 not legitimate addresses. */ 1444 riscv_split_symbol (dest, XEXP (src, 0), mode, &XEXP (src, 0), FALSE); 1445 riscv_emit_move (dest, src); 1446 } 1447 1448 /* If (set DEST SRC) is not a valid move instruction, emit an equivalent 1449 sequence that is valid. */ 1450 1451 bool 1452 riscv_legitimize_move (machine_mode mode, rtx dest, rtx src) 1453 { 1454 if (!register_operand (dest, mode) && !reg_or_0_operand (src, mode)) 1455 { 1456 rtx reg; 1457 1458 if (GET_CODE (src) == CONST_INT) 1459 { 1460 /* Apply the equivalent of PROMOTE_MODE here for constants to 1461 improve cse. */ 1462 machine_mode promoted_mode = mode; 1463 if (GET_MODE_CLASS (mode) == MODE_INT 1464 && GET_MODE_SIZE (mode) < UNITS_PER_WORD) 1465 promoted_mode = word_mode; 1466 1467 if (splittable_const_int_operand (src, mode)) 1468 { 1469 reg = gen_reg_rtx (promoted_mode); 1470 riscv_move_integer (reg, reg, INTVAL (src), mode, FALSE); 1471 } 1472 else 1473 reg = force_reg (promoted_mode, src); 1474 1475 if (promoted_mode != mode) 1476 reg = gen_lowpart (mode, reg); 1477 } 1478 else 1479 reg = force_reg (mode, src); 1480 riscv_emit_move (dest, reg); 1481 return true; 1482 } 1483 1484 /* We need to deal with constants that would be legitimate 1485 immediate_operands but aren't legitimate move_operands. */ 1486 if (CONSTANT_P (src) && !move_operand (src, mode)) 1487 { 1488 riscv_legitimize_const_move (mode, dest, src); 1489 set_unique_reg_note (get_last_insn (), REG_EQUAL, copy_rtx (src)); 1490 return true; 1491 } 1492 1493 /* RISC-V GCC may generate non-legitimate address due to we provide some 1494 pattern for optimize access PIC local symbol and it's make GCC generate 1495 unrecognizable instruction during optmizing. */ 1496 1497 if (MEM_P (dest) && !riscv_legitimate_address_p (mode, XEXP (dest, 0), 1498 reload_completed)) 1499 { 1500 XEXP (dest, 0) = riscv_force_address (XEXP (dest, 0), mode); 1501 } 1502 1503 if (MEM_P (src) && !riscv_legitimate_address_p (mode, XEXP (src, 0), 1504 reload_completed)) 1505 { 1506 XEXP (src, 0) = riscv_force_address (XEXP (src, 0), mode); 1507 } 1508 1509 return false; 1510 } 1511 1512 /* Return true if there is an instruction that implements CODE and accepts 1513 X as an immediate operand. */ 1514 1515 static int 1516 riscv_immediate_operand_p (int code, HOST_WIDE_INT x) 1517 { 1518 switch (code) 1519 { 1520 case ASHIFT: 1521 case ASHIFTRT: 1522 case LSHIFTRT: 1523 /* All shift counts are truncated to a valid constant. */ 1524 return true; 1525 1526 case AND: 1527 case IOR: 1528 case XOR: 1529 case PLUS: 1530 case LT: 1531 case LTU: 1532 /* These instructions take 12-bit signed immediates. */ 1533 return SMALL_OPERAND (x); 1534 1535 case LE: 1536 /* We add 1 to the immediate and use SLT. */ 1537 return SMALL_OPERAND (x + 1); 1538 1539 case LEU: 1540 /* Likewise SLTU, but reject the always-true case. */ 1541 return SMALL_OPERAND (x + 1) && x + 1 != 0; 1542 1543 case GE: 1544 case GEU: 1545 /* We can emulate an immediate of 1 by using GT/GTU against x0. */ 1546 return x == 1; 1547 1548 default: 1549 /* By default assume that x0 can be used for 0. */ 1550 return x == 0; 1551 } 1552 } 1553 1554 /* Return the cost of binary operation X, given that the instruction 1555 sequence for a word-sized or smaller operation takes SIGNLE_INSNS 1556 instructions and that the sequence of a double-word operation takes 1557 DOUBLE_INSNS instructions. */ 1558 1559 static int 1560 riscv_binary_cost (rtx x, int single_insns, int double_insns) 1561 { 1562 if (GET_MODE_SIZE (GET_MODE (x)) == UNITS_PER_WORD * 2) 1563 return COSTS_N_INSNS (double_insns); 1564 return COSTS_N_INSNS (single_insns); 1565 } 1566 1567 /* Return the cost of sign- or zero-extending OP. */ 1568 1569 static int 1570 riscv_extend_cost (rtx op, bool unsigned_p) 1571 { 1572 if (MEM_P (op)) 1573 return 0; 1574 1575 if (unsigned_p && GET_MODE (op) == QImode) 1576 /* We can use ANDI. */ 1577 return COSTS_N_INSNS (1); 1578 1579 if (!unsigned_p && GET_MODE (op) == SImode) 1580 /* We can use SEXT.W. */ 1581 return COSTS_N_INSNS (1); 1582 1583 /* We need to use a shift left and a shift right. */ 1584 return COSTS_N_INSNS (2); 1585 } 1586 1587 /* Implement TARGET_RTX_COSTS. */ 1588 1589 #define SINGLE_SHIFT_COST 1 1590 1591 static bool 1592 riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UNUSED, 1593 int *total, bool speed) 1594 { 1595 bool float_mode_p = FLOAT_MODE_P (mode); 1596 int cost; 1597 1598 switch (GET_CODE (x)) 1599 { 1600 case CONST_INT: 1601 if (riscv_immediate_operand_p (outer_code, INTVAL (x))) 1602 { 1603 *total = 0; 1604 return true; 1605 } 1606 /* Fall through. */ 1607 1608 case SYMBOL_REF: 1609 case LABEL_REF: 1610 case CONST_DOUBLE: 1611 case CONST: 1612 if ((cost = riscv_const_insns (x)) > 0) 1613 { 1614 /* If the constant is likely to be stored in a GPR, SETs of 1615 single-insn constants are as cheap as register sets; we 1616 never want to CSE them. */ 1617 if (cost == 1 && outer_code == SET) 1618 *total = 0; 1619 /* When we load a constant more than once, it usually is better 1620 to duplicate the last operation in the sequence than to CSE 1621 the constant itself. */ 1622 else if (outer_code == SET || GET_MODE (x) == VOIDmode) 1623 *total = COSTS_N_INSNS (1); 1624 } 1625 else /* The instruction will be fetched from the constant pool. */ 1626 *total = COSTS_N_INSNS (riscv_symbol_insns (SYMBOL_ABSOLUTE)); 1627 return true; 1628 1629 case MEM: 1630 /* If the address is legitimate, return the number of 1631 instructions it needs. */ 1632 if ((cost = riscv_address_insns (XEXP (x, 0), mode, true)) > 0) 1633 { 1634 *total = COSTS_N_INSNS (cost + tune_info->memory_cost); 1635 return true; 1636 } 1637 /* Otherwise use the default handling. */ 1638 return false; 1639 1640 case NOT: 1641 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 2 : 1); 1642 return false; 1643 1644 case AND: 1645 case IOR: 1646 case XOR: 1647 /* Double-word operations use two single-word operations. */ 1648 *total = riscv_binary_cost (x, 1, 2); 1649 return false; 1650 1651 case ZERO_EXTRACT: 1652 /* This is an SImode shift. */ 1653 if (outer_code == SET 1654 && CONST_INT_P (XEXP (x, 1)) 1655 && CONST_INT_P (XEXP (x, 2)) 1656 && (INTVAL (XEXP (x, 2)) > 0) 1657 && (INTVAL (XEXP (x, 1)) + INTVAL (XEXP (x, 2)) == 32)) 1658 { 1659 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 1660 return true; 1661 } 1662 return false; 1663 1664 case ASHIFT: 1665 case ASHIFTRT: 1666 case LSHIFTRT: 1667 *total = riscv_binary_cost (x, SINGLE_SHIFT_COST, 1668 CONSTANT_P (XEXP (x, 1)) ? 4 : 9); 1669 return false; 1670 1671 case ABS: 1672 *total = COSTS_N_INSNS (float_mode_p ? 1 : 3); 1673 return false; 1674 1675 case LO_SUM: 1676 *total = set_src_cost (XEXP (x, 0), mode, speed); 1677 return true; 1678 1679 case LT: 1680 /* This is an SImode shift. */ 1681 if (outer_code == SET && GET_MODE (x) == DImode 1682 && GET_MODE (XEXP (x, 0)) == SImode) 1683 { 1684 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 1685 return true; 1686 } 1687 /* Fall through. */ 1688 case LTU: 1689 case LE: 1690 case LEU: 1691 case GT: 1692 case GTU: 1693 case GE: 1694 case GEU: 1695 case EQ: 1696 case NE: 1697 /* Branch comparisons have VOIDmode, so use the first operand's 1698 mode instead. */ 1699 mode = GET_MODE (XEXP (x, 0)); 1700 if (float_mode_p) 1701 *total = tune_info->fp_add[mode == DFmode]; 1702 else 1703 *total = riscv_binary_cost (x, 1, 3); 1704 return false; 1705 1706 case UNORDERED: 1707 case ORDERED: 1708 /* (FEQ(A, A) & FEQ(B, B)) compared against 0. */ 1709 mode = GET_MODE (XEXP (x, 0)); 1710 *total = tune_info->fp_add[mode == DFmode] + COSTS_N_INSNS (2); 1711 return false; 1712 1713 case UNEQ: 1714 /* (FEQ(A, A) & FEQ(B, B)) compared against FEQ(A, B). */ 1715 mode = GET_MODE (XEXP (x, 0)); 1716 *total = tune_info->fp_add[mode == DFmode] + COSTS_N_INSNS (3); 1717 return false; 1718 1719 case LTGT: 1720 /* (FLT(A, A) || FGT(B, B)). */ 1721 mode = GET_MODE (XEXP (x, 0)); 1722 *total = tune_info->fp_add[mode == DFmode] + COSTS_N_INSNS (2); 1723 return false; 1724 1725 case UNGE: 1726 case UNGT: 1727 case UNLE: 1728 case UNLT: 1729 /* FLT or FLE, but guarded by an FFLAGS read and write. */ 1730 mode = GET_MODE (XEXP (x, 0)); 1731 *total = tune_info->fp_add[mode == DFmode] + COSTS_N_INSNS (4); 1732 return false; 1733 1734 case MINUS: 1735 case PLUS: 1736 if (float_mode_p) 1737 *total = tune_info->fp_add[mode == DFmode]; 1738 else 1739 *total = riscv_binary_cost (x, 1, 4); 1740 return false; 1741 1742 case NEG: 1743 { 1744 rtx op = XEXP (x, 0); 1745 if (GET_CODE (op) == FMA && !HONOR_SIGNED_ZEROS (mode)) 1746 { 1747 *total = (tune_info->fp_mul[mode == DFmode] 1748 + set_src_cost (XEXP (op, 0), mode, speed) 1749 + set_src_cost (XEXP (op, 1), mode, speed) 1750 + set_src_cost (XEXP (op, 2), mode, speed)); 1751 return true; 1752 } 1753 } 1754 1755 if (float_mode_p) 1756 *total = tune_info->fp_add[mode == DFmode]; 1757 else 1758 *total = COSTS_N_INSNS (GET_MODE_SIZE (mode) > UNITS_PER_WORD ? 4 : 1); 1759 return false; 1760 1761 case MULT: 1762 if (float_mode_p) 1763 *total = tune_info->fp_mul[mode == DFmode]; 1764 else if (!TARGET_MUL) 1765 /* Estimate the cost of a library call. */ 1766 *total = COSTS_N_INSNS (speed ? 32 : 6); 1767 else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) 1768 *total = 3 * tune_info->int_mul[0] + COSTS_N_INSNS (2); 1769 else if (!speed) 1770 *total = COSTS_N_INSNS (1); 1771 else 1772 *total = tune_info->int_mul[mode == DImode]; 1773 return false; 1774 1775 case DIV: 1776 case SQRT: 1777 case MOD: 1778 if (float_mode_p) 1779 { 1780 *total = tune_info->fp_div[mode == DFmode]; 1781 return false; 1782 } 1783 /* Fall through. */ 1784 1785 case UDIV: 1786 case UMOD: 1787 if (!TARGET_DIV) 1788 /* Estimate the cost of a library call. */ 1789 *total = COSTS_N_INSNS (speed ? 32 : 6); 1790 else if (speed) 1791 *total = tune_info->int_div[mode == DImode]; 1792 else 1793 *total = COSTS_N_INSNS (1); 1794 return false; 1795 1796 case ZERO_EXTEND: 1797 /* This is an SImode shift. */ 1798 if (GET_CODE (XEXP (x, 0)) == LSHIFTRT) 1799 { 1800 *total = COSTS_N_INSNS (SINGLE_SHIFT_COST); 1801 return true; 1802 } 1803 /* Fall through. */ 1804 case SIGN_EXTEND: 1805 *total = riscv_extend_cost (XEXP (x, 0), GET_CODE (x) == ZERO_EXTEND); 1806 return false; 1807 1808 case FLOAT: 1809 case UNSIGNED_FLOAT: 1810 case FIX: 1811 case FLOAT_EXTEND: 1812 case FLOAT_TRUNCATE: 1813 *total = tune_info->fp_add[mode == DFmode]; 1814 return false; 1815 1816 case FMA: 1817 *total = (tune_info->fp_mul[mode == DFmode] 1818 + set_src_cost (XEXP (x, 0), mode, speed) 1819 + set_src_cost (XEXP (x, 1), mode, speed) 1820 + set_src_cost (XEXP (x, 2), mode, speed)); 1821 return true; 1822 1823 case UNSPEC: 1824 if (XINT (x, 1) == UNSPEC_AUIPC) 1825 { 1826 /* Make AUIPC cheap to avoid spilling its result to the stack. */ 1827 *total = 1; 1828 return true; 1829 } 1830 return false; 1831 1832 default: 1833 return false; 1834 } 1835 } 1836 1837 /* Implement TARGET_ADDRESS_COST. */ 1838 1839 static int 1840 riscv_address_cost (rtx addr, machine_mode mode, 1841 addr_space_t as ATTRIBUTE_UNUSED, 1842 bool speed ATTRIBUTE_UNUSED) 1843 { 1844 return riscv_address_insns (addr, mode, false); 1845 } 1846 1847 /* Return one word of double-word value OP. HIGH_P is true to select the 1848 high part or false to select the low part. */ 1849 1850 rtx 1851 riscv_subword (rtx op, bool high_p) 1852 { 1853 unsigned int byte = high_p ? UNITS_PER_WORD : 0; 1854 machine_mode mode = GET_MODE (op); 1855 1856 if (mode == VOIDmode) 1857 mode = TARGET_64BIT ? TImode : DImode; 1858 1859 if (MEM_P (op)) 1860 return adjust_address (op, word_mode, byte); 1861 1862 if (REG_P (op)) 1863 gcc_assert (!FP_REG_RTX_P (op)); 1864 1865 return simplify_gen_subreg (word_mode, op, mode, byte); 1866 } 1867 1868 /* Return true if a 64-bit move from SRC to DEST should be split into two. */ 1869 1870 bool 1871 riscv_split_64bit_move_p (rtx dest, rtx src) 1872 { 1873 if (TARGET_64BIT) 1874 return false; 1875 1876 /* Allow FPR <-> FPR and FPR <-> MEM moves, and permit the special case 1877 of zeroing an FPR with FCVT.D.W. */ 1878 if (TARGET_DOUBLE_FLOAT 1879 && ((FP_REG_RTX_P (src) && FP_REG_RTX_P (dest)) 1880 || (FP_REG_RTX_P (dest) && MEM_P (src)) 1881 || (FP_REG_RTX_P (src) && MEM_P (dest)) 1882 || (FP_REG_RTX_P (dest) && src == CONST0_RTX (GET_MODE (src))))) 1883 return false; 1884 1885 return true; 1886 } 1887 1888 /* Split a doubleword move from SRC to DEST. On 32-bit targets, 1889 this function handles 64-bit moves for which riscv_split_64bit_move_p 1890 holds. For 64-bit targets, this function handles 128-bit moves. */ 1891 1892 void 1893 riscv_split_doubleword_move (rtx dest, rtx src) 1894 { 1895 rtx low_dest; 1896 1897 /* The operation can be split into two normal moves. Decide in 1898 which order to do them. */ 1899 low_dest = riscv_subword (dest, false); 1900 if (REG_P (low_dest) && reg_overlap_mentioned_p (low_dest, src)) 1901 { 1902 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); 1903 riscv_emit_move (low_dest, riscv_subword (src, false)); 1904 } 1905 else 1906 { 1907 riscv_emit_move (low_dest, riscv_subword (src, false)); 1908 riscv_emit_move (riscv_subword (dest, true), riscv_subword (src, true)); 1909 } 1910 } 1911 1912 /* Return the appropriate instructions to move SRC into DEST. Assume 1913 that SRC is operand 1 and DEST is operand 0. */ 1914 1915 const char * 1916 riscv_output_move (rtx dest, rtx src) 1917 { 1918 enum rtx_code dest_code, src_code; 1919 machine_mode mode; 1920 bool dbl_p; 1921 1922 dest_code = GET_CODE (dest); 1923 src_code = GET_CODE (src); 1924 mode = GET_MODE (dest); 1925 dbl_p = (GET_MODE_SIZE (mode) == 8); 1926 1927 if (dbl_p && riscv_split_64bit_move_p (dest, src)) 1928 return "#"; 1929 1930 if (dest_code == REG && GP_REG_P (REGNO (dest))) 1931 { 1932 if (src_code == REG && FP_REG_P (REGNO (src))) 1933 return dbl_p ? "fmv.x.d\t%0,%1" : "fmv.x.w\t%0,%1"; 1934 1935 if (src_code == MEM) 1936 switch (GET_MODE_SIZE (mode)) 1937 { 1938 case 1: return "lbu\t%0,%1"; 1939 case 2: return "lhu\t%0,%1"; 1940 case 4: return "lw\t%0,%1"; 1941 case 8: return "ld\t%0,%1"; 1942 } 1943 1944 if (src_code == CONST_INT) 1945 return "li\t%0,%1"; 1946 1947 if (src_code == HIGH) 1948 return "lui\t%0,%h1"; 1949 1950 if (symbolic_operand (src, VOIDmode)) 1951 switch (riscv_classify_symbolic_expression (src)) 1952 { 1953 case SYMBOL_GOT_DISP: return "la\t%0,%1"; 1954 case SYMBOL_ABSOLUTE: return "lla\t%0,%1"; 1955 case SYMBOL_PCREL: return "lla\t%0,%1"; 1956 default: gcc_unreachable (); 1957 } 1958 } 1959 if ((src_code == REG && GP_REG_P (REGNO (src))) 1960 || (src == CONST0_RTX (mode))) 1961 { 1962 if (dest_code == REG) 1963 { 1964 if (GP_REG_P (REGNO (dest))) 1965 return "mv\t%0,%z1"; 1966 1967 if (FP_REG_P (REGNO (dest))) 1968 { 1969 if (!dbl_p) 1970 return "fmv.w.x\t%0,%z1"; 1971 if (TARGET_64BIT) 1972 return "fmv.d.x\t%0,%z1"; 1973 /* in RV32, we can emulate fmv.d.x %0, x0 using fcvt.d.w */ 1974 gcc_assert (src == CONST0_RTX (mode)); 1975 return "fcvt.d.w\t%0,x0"; 1976 } 1977 } 1978 if (dest_code == MEM) 1979 switch (GET_MODE_SIZE (mode)) 1980 { 1981 case 1: return "sb\t%z1,%0"; 1982 case 2: return "sh\t%z1,%0"; 1983 case 4: return "sw\t%z1,%0"; 1984 case 8: return "sd\t%z1,%0"; 1985 } 1986 } 1987 if (src_code == REG && FP_REG_P (REGNO (src))) 1988 { 1989 if (dest_code == REG && FP_REG_P (REGNO (dest))) 1990 return dbl_p ? "fmv.d\t%0,%1" : "fmv.s\t%0,%1"; 1991 1992 if (dest_code == MEM) 1993 return dbl_p ? "fsd\t%1,%0" : "fsw\t%1,%0"; 1994 } 1995 if (dest_code == REG && FP_REG_P (REGNO (dest))) 1996 { 1997 if (src_code == MEM) 1998 return dbl_p ? "fld\t%0,%1" : "flw\t%0,%1"; 1999 } 2000 gcc_unreachable (); 2001 } 2002 2003 const char * 2004 riscv_output_return () 2005 { 2006 if (cfun->machine->naked_p) 2007 return ""; 2008 2009 return "ret"; 2010 } 2011 2012 2013 /* Return true if CMP1 is a suitable second operand for integer ordering 2014 test CODE. See also the *sCC patterns in riscv.md. */ 2015 2016 static bool 2017 riscv_int_order_operand_ok_p (enum rtx_code code, rtx cmp1) 2018 { 2019 switch (code) 2020 { 2021 case GT: 2022 case GTU: 2023 return reg_or_0_operand (cmp1, VOIDmode); 2024 2025 case GE: 2026 case GEU: 2027 return cmp1 == const1_rtx; 2028 2029 case LT: 2030 case LTU: 2031 return arith_operand (cmp1, VOIDmode); 2032 2033 case LE: 2034 return sle_operand (cmp1, VOIDmode); 2035 2036 case LEU: 2037 return sleu_operand (cmp1, VOIDmode); 2038 2039 default: 2040 gcc_unreachable (); 2041 } 2042 } 2043 2044 /* Return true if *CMP1 (of mode MODE) is a valid second operand for 2045 integer ordering test *CODE, or if an equivalent combination can 2046 be formed by adjusting *CODE and *CMP1. When returning true, update 2047 *CODE and *CMP1 with the chosen code and operand, otherwise leave 2048 them alone. */ 2049 2050 static bool 2051 riscv_canonicalize_int_order_test (enum rtx_code *code, rtx *cmp1, 2052 machine_mode mode) 2053 { 2054 HOST_WIDE_INT plus_one; 2055 2056 if (riscv_int_order_operand_ok_p (*code, *cmp1)) 2057 return true; 2058 2059 if (CONST_INT_P (*cmp1)) 2060 switch (*code) 2061 { 2062 case LE: 2063 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 2064 if (INTVAL (*cmp1) < plus_one) 2065 { 2066 *code = LT; 2067 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 2068 return true; 2069 } 2070 break; 2071 2072 case LEU: 2073 plus_one = trunc_int_for_mode (UINTVAL (*cmp1) + 1, mode); 2074 if (plus_one != 0) 2075 { 2076 *code = LTU; 2077 *cmp1 = force_reg (mode, GEN_INT (plus_one)); 2078 return true; 2079 } 2080 break; 2081 2082 default: 2083 break; 2084 } 2085 return false; 2086 } 2087 2088 /* Compare CMP0 and CMP1 using ordering test CODE and store the result 2089 in TARGET. CMP0 and TARGET are register_operands. If INVERT_PTR 2090 is nonnull, it's OK to set TARGET to the inverse of the result and 2091 flip *INVERT_PTR instead. */ 2092 2093 static void 2094 riscv_emit_int_order_test (enum rtx_code code, bool *invert_ptr, 2095 rtx target, rtx cmp0, rtx cmp1) 2096 { 2097 machine_mode mode; 2098 2099 /* First see if there is a RISCV instruction that can do this operation. 2100 If not, try doing the same for the inverse operation. If that also 2101 fails, force CMP1 into a register and try again. */ 2102 mode = GET_MODE (cmp0); 2103 if (riscv_canonicalize_int_order_test (&code, &cmp1, mode)) 2104 riscv_emit_binary (code, target, cmp0, cmp1); 2105 else 2106 { 2107 enum rtx_code inv_code = reverse_condition (code); 2108 if (!riscv_canonicalize_int_order_test (&inv_code, &cmp1, mode)) 2109 { 2110 cmp1 = force_reg (mode, cmp1); 2111 riscv_emit_int_order_test (code, invert_ptr, target, cmp0, cmp1); 2112 } 2113 else if (invert_ptr == 0) 2114 { 2115 rtx inv_target = riscv_force_binary (GET_MODE (target), 2116 inv_code, cmp0, cmp1); 2117 riscv_emit_binary (XOR, target, inv_target, const1_rtx); 2118 } 2119 else 2120 { 2121 *invert_ptr = !*invert_ptr; 2122 riscv_emit_binary (inv_code, target, cmp0, cmp1); 2123 } 2124 } 2125 } 2126 2127 /* Return a register that is zero iff CMP0 and CMP1 are equal. 2128 The register will have the same mode as CMP0. */ 2129 2130 static rtx 2131 riscv_zero_if_equal (rtx cmp0, rtx cmp1) 2132 { 2133 if (cmp1 == const0_rtx) 2134 return cmp0; 2135 2136 return expand_binop (GET_MODE (cmp0), sub_optab, 2137 cmp0, cmp1, 0, 0, OPTAB_DIRECT); 2138 } 2139 2140 /* Sign- or zero-extend OP0 and OP1 for integer comparisons. */ 2141 2142 static void 2143 riscv_extend_comparands (rtx_code code, rtx *op0, rtx *op1) 2144 { 2145 /* Comparisons consider all XLEN bits, so extend sub-XLEN values. */ 2146 if (GET_MODE_SIZE (word_mode) > GET_MODE_SIZE (GET_MODE (*op0))) 2147 { 2148 /* It is more profitable to zero-extend QImode values. But not if the 2149 first operand has already been sign-extended, and the second one is 2150 is a constant or has already been sign-extended also. */ 2151 if (unsigned_condition (code) == code 2152 && (GET_MODE (*op0) == QImode 2153 && ! (GET_CODE (*op0) == SUBREG 2154 && SUBREG_PROMOTED_VAR_P (*op0) 2155 && SUBREG_PROMOTED_SIGNED_P (*op0) 2156 && (CONST_INT_P (*op1) 2157 || (GET_CODE (*op1) == SUBREG 2158 && SUBREG_PROMOTED_VAR_P (*op1) 2159 && SUBREG_PROMOTED_SIGNED_P (*op1)))))) 2160 { 2161 *op0 = gen_rtx_ZERO_EXTEND (word_mode, *op0); 2162 if (CONST_INT_P (*op1)) 2163 *op1 = GEN_INT ((uint8_t) INTVAL (*op1)); 2164 else 2165 *op1 = gen_rtx_ZERO_EXTEND (word_mode, *op1); 2166 } 2167 else 2168 { 2169 *op0 = gen_rtx_SIGN_EXTEND (word_mode, *op0); 2170 if (*op1 != const0_rtx) 2171 *op1 = gen_rtx_SIGN_EXTEND (word_mode, *op1); 2172 } 2173 } 2174 } 2175 2176 /* Convert a comparison into something that can be used in a branch. On 2177 entry, *OP0 and *OP1 are the values being compared and *CODE is the code 2178 used to compare them. Update them to describe the final comparison. */ 2179 2180 static void 2181 riscv_emit_int_compare (enum rtx_code *code, rtx *op0, rtx *op1) 2182 { 2183 if (splittable_const_int_operand (*op1, VOIDmode)) 2184 { 2185 HOST_WIDE_INT rhs = INTVAL (*op1); 2186 2187 if (*code == EQ || *code == NE) 2188 { 2189 /* Convert e.g. OP0 == 2048 into OP0 - 2048 == 0. */ 2190 if (SMALL_OPERAND (-rhs)) 2191 { 2192 *op0 = riscv_force_binary (GET_MODE (*op0), PLUS, *op0, 2193 GEN_INT (-rhs)); 2194 *op1 = const0_rtx; 2195 } 2196 } 2197 else 2198 { 2199 static const enum rtx_code mag_comparisons[][2] = { 2200 {LEU, LTU}, {GTU, GEU}, {LE, LT}, {GT, GE} 2201 }; 2202 2203 /* Convert e.g. (OP0 <= 0xFFF) into (OP0 < 0x1000). */ 2204 for (size_t i = 0; i < ARRAY_SIZE (mag_comparisons); i++) 2205 { 2206 HOST_WIDE_INT new_rhs; 2207 bool increment = *code == mag_comparisons[i][0]; 2208 bool decrement = *code == mag_comparisons[i][1]; 2209 if (!increment && !decrement) 2210 continue; 2211 2212 new_rhs = rhs + (increment ? 1 : -1); 2213 if (riscv_integer_cost (new_rhs) < riscv_integer_cost (rhs) 2214 && (rhs < 0) == (new_rhs < 0)) 2215 { 2216 *op1 = GEN_INT (new_rhs); 2217 *code = mag_comparisons[i][increment]; 2218 } 2219 break; 2220 } 2221 } 2222 } 2223 2224 riscv_extend_comparands (*code, op0, op1); 2225 2226 *op0 = force_reg (word_mode, *op0); 2227 if (*op1 != const0_rtx) 2228 *op1 = force_reg (word_mode, *op1); 2229 } 2230 2231 /* Like riscv_emit_int_compare, but for floating-point comparisons. */ 2232 2233 static void 2234 riscv_emit_float_compare (enum rtx_code *code, rtx *op0, rtx *op1) 2235 { 2236 rtx tmp0, tmp1, cmp_op0 = *op0, cmp_op1 = *op1; 2237 enum rtx_code fp_code = *code; 2238 *code = NE; 2239 2240 switch (fp_code) 2241 { 2242 case UNORDERED: 2243 *code = EQ; 2244 /* Fall through. */ 2245 2246 case ORDERED: 2247 /* a == a && b == b */ 2248 tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0); 2249 tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1); 2250 *op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1); 2251 *op1 = const0_rtx; 2252 break; 2253 2254 case UNEQ: 2255 /* ordered(a, b) > (a == b) */ 2256 *code = EQ; 2257 tmp0 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op0); 2258 tmp1 = riscv_force_binary (word_mode, EQ, cmp_op1, cmp_op1); 2259 *op0 = riscv_force_binary (word_mode, AND, tmp0, tmp1); 2260 *op1 = riscv_force_binary (word_mode, EQ, cmp_op0, cmp_op1); 2261 break; 2262 2263 #define UNORDERED_COMPARISON(CODE, CMP) \ 2264 case CODE: \ 2265 *code = EQ; \ 2266 *op0 = gen_reg_rtx (word_mode); \ 2267 if (GET_MODE (cmp_op0) == SFmode && TARGET_64BIT) \ 2268 emit_insn (gen_f##CMP##_quietsfdi4 (*op0, cmp_op0, cmp_op1)); \ 2269 else if (GET_MODE (cmp_op0) == SFmode) \ 2270 emit_insn (gen_f##CMP##_quietsfsi4 (*op0, cmp_op0, cmp_op1)); \ 2271 else if (GET_MODE (cmp_op0) == DFmode && TARGET_64BIT) \ 2272 emit_insn (gen_f##CMP##_quietdfdi4 (*op0, cmp_op0, cmp_op1)); \ 2273 else if (GET_MODE (cmp_op0) == DFmode) \ 2274 emit_insn (gen_f##CMP##_quietdfsi4 (*op0, cmp_op0, cmp_op1)); \ 2275 else \ 2276 gcc_unreachable (); \ 2277 *op1 = const0_rtx; \ 2278 break; 2279 2280 case UNLT: 2281 std::swap (cmp_op0, cmp_op1); 2282 gcc_fallthrough (); 2283 2284 UNORDERED_COMPARISON(UNGT, le) 2285 2286 case UNLE: 2287 std::swap (cmp_op0, cmp_op1); 2288 gcc_fallthrough (); 2289 2290 UNORDERED_COMPARISON(UNGE, lt) 2291 #undef UNORDERED_COMPARISON 2292 2293 case NE: 2294 fp_code = EQ; 2295 *code = EQ; 2296 /* Fall through. */ 2297 2298 case EQ: 2299 case LE: 2300 case LT: 2301 case GE: 2302 case GT: 2303 /* We have instructions for these cases. */ 2304 *op0 = riscv_force_binary (word_mode, fp_code, cmp_op0, cmp_op1); 2305 *op1 = const0_rtx; 2306 break; 2307 2308 case LTGT: 2309 /* (a < b) | (a > b) */ 2310 tmp0 = riscv_force_binary (word_mode, LT, cmp_op0, cmp_op1); 2311 tmp1 = riscv_force_binary (word_mode, GT, cmp_op0, cmp_op1); 2312 *op0 = riscv_force_binary (word_mode, IOR, tmp0, tmp1); 2313 *op1 = const0_rtx; 2314 break; 2315 2316 default: 2317 gcc_unreachable (); 2318 } 2319 } 2320 2321 /* CODE-compare OP0 and OP1. Store the result in TARGET. */ 2322 2323 void 2324 riscv_expand_int_scc (rtx target, enum rtx_code code, rtx op0, rtx op1) 2325 { 2326 riscv_extend_comparands (code, &op0, &op1); 2327 op0 = force_reg (word_mode, op0); 2328 2329 if (code == EQ || code == NE) 2330 { 2331 rtx zie = riscv_zero_if_equal (op0, op1); 2332 riscv_emit_binary (code, target, zie, const0_rtx); 2333 } 2334 else 2335 riscv_emit_int_order_test (code, 0, target, op0, op1); 2336 } 2337 2338 /* Like riscv_expand_int_scc, but for floating-point comparisons. */ 2339 2340 void 2341 riscv_expand_float_scc (rtx target, enum rtx_code code, rtx op0, rtx op1) 2342 { 2343 riscv_emit_float_compare (&code, &op0, &op1); 2344 2345 rtx cmp = riscv_force_binary (word_mode, code, op0, op1); 2346 riscv_emit_set (target, lowpart_subreg (SImode, cmp, word_mode)); 2347 } 2348 2349 /* Jump to LABEL if (CODE OP0 OP1) holds. */ 2350 2351 void 2352 riscv_expand_conditional_branch (rtx label, rtx_code code, rtx op0, rtx op1) 2353 { 2354 if (FLOAT_MODE_P (GET_MODE (op1))) 2355 riscv_emit_float_compare (&code, &op0, &op1); 2356 else 2357 riscv_emit_int_compare (&code, &op0, &op1); 2358 2359 rtx condition = gen_rtx_fmt_ee (code, VOIDmode, op0, op1); 2360 emit_jump_insn (gen_condjump (condition, label)); 2361 } 2362 2363 /* If (CODE OP0 OP1) holds, move CONS to DEST; else move ALT to DEST. */ 2364 2365 void 2366 riscv_expand_conditional_move (rtx dest, rtx cons, rtx alt, rtx_code code, 2367 rtx op0, rtx op1) 2368 { 2369 riscv_emit_int_compare (&code, &op0, &op1); 2370 rtx cond = gen_rtx_fmt_ee (code, GET_MODE (op0), op0, op1); 2371 emit_insn (gen_rtx_SET (dest, gen_rtx_IF_THEN_ELSE (GET_MODE (dest), cond, 2372 cons, alt))); 2373 } 2374 2375 /* Implement TARGET_FUNCTION_ARG_BOUNDARY. Every parameter gets at 2376 least PARM_BOUNDARY bits of alignment, but will be given anything up 2377 to PREFERRED_STACK_BOUNDARY bits if the type requires it. */ 2378 2379 static unsigned int 2380 riscv_function_arg_boundary (machine_mode mode, const_tree type) 2381 { 2382 unsigned int alignment; 2383 2384 /* Use natural alignment if the type is not aggregate data. */ 2385 if (type && !AGGREGATE_TYPE_P (type)) 2386 alignment = TYPE_ALIGN (TYPE_MAIN_VARIANT (type)); 2387 else 2388 alignment = type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode); 2389 2390 return MIN (PREFERRED_STACK_BOUNDARY, MAX (PARM_BOUNDARY, alignment)); 2391 } 2392 2393 /* If MODE represents an argument that can be passed or returned in 2394 floating-point registers, return the number of registers, else 0. */ 2395 2396 static unsigned 2397 riscv_pass_mode_in_fpr_p (machine_mode mode) 2398 { 2399 if (GET_MODE_UNIT_SIZE (mode) <= UNITS_PER_FP_ARG) 2400 { 2401 if (GET_MODE_CLASS (mode) == MODE_FLOAT) 2402 return 1; 2403 2404 if (GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 2405 return 2; 2406 } 2407 2408 return 0; 2409 } 2410 2411 typedef struct { 2412 const_tree type; 2413 HOST_WIDE_INT offset; 2414 } riscv_aggregate_field; 2415 2416 /* Identify subfields of aggregates that are candidates for passing in 2417 floating-point registers. */ 2418 2419 static int 2420 riscv_flatten_aggregate_field (const_tree type, 2421 riscv_aggregate_field fields[2], 2422 int n, HOST_WIDE_INT offset, 2423 bool ignore_zero_width_bit_field_p) 2424 { 2425 switch (TREE_CODE (type)) 2426 { 2427 case RECORD_TYPE: 2428 /* Can't handle incomplete types nor sizes that are not fixed. */ 2429 if (!COMPLETE_TYPE_P (type) 2430 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST 2431 || !tree_fits_uhwi_p (TYPE_SIZE (type))) 2432 return -1; 2433 2434 for (tree f = TYPE_FIELDS (type); f; f = DECL_CHAIN (f)) 2435 if (TREE_CODE (f) == FIELD_DECL) 2436 { 2437 if (!TYPE_P (TREE_TYPE (f))) 2438 return -1; 2439 2440 /* The C++ front end strips zero-length bit-fields from structs. 2441 So we need to ignore them in the C front end to make C code 2442 compatible with C++ code. */ 2443 if (ignore_zero_width_bit_field_p 2444 && DECL_BIT_FIELD (f) 2445 && (DECL_SIZE (f) == NULL_TREE 2446 || integer_zerop (DECL_SIZE (f)))) 2447 ; 2448 else 2449 { 2450 HOST_WIDE_INT pos = offset + int_byte_position (f); 2451 n = riscv_flatten_aggregate_field (TREE_TYPE (f), 2452 fields, n, pos, 2453 ignore_zero_width_bit_field_p); 2454 } 2455 if (n < 0) 2456 return -1; 2457 } 2458 return n; 2459 2460 case ARRAY_TYPE: 2461 { 2462 HOST_WIDE_INT n_elts; 2463 riscv_aggregate_field subfields[2]; 2464 tree index = TYPE_DOMAIN (type); 2465 tree elt_size = TYPE_SIZE_UNIT (TREE_TYPE (type)); 2466 int n_subfields = riscv_flatten_aggregate_field (TREE_TYPE (type), 2467 subfields, 0, offset, 2468 ignore_zero_width_bit_field_p); 2469 2470 /* Can't handle incomplete types nor sizes that are not fixed. */ 2471 if (n_subfields <= 0 2472 || !COMPLETE_TYPE_P (type) 2473 || TREE_CODE (TYPE_SIZE (type)) != INTEGER_CST 2474 || !index 2475 || !TYPE_MAX_VALUE (index) 2476 || !tree_fits_uhwi_p (TYPE_MAX_VALUE (index)) 2477 || !TYPE_MIN_VALUE (index) 2478 || !tree_fits_uhwi_p (TYPE_MIN_VALUE (index)) 2479 || !tree_fits_uhwi_p (elt_size)) 2480 return -1; 2481 2482 n_elts = 1 + tree_to_uhwi (TYPE_MAX_VALUE (index)) 2483 - tree_to_uhwi (TYPE_MIN_VALUE (index)); 2484 gcc_assert (n_elts >= 0); 2485 2486 for (HOST_WIDE_INT i = 0; i < n_elts; i++) 2487 for (int j = 0; j < n_subfields; j++) 2488 { 2489 if (n >= 2) 2490 return -1; 2491 2492 fields[n] = subfields[j]; 2493 fields[n++].offset += i * tree_to_uhwi (elt_size); 2494 } 2495 2496 return n; 2497 } 2498 2499 case COMPLEX_TYPE: 2500 { 2501 /* Complex type need consume 2 field, so n must be 0. */ 2502 if (n != 0) 2503 return -1; 2504 2505 HOST_WIDE_INT elt_size = GET_MODE_SIZE (TYPE_MODE (TREE_TYPE (type))); 2506 2507 if (elt_size <= UNITS_PER_FP_ARG) 2508 { 2509 fields[0].type = TREE_TYPE (type); 2510 fields[0].offset = offset; 2511 fields[1].type = TREE_TYPE (type); 2512 fields[1].offset = offset + elt_size; 2513 2514 return 2; 2515 } 2516 2517 return -1; 2518 } 2519 2520 default: 2521 if (n < 2 2522 && ((SCALAR_FLOAT_TYPE_P (type) 2523 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_FP_ARG) 2524 || (INTEGRAL_TYPE_P (type) 2525 && GET_MODE_SIZE (TYPE_MODE (type)) <= UNITS_PER_WORD))) 2526 { 2527 fields[n].type = type; 2528 fields[n].offset = offset; 2529 return n + 1; 2530 } 2531 else 2532 return -1; 2533 } 2534 } 2535 2536 /* Identify candidate aggregates for passing in floating-point registers. 2537 Candidates have at most two fields after flattening. */ 2538 2539 static int 2540 riscv_flatten_aggregate_argument (const_tree type, 2541 riscv_aggregate_field fields[2], 2542 bool ignore_zero_width_bit_field_p) 2543 { 2544 if (!type || TREE_CODE (type) != RECORD_TYPE) 2545 return -1; 2546 2547 return riscv_flatten_aggregate_field (type, fields, 0, 0, 2548 ignore_zero_width_bit_field_p); 2549 } 2550 2551 /* See whether TYPE is a record whose fields should be returned in one or 2552 two floating-point registers. If so, populate FIELDS accordingly. */ 2553 2554 static unsigned 2555 riscv_pass_aggregate_in_fpr_pair_p (const_tree type, 2556 riscv_aggregate_field fields[2]) 2557 { 2558 static int warned = 0; 2559 2560 /* This is the old ABI, which differs for C++ and C. */ 2561 int n_old = riscv_flatten_aggregate_argument (type, fields, false); 2562 for (int i = 0; i < n_old; i++) 2563 if (!SCALAR_FLOAT_TYPE_P (fields[i].type)) 2564 { 2565 n_old = -1; 2566 break; 2567 } 2568 2569 /* This is the new ABI, which is the same for C++ and C. */ 2570 int n_new = riscv_flatten_aggregate_argument (type, fields, true); 2571 for (int i = 0; i < n_new; i++) 2572 if (!SCALAR_FLOAT_TYPE_P (fields[i].type)) 2573 { 2574 n_new = -1; 2575 break; 2576 } 2577 2578 if ((n_old != n_new) && (warned == 0)) 2579 { 2580 warning (0, "ABI for flattened struct with zero-length bit-fields " 2581 "changed in GCC 10"); 2582 warned = 1; 2583 } 2584 2585 return n_new > 0 ? n_new : 0; 2586 } 2587 2588 /* See whether TYPE is a record whose fields should be returned in one or 2589 floating-point register and one integer register. If so, populate 2590 FIELDS accordingly. */ 2591 2592 static bool 2593 riscv_pass_aggregate_in_fpr_and_gpr_p (const_tree type, 2594 riscv_aggregate_field fields[2]) 2595 { 2596 static int warned = 0; 2597 2598 /* This is the old ABI, which differs for C++ and C. */ 2599 unsigned num_int_old = 0, num_float_old = 0; 2600 int n_old = riscv_flatten_aggregate_argument (type, fields, false); 2601 for (int i = 0; i < n_old; i++) 2602 { 2603 num_float_old += SCALAR_FLOAT_TYPE_P (fields[i].type); 2604 num_int_old += INTEGRAL_TYPE_P (fields[i].type); 2605 } 2606 2607 /* This is the new ABI, which is the same for C++ and C. */ 2608 unsigned num_int_new = 0, num_float_new = 0; 2609 int n_new = riscv_flatten_aggregate_argument (type, fields, true); 2610 for (int i = 0; i < n_new; i++) 2611 { 2612 num_float_new += SCALAR_FLOAT_TYPE_P (fields[i].type); 2613 num_int_new += INTEGRAL_TYPE_P (fields[i].type); 2614 } 2615 2616 if (((num_int_old == 1 && num_float_old == 1 2617 && (num_int_old != num_int_new || num_float_old != num_float_new)) 2618 || (num_int_new == 1 && num_float_new == 1 2619 && (num_int_old != num_int_new || num_float_old != num_float_new))) 2620 && (warned == 0)) 2621 { 2622 warning (0, "ABI for flattened struct with zero-length bit-fields " 2623 "changed in GCC 10"); 2624 warned = 1; 2625 } 2626 2627 return num_int_new == 1 && num_float_new == 1; 2628 } 2629 2630 /* Return the representation of an argument passed or returned in an FPR 2631 when the value has mode VALUE_MODE and the type has TYPE_MODE. The 2632 two modes may be different for structures like: 2633 2634 struct __attribute__((packed)) foo { float f; } 2635 2636 where the SFmode value "f" is passed in REGNO but the struct itself 2637 has mode BLKmode. */ 2638 2639 static rtx 2640 riscv_pass_fpr_single (machine_mode type_mode, unsigned regno, 2641 machine_mode value_mode, 2642 HOST_WIDE_INT offset) 2643 { 2644 rtx x = gen_rtx_REG (value_mode, regno); 2645 2646 if (type_mode != value_mode) 2647 { 2648 x = gen_rtx_EXPR_LIST (VOIDmode, x, GEN_INT (offset)); 2649 x = gen_rtx_PARALLEL (type_mode, gen_rtvec (1, x)); 2650 } 2651 return x; 2652 } 2653 2654 /* Pass or return a composite value in the FPR pair REGNO and REGNO + 1. 2655 MODE is the mode of the composite. MODE1 and OFFSET1 are the mode and 2656 byte offset for the first value, likewise MODE2 and OFFSET2 for the 2657 second value. */ 2658 2659 static rtx 2660 riscv_pass_fpr_pair (machine_mode mode, unsigned regno1, 2661 machine_mode mode1, HOST_WIDE_INT offset1, 2662 unsigned regno2, machine_mode mode2, 2663 HOST_WIDE_INT offset2) 2664 { 2665 return gen_rtx_PARALLEL 2666 (mode, 2667 gen_rtvec (2, 2668 gen_rtx_EXPR_LIST (VOIDmode, 2669 gen_rtx_REG (mode1, regno1), 2670 GEN_INT (offset1)), 2671 gen_rtx_EXPR_LIST (VOIDmode, 2672 gen_rtx_REG (mode2, regno2), 2673 GEN_INT (offset2)))); 2674 } 2675 2676 /* Fill INFO with information about a single argument, and return an 2677 RTL pattern to pass or return the argument. CUM is the cumulative 2678 state for earlier arguments. MODE is the mode of this argument and 2679 TYPE is its type (if known). NAMED is true if this is a named 2680 (fixed) argument rather than a variable one. RETURN_P is true if 2681 returning the argument, or false if passing the argument. */ 2682 2683 static rtx 2684 riscv_get_arg_info (struct riscv_arg_info *info, const CUMULATIVE_ARGS *cum, 2685 machine_mode mode, const_tree type, bool named, 2686 bool return_p) 2687 { 2688 unsigned num_bytes, num_words; 2689 unsigned fpr_base = return_p ? FP_RETURN : FP_ARG_FIRST; 2690 unsigned gpr_base = return_p ? GP_RETURN : GP_ARG_FIRST; 2691 unsigned alignment = riscv_function_arg_boundary (mode, type); 2692 2693 memset (info, 0, sizeof (*info)); 2694 info->gpr_offset = cum->num_gprs; 2695 info->fpr_offset = cum->num_fprs; 2696 2697 if (named) 2698 { 2699 riscv_aggregate_field fields[2]; 2700 unsigned fregno = fpr_base + info->fpr_offset; 2701 unsigned gregno = gpr_base + info->gpr_offset; 2702 2703 /* Pass one- or two-element floating-point aggregates in FPRs. */ 2704 if ((info->num_fprs = riscv_pass_aggregate_in_fpr_pair_p (type, fields)) 2705 && info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS) 2706 switch (info->num_fprs) 2707 { 2708 case 1: 2709 return riscv_pass_fpr_single (mode, fregno, 2710 TYPE_MODE (fields[0].type), 2711 fields[0].offset); 2712 2713 case 2: 2714 return riscv_pass_fpr_pair (mode, fregno, 2715 TYPE_MODE (fields[0].type), 2716 fields[0].offset, 2717 fregno + 1, 2718 TYPE_MODE (fields[1].type), 2719 fields[1].offset); 2720 2721 default: 2722 gcc_unreachable (); 2723 } 2724 2725 /* Pass real and complex floating-point numbers in FPRs. */ 2726 if ((info->num_fprs = riscv_pass_mode_in_fpr_p (mode)) 2727 && info->fpr_offset + info->num_fprs <= MAX_ARGS_IN_REGISTERS) 2728 switch (GET_MODE_CLASS (mode)) 2729 { 2730 case MODE_FLOAT: 2731 return gen_rtx_REG (mode, fregno); 2732 2733 case MODE_COMPLEX_FLOAT: 2734 return riscv_pass_fpr_pair (mode, fregno, GET_MODE_INNER (mode), 0, 2735 fregno + 1, GET_MODE_INNER (mode), 2736 GET_MODE_UNIT_SIZE (mode)); 2737 2738 default: 2739 gcc_unreachable (); 2740 } 2741 2742 /* Pass structs with one float and one integer in an FPR and a GPR. */ 2743 if (riscv_pass_aggregate_in_fpr_and_gpr_p (type, fields) 2744 && info->gpr_offset < MAX_ARGS_IN_REGISTERS 2745 && info->fpr_offset < MAX_ARGS_IN_REGISTERS) 2746 { 2747 info->num_gprs = 1; 2748 info->num_fprs = 1; 2749 2750 if (!SCALAR_FLOAT_TYPE_P (fields[0].type)) 2751 std::swap (fregno, gregno); 2752 2753 return riscv_pass_fpr_pair (mode, fregno, TYPE_MODE (fields[0].type), 2754 fields[0].offset, 2755 gregno, TYPE_MODE (fields[1].type), 2756 fields[1].offset); 2757 } 2758 } 2759 2760 /* Work out the size of the argument. */ 2761 num_bytes = type ? int_size_in_bytes (type) : GET_MODE_SIZE (mode); 2762 num_words = (num_bytes + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 2763 2764 /* Doubleword-aligned varargs start on an even register boundary. */ 2765 if (!named && num_bytes != 0 && alignment > BITS_PER_WORD) 2766 info->gpr_offset += info->gpr_offset & 1; 2767 2768 /* Partition the argument between registers and stack. */ 2769 info->num_fprs = 0; 2770 info->num_gprs = MIN (num_words, MAX_ARGS_IN_REGISTERS - info->gpr_offset); 2771 info->stack_p = (num_words - info->num_gprs) != 0; 2772 2773 if (info->num_gprs || return_p) 2774 return gen_rtx_REG (mode, gpr_base + info->gpr_offset); 2775 2776 return NULL_RTX; 2777 } 2778 2779 /* Implement TARGET_FUNCTION_ARG. */ 2780 2781 static rtx 2782 riscv_function_arg (cumulative_args_t cum_v, const function_arg_info &arg) 2783 { 2784 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2785 struct riscv_arg_info info; 2786 2787 if (arg.end_marker_p ()) 2788 return NULL; 2789 2790 return riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false); 2791 } 2792 2793 /* Implement TARGET_FUNCTION_ARG_ADVANCE. */ 2794 2795 static void 2796 riscv_function_arg_advance (cumulative_args_t cum_v, 2797 const function_arg_info &arg) 2798 { 2799 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2800 struct riscv_arg_info info; 2801 2802 riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false); 2803 2804 /* Advance the register count. This has the effect of setting 2805 num_gprs to MAX_ARGS_IN_REGISTERS if a doubleword-aligned 2806 argument required us to skip the final GPR and pass the whole 2807 argument on the stack. */ 2808 cum->num_fprs = info.fpr_offset + info.num_fprs; 2809 cum->num_gprs = info.gpr_offset + info.num_gprs; 2810 } 2811 2812 /* Implement TARGET_ARG_PARTIAL_BYTES. */ 2813 2814 static int 2815 riscv_arg_partial_bytes (cumulative_args_t cum, 2816 const function_arg_info &generic_arg) 2817 { 2818 struct riscv_arg_info arg; 2819 2820 riscv_get_arg_info (&arg, get_cumulative_args (cum), generic_arg.mode, 2821 generic_arg.type, generic_arg.named, false); 2822 return arg.stack_p ? arg.num_gprs * UNITS_PER_WORD : 0; 2823 } 2824 2825 /* Implement FUNCTION_VALUE and LIBCALL_VALUE. For normal calls, 2826 VALTYPE is the return type and MODE is VOIDmode. For libcalls, 2827 VALTYPE is null and MODE is the mode of the return value. */ 2828 2829 rtx 2830 riscv_function_value (const_tree type, const_tree func, machine_mode mode) 2831 { 2832 struct riscv_arg_info info; 2833 CUMULATIVE_ARGS args; 2834 2835 if (type) 2836 { 2837 int unsigned_p = TYPE_UNSIGNED (type); 2838 2839 mode = TYPE_MODE (type); 2840 2841 /* Since TARGET_PROMOTE_FUNCTION_MODE unconditionally promotes, 2842 return values, promote the mode here too. */ 2843 mode = promote_function_mode (type, mode, &unsigned_p, func, 1); 2844 } 2845 2846 memset (&args, 0, sizeof args); 2847 return riscv_get_arg_info (&info, &args, mode, type, true, true); 2848 } 2849 2850 /* Implement TARGET_PASS_BY_REFERENCE. */ 2851 2852 static bool 2853 riscv_pass_by_reference (cumulative_args_t cum_v, const function_arg_info &arg) 2854 { 2855 HOST_WIDE_INT size = arg.type_size_in_bytes (); 2856 struct riscv_arg_info info; 2857 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 2858 2859 /* ??? std_gimplify_va_arg_expr passes NULL for cum. Fortunately, we 2860 never pass variadic arguments in floating-point registers, so we can 2861 avoid the call to riscv_get_arg_info in this case. */ 2862 if (cum != NULL) 2863 { 2864 /* Don't pass by reference if we can use a floating-point register. */ 2865 riscv_get_arg_info (&info, cum, arg.mode, arg.type, arg.named, false); 2866 if (info.num_fprs) 2867 return false; 2868 } 2869 2870 /* Pass by reference if the data do not fit in two integer registers. */ 2871 return !IN_RANGE (size, 0, 2 * UNITS_PER_WORD); 2872 } 2873 2874 /* Implement TARGET_RETURN_IN_MEMORY. */ 2875 2876 static bool 2877 riscv_return_in_memory (const_tree type, const_tree fndecl ATTRIBUTE_UNUSED) 2878 { 2879 CUMULATIVE_ARGS args; 2880 cumulative_args_t cum = pack_cumulative_args (&args); 2881 2882 /* The rules for returning in memory are the same as for passing the 2883 first named argument by reference. */ 2884 memset (&args, 0, sizeof args); 2885 function_arg_info arg (const_cast<tree> (type), /*named=*/true); 2886 return riscv_pass_by_reference (cum, arg); 2887 } 2888 2889 /* Implement TARGET_SETUP_INCOMING_VARARGS. */ 2890 2891 static void 2892 riscv_setup_incoming_varargs (cumulative_args_t cum, 2893 const function_arg_info &arg, 2894 int *pretend_size ATTRIBUTE_UNUSED, int no_rtl) 2895 { 2896 CUMULATIVE_ARGS local_cum; 2897 int gp_saved; 2898 2899 /* The caller has advanced CUM up to, but not beyond, the last named 2900 argument. Advance a local copy of CUM past the last "real" named 2901 argument, to find out how many registers are left over. */ 2902 local_cum = *get_cumulative_args (cum); 2903 riscv_function_arg_advance (pack_cumulative_args (&local_cum), arg); 2904 2905 /* Found out how many registers we need to save. */ 2906 gp_saved = MAX_ARGS_IN_REGISTERS - local_cum.num_gprs; 2907 2908 if (!no_rtl && gp_saved > 0) 2909 { 2910 rtx ptr = plus_constant (Pmode, virtual_incoming_args_rtx, 2911 REG_PARM_STACK_SPACE (cfun->decl) 2912 - gp_saved * UNITS_PER_WORD); 2913 rtx mem = gen_frame_mem (BLKmode, ptr); 2914 set_mem_alias_set (mem, get_varargs_alias_set ()); 2915 2916 move_block_from_reg (local_cum.num_gprs + GP_ARG_FIRST, 2917 mem, gp_saved); 2918 } 2919 if (REG_PARM_STACK_SPACE (cfun->decl) == 0) 2920 cfun->machine->varargs_size = gp_saved * UNITS_PER_WORD; 2921 } 2922 2923 /* Handle an attribute requiring a FUNCTION_DECL; 2924 arguments as in struct attribute_spec.handler. */ 2925 static tree 2926 riscv_handle_fndecl_attribute (tree *node, tree name, 2927 tree args ATTRIBUTE_UNUSED, 2928 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) 2929 { 2930 if (TREE_CODE (*node) != FUNCTION_DECL) 2931 { 2932 warning (OPT_Wattributes, "%qE attribute only applies to functions", 2933 name); 2934 *no_add_attrs = true; 2935 } 2936 2937 return NULL_TREE; 2938 } 2939 2940 /* Verify type based attributes. NODE is the what the attribute is being 2941 applied to. NAME is the attribute name. ARGS are the attribute args. 2942 FLAGS gives info about the context. NO_ADD_ATTRS should be set to true if 2943 the attribute should be ignored. */ 2944 2945 static tree 2946 riscv_handle_type_attribute (tree *node ATTRIBUTE_UNUSED, tree name, tree args, 2947 int flags ATTRIBUTE_UNUSED, bool *no_add_attrs) 2948 { 2949 /* Check for an argument. */ 2950 if (is_attribute_p ("interrupt", name)) 2951 { 2952 if (args) 2953 { 2954 tree cst = TREE_VALUE (args); 2955 const char *string; 2956 2957 if (TREE_CODE (cst) != STRING_CST) 2958 { 2959 warning (OPT_Wattributes, 2960 "%qE attribute requires a string argument", 2961 name); 2962 *no_add_attrs = true; 2963 return NULL_TREE; 2964 } 2965 2966 string = TREE_STRING_POINTER (cst); 2967 if (strcmp (string, "user") && strcmp (string, "supervisor") 2968 && strcmp (string, "machine")) 2969 { 2970 warning (OPT_Wattributes, 2971 "argument to %qE attribute is not \"user\", \"supervisor\", or \"machine\"", 2972 name); 2973 *no_add_attrs = true; 2974 } 2975 } 2976 } 2977 2978 return NULL_TREE; 2979 } 2980 2981 /* Return true if function TYPE is an interrupt function. */ 2982 static bool 2983 riscv_interrupt_type_p (tree type) 2984 { 2985 return lookup_attribute ("interrupt", TYPE_ATTRIBUTES (type)) != NULL; 2986 } 2987 2988 /* Return true if FUNC is a naked function. */ 2989 static bool 2990 riscv_naked_function_p (tree func) 2991 { 2992 tree func_decl = func; 2993 if (func == NULL_TREE) 2994 func_decl = current_function_decl; 2995 return NULL_TREE != lookup_attribute ("naked", DECL_ATTRIBUTES (func_decl)); 2996 } 2997 2998 /* Implement TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS. */ 2999 static bool 3000 riscv_allocate_stack_slots_for_args () 3001 { 3002 /* Naked functions should not allocate stack slots for arguments. */ 3003 return !riscv_naked_function_p (current_function_decl); 3004 } 3005 3006 /* Implement TARGET_WARN_FUNC_RETURN. */ 3007 static bool 3008 riscv_warn_func_return (tree decl) 3009 { 3010 /* Naked functions are implemented entirely in assembly, including the 3011 return sequence, so suppress warnings about this. */ 3012 return !riscv_naked_function_p (decl); 3013 } 3014 3015 /* Implement TARGET_EXPAND_BUILTIN_VA_START. */ 3016 3017 static void 3018 riscv_va_start (tree valist, rtx nextarg) 3019 { 3020 nextarg = plus_constant (Pmode, nextarg, -cfun->machine->varargs_size); 3021 std_expand_builtin_va_start (valist, nextarg); 3022 } 3023 3024 /* Make ADDR suitable for use as a call or sibcall target. */ 3025 3026 rtx 3027 riscv_legitimize_call_address (rtx addr) 3028 { 3029 if (!call_insn_operand (addr, VOIDmode)) 3030 { 3031 rtx reg = RISCV_CALL_ADDRESS_TEMP (Pmode); 3032 riscv_emit_move (reg, addr); 3033 return reg; 3034 } 3035 return addr; 3036 } 3037 3038 /* Emit straight-line code to move LENGTH bytes from SRC to DEST. 3039 Assume that the areas do not overlap. */ 3040 3041 static void 3042 riscv_block_move_straight (rtx dest, rtx src, unsigned HOST_WIDE_INT length) 3043 { 3044 unsigned HOST_WIDE_INT offset, delta; 3045 unsigned HOST_WIDE_INT bits; 3046 int i; 3047 enum machine_mode mode; 3048 rtx *regs; 3049 3050 bits = MAX (BITS_PER_UNIT, 3051 MIN (BITS_PER_WORD, MIN (MEM_ALIGN (src), MEM_ALIGN (dest)))); 3052 3053 mode = mode_for_size (bits, MODE_INT, 0).require (); 3054 delta = bits / BITS_PER_UNIT; 3055 3056 /* Allocate a buffer for the temporary registers. */ 3057 regs = XALLOCAVEC (rtx, length / delta); 3058 3059 /* Load as many BITS-sized chunks as possible. Use a normal load if 3060 the source has enough alignment, otherwise use left/right pairs. */ 3061 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 3062 { 3063 regs[i] = gen_reg_rtx (mode); 3064 riscv_emit_move (regs[i], adjust_address (src, mode, offset)); 3065 } 3066 3067 /* Copy the chunks to the destination. */ 3068 for (offset = 0, i = 0; offset + delta <= length; offset += delta, i++) 3069 riscv_emit_move (adjust_address (dest, mode, offset), regs[i]); 3070 3071 /* Mop up any left-over bytes. */ 3072 if (offset < length) 3073 { 3074 src = adjust_address (src, BLKmode, offset); 3075 dest = adjust_address (dest, BLKmode, offset); 3076 move_by_pieces (dest, src, length - offset, 3077 MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), RETURN_BEGIN); 3078 } 3079 } 3080 3081 /* Helper function for doing a loop-based block operation on memory 3082 reference MEM. Each iteration of the loop will operate on LENGTH 3083 bytes of MEM. 3084 3085 Create a new base register for use within the loop and point it to 3086 the start of MEM. Create a new memory reference that uses this 3087 register. Store them in *LOOP_REG and *LOOP_MEM respectively. */ 3088 3089 static void 3090 riscv_adjust_block_mem (rtx mem, unsigned HOST_WIDE_INT length, 3091 rtx *loop_reg, rtx *loop_mem) 3092 { 3093 *loop_reg = copy_addr_to_reg (XEXP (mem, 0)); 3094 3095 /* Although the new mem does not refer to a known location, 3096 it does keep up to LENGTH bytes of alignment. */ 3097 *loop_mem = change_address (mem, BLKmode, *loop_reg); 3098 set_mem_align (*loop_mem, MIN (MEM_ALIGN (mem), length * BITS_PER_UNIT)); 3099 } 3100 3101 /* Move LENGTH bytes from SRC to DEST using a loop that moves BYTES_PER_ITER 3102 bytes at a time. LENGTH must be at least BYTES_PER_ITER. Assume that 3103 the memory regions do not overlap. */ 3104 3105 static void 3106 riscv_block_move_loop (rtx dest, rtx src, unsigned HOST_WIDE_INT length, 3107 unsigned HOST_WIDE_INT bytes_per_iter) 3108 { 3109 rtx label, src_reg, dest_reg, final_src, test; 3110 unsigned HOST_WIDE_INT leftover; 3111 3112 leftover = length % bytes_per_iter; 3113 length -= leftover; 3114 3115 /* Create registers and memory references for use within the loop. */ 3116 riscv_adjust_block_mem (src, bytes_per_iter, &src_reg, &src); 3117 riscv_adjust_block_mem (dest, bytes_per_iter, &dest_reg, &dest); 3118 3119 /* Calculate the value that SRC_REG should have after the last iteration 3120 of the loop. */ 3121 final_src = expand_simple_binop (Pmode, PLUS, src_reg, GEN_INT (length), 3122 0, 0, OPTAB_WIDEN); 3123 3124 /* Emit the start of the loop. */ 3125 label = gen_label_rtx (); 3126 emit_label (label); 3127 3128 /* Emit the loop body. */ 3129 riscv_block_move_straight (dest, src, bytes_per_iter); 3130 3131 /* Move on to the next block. */ 3132 riscv_emit_move (src_reg, plus_constant (Pmode, src_reg, bytes_per_iter)); 3133 riscv_emit_move (dest_reg, plus_constant (Pmode, dest_reg, bytes_per_iter)); 3134 3135 /* Emit the loop condition. */ 3136 test = gen_rtx_NE (VOIDmode, src_reg, final_src); 3137 if (Pmode == DImode) 3138 emit_jump_insn (gen_cbranchdi4 (test, src_reg, final_src, label)); 3139 else 3140 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); 3141 3142 /* Mop up any left-over bytes. */ 3143 if (leftover) 3144 riscv_block_move_straight (dest, src, leftover); 3145 else 3146 emit_insn(gen_nop ()); 3147 } 3148 3149 /* Expand a cpymemsi instruction, which copies LENGTH bytes from 3150 memory reference SRC to memory reference DEST. */ 3151 3152 bool 3153 riscv_expand_block_move (rtx dest, rtx src, rtx length) 3154 { 3155 if (CONST_INT_P (length)) 3156 { 3157 unsigned HOST_WIDE_INT hwi_length = UINTVAL (length); 3158 unsigned HOST_WIDE_INT factor, align; 3159 3160 align = MIN (MIN (MEM_ALIGN (src), MEM_ALIGN (dest)), BITS_PER_WORD); 3161 factor = BITS_PER_WORD / align; 3162 3163 if (optimize_function_for_size_p (cfun) 3164 && hwi_length * factor * UNITS_PER_WORD > MOVE_RATIO (false)) 3165 return false; 3166 3167 if (hwi_length <= (RISCV_MAX_MOVE_BYTES_STRAIGHT / factor)) 3168 { 3169 riscv_block_move_straight (dest, src, INTVAL (length)); 3170 return true; 3171 } 3172 else if (optimize && align >= BITS_PER_WORD) 3173 { 3174 unsigned min_iter_words 3175 = RISCV_MAX_MOVE_BYTES_PER_LOOP_ITER / UNITS_PER_WORD; 3176 unsigned iter_words = min_iter_words; 3177 unsigned HOST_WIDE_INT bytes = hwi_length; 3178 unsigned HOST_WIDE_INT words = bytes / UNITS_PER_WORD; 3179 3180 /* Lengthen the loop body if it shortens the tail. */ 3181 for (unsigned i = min_iter_words; i < min_iter_words * 2 - 1; i++) 3182 { 3183 unsigned cur_cost = iter_words + words % iter_words; 3184 unsigned new_cost = i + words % i; 3185 if (new_cost <= cur_cost) 3186 iter_words = i; 3187 } 3188 3189 riscv_block_move_loop (dest, src, bytes, iter_words * UNITS_PER_WORD); 3190 return true; 3191 } 3192 } 3193 return false; 3194 } 3195 3196 /* Print symbolic operand OP, which is part of a HIGH or LO_SUM 3197 in context CONTEXT. HI_RELOC indicates a high-part reloc. */ 3198 3199 static void 3200 riscv_print_operand_reloc (FILE *file, rtx op, bool hi_reloc) 3201 { 3202 const char *reloc; 3203 3204 switch (riscv_classify_symbolic_expression (op)) 3205 { 3206 case SYMBOL_ABSOLUTE: 3207 reloc = hi_reloc ? "%hi" : "%lo"; 3208 break; 3209 3210 case SYMBOL_PCREL: 3211 reloc = hi_reloc ? "%pcrel_hi" : "%pcrel_lo"; 3212 break; 3213 3214 case SYMBOL_TLS_LE: 3215 reloc = hi_reloc ? "%tprel_hi" : "%tprel_lo"; 3216 break; 3217 3218 default: 3219 output_operand_lossage ("invalid use of '%%%c'", hi_reloc ? 'h' : 'R'); 3220 return; 3221 } 3222 3223 fprintf (file, "%s(", reloc); 3224 output_addr_const (file, riscv_strip_unspec_address (op)); 3225 fputc (')', file); 3226 } 3227 3228 /* Return true if the .AQ suffix should be added to an AMO to implement the 3229 acquire portion of memory model MODEL. */ 3230 3231 static bool 3232 riscv_memmodel_needs_amo_acquire (enum memmodel model) 3233 { 3234 switch (model) 3235 { 3236 case MEMMODEL_ACQ_REL: 3237 case MEMMODEL_SEQ_CST: 3238 case MEMMODEL_SYNC_SEQ_CST: 3239 case MEMMODEL_ACQUIRE: 3240 case MEMMODEL_CONSUME: 3241 case MEMMODEL_SYNC_ACQUIRE: 3242 return true; 3243 3244 case MEMMODEL_RELEASE: 3245 case MEMMODEL_SYNC_RELEASE: 3246 case MEMMODEL_RELAXED: 3247 return false; 3248 3249 default: 3250 gcc_unreachable (); 3251 } 3252 } 3253 3254 /* Return true if a FENCE should be emitted to before a memory access to 3255 implement the release portion of memory model MODEL. */ 3256 3257 static bool 3258 riscv_memmodel_needs_release_fence (enum memmodel model) 3259 { 3260 switch (model) 3261 { 3262 case MEMMODEL_ACQ_REL: 3263 case MEMMODEL_SEQ_CST: 3264 case MEMMODEL_SYNC_SEQ_CST: 3265 case MEMMODEL_RELEASE: 3266 case MEMMODEL_SYNC_RELEASE: 3267 return true; 3268 3269 case MEMMODEL_ACQUIRE: 3270 case MEMMODEL_CONSUME: 3271 case MEMMODEL_SYNC_ACQUIRE: 3272 case MEMMODEL_RELAXED: 3273 return false; 3274 3275 default: 3276 gcc_unreachable (); 3277 } 3278 } 3279 3280 /* Implement TARGET_PRINT_OPERAND. The RISCV-specific operand codes are: 3281 3282 'h' Print the high-part relocation associated with OP, after stripping 3283 any outermost HIGH. 3284 'R' Print the low-part relocation associated with OP. 3285 'C' Print the integer branch condition for comparison OP. 3286 'A' Print the atomic operation suffix for memory model OP. 3287 'F' Print a FENCE if the memory model requires a release. 3288 'z' Print x0 if OP is zero, otherwise print OP normally. 3289 'i' Print i if the operand is not a register. */ 3290 3291 static void 3292 riscv_print_operand (FILE *file, rtx op, int letter) 3293 { 3294 machine_mode mode = GET_MODE (op); 3295 enum rtx_code code = GET_CODE (op); 3296 3297 switch (letter) 3298 { 3299 case 'h': 3300 if (code == HIGH) 3301 op = XEXP (op, 0); 3302 riscv_print_operand_reloc (file, op, true); 3303 break; 3304 3305 case 'R': 3306 riscv_print_operand_reloc (file, op, false); 3307 break; 3308 3309 case 'C': 3310 /* The RTL names match the instruction names. */ 3311 fputs (GET_RTX_NAME (code), file); 3312 break; 3313 3314 case 'A': 3315 if (riscv_memmodel_needs_amo_acquire ((enum memmodel) INTVAL (op))) 3316 fputs (".aq", file); 3317 break; 3318 3319 case 'F': 3320 if (riscv_memmodel_needs_release_fence ((enum memmodel) INTVAL (op))) 3321 fputs ("fence iorw,ow; ", file); 3322 break; 3323 3324 case 'i': 3325 if (code != REG) 3326 fputs ("i", file); 3327 break; 3328 3329 default: 3330 switch (code) 3331 { 3332 case REG: 3333 if (letter && letter != 'z') 3334 output_operand_lossage ("invalid use of '%%%c'", letter); 3335 fprintf (file, "%s", reg_names[REGNO (op)]); 3336 break; 3337 3338 case MEM: 3339 if (letter && letter != 'z') 3340 output_operand_lossage ("invalid use of '%%%c'", letter); 3341 else 3342 output_address (mode, XEXP (op, 0)); 3343 break; 3344 3345 default: 3346 if (letter == 'z' && op == CONST0_RTX (GET_MODE (op))) 3347 fputs (reg_names[GP_REG_FIRST], file); 3348 else if (letter && letter != 'z') 3349 output_operand_lossage ("invalid use of '%%%c'", letter); 3350 else 3351 output_addr_const (file, riscv_strip_unspec_address (op)); 3352 break; 3353 } 3354 } 3355 } 3356 3357 /* Implement TARGET_PRINT_OPERAND_ADDRESS. */ 3358 3359 static void 3360 riscv_print_operand_address (FILE *file, machine_mode mode ATTRIBUTE_UNUSED, rtx x) 3361 { 3362 struct riscv_address_info addr; 3363 3364 if (riscv_classify_address (&addr, x, word_mode, true)) 3365 switch (addr.type) 3366 { 3367 case ADDRESS_REG: 3368 riscv_print_operand (file, addr.offset, 0); 3369 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 3370 return; 3371 3372 case ADDRESS_LO_SUM: 3373 riscv_print_operand_reloc (file, addr.offset, false); 3374 fprintf (file, "(%s)", reg_names[REGNO (addr.reg)]); 3375 return; 3376 3377 case ADDRESS_CONST_INT: 3378 output_addr_const (file, x); 3379 fprintf (file, "(%s)", reg_names[GP_REG_FIRST]); 3380 return; 3381 3382 case ADDRESS_SYMBOLIC: 3383 output_addr_const (file, riscv_strip_unspec_address (x)); 3384 return; 3385 } 3386 gcc_unreachable (); 3387 } 3388 3389 static bool 3390 riscv_size_ok_for_small_data_p (int size) 3391 { 3392 return g_switch_value && IN_RANGE (size, 1, g_switch_value); 3393 } 3394 3395 /* Return true if EXP should be placed in the small data section. */ 3396 3397 static bool 3398 riscv_in_small_data_p (const_tree x) 3399 { 3400 if (TREE_CODE (x) == STRING_CST || TREE_CODE (x) == FUNCTION_DECL) 3401 return false; 3402 3403 if (TREE_CODE (x) == VAR_DECL && DECL_SECTION_NAME (x)) 3404 { 3405 const char *sec = DECL_SECTION_NAME (x); 3406 return strcmp (sec, ".sdata") == 0 || strcmp (sec, ".sbss") == 0; 3407 } 3408 3409 return riscv_size_ok_for_small_data_p (int_size_in_bytes (TREE_TYPE (x))); 3410 } 3411 3412 /* Switch to the appropriate section for output of DECL. */ 3413 3414 static section * 3415 riscv_select_section (tree decl, int reloc, 3416 unsigned HOST_WIDE_INT align) 3417 { 3418 switch (categorize_decl_for_section (decl, reloc)) 3419 { 3420 case SECCAT_SRODATA: 3421 return get_named_section (decl, ".srodata", reloc); 3422 3423 default: 3424 return default_elf_select_section (decl, reloc, align); 3425 } 3426 } 3427 3428 /* Switch to the appropriate section for output of DECL. */ 3429 3430 static void 3431 riscv_unique_section (tree decl, int reloc) 3432 { 3433 const char *prefix = NULL; 3434 bool one_only = DECL_ONE_ONLY (decl) && !HAVE_COMDAT_GROUP; 3435 3436 switch (categorize_decl_for_section (decl, reloc)) 3437 { 3438 case SECCAT_SRODATA: 3439 prefix = one_only ? ".sr" : ".srodata"; 3440 break; 3441 3442 default: 3443 break; 3444 } 3445 if (prefix) 3446 { 3447 const char *name, *linkonce; 3448 char *string; 3449 3450 name = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (decl)); 3451 name = targetm.strip_name_encoding (name); 3452 3453 /* If we're using one_only, then there needs to be a .gnu.linkonce 3454 prefix to the section name. */ 3455 linkonce = one_only ? ".gnu.linkonce" : ""; 3456 3457 string = ACONCAT ((linkonce, prefix, ".", name, NULL)); 3458 3459 set_decl_section_name (decl, string); 3460 return; 3461 } 3462 default_unique_section (decl, reloc); 3463 } 3464 3465 /* Return a section for X, handling small data. */ 3466 3467 static section * 3468 riscv_elf_select_rtx_section (machine_mode mode, rtx x, 3469 unsigned HOST_WIDE_INT align) 3470 { 3471 section *s = default_elf_select_rtx_section (mode, x, align); 3472 3473 if (riscv_size_ok_for_small_data_p (GET_MODE_SIZE (mode))) 3474 { 3475 if (strncmp (s->named.name, ".rodata.cst", strlen (".rodata.cst")) == 0) 3476 { 3477 /* Rename .rodata.cst* to .srodata.cst*. */ 3478 char *name = (char *) alloca (strlen (s->named.name) + 2); 3479 sprintf (name, ".s%s", s->named.name + 1); 3480 return get_section (name, s->named.common.flags, NULL); 3481 } 3482 3483 if (s == data_section) 3484 return sdata_section; 3485 } 3486 3487 return s; 3488 } 3489 3490 /* Make the last instruction frame-related and note that it performs 3491 the operation described by FRAME_PATTERN. */ 3492 3493 static void 3494 riscv_set_frame_expr (rtx frame_pattern) 3495 { 3496 rtx insn; 3497 3498 insn = get_last_insn (); 3499 RTX_FRAME_RELATED_P (insn) = 1; 3500 REG_NOTES (insn) = alloc_EXPR_LIST (REG_FRAME_RELATED_EXPR, 3501 frame_pattern, 3502 REG_NOTES (insn)); 3503 } 3504 3505 /* Return a frame-related rtx that stores REG at MEM. 3506 REG must be a single register. */ 3507 3508 static rtx 3509 riscv_frame_set (rtx mem, rtx reg) 3510 { 3511 rtx set = gen_rtx_SET (mem, reg); 3512 RTX_FRAME_RELATED_P (set) = 1; 3513 return set; 3514 } 3515 3516 /* Return true if the current function must save register REGNO. */ 3517 3518 static bool 3519 riscv_save_reg_p (unsigned int regno) 3520 { 3521 bool call_saved = !global_regs[regno] && !call_used_or_fixed_reg_p (regno); 3522 bool might_clobber = crtl->saves_all_registers 3523 || df_regs_ever_live_p (regno); 3524 3525 if (call_saved && might_clobber) 3526 return true; 3527 3528 if (regno == HARD_FRAME_POINTER_REGNUM && frame_pointer_needed) 3529 return true; 3530 3531 if (regno == RETURN_ADDR_REGNUM && crtl->calls_eh_return) 3532 return true; 3533 3534 /* If this is an interrupt handler, then must save extra registers. */ 3535 if (cfun->machine->interrupt_handler_p) 3536 { 3537 /* zero register is always zero. */ 3538 if (regno == GP_REG_FIRST) 3539 return false; 3540 3541 /* The function will return the stack pointer to its original value. */ 3542 if (regno == STACK_POINTER_REGNUM) 3543 return false; 3544 3545 /* By convention, we assume that gp and tp are safe. */ 3546 if (regno == GP_REGNUM || regno == THREAD_POINTER_REGNUM) 3547 return false; 3548 3549 /* We must save every register used in this function. If this is not a 3550 leaf function, then we must save all temporary registers. */ 3551 if (df_regs_ever_live_p (regno) 3552 || (!crtl->is_leaf && call_used_or_fixed_reg_p (regno))) 3553 return true; 3554 } 3555 3556 return false; 3557 } 3558 3559 /* Determine whether to call GPR save/restore routines. */ 3560 static bool 3561 riscv_use_save_libcall (const struct riscv_frame_info *frame) 3562 { 3563 if (!TARGET_SAVE_RESTORE || crtl->calls_eh_return || frame_pointer_needed 3564 || cfun->machine->interrupt_handler_p) 3565 return false; 3566 3567 return frame->save_libcall_adjustment != 0; 3568 } 3569 3570 /* Determine which GPR save/restore routine to call. */ 3571 3572 static unsigned 3573 riscv_save_libcall_count (unsigned mask) 3574 { 3575 for (unsigned n = GP_REG_LAST; n > GP_REG_FIRST; n--) 3576 if (BITSET_P (mask, n)) 3577 return CALLEE_SAVED_REG_NUMBER (n) + 1; 3578 abort (); 3579 } 3580 3581 /* Populate the current function's riscv_frame_info structure. 3582 3583 RISC-V stack frames grown downward. High addresses are at the top. 3584 3585 +-------------------------------+ 3586 | | 3587 | incoming stack arguments | 3588 | | 3589 +-------------------------------+ <-- incoming stack pointer 3590 | | 3591 | callee-allocated save area | 3592 | for arguments that are | 3593 | split between registers and | 3594 | the stack | 3595 | | 3596 +-------------------------------+ <-- arg_pointer_rtx 3597 | | 3598 | callee-allocated save area | 3599 | for register varargs | 3600 | | 3601 +-------------------------------+ <-- hard_frame_pointer_rtx; 3602 | | stack_pointer_rtx + gp_sp_offset 3603 | GPR save area | + UNITS_PER_WORD 3604 | | 3605 +-------------------------------+ <-- stack_pointer_rtx + fp_sp_offset 3606 | | + UNITS_PER_HWVALUE 3607 | FPR save area | 3608 | | 3609 +-------------------------------+ <-- frame_pointer_rtx (virtual) 3610 | | 3611 | local variables | 3612 | | 3613 P +-------------------------------+ 3614 | | 3615 | outgoing stack arguments | 3616 | | 3617 +-------------------------------+ <-- stack_pointer_rtx 3618 3619 Dynamic stack allocations such as alloca insert data at point P. 3620 They decrease stack_pointer_rtx but leave frame_pointer_rtx and 3621 hard_frame_pointer_rtx unchanged. */ 3622 3623 static HOST_WIDE_INT riscv_first_stack_step (struct riscv_frame_info *frame); 3624 3625 static void 3626 riscv_compute_frame_info (void) 3627 { 3628 struct riscv_frame_info *frame; 3629 HOST_WIDE_INT offset; 3630 bool interrupt_save_prologue_temp = false; 3631 unsigned int regno, i, num_x_saved = 0, num_f_saved = 0; 3632 3633 frame = &cfun->machine->frame; 3634 3635 /* In an interrupt function, if we have a large frame, then we need to 3636 save/restore t0. We check for this before clearing the frame struct. */ 3637 if (cfun->machine->interrupt_handler_p) 3638 { 3639 HOST_WIDE_INT step1 = riscv_first_stack_step (frame); 3640 if (! SMALL_OPERAND (frame->total_size - step1)) 3641 interrupt_save_prologue_temp = true; 3642 } 3643 3644 memset (frame, 0, sizeof (*frame)); 3645 3646 if (!cfun->machine->naked_p) 3647 { 3648 /* Find out which GPRs we need to save. */ 3649 for (regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 3650 if (riscv_save_reg_p (regno) 3651 || (interrupt_save_prologue_temp 3652 && (regno == RISCV_PROLOGUE_TEMP_REGNUM))) 3653 frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++; 3654 3655 /* If this function calls eh_return, we must also save and restore the 3656 EH data registers. */ 3657 if (crtl->calls_eh_return) 3658 for (i = 0; (regno = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; i++) 3659 frame->mask |= 1 << (regno - GP_REG_FIRST), num_x_saved++; 3660 3661 /* Find out which FPRs we need to save. This loop must iterate over 3662 the same space as its companion in riscv_for_each_saved_reg. */ 3663 if (TARGET_HARD_FLOAT) 3664 for (regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 3665 if (riscv_save_reg_p (regno)) 3666 frame->fmask |= 1 << (regno - FP_REG_FIRST), num_f_saved++; 3667 } 3668 3669 /* At the bottom of the frame are any outgoing stack arguments. */ 3670 offset = RISCV_STACK_ALIGN (crtl->outgoing_args_size); 3671 /* Next are local stack variables. */ 3672 offset += RISCV_STACK_ALIGN (get_frame_size ()); 3673 /* The virtual frame pointer points above the local variables. */ 3674 frame->frame_pointer_offset = offset; 3675 /* Next are the callee-saved FPRs. */ 3676 if (frame->fmask) 3677 offset += RISCV_STACK_ALIGN (num_f_saved * UNITS_PER_FP_REG); 3678 frame->fp_sp_offset = offset - UNITS_PER_FP_REG; 3679 /* Next are the callee-saved GPRs. */ 3680 if (frame->mask) 3681 { 3682 unsigned x_save_size = RISCV_STACK_ALIGN (num_x_saved * UNITS_PER_WORD); 3683 unsigned num_save_restore = 1 + riscv_save_libcall_count (frame->mask); 3684 3685 /* Only use save/restore routines if they don't alter the stack size. */ 3686 if (RISCV_STACK_ALIGN (num_save_restore * UNITS_PER_WORD) == x_save_size) 3687 { 3688 /* Libcall saves/restores 3 registers at once, so we need to 3689 allocate 12 bytes for callee-saved register. */ 3690 if (TARGET_RVE) 3691 x_save_size = 3 * UNITS_PER_WORD; 3692 3693 frame->save_libcall_adjustment = x_save_size; 3694 } 3695 3696 offset += x_save_size; 3697 } 3698 frame->gp_sp_offset = offset - UNITS_PER_WORD; 3699 /* The hard frame pointer points above the callee-saved GPRs. */ 3700 frame->hard_frame_pointer_offset = offset; 3701 /* Above the hard frame pointer is the callee-allocated varags save area. */ 3702 offset += RISCV_STACK_ALIGN (cfun->machine->varargs_size); 3703 /* Next is the callee-allocated area for pretend stack arguments. */ 3704 offset += RISCV_STACK_ALIGN (crtl->args.pretend_args_size); 3705 /* Arg pointer must be below pretend args, but must be above alignment 3706 padding. */ 3707 frame->arg_pointer_offset = offset - crtl->args.pretend_args_size; 3708 frame->total_size = offset; 3709 /* Next points the incoming stack pointer and any incoming arguments. */ 3710 3711 /* Only use save/restore routines when the GPRs are atop the frame. */ 3712 if (frame->hard_frame_pointer_offset != frame->total_size) 3713 frame->save_libcall_adjustment = 0; 3714 } 3715 3716 /* Make sure that we're not trying to eliminate to the wrong hard frame 3717 pointer. */ 3718 3719 static bool 3720 riscv_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 3721 { 3722 return (to == HARD_FRAME_POINTER_REGNUM || to == STACK_POINTER_REGNUM); 3723 } 3724 3725 /* Implement INITIAL_ELIMINATION_OFFSET. FROM is either the frame pointer 3726 or argument pointer. TO is either the stack pointer or hard frame 3727 pointer. */ 3728 3729 HOST_WIDE_INT 3730 riscv_initial_elimination_offset (int from, int to) 3731 { 3732 HOST_WIDE_INT src, dest; 3733 3734 riscv_compute_frame_info (); 3735 3736 if (to == HARD_FRAME_POINTER_REGNUM) 3737 dest = cfun->machine->frame.hard_frame_pointer_offset; 3738 else if (to == STACK_POINTER_REGNUM) 3739 dest = 0; /* The stack pointer is the base of all offsets, hence 0. */ 3740 else 3741 gcc_unreachable (); 3742 3743 if (from == FRAME_POINTER_REGNUM) 3744 src = cfun->machine->frame.frame_pointer_offset; 3745 else if (from == ARG_POINTER_REGNUM) 3746 src = cfun->machine->frame.arg_pointer_offset; 3747 else 3748 gcc_unreachable (); 3749 3750 return src - dest; 3751 } 3752 3753 /* Implement RETURN_ADDR_RTX. We do not support moving back to a 3754 previous frame. */ 3755 3756 rtx 3757 riscv_return_addr (int count, rtx frame ATTRIBUTE_UNUSED) 3758 { 3759 if (count != 0) 3760 return const0_rtx; 3761 3762 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); 3763 } 3764 3765 /* Emit code to change the current function's return address to 3766 ADDRESS. SCRATCH is available as a scratch register, if needed. 3767 ADDRESS and SCRATCH are both word-mode GPRs. */ 3768 3769 void 3770 riscv_set_return_address (rtx address, rtx scratch) 3771 { 3772 rtx slot_address; 3773 3774 gcc_assert (BITSET_P (cfun->machine->frame.mask, RETURN_ADDR_REGNUM)); 3775 slot_address = riscv_add_offset (scratch, stack_pointer_rtx, 3776 cfun->machine->frame.gp_sp_offset); 3777 riscv_emit_move (gen_frame_mem (GET_MODE (address), slot_address), address); 3778 } 3779 3780 /* A function to save or store a register. The first argument is the 3781 register and the second is the stack slot. */ 3782 typedef void (*riscv_save_restore_fn) (rtx, rtx); 3783 3784 /* Use FN to save or restore register REGNO. MODE is the register's 3785 mode and OFFSET is the offset of its save slot from the current 3786 stack pointer. */ 3787 3788 static void 3789 riscv_save_restore_reg (machine_mode mode, int regno, 3790 HOST_WIDE_INT offset, riscv_save_restore_fn fn) 3791 { 3792 rtx mem; 3793 3794 mem = gen_frame_mem (mode, plus_constant (Pmode, stack_pointer_rtx, offset)); 3795 fn (gen_rtx_REG (mode, regno), mem); 3796 } 3797 3798 /* Call FN for each register that is saved by the current function. 3799 SP_OFFSET is the offset of the current stack pointer from the start 3800 of the frame. */ 3801 3802 static void 3803 riscv_for_each_saved_reg (HOST_WIDE_INT sp_offset, riscv_save_restore_fn fn, 3804 bool epilogue, bool maybe_eh_return) 3805 { 3806 HOST_WIDE_INT offset; 3807 3808 /* Save the link register and s-registers. */ 3809 offset = cfun->machine->frame.gp_sp_offset - sp_offset; 3810 for (unsigned int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 3811 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 3812 { 3813 bool handle_reg = TRUE; 3814 3815 /* If this is a normal return in a function that calls the eh_return 3816 builtin, then do not restore the eh return data registers as that 3817 would clobber the return value. But we do still need to save them 3818 in the prologue, and restore them for an exception return, so we 3819 need special handling here. */ 3820 if (epilogue && !maybe_eh_return && crtl->calls_eh_return) 3821 { 3822 unsigned int i, regnum; 3823 3824 for (i = 0; (regnum = EH_RETURN_DATA_REGNO (i)) != INVALID_REGNUM; 3825 i++) 3826 if (regno == regnum) 3827 { 3828 handle_reg = FALSE; 3829 break; 3830 } 3831 } 3832 3833 if (handle_reg) 3834 riscv_save_restore_reg (word_mode, regno, offset, fn); 3835 offset -= UNITS_PER_WORD; 3836 } 3837 3838 /* This loop must iterate over the same space as its companion in 3839 riscv_compute_frame_info. */ 3840 offset = cfun->machine->frame.fp_sp_offset - sp_offset; 3841 for (unsigned int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 3842 if (BITSET_P (cfun->machine->frame.fmask, regno - FP_REG_FIRST)) 3843 { 3844 machine_mode mode = TARGET_DOUBLE_FLOAT ? DFmode : SFmode; 3845 3846 riscv_save_restore_reg (mode, regno, offset, fn); 3847 offset -= GET_MODE_SIZE (mode); 3848 } 3849 } 3850 3851 /* Save register REG to MEM. Make the instruction frame-related. */ 3852 3853 static void 3854 riscv_save_reg (rtx reg, rtx mem) 3855 { 3856 riscv_emit_move (mem, reg); 3857 riscv_set_frame_expr (riscv_frame_set (mem, reg)); 3858 } 3859 3860 /* Restore register REG from MEM. */ 3861 3862 static void 3863 riscv_restore_reg (rtx reg, rtx mem) 3864 { 3865 rtx insn = riscv_emit_move (reg, mem); 3866 rtx dwarf = NULL_RTX; 3867 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 3868 3869 if (epilogue_cfa_sp_offset && REGNO (reg) == HARD_FRAME_POINTER_REGNUM) 3870 { 3871 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 3872 GEN_INT (epilogue_cfa_sp_offset)); 3873 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 3874 } 3875 3876 REG_NOTES (insn) = dwarf; 3877 RTX_FRAME_RELATED_P (insn) = 1; 3878 } 3879 3880 /* For stack frames that can't be allocated with a single ADDI instruction, 3881 compute the best value to initially allocate. It must at a minimum 3882 allocate enough space to spill the callee-saved registers. If TARGET_RVC, 3883 try to pick a value that will allow compression of the register saves 3884 without adding extra instructions. */ 3885 3886 static HOST_WIDE_INT 3887 riscv_first_stack_step (struct riscv_frame_info *frame) 3888 { 3889 if (SMALL_OPERAND (frame->total_size)) 3890 return frame->total_size; 3891 3892 HOST_WIDE_INT min_first_step = 3893 RISCV_STACK_ALIGN (frame->total_size - frame->fp_sp_offset); 3894 HOST_WIDE_INT max_first_step = IMM_REACH / 2 - PREFERRED_STACK_BOUNDARY / 8; 3895 HOST_WIDE_INT min_second_step = frame->total_size - max_first_step; 3896 gcc_assert (min_first_step <= max_first_step); 3897 3898 /* As an optimization, use the least-significant bits of the total frame 3899 size, so that the second adjustment step is just LUI + ADD. */ 3900 if (!SMALL_OPERAND (min_second_step) 3901 && frame->total_size % IMM_REACH < IMM_REACH / 2 3902 && frame->total_size % IMM_REACH >= min_first_step) 3903 return frame->total_size % IMM_REACH; 3904 3905 if (TARGET_RVC) 3906 { 3907 /* If we need two subtracts, and one is small enough to allow compressed 3908 loads and stores, then put that one first. */ 3909 if (IN_RANGE (min_second_step, 0, 3910 (TARGET_64BIT ? SDSP_REACH : SWSP_REACH))) 3911 return MAX (min_second_step, min_first_step); 3912 3913 /* If we need LUI + ADDI + ADD for the second adjustment step, then start 3914 with the minimum first step, so that we can get compressed loads and 3915 stores. */ 3916 else if (!SMALL_OPERAND (min_second_step)) 3917 return min_first_step; 3918 } 3919 3920 return max_first_step; 3921 } 3922 3923 static rtx 3924 riscv_adjust_libcall_cfi_prologue () 3925 { 3926 rtx dwarf = NULL_RTX; 3927 rtx adjust_sp_rtx, reg, mem, insn; 3928 int saved_size = cfun->machine->frame.save_libcall_adjustment; 3929 int offset; 3930 3931 for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 3932 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 3933 { 3934 /* The save order is ra, s0, s1, s2 to s11. */ 3935 if (regno == RETURN_ADDR_REGNUM) 3936 offset = saved_size - UNITS_PER_WORD; 3937 else if (regno == S0_REGNUM) 3938 offset = saved_size - UNITS_PER_WORD * 2; 3939 else if (regno == S1_REGNUM) 3940 offset = saved_size - UNITS_PER_WORD * 3; 3941 else 3942 offset = saved_size - ((regno - S2_REGNUM + 4) * UNITS_PER_WORD); 3943 3944 reg = gen_rtx_REG (SImode, regno); 3945 mem = gen_frame_mem (SImode, plus_constant (Pmode, 3946 stack_pointer_rtx, 3947 offset)); 3948 3949 insn = gen_rtx_SET (mem, reg); 3950 dwarf = alloc_reg_note (REG_CFA_OFFSET, insn, dwarf); 3951 } 3952 3953 /* Debug info for adjust sp. */ 3954 adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, 3955 stack_pointer_rtx, GEN_INT (-saved_size)); 3956 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, 3957 dwarf); 3958 return dwarf; 3959 } 3960 3961 static void 3962 riscv_emit_stack_tie (void) 3963 { 3964 if (Pmode == SImode) 3965 emit_insn (gen_stack_tiesi (stack_pointer_rtx, hard_frame_pointer_rtx)); 3966 else 3967 emit_insn (gen_stack_tiedi (stack_pointer_rtx, hard_frame_pointer_rtx)); 3968 } 3969 3970 /* Expand the "prologue" pattern. */ 3971 3972 void 3973 riscv_expand_prologue (void) 3974 { 3975 struct riscv_frame_info *frame = &cfun->machine->frame; 3976 HOST_WIDE_INT size = frame->total_size; 3977 unsigned mask = frame->mask; 3978 rtx insn; 3979 3980 if (flag_stack_usage_info) 3981 current_function_static_stack_size = size; 3982 3983 if (cfun->machine->naked_p) 3984 return; 3985 3986 /* When optimizing for size, call a subroutine to save the registers. */ 3987 if (riscv_use_save_libcall (frame)) 3988 { 3989 rtx dwarf = NULL_RTX; 3990 dwarf = riscv_adjust_libcall_cfi_prologue (); 3991 3992 size -= frame->save_libcall_adjustment; 3993 insn = emit_insn (riscv_gen_gpr_save_insn (frame)); 3994 frame->mask = 0; /* Temporarily fib that we need not save GPRs. */ 3995 3996 RTX_FRAME_RELATED_P (insn) = 1; 3997 REG_NOTES (insn) = dwarf; 3998 } 3999 4000 /* Save the registers. */ 4001 if ((frame->mask | frame->fmask) != 0) 4002 { 4003 HOST_WIDE_INT step1 = MIN (size, riscv_first_stack_step (frame)); 4004 4005 insn = gen_add3_insn (stack_pointer_rtx, 4006 stack_pointer_rtx, 4007 GEN_INT (-step1)); 4008 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 4009 size -= step1; 4010 riscv_for_each_saved_reg (size, riscv_save_reg, false, false); 4011 } 4012 4013 frame->mask = mask; /* Undo the above fib. */ 4014 4015 /* Set up the frame pointer, if we're using one. */ 4016 if (frame_pointer_needed) 4017 { 4018 insn = gen_add3_insn (hard_frame_pointer_rtx, stack_pointer_rtx, 4019 GEN_INT (frame->hard_frame_pointer_offset - size)); 4020 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 4021 4022 riscv_emit_stack_tie (); 4023 } 4024 4025 /* Allocate the rest of the frame. */ 4026 if (size > 0) 4027 { 4028 if (SMALL_OPERAND (-size)) 4029 { 4030 insn = gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 4031 GEN_INT (-size)); 4032 RTX_FRAME_RELATED_P (emit_insn (insn)) = 1; 4033 } 4034 else 4035 { 4036 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), GEN_INT (-size)); 4037 emit_insn (gen_add3_insn (stack_pointer_rtx, 4038 stack_pointer_rtx, 4039 RISCV_PROLOGUE_TEMP (Pmode))); 4040 4041 /* Describe the effect of the previous instructions. */ 4042 insn = plus_constant (Pmode, stack_pointer_rtx, -size); 4043 insn = gen_rtx_SET (stack_pointer_rtx, insn); 4044 riscv_set_frame_expr (insn); 4045 } 4046 } 4047 } 4048 4049 static rtx 4050 riscv_adjust_libcall_cfi_epilogue () 4051 { 4052 rtx dwarf = NULL_RTX; 4053 rtx adjust_sp_rtx, reg; 4054 int saved_size = cfun->machine->frame.save_libcall_adjustment; 4055 4056 /* Debug info for adjust sp. */ 4057 adjust_sp_rtx = gen_add3_insn (stack_pointer_rtx, 4058 stack_pointer_rtx, GEN_INT (saved_size)); 4059 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, adjust_sp_rtx, 4060 dwarf); 4061 4062 for (int regno = GP_REG_FIRST; regno <= GP_REG_LAST; regno++) 4063 if (BITSET_P (cfun->machine->frame.mask, regno - GP_REG_FIRST)) 4064 { 4065 reg = gen_rtx_REG (SImode, regno); 4066 dwarf = alloc_reg_note (REG_CFA_RESTORE, reg, dwarf); 4067 } 4068 4069 return dwarf; 4070 } 4071 4072 /* Expand an "epilogue", "sibcall_epilogue", or "eh_return_internal" pattern; 4073 style says which. */ 4074 4075 void 4076 riscv_expand_epilogue (int style) 4077 { 4078 /* Split the frame into two. STEP1 is the amount of stack we should 4079 deallocate before restoring the registers. STEP2 is the amount we 4080 should deallocate afterwards. 4081 4082 Start off by assuming that no registers need to be restored. */ 4083 struct riscv_frame_info *frame = &cfun->machine->frame; 4084 unsigned mask = frame->mask; 4085 HOST_WIDE_INT step1 = frame->total_size; 4086 HOST_WIDE_INT step2 = 0; 4087 bool use_restore_libcall = ((style == NORMAL_RETURN) 4088 && riscv_use_save_libcall (frame)); 4089 rtx ra = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); 4090 rtx insn; 4091 4092 /* We need to add memory barrier to prevent read from deallocated stack. */ 4093 bool need_barrier_p = (get_frame_size () 4094 + cfun->machine->frame.arg_pointer_offset) != 0; 4095 4096 if (cfun->machine->naked_p) 4097 { 4098 gcc_assert (style == NORMAL_RETURN); 4099 4100 emit_jump_insn (gen_return ()); 4101 4102 return; 4103 } 4104 4105 if ((style == NORMAL_RETURN) && riscv_can_use_return_insn ()) 4106 { 4107 emit_jump_insn (gen_return ()); 4108 return; 4109 } 4110 4111 /* Reset the epilogue cfa info before starting to emit the epilogue. */ 4112 epilogue_cfa_sp_offset = 0; 4113 4114 /* Move past any dynamic stack allocations. */ 4115 if (cfun->calls_alloca) 4116 { 4117 /* Emit a barrier to prevent loads from a deallocated stack. */ 4118 riscv_emit_stack_tie (); 4119 need_barrier_p = false; 4120 4121 rtx adjust = GEN_INT (-frame->hard_frame_pointer_offset); 4122 if (!SMALL_OPERAND (INTVAL (adjust))) 4123 { 4124 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); 4125 adjust = RISCV_PROLOGUE_TEMP (Pmode); 4126 } 4127 4128 insn = emit_insn ( 4129 gen_add3_insn (stack_pointer_rtx, hard_frame_pointer_rtx, 4130 adjust)); 4131 4132 rtx dwarf = NULL_RTX; 4133 rtx cfa_adjust_value = gen_rtx_PLUS ( 4134 Pmode, hard_frame_pointer_rtx, 4135 GEN_INT (-frame->hard_frame_pointer_offset)); 4136 rtx cfa_adjust_rtx = gen_rtx_SET (stack_pointer_rtx, cfa_adjust_value); 4137 dwarf = alloc_reg_note (REG_CFA_ADJUST_CFA, cfa_adjust_rtx, dwarf); 4138 RTX_FRAME_RELATED_P (insn) = 1; 4139 4140 REG_NOTES (insn) = dwarf; 4141 } 4142 4143 /* If we need to restore registers, deallocate as much stack as 4144 possible in the second step without going out of range. */ 4145 if ((frame->mask | frame->fmask) != 0) 4146 { 4147 step2 = riscv_first_stack_step (frame); 4148 step1 -= step2; 4149 } 4150 4151 /* Set TARGET to BASE + STEP1. */ 4152 if (step1 > 0) 4153 { 4154 /* Emit a barrier to prevent loads from a deallocated stack. */ 4155 riscv_emit_stack_tie (); 4156 need_barrier_p = false; 4157 4158 /* Get an rtx for STEP1 that we can add to BASE. */ 4159 rtx adjust = GEN_INT (step1); 4160 if (!SMALL_OPERAND (step1)) 4161 { 4162 riscv_emit_move (RISCV_PROLOGUE_TEMP (Pmode), adjust); 4163 adjust = RISCV_PROLOGUE_TEMP (Pmode); 4164 } 4165 4166 insn = emit_insn ( 4167 gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, adjust)); 4168 4169 rtx dwarf = NULL_RTX; 4170 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 4171 GEN_INT (step2)); 4172 4173 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 4174 RTX_FRAME_RELATED_P (insn) = 1; 4175 4176 REG_NOTES (insn) = dwarf; 4177 } 4178 else if (frame_pointer_needed) 4179 { 4180 /* Tell riscv_restore_reg to emit dwarf to redefine CFA when restoring 4181 old value of FP. */ 4182 epilogue_cfa_sp_offset = step2; 4183 } 4184 4185 if (use_restore_libcall) 4186 frame->mask = 0; /* Temporarily fib that we need not save GPRs. */ 4187 4188 /* Restore the registers. */ 4189 riscv_for_each_saved_reg (frame->total_size - step2, riscv_restore_reg, 4190 true, style == EXCEPTION_RETURN); 4191 4192 if (use_restore_libcall) 4193 { 4194 frame->mask = mask; /* Undo the above fib. */ 4195 gcc_assert (step2 >= frame->save_libcall_adjustment); 4196 step2 -= frame->save_libcall_adjustment; 4197 } 4198 4199 if (need_barrier_p) 4200 riscv_emit_stack_tie (); 4201 4202 /* Deallocate the final bit of the frame. */ 4203 if (step2 > 0) 4204 { 4205 insn = emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 4206 GEN_INT (step2))); 4207 4208 rtx dwarf = NULL_RTX; 4209 rtx cfa_adjust_rtx = gen_rtx_PLUS (Pmode, stack_pointer_rtx, 4210 const0_rtx); 4211 dwarf = alloc_reg_note (REG_CFA_DEF_CFA, cfa_adjust_rtx, dwarf); 4212 RTX_FRAME_RELATED_P (insn) = 1; 4213 4214 REG_NOTES (insn) = dwarf; 4215 } 4216 4217 if (use_restore_libcall) 4218 { 4219 rtx dwarf = riscv_adjust_libcall_cfi_epilogue (); 4220 insn = emit_insn (gen_gpr_restore (GEN_INT (riscv_save_libcall_count (mask)))); 4221 RTX_FRAME_RELATED_P (insn) = 1; 4222 REG_NOTES (insn) = dwarf; 4223 4224 emit_jump_insn (gen_gpr_restore_return (ra)); 4225 return; 4226 } 4227 4228 /* Add in the __builtin_eh_return stack adjustment. */ 4229 if ((style == EXCEPTION_RETURN) && crtl->calls_eh_return) 4230 emit_insn (gen_add3_insn (stack_pointer_rtx, stack_pointer_rtx, 4231 EH_RETURN_STACKADJ_RTX)); 4232 4233 /* Return from interrupt. */ 4234 if (cfun->machine->interrupt_handler_p) 4235 { 4236 enum riscv_privilege_levels mode = cfun->machine->interrupt_mode; 4237 4238 gcc_assert (mode != UNKNOWN_MODE); 4239 4240 if (mode == MACHINE_MODE) 4241 emit_jump_insn (gen_riscv_mret ()); 4242 else if (mode == SUPERVISOR_MODE) 4243 emit_jump_insn (gen_riscv_sret ()); 4244 else 4245 emit_jump_insn (gen_riscv_uret ()); 4246 } 4247 else if (style != SIBCALL_RETURN) 4248 emit_jump_insn (gen_simple_return_internal (ra)); 4249 } 4250 4251 /* Implement EPILOGUE_USES. */ 4252 4253 bool 4254 riscv_epilogue_uses (unsigned int regno) 4255 { 4256 if (regno == RETURN_ADDR_REGNUM) 4257 return true; 4258 4259 if (epilogue_completed && cfun->machine->interrupt_handler_p) 4260 { 4261 /* An interrupt function restores temp regs, so we must indicate that 4262 they are live at function end. */ 4263 if (df_regs_ever_live_p (regno) 4264 || (!crtl->is_leaf && call_used_or_fixed_reg_p (regno))) 4265 return true; 4266 } 4267 4268 return false; 4269 } 4270 4271 /* Return nonzero if this function is known to have a null epilogue. 4272 This allows the optimizer to omit jumps to jumps if no stack 4273 was created. */ 4274 4275 bool 4276 riscv_can_use_return_insn (void) 4277 { 4278 return (reload_completed && cfun->machine->frame.total_size == 0 4279 && ! cfun->machine->interrupt_handler_p); 4280 } 4281 4282 /* Given that there exists at least one variable that is set (produced) 4283 by OUT_INSN and read (consumed) by IN_INSN, return true iff 4284 IN_INSN represents one or more memory store operations and none of 4285 the variables set by OUT_INSN is used by IN_INSN as the address of a 4286 store operation. If either IN_INSN or OUT_INSN does not represent 4287 a "single" RTL SET expression (as loosely defined by the 4288 implementation of the single_set function) or a PARALLEL with only 4289 SETs, CLOBBERs, and USEs inside, this function returns false. 4290 4291 Borrowed from rs6000, riscv_store_data_bypass_p checks for certain 4292 conditions that result in assertion failures in the generic 4293 store_data_bypass_p function and returns FALSE in such cases. 4294 4295 This is required to make -msave-restore work with the sifive-7 4296 pipeline description. */ 4297 4298 bool 4299 riscv_store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) 4300 { 4301 rtx out_set, in_set; 4302 rtx out_pat, in_pat; 4303 rtx out_exp, in_exp; 4304 int i, j; 4305 4306 in_set = single_set (in_insn); 4307 if (in_set) 4308 { 4309 if (MEM_P (SET_DEST (in_set))) 4310 { 4311 out_set = single_set (out_insn); 4312 if (!out_set) 4313 { 4314 out_pat = PATTERN (out_insn); 4315 if (GET_CODE (out_pat) == PARALLEL) 4316 { 4317 for (i = 0; i < XVECLEN (out_pat, 0); i++) 4318 { 4319 out_exp = XVECEXP (out_pat, 0, i); 4320 if ((GET_CODE (out_exp) == CLOBBER) 4321 || (GET_CODE (out_exp) == USE)) 4322 continue; 4323 else if (GET_CODE (out_exp) != SET) 4324 return false; 4325 } 4326 } 4327 } 4328 } 4329 } 4330 else 4331 { 4332 in_pat = PATTERN (in_insn); 4333 if (GET_CODE (in_pat) != PARALLEL) 4334 return false; 4335 4336 for (i = 0; i < XVECLEN (in_pat, 0); i++) 4337 { 4338 in_exp = XVECEXP (in_pat, 0, i); 4339 if ((GET_CODE (in_exp) == CLOBBER) || (GET_CODE (in_exp) == USE)) 4340 continue; 4341 else if (GET_CODE (in_exp) != SET) 4342 return false; 4343 4344 if (MEM_P (SET_DEST (in_exp))) 4345 { 4346 out_set = single_set (out_insn); 4347 if (!out_set) 4348 { 4349 out_pat = PATTERN (out_insn); 4350 if (GET_CODE (out_pat) != PARALLEL) 4351 return false; 4352 for (j = 0; j < XVECLEN (out_pat, 0); j++) 4353 { 4354 out_exp = XVECEXP (out_pat, 0, j); 4355 if ((GET_CODE (out_exp) == CLOBBER) 4356 || (GET_CODE (out_exp) == USE)) 4357 continue; 4358 else if (GET_CODE (out_exp) != SET) 4359 return false; 4360 } 4361 } 4362 } 4363 } 4364 } 4365 4366 return store_data_bypass_p (out_insn, in_insn); 4367 } 4368 4369 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. 4370 4371 When floating-point registers are wider than integer ones, moves between 4372 them must go through memory. */ 4373 4374 static bool 4375 riscv_secondary_memory_needed (machine_mode mode, reg_class_t class1, 4376 reg_class_t class2) 4377 { 4378 return (GET_MODE_SIZE (mode) > UNITS_PER_WORD 4379 && (class1 == FP_REGS) != (class2 == FP_REGS)); 4380 } 4381 4382 /* Implement TARGET_REGISTER_MOVE_COST. */ 4383 4384 static int 4385 riscv_register_move_cost (machine_mode mode, 4386 reg_class_t from, reg_class_t to) 4387 { 4388 return riscv_secondary_memory_needed (mode, from, to) ? 8 : 2; 4389 } 4390 4391 /* Implement TARGET_HARD_REGNO_NREGS. */ 4392 4393 static unsigned int 4394 riscv_hard_regno_nregs (unsigned int regno, machine_mode mode) 4395 { 4396 if (FP_REG_P (regno)) 4397 return (GET_MODE_SIZE (mode) + UNITS_PER_FP_REG - 1) / UNITS_PER_FP_REG; 4398 4399 /* All other registers are word-sized. */ 4400 return (GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD; 4401 } 4402 4403 /* Implement TARGET_HARD_REGNO_MODE_OK. */ 4404 4405 static bool 4406 riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 4407 { 4408 unsigned int nregs = riscv_hard_regno_nregs (regno, mode); 4409 4410 if (GP_REG_P (regno)) 4411 { 4412 if (!GP_REG_P (regno + nregs - 1)) 4413 return false; 4414 } 4415 else if (FP_REG_P (regno)) 4416 { 4417 if (!FP_REG_P (regno + nregs - 1)) 4418 return false; 4419 4420 if (GET_MODE_CLASS (mode) != MODE_FLOAT 4421 && GET_MODE_CLASS (mode) != MODE_COMPLEX_FLOAT) 4422 return false; 4423 4424 /* Only use callee-saved registers if a potential callee is guaranteed 4425 to spill the requisite width. */ 4426 if (GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_REG 4427 || (!call_used_or_fixed_reg_p (regno) 4428 && GET_MODE_UNIT_SIZE (mode) > UNITS_PER_FP_ARG)) 4429 return false; 4430 } 4431 else 4432 return false; 4433 4434 /* Require same callee-savedness for all registers. */ 4435 for (unsigned i = 1; i < nregs; i++) 4436 if (call_used_or_fixed_reg_p (regno) 4437 != call_used_or_fixed_reg_p (regno + i)) 4438 return false; 4439 4440 return true; 4441 } 4442 4443 /* Implement TARGET_MODES_TIEABLE_P. 4444 4445 Don't allow floating-point modes to be tied, since type punning of 4446 single-precision and double-precision is implementation defined. */ 4447 4448 static bool 4449 riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) 4450 { 4451 return (mode1 == mode2 4452 || !(GET_MODE_CLASS (mode1) == MODE_FLOAT 4453 && GET_MODE_CLASS (mode2) == MODE_FLOAT)); 4454 } 4455 4456 /* Implement CLASS_MAX_NREGS. */ 4457 4458 static unsigned char 4459 riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) 4460 { 4461 if (reg_class_subset_p (FP_REGS, rclass)) 4462 return riscv_hard_regno_nregs (FP_REG_FIRST, mode); 4463 4464 if (reg_class_subset_p (GR_REGS, rclass)) 4465 return riscv_hard_regno_nregs (GP_REG_FIRST, mode); 4466 4467 return 0; 4468 } 4469 4470 /* Implement TARGET_MEMORY_MOVE_COST. */ 4471 4472 static int 4473 riscv_memory_move_cost (machine_mode mode, reg_class_t rclass, bool in) 4474 { 4475 return (tune_info->memory_cost 4476 + memory_move_secondary_cost (mode, rclass, in)); 4477 } 4478 4479 /* Return the number of instructions that can be issued per cycle. */ 4480 4481 static int 4482 riscv_issue_rate (void) 4483 { 4484 return tune_info->issue_rate; 4485 } 4486 4487 /* Auxiliary function to emit RISC-V ELF attribute. */ 4488 static void 4489 riscv_emit_attribute () 4490 { 4491 fprintf (asm_out_file, "\t.attribute arch, \"%s\"\n", 4492 riscv_arch_str ().c_str ()); 4493 4494 fprintf (asm_out_file, "\t.attribute unaligned_access, %d\n", 4495 TARGET_STRICT_ALIGN ? 0 : 1); 4496 4497 fprintf (asm_out_file, "\t.attribute stack_align, %d\n", 4498 riscv_stack_boundary / 8); 4499 } 4500 4501 /* Implement TARGET_ASM_FILE_START. */ 4502 4503 static void 4504 riscv_file_start (void) 4505 { 4506 default_file_start (); 4507 4508 /* Instruct GAS to generate position-[in]dependent code. */ 4509 fprintf (asm_out_file, "\t.option %spic\n", (flag_pic ? "" : "no")); 4510 4511 /* If the user specifies "-mno-relax" on the command line then disable linker 4512 relaxation in the assembler. */ 4513 if (! riscv_mrelax) 4514 fprintf (asm_out_file, "\t.option norelax\n"); 4515 4516 if (riscv_emit_attribute_p) 4517 riscv_emit_attribute (); 4518 } 4519 4520 /* Implement TARGET_ASM_OUTPUT_MI_THUNK. Generate rtl rather than asm text 4521 in order to avoid duplicating too much logic from elsewhere. */ 4522 4523 static void 4524 riscv_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED, 4525 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 4526 tree function) 4527 { 4528 const char *fnname = IDENTIFIER_POINTER (DECL_ASSEMBLER_NAME (thunk_fndecl)); 4529 rtx this_rtx, temp1, temp2, fnaddr; 4530 rtx_insn *insn; 4531 4532 /* Pretend to be a post-reload pass while generating rtl. */ 4533 reload_completed = 1; 4534 4535 /* Mark the end of the (empty) prologue. */ 4536 emit_note (NOTE_INSN_PROLOGUE_END); 4537 4538 /* Determine if we can use a sibcall to call FUNCTION directly. */ 4539 fnaddr = gen_rtx_MEM (FUNCTION_MODE, XEXP (DECL_RTL (function), 0)); 4540 4541 /* We need two temporary registers in some cases. */ 4542 temp1 = gen_rtx_REG (Pmode, RISCV_PROLOGUE_TEMP_REGNUM); 4543 temp2 = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); 4544 4545 /* Find out which register contains the "this" pointer. */ 4546 if (aggregate_value_p (TREE_TYPE (TREE_TYPE (function)), function)) 4547 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST + 1); 4548 else 4549 this_rtx = gen_rtx_REG (Pmode, GP_ARG_FIRST); 4550 4551 /* Add DELTA to THIS_RTX. */ 4552 if (delta != 0) 4553 { 4554 rtx offset = GEN_INT (delta); 4555 if (!SMALL_OPERAND (delta)) 4556 { 4557 riscv_emit_move (temp1, offset); 4558 offset = temp1; 4559 } 4560 emit_insn (gen_add3_insn (this_rtx, this_rtx, offset)); 4561 } 4562 4563 /* If needed, add *(*THIS_RTX + VCALL_OFFSET) to THIS_RTX. */ 4564 if (vcall_offset != 0) 4565 { 4566 rtx addr; 4567 4568 /* Set TEMP1 to *THIS_RTX. */ 4569 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, this_rtx)); 4570 4571 /* Set ADDR to a legitimate address for *THIS_RTX + VCALL_OFFSET. */ 4572 addr = riscv_add_offset (temp2, temp1, vcall_offset); 4573 4574 /* Load the offset and add it to THIS_RTX. */ 4575 riscv_emit_move (temp1, gen_rtx_MEM (Pmode, addr)); 4576 emit_insn (gen_add3_insn (this_rtx, this_rtx, temp1)); 4577 } 4578 4579 /* Jump to the target function. */ 4580 insn = emit_call_insn (gen_sibcall (fnaddr, const0_rtx, NULL, const0_rtx)); 4581 SIBLING_CALL_P (insn) = 1; 4582 4583 /* Run just enough of rest_of_compilation. This sequence was 4584 "borrowed" from alpha.c. */ 4585 insn = get_insns (); 4586 split_all_insns_noflow (); 4587 shorten_branches (insn); 4588 assemble_start_function (thunk_fndecl, fnname); 4589 final_start_function (insn, file, 1); 4590 final (insn, file, 1); 4591 final_end_function (); 4592 assemble_end_function (thunk_fndecl, fnname); 4593 4594 /* Clean up the vars set above. Note that final_end_function resets 4595 the global pointer for us. */ 4596 reload_completed = 0; 4597 } 4598 4599 /* Allocate a chunk of memory for per-function machine-dependent data. */ 4600 4601 static struct machine_function * 4602 riscv_init_machine_status (void) 4603 { 4604 return ggc_cleared_alloc<machine_function> (); 4605 } 4606 4607 /* Implement TARGET_OPTION_OVERRIDE. */ 4608 4609 static void 4610 riscv_option_override (void) 4611 { 4612 const struct riscv_cpu_info *cpu; 4613 4614 #ifdef SUBTARGET_OVERRIDE_OPTIONS 4615 SUBTARGET_OVERRIDE_OPTIONS; 4616 #endif 4617 4618 flag_pcc_struct_return = 0; 4619 4620 if (flag_pic) 4621 g_switch_value = 0; 4622 4623 /* The presence of the M extension implies that division instructions 4624 are present, so include them unless explicitly disabled. */ 4625 if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) 4626 target_flags |= MASK_DIV; 4627 else if (!TARGET_MUL && TARGET_DIV) 4628 error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension"); 4629 4630 /* Likewise floating-point division and square root. */ 4631 if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0) 4632 target_flags |= MASK_FDIV; 4633 4634 /* Handle -mtune. */ 4635 cpu = riscv_parse_cpu (riscv_tune_string ? riscv_tune_string : 4636 RISCV_TUNE_STRING_DEFAULT); 4637 riscv_microarchitecture = cpu->microarchitecture; 4638 tune_info = optimize_size ? &optimize_size_tune_info : cpu->tune_info; 4639 4640 /* Use -mtune's setting for slow_unaligned_access, even when optimizing 4641 for size. For architectures that trap and emulate unaligned accesses, 4642 the performance cost is too great, even for -Os. Similarly, if 4643 -m[no-]strict-align is left unspecified, heed -mtune's advice. */ 4644 riscv_slow_unaligned_access_p = (cpu->tune_info->slow_unaligned_access 4645 || TARGET_STRICT_ALIGN); 4646 if ((target_flags_explicit & MASK_STRICT_ALIGN) == 0 4647 && cpu->tune_info->slow_unaligned_access) 4648 target_flags |= MASK_STRICT_ALIGN; 4649 4650 /* If the user hasn't specified a branch cost, use the processor's 4651 default. */ 4652 if (riscv_branch_cost == 0) 4653 riscv_branch_cost = tune_info->branch_cost; 4654 4655 /* Function to allocate machine-dependent function status. */ 4656 init_machine_status = &riscv_init_machine_status; 4657 4658 if (flag_pic) 4659 riscv_cmodel = CM_PIC; 4660 4661 /* We get better code with explicit relocs for CM_MEDLOW, but 4662 worse code for the others (for now). Pick the best default. */ 4663 if ((target_flags_explicit & MASK_EXPLICIT_RELOCS) == 0) 4664 if (riscv_cmodel == CM_MEDLOW) 4665 target_flags |= MASK_EXPLICIT_RELOCS; 4666 4667 /* Require that the ISA supports the requested floating-point ABI. */ 4668 if (UNITS_PER_FP_ARG > (TARGET_HARD_FLOAT ? UNITS_PER_FP_REG : 0)) 4669 error ("requested ABI requires %<-march%> to subsume the %qc extension", 4670 UNITS_PER_FP_ARG > 8 ? 'Q' : (UNITS_PER_FP_ARG > 4 ? 'D' : 'F')); 4671 4672 if (TARGET_RVE && riscv_abi != ABI_ILP32E) 4673 error ("rv32e requires ilp32e ABI"); 4674 4675 /* We do not yet support ILP32 on RV64. */ 4676 if (BITS_PER_WORD != POINTER_SIZE) 4677 error ("ABI requires %<-march=rv%d%>", POINTER_SIZE); 4678 4679 /* Validate -mpreferred-stack-boundary= value. */ 4680 riscv_stack_boundary = ABI_STACK_BOUNDARY; 4681 if (riscv_preferred_stack_boundary_arg) 4682 { 4683 int min = ctz_hwi (STACK_BOUNDARY / 8); 4684 int max = 8; 4685 4686 if (!IN_RANGE (riscv_preferred_stack_boundary_arg, min, max)) 4687 error ("%<-mpreferred-stack-boundary=%d%> must be between %d and %d", 4688 riscv_preferred_stack_boundary_arg, min, max); 4689 4690 riscv_stack_boundary = 8 << riscv_preferred_stack_boundary_arg; 4691 } 4692 4693 if (riscv_emit_attribute_p < 0) 4694 #ifdef HAVE_AS_RISCV_ATTRIBUTE 4695 riscv_emit_attribute_p = TARGET_RISCV_ATTRIBUTE; 4696 #else 4697 riscv_emit_attribute_p = 0; 4698 4699 if (riscv_emit_attribute_p) 4700 error ("%<-mriscv-attribute%> RISC-V ELF attribute requires GNU as 2.32" 4701 " [%<-mriscv-attribute%>]"); 4702 #endif 4703 } 4704 4705 /* Implement TARGET_CONDITIONAL_REGISTER_USAGE. */ 4706 4707 static void 4708 riscv_conditional_register_usage (void) 4709 { 4710 /* We have only x0~x15 on RV32E. */ 4711 if (TARGET_RVE) 4712 { 4713 for (int r = 16; r <= 31; r++) 4714 fixed_regs[r] = 1; 4715 } 4716 4717 if (riscv_abi == ABI_ILP32E) 4718 { 4719 for (int r = 16; r <= 31; r++) 4720 call_used_regs[r] = 1; 4721 } 4722 4723 if (!TARGET_HARD_FLOAT) 4724 { 4725 for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 4726 fixed_regs[regno] = call_used_regs[regno] = 1; 4727 } 4728 4729 /* In the soft-float ABI, there are no callee-saved FP registers. */ 4730 if (UNITS_PER_FP_ARG == 0) 4731 { 4732 for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) 4733 call_used_regs[regno] = 1; 4734 } 4735 } 4736 4737 /* Return a register priority for hard reg REGNO. */ 4738 4739 static int 4740 riscv_register_priority (int regno) 4741 { 4742 /* Favor x8-x15/f8-f15 to improve the odds of RVC instruction selection. */ 4743 if (TARGET_RVC && (IN_RANGE (regno, GP_REG_FIRST + 8, GP_REG_FIRST + 15) 4744 || IN_RANGE (regno, FP_REG_FIRST + 8, FP_REG_FIRST + 15))) 4745 return 1; 4746 4747 return 0; 4748 } 4749 4750 /* Implement TARGET_TRAMPOLINE_INIT. */ 4751 4752 static void 4753 riscv_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 4754 { 4755 rtx addr, end_addr, mem; 4756 uint32_t trampoline[4]; 4757 unsigned int i; 4758 HOST_WIDE_INT static_chain_offset, target_function_offset; 4759 4760 /* Work out the offsets of the pointers from the start of the 4761 trampoline code. */ 4762 gcc_assert (ARRAY_SIZE (trampoline) * 4 == TRAMPOLINE_CODE_SIZE); 4763 4764 /* Get pointers to the beginning and end of the code block. */ 4765 addr = force_reg (Pmode, XEXP (m_tramp, 0)); 4766 end_addr = riscv_force_binary (Pmode, PLUS, addr, 4767 GEN_INT (TRAMPOLINE_CODE_SIZE)); 4768 4769 4770 if (Pmode == SImode) 4771 { 4772 chain_value = force_reg (Pmode, chain_value); 4773 4774 rtx target_function = force_reg (Pmode, XEXP (DECL_RTL (fndecl), 0)); 4775 /* lui t2, hi(chain) 4776 lui t0, hi(func) 4777 addi t2, t2, lo(chain) 4778 jr t0, lo(func) 4779 */ 4780 unsigned HOST_WIDE_INT lui_hi_chain_code, lui_hi_func_code; 4781 unsigned HOST_WIDE_INT lo_chain_code, lo_func_code; 4782 4783 rtx uimm_mask = force_reg (SImode, gen_int_mode (-IMM_REACH, SImode)); 4784 4785 /* 0xfff. */ 4786 rtx imm12_mask = gen_reg_rtx (SImode); 4787 emit_insn (gen_one_cmplsi2 (imm12_mask, uimm_mask)); 4788 4789 rtx fixup_value = force_reg (SImode, gen_int_mode (IMM_REACH/2, SImode)); 4790 4791 /* Gen lui t2, hi(chain). */ 4792 rtx hi_chain = riscv_force_binary (SImode, PLUS, chain_value, 4793 fixup_value); 4794 hi_chain = riscv_force_binary (SImode, AND, hi_chain, 4795 uimm_mask); 4796 lui_hi_chain_code = OPCODE_LUI | (STATIC_CHAIN_REGNUM << SHIFT_RD); 4797 rtx lui_hi_chain = riscv_force_binary (SImode, IOR, hi_chain, 4798 gen_int_mode (lui_hi_chain_code, SImode)); 4799 4800 mem = adjust_address (m_tramp, SImode, 0); 4801 riscv_emit_move (mem, lui_hi_chain); 4802 4803 /* Gen lui t0, hi(func). */ 4804 rtx hi_func = riscv_force_binary (SImode, PLUS, target_function, 4805 fixup_value); 4806 hi_func = riscv_force_binary (SImode, AND, hi_func, 4807 uimm_mask); 4808 lui_hi_func_code = OPCODE_LUI | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD); 4809 rtx lui_hi_func = riscv_force_binary (SImode, IOR, hi_func, 4810 gen_int_mode (lui_hi_func_code, SImode)); 4811 4812 mem = adjust_address (m_tramp, SImode, 1 * GET_MODE_SIZE (SImode)); 4813 riscv_emit_move (mem, lui_hi_func); 4814 4815 /* Gen addi t2, t2, lo(chain). */ 4816 rtx lo_chain = riscv_force_binary (SImode, AND, chain_value, 4817 imm12_mask); 4818 lo_chain = riscv_force_binary (SImode, ASHIFT, lo_chain, GEN_INT (20)); 4819 4820 lo_chain_code = OPCODE_ADDI 4821 | (STATIC_CHAIN_REGNUM << SHIFT_RD) 4822 | (STATIC_CHAIN_REGNUM << SHIFT_RS1); 4823 4824 rtx addi_lo_chain = riscv_force_binary (SImode, IOR, lo_chain, 4825 force_reg (SImode, GEN_INT (lo_chain_code))); 4826 4827 mem = adjust_address (m_tramp, SImode, 2 * GET_MODE_SIZE (SImode)); 4828 riscv_emit_move (mem, addi_lo_chain); 4829 4830 /* Gen jr t0, lo(func). */ 4831 rtx lo_func = riscv_force_binary (SImode, AND, target_function, 4832 imm12_mask); 4833 lo_func = riscv_force_binary (SImode, ASHIFT, lo_func, GEN_INT (20)); 4834 4835 lo_func_code = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1); 4836 4837 rtx jr_lo_func = riscv_force_binary (SImode, IOR, lo_func, 4838 force_reg (SImode, GEN_INT (lo_func_code))); 4839 4840 mem = adjust_address (m_tramp, SImode, 3 * GET_MODE_SIZE (SImode)); 4841 riscv_emit_move (mem, jr_lo_func); 4842 } 4843 else 4844 { 4845 static_chain_offset = TRAMPOLINE_CODE_SIZE; 4846 target_function_offset = static_chain_offset + GET_MODE_SIZE (ptr_mode); 4847 4848 /* auipc t2, 0 4849 l[wd] t0, target_function_offset(t2) 4850 l[wd] t2, static_chain_offset(t2) 4851 jr t0 4852 */ 4853 trampoline[0] = OPCODE_AUIPC | (STATIC_CHAIN_REGNUM << SHIFT_RD); 4854 trampoline[1] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) 4855 | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RD) 4856 | (STATIC_CHAIN_REGNUM << SHIFT_RS1) 4857 | (target_function_offset << SHIFT_IMM); 4858 trampoline[2] = (Pmode == DImode ? OPCODE_LD : OPCODE_LW) 4859 | (STATIC_CHAIN_REGNUM << SHIFT_RD) 4860 | (STATIC_CHAIN_REGNUM << SHIFT_RS1) 4861 | (static_chain_offset << SHIFT_IMM); 4862 trampoline[3] = OPCODE_JALR | (RISCV_PROLOGUE_TEMP_REGNUM << SHIFT_RS1); 4863 4864 /* Copy the trampoline code. */ 4865 for (i = 0; i < ARRAY_SIZE (trampoline); i++) 4866 { 4867 mem = adjust_address (m_tramp, SImode, i * GET_MODE_SIZE (SImode)); 4868 riscv_emit_move (mem, gen_int_mode (trampoline[i], SImode)); 4869 } 4870 4871 /* Set up the static chain pointer field. */ 4872 mem = adjust_address (m_tramp, ptr_mode, static_chain_offset); 4873 riscv_emit_move (mem, chain_value); 4874 4875 /* Set up the target function field. */ 4876 mem = adjust_address (m_tramp, ptr_mode, target_function_offset); 4877 riscv_emit_move (mem, XEXP (DECL_RTL (fndecl), 0)); 4878 } 4879 4880 /* Flush the code part of the trampoline. */ 4881 emit_insn (gen_add3_insn (end_addr, addr, GEN_INT (TRAMPOLINE_SIZE))); 4882 emit_insn (gen_clear_cache (addr, end_addr)); 4883 } 4884 4885 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL. */ 4886 4887 static bool 4888 riscv_function_ok_for_sibcall (tree decl ATTRIBUTE_UNUSED, 4889 tree exp ATTRIBUTE_UNUSED) 4890 { 4891 /* Don't use sibcalls when use save-restore routine. */ 4892 if (TARGET_SAVE_RESTORE) 4893 return false; 4894 4895 /* Don't use sibcall for naked functions. */ 4896 if (cfun->machine->naked_p) 4897 return false; 4898 4899 /* Don't use sibcall for interrupt functions. */ 4900 if (cfun->machine->interrupt_handler_p) 4901 return false; 4902 4903 return true; 4904 } 4905 4906 /* Get the interrupt type, return UNKNOWN_MODE if it's not 4907 interrupt function. */ 4908 static enum riscv_privilege_levels 4909 riscv_get_interrupt_type (tree decl) 4910 { 4911 gcc_assert (decl != NULL_TREE); 4912 4913 if ((TREE_CODE(decl) != FUNCTION_DECL) 4914 || (!riscv_interrupt_type_p (TREE_TYPE (decl)))) 4915 return UNKNOWN_MODE; 4916 4917 tree attr_args 4918 = TREE_VALUE (lookup_attribute ("interrupt", 4919 TYPE_ATTRIBUTES (TREE_TYPE (decl)))); 4920 4921 if (attr_args && TREE_CODE (TREE_VALUE (attr_args)) != VOID_TYPE) 4922 { 4923 const char *string = TREE_STRING_POINTER (TREE_VALUE (attr_args)); 4924 4925 if (!strcmp (string, "user")) 4926 return USER_MODE; 4927 else if (!strcmp (string, "supervisor")) 4928 return SUPERVISOR_MODE; 4929 else /* Must be "machine". */ 4930 return MACHINE_MODE; 4931 } 4932 else 4933 /* Interrupt attributes are machine mode by default. */ 4934 return MACHINE_MODE; 4935 } 4936 4937 /* Implement `TARGET_SET_CURRENT_FUNCTION'. */ 4938 /* Sanity cheching for above function attributes. */ 4939 static void 4940 riscv_set_current_function (tree decl) 4941 { 4942 if (decl == NULL_TREE 4943 || current_function_decl == NULL_TREE 4944 || current_function_decl == error_mark_node 4945 || ! cfun->machine 4946 || cfun->machine->attributes_checked_p) 4947 return; 4948 4949 cfun->machine->naked_p = riscv_naked_function_p (decl); 4950 cfun->machine->interrupt_handler_p 4951 = riscv_interrupt_type_p (TREE_TYPE (decl)); 4952 4953 if (cfun->machine->naked_p && cfun->machine->interrupt_handler_p) 4954 error ("function attributes %qs and %qs are mutually exclusive", 4955 "interrupt", "naked"); 4956 4957 if (cfun->machine->interrupt_handler_p) 4958 { 4959 tree ret = TREE_TYPE (TREE_TYPE (decl)); 4960 tree args = TYPE_ARG_TYPES (TREE_TYPE (decl)); 4961 4962 if (TREE_CODE (ret) != VOID_TYPE) 4963 error ("%qs function cannot return a value", "interrupt"); 4964 4965 if (args && TREE_CODE (TREE_VALUE (args)) != VOID_TYPE) 4966 error ("%qs function cannot have arguments", "interrupt"); 4967 4968 cfun->machine->interrupt_mode = riscv_get_interrupt_type (decl); 4969 4970 gcc_assert (cfun->machine->interrupt_mode != UNKNOWN_MODE); 4971 } 4972 4973 /* Don't print the above diagnostics more than once. */ 4974 cfun->machine->attributes_checked_p = 1; 4975 } 4976 4977 /* Implement TARGET_MERGE_DECL_ATTRIBUTES. */ 4978 static tree 4979 riscv_merge_decl_attributes (tree olddecl, tree newdecl) 4980 { 4981 tree combined_attrs; 4982 4983 enum riscv_privilege_levels old_interrupt_type 4984 = riscv_get_interrupt_type (olddecl); 4985 enum riscv_privilege_levels new_interrupt_type 4986 = riscv_get_interrupt_type (newdecl); 4987 4988 /* Check old and new has same interrupt type. */ 4989 if ((old_interrupt_type != UNKNOWN_MODE) 4990 && (new_interrupt_type != UNKNOWN_MODE) 4991 && (old_interrupt_type != new_interrupt_type)) 4992 error ("%qs function cannot have different interrupt type", "interrupt"); 4993 4994 /* Create combined attributes. */ 4995 combined_attrs = merge_attributes (DECL_ATTRIBUTES (olddecl), 4996 DECL_ATTRIBUTES (newdecl)); 4997 4998 return combined_attrs; 4999 } 5000 5001 /* Implement TARGET_CANNOT_COPY_INSN_P. */ 5002 5003 static bool 5004 riscv_cannot_copy_insn_p (rtx_insn *insn) 5005 { 5006 return recog_memoized (insn) >= 0 && get_attr_cannot_copy (insn); 5007 } 5008 5009 /* Implement TARGET_SLOW_UNALIGNED_ACCESS. */ 5010 5011 static bool 5012 riscv_slow_unaligned_access (machine_mode, unsigned int) 5013 { 5014 return riscv_slow_unaligned_access_p; 5015 } 5016 5017 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */ 5018 5019 static bool 5020 riscv_can_change_mode_class (machine_mode, machine_mode, reg_class_t rclass) 5021 { 5022 return !reg_classes_intersect_p (FP_REGS, rclass); 5023 } 5024 5025 5026 /* Implement TARGET_CONSTANT_ALIGNMENT. */ 5027 5028 static HOST_WIDE_INT 5029 riscv_constant_alignment (const_tree exp, HOST_WIDE_INT align) 5030 { 5031 if ((TREE_CODE (exp) == STRING_CST || TREE_CODE (exp) == CONSTRUCTOR) 5032 && (riscv_align_data_type == riscv_align_data_type_xlen)) 5033 return MAX (align, BITS_PER_WORD); 5034 return align; 5035 } 5036 5037 /* Implement TARGET_PROMOTE_FUNCTION_MODE. */ 5038 5039 /* This function is equivalent to default_promote_function_mode_always_promote 5040 except that it returns a promoted mode even if type is NULL_TREE. This is 5041 needed by libcalls which have no type (only a mode) such as fixed conversion 5042 routines that take a signed or unsigned char/short/int argument and convert 5043 it to a fixed type. */ 5044 5045 static machine_mode 5046 riscv_promote_function_mode (const_tree type ATTRIBUTE_UNUSED, 5047 machine_mode mode, 5048 int *punsignedp ATTRIBUTE_UNUSED, 5049 const_tree fntype ATTRIBUTE_UNUSED, 5050 int for_return ATTRIBUTE_UNUSED) 5051 { 5052 int unsignedp; 5053 5054 if (type != NULL_TREE) 5055 return promote_mode (type, mode, punsignedp); 5056 5057 unsignedp = *punsignedp; 5058 PROMOTE_MODE (mode, unsignedp, type); 5059 *punsignedp = unsignedp; 5060 return mode; 5061 } 5062 5063 /* Implement TARGET_MACHINE_DEPENDENT_REORG. */ 5064 5065 static void 5066 riscv_reorg (void) 5067 { 5068 /* Do nothing unless we have -msave-restore */ 5069 if (TARGET_SAVE_RESTORE) 5070 riscv_remove_unneeded_save_restore_calls (); 5071 } 5072 5073 /* Return nonzero if register FROM_REGNO can be renamed to register 5074 TO_REGNO. */ 5075 5076 bool 5077 riscv_hard_regno_rename_ok (unsigned from_regno ATTRIBUTE_UNUSED, 5078 unsigned to_regno) 5079 { 5080 /* Interrupt functions can only use registers that have already been 5081 saved by the prologue, even if they would normally be 5082 call-clobbered. */ 5083 return !cfun->machine->interrupt_handler_p || df_regs_ever_live_p (to_regno); 5084 } 5085 5086 5087 /* Helper function for generating gpr_save pattern. */ 5088 5089 rtx 5090 riscv_gen_gpr_save_insn (struct riscv_frame_info *frame) 5091 { 5092 unsigned count = riscv_save_libcall_count (frame->mask); 5093 /* 1 for unspec 2 for clobber t0/t1 and 1 for ra. */ 5094 unsigned veclen = 1 + 2 + 1 + count; 5095 rtvec vec = rtvec_alloc (veclen); 5096 5097 gcc_assert (veclen <= ARRAY_SIZE (gpr_save_reg_order)); 5098 5099 RTVEC_ELT (vec, 0) = 5100 gen_rtx_UNSPEC_VOLATILE (VOIDmode, 5101 gen_rtvec (1, GEN_INT (count)), UNSPECV_GPR_SAVE); 5102 5103 for (unsigned i = 1; i < veclen; ++i) 5104 { 5105 unsigned regno = gpr_save_reg_order[i]; 5106 rtx reg = gen_rtx_REG (Pmode, regno); 5107 rtx elt; 5108 5109 /* t0 and t1 are CLOBBERs, others are USEs. */ 5110 if (i < 3) 5111 elt = gen_rtx_CLOBBER (Pmode, reg); 5112 else 5113 elt = gen_rtx_USE (Pmode, reg); 5114 5115 RTVEC_ELT (vec, i) = elt; 5116 } 5117 5118 /* Largest number of caller-save register must set in mask if we are 5119 not using __riscv_save_0. */ 5120 gcc_assert ((count == 0) || 5121 BITSET_P (frame->mask, gpr_save_reg_order[veclen - 1])); 5122 5123 return gen_rtx_PARALLEL (VOIDmode, vec); 5124 } 5125 5126 /* Return true if it's valid gpr_save pattern. */ 5127 5128 bool 5129 riscv_gpr_save_operation_p (rtx op) 5130 { 5131 unsigned len = XVECLEN (op, 0); 5132 5133 if (len > ARRAY_SIZE (gpr_save_reg_order)) 5134 return false; 5135 5136 for (unsigned i = 0; i < len; i++) 5137 { 5138 rtx elt = XVECEXP (op, 0, i); 5139 if (i == 0) 5140 { 5141 /* First element in parallel is unspec. */ 5142 if (GET_CODE (elt) != UNSPEC_VOLATILE 5143 || GET_CODE (XVECEXP (elt, 0, 0)) != CONST_INT 5144 || XINT (elt, 1) != UNSPECV_GPR_SAVE) 5145 return false; 5146 } 5147 else 5148 { 5149 /* Two CLOBBER and USEs, must check the order. */ 5150 unsigned expect_code = i < 3 ? CLOBBER : USE; 5151 if (GET_CODE (elt) != expect_code 5152 || !REG_P (XEXP (elt, 1)) 5153 || (REGNO (XEXP (elt, 1)) != gpr_save_reg_order[i])) 5154 return false; 5155 } 5156 break; 5157 } 5158 return true; 5159 } 5160 5161 /* Initialize the GCC target structure. */ 5162 #undef TARGET_ASM_ALIGNED_HI_OP 5163 #define TARGET_ASM_ALIGNED_HI_OP "\t.half\t" 5164 #undef TARGET_ASM_ALIGNED_SI_OP 5165 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 5166 #undef TARGET_ASM_ALIGNED_DI_OP 5167 #define TARGET_ASM_ALIGNED_DI_OP "\t.dword\t" 5168 5169 #undef TARGET_OPTION_OVERRIDE 5170 #define TARGET_OPTION_OVERRIDE riscv_option_override 5171 5172 #undef TARGET_LEGITIMIZE_ADDRESS 5173 #define TARGET_LEGITIMIZE_ADDRESS riscv_legitimize_address 5174 5175 #undef TARGET_SCHED_ISSUE_RATE 5176 #define TARGET_SCHED_ISSUE_RATE riscv_issue_rate 5177 5178 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 5179 #define TARGET_FUNCTION_OK_FOR_SIBCALL riscv_function_ok_for_sibcall 5180 5181 #undef TARGET_SET_CURRENT_FUNCTION 5182 #define TARGET_SET_CURRENT_FUNCTION riscv_set_current_function 5183 5184 #undef TARGET_REGISTER_MOVE_COST 5185 #define TARGET_REGISTER_MOVE_COST riscv_register_move_cost 5186 #undef TARGET_MEMORY_MOVE_COST 5187 #define TARGET_MEMORY_MOVE_COST riscv_memory_move_cost 5188 #undef TARGET_RTX_COSTS 5189 #define TARGET_RTX_COSTS riscv_rtx_costs 5190 #undef TARGET_ADDRESS_COST 5191 #define TARGET_ADDRESS_COST riscv_address_cost 5192 5193 #undef TARGET_ASM_FILE_START 5194 #define TARGET_ASM_FILE_START riscv_file_start 5195 #undef TARGET_ASM_FILE_START_FILE_DIRECTIVE 5196 #define TARGET_ASM_FILE_START_FILE_DIRECTIVE true 5197 5198 #undef TARGET_EXPAND_BUILTIN_VA_START 5199 #define TARGET_EXPAND_BUILTIN_VA_START riscv_va_start 5200 5201 #undef TARGET_PROMOTE_FUNCTION_MODE 5202 #define TARGET_PROMOTE_FUNCTION_MODE riscv_promote_function_mode 5203 5204 #undef TARGET_RETURN_IN_MEMORY 5205 #define TARGET_RETURN_IN_MEMORY riscv_return_in_memory 5206 5207 #undef TARGET_ASM_OUTPUT_MI_THUNK 5208 #define TARGET_ASM_OUTPUT_MI_THUNK riscv_output_mi_thunk 5209 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 5210 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true 5211 5212 #undef TARGET_PRINT_OPERAND 5213 #define TARGET_PRINT_OPERAND riscv_print_operand 5214 #undef TARGET_PRINT_OPERAND_ADDRESS 5215 #define TARGET_PRINT_OPERAND_ADDRESS riscv_print_operand_address 5216 5217 #undef TARGET_SETUP_INCOMING_VARARGS 5218 #define TARGET_SETUP_INCOMING_VARARGS riscv_setup_incoming_varargs 5219 #undef TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS 5220 #define TARGET_ALLOCATE_STACK_SLOTS_FOR_ARGS riscv_allocate_stack_slots_for_args 5221 #undef TARGET_STRICT_ARGUMENT_NAMING 5222 #define TARGET_STRICT_ARGUMENT_NAMING hook_bool_CUMULATIVE_ARGS_true 5223 #undef TARGET_MUST_PASS_IN_STACK 5224 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 5225 #undef TARGET_PASS_BY_REFERENCE 5226 #define TARGET_PASS_BY_REFERENCE riscv_pass_by_reference 5227 #undef TARGET_ARG_PARTIAL_BYTES 5228 #define TARGET_ARG_PARTIAL_BYTES riscv_arg_partial_bytes 5229 #undef TARGET_FUNCTION_ARG 5230 #define TARGET_FUNCTION_ARG riscv_function_arg 5231 #undef TARGET_FUNCTION_ARG_ADVANCE 5232 #define TARGET_FUNCTION_ARG_ADVANCE riscv_function_arg_advance 5233 #undef TARGET_FUNCTION_ARG_BOUNDARY 5234 #define TARGET_FUNCTION_ARG_BOUNDARY riscv_function_arg_boundary 5235 5236 /* The generic ELF target does not always have TLS support. */ 5237 #ifdef HAVE_AS_TLS 5238 #undef TARGET_HAVE_TLS 5239 #define TARGET_HAVE_TLS true 5240 #endif 5241 5242 #undef TARGET_CANNOT_FORCE_CONST_MEM 5243 #define TARGET_CANNOT_FORCE_CONST_MEM riscv_cannot_force_const_mem 5244 5245 #undef TARGET_LEGITIMATE_CONSTANT_P 5246 #define TARGET_LEGITIMATE_CONSTANT_P riscv_legitimate_constant_p 5247 5248 #undef TARGET_USE_BLOCKS_FOR_CONSTANT_P 5249 #define TARGET_USE_BLOCKS_FOR_CONSTANT_P hook_bool_mode_const_rtx_true 5250 5251 #undef TARGET_LEGITIMATE_ADDRESS_P 5252 #define TARGET_LEGITIMATE_ADDRESS_P riscv_legitimate_address_p 5253 5254 #undef TARGET_CAN_ELIMINATE 5255 #define TARGET_CAN_ELIMINATE riscv_can_eliminate 5256 5257 #undef TARGET_CONDITIONAL_REGISTER_USAGE 5258 #define TARGET_CONDITIONAL_REGISTER_USAGE riscv_conditional_register_usage 5259 5260 #undef TARGET_CLASS_MAX_NREGS 5261 #define TARGET_CLASS_MAX_NREGS riscv_class_max_nregs 5262 5263 #undef TARGET_TRAMPOLINE_INIT 5264 #define TARGET_TRAMPOLINE_INIT riscv_trampoline_init 5265 5266 #undef TARGET_IN_SMALL_DATA_P 5267 #define TARGET_IN_SMALL_DATA_P riscv_in_small_data_p 5268 5269 #undef TARGET_HAVE_SRODATA_SECTION 5270 #define TARGET_HAVE_SRODATA_SECTION true 5271 5272 #undef TARGET_ASM_SELECT_SECTION 5273 #define TARGET_ASM_SELECT_SECTION riscv_select_section 5274 5275 #undef TARGET_ASM_UNIQUE_SECTION 5276 #define TARGET_ASM_UNIQUE_SECTION riscv_unique_section 5277 5278 #undef TARGET_ASM_SELECT_RTX_SECTION 5279 #define TARGET_ASM_SELECT_RTX_SECTION riscv_elf_select_rtx_section 5280 5281 #undef TARGET_MIN_ANCHOR_OFFSET 5282 #define TARGET_MIN_ANCHOR_OFFSET (-IMM_REACH/2) 5283 5284 #undef TARGET_MAX_ANCHOR_OFFSET 5285 #define TARGET_MAX_ANCHOR_OFFSET (IMM_REACH/2-1) 5286 5287 #undef TARGET_REGISTER_PRIORITY 5288 #define TARGET_REGISTER_PRIORITY riscv_register_priority 5289 5290 #undef TARGET_CANNOT_COPY_INSN_P 5291 #define TARGET_CANNOT_COPY_INSN_P riscv_cannot_copy_insn_p 5292 5293 #undef TARGET_ATOMIC_ASSIGN_EXPAND_FENV 5294 #define TARGET_ATOMIC_ASSIGN_EXPAND_FENV riscv_atomic_assign_expand_fenv 5295 5296 #undef TARGET_INIT_BUILTINS 5297 #define TARGET_INIT_BUILTINS riscv_init_builtins 5298 5299 #undef TARGET_BUILTIN_DECL 5300 #define TARGET_BUILTIN_DECL riscv_builtin_decl 5301 5302 #undef TARGET_EXPAND_BUILTIN 5303 #define TARGET_EXPAND_BUILTIN riscv_expand_builtin 5304 5305 #undef TARGET_HARD_REGNO_NREGS 5306 #define TARGET_HARD_REGNO_NREGS riscv_hard_regno_nregs 5307 #undef TARGET_HARD_REGNO_MODE_OK 5308 #define TARGET_HARD_REGNO_MODE_OK riscv_hard_regno_mode_ok 5309 5310 #undef TARGET_MODES_TIEABLE_P 5311 #define TARGET_MODES_TIEABLE_P riscv_modes_tieable_p 5312 5313 #undef TARGET_SLOW_UNALIGNED_ACCESS 5314 #define TARGET_SLOW_UNALIGNED_ACCESS riscv_slow_unaligned_access 5315 5316 #undef TARGET_SECONDARY_MEMORY_NEEDED 5317 #define TARGET_SECONDARY_MEMORY_NEEDED riscv_secondary_memory_needed 5318 5319 #undef TARGET_CAN_CHANGE_MODE_CLASS 5320 #define TARGET_CAN_CHANGE_MODE_CLASS riscv_can_change_mode_class 5321 5322 #undef TARGET_CONSTANT_ALIGNMENT 5323 #define TARGET_CONSTANT_ALIGNMENT riscv_constant_alignment 5324 5325 #undef TARGET_MERGE_DECL_ATTRIBUTES 5326 #define TARGET_MERGE_DECL_ATTRIBUTES riscv_merge_decl_attributes 5327 5328 #undef TARGET_ATTRIBUTE_TABLE 5329 #define TARGET_ATTRIBUTE_TABLE riscv_attribute_table 5330 5331 #undef TARGET_WARN_FUNC_RETURN 5332 #define TARGET_WARN_FUNC_RETURN riscv_warn_func_return 5333 5334 /* The low bit is ignored by jump instructions so is safe to use. */ 5335 #undef TARGET_CUSTOM_FUNCTION_DESCRIPTORS 5336 #define TARGET_CUSTOM_FUNCTION_DESCRIPTORS 1 5337 5338 #undef TARGET_MACHINE_DEPENDENT_REORG 5339 #define TARGET_MACHINE_DEPENDENT_REORG riscv_reorg 5340 5341 struct gcc_target targetm = TARGET_INITIALIZER; 5342 5343 #include "gt-riscv.h" 5344