1 /* Subroutines for gcc2 for pdp11. 2 Copyright (C) 1994-2018 Free Software Foundation, Inc. 3 Contributed by Michael K. Gschwind (mike@vlsivie.tuwien.ac.at). 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3, or (at your option) 10 any later version. 11 12 GCC is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #define IN_TARGET_CODE 1 22 23 #include "config.h" 24 #include "system.h" 25 #include "coretypes.h" 26 #include "backend.h" 27 #include "target.h" 28 #include "rtl.h" 29 #include "tree.h" 30 #include "stringpool.h" 31 #include "attribs.h" 32 #include "df.h" 33 #include "memmodel.h" 34 #include "tm_p.h" 35 #include "insn-config.h" 36 #include "regs.h" 37 #include "emit-rtl.h" 38 #include "recog.h" 39 #include "conditions.h" 40 #include "output.h" 41 #include "stor-layout.h" 42 #include "varasm.h" 43 #include "calls.h" 44 #include "expr.h" 45 #include "builtins.h" 46 #include "dbxout.h" 47 48 /* This file should be included last. */ 49 #include "target-def.h" 50 51 /* this is the current value returned by the macro FIRST_PARM_OFFSET 52 defined in tm.h */ 53 int current_first_parm_offset; 54 55 /* Routines to encode/decode pdp11 floats */ 56 static void encode_pdp11_f (const struct real_format *fmt, 57 long *, const REAL_VALUE_TYPE *); 58 static void decode_pdp11_f (const struct real_format *, 59 REAL_VALUE_TYPE *, const long *); 60 static void encode_pdp11_d (const struct real_format *fmt, 61 long *, const REAL_VALUE_TYPE *); 62 static void decode_pdp11_d (const struct real_format *, 63 REAL_VALUE_TYPE *, const long *); 64 65 /* These two are taken from the corresponding vax descriptors 66 in real.c, changing only the encode/decode routine pointers. */ 67 const struct real_format pdp11_f_format = 68 { 69 encode_pdp11_f, 70 decode_pdp11_f, 71 2, 72 24, 73 24, 74 -127, 75 127, 76 15, 77 15, 78 0, 79 false, 80 false, 81 false, 82 false, 83 false, 84 false, 85 false, 86 false, 87 "pdp11_f" 88 }; 89 90 const struct real_format pdp11_d_format = 91 { 92 encode_pdp11_d, 93 decode_pdp11_d, 94 2, 95 56, 96 56, 97 -127, 98 127, 99 15, 100 15, 101 0, 102 false, 103 false, 104 false, 105 false, 106 false, 107 false, 108 false, 109 false, 110 "pdp11_d" 111 }; 112 113 static void 114 encode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf, 115 const REAL_VALUE_TYPE *r) 116 { 117 (*vax_f_format.encode) (fmt, buf, r); 118 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); 119 } 120 121 static void 122 decode_pdp11_f (const struct real_format *fmt ATTRIBUTE_UNUSED, 123 REAL_VALUE_TYPE *r, const long *buf) 124 { 125 long tbuf; 126 tbuf = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); 127 (*vax_f_format.decode) (fmt, r, &tbuf); 128 } 129 130 static void 131 encode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, long *buf, 132 const REAL_VALUE_TYPE *r) 133 { 134 (*vax_d_format.encode) (fmt, buf, r); 135 buf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); 136 buf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16); 137 } 138 139 static void 140 decode_pdp11_d (const struct real_format *fmt ATTRIBUTE_UNUSED, 141 REAL_VALUE_TYPE *r, const long *buf) 142 { 143 long tbuf[2]; 144 tbuf[0] = ((buf[0] >> 16) & 0xffff) | ((buf[0] & 0xffff) << 16); 145 tbuf[1] = ((buf[1] >> 16) & 0xffff) | ((buf[1] & 0xffff) << 16); 146 (*vax_d_format.decode) (fmt, r, tbuf); 147 } 148 149 /* This is where the condition code register lives. */ 150 /* rtx cc0_reg_rtx; - no longer needed? */ 151 152 static const char *singlemove_string (rtx *); 153 static bool pdp11_assemble_integer (rtx, unsigned int, int); 154 static bool pdp11_rtx_costs (rtx, machine_mode, int, int, int *, bool); 155 static bool pdp11_return_in_memory (const_tree, const_tree); 156 static rtx pdp11_function_value (const_tree, const_tree, bool); 157 static rtx pdp11_libcall_value (machine_mode, const_rtx); 158 static bool pdp11_function_value_regno_p (const unsigned int); 159 static void pdp11_trampoline_init (rtx, tree, rtx); 160 static rtx pdp11_function_arg (cumulative_args_t, machine_mode, 161 const_tree, bool); 162 static void pdp11_function_arg_advance (cumulative_args_t, 163 machine_mode, const_tree, bool); 164 static void pdp11_conditional_register_usage (void); 165 static bool pdp11_legitimate_constant_p (machine_mode, rtx); 166 167 static bool pdp11_scalar_mode_supported_p (scalar_mode); 168 169 /* Initialize the GCC target structure. */ 170 #undef TARGET_ASM_BYTE_OP 171 #define TARGET_ASM_BYTE_OP NULL 172 #undef TARGET_ASM_ALIGNED_HI_OP 173 #define TARGET_ASM_ALIGNED_HI_OP NULL 174 #undef TARGET_ASM_ALIGNED_SI_OP 175 #define TARGET_ASM_ALIGNED_SI_OP NULL 176 #undef TARGET_ASM_INTEGER 177 #define TARGET_ASM_INTEGER pdp11_assemble_integer 178 179 #undef TARGET_ASM_OPEN_PAREN 180 #define TARGET_ASM_OPEN_PAREN "[" 181 #undef TARGET_ASM_CLOSE_PAREN 182 #define TARGET_ASM_CLOSE_PAREN "]" 183 184 #undef TARGET_RTX_COSTS 185 #define TARGET_RTX_COSTS pdp11_rtx_costs 186 187 #undef TARGET_FUNCTION_ARG 188 #define TARGET_FUNCTION_ARG pdp11_function_arg 189 #undef TARGET_FUNCTION_ARG_ADVANCE 190 #define TARGET_FUNCTION_ARG_ADVANCE pdp11_function_arg_advance 191 192 #undef TARGET_RETURN_IN_MEMORY 193 #define TARGET_RETURN_IN_MEMORY pdp11_return_in_memory 194 195 #undef TARGET_FUNCTION_VALUE 196 #define TARGET_FUNCTION_VALUE pdp11_function_value 197 #undef TARGET_LIBCALL_VALUE 198 #define TARGET_LIBCALL_VALUE pdp11_libcall_value 199 #undef TARGET_FUNCTION_VALUE_REGNO_P 200 #define TARGET_FUNCTION_VALUE_REGNO_P pdp11_function_value_regno_p 201 202 #undef TARGET_TRAMPOLINE_INIT 203 #define TARGET_TRAMPOLINE_INIT pdp11_trampoline_init 204 205 #undef TARGET_SECONDARY_RELOAD 206 #define TARGET_SECONDARY_RELOAD pdp11_secondary_reload 207 208 #undef TARGET_REGISTER_MOVE_COST 209 #define TARGET_REGISTER_MOVE_COST pdp11_register_move_cost 210 211 #undef TARGET_PREFERRED_RELOAD_CLASS 212 #define TARGET_PREFERRED_RELOAD_CLASS pdp11_preferred_reload_class 213 214 #undef TARGET_PREFERRED_OUTPUT_RELOAD_CLASS 215 #define TARGET_PREFERRED_OUTPUT_RELOAD_CLASS pdp11_preferred_output_reload_class 216 217 #undef TARGET_LRA_P 218 #define TARGET_LRA_P hook_bool_void_false 219 220 #undef TARGET_LEGITIMATE_ADDRESS_P 221 #define TARGET_LEGITIMATE_ADDRESS_P pdp11_legitimate_address_p 222 223 #undef TARGET_CONDITIONAL_REGISTER_USAGE 224 #define TARGET_CONDITIONAL_REGISTER_USAGE pdp11_conditional_register_usage 225 226 #undef TARGET_ASM_FUNCTION_SECTION 227 #define TARGET_ASM_FUNCTION_SECTION pdp11_function_section 228 229 #undef TARGET_PRINT_OPERAND 230 #define TARGET_PRINT_OPERAND pdp11_asm_print_operand 231 232 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 233 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P pdp11_asm_print_operand_punct_valid_p 234 235 #undef TARGET_LEGITIMATE_CONSTANT_P 236 #define TARGET_LEGITIMATE_CONSTANT_P pdp11_legitimate_constant_p 237 238 #undef TARGET_SCALAR_MODE_SUPPORTED_P 239 #define TARGET_SCALAR_MODE_SUPPORTED_P pdp11_scalar_mode_supported_p 240 241 #undef TARGET_HARD_REGNO_NREGS 242 #define TARGET_HARD_REGNO_NREGS pdp11_hard_regno_nregs 243 #undef TARGET_HARD_REGNO_MODE_OK 244 #define TARGET_HARD_REGNO_MODE_OK pdp11_hard_regno_mode_ok 245 246 #undef TARGET_MODES_TIEABLE_P 247 #define TARGET_MODES_TIEABLE_P pdp11_modes_tieable_p 248 249 #undef TARGET_SECONDARY_MEMORY_NEEDED 250 #define TARGET_SECONDARY_MEMORY_NEEDED pdp11_secondary_memory_needed 251 252 #undef TARGET_CAN_CHANGE_MODE_CLASS 253 #define TARGET_CAN_CHANGE_MODE_CLASS pdp11_can_change_mode_class 254 255 /* A helper function to determine if REGNO should be saved in the 256 current function's stack frame. */ 257 258 static inline bool 259 pdp11_saved_regno (unsigned regno) 260 { 261 return !call_used_regs[regno] && df_regs_ever_live_p (regno); 262 } 263 264 /* Expand the function prologue. */ 265 266 void 267 pdp11_expand_prologue (void) 268 { 269 HOST_WIDE_INT fsize = get_frame_size (); 270 unsigned regno; 271 rtx x, via_ac = NULL; 272 273 /* If we are outputting code for main, the switch FPU to the 274 right mode if TARGET_FPU. */ 275 if (MAIN_NAME_P (DECL_NAME (current_function_decl)) && TARGET_FPU) 276 { 277 emit_insn (gen_setd ()); 278 emit_insn (gen_seti ()); 279 } 280 281 if (frame_pointer_needed) 282 { 283 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); 284 x = gen_frame_mem (Pmode, x); 285 emit_move_insn (x, hard_frame_pointer_rtx); 286 287 emit_move_insn (hard_frame_pointer_rtx, stack_pointer_rtx); 288 } 289 290 /* Make frame. */ 291 if (fsize) 292 { 293 emit_insn (gen_addhi3 (stack_pointer_rtx, stack_pointer_rtx, 294 GEN_INT (-fsize))); 295 296 /* Prevent frame references via the frame pointer from being 297 scheduled before the frame is allocated. */ 298 if (frame_pointer_needed) 299 emit_insn (gen_blockage ()); 300 } 301 302 /* Save CPU registers. */ 303 for (regno = R0_REGNUM; regno <= PC_REGNUM; regno++) 304 if (pdp11_saved_regno (regno) 305 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed)) 306 { 307 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); 308 x = gen_frame_mem (Pmode, x); 309 emit_move_insn (x, gen_rtx_REG (Pmode, regno)); 310 } 311 312 /* Save FPU registers. */ 313 for (regno = AC0_REGNUM; regno <= AC3_REGNUM; regno++) 314 if (pdp11_saved_regno (regno)) 315 { 316 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); 317 x = gen_frame_mem (DFmode, x); 318 via_ac = gen_rtx_REG (DFmode, regno); 319 emit_move_insn (x, via_ac); 320 } 321 322 /* ??? Maybe make ac4, ac5 call used regs?? */ 323 for (regno = AC4_REGNUM; regno <= AC5_REGNUM; regno++) 324 if (pdp11_saved_regno (regno)) 325 { 326 gcc_assert (via_ac != NULL); 327 emit_move_insn (via_ac, gen_rtx_REG (DFmode, regno)); 328 329 x = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); 330 x = gen_frame_mem (DFmode, x); 331 emit_move_insn (x, via_ac); 332 } 333 } 334 335 /* The function epilogue should not depend on the current stack pointer! 336 It should use the frame pointer only. This is mandatory because 337 of alloca; we also take advantage of it to omit stack adjustments 338 before returning. */ 339 340 /* Maybe we can make leaf functions faster by switching to the 341 second register file - this way we don't have to save regs! 342 leaf functions are ~ 50% of all functions (dynamically!) 343 344 set/clear bit 11 (dec. 2048) of status word for switching register files - 345 but how can we do this? the pdp11/45 manual says bit may only 346 be set (p.24), but not cleared! 347 348 switching to kernel is probably more expensive, so we'll leave it 349 like this and not use the second set of registers... 350 351 maybe as option if you want to generate code for kernel mode? */ 352 353 void 354 pdp11_expand_epilogue (void) 355 { 356 HOST_WIDE_INT fsize = get_frame_size (); 357 unsigned regno; 358 rtx x, reg, via_ac = NULL; 359 360 if (pdp11_saved_regno (AC4_REGNUM) || pdp11_saved_regno (AC5_REGNUM)) 361 { 362 /* Find a temporary with which to restore AC4/5. */ 363 for (regno = AC0_REGNUM; regno <= AC3_REGNUM; regno++) 364 if (pdp11_saved_regno (regno)) 365 { 366 via_ac = gen_rtx_REG (DFmode, regno); 367 break; 368 } 369 } 370 371 /* If possible, restore registers via pops. */ 372 if (!frame_pointer_needed || crtl->sp_is_unchanging) 373 { 374 /* Restore registers via pops. */ 375 376 for (regno = AC5_REGNUM; regno >= AC0_REGNUM; regno--) 377 if (pdp11_saved_regno (regno)) 378 { 379 x = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); 380 x = gen_frame_mem (DFmode, x); 381 reg = gen_rtx_REG (DFmode, regno); 382 383 if (LOAD_FPU_REG_P (regno)) 384 emit_move_insn (reg, x); 385 else 386 { 387 emit_move_insn (via_ac, x); 388 emit_move_insn (reg, via_ac); 389 } 390 } 391 392 for (regno = PC_REGNUM; regno >= R0_REGNUM + 2; regno--) 393 if (pdp11_saved_regno (regno) 394 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed)) 395 { 396 x = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); 397 x = gen_frame_mem (Pmode, x); 398 emit_move_insn (gen_rtx_REG (Pmode, regno), x); 399 } 400 } 401 else 402 { 403 /* Restore registers via moves. */ 404 /* ??? If more than a few registers need to be restored, it's smaller 405 to generate a pointer through which we can emit pops. Consider 406 that moves cost 2*NREG words and pops cost NREG+3 words. This 407 means that the crossover is NREG=3. 408 409 Possible registers to use are: 410 (1) The first call-saved general register. This register will 411 be restored with the last pop. 412 (2) R1, if it's not used as a return register. 413 (3) FP itself. This option may result in +4 words, since we 414 may need two add imm,rn instructions instead of just one. 415 This also has the downside that we're not representing 416 the unwind info in any way, so during the epilogue the 417 debugger may get lost. */ 418 419 HOST_WIDE_INT ofs = -pdp11_sp_frame_offset (); 420 421 for (regno = AC5_REGNUM; regno >= AC0_REGNUM; regno--) 422 if (pdp11_saved_regno (regno)) 423 { 424 x = plus_constant (Pmode, hard_frame_pointer_rtx, ofs); 425 x = gen_frame_mem (DFmode, x); 426 reg = gen_rtx_REG (DFmode, regno); 427 428 if (LOAD_FPU_REG_P (regno)) 429 emit_move_insn (reg, x); 430 else 431 { 432 emit_move_insn (via_ac, x); 433 emit_move_insn (reg, via_ac); 434 } 435 ofs += 8; 436 } 437 438 for (regno = PC_REGNUM; regno >= R0_REGNUM + 2; regno--) 439 if (pdp11_saved_regno (regno) 440 && (regno != HARD_FRAME_POINTER_REGNUM || !frame_pointer_needed)) 441 { 442 x = plus_constant (Pmode, hard_frame_pointer_rtx, ofs); 443 x = gen_frame_mem (Pmode, x); 444 emit_move_insn (gen_rtx_REG (Pmode, regno), x); 445 ofs += 2; 446 } 447 } 448 449 /* Deallocate the stack frame. */ 450 if (fsize) 451 { 452 /* Prevent frame references via any pointer from being 453 scheduled after the frame is deallocated. */ 454 emit_insn (gen_blockage ()); 455 456 if (frame_pointer_needed) 457 { 458 /* We can deallocate the frame with a single move. */ 459 emit_move_insn (stack_pointer_rtx, hard_frame_pointer_rtx); 460 } 461 else 462 emit_insn (gen_addhi3 (stack_pointer_rtx, stack_pointer_rtx, 463 GEN_INT (fsize))); 464 } 465 466 if (frame_pointer_needed) 467 { 468 x = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); 469 x = gen_frame_mem (Pmode, x); 470 emit_move_insn (hard_frame_pointer_rtx, x); 471 } 472 473 emit_jump_insn (gen_return ()); 474 } 475 476 /* Return the best assembler insn template 477 for moving operands[1] into operands[0] as a fullword. */ 478 static const char * 479 singlemove_string (rtx *operands) 480 { 481 if (operands[1] != const0_rtx) 482 return "mov %1,%0"; 483 484 return "clr %0"; 485 } 486 487 488 /* Expand multi-word operands (SImode or DImode) into the 2 or 4 489 corresponding HImode operands. The number of operands is given 490 as the third argument, and the required order of the parts as 491 the fourth argument. */ 492 bool 493 pdp11_expand_operands (rtx *operands, rtx exops[][2], int opcount, 494 pdp11_action *action, pdp11_partorder order) 495 { 496 int words, op, w, i, sh; 497 pdp11_partorder useorder; 498 bool sameoff = false; 499 enum { REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP } optype; 500 long sval[2]; 501 502 words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16; 503 504 /* If either piece order is accepted and one is pre-decrement 505 while the other is post-increment, set order to be high order 506 word first. That will force the pre-decrement to be turned 507 into a pointer adjust, then offset addressing. 508 Otherwise, if either operand uses pre-decrement, that means 509 the order is low order first. 510 Otherwise, if both operands are registers and destination is 511 higher than source and they overlap, do low order word (highest 512 register number) first. */ 513 useorder = either; 514 if (opcount == 2) 515 { 516 if (!REG_P (operands[0]) && !REG_P (operands[1]) && 517 !(CONSTANT_P (operands[1]) || 518 GET_CODE (operands[1]) == CONST_DOUBLE) && 519 ((GET_CODE (XEXP (operands[0], 0)) == POST_INC && 520 GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) || 521 (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC && 522 GET_CODE (XEXP (operands[1], 0)) == POST_INC))) 523 useorder = big; 524 else if ((!REG_P (operands[0]) && 525 GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) || 526 (!REG_P (operands[1]) && 527 !(CONSTANT_P (operands[1]) || 528 GET_CODE (operands[1]) == CONST_DOUBLE) && 529 GET_CODE (XEXP (operands[1], 0)) == PRE_DEC)) 530 useorder = little; 531 else if (REG_P (operands[0]) && REG_P (operands[1]) && 532 REGNO (operands[0]) > REGNO (operands[1]) && 533 REGNO (operands[0]) < REGNO (operands[1]) + words) 534 useorder = little; 535 536 /* Check for source == offset from register and dest == push of 537 the same register. In that case, we have to use the same 538 offset (the one for the low order word) for all words, because 539 the push increases the offset to each source word. 540 In theory there are other cases like this, for example dest == pop, 541 but those don't occur in real life so ignore those. */ 542 if (GET_CODE (operands[0]) == MEM 543 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC 544 && REGNO (XEXP (XEXP (operands[0], 0), 0)) == STACK_POINTER_REGNUM 545 && reg_overlap_mentioned_p (stack_pointer_rtx, operands[1])) 546 sameoff = true; 547 } 548 549 /* If the caller didn't specify order, use the one we computed, 550 or high word first if we don't care either. If the caller did 551 specify, verify we don't have a problem with that order. 552 (If it matters to the caller, constraints need to be used to 553 ensure this case doesn't occur). */ 554 if (order == either) 555 order = (useorder == either) ? big : useorder; 556 else 557 gcc_assert (useorder == either || useorder == order); 558 559 560 for (op = 0; op < opcount; op++) 561 { 562 /* First classify the operand. */ 563 if (REG_P (operands[op])) 564 optype = REGOP; 565 else if (CONSTANT_P (operands[op]) 566 || GET_CODE (operands[op]) == CONST_DOUBLE) 567 optype = CNSTOP; 568 else if (GET_CODE (XEXP (operands[op], 0)) == POST_INC) 569 optype = POPOP; 570 else if (GET_CODE (XEXP (operands[op], 0)) == PRE_DEC) 571 optype = PUSHOP; 572 else if (!reload_in_progress || offsettable_memref_p (operands[op])) 573 optype = OFFSOP; 574 else if (GET_CODE (operands[op]) == MEM) 575 optype = MEMOP; 576 else 577 optype = RNDOP; 578 579 /* Check for the cases that the operand constraints are not 580 supposed to allow to happen. Return failure for such cases. */ 581 if (optype == RNDOP) 582 return false; 583 584 if (action != NULL) 585 action[op] = no_action; 586 587 /* If the operand uses pre-decrement addressing but we 588 want to get the parts high order first, 589 decrement the former register explicitly 590 and change the operand into ordinary indexing. */ 591 if (optype == PUSHOP && order == big) 592 { 593 gcc_assert (action != NULL); 594 action[op] = dec_before; 595 operands[op] = gen_rtx_MEM (GET_MODE (operands[op]), 596 XEXP (XEXP (operands[op], 0), 0)); 597 optype = OFFSOP; 598 } 599 /* If the operand uses post-increment mode but we want 600 to get the parts low order first, change the operand 601 into ordinary indexing and remember to increment 602 the register explicitly when we're done. */ 603 else if (optype == POPOP && order == little) 604 { 605 gcc_assert (action != NULL); 606 action[op] = inc_after; 607 operands[op] = gen_rtx_MEM (GET_MODE (operands[op]), 608 XEXP (XEXP (operands[op], 0), 0)); 609 optype = OFFSOP; 610 } 611 612 if (GET_CODE (operands[op]) == CONST_DOUBLE) 613 REAL_VALUE_TO_TARGET_DOUBLE 614 (*CONST_DOUBLE_REAL_VALUE (operands[op]), sval); 615 616 for (i = 0; i < words; i++) 617 { 618 if (order == big) 619 w = i; 620 else if (sameoff) 621 w = words - 1; 622 else 623 w = words - 1 - i; 624 625 /* Set the output operand to be word "w" of the input. */ 626 if (optype == REGOP) 627 exops[i][op] = gen_rtx_REG (HImode, REGNO (operands[op]) + w); 628 else if (optype == OFFSOP) 629 exops[i][op] = adjust_address (operands[op], HImode, w * 2); 630 else if (optype == CNSTOP) 631 { 632 if (GET_CODE (operands[op]) == CONST_DOUBLE) 633 { 634 sh = 16 - (w & 1) * 16; 635 exops[i][op] = gen_rtx_CONST_INT (HImode, (sval[w / 2] >> sh) & 0xffff); 636 } 637 else 638 { 639 sh = ((words - 1 - w) * 16); 640 exops[i][op] = gen_rtx_CONST_INT (HImode, trunc_int_for_mode (INTVAL(operands[op]) >> sh, HImode)); 641 } 642 } 643 else 644 exops[i][op] = operands[op]; 645 } 646 } 647 return true; 648 } 649 650 /* Output assembler code to perform a multiple-word move insn 651 with operands OPERANDS. This moves 2 or 4 words depending 652 on the machine mode of the operands. */ 653 654 const char * 655 output_move_multiple (rtx *operands) 656 { 657 rtx exops[4][2]; 658 pdp11_action action[2]; 659 int i, words; 660 661 words = GET_MODE_BITSIZE (GET_MODE (operands[0])) / 16; 662 663 pdp11_expand_operands (operands, exops, 2, action, either); 664 665 /* Check for explicit decrement before. */ 666 if (action[0] == dec_before) 667 { 668 operands[0] = XEXP (operands[0], 0); 669 output_asm_insn ("sub $4,%0", operands); 670 } 671 if (action[1] == dec_before) 672 { 673 operands[1] = XEXP (operands[1], 0); 674 output_asm_insn ("sub $4,%1", operands); 675 } 676 677 /* Do the words. */ 678 for (i = 0; i < words; i++) 679 output_asm_insn (singlemove_string (exops[i]), exops[i]); 680 681 /* Check for increment after. */ 682 if (action[0] == inc_after) 683 { 684 operands[0] = XEXP (operands[0], 0); 685 output_asm_insn ("add $4,%0", operands); 686 } 687 if (action[1] == inc_after) 688 { 689 operands[1] = XEXP (operands[1], 0); 690 output_asm_insn ("add $4,%1", operands); 691 } 692 693 return ""; 694 } 695 696 /* Output an ascii string. */ 697 void 698 output_ascii (FILE *file, const char *p, int size) 699 { 700 int i; 701 702 /* This used to output .byte "string", which doesn't work with the UNIX 703 assembler and I think not with DEC ones either. */ 704 fprintf (file, "\t.byte "); 705 706 for (i = 0; i < size; i++) 707 { 708 register int c = p[i]; 709 if (c < 0) 710 c += 256; 711 fprintf (file, "%#o", c); 712 if (i < size - 1) 713 putc (',', file); 714 } 715 putc ('\n', file); 716 } 717 718 719 void 720 pdp11_asm_output_var (FILE *file, const char *name, int size, 721 int align, bool global) 722 { 723 if (align > 8) 724 fprintf (file, "\n\t.even\n"); 725 if (global) 726 { 727 fprintf (file, ".globl "); 728 assemble_name (file, name); 729 } 730 fprintf (file, "\n"); 731 assemble_name (file, name); 732 fprintf (file, ": .=.+ %#ho\n", (unsigned short)size); 733 } 734 735 static void 736 pdp11_asm_print_operand (FILE *file, rtx x, int code) 737 { 738 long sval[2]; 739 740 if (code == '#') 741 fprintf (file, "#"); 742 else if (code == '@') 743 { 744 if (TARGET_UNIX_ASM) 745 fprintf (file, "*"); 746 else 747 fprintf (file, "@"); 748 } 749 else if (GET_CODE (x) == REG) 750 fprintf (file, "%s", reg_names[REGNO (x)]); 751 else if (GET_CODE (x) == MEM) 752 output_address (GET_MODE (x), XEXP (x, 0)); 753 else if (GET_CODE (x) == CONST_DOUBLE && GET_MODE (x) != SImode) 754 { 755 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (x), sval); 756 fprintf (file, "$%#lo", sval[0] >> 16); 757 } 758 else 759 { 760 putc ('$', file); 761 output_addr_const_pdp11 (file, x); 762 } 763 } 764 765 static bool 766 pdp11_asm_print_operand_punct_valid_p (unsigned char c) 767 { 768 return (c == '#' || c == '@'); 769 } 770 771 void 772 print_operand_address (FILE *file, register rtx addr) 773 { 774 register rtx breg; 775 rtx offset; 776 int again = 0; 777 778 retry: 779 780 switch (GET_CODE (addr)) 781 { 782 case MEM: 783 if (TARGET_UNIX_ASM) 784 fprintf (file, "*"); 785 else 786 fprintf (file, "@"); 787 addr = XEXP (addr, 0); 788 again = 1; 789 goto retry; 790 791 case REG: 792 fprintf (file, "(%s)", reg_names[REGNO (addr)]); 793 break; 794 795 case PRE_MODIFY: 796 case PRE_DEC: 797 fprintf (file, "-(%s)", reg_names[REGNO (XEXP (addr, 0))]); 798 break; 799 800 case POST_MODIFY: 801 case POST_INC: 802 fprintf (file, "(%s)+", reg_names[REGNO (XEXP (addr, 0))]); 803 break; 804 805 case PLUS: 806 breg = 0; 807 offset = 0; 808 if (CONSTANT_ADDRESS_P (XEXP (addr, 0)) 809 || GET_CODE (XEXP (addr, 0)) == MEM) 810 { 811 offset = XEXP (addr, 0); 812 addr = XEXP (addr, 1); 813 } 814 else if (CONSTANT_ADDRESS_P (XEXP (addr, 1)) 815 || GET_CODE (XEXP (addr, 1)) == MEM) 816 { 817 offset = XEXP (addr, 1); 818 addr = XEXP (addr, 0); 819 } 820 if (GET_CODE (addr) != PLUS) 821 ; 822 else if (GET_CODE (XEXP (addr, 0)) == REG) 823 { 824 breg = XEXP (addr, 0); 825 addr = XEXP (addr, 1); 826 } 827 else if (GET_CODE (XEXP (addr, 1)) == REG) 828 { 829 breg = XEXP (addr, 1); 830 addr = XEXP (addr, 0); 831 } 832 if (GET_CODE (addr) == REG) 833 { 834 gcc_assert (breg == 0); 835 breg = addr; 836 addr = 0; 837 } 838 if (offset != 0) 839 { 840 gcc_assert (addr == 0); 841 addr = offset; 842 } 843 if (addr != 0) 844 output_addr_const_pdp11 (file, addr); 845 if (breg != 0) 846 { 847 gcc_assert (GET_CODE (breg) == REG); 848 fprintf (file, "(%s)", reg_names[REGNO (breg)]); 849 } 850 break; 851 852 default: 853 if (!again && GET_CODE (addr) == CONST_INT) 854 { 855 /* Absolute (integer number) address. */ 856 if (!TARGET_UNIX_ASM) 857 fprintf (file, "@$"); 858 } 859 output_addr_const_pdp11 (file, addr); 860 } 861 } 862 863 /* Target hook to assemble integer objects. We need to use the 864 pdp-specific version of output_addr_const. */ 865 866 static bool 867 pdp11_assemble_integer (rtx x, unsigned int size, int aligned_p) 868 { 869 if (aligned_p) 870 switch (size) 871 { 872 case 1: 873 fprintf (asm_out_file, "\t.byte\t"); 874 output_addr_const_pdp11 (asm_out_file, GEN_INT (INTVAL (x) & 0xff)); 875 ; 876 fprintf (asm_out_file, " /* char */\n"); 877 return true; 878 879 case 2: 880 fprintf (asm_out_file, TARGET_UNIX_ASM ? "\t" : "\t.word\t"); 881 output_addr_const_pdp11 (asm_out_file, x); 882 fprintf (asm_out_file, " /* short */\n"); 883 return true; 884 } 885 return default_assemble_integer (x, size, aligned_p); 886 } 887 888 889 /* register move costs, indexed by regs */ 890 891 static const int move_costs[N_REG_CLASSES][N_REG_CLASSES] = 892 { 893 /* NO MUL GEN LFPU NLFPU FPU ALL */ 894 895 /* NO */ { 0, 0, 0, 0, 0, 0, 0}, 896 /* MUL */ { 0, 2, 2, 22, 22, 22, 22}, 897 /* GEN */ { 0, 2, 2, 22, 22, 22, 22}, 898 /* LFPU */ { 0, 22, 22, 2, 2, 2, 22}, 899 /* NLFPU */ { 0, 22, 22, 2, 10, 10, 22}, 900 /* FPU */ { 0, 22, 22, 2, 10, 10, 22}, 901 /* ALL */ { 0, 22, 22, 22, 22, 22, 22} 902 } ; 903 904 905 /* -- note that some moves are tremendously expensive, 906 because they require lots of tricks! do we have to 907 charge the costs incurred by secondary reload class 908 -- as we do here with 10 -- or not ? */ 909 910 static int 911 pdp11_register_move_cost (machine_mode mode ATTRIBUTE_UNUSED, 912 reg_class_t c1, reg_class_t c2) 913 { 914 return move_costs[(int)c1][(int)c2]; 915 } 916 917 static bool 918 pdp11_rtx_costs (rtx x, machine_mode mode, int outer_code ATTRIBUTE_UNUSED, 919 int opno ATTRIBUTE_UNUSED, int *total, 920 bool speed ATTRIBUTE_UNUSED) 921 { 922 int code = GET_CODE (x); 923 924 switch (code) 925 { 926 case CONST_INT: 927 if (INTVAL (x) == 0 || INTVAL (x) == -1 || INTVAL (x) == 1) 928 { 929 *total = 0; 930 return true; 931 } 932 /* FALLTHRU */ 933 934 case CONST: 935 case LABEL_REF: 936 case SYMBOL_REF: 937 /* Twice as expensive as REG. */ 938 *total = 2; 939 return true; 940 941 case CONST_DOUBLE: 942 /* Twice (or 4 times) as expensive as 16 bit. */ 943 *total = 4; 944 return true; 945 946 case MULT: 947 /* ??? There is something wrong in MULT because MULT is not 948 as cheap as total = 2 even if we can shift! */ 949 /* If optimizing for size make mult etc cheap, but not 1, so when 950 in doubt the faster insn is chosen. */ 951 if (optimize_size) 952 *total = COSTS_N_INSNS (2); 953 else 954 *total = COSTS_N_INSNS (11); 955 return false; 956 957 case DIV: 958 if (optimize_size) 959 *total = COSTS_N_INSNS (2); 960 else 961 *total = COSTS_N_INSNS (25); 962 return false; 963 964 case MOD: 965 if (optimize_size) 966 *total = COSTS_N_INSNS (2); 967 else 968 *total = COSTS_N_INSNS (26); 969 return false; 970 971 case ABS: 972 /* Equivalent to length, so same for optimize_size. */ 973 *total = COSTS_N_INSNS (3); 974 return false; 975 976 case ZERO_EXTEND: 977 /* Only used for qi->hi. */ 978 *total = COSTS_N_INSNS (1); 979 return false; 980 981 case SIGN_EXTEND: 982 if (mode == HImode) 983 *total = COSTS_N_INSNS (1); 984 else if (mode == SImode) 985 *total = COSTS_N_INSNS (6); 986 else 987 *total = COSTS_N_INSNS (2); 988 return false; 989 990 case ASHIFT: 991 case LSHIFTRT: 992 case ASHIFTRT: 993 if (optimize_size) 994 *total = COSTS_N_INSNS (1); 995 else if (mode == QImode) 996 { 997 if (GET_CODE (XEXP (x, 1)) != CONST_INT) 998 *total = COSTS_N_INSNS (8); /* worst case */ 999 else 1000 *total = COSTS_N_INSNS (INTVAL (XEXP (x, 1))); 1001 } 1002 else if (mode == HImode) 1003 { 1004 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 1005 { 1006 if (abs (INTVAL (XEXP (x, 1))) == 1) 1007 *total = COSTS_N_INSNS (1); 1008 else 1009 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1))); 1010 } 1011 else 1012 *total = COSTS_N_INSNS (10); /* worst case */ 1013 } 1014 else if (mode == SImode) 1015 { 1016 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 1017 *total = COSTS_N_INSNS (2.5 + 0.5 * INTVAL (XEXP (x, 1))); 1018 else /* worst case */ 1019 *total = COSTS_N_INSNS (18); 1020 } 1021 return false; 1022 1023 default: 1024 return false; 1025 } 1026 } 1027 1028 const char * 1029 output_jump (enum rtx_code code, int inv, int length) 1030 { 1031 static int x = 0; 1032 1033 static char buf[1000]; 1034 const char *pos, *neg; 1035 1036 if (cc_prev_status.flags & CC_NO_OVERFLOW) 1037 { 1038 switch (code) 1039 { 1040 case GTU: code = GT; break; 1041 case LTU: code = LT; break; 1042 case GEU: code = GE; break; 1043 case LEU: code = LE; break; 1044 default: ; 1045 } 1046 } 1047 switch (code) 1048 { 1049 case EQ: pos = "beq", neg = "bne"; break; 1050 case NE: pos = "bne", neg = "beq"; break; 1051 case GT: pos = "bgt", neg = "ble"; break; 1052 case GTU: pos = "bhi", neg = "blos"; break; 1053 case LT: pos = "blt", neg = "bge"; break; 1054 case LTU: pos = "blo", neg = "bhis"; break; 1055 case GE: pos = "bge", neg = "blt"; break; 1056 case GEU: pos = "bhis", neg = "blo"; break; 1057 case LE: pos = "ble", neg = "bgt"; break; 1058 case LEU: pos = "blos", neg = "bhi"; break; 1059 default: gcc_unreachable (); 1060 } 1061 1062 #if 0 1063 /* currently we don't need this, because the tstdf and cmpdf 1064 copy the condition code immediately, and other float operations are not 1065 yet recognized as changing the FCC - if so, then the length-cost of all 1066 jump insns increases by one, because we have to potentially copy the 1067 FCC! */ 1068 if (cc_status.flags & CC_IN_FPU) 1069 output_asm_insn("cfcc", NULL); 1070 #endif 1071 1072 switch (length) 1073 { 1074 case 2: 1075 1076 sprintf(buf, "%s %%l1", inv ? neg : pos); 1077 1078 return buf; 1079 1080 case 6: 1081 1082 sprintf(buf, "%s JMP_%d\n\tjmp %%l1\nJMP_%d:", inv ? pos : neg, x, x); 1083 1084 x++; 1085 1086 return buf; 1087 1088 default: 1089 1090 gcc_unreachable (); 1091 } 1092 1093 } 1094 1095 void 1096 notice_update_cc_on_set(rtx exp, rtx insn ATTRIBUTE_UNUSED) 1097 { 1098 if (GET_CODE (SET_DEST (exp)) == CC0) 1099 { 1100 cc_status.flags = 0; 1101 cc_status.value1 = SET_DEST (exp); 1102 cc_status.value2 = SET_SRC (exp); 1103 } 1104 else if (GET_CODE (SET_SRC (exp)) == CALL) 1105 { 1106 CC_STATUS_INIT; 1107 } 1108 else if (SET_DEST(exp) == pc_rtx) 1109 { 1110 /* jump */ 1111 } 1112 else if (GET_MODE (SET_DEST(exp)) == HImode 1113 || GET_MODE (SET_DEST(exp)) == QImode) 1114 { 1115 cc_status.flags = GET_CODE (SET_SRC(exp)) == MINUS ? 0 : CC_NO_OVERFLOW; 1116 cc_status.value1 = SET_SRC (exp); 1117 cc_status.value2 = SET_DEST (exp); 1118 1119 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG 1120 && cc_status.value2 1121 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) 1122 cc_status.value2 = 0; 1123 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM 1124 && cc_status.value2 1125 && GET_CODE (cc_status.value2) == MEM) 1126 cc_status.value2 = 0; 1127 } 1128 else 1129 { 1130 CC_STATUS_INIT; 1131 } 1132 } 1133 1134 1135 int 1136 simple_memory_operand(rtx op, machine_mode mode ATTRIBUTE_UNUSED) 1137 { 1138 rtx addr; 1139 1140 /* Eliminate non-memory operations */ 1141 if (GET_CODE (op) != MEM) 1142 return FALSE; 1143 1144 #if 0 1145 /* dword operations really put out 2 instructions, so eliminate them. */ 1146 if (GET_MODE_SIZE (GET_MODE (op)) > (HAVE_64BIT_P () ? 8 : 4)) 1147 return FALSE; 1148 #endif 1149 1150 /* Decode the address now. */ 1151 1152 indirection: 1153 1154 addr = XEXP (op, 0); 1155 1156 switch (GET_CODE (addr)) 1157 { 1158 case REG: 1159 /* (R0) - no extra cost */ 1160 return 1; 1161 1162 case PRE_DEC: 1163 case POST_INC: 1164 /* -(R0), (R0)+ - cheap! */ 1165 return 0; 1166 1167 case MEM: 1168 /* cheap - is encoded in addressing mode info! 1169 1170 -- except for @(R0), which has to be @0(R0) !!! */ 1171 1172 if (GET_CODE (XEXP (addr, 0)) == REG) 1173 return 0; 1174 1175 op=addr; 1176 goto indirection; 1177 1178 case CONST_INT: 1179 case LABEL_REF: 1180 case CONST: 1181 case SYMBOL_REF: 1182 /* @#address - extra cost */ 1183 return 0; 1184 1185 case PLUS: 1186 /* X(R0) - extra cost */ 1187 return 0; 1188 1189 default: 1190 break; 1191 } 1192 1193 return FALSE; 1194 } 1195 1196 1197 /* 1198 * output a block move: 1199 * 1200 * operands[0] ... to 1201 * operands[1] ... from 1202 * operands[2] ... length 1203 * operands[3] ... alignment 1204 * operands[4] ... scratch register 1205 */ 1206 1207 1208 const char * 1209 output_block_move(rtx *operands) 1210 { 1211 static int count = 0; 1212 char buf[200]; 1213 int unroll; 1214 int lastbyte = 0; 1215 1216 /* Move of zero bytes is a NOP. */ 1217 if (operands[2] == const0_rtx) 1218 return ""; 1219 1220 /* Look for moves by small constant byte counts, those we'll 1221 expand to straight line code. */ 1222 if (CONSTANT_P (operands[2])) 1223 { 1224 if (INTVAL (operands[2]) < 16 1225 && (!optimize_size || INTVAL (operands[2]) < 5) 1226 && INTVAL (operands[3]) == 1) 1227 { 1228 register int i; 1229 1230 for (i = 1; i <= INTVAL (operands[2]); i++) 1231 output_asm_insn("movb (%1)+, (%0)+", operands); 1232 1233 return ""; 1234 } 1235 else if (INTVAL(operands[2]) < 32 1236 && (!optimize_size || INTVAL (operands[2]) < 9) 1237 && INTVAL (operands[3]) >= 2) 1238 { 1239 register int i; 1240 1241 for (i = 1; i <= INTVAL (operands[2]) / 2; i++) 1242 output_asm_insn ("mov (%1)+, (%0)+", operands); 1243 if (INTVAL (operands[2]) & 1) 1244 output_asm_insn ("movb (%1), (%0)", operands); 1245 1246 return ""; 1247 } 1248 } 1249 1250 /* Ideally we'd look for moves that are multiples of 4 or 8 1251 bytes and handle those by unrolling the move loop. That 1252 makes for a lot of code if done at run time, but it's ok 1253 for constant counts. Also, for variable counts we have 1254 to worry about odd byte count with even aligned pointers. 1255 On 11/40 and up we handle that case; on older machines 1256 we don't and just use byte-wise moves all the time. */ 1257 1258 if (CONSTANT_P (operands[2]) ) 1259 { 1260 if (INTVAL (operands[3]) < 2) 1261 unroll = 0; 1262 else 1263 { 1264 lastbyte = INTVAL (operands[2]) & 1; 1265 1266 if (optimize_size || INTVAL (operands[2]) & 2) 1267 unroll = 1; 1268 else if (INTVAL (operands[2]) & 4) 1269 unroll = 2; 1270 else 1271 unroll = 3; 1272 } 1273 1274 /* Loop count is byte count scaled by unroll. */ 1275 operands[2] = GEN_INT (INTVAL (operands[2]) >> unroll); 1276 output_asm_insn ("mov %2, %4", operands); 1277 } 1278 else 1279 { 1280 /* Variable byte count; use the input register 1281 as the scratch. */ 1282 operands[4] = operands[2]; 1283 1284 /* Decide whether to move by words, and check 1285 the byte count for zero. */ 1286 if (TARGET_40_PLUS && INTVAL (operands[3]) > 1) 1287 { 1288 unroll = 1; 1289 output_asm_insn ("asr %4", operands); 1290 } 1291 else 1292 { 1293 unroll = 0; 1294 output_asm_insn ("tst %4", operands); 1295 } 1296 sprintf (buf, "beq movestrhi%d", count + 1); 1297 output_asm_insn (buf, NULL); 1298 } 1299 1300 /* Output the loop label. */ 1301 sprintf (buf, "\nmovestrhi%d:", count); 1302 output_asm_insn (buf, NULL); 1303 1304 /* Output the appropriate move instructions. */ 1305 switch (unroll) 1306 { 1307 case 0: 1308 output_asm_insn ("movb (%1)+, (%0)+", operands); 1309 break; 1310 1311 case 1: 1312 output_asm_insn ("mov (%1)+, (%0)+", operands); 1313 break; 1314 1315 case 2: 1316 output_asm_insn ("mov (%1)+, (%0)+", operands); 1317 output_asm_insn ("mov (%1)+, (%0)+", operands); 1318 break; 1319 1320 default: 1321 output_asm_insn ("mov (%1)+, (%0)+", operands); 1322 output_asm_insn ("mov (%1)+, (%0)+", operands); 1323 output_asm_insn ("mov (%1)+, (%0)+", operands); 1324 output_asm_insn ("mov (%1)+, (%0)+", operands); 1325 break; 1326 } 1327 1328 /* Output the decrement and test. */ 1329 if (TARGET_40_PLUS) 1330 { 1331 sprintf (buf, "sob %%4, movestrhi%d", count); 1332 output_asm_insn (buf, operands); 1333 } 1334 else 1335 { 1336 output_asm_insn ("dec %4", operands); 1337 sprintf (buf, "bgt movestrhi%d", count); 1338 output_asm_insn (buf, NULL); 1339 } 1340 count ++; 1341 1342 /* If constant odd byte count, move the last byte. */ 1343 if (lastbyte) 1344 output_asm_insn ("movb (%1), (%0)", operands); 1345 else if (!CONSTANT_P (operands[2])) 1346 { 1347 /* Output the destination label for the zero byte count check. */ 1348 sprintf (buf, "\nmovestrhi%d:", count); 1349 output_asm_insn (buf, NULL); 1350 count++; 1351 1352 /* If we did word moves, check for trailing last byte. */ 1353 if (unroll) 1354 { 1355 sprintf (buf, "bcc movestrhi%d", count); 1356 output_asm_insn (buf, NULL); 1357 output_asm_insn ("movb (%1), (%0)", operands); 1358 sprintf (buf, "\nmovestrhi%d:", count); 1359 output_asm_insn (buf, NULL); 1360 count++; 1361 } 1362 } 1363 1364 return ""; 1365 } 1366 1367 /* This function checks whether a real value can be encoded as 1368 a literal, i.e., addressing mode 27. In that mode, real values 1369 are one word values, so the remaining 48 bits have to be zero. */ 1370 int 1371 legitimate_const_double_p (rtx address) 1372 { 1373 long sval[2]; 1374 REAL_VALUE_TO_TARGET_DOUBLE (*CONST_DOUBLE_REAL_VALUE (address), sval); 1375 if ((sval[0] & 0xffff) == 0 && sval[1] == 0) 1376 return 1; 1377 return 0; 1378 } 1379 1380 /* Implement TARGET_CAN_CHANGE_MODE_CLASS. */ 1381 static bool 1382 pdp11_can_change_mode_class (machine_mode from, 1383 machine_mode to, 1384 reg_class_t rclass) 1385 { 1386 /* Also, FPU registers contain a whole float value and the parts of 1387 it are not separately accessible. 1388 1389 So we disallow all mode changes involving FPRs. */ 1390 if (FLOAT_MODE_P (from) != FLOAT_MODE_P (to)) 1391 return false; 1392 1393 return !reg_classes_intersect_p (FPU_REGS, rclass); 1394 } 1395 1396 /* TARGET_PREFERRED_RELOAD_CLASS 1397 1398 Given an rtx X being reloaded into a reg required to be 1399 in class CLASS, return the class of reg to actually use. 1400 In general this is just CLASS; but on some machines 1401 in some cases it is preferable to use a more restrictive class. 1402 1403 loading is easier into LOAD_FPU_REGS than FPU_REGS! */ 1404 1405 static reg_class_t 1406 pdp11_preferred_reload_class (rtx x, reg_class_t rclass) 1407 { 1408 if (rclass == FPU_REGS) 1409 return LOAD_FPU_REGS; 1410 if (rclass == ALL_REGS) 1411 { 1412 if (FLOAT_MODE_P (GET_MODE (x))) 1413 return LOAD_FPU_REGS; 1414 else 1415 return GENERAL_REGS; 1416 } 1417 return rclass; 1418 } 1419 1420 /* TARGET_PREFERRED_OUTPUT_RELOAD_CLASS 1421 1422 Given an rtx X being reloaded into a reg required to be 1423 in class CLASS, return the class of reg to actually use. 1424 In general this is just CLASS; but on some machines 1425 in some cases it is preferable to use a more restrictive class. 1426 1427 loading is easier into LOAD_FPU_REGS than FPU_REGS! */ 1428 1429 static reg_class_t 1430 pdp11_preferred_output_reload_class (rtx x, reg_class_t rclass) 1431 { 1432 if (rclass == FPU_REGS) 1433 return LOAD_FPU_REGS; 1434 if (rclass == ALL_REGS) 1435 { 1436 if (FLOAT_MODE_P (GET_MODE (x))) 1437 return LOAD_FPU_REGS; 1438 else 1439 return GENERAL_REGS; 1440 } 1441 return rclass; 1442 } 1443 1444 1445 /* TARGET_SECONDARY_RELOAD. 1446 1447 FPU registers AC4 and AC5 (class NO_LOAD_FPU_REGS) require an 1448 intermediate register (AC0-AC3: LOAD_FPU_REGS). Everything else 1449 can be loade/stored directly. */ 1450 static reg_class_t 1451 pdp11_secondary_reload (bool in_p ATTRIBUTE_UNUSED, 1452 rtx x, 1453 reg_class_t reload_class, 1454 machine_mode reload_mode ATTRIBUTE_UNUSED, 1455 secondary_reload_info *sri ATTRIBUTE_UNUSED) 1456 { 1457 if (reload_class != NO_LOAD_FPU_REGS || GET_CODE (x) != REG || 1458 REGNO_REG_CLASS (REGNO (x)) == LOAD_FPU_REGS) 1459 return NO_REGS; 1460 1461 return LOAD_FPU_REGS; 1462 } 1463 1464 /* Implement TARGET_SECONDARY_MEMORY_NEEDED. 1465 1466 The answer is yes if we're going between general register and FPU 1467 registers. The mode doesn't matter in making this check. 1468 */ 1469 static bool 1470 pdp11_secondary_memory_needed (machine_mode, reg_class_t c1, reg_class_t c2) 1471 { 1472 int fromfloat = (c1 == LOAD_FPU_REGS || c1 == NO_LOAD_FPU_REGS || 1473 c1 == FPU_REGS); 1474 int tofloat = (c2 == LOAD_FPU_REGS || c2 == NO_LOAD_FPU_REGS || 1475 c2 == FPU_REGS); 1476 1477 return (fromfloat != tofloat); 1478 } 1479 1480 /* TARGET_LEGITIMATE_ADDRESS_P recognizes an RTL expression 1481 that is a valid memory address for an instruction. 1482 The MODE argument is the machine mode for the MEM expression 1483 that wants to use this address. 1484 1485 */ 1486 1487 static bool 1488 pdp11_legitimate_address_p (machine_mode mode, 1489 rtx operand, bool strict) 1490 { 1491 rtx xfoob; 1492 1493 /* accept @#address */ 1494 if (CONSTANT_ADDRESS_P (operand)) 1495 return true; 1496 1497 switch (GET_CODE (operand)) 1498 { 1499 case REG: 1500 /* accept (R0) */ 1501 return !strict || REGNO_OK_FOR_BASE_P (REGNO (operand)); 1502 1503 case PLUS: 1504 /* accept X(R0) */ 1505 return GET_CODE (XEXP (operand, 0)) == REG 1506 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))) 1507 && CONSTANT_ADDRESS_P (XEXP (operand, 1)); 1508 1509 case PRE_DEC: 1510 /* accept -(R0) */ 1511 return GET_CODE (XEXP (operand, 0)) == REG 1512 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))); 1513 1514 case POST_INC: 1515 /* accept (R0)+ */ 1516 return GET_CODE (XEXP (operand, 0)) == REG 1517 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (operand, 0)))); 1518 1519 case PRE_MODIFY: 1520 /* accept -(SP) -- which uses PRE_MODIFY for byte mode */ 1521 return GET_CODE (XEXP (operand, 0)) == REG 1522 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM 1523 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS 1524 && GET_CODE (XEXP (xfoob, 0)) == REG 1525 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM 1526 && CONSTANT_P (XEXP (xfoob, 1)) 1527 && INTVAL (XEXP (xfoob,1)) == -2; 1528 1529 case POST_MODIFY: 1530 /* accept (SP)+ -- which uses POST_MODIFY for byte mode */ 1531 return GET_CODE (XEXP (operand, 0)) == REG 1532 && REGNO (XEXP (operand, 0)) == STACK_POINTER_REGNUM 1533 && GET_CODE ((xfoob = XEXP (operand, 1))) == PLUS 1534 && GET_CODE (XEXP (xfoob, 0)) == REG 1535 && REGNO (XEXP (xfoob, 0)) == STACK_POINTER_REGNUM 1536 && CONSTANT_P (XEXP (xfoob, 1)) 1537 && INTVAL (XEXP (xfoob,1)) == 2; 1538 1539 case MEM: 1540 /* handle another level of indirection ! */ 1541 xfoob = XEXP (operand, 0); 1542 1543 /* (MEM:xx (MEM:xx ())) is not valid for SI, DI and currently 1544 also forbidden for float, because we have to handle this 1545 in output_move_double and/or output_move_quad() - we could 1546 do it, but currently it's not worth it!!! 1547 now that DFmode cannot go into CPU register file, 1548 maybe I should allow float ... 1549 but then I have to handle memory-to-memory moves in movdf ?? */ 1550 if (GET_MODE_BITSIZE(mode) > 16) 1551 return false; 1552 1553 /* accept @address */ 1554 if (CONSTANT_ADDRESS_P (xfoob)) 1555 return true; 1556 1557 switch (GET_CODE (xfoob)) 1558 { 1559 case REG: 1560 /* accept @(R0) - which is @0(R0) */ 1561 return !strict || REGNO_OK_FOR_BASE_P(REGNO (xfoob)); 1562 1563 case PLUS: 1564 /* accept @X(R0) */ 1565 return GET_CODE (XEXP (xfoob, 0)) == REG 1566 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))) 1567 && CONSTANT_ADDRESS_P (XEXP (xfoob, 1)); 1568 1569 case PRE_DEC: 1570 /* accept @-(R0) */ 1571 return GET_CODE (XEXP (xfoob, 0)) == REG 1572 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))); 1573 1574 case POST_INC: 1575 /* accept @(R0)+ */ 1576 return GET_CODE (XEXP (xfoob, 0)) == REG 1577 && (!strict || REGNO_OK_FOR_BASE_P (REGNO (XEXP (xfoob, 0)))); 1578 1579 default: 1580 /* anything else is invalid */ 1581 return false; 1582 } 1583 1584 default: 1585 /* anything else is invalid */ 1586 return false; 1587 } 1588 } 1589 1590 /* Return the class number of the smallest class containing 1591 reg number REGNO. */ 1592 enum reg_class 1593 pdp11_regno_reg_class (int regno) 1594 { 1595 if (regno == FRAME_POINTER_REGNUM || regno == ARG_POINTER_REGNUM) 1596 return GENERAL_REGS; 1597 else if (regno > AC3_REGNUM) 1598 return NO_LOAD_FPU_REGS; 1599 else if (regno >= AC0_REGNUM) 1600 return LOAD_FPU_REGS; 1601 else if (regno & 1) 1602 return MUL_REGS; 1603 else 1604 return GENERAL_REGS; 1605 } 1606 1607 1608 int 1609 pdp11_sp_frame_offset (void) 1610 { 1611 int offset = 0, regno; 1612 offset = get_frame_size(); 1613 for (regno = 0; regno <= PC_REGNUM; regno++) 1614 if (pdp11_saved_regno (regno)) 1615 offset += 2; 1616 for (regno = AC0_REGNUM; regno <= AC5_REGNUM; regno++) 1617 if (pdp11_saved_regno (regno)) 1618 offset += 8; 1619 1620 return offset; 1621 } 1622 1623 /* Return the offset between two registers, one to be eliminated, and the other 1624 its replacement, at the start of a routine. */ 1625 1626 int 1627 pdp11_initial_elimination_offset (int from, int to) 1628 { 1629 int spoff; 1630 1631 if (from == ARG_POINTER_REGNUM && to == HARD_FRAME_POINTER_REGNUM) 1632 return 4; 1633 else if (from == FRAME_POINTER_REGNUM 1634 && to == HARD_FRAME_POINTER_REGNUM) 1635 return 0; 1636 else 1637 { 1638 gcc_assert (to == STACK_POINTER_REGNUM); 1639 1640 /* Get the size of the register save area. */ 1641 spoff = pdp11_sp_frame_offset (); 1642 if (from == FRAME_POINTER_REGNUM) 1643 return spoff; 1644 1645 gcc_assert (from == ARG_POINTER_REGNUM); 1646 1647 /* If there is a frame pointer, that is saved too. */ 1648 if (frame_pointer_needed) 1649 spoff += 2; 1650 1651 /* Account for the saved PC in the function call. */ 1652 return spoff + 2; 1653 } 1654 } 1655 1656 /* A copy of output_addr_const modified for pdp11 expression syntax. 1657 output_addr_const also gets called for %cDIGIT and %nDIGIT, which we don't 1658 use, and for debugging output, which we don't support with this port either. 1659 So this copy should get called whenever needed. 1660 */ 1661 void 1662 output_addr_const_pdp11 (FILE *file, rtx x) 1663 { 1664 char buf[256]; 1665 int i; 1666 1667 restart: 1668 switch (GET_CODE (x)) 1669 { 1670 case PC: 1671 gcc_assert (flag_pic); 1672 putc ('.', file); 1673 break; 1674 1675 case SYMBOL_REF: 1676 assemble_name (file, XSTR (x, 0)); 1677 break; 1678 1679 case LABEL_REF: 1680 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (XEXP (x, 0))); 1681 assemble_name (file, buf); 1682 break; 1683 1684 case CODE_LABEL: 1685 ASM_GENERATE_INTERNAL_LABEL (buf, "L", CODE_LABEL_NUMBER (x)); 1686 assemble_name (file, buf); 1687 break; 1688 1689 case CONST_INT: 1690 i = INTVAL (x); 1691 if (i < 0) 1692 { 1693 i = -i; 1694 fprintf (file, "-"); 1695 } 1696 fprintf (file, "%#o", i & 0xffff); 1697 break; 1698 1699 case CONST: 1700 /* This used to output parentheses around the expression, 1701 but that does not work on the 386 (either ATT or BSD assembler). */ 1702 output_addr_const_pdp11 (file, XEXP (x, 0)); 1703 break; 1704 1705 case CONST_DOUBLE: 1706 if (GET_MODE (x) == VOIDmode) 1707 { 1708 /* We can use %o if the number is one word and positive. */ 1709 gcc_assert (!CONST_DOUBLE_HIGH (x)); 1710 fprintf (file, "%#ho", (unsigned short) CONST_DOUBLE_LOW (x)); 1711 } 1712 else 1713 /* We can't handle floating point constants; 1714 PRINT_OPERAND must handle them. */ 1715 output_operand_lossage ("floating constant misused"); 1716 break; 1717 1718 case PLUS: 1719 /* Some assemblers need integer constants to appear last (e.g. masm). */ 1720 if (GET_CODE (XEXP (x, 0)) == CONST_INT) 1721 { 1722 output_addr_const_pdp11 (file, XEXP (x, 1)); 1723 if (INTVAL (XEXP (x, 0)) >= 0) 1724 fprintf (file, "+"); 1725 output_addr_const_pdp11 (file, XEXP (x, 0)); 1726 } 1727 else 1728 { 1729 output_addr_const_pdp11 (file, XEXP (x, 0)); 1730 if (INTVAL (XEXP (x, 1)) >= 0) 1731 fprintf (file, "+"); 1732 output_addr_const_pdp11 (file, XEXP (x, 1)); 1733 } 1734 break; 1735 1736 case MINUS: 1737 /* Avoid outputting things like x-x or x+5-x, 1738 since some assemblers can't handle that. */ 1739 x = simplify_subtraction (x); 1740 if (GET_CODE (x) != MINUS) 1741 goto restart; 1742 1743 output_addr_const_pdp11 (file, XEXP (x, 0)); 1744 if (GET_CODE (XEXP (x, 1)) != CONST_INT 1745 || INTVAL (XEXP (x, 1)) >= 0) 1746 fprintf (file, "-"); 1747 output_addr_const_pdp11 (file, XEXP (x, 1)); 1748 break; 1749 1750 case ZERO_EXTEND: 1751 case SIGN_EXTEND: 1752 output_addr_const_pdp11 (file, XEXP (x, 0)); 1753 break; 1754 1755 default: 1756 output_operand_lossage ("invalid expression as operand"); 1757 } 1758 } 1759 1760 /* Worker function for TARGET_RETURN_IN_MEMORY. */ 1761 1762 static bool 1763 pdp11_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 1764 { 1765 /* Integers 32 bits and under, and scalar floats (if FPU), are returned 1766 in registers. The rest go into memory. */ 1767 return (TYPE_MODE (type) == DImode 1768 || (FLOAT_MODE_P (TYPE_MODE (type)) && ! TARGET_AC0) 1769 || TREE_CODE (type) == VECTOR_TYPE 1770 || COMPLEX_MODE_P (TYPE_MODE (type))); 1771 } 1772 1773 /* Worker function for TARGET_FUNCTION_VALUE. 1774 1775 On the pdp11 the value is found in R0 (or ac0??? not without FPU!!!! ) */ 1776 1777 static rtx 1778 pdp11_function_value (const_tree valtype, 1779 const_tree fntype_or_decl ATTRIBUTE_UNUSED, 1780 bool outgoing ATTRIBUTE_UNUSED) 1781 { 1782 return gen_rtx_REG (TYPE_MODE (valtype), 1783 BASE_RETURN_VALUE_REG(TYPE_MODE(valtype))); 1784 } 1785 1786 /* Worker function for TARGET_LIBCALL_VALUE. */ 1787 1788 static rtx 1789 pdp11_libcall_value (machine_mode mode, 1790 const_rtx fun ATTRIBUTE_UNUSED) 1791 { 1792 return gen_rtx_REG (mode, BASE_RETURN_VALUE_REG(mode)); 1793 } 1794 1795 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. 1796 1797 On the pdp, the first "output" reg is the only register thus used. 1798 1799 maybe ac0 ? - as option someday! */ 1800 1801 static bool 1802 pdp11_function_value_regno_p (const unsigned int regno) 1803 { 1804 return (regno == RETVAL_REGNUM) || (TARGET_AC0 && (regno == AC0_REGNUM)); 1805 } 1806 1807 /* Worker function for TARGET_TRAMPOLINE_INIT. 1808 1809 trampoline - how should i do it in separate i+d ? 1810 have some allocate_trampoline magic??? 1811 1812 the following should work for shared I/D: 1813 1814 MOV #STATIC, $4 01270Y 0x0000 <- STATIC; Y = STATIC_CHAIN_REGNUM 1815 JMP @#FUNCTION 000137 0x0000 <- FUNCTION 1816 */ 1817 1818 static void 1819 pdp11_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 1820 { 1821 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 1822 rtx mem; 1823 1824 gcc_assert (!TARGET_SPLIT); 1825 1826 mem = adjust_address (m_tramp, HImode, 0); 1827 emit_move_insn (mem, GEN_INT (012700+STATIC_CHAIN_REGNUM)); 1828 mem = adjust_address (m_tramp, HImode, 2); 1829 emit_move_insn (mem, chain_value); 1830 mem = adjust_address (m_tramp, HImode, 4); 1831 emit_move_insn (mem, GEN_INT (000137)); 1832 emit_move_insn (mem, fnaddr); 1833 } 1834 1835 /* Worker function for TARGET_FUNCTION_ARG. 1836 1837 Determine where to put an argument to a function. 1838 Value is zero to push the argument on the stack, 1839 or a hard register in which to store the argument. 1840 1841 MODE is the argument's machine mode. 1842 TYPE is the data type of the argument (as a tree). 1843 This is null for libcalls where that information may 1844 not be available. 1845 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1846 the preceding args and about the function being called. 1847 NAMED is nonzero if this argument is a named parameter 1848 (otherwise it is an extra parameter matching an ellipsis). */ 1849 1850 static rtx 1851 pdp11_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED, 1852 machine_mode mode ATTRIBUTE_UNUSED, 1853 const_tree type ATTRIBUTE_UNUSED, 1854 bool named ATTRIBUTE_UNUSED) 1855 { 1856 return NULL_RTX; 1857 } 1858 1859 /* Worker function for TARGET_FUNCTION_ARG_ADVANCE. 1860 1861 Update the data in CUM to advance over an argument of mode MODE and 1862 data type TYPE. (TYPE is null for libcalls where that information 1863 may not be available.) */ 1864 1865 static void 1866 pdp11_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, 1867 const_tree type, bool named ATTRIBUTE_UNUSED) 1868 { 1869 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1870 1871 *cum += (mode != BLKmode 1872 ? GET_MODE_SIZE (mode) 1873 : int_size_in_bytes (type)); 1874 } 1875 1876 /* Make sure everything's fine if we *don't* have an FPU. 1877 This assumes that putting a register in fixed_regs will keep the 1878 compiler's mitts completely off it. We don't bother to zero it out 1879 of register classes. Also fix incompatible register naming with 1880 the UNIX assembler. */ 1881 1882 static void 1883 pdp11_conditional_register_usage (void) 1884 { 1885 int i; 1886 HARD_REG_SET x; 1887 if (!TARGET_FPU) 1888 { 1889 COPY_HARD_REG_SET (x, reg_class_contents[(int)FPU_REGS]); 1890 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++ ) 1891 if (TEST_HARD_REG_BIT (x, i)) 1892 fixed_regs[i] = call_used_regs[i] = 1; 1893 } 1894 1895 if (TARGET_AC0) 1896 call_used_regs[AC0_REGNUM] = 1; 1897 if (TARGET_UNIX_ASM) 1898 { 1899 /* Change names of FPU registers for the UNIX assembler. */ 1900 reg_names[8] = "fr0"; 1901 reg_names[9] = "fr1"; 1902 reg_names[10] = "fr2"; 1903 reg_names[11] = "fr3"; 1904 reg_names[12] = "fr4"; 1905 reg_names[13] = "fr5"; 1906 } 1907 } 1908 1909 static section * 1910 pdp11_function_section (tree decl ATTRIBUTE_UNUSED, 1911 enum node_frequency freq ATTRIBUTE_UNUSED, 1912 bool startup ATTRIBUTE_UNUSED, 1913 bool exit ATTRIBUTE_UNUSED) 1914 { 1915 return NULL; 1916 } 1917 1918 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ 1919 1920 static bool 1921 pdp11_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 1922 { 1923 return GET_CODE (x) != CONST_DOUBLE || legitimate_const_double_p (x); 1924 } 1925 1926 /* Implement TARGET_SCALAR_MODE_SUPPORTED_P. */ 1927 1928 static bool 1929 pdp11_scalar_mode_supported_p (scalar_mode mode) 1930 { 1931 /* Support SFmode even with -mfloat64. */ 1932 if (mode == SFmode) 1933 return true; 1934 return default_scalar_mode_supported_p (mode); 1935 } 1936 1937 int 1938 pdp11_branch_cost () 1939 { 1940 return (TARGET_BRANCH_CHEAP ? 0 : 1); 1941 } 1942 1943 /* Implement TARGET_HARD_REGNO_NREGS. */ 1944 1945 static unsigned int 1946 pdp11_hard_regno_nregs (unsigned int regno, machine_mode mode) 1947 { 1948 if (regno <= PC_REGNUM) 1949 return CEIL (GET_MODE_SIZE (mode), UNITS_PER_WORD); 1950 return 1; 1951 } 1952 1953 /* Implement TARGET_HARD_REGNO_MODE_OK. On the pdp, the cpu registers 1954 can hold any mode other than float (because otherwise we may end up 1955 being asked to move from CPU to FPU register, which isn't a valid 1956 operation on the PDP11). For CPU registers, check alignment. 1957 1958 FPU accepts SF and DF but actually holds a DF - simplifies life! */ 1959 1960 static bool 1961 pdp11_hard_regno_mode_ok (unsigned int regno, machine_mode mode) 1962 { 1963 if (regno <= PC_REGNUM) 1964 return (GET_MODE_BITSIZE (mode) <= 16 1965 || (GET_MODE_BITSIZE (mode) >= 32 1966 && !(regno & 1) 1967 && !FLOAT_MODE_P (mode))); 1968 1969 return FLOAT_MODE_P (mode); 1970 } 1971 1972 /* Implement TARGET_MODES_TIEABLE_P. */ 1973 1974 static bool 1975 pdp11_modes_tieable_p (machine_mode, machine_mode) 1976 { 1977 return false; 1978 } 1979 1980 /* Implement PUSH_ROUNDING. On the pdp11, the stack is on an even 1981 boundary. */ 1982 1983 poly_int64 1984 pdp11_push_rounding (poly_int64 bytes) 1985 { 1986 return (bytes + 1) & ~1; 1987 } 1988 1989 struct gcc_target targetm = TARGET_INITIALIZER; 1990