1 /* Definitions of target machine of Andes NDS32 cpu for GNU compiler 2 Copyright (C) 2012-2018 Free Software Foundation, Inc. 3 Contributed by Andes Technology Corporation. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 22 /* ------------------------------------------------------------------------ */ 23 24 /* The following are auxiliary macros or structure declarations 25 that are used all over the nds32.c and nds32.h. */ 26 27 #define ADJUST_INSN_LENGTH(INSN, LENGTH) \ 28 (LENGTH = nds32_adjust_insn_length (INSN, LENGTH)) 29 30 /* Use SYMBOL_FLAG_MACH_DEP to define our own symbol_ref flag. 31 It is used in nds32_encode_section_info() to store flag in symbol_ref 32 in case the symbol should be placed in .rodata section. 33 So that we can check it in nds32_legitimate_address_p(). */ 34 #define NDS32_SYMBOL_FLAG_RODATA \ 35 (SYMBOL_FLAG_MACH_DEP << 0) 36 #define NDS32_SYMBOL_REF_RODATA_P(x) \ 37 ((SYMBOL_REF_FLAGS (x) & NDS32_SYMBOL_FLAG_RODATA) != 0) 38 39 /* Classifies expand result for expand helper function. */ 40 enum nds32_expand_result_type 41 { 42 EXPAND_DONE, 43 EXPAND_FAIL, 44 EXPAND_CREATE_TEMPLATE 45 }; 46 47 /* Classifies address type to distinguish 16-bit/32-bit format. */ 48 enum nds32_16bit_address_type 49 { 50 /* [reg]: 45 format address. */ 51 ADDRESS_REG, 52 /* [lo_reg + imm3u]: 333 format address. */ 53 ADDRESS_LO_REG_IMM3U, 54 /* post_inc [lo_reg + imm3u]: 333 format address. */ 55 ADDRESS_POST_INC_LO_REG_IMM3U, 56 /* post_modify [lo_reg + imm3u]: 333 format address. */ 57 ADDRESS_POST_MODIFY_LO_REG_IMM3U, 58 /* [$r8 + imm7u]: r8 imply address. */ 59 ADDRESS_R8_IMM7U, 60 /* [$fp + imm7u]: fp imply address. */ 61 ADDRESS_FP_IMM7U, 62 /* [$sp + imm7u]: sp imply address. */ 63 ADDRESS_SP_IMM7U, 64 /* Other address format. */ 65 ADDRESS_NOT_16BIT_FORMAT 66 }; 67 68 69 /* ------------------------------------------------------------------------ */ 70 71 /* Define maximum numbers of registers for passing arguments. */ 72 #define NDS32_MAX_GPR_REGS_FOR_ARGS 6 73 #define NDS32_MAX_FPR_REGS_FOR_ARGS 6 74 75 /* Define the register number for first argument. */ 76 #define NDS32_GPR_ARG_FIRST_REGNUM 0 77 #define NDS32_FPR_ARG_FIRST_REGNUM 34 78 79 /* Define the register number for return value. */ 80 #define NDS32_GPR_RET_FIRST_REGNUM 0 81 #define NDS32_FPR_RET_FIRST_REGNUM 34 82 83 /* Define the first integer register number. */ 84 #define NDS32_FIRST_GPR_REGNUM 0 85 /* Define the last integer register number. */ 86 #define NDS32_LAST_GPR_REGNUM 31 87 88 #define NDS32_FIRST_CALLEE_SAVE_GPR_REGNUM 6 89 #define NDS32_LAST_CALLEE_SAVE_GPR_REGNUM \ 90 (TARGET_REDUCED_REGS ? 10 : 14) 91 92 /* Define the floating-point number of registers. */ 93 #define NDS32_FLOAT_REGISTER_NUMBER \ 94 (((nds32_fp_regnum == NDS32_CONFIG_FPU_0) \ 95 || (nds32_fp_regnum == NDS32_CONFIG_FPU_4)) ? 8 \ 96 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_1) \ 97 || (nds32_fp_regnum == NDS32_CONFIG_FPU_5)) ? 16 \ 98 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_2) \ 99 || (nds32_fp_regnum == NDS32_CONFIG_FPU_6)) ? 32 \ 100 : ((nds32_fp_regnum == NDS32_CONFIG_FPU_3) \ 101 || (nds32_fp_regnum == NDS32_CONFIG_FPU_7)) ? 64 \ 102 : 32) 103 104 #define NDS32_EXT_FPU_DOT_E (nds32_fp_regnum >= 4) 105 106 /* Define the first floating-point register number. */ 107 #define NDS32_FIRST_FPR_REGNUM 34 108 /* Define the last floating-point register number. */ 109 #define NDS32_LAST_FPR_REGNUM \ 110 (NDS32_FIRST_FPR_REGNUM + NDS32_FLOAT_REGISTER_NUMBER - 1) 111 112 113 #define NDS32_IS_EXT_FPR_REGNUM(regno) \ 114 (((regno) >= NDS32_FIRST_FPR_REGNUM + 32) \ 115 && ((regno) < NDS32_FIRST_FPR_REGNUM + 64)) 116 117 #define NDS32_IS_FPR_REGNUM(regno) \ 118 (((regno) >= NDS32_FIRST_FPR_REGNUM) \ 119 && ((regno) <= NDS32_LAST_FPR_REGNUM)) 120 121 #define NDS32_FPR_REGNO_OK_FOR_SINGLE(regno) \ 122 ((regno) <= NDS32_LAST_FPR_REGNUM) 123 124 #define NDS32_FPR_REGNO_OK_FOR_DOUBLE(regno) \ 125 ((((regno) - NDS32_FIRST_FPR_REGNUM) & 1) == 0) 126 127 #define NDS32_IS_GPR_REGNUM(regno) \ 128 (((regno) <= NDS32_LAST_GPR_REGNUM)) 129 130 /* Define double word alignment bits. */ 131 #define NDS32_DOUBLE_WORD_ALIGNMENT 64 132 133 /* Define alignment checking macros for convenience. */ 134 #define NDS32_HALF_WORD_ALIGN_P(value) (((value) & 0x01) == 0) 135 #define NDS32_SINGLE_WORD_ALIGN_P(value) (((value) & 0x03) == 0) 136 #define NDS32_DOUBLE_WORD_ALIGN_P(value) (((value) & 0x07) == 0) 137 138 /* Determine whether we would like to have code generation strictly aligned. 139 We set it strictly aligned when -malways-align is enabled. 140 Check gcc/common/config/nds32/nds32-common.c for the optimizations that 141 apply -malways-align. */ 142 #define NDS32_ALIGN_P() (TARGET_ALWAYS_ALIGN) 143 /* Get alignment according to mode or type information. 144 When 'type' is nonnull, there is no need to look at 'mode'. */ 145 #define NDS32_MODE_TYPE_ALIGN(mode, type) \ 146 (type ? TYPE_ALIGN (type) : GET_MODE_ALIGNMENT (mode)) 147 148 /* Round X up to the nearest double word. */ 149 #define NDS32_ROUND_UP_DOUBLE_WORD(value) (((value) + 7) & ~7) 150 151 152 /* This macro is used to calculate the numbers of registers for 153 containing 'size' bytes of the argument. 154 The size of a register is a word in nds32 target. 155 So we use UNITS_PER_WORD to do the calculation. */ 156 #define NDS32_NEED_N_REGS_FOR_ARG(mode, type) \ 157 ((mode == BLKmode) \ 158 ? ((int_size_in_bytes (type) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) \ 159 : ((GET_MODE_SIZE (mode) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 160 161 /* This macro is used to return the register number for passing argument. 162 We need to obey the following rules: 163 1. If it is required MORE THAN one register, 164 we need to further check if it really needs to be 165 aligned on double words. 166 a) If double word alignment is necessary, 167 the register number must be even value. 168 b) Otherwise, the register number can be odd or even value. 169 2. If it is required ONLY one register, 170 the register number can be odd or even value. */ 171 #define NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG(reg_offset, mode, type) \ 172 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \ 173 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \ 174 ? (((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM + 1) & ~1) \ 175 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) \ 176 : ((reg_offset) + NDS32_GPR_ARG_FIRST_REGNUM)) 177 178 #define NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG(reg_offset, mode, type) \ 179 ((NDS32_NEED_N_REGS_FOR_ARG (mode, type) > 1) \ 180 ? ((NDS32_MODE_TYPE_ALIGN (mode, type) > PARM_BOUNDARY) \ 181 ? (((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM + 1) & ~1) \ 182 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM)) \ 183 : ((reg_offset) + NDS32_FPR_ARG_FIRST_REGNUM)) 184 185 /* These two macros are to check if there are still available registers 186 for passing argument, which must be entirely in registers. */ 187 #define NDS32_ARG_ENTIRE_IN_GPR_REG_P(reg_offset, mode, type) \ 188 ((NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \ 189 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \ 190 <= (NDS32_GPR_ARG_FIRST_REGNUM \ 191 + NDS32_MAX_GPR_REGS_FOR_ARGS)) 192 193 #define NDS32_ARG_ENTIRE_IN_FPR_REG_P(reg_offset, mode, type) \ 194 ((NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \ 195 + NDS32_NEED_N_REGS_FOR_ARG (mode, type)) \ 196 <= (NDS32_FPR_ARG_FIRST_REGNUM \ 197 + NDS32_MAX_FPR_REGS_FOR_ARGS)) 198 199 /* These two macros are to check if there are still available registers 200 for passing argument, either entirely in registers or partially 201 in registers. */ 202 #define NDS32_ARG_PARTIAL_IN_GPR_REG_P(reg_offset, mode, type) \ 203 (NDS32_AVAILABLE_REGNUM_FOR_GPR_ARG (reg_offset, mode, type) \ 204 < NDS32_GPR_ARG_FIRST_REGNUM + NDS32_MAX_GPR_REGS_FOR_ARGS) 205 206 #define NDS32_ARG_PARTIAL_IN_FPR_REG_P(reg_offset, mode, type) \ 207 (NDS32_AVAILABLE_REGNUM_FOR_FPR_ARG (reg_offset, mode, type) \ 208 < NDS32_FPR_ARG_FIRST_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS) 209 210 /* This macro is to check if the register is required to be saved on stack. 211 If call_used_regs[regno] == 0, regno is the callee-saved register. 212 If df_regs_ever_live_p(regno) == true, it is used in the current function. 213 As long as the register satisfies both criteria above, 214 it is required to be saved. */ 215 #define NDS32_REQUIRED_CALLEE_SAVED_P(regno) \ 216 ((!call_used_regs[regno]) && (df_regs_ever_live_p (regno))) 217 218 /* This macro is to check if the push25/pop25 are available to be used 219 for code generation. Because pop25 also performs return behavior, 220 the instructions may not be available for some cases. 221 If we want to use push25/pop25, all the following conditions must 222 be satisfied: 223 1. TARGET_V3PUSH is set. 224 2. Current function is not an ISR function. 225 3. Current function is not a variadic function.*/ 226 #define NDS32_V3PUSH_AVAILABLE_P \ 227 (TARGET_V3PUSH \ 228 && !nds32_isr_function_p (current_function_decl) \ 229 && (cfun->machine->va_args_size == 0)) 230 231 /* ------------------------------------------------------------------------ */ 232 233 /* A C structure for machine-specific, per-function data. 234 This is added to the cfun structure. */ 235 struct GTY(()) machine_function 236 { 237 /* Number of bytes allocated on the stack for variadic args 238 if we want to push them into stack as pretend arguments by ourself. */ 239 int va_args_size; 240 /* Number of bytes reserved on the stack for 241 local and temporary variables. */ 242 int local_size; 243 /* Number of bytes allocated on the stack for outgoing arguments. */ 244 int out_args_size; 245 246 /* Number of bytes on the stack for saving $fp. */ 247 int fp_size; 248 /* Number of bytes on the stack for saving $gp. */ 249 int gp_size; 250 /* Number of bytes on the stack for saving $lp. */ 251 int lp_size; 252 253 /* Number of bytes on the stack for saving general purpose 254 callee-saved registers. */ 255 int callee_saved_gpr_regs_size; 256 257 /* Number of bytes on the stack for saving floating-point 258 callee-saved registers. */ 259 int callee_saved_fpr_regs_size; 260 261 /* The padding bytes in callee-saved area may be required. */ 262 int callee_saved_area_gpr_padding_bytes; 263 264 /* The first required general purpose callee-saved register. */ 265 int callee_saved_first_gpr_regno; 266 /* The last required general purpose callee-saved register. */ 267 int callee_saved_last_gpr_regno; 268 269 /* The first required floating-point callee-saved register. */ 270 int callee_saved_first_fpr_regno; 271 /* The last required floating-point callee-saved register. */ 272 int callee_saved_last_fpr_regno; 273 274 /* The padding bytes in varargs area may be required. */ 275 int va_args_area_padding_bytes; 276 277 /* The first required register that should be saved on stack for va_args. */ 278 int va_args_first_regno; 279 /* The last required register that should be saved on stack for va_args. */ 280 int va_args_last_regno; 281 282 /* Number of bytes on the stack for saving exception handling registers. */ 283 int eh_return_data_regs_size; 284 /* The first register of passing exception handling information. */ 285 int eh_return_data_first_regno; 286 /* The last register of passing exception handling information. */ 287 int eh_return_data_last_regno; 288 289 /* Indicate that whether this function 290 calls __builtin_eh_return. */ 291 int use_eh_return_p; 292 293 /* Indicate that whether this function needs 294 prologue/epilogue code generation. */ 295 int naked_p; 296 /* Indicate that whether this function 297 uses fp_as_gp optimization. */ 298 int fp_as_gp_p; 299 /* Indicate that whether this function is under strictly aligned 300 situation for legitimate address checking. This flag informs 301 nds32_legitimate_address_p() how to treat offset alignment: 302 1. The IVOPT phase needs to detect available range for memory access, 303 such as checking [base + 32767] ~ [base + (-32768)]. 304 For this case we do not want address to be strictly aligned. 305 2. The rtl lowering and optimization are close to target code. 306 For this case we need address to be strictly aligned. */ 307 int strict_aligned_p; 308 }; 309 310 /* A C structure that contains the arguments information. */ 311 typedef struct 312 { 313 unsigned int gpr_offset; 314 unsigned int fpr_offset; 315 } nds32_cumulative_args; 316 317 /* ------------------------------------------------------------------------ */ 318 319 /* The following we define C-ISR related stuff. 320 In nds32 architecture, we have 73 vectors for interrupt/exception. 321 For each vector (except for vector 0, which is used for reset behavior), 322 we allow users to set its register saving scheme and interrupt level. */ 323 324 /* There are 73 vectors in nds32 architecture. 325 0 for reset handler, 326 1-8 for exception handler, 327 and 9-72 for interrupt handler. 328 We use an array, which is defined in nds32.c, to record 329 essential information for each vector. */ 330 #define NDS32_N_ISR_VECTORS 73 331 332 /* Define possible isr category. */ 333 enum nds32_isr_category 334 { 335 NDS32_ISR_NONE, 336 NDS32_ISR_INTERRUPT, 337 NDS32_ISR_EXCEPTION, 338 NDS32_ISR_RESET 339 }; 340 341 /* Define isr register saving scheme. */ 342 enum nds32_isr_save_reg 343 { 344 NDS32_SAVE_ALL, 345 NDS32_PARTIAL_SAVE 346 }; 347 348 /* Define isr nested type. */ 349 enum nds32_isr_nested_type 350 { 351 NDS32_NESTED, 352 NDS32_NOT_NESTED, 353 NDS32_NESTED_READY 354 }; 355 356 /* Define structure to record isr information. 357 The isr vector array 'isr_vectors[]' with this structure 358 is defined in nds32.c. */ 359 struct nds32_isr_info 360 { 361 /* The field to identify isr category. 362 It should be set to NDS32_ISR_NONE by default. 363 If user specifies a function as isr by using attribute, 364 this field will be set accordingly. */ 365 enum nds32_isr_category category; 366 367 /* A string for the applied function name. 368 It should be set to empty string by default. */ 369 char func_name[100]; 370 371 /* The register saving scheme. 372 It should be set to NDS32_PARTIAL_SAVE by default 373 unless user specifies attribute to change it. */ 374 enum nds32_isr_save_reg save_reg; 375 376 /* The nested type. 377 It should be set to NDS32_NOT_NESTED by default 378 unless user specifies attribute to change it. */ 379 enum nds32_isr_nested_type nested_type; 380 381 /* Total vectors. 382 The total vectors = interrupt + exception numbers + reset. 383 It should be set to 0 by default. 384 This field is ONLY used in NDS32_ISR_RESET category. */ 385 unsigned int total_n_vectors; 386 387 /* A string for nmi handler name. 388 It should be set to empty string by default. 389 This field is ONLY used in NDS32_ISR_RESET category. */ 390 char nmi_name[100]; 391 392 /* A string for warm handler name. 393 It should be set to empty string by default. 394 This field is ONLY used in NDS32_ISR_RESET category. */ 395 char warm_name[100]; 396 }; 397 398 /* ------------------------------------------------------------------------ */ 399 400 /* Define code for all nds32 builtins. */ 401 enum nds32_builtins 402 { 403 NDS32_BUILTIN_ISYNC, 404 NDS32_BUILTIN_ISB, 405 NDS32_BUILTIN_DSB, 406 NDS32_BUILTIN_MSYNC_ALL, 407 NDS32_BUILTIN_MSYNC_STORE, 408 NDS32_BUILTIN_MFSR, 409 NDS32_BUILTIN_MFUSR, 410 NDS32_BUILTIN_MTSR, 411 NDS32_BUILTIN_MTSR_ISB, 412 NDS32_BUILTIN_MTSR_DSB, 413 NDS32_BUILTIN_MTUSR, 414 NDS32_BUILTIN_SETGIE_EN, 415 NDS32_BUILTIN_SETGIE_DIS, 416 NDS32_BUILTIN_FMFCFG, 417 NDS32_BUILTIN_FMFCSR, 418 NDS32_BUILTIN_FMTCSR, 419 NDS32_BUILTIN_FCPYNSS, 420 NDS32_BUILTIN_FCPYSS, 421 NDS32_BUILTIN_FCPYNSD, 422 NDS32_BUILTIN_FCPYSD, 423 NDS32_BUILTIN_ABS, 424 NDS32_BUILTIN_AVE, 425 NDS32_BUILTIN_BCLR, 426 NDS32_BUILTIN_BSET, 427 NDS32_BUILTIN_BTGL, 428 NDS32_BUILTIN_BTST, 429 NDS32_BUILTIN_CLIP, 430 NDS32_BUILTIN_CLIPS, 431 NDS32_BUILTIN_CLZ, 432 NDS32_BUILTIN_CLO, 433 NDS32_BUILTIN_MAX, 434 NDS32_BUILTIN_MIN, 435 NDS32_BUILTIN_PBSAD, 436 NDS32_BUILTIN_PBSADA, 437 NDS32_BUILTIN_BSE, 438 NDS32_BUILTIN_BSP, 439 NDS32_BUILTIN_FFB, 440 NDS32_BUILTIN_FFMISM, 441 NDS32_BUILTIN_FLMISM, 442 443 NDS32_BUILTIN_ROTR, 444 NDS32_BUILTIN_SVA, 445 NDS32_BUILTIN_SVS, 446 NDS32_BUILTIN_WSBH, 447 NDS32_BUILTIN_JR_ITOFF, 448 NDS32_BUILTIN_JR_TOFF, 449 NDS32_BUILTIN_JRAL_ITON, 450 NDS32_BUILTIN_JRAL_TON, 451 NDS32_BUILTIN_RET_ITOFF, 452 NDS32_BUILTIN_RET_TOFF, 453 NDS32_BUILTIN_STANDBY_NO_WAKE_GRANT, 454 NDS32_BUILTIN_STANDBY_WAKE_GRANT, 455 NDS32_BUILTIN_STANDBY_WAKE_DONE, 456 NDS32_BUILTIN_TEQZ, 457 NDS32_BUILTIN_TNEZ, 458 NDS32_BUILTIN_TRAP, 459 NDS32_BUILTIN_SETEND_BIG, 460 NDS32_BUILTIN_SETEND_LITTLE, 461 NDS32_BUILTIN_SYSCALL, 462 NDS32_BUILTIN_BREAK, 463 NDS32_BUILTIN_NOP, 464 NDS32_BUILTIN_SCHE_BARRIER, 465 NDS32_BUILTIN_GET_CURRENT_SP, 466 NDS32_BUILTIN_SET_CURRENT_SP, 467 NDS32_BUILTIN_RETURN_ADDRESS, 468 NDS32_BUILTIN_LLW, 469 NDS32_BUILTIN_LWUP, 470 NDS32_BUILTIN_LBUP, 471 NDS32_BUILTIN_SCW, 472 NDS32_BUILTIN_SWUP, 473 NDS32_BUILTIN_SBUP, 474 NDS32_BUILTIN_CCTL_VA_LCK, 475 NDS32_BUILTIN_CCTL_IDX_WBINVAL, 476 NDS32_BUILTIN_CCTL_VA_WBINVAL_L1, 477 NDS32_BUILTIN_CCTL_VA_WBINVAL_LA, 478 NDS32_BUILTIN_CCTL_IDX_READ, 479 NDS32_BUILTIN_CCTL_IDX_WRITE, 480 NDS32_BUILTIN_CCTL_L1D_INVALALL, 481 NDS32_BUILTIN_CCTL_L1D_WBALL_ALVL, 482 NDS32_BUILTIN_CCTL_L1D_WBALL_ONE_LVL, 483 NDS32_BUILTIN_DPREF_QW, 484 NDS32_BUILTIN_DPREF_HW, 485 NDS32_BUILTIN_DPREF_W, 486 NDS32_BUILTIN_DPREF_DW, 487 NDS32_BUILTIN_TLBOP_TRD, 488 NDS32_BUILTIN_TLBOP_TWR, 489 NDS32_BUILTIN_TLBOP_RWR, 490 NDS32_BUILTIN_TLBOP_RWLK, 491 NDS32_BUILTIN_TLBOP_UNLK, 492 NDS32_BUILTIN_TLBOP_PB, 493 NDS32_BUILTIN_TLBOP_INV, 494 NDS32_BUILTIN_TLBOP_FLUA, 495 NDS32_BUILTIN_UALOAD_HW, 496 NDS32_BUILTIN_UALOAD_W, 497 NDS32_BUILTIN_UALOAD_DW, 498 NDS32_BUILTIN_UASTORE_HW, 499 NDS32_BUILTIN_UASTORE_W, 500 NDS32_BUILTIN_UASTORE_DW, 501 NDS32_BUILTIN_GIE_DIS, 502 NDS32_BUILTIN_GIE_EN, 503 NDS32_BUILTIN_ENABLE_INT, 504 NDS32_BUILTIN_DISABLE_INT, 505 NDS32_BUILTIN_SET_PENDING_SWINT, 506 NDS32_BUILTIN_CLR_PENDING_SWINT, 507 NDS32_BUILTIN_CLR_PENDING_HWINT, 508 NDS32_BUILTIN_GET_ALL_PENDING_INT, 509 NDS32_BUILTIN_GET_PENDING_INT, 510 NDS32_BUILTIN_SET_INT_PRIORITY, 511 NDS32_BUILTIN_GET_INT_PRIORITY, 512 NDS32_BUILTIN_SET_TRIG_LEVEL, 513 NDS32_BUILTIN_SET_TRIG_EDGE, 514 NDS32_BUILTIN_GET_TRIG_TYPE, 515 516 NDS32_BUILTIN_UNALIGNED_FEATURE, 517 NDS32_BUILTIN_ENABLE_UNALIGNED, 518 NDS32_BUILTIN_DISABLE_UNALIGNED, 519 NDS32_BUILTIN_COUNT 520 }; 521 522 /* ------------------------------------------------------------------------ */ 523 524 #define TARGET_ISA_V2 (nds32_arch_option == ARCH_V2) 525 526 #define TARGET_ISA_V3 \ 527 (nds32_arch_option == ARCH_V3 \ 528 || nds32_arch_option == ARCH_V3F \ 529 || nds32_arch_option == ARCH_V3S) 530 #define TARGET_ISA_V3M (nds32_arch_option == ARCH_V3M) 531 532 #define TARGET_PIPELINE_N9 \ 533 (nds32_cpu_option == CPU_N9) 534 #define TARGET_PIPELINE_SIMPLE \ 535 (nds32_cpu_option == CPU_SIMPLE) 536 537 #define TARGET_CMODEL_SMALL \ 538 (nds32_cmodel_option == CMODEL_SMALL) 539 #define TARGET_CMODEL_MEDIUM \ 540 (nds32_cmodel_option == CMODEL_MEDIUM) 541 #define TARGET_CMODEL_LARGE \ 542 (nds32_cmodel_option == CMODEL_LARGE) 543 544 /* When -mcmodel=small or -mcmodel=medium, 545 compiler may generate gp-base instruction directly. */ 546 #define TARGET_GP_DIRECT \ 547 (nds32_cmodel_option == CMODEL_SMALL\ 548 || nds32_cmodel_option == CMODEL_MEDIUM) 549 550 #define TARGET_MUL_SLOW \ 551 (nds32_mul_config == MUL_TYPE_SLOW) 552 553 /* Run-time Target Specification. */ 554 #define TARGET_SOFT_FLOAT (nds32_abi == NDS32_ABI_V2) 555 /* Use hardware floating point calling convention. */ 556 #define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS) 557 558 /* Record arch version in TARGET_ARCH_DEFAULT. 0 means soft ABI, 559 1 means hard ABI and using full floating-point instruction, 560 2 means hard ABI and only using single-precision floating-point 561 instruction */ 562 #if TARGET_ARCH_DEFAULT == 1 563 # define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS 564 # define TARGET_DEFAULT_FPU_ISA MASK_FPU_DOUBLE | MASK_FPU_SINGLE 565 # define TARGET_DEFAULT_FPU_FMA 0 566 #else 567 # if TARGET_ARCH_DEFAULT == 2 568 # define TARGET_DEFAULT_ABI NDS32_ABI_V2_FP_PLUS 569 # define TARGET_DEFAULT_FPU_ISA MASK_FPU_SINGLE 570 # define TARGET_DEFAULT_FPU_FMA 0 571 # else 572 # define TARGET_DEFAULT_ABI NDS32_ABI_V2 573 # define TARGET_DEFAULT_FPU_ISA 0 574 # define TARGET_DEFAULT_FPU_FMA 0 575 # endif 576 #endif 577 578 #define TARGET_CONFIG_FPU_DEFAULT NDS32_CONFIG_FPU_2 579 /* ------------------------------------------------------------------------ */ 580 581 /* Controlling the Compilation Driver. */ 582 583 #define OPTION_DEFAULT_SPECS \ 584 {"arch", " %{!march=*:-march=%(VALUE)}" \ 585 " %{march=v3f:%{!mfloat-abi=*:-mfloat-abi=hard}" \ 586 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}" \ 587 " %{!mno-ext-fpu-dp:%{!mext-fpu-dp:-mext-fpu-dp}}}" \ 588 " %{march=v3s:%{!mfloat-abi=*:-mfloat-abi=hard}" \ 589 " %{!mno-ext-fpu-sp:%{!mext-fpu-sp:-mext-fpu-sp}}}" }, \ 590 {"cpu", "%{!mcpu=*:-mcpu=%(VALUE)}" }, \ 591 {"float", "%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}" } 592 593 #define CC1_SPEC \ 594 "" 595 596 #define ASM_SPEC \ 597 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ 598 " %{march=*:-march=%*}" \ 599 " %{mabi=*:-mabi=v%*}" \ 600 " %{mconfig-fpu=*:-mfpu-freg=%*}" \ 601 " %{mext-fpu-mac:-mmac}" \ 602 " %{mno-ext-fpu-mac:-mno-mac}" \ 603 " %{mext-fpu-sp:-mfpu-sp-ext}" \ 604 " %{mno-ext-fpu-sp:-mno-fpu-sp-ext}" \ 605 " %{mext-fpu-dp:-mfpu-dp-ext}" \ 606 " %{mno-ext-fpu-sp:-mno-fpu-dp-ext}" 607 608 /* If user issues -mrelax, we need to pass '--relax' to linker. */ 609 #define LINK_SPEC \ 610 " %{mbig-endian:-EB} %{mlittle-endian:-EL}" \ 611 " %{mrelax:--relax}" 612 613 #define LIB_SPEC \ 614 " -lc -lgloss" 615 616 /* The option -mno-ctor-dtor can disable constructor/destructor feature 617 by applying different crt stuff. In the convention, crt0.o is the 618 startup file without constructor/destructor; 619 crt1.o, crti.o, crtbegin.o, crtend.o, and crtn.o are the 620 startup files with constructor/destructor. 621 Note that crt0.o, crt1.o, crti.o, and crtn.o are provided 622 by newlib/mculib/glibc/ublic, while crtbegin.o and crtend.o are 623 currently provided by GCC for nds32 target. 624 625 For nds32 target so far: 626 If -mno-ctor-dtor, we are going to link 627 "crt0.o [user objects]". 628 If general cases, we are going to link 629 "crt1.o crtbegin1.o [user objects] crtend1.o". */ 630 #define STARTFILE_SPEC \ 631 " %{!mno-ctor-dtor:crt1.o%s;:crt0.o%s}" \ 632 " %{!mno-ctor-dtor:crtbegin1.o%s}" 633 #define ENDFILE_SPEC \ 634 " %{!mno-ctor-dtor:crtend1.o%s}" 635 636 /* The TARGET_BIG_ENDIAN_DEFAULT is defined if we 637 configure gcc with --target=nds32be-* setting. 638 Check gcc/config.gcc for more information. */ 639 #ifdef TARGET_BIG_ENDIAN_DEFAULT 640 # define NDS32_ENDIAN_DEFAULT "mbig-endian" 641 #else 642 # define NDS32_ENDIAN_DEFAULT "mlittle-endian" 643 #endif 644 645 /* Currently we only have elf toolchain, 646 where -mcmodel=medium is always the default. */ 647 #define NDS32_CMODEL_DEFAULT "mcmodel=medium" 648 649 #define MULTILIB_DEFAULTS \ 650 { NDS32_ENDIAN_DEFAULT, NDS32_CMODEL_DEFAULT } 651 652 653 /* Run-time Target Specification. */ 654 655 #define TARGET_CPU_CPP_BUILTINS() \ 656 nds32_cpu_cpp_builtins (pfile) 657 658 659 /* Defining Data Structures for Per-function Information. */ 660 661 /* This macro is called once per function, 662 before generation of any RTL has begun. */ 663 #define INIT_EXPANDERS nds32_init_expanders () 664 665 666 /* Storage Layout. */ 667 668 #define BITS_BIG_ENDIAN 0 669 670 #define BYTES_BIG_ENDIAN (TARGET_BIG_ENDIAN) 671 672 #define WORDS_BIG_ENDIAN (TARGET_BIG_ENDIAN) 673 674 #define UNITS_PER_WORD 4 675 676 #define PROMOTE_MODE(m, unsignedp, type) \ 677 if (GET_MODE_CLASS (m) == MODE_INT && GET_MODE_SIZE (m) < UNITS_PER_WORD) \ 678 { \ 679 (m) = SImode; \ 680 } 681 682 #define PARM_BOUNDARY 32 683 684 #define STACK_BOUNDARY 64 685 686 #define FUNCTION_BOUNDARY \ 687 ((NDS32_ALIGN_P () || TARGET_ALIGN_FUNCTION) ? 32 : 16) 688 689 #define BIGGEST_ALIGNMENT 64 690 691 #define DATA_ALIGNMENT(constant, basic_align) \ 692 nds32_data_alignment (constant, basic_align) 693 694 #define LOCAL_ALIGNMENT(type, basic_align) \ 695 nds32_local_alignment (type, basic_align) 696 697 #define EMPTY_FIELD_BOUNDARY 32 698 699 #define STRUCTURE_SIZE_BOUNDARY 8 700 701 #define STRICT_ALIGNMENT 1 702 703 #define PCC_BITFIELD_TYPE_MATTERS 1 704 705 706 /* Layout of Source Language Data Types. */ 707 708 #define INT_TYPE_SIZE 32 709 #define SHORT_TYPE_SIZE 16 710 #define LONG_TYPE_SIZE 32 711 #define LONG_LONG_TYPE_SIZE 64 712 713 #define FLOAT_TYPE_SIZE 32 714 #define DOUBLE_TYPE_SIZE 64 715 #define LONG_DOUBLE_TYPE_SIZE 64 716 717 #define DEFAULT_SIGNED_CHAR 1 718 719 #define SIZE_TYPE "long unsigned int" 720 #define PTRDIFF_TYPE "long int" 721 #define WCHAR_TYPE "unsigned int" 722 #define WCHAR_TYPE_SIZE 32 723 724 725 /* Register Usage. */ 726 727 /* Number of actual hardware registers. 728 The hardware registers are assigned numbers for the compiler 729 from 0 to just below FIRST_PSEUDO_REGISTER. 730 All registers that the compiler knows about must be given numbers, 731 even those that are not normally considered general registers. */ 732 #define FIRST_PSEUDO_REGISTER 101 733 734 /* An initializer that says which registers are used for fixed 735 purposes all throughout the compiled code and are therefore 736 not available for general allocation. 737 738 $r28 : $fp 739 $r29 : $gp 740 $r30 : $lp 741 $r31 : $sp 742 743 caller-save registers: $r0 ~ $r5, $r16 ~ $r23, $fs0 ~ $fs5, $fs22 ~ $fs47 744 callee-save registers: $r6 ~ $r10, $r11 ~ $r14, $fs6 ~ $fs21, $fs48 ~ $fs63 745 746 reserved for assembler : $r15 747 reserved for other use : $r24, $r25, $r26, $r27 */ 748 #define FIXED_REGISTERS \ 749 { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \ 750 0, 0, 0, 0, 0, 0, 0, 0, \ 751 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \ 752 0, 0, 0, 0, 0, 0, 0, 1, \ 753 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \ 754 0, 0, 0, 0, 0, 0, 0, 0, \ 755 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \ 756 1, 1, 1, 1, 0, 1, 0, 1, \ 757 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \ 758 1, 1, 1, 1, 1, 1, 1, 1, \ 759 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \ 760 1, 1, 1, 1, 1, 1, 1, 1, \ 761 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \ 762 1, 1, 1, 1, 1, 1, 1, 1, \ 763 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \ 764 1, 1, 1, 1, 1, 1, 1, 1, \ 765 /* fs30 fs31 fd16 fd17 fd18 */ \ 766 1, 1, 1, 1, 1, 1, 1, 1, \ 767 /* fd19 fd20 fd21 fd22 */ \ 768 1, 1, 1, 1, 1, 1, 1, 1, \ 769 /* fd23 fd24 fd25 fd26 */ \ 770 1, 1, 1, 1, 1, 1, 1, 1, \ 771 /* fd27 fd28 fd29 fd30 */ \ 772 1, 1, 1, 1, 1, 1, 1, 1, \ 773 /* fd31 Reserved..................... */ \ 774 1, 1, 1, 1, 1 \ 775 } 776 777 /* Identifies the registers that are not available for 778 general allocation of values that must live across 779 function calls -- so they are caller-save registers. 780 781 0 : callee-save registers 782 1 : caller-save registers */ 783 #define CALL_USED_REGISTERS \ 784 { /* r0 r1 r2 r3 r4 r5 r6 r7 */ \ 785 1, 1, 1, 1, 1, 1, 0, 0, \ 786 /* r8 r9 r10 r11 r12 r13 r14 r15 */ \ 787 0, 0, 0, 0, 0, 0, 0, 1, \ 788 /* r16 r17 r18 r19 r20 r21 r22 r23 */ \ 789 1, 1, 1, 1, 1, 1, 1, 1, \ 790 /* r24 r25 r26 r27 r28 r29 r30 r31 */ \ 791 1, 1, 1, 1, 0, 1, 0, 1, \ 792 /* AP FP fs0 fs1 fs2 fs3 fs4 fs5 */ \ 793 1, 1, 1, 1, 1, 1, 1, 1, \ 794 /* fs6 fs7 fs8 fs9 fs10 fs11 fs12 fs13 */ \ 795 1, 1, 1, 1, 1, 1, 1, 1, \ 796 /* fs14 fs15 fs16 fs17 fs18 fs19 fs20 fs21 */ \ 797 1, 1, 1, 1, 1, 1, 1, 1, \ 798 /* fs22 fs23 fs24 fs25 fs26 fs27 fs28 fs29 */ \ 799 1, 1, 1, 1, 1, 1, 1, 1, \ 800 /* fs30 fs31 fd16 fd17 fd18 */ \ 801 1, 1, 1, 1, 1, 1, 1, 1, \ 802 /* fd19 fd20 fd21 fd22 */ \ 803 1, 1, 1, 1, 1, 1, 1, 1, \ 804 /* fd23 fd24 fd25 fd26 */ \ 805 1, 1, 1, 1, 1, 1, 1, 1, \ 806 /* fd27 fd28 fd29 fd30 */ \ 807 1, 1, 1, 1, 1, 1, 1, 1, \ 808 /* fd31 Reserved..................... */ \ 809 1, 1, 1, 1, 1 \ 810 } 811 812 /* In nds32 target, we have three levels of registers: 813 LOW_COST_REGS : $r0 ~ $r7 814 MIDDLE_COST_REGS : $r8 ~ $r11, $r16 ~ $r19 815 HIGH_COST_REGS : $r12 ~ $r14, $r20 ~ $r31 */ 816 #define REG_ALLOC_ORDER \ 817 { 0, 1, 2, 3, 4, 5, 6, 7, \ 818 16, 17, 18, 19, 9, 10, 11, 12, \ 819 13, 14, 8, 15, 20, 21, 22, 23, \ 820 24, 25, 26, 27, 28, 29, 30, 31, \ 821 32, 33, 34, 35, 36, 37, 38, 39, \ 822 40, 41, 42, 43, 44, 45, 46, 47, \ 823 48, 49, 50, 51, 52, 53, 54, 55, \ 824 56, 57, 58, 59, 60, 61, 62, 63, \ 825 64, 65, 66, 67, 68, 69, 70, 71, \ 826 72, 73, 74, 75, 76, 77, 78, 79, \ 827 80, 81, 82, 83, 84, 85, 86, 87, \ 828 88, 89, 90, 91, 92, 93, 94, 95, \ 829 96, 97, 98, 99, 100, \ 830 } 831 832 /* ADJUST_REG_ALLOC_ORDER is a macro which permits reg_alloc_order 833 to be rearranged based on optimizing for speed or size. */ 834 #define ADJUST_REG_ALLOC_ORDER nds32_adjust_reg_alloc_order () 835 836 /* Tell IRA to use the order we define rather than messing it up with its 837 own cost calculations. */ 838 #define HONOR_REG_ALLOC_ORDER optimize_size 839 840 841 /* Register Classes. */ 842 843 /* In nds32 target, we have three levels of registers: 844 Low cost regsiters : $r0 ~ $r7 845 Middle cost registers : $r8 ~ $r11, $r16 ~ $r19 846 High cost registers : $r12 ~ $r14, $r20 ~ $r31 847 848 In practice, we have MIDDLE_REGS cover LOW_REGS register class contents 849 so that it provides more chance to use low cost registers. */ 850 enum reg_class 851 { 852 NO_REGS, 853 R5_REG, 854 R8_REG, 855 R15_TA_REG, 856 STACK_REG, 857 FRAME_POINTER_REG, 858 LOW_REGS, 859 MIDDLE_REGS, 860 HIGH_REGS, 861 GENERAL_REGS, 862 FRAME_REGS, 863 FP_REGS, 864 ALL_REGS, 865 LIM_REG_CLASSES 866 }; 867 868 #define N_REG_CLASSES (int) LIM_REG_CLASSES 869 870 #define REG_CLASS_NAMES \ 871 { \ 872 "NO_REGS", \ 873 "R5_REG", \ 874 "R8_REG", \ 875 "R15_TA_REG", \ 876 "STACK_REG", \ 877 "FRAME_POINTER_REG", \ 878 "LOW_REGS", \ 879 "MIDDLE_REGS", \ 880 "HIGH_REGS", \ 881 "GENERAL_REGS", \ 882 "FRAME_REGS", \ 883 "FP_REGS", \ 884 "ALL_REGS" \ 885 } 886 887 #define REG_CLASS_CONTENTS \ 888 { /* NO_REGS */ \ 889 {0x00000000, 0x00000000, 0x00000000, 0x00000000}, \ 890 /* R5_REG : 5 */ \ 891 {0x00000020, 0x00000000, 0x00000000, 0x00000000}, \ 892 /* R8_REG : 8 */ \ 893 {0x00000100, 0x00000000, 0x00000000, 0x00000000}, \ 894 /* R15_TA_REG : 15 */ \ 895 {0x00008000, 0x00000000, 0x00000000, 0x00000000}, \ 896 /* STACK_REG : 31 */ \ 897 {0x80000000, 0x00000000, 0x00000000, 0x00000000}, \ 898 /* FRAME_POINTER_REG : 28 */ \ 899 {0x10000000, 0x00000000, 0x00000000, 0x00000000}, \ 900 /* LOW_REGS : 0-7 */ \ 901 {0x000000ff, 0x00000000, 0x00000000, 0x00000000}, \ 902 /* MIDDLE_REGS : 0-11, 16-19 */ \ 903 {0x000f0fff, 0x00000000, 0x00000000, 0x00000000}, \ 904 /* HIGH_REGS : 12-14, 20-31 */ \ 905 {0xfff07000, 0x00000000, 0x00000000, 0x00000000}, \ 906 /* GENERAL_REGS : 0-31 */ \ 907 {0xffffffff, 0x00000000, 0x00000000, 0x00000000}, \ 908 /* FRAME_REGS : 32, 33 */ \ 909 {0x00000000, 0x00000003, 0x00000000, 0x00000000}, \ 910 /* FP_REGS : 34-98 */ \ 911 {0x00000000, 0xfffffffc, 0xffffffff, 0x00000003}, \ 912 /* ALL_REGS : 0-100 */ \ 913 {0xffffffff, 0xffffffff, 0xffffffff, 0x0000001f} \ 914 } 915 916 #define REGNO_REG_CLASS(regno) nds32_regno_reg_class (regno) 917 918 #define BASE_REG_CLASS GENERAL_REGS 919 #define INDEX_REG_CLASS GENERAL_REGS 920 921 #define TEST_REGNO(R, TEST, VALUE) \ 922 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 923 924 /* Return nonzero if it is suitable for use as a 925 base register in operand addresses. 926 So far, we return nonzero only if "num" is a hard reg 927 of the suitable class or a pseudo register which is 928 allocated to a suitable hard reg. */ 929 #define REGNO_OK_FOR_BASE_P(num) \ 930 (TEST_REGNO (num, <, 32) \ 931 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \ 932 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM)) 933 934 /* Return nonzero if it is suitable for use as a 935 index register in operand addresses. 936 So far, we return nonzero only if "num" is a hard reg 937 of the suitable class or a pseudo register which is 938 allocated to a suitable hard reg. 939 The difference between an index register and a base register is that 940 the index register may be scaled. */ 941 #define REGNO_OK_FOR_INDEX_P(num) \ 942 (TEST_REGNO (num, <, 32) \ 943 || TEST_REGNO (num, ==, FRAME_POINTER_REGNUM) \ 944 || TEST_REGNO (num, ==, ARG_POINTER_REGNUM)) 945 946 947 /* Obsolete Macros for Defining Constraints. */ 948 949 950 /* Stack Layout and Calling Conventions. */ 951 952 #define STACK_GROWS_DOWNWARD 1 953 954 #define FRAME_GROWS_DOWNWARD 1 955 956 #define STACK_POINTER_OFFSET 0 957 958 #define FIRST_PARM_OFFSET(fundecl) \ 959 (NDS32_DOUBLE_WORD_ALIGN_P (crtl->args.pretend_args_size) ? 0 : 4) 960 961 /* A C expression whose value is RTL representing the address in a stack frame 962 where the pointer to the caller's frame is stored. */ 963 #define DYNAMIC_CHAIN_ADDRESS(frameaddr) \ 964 nds32_dynamic_chain_address (frameaddr) 965 966 #define RETURN_ADDR_RTX(count, frameaddr) \ 967 nds32_return_addr_rtx (count, frameaddr) 968 969 /* A C expression whose value is RTL representing the location 970 of the incoming return address at the beginning of any function 971 before the prologue. 972 If this RTL is REG, you should also define 973 DWARF_FRAME_RETURN_COLUMN to DWARF_FRAME_REGNUM (REGNO). */ 974 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LP_REGNUM) 975 #define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LP_REGNUM) 976 977 /* Use $r0 $r1 to pass exception handling information. */ 978 #define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? (N) : INVALID_REGNUM) 979 /* The register $r2 that represents a location in which to store a stack 980 adjustment to be applied before function return. 981 This is used to unwind the stack to an exception handler's call frame. */ 982 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, 2) 983 984 #define DBX_REGISTER_NUMBER(REGNO) nds32_dbx_register_number (REGNO) 985 986 #define STACK_POINTER_REGNUM SP_REGNUM 987 988 #define FRAME_POINTER_REGNUM 33 989 990 #define HARD_FRAME_POINTER_REGNUM FP_REGNUM 991 992 #define ARG_POINTER_REGNUM 32 993 994 #define STATIC_CHAIN_REGNUM 16 995 996 #define ELIMINABLE_REGS \ 997 { { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 998 { ARG_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM }, \ 999 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 1000 { FRAME_POINTER_REGNUM, HARD_FRAME_POINTER_REGNUM } } 1001 1002 #define INITIAL_ELIMINATION_OFFSET(from_reg, to_reg, offset_var) \ 1003 (offset_var) = nds32_initial_elimination_offset (from_reg, to_reg) 1004 1005 #define ACCUMULATE_OUTGOING_ARGS 1 1006 1007 #define OUTGOING_REG_PARM_STACK_SPACE(fntype) 1 1008 1009 #define CUMULATIVE_ARGS nds32_cumulative_args 1010 1011 #define INIT_CUMULATIVE_ARGS(cum, fntype, libname, fndecl, n_named_args) \ 1012 nds32_init_cumulative_args (&cum, fntype, libname, fndecl, n_named_args) 1013 1014 #define FUNCTION_ARG_REGNO_P(regno) \ 1015 (IN_RANGE ((regno), NDS32_FIRST_GPR_REGNUM, NDS32_MAX_GPR_REGS_FOR_ARGS - 1) \ 1016 || ((TARGET_FPU_SINGLE || TARGET_FPU_DOUBLE) \ 1017 && IN_RANGE ((regno), NDS32_FPR_ARG_FIRST_REGNUM, \ 1018 NDS32_FIRST_FPR_REGNUM + NDS32_MAX_FPR_REGS_FOR_ARGS - 1))) 1019 1020 #define DEFAULT_PCC_STRUCT_RETURN 0 1021 1022 /* EXIT_IGNORE_STACK should be nonzero if, when returning 1023 from a function, the stack pointer does not matter. 1024 The value is tested only in functions that have frame pointers. 1025 In nds32 target, the function epilogue recovers the 1026 stack pointer from the frame. */ 1027 #define EXIT_IGNORE_STACK 1 1028 1029 #define FUNCTION_PROFILER(file, labelno) \ 1030 fprintf (file, "/* profiler %d */\n", (labelno)) 1031 1032 #define PROFILE_HOOK(LABEL) \ 1033 { \ 1034 rtx fun, lp; \ 1035 lp = get_hard_reg_initial_val (Pmode, LP_REGNUM); \ 1036 fun = gen_rtx_SYMBOL_REF (Pmode, "_mcount"); \ 1037 emit_library_call (fun, LCT_NORMAL, VOIDmode, lp, Pmode); \ 1038 } 1039 1040 1041 /* Implementing the Varargs Macros. */ 1042 1043 1044 /* Trampolines for Nested Functions. */ 1045 1046 /* Giving A-function and B-function, 1047 if B-function wants to call A-function's nested function, 1048 we need to fill trampoline code into A-function's stack 1049 so that B-function can execute the code in stack to indirectly 1050 jump to (like 'trampoline' action) desired nested function. 1051 1052 The trampoline code for nds32 target must contains following parts: 1053 1054 1. instructions (4 * 4 = 16 bytes): 1055 get $pc first 1056 load chain_value to static chain register via $pc 1057 load nested function address to $r15 via $pc 1058 jump to desired nested function via $r15 1059 2. data (4 * 2 = 8 bytes): 1060 chain_value 1061 nested function address 1062 1063 Please check nds32.c implementation for more information. */ 1064 #define TRAMPOLINE_SIZE 24 1065 1066 /* Because all instructions/data in trampoline template are 4-byte size, 1067 we set trampoline alignment 8*4=32 bits. */ 1068 #define TRAMPOLINE_ALIGNMENT 32 1069 1070 1071 /* Implicit Calls to Library Routines. */ 1072 1073 1074 /* Addressing Modes. */ 1075 1076 /* We can use "LWI.bi Rt, [Ra], 4" to support post increment. */ 1077 #define HAVE_POST_INCREMENT 1 1078 /* We can use "LWI.bi Rt, [Ra], -4" to support post decrement. */ 1079 #define HAVE_POST_DECREMENT 1 1080 1081 /* We have "LWI.bi Rt, [Ra], imm" instruction form. */ 1082 #define HAVE_POST_MODIFY_DISP 1 1083 /* We have "LW.bi Rt, [Ra], Rb" instruction form. */ 1084 #define HAVE_POST_MODIFY_REG 1 1085 1086 #define USE_LOAD_POST_INCREMENT(mode) \ 1087 nds32_use_load_post_increment(mode) 1088 #define USE_LOAD_POST_DECREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1089 #define USE_STORE_POST_DECREMENT(mode) USE_LOAD_POST_DECREMENT(mode) 1090 #define USE_STORE_POST_INCREMENT(mode) USE_LOAD_POST_INCREMENT(mode) 1091 1092 #define CONSTANT_ADDRESS_P(x) (CONSTANT_P (x) && GET_CODE (x) != CONST_DOUBLE) 1093 1094 #define MAX_REGS_PER_ADDRESS 3 1095 1096 1097 /* Anchored Addresses. */ 1098 1099 1100 /* Condition Code Status. */ 1101 1102 1103 /* Describing Relative Costs of Operations. */ 1104 1105 /* A C expression for the cost of a branch instruction. 1106 A value of 1 is the default; 1107 other values are interpreted relative to that. */ 1108 #define BRANCH_COST(speed_p, predictable_p) ((speed_p) ? 2 : 1) 1109 1110 /* Override BRANCH_COST heuristic which empirically produces worse 1111 performance for removing short circuiting from the logical ops. */ 1112 #define LOGICAL_OP_NON_SHORT_CIRCUIT 0 1113 1114 #define SLOW_BYTE_ACCESS 1 1115 1116 #define NO_FUNCTION_CSE 1 1117 1118 1119 /* Adjusting the Instruction Scheduler. */ 1120 1121 1122 /* Dividing the Output into Sections (Texts, Data, . . . ). */ 1123 1124 #define TEXT_SECTION_ASM_OP "\t.text" 1125 #define DATA_SECTION_ASM_OP "\t.data" 1126 1127 /* Currently, nds32 assembler does NOT handle '.bss' pseudo-op. 1128 So we use '.section .bss' alternatively. */ 1129 #define BSS_SECTION_ASM_OP "\t.section\t.bss" 1130 1131 /* Define this macro to be an expression with a nonzero value if jump tables 1132 (for tablejump insns) should be output in the text section, 1133 along with the assembler instructions. 1134 Otherwise, the readonly data section is used. */ 1135 #define JUMP_TABLES_IN_TEXT_SECTION 1 1136 1137 1138 /* Position Independent Code. */ 1139 1140 #define PIC_OFFSET_TABLE_REGNUM GP_REGNUM 1141 1142 1143 /* Defining the Output Assembler Language. */ 1144 1145 #define ASM_COMMENT_START "!" 1146 1147 #define ASM_APP_ON "! #APP\n" 1148 1149 #define ASM_APP_OFF "! #NO_APP\n" 1150 1151 #define ASM_OUTPUT_LABELREF(stream, name) \ 1152 asm_fprintf (stream, "%U%s", (*targetm.strip_name_encoding) (name)) 1153 1154 #define ASM_OUTPUT_SYMBOL_REF(stream, sym) \ 1155 assemble_name (stream, XSTR (sym, 0)) 1156 1157 #define ASM_OUTPUT_LABEL_REF(stream, buf) \ 1158 assemble_name (stream, buf) 1159 1160 #define LOCAL_LABEL_PREFIX "." 1161 1162 #define REGISTER_NAMES \ 1163 { "$r0", "$r1", "$r2", "$r3", "$r4", "$r5", "$r6", "$r7", \ 1164 "$r8", "$r9", "$r10", "$r11", "$r12", "$r13", "$r14", "$ta", \ 1165 "$r16", "$r17", "$r18", "$r19", "$r20", "$r21", "$r22", "$r23", \ 1166 "$r24", "$r25", "$r26", "$r27", "$fp", "$gp", "$lp", "$sp", \ 1167 "$AP", "$SFP", "$fs0", "$fs1", "$fs2", "$fs3", "$fs4", "$fs5", \ 1168 "$fs6", "$fs7", "$fs8", "$fs9", "$fs10","$fs11","$fs12","$fs13",\ 1169 "$fs14","$fs15","$fs16","$fs17","$fs18","$fs19","$fs20","$fs21",\ 1170 "$fs22","$fs23","$fs24","$fs25","$fs26","$fs27","$fs28","$fs29",\ 1171 "$fs30","$fs31","$fs32","$fs33","$fs34","$fs35","$fs36","$fs37",\ 1172 "$fs38","$fs39","$fs40","$fs41","$fs42","$fs43","$fs44","$fs45",\ 1173 "$fs46","$fs47","$fs48","$fs49","$fs50","$fs51","$fs52","$fs53",\ 1174 "$fs54","$fs55","$fs56","$fs57","$fs58","$fs59","$fs60","$fs61",\ 1175 "$fs62","$fs63", "LB", "LE", "LC" \ 1176 } 1177 1178 #define ADDITIONAL_REGISTER_NAMES \ 1179 { \ 1180 {"$r15", 15}, \ 1181 {"$r28", 28}, {"$r29", 29}, {"$r30", 30}, {"$r31", 31}, \ 1182 {"$a0", 0}, {"$a1", 1}, {"$a2", 2}, \ 1183 {"$a3", 3}, {"$a4", 4}, {"$a5", 5}, \ 1184 {"$s0", 6}, {"$s1", 7}, {"$s2", 8}, {"$s3", 9}, \ 1185 {"$s4", 10}, {"$s5", 11}, {"$s6", 12}, {"$s7", 13}, \ 1186 {"$s8", 14}, \ 1187 {"$t0", 16}, {"$t1", 17}, {"$t2", 18}, {"$t3", 19}, \ 1188 {"$t4", 20}, {"$t5", 21}, {"$t6", 22}, {"$t7", 23}, \ 1189 {"$t8", 24}, {"$t9", 25}, \ 1190 {"$p0", 26}, {"$p1", 27}, \ 1191 {"$h0", 0}, {"$h1", 1}, {"$h2", 2}, {"$h3", 3}, \ 1192 {"$h4", 4}, {"$h5", 5}, {"$h6", 6}, {"$h7", 7}, \ 1193 {"$h8", 8}, {"$h9", 9}, {"$h10", 10}, {"$h11", 11}, \ 1194 {"$h12", 16}, {"$h13", 17}, {"$h14", 18}, {"$h15", 19}, \ 1195 {"$o0", 0}, {"$o1", 1}, {"$o2", 2}, {"$o3", 3}, \ 1196 {"$o4", 4}, {"$o5", 5}, {"$o6", 6}, {"$o7", 7}, \ 1197 } 1198 1199 #define OVERLAPPING_REGISTER_NAMES \ 1200 { \ 1201 {"$fd0", NDS32_FIRST_FPR_REGNUM + 0, 2}, \ 1202 {"$fd1", NDS32_FIRST_FPR_REGNUM + 2, 2}, \ 1203 {"$fd2", NDS32_FIRST_FPR_REGNUM + 4, 2}, \ 1204 {"$fd3", NDS32_FIRST_FPR_REGNUM + 6, 2}, \ 1205 {"$fd4", NDS32_FIRST_FPR_REGNUM + 8, 2}, \ 1206 {"$fd5", NDS32_FIRST_FPR_REGNUM + 10, 2}, \ 1207 {"$fd6", NDS32_FIRST_FPR_REGNUM + 12, 2}, \ 1208 {"$fd7", NDS32_FIRST_FPR_REGNUM + 14, 2}, \ 1209 {"$fd8", NDS32_FIRST_FPR_REGNUM + 16, 2}, \ 1210 {"$fd9", NDS32_FIRST_FPR_REGNUM + 18, 2}, \ 1211 {"$fd10", NDS32_FIRST_FPR_REGNUM + 20, 2}, \ 1212 {"$fd11", NDS32_FIRST_FPR_REGNUM + 22, 2}, \ 1213 {"$fd12", NDS32_FIRST_FPR_REGNUM + 24, 2}, \ 1214 {"$fd13", NDS32_FIRST_FPR_REGNUM + 26, 2}, \ 1215 {"$fd14", NDS32_FIRST_FPR_REGNUM + 28, 2}, \ 1216 {"$fd15", NDS32_FIRST_FPR_REGNUM + 30, 2}, \ 1217 {"$fd16", NDS32_FIRST_FPR_REGNUM + 32, 2}, \ 1218 {"$fd17", NDS32_FIRST_FPR_REGNUM + 34, 2}, \ 1219 {"$fd18", NDS32_FIRST_FPR_REGNUM + 36, 2}, \ 1220 {"$fd19", NDS32_FIRST_FPR_REGNUM + 38, 2}, \ 1221 {"$fd20", NDS32_FIRST_FPR_REGNUM + 40, 2}, \ 1222 {"$fd21", NDS32_FIRST_FPR_REGNUM + 42, 2}, \ 1223 {"$fd22", NDS32_FIRST_FPR_REGNUM + 44, 2}, \ 1224 {"$fd23", NDS32_FIRST_FPR_REGNUM + 46, 2}, \ 1225 {"$fd24", NDS32_FIRST_FPR_REGNUM + 48, 2}, \ 1226 {"$fd25", NDS32_FIRST_FPR_REGNUM + 50, 2}, \ 1227 {"$fd26", NDS32_FIRST_FPR_REGNUM + 52, 2}, \ 1228 {"$fd27", NDS32_FIRST_FPR_REGNUM + 54, 2}, \ 1229 {"$fd28", NDS32_FIRST_FPR_REGNUM + 56, 2}, \ 1230 {"$fd29", NDS32_FIRST_FPR_REGNUM + 58, 2}, \ 1231 {"$fd30", NDS32_FIRST_FPR_REGNUM + 60, 2}, \ 1232 {"$fd31", NDS32_FIRST_FPR_REGNUM + 62, 2}, \ 1233 } 1234 1235 /* Output normal jump table entry. */ 1236 #define ASM_OUTPUT_ADDR_VEC_ELT(stream, value) \ 1237 asm_fprintf (stream, "\t.word\t%LL%d\n", value) 1238 1239 /* Output pc relative jump table entry. */ 1240 #define ASM_OUTPUT_ADDR_DIFF_ELT(stream, body, value, rel) \ 1241 do \ 1242 { \ 1243 switch (GET_MODE (body)) \ 1244 { \ 1245 case E_QImode: \ 1246 asm_fprintf (stream, "\t.byte\t.L%d-.L%d\n", value, rel); \ 1247 break; \ 1248 case E_HImode: \ 1249 asm_fprintf (stream, "\t.short\t.L%d-.L%d\n", value, rel); \ 1250 break; \ 1251 case E_SImode: \ 1252 asm_fprintf (stream, "\t.word\t.L%d-.L%d\n", value, rel); \ 1253 break; \ 1254 default: \ 1255 gcc_unreachable(); \ 1256 } \ 1257 } while (0) 1258 1259 /* We have to undef it first because elfos.h formerly define it 1260 check gcc/config.gcc and gcc/config/elfos.h for more information. */ 1261 #undef ASM_OUTPUT_CASE_LABEL 1262 #define ASM_OUTPUT_CASE_LABEL(stream, prefix, num, table) \ 1263 do \ 1264 { \ 1265 asm_fprintf (stream, "\t! Jump Table Begin\n"); \ 1266 (*targetm.asm_out.internal_label) (stream, prefix, num); \ 1267 } while (0) 1268 1269 #define ASM_OUTPUT_CASE_END(stream, num, table) \ 1270 do \ 1271 { \ 1272 /* Because our jump table is in text section, \ 1273 we need to make sure 2-byte alignment after \ 1274 the jump table for instructions fetch. */ \ 1275 if (GET_MODE (PATTERN (table)) == QImode) \ 1276 ASM_OUTPUT_ALIGN (stream, 1); \ 1277 asm_fprintf (stream, "\t! Jump Table End\n"); \ 1278 } while (0) 1279 1280 /* This macro is not documented yet. 1281 But we do need it to make jump table vector aligned. */ 1282 #define ADDR_VEC_ALIGN(JUMPTABLE) 2 1283 1284 #define DWARF2_UNWIND_INFO 1 1285 1286 #define JUMP_ALIGN(x) \ 1287 (align_jumps_log ? align_jumps_log : nds32_target_alignment (x)) 1288 1289 #define LOOP_ALIGN(x) \ 1290 (align_loops_log ? align_loops_log : nds32_target_alignment (x)) 1291 1292 #define LABEL_ALIGN(x) \ 1293 (align_labels_log ? align_labels_log : nds32_target_alignment (x)) 1294 1295 #define ASM_OUTPUT_ALIGN(stream, power) \ 1296 fprintf (stream, "\t.align\t%d\n", power) 1297 1298 1299 /* Controlling Debugging Information Format. */ 1300 1301 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1302 1303 #define DWARF2_DEBUGGING_INFO 1 1304 1305 #define DWARF2_ASM_LINE_DEBUG_INFO 1 1306 1307 1308 /* Cross Compilation and Floating Point. */ 1309 1310 1311 /* Mode Switching Instructions. */ 1312 1313 1314 /* Defining target-specific uses of __attribute__. */ 1315 1316 1317 /* Emulating TLS. */ 1318 1319 1320 /* Defining coprocessor specifics for MIPS targets. */ 1321 1322 1323 /* Parameters for Precompiled Header Validity Checking. */ 1324 1325 1326 /* C++ ABI parameters. */ 1327 1328 1329 /* Adding support for named address spaces. */ 1330 1331 1332 /* Miscellaneous Parameters. */ 1333 1334 /* This is the machine mode that elements of a jump-table should have. */ 1335 #define CASE_VECTOR_MODE Pmode 1336 1337 /* Return the preferred mode for and addr_diff_vec when the mininum 1338 and maximum offset are known. */ 1339 #define CASE_VECTOR_SHORTEN_MODE(min_offset, max_offset, body) \ 1340 nds32_case_vector_shorten_mode (min_offset, max_offset, body) 1341 1342 /* Generate pc relative jump table when -fpic or -Os. */ 1343 #define CASE_VECTOR_PC_RELATIVE (flag_pic || optimize_size) 1344 1345 /* Define this macro if operations between registers with integral mode 1346 smaller than a word are always performed on the entire register. */ 1347 #define WORD_REGISTER_OPERATIONS 1 1348 1349 /* A C expression indicating when insns that read memory in mem_mode, 1350 an integral mode narrower than a word, set the bits outside of mem_mode 1351 to be either the sign-extension or the zero-extension of the data read. */ 1352 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1353 1354 /* The maximum number of bytes that a single instruction can move quickly 1355 between memory and registers or between two memory locations. */ 1356 #define MOVE_MAX 4 1357 1358 /* A C expression that is nonzero if on this machine the number of bits 1359 actually used for the count of a shift operation is equal to the number 1360 of bits needed to represent the size of the object being shifted. */ 1361 #define SHIFT_COUNT_TRUNCATED 1 1362 1363 /* A C expression describing the value returned by a comparison operator with 1364 an integral mode and stored by a store-flag instruction ('cstoremode4') 1365 when the condition is true. */ 1366 #define STORE_FLAG_VALUE 1 1367 1368 /* A C expression that indicates whether the architecture defines a value for 1369 clz or ctz with a zero operand. In nds32 clz for 0 result 32 is defined 1370 in ISA spec */ 1371 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 1372 1373 /* An alias for the machine mode for pointers. */ 1374 #define Pmode SImode 1375 1376 /* An alias for the machine mode used for memory references to functions 1377 being called, in call RTL expressions. */ 1378 #define FUNCTION_MODE SImode 1379 1380 /* ------------------------------------------------------------------------ */ 1381