1;; Machine description of Andes NDS32 cpu for GNU compiler 2;; Copyright (C) 2012-2019 Free Software Foundation, Inc. 3;; Contributed by Andes Technology Corporation. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21(define_expand "mov<mode>" 22 [(set (match_operand:VQIHI 0 "general_operand" "") 23 (match_operand:VQIHI 1 "general_operand" ""))] 24 "NDS32_EXT_DSP_P ()" 25{ 26 /* Need to force register if mem <- !reg. */ 27 if (MEM_P (operands[0]) && !REG_P (operands[1])) 28 operands[1] = force_reg (<MODE>mode, operands[1]); 29 30 /* If operands[1] is a large constant and cannot be performed 31 by a single instruction, we need to split it. */ 32 if (GET_CODE (operands[1]) == CONST_VECTOR 33 && !satisfies_constraint_CVs2 (operands[1]) 34 && !satisfies_constraint_CVhi (operands[1])) 35 { 36 HOST_WIDE_INT ival = const_vector_to_hwint (operands[1]); 37 rtx tmp_rtx; 38 39 tmp_rtx = can_create_pseudo_p () 40 ? gen_reg_rtx (SImode) 41 : simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0); 42 43 emit_move_insn (tmp_rtx, gen_int_mode (ival, SImode)); 44 convert_move (operands[0], tmp_rtx, false); 45 DONE; 46 } 47 48 if (REG_P (operands[0]) && SYMBOLIC_CONST_P (operands[1])) 49 { 50 if (nds32_tls_referenced_p (operands [1])) 51 { 52 nds32_expand_tls_move (operands); 53 DONE; 54 } 55 else if (flag_pic) 56 { 57 nds32_expand_pic_move (operands); 58 DONE; 59 } 60 } 61}) 62 63(define_insn "*mov<mode>" 64 [(set (match_operand:VQIHI 0 "nonimmediate_operand" "=r, r,$U45,$U33,$U37,$U45, m,$ l,$ l,$ l,$ d, d, r,$ d, r, r, r, *f, *f, r, *f, Q") 65 (match_operand:VQIHI 1 "nds32_vmove_operand" " r, r, l, l, l, d, r, U45, U33, U37, U45,Ufe, m, CVp5, CVs5, CVs2, CVhi, *f, r, *f, Q, *f"))] 66 "NDS32_EXT_DSP_P () 67 && (register_operand(operands[0], <MODE>mode) 68 || register_operand(operands[1], <MODE>mode))" 69{ 70 switch (which_alternative) 71 { 72 case 0: 73 return "mov55\t%0, %1"; 74 case 1: 75 return "ori\t%0, %1, 0"; 76 case 2: 77 case 3: 78 case 4: 79 case 5: 80 return nds32_output_16bit_store (operands, <byte>); 81 case 6: 82 return nds32_output_32bit_store (operands, <byte>); 83 case 7: 84 case 8: 85 case 9: 86 case 10: 87 case 11: 88 return nds32_output_16bit_load (operands, <byte>); 89 case 12: 90 return nds32_output_32bit_load (operands, <byte>); 91 case 13: 92 return "movpi45\t%0, %1"; 93 case 14: 94 return "movi55\t%0, %1"; 95 case 15: 96 return "movi\t%0, %1"; 97 case 16: 98 return "sethi\t%0, hi20(%1)"; 99 case 17: 100 if (TARGET_FPU_SINGLE) 101 return "fcpyss\t%0, %1, %1"; 102 else 103 return "#"; 104 case 18: 105 return "fmtsr\t%1, %0"; 106 case 19: 107 return "fmfsr\t%0, %1"; 108 case 20: 109 return nds32_output_float_load (operands); 110 case 21: 111 return nds32_output_float_store (operands); 112 default: 113 gcc_unreachable (); 114 } 115} 116 [(set_attr "type" "alu,alu,store,store,store,store,store,load,load,load,load,load,load,alu,alu,alu,alu,fcpy,fmtsr,fmfsr,fload,fstore") 117 (set_attr "length" " 2, 4, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 4, 2, 2, 4, 4, 4, 4, 4, 4, 4") 118 (set_attr "feature" " v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v1, v3m, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")]) 119 120(define_expand "movv2si" 121 [(set (match_operand:V2SI 0 "general_operand" "") 122 (match_operand:V2SI 1 "general_operand" ""))] 123 "NDS32_EXT_DSP_P ()" 124{ 125 /* Need to force register if mem <- !reg. */ 126 if (MEM_P (operands[0]) && !REG_P (operands[1])) 127 operands[1] = force_reg (V2SImode, operands[1]); 128}) 129 130(define_insn "*movv2si" 131 [(set (match_operand:V2SI 0 "nonimmediate_operand" "=r, r, r, r, Da, m, f, Q, f, r, f") 132 (match_operand:V2SI 1 "general_operand" " r, i, Da, m, r, r, Q, f, f, f, r"))] 133 "NDS32_EXT_DSP_P () 134 && (register_operand(operands[0], V2SImode) 135 || register_operand(operands[1], V2SImode))" 136{ 137 switch (which_alternative) 138 { 139 case 0: 140 return "movd44\t%0, %1"; 141 case 1: 142 /* reg <- const_int, we ask gcc to split instruction. */ 143 return "#"; 144 case 2: 145 /* The memory format is (mem (reg)), 146 we can generate 'lmw.bi' instruction. */ 147 return nds32_output_double (operands, true); 148 case 3: 149 /* We haven't 64-bit load instruction, 150 we split this pattern to two SImode pattern. */ 151 return "#"; 152 case 4: 153 /* The memory format is (mem (reg)), 154 we can generate 'smw.bi' instruction. */ 155 return nds32_output_double (operands, false); 156 case 5: 157 /* We haven't 64-bit store instruction, 158 we split this pattern to two SImode pattern. */ 159 return "#"; 160 case 6: 161 return nds32_output_float_load (operands); 162 case 7: 163 return nds32_output_float_store (operands); 164 case 8: 165 return "fcpysd\t%0, %1, %1"; 166 case 9: 167 return "fmfdr\t%0, %1"; 168 case 10: 169 return "fmtdr\t%1, %0"; 170 default: 171 gcc_unreachable (); 172 } 173} 174 [(set_attr "type" "alu,alu,load,load,store,store,unknown,unknown,unknown,unknown,unknown") 175 (set_attr_alternative "length" 176 [ 177 ;; Alternative 0 178 (if_then_else (match_test "!TARGET_16_BIT") 179 (const_int 4) 180 (const_int 2)) 181 ;; Alternative 1 182 (const_int 16) 183 ;; Alternative 2 184 (const_int 4) 185 ;; Alternative 3 186 (const_int 8) 187 ;; Alternative 4 188 (const_int 4) 189 ;; Alternative 5 190 (const_int 8) 191 ;; Alternative 6 192 (const_int 4) 193 ;; Alternative 7 194 (const_int 4) 195 ;; Alternative 8 196 (const_int 4) 197 ;; Alternative 9 198 (const_int 4) 199 ;; Alternative 10 200 (const_int 4) 201 ]) 202 (set_attr "feature" " v1, v1, v1, v1, v1, v1, fpu, fpu, fpu, fpu, fpu")]) 203 204(define_expand "movmisalign<mode>" 205 [(set (match_operand:VQIHI 0 "general_operand" "") 206 (match_operand:VQIHI 1 "general_operand" ""))] 207 "NDS32_EXT_DSP_P ()" 208{ 209 rtx addr; 210 if (MEM_P (operands[0]) && !REG_P (operands[1])) 211 operands[1] = force_reg (<MODE>mode, operands[1]); 212 213 if (MEM_P (operands[0])) 214 { 215 addr = force_reg (Pmode, XEXP (operands[0], 0)); 216 emit_insn (gen_unaligned_store<mode> (addr, operands[1])); 217 } 218 else 219 { 220 addr = force_reg (Pmode, XEXP (operands[1], 0)); 221 emit_insn (gen_unaligned_load<mode> (operands[0], addr)); 222 } 223 DONE; 224}) 225 226(define_expand "unaligned_load<mode>" 227 [(set (match_operand:VQIHI 0 "register_operand" "=r") 228 (unspec:VQIHI [(mem:VQIHI (match_operand:SI 1 "register_operand" "r"))] UNSPEC_UALOAD_W))] 229 "NDS32_EXT_DSP_P ()" 230{ 231 if (TARGET_ISA_V3M) 232 nds32_expand_unaligned_load (operands, <MODE>mode); 233 else 234 emit_insn (gen_unaligned_load_w<mode> (operands[0], gen_rtx_MEM (<MODE>mode, operands[1]))); 235 DONE; 236}) 237 238(define_insn "unaligned_load_w<mode>" 239 [(set (match_operand:VQIHI 0 "register_operand" "= r") 240 (unspec:VQIHI [(match_operand:VQIHI 1 "nds32_lmw_smw_base_operand" " Umw")] UNSPEC_UALOAD_W))] 241 "NDS32_EXT_DSP_P ()" 242{ 243 return nds32_output_lmw_single_word (operands); 244} 245 [(set_attr "type" "load") 246 (set_attr "length" "4")] 247) 248 249(define_expand "unaligned_store<mode>" 250 [(set (mem:VQIHI (match_operand:SI 0 "register_operand" "r")) 251 (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" "r")] UNSPEC_UASTORE_W))] 252 "NDS32_EXT_DSP_P ()" 253{ 254 if (TARGET_ISA_V3M) 255 nds32_expand_unaligned_store (operands, <MODE>mode); 256 else 257 emit_insn (gen_unaligned_store_w<mode> (gen_rtx_MEM (<MODE>mode, operands[0]), operands[1])); 258 DONE; 259}) 260 261(define_insn "unaligned_store_w<mode>" 262 [(set (match_operand:VQIHI 0 "nds32_lmw_smw_base_operand" "=Umw") 263 (unspec:VQIHI [(match_operand:VQIHI 1 "register_operand" " r")] UNSPEC_UASTORE_W))] 264 "NDS32_EXT_DSP_P ()" 265{ 266 return nds32_output_smw_single_word (operands); 267} 268 [(set_attr "type" "store") 269 (set_attr "length" "4")] 270) 271 272(define_insn "<uk>add<mode>3" 273 [(set (match_operand:VQIHI 0 "register_operand" "=r") 274 (all_plus:VQIHI (match_operand:VQIHI 1 "register_operand" " r") 275 (match_operand:VQIHI 2 "register_operand" " r")))] 276 "NDS32_EXT_DSP_P ()" 277 "<uk>add<bits> %0, %1, %2" 278 [(set_attr "type" "dalu") 279 (set_attr "length" "4") 280 (set_attr "feature" "v1")]) 281 282(define_insn "<uk>adddi3" 283 [(set (match_operand:DI 0 "register_operand" "=r") 284 (all_plus:DI (match_operand:DI 1 "register_operand" " r") 285 (match_operand:DI 2 "register_operand" " r")))] 286 "NDS32_EXT_DSP_P ()" 287 "<uk>add64 %0, %1, %2" 288 [(set_attr "type" "dalu64") 289 (set_attr "length" "4") 290 (set_attr "feature" "v1")]) 291 292(define_insn "raddv4qi3" 293 [(set (match_operand:V4QI 0 "register_operand" "=r") 294 (truncate:V4QI 295 (ashiftrt:V4HI 296 (plus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) 297 (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) 298 (const_int 1))))] 299 "NDS32_EXT_DSP_P ()" 300 "radd8\t%0, %1, %2" 301 [(set_attr "type" "dalu") 302 (set_attr "length" "4") 303 (set_attr "feature" "v1")]) 304 305 306(define_insn "uraddv4qi3" 307 [(set (match_operand:V4QI 0 "register_operand" "=r") 308 (truncate:V4QI 309 (lshiftrt:V4HI 310 (plus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) 311 (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) 312 (const_int 1))))] 313 "NDS32_EXT_DSP_P ()" 314 "uradd8\t%0, %1, %2" 315 [(set_attr "type" "dalu") 316 (set_attr "length" "4") 317 (set_attr "feature" "v1")]) 318 319(define_insn "raddv2hi3" 320 [(set (match_operand:V2HI 0 "register_operand" "=r") 321 (truncate:V2HI 322 (ashiftrt:V2SI 323 (plus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) 324 (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) 325 (const_int 1))))] 326 "NDS32_EXT_DSP_P ()" 327 "radd16\t%0, %1, %2" 328 [(set_attr "type" "dalu") 329 (set_attr "length" "4") 330 (set_attr "feature" "v1")]) 331 332(define_insn "uraddv2hi3" 333 [(set (match_operand:V2HI 0 "register_operand" "=r") 334 (truncate:V2HI 335 (lshiftrt:V2SI 336 (plus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) 337 (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) 338 (const_int 1))))] 339 "NDS32_EXT_DSP_P ()" 340 "uradd16\t%0, %1, %2" 341 [(set_attr "type" "dalu") 342 (set_attr "length" "4") 343 (set_attr "feature" "v1")]) 344 345(define_insn "radddi3" 346 [(set (match_operand:DI 0 "register_operand" "=r") 347 (truncate:DI 348 (ashiftrt:TI 349 (plus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r")) 350 (sign_extend:TI (match_operand:DI 2 "register_operand" " r"))) 351 (const_int 1))))] 352 "NDS32_EXT_DSP_P ()" 353 "radd64\t%0, %1, %2" 354 [(set_attr "type" "dalu64") 355 (set_attr "length" "4") 356 (set_attr "feature" "v1")]) 357 358 359(define_insn "uradddi3" 360 [(set (match_operand:DI 0 "register_operand" "=r") 361 (truncate:DI 362 (lshiftrt:TI 363 (plus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r")) 364 (zero_extend:TI (match_operand:DI 2 "register_operand" " r"))) 365 (const_int 1))))] 366 "NDS32_EXT_DSP_P ()" 367 "uradd64\t%0, %1, %2" 368 [(set_attr "type" "dalu64") 369 (set_attr "length" "4") 370 (set_attr "feature" "v1")]) 371 372(define_insn "<uk>sub<mode>3" 373 [(set (match_operand:VQIHI 0 "register_operand" "=r") 374 (all_minus:VQIHI (match_operand:VQIHI 1 "register_operand" " r") 375 (match_operand:VQIHI 2 "register_operand" " r")))] 376 "NDS32_EXT_DSP_P ()" 377 "<uk>sub<bits> %0, %1, %2" 378 [(set_attr "type" "dalu") 379 (set_attr "length" "4") 380 (set_attr "feature" "v1")]) 381 382(define_insn "<uk>subdi3" 383 [(set (match_operand:DI 0 "register_operand" "=r") 384 (all_minus:DI (match_operand:DI 1 "register_operand" " r") 385 (match_operand:DI 2 "register_operand" " r")))] 386 "NDS32_EXT_DSP_P ()" 387 "<uk>sub64 %0, %1, %2" 388 [(set_attr "type" "dalu64") 389 (set_attr "length" "4") 390 (set_attr "feature" "v1")]) 391 392(define_insn "rsubv4qi3" 393 [(set (match_operand:V4QI 0 "register_operand" "=r") 394 (truncate:V4QI 395 (ashiftrt:V4HI 396 (minus:V4HI (sign_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) 397 (sign_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) 398 (const_int 1))))] 399 "NDS32_EXT_DSP_P ()" 400 "rsub8\t%0, %1, %2" 401 [(set_attr "type" "dalu") 402 (set_attr "length" "4")]) 403 404(define_insn "ursubv4qi3" 405 [(set (match_operand:V4QI 0 "register_operand" "=r") 406 (truncate:V4QI 407 (lshiftrt:V4HI 408 (minus:V4HI (zero_extend:V4HI (match_operand:V4QI 1 "register_operand" " r")) 409 (zero_extend:V4HI (match_operand:V4QI 2 "register_operand" " r"))) 410 (const_int 1))))] 411 "NDS32_EXT_DSP_P ()" 412 "ursub8\t%0, %1, %2" 413 [(set_attr "type" "dalu") 414 (set_attr "length" "4")]) 415 416(define_insn "rsubv2hi3" 417 [(set (match_operand:V2HI 0 "register_operand" "=r") 418 (truncate:V2HI 419 (ashiftrt:V2SI 420 (minus:V2SI (sign_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) 421 (sign_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) 422 (const_int 1))))] 423 "NDS32_EXT_DSP_P ()" 424 "rsub16\t%0, %1, %2" 425 [(set_attr "type" "dalu") 426 (set_attr "length" "4")]) 427 428(define_insn "ursubv2hi3" 429 [(set (match_operand:V2HI 0 "register_operand" "=r") 430 (truncate:V2HI 431 (lshiftrt:V2SI 432 (minus:V2SI (zero_extend:V2SI (match_operand:V2HI 1 "register_operand" " r")) 433 (zero_extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))) 434 (const_int 1))))] 435 "NDS32_EXT_DSP_P ()" 436 "ursub16\t%0, %1, %2" 437 [(set_attr "type" "dalu") 438 (set_attr "length" "4")]) 439 440(define_insn "rsubdi3" 441 [(set (match_operand:DI 0 "register_operand" "=r") 442 (truncate:DI 443 (ashiftrt:TI 444 (minus:TI (sign_extend:TI (match_operand:DI 1 "register_operand" " r")) 445 (sign_extend:TI (match_operand:DI 2 "register_operand" " r"))) 446 (const_int 1))))] 447 "NDS32_EXT_DSP_P ()" 448 "rsub64\t%0, %1, %2" 449 [(set_attr "type" "dalu64") 450 (set_attr "length" "4")]) 451 452 453(define_insn "ursubdi3" 454 [(set (match_operand:DI 0 "register_operand" "=r") 455 (truncate:DI 456 (lshiftrt:TI 457 (minus:TI (zero_extend:TI (match_operand:DI 1 "register_operand" " r")) 458 (zero_extend:TI (match_operand:DI 2 "register_operand" " r"))) 459 (const_int 1))))] 460 "NDS32_EXT_DSP_P ()" 461 "ursub64\t%0, %1, %2" 462 [(set_attr "type" "dalu64") 463 (set_attr "length" "4")]) 464 465(define_expand "cras16_1" 466 [(match_operand:V2HI 0 "register_operand" "") 467 (match_operand:V2HI 1 "register_operand" "") 468 (match_operand:V2HI 2 "register_operand" "")] 469 "NDS32_EXT_DSP_P ()" 470{ 471 if (TARGET_BIG_ENDIAN) 472 emit_insn (gen_cras16_1_be (operands[0], operands[1], operands[2])); 473 else 474 emit_insn (gen_cras16_1_le (operands[0], operands[1], operands[2])); 475 DONE; 476}) 477 478(define_insn "cras16_1_le" 479 [(set (match_operand:V2HI 0 "register_operand" "=r") 480 (vec_merge:V2HI 481 (vec_duplicate:V2HI 482 (minus:HI 483 (vec_select:HI 484 (match_operand:V2HI 1 "register_operand" " r") 485 (parallel [(const_int 0)])) 486 (vec_select:HI 487 (match_operand:V2HI 2 "register_operand" " r") 488 (parallel [(const_int 1)])))) 489 (vec_duplicate:V2HI 490 (plus:HI 491 (vec_select:HI 492 (match_dup 2) 493 (parallel [(const_int 0)])) 494 (vec_select:HI 495 (match_dup 1) 496 (parallel [(const_int 1)])))) 497 (const_int 1)))] 498 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 499 "cras16\t%0, %1, %2" 500 [(set_attr "type" "dalu")] 501) 502 503(define_insn "cras16_1_be" 504 [(set (match_operand:V2HI 0 "register_operand" "=r") 505 (vec_merge:V2HI 506 (vec_duplicate:V2HI 507 (minus:HI 508 (vec_select:HI 509 (match_operand:V2HI 1 "register_operand" " r") 510 (parallel [(const_int 1)])) 511 (vec_select:HI 512 (match_operand:V2HI 2 "register_operand" " r") 513 (parallel [(const_int 0)])))) 514 (vec_duplicate:V2HI 515 (plus:HI 516 (vec_select:HI 517 (match_dup 2) 518 (parallel [(const_int 1)])) 519 (vec_select:HI 520 (match_dup 1) 521 (parallel [(const_int 0)])))) 522 (const_int 2)))] 523 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 524 "cras16\t%0, %1, %2" 525 [(set_attr "type" "dalu")] 526) 527 528(define_expand "kcras16_1" 529 [(match_operand:V2HI 0 "register_operand" "") 530 (match_operand:V2HI 1 "register_operand" "") 531 (match_operand:V2HI 2 "register_operand" "")] 532 "NDS32_EXT_DSP_P ()" 533{ 534 if (TARGET_BIG_ENDIAN) 535 emit_insn (gen_kcras16_1_be (operands[0], operands[1], operands[2])); 536 else 537 emit_insn (gen_kcras16_1_le (operands[0], operands[1], operands[2])); 538 DONE; 539}) 540 541(define_insn "kcras16_1_le" 542 [(set (match_operand:V2HI 0 "register_operand" "=r") 543 (vec_merge:V2HI 544 (vec_duplicate:V2HI 545 (ss_minus:HI 546 (vec_select:HI 547 (match_operand:V2HI 1 "register_operand" " r") 548 (parallel [(const_int 0)])) 549 (vec_select:HI 550 (match_operand:V2HI 2 "register_operand" " r") 551 (parallel [(const_int 1)])))) 552 (vec_duplicate:V2HI 553 (ss_plus:HI 554 (vec_select:HI 555 (match_dup 2) 556 (parallel [(const_int 0)])) 557 (vec_select:HI 558 (match_dup 1) 559 (parallel [(const_int 1)])))) 560 (const_int 1)))] 561 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 562 "kcras16\t%0, %1, %2" 563 [(set_attr "type" "dalu")] 564) 565 566(define_insn "kcras16_1_be" 567 [(set (match_operand:V2HI 0 "register_operand" "=r") 568 (vec_merge:V2HI 569 (vec_duplicate:V2HI 570 (ss_minus:HI 571 (vec_select:HI 572 (match_operand:V2HI 1 "register_operand" " r") 573 (parallel [(const_int 1)])) 574 (vec_select:HI 575 (match_operand:V2HI 2 "register_operand" " r") 576 (parallel [(const_int 0)])))) 577 (vec_duplicate:V2HI 578 (ss_plus:HI 579 (vec_select:HI 580 (match_dup 2) 581 (parallel [(const_int 1)])) 582 (vec_select:HI 583 (match_dup 1) 584 (parallel [(const_int 0)])))) 585 (const_int 2)))] 586 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 587 "kcras16\t%0, %1, %2" 588 [(set_attr "type" "dalu")] 589) 590 591(define_expand "ukcras16_1" 592 [(match_operand:V2HI 0 "register_operand" "") 593 (match_operand:V2HI 1 "register_operand" "") 594 (match_operand:V2HI 2 "register_operand" "")] 595 "NDS32_EXT_DSP_P ()" 596{ 597 if (TARGET_BIG_ENDIAN) 598 emit_insn (gen_ukcras16_1_be (operands[0], operands[1], operands[2])); 599 else 600 emit_insn (gen_ukcras16_1_le (operands[0], operands[1], operands[2])); 601 DONE; 602}) 603 604(define_insn "ukcras16_1_le" 605 [(set (match_operand:V2HI 0 "register_operand" "=r") 606 (vec_merge:V2HI 607 (vec_duplicate:V2HI 608 (us_minus:HI 609 (vec_select:HI 610 (match_operand:V2HI 1 "register_operand" " r") 611 (parallel [(const_int 0)])) 612 (vec_select:HI 613 (match_operand:V2HI 2 "register_operand" " r") 614 (parallel [(const_int 1)])))) 615 (vec_duplicate:V2HI 616 (us_plus:HI 617 (vec_select:HI 618 (match_dup 2) 619 (parallel [(const_int 0)])) 620 (vec_select:HI 621 (match_dup 1) 622 (parallel [(const_int 1)])))) 623 (const_int 1)))] 624 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 625 "ukcras16\t%0, %1, %2" 626 [(set_attr "type" "dalu")] 627) 628 629(define_insn "ukcras16_1_be" 630 [(set (match_operand:V2HI 0 "register_operand" "=r") 631 (vec_merge:V2HI 632 (vec_duplicate:V2HI 633 (us_minus:HI 634 (vec_select:HI 635 (match_operand:V2HI 1 "register_operand" " r") 636 (parallel [(const_int 1)])) 637 (vec_select:HI 638 (match_operand:V2HI 2 "register_operand" " r") 639 (parallel [(const_int 0)])))) 640 (vec_duplicate:V2HI 641 (us_plus:HI 642 (vec_select:HI 643 (match_dup 2) 644 (parallel [(const_int 1)])) 645 (vec_select:HI 646 (match_dup 1) 647 (parallel [(const_int 0)])))) 648 (const_int 2)))] 649 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 650 "ukcras16\t%0, %1, %2" 651 [(set_attr "type" "dalu")] 652) 653 654(define_expand "crsa16_1" 655 [(match_operand:V2HI 0 "register_operand" "") 656 (match_operand:V2HI 1 "register_operand" "") 657 (match_operand:V2HI 2 "register_operand" "")] 658 "NDS32_EXT_DSP_P ()" 659{ 660 if (TARGET_BIG_ENDIAN) 661 emit_insn (gen_crsa16_1_be (operands[0], operands[1], operands[2])); 662 else 663 emit_insn (gen_crsa16_1_le (operands[0], operands[1], operands[2])); 664 DONE; 665}) 666 667(define_insn "crsa16_1_le" 668 [(set (match_operand:V2HI 0 "register_operand" "=r") 669 (vec_merge:V2HI 670 (vec_duplicate:V2HI 671 (minus:HI 672 (vec_select:HI 673 (match_operand:V2HI 1 "register_operand" " r") 674 (parallel [(const_int 1)])) 675 (vec_select:HI 676 (match_operand:V2HI 2 "register_operand" " r") 677 (parallel [(const_int 0)])))) 678 (vec_duplicate:V2HI 679 (plus:HI 680 (vec_select:HI 681 (match_dup 1) 682 (parallel [(const_int 0)])) 683 (vec_select:HI 684 (match_dup 2) 685 (parallel [(const_int 1)])))) 686 (const_int 2)))] 687 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 688 "crsa16\t%0, %1, %2" 689 [(set_attr "type" "dalu")] 690) 691 692(define_insn "crsa16_1_be" 693 [(set (match_operand:V2HI 0 "register_operand" "=r") 694 (vec_merge:V2HI 695 (vec_duplicate:V2HI 696 (minus:HI 697 (vec_select:HI 698 (match_operand:V2HI 1 "register_operand" " r") 699 (parallel [(const_int 0)])) 700 (vec_select:HI 701 (match_operand:V2HI 2 "register_operand" " r") 702 (parallel [(const_int 1)])))) 703 (vec_duplicate:V2HI 704 (plus:HI 705 (vec_select:HI 706 (match_dup 1) 707 (parallel [(const_int 1)])) 708 (vec_select:HI 709 (match_dup 2) 710 (parallel [(const_int 0)])))) 711 (const_int 1)))] 712 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 713 "crsa16\t%0, %1, %2" 714 [(set_attr "type" "dalu")] 715) 716 717(define_expand "kcrsa16_1" 718 [(match_operand:V2HI 0 "register_operand" "") 719 (match_operand:V2HI 1 "register_operand" "") 720 (match_operand:V2HI 2 "register_operand" "")] 721 "NDS32_EXT_DSP_P ()" 722{ 723 if (TARGET_BIG_ENDIAN) 724 emit_insn (gen_kcrsa16_1_be (operands[0], operands[1], operands[2])); 725 else 726 emit_insn (gen_kcrsa16_1_le (operands[0], operands[1], operands[2])); 727 DONE; 728}) 729 730(define_insn "kcrsa16_1_le" 731 [(set (match_operand:V2HI 0 "register_operand" "=r") 732 (vec_merge:V2HI 733 (vec_duplicate:V2HI 734 (ss_minus:HI 735 (vec_select:HI 736 (match_operand:V2HI 1 "register_operand" " r") 737 (parallel [(const_int 1)])) 738 (vec_select:HI 739 (match_operand:V2HI 2 "register_operand" " r") 740 (parallel [(const_int 0)])))) 741 (vec_duplicate:V2HI 742 (ss_plus:HI 743 (vec_select:HI 744 (match_dup 1) 745 (parallel [(const_int 0)])) 746 (vec_select:HI 747 (match_dup 2) 748 (parallel [(const_int 1)])))) 749 (const_int 2)))] 750 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 751 "kcrsa16\t%0, %1, %2" 752 [(set_attr "type" "dalu")] 753) 754 755(define_insn "kcrsa16_1_be" 756 [(set (match_operand:V2HI 0 "register_operand" "=r") 757 (vec_merge:V2HI 758 (vec_duplicate:V2HI 759 (ss_minus:HI 760 (vec_select:HI 761 (match_operand:V2HI 1 "register_operand" " r") 762 (parallel [(const_int 0)])) 763 (vec_select:HI 764 (match_operand:V2HI 2 "register_operand" " r") 765 (parallel [(const_int 1)])))) 766 (vec_duplicate:V2HI 767 (ss_plus:HI 768 (vec_select:HI 769 (match_dup 1) 770 (parallel [(const_int 1)])) 771 (vec_select:HI 772 (match_dup 2) 773 (parallel [(const_int 0)])))) 774 (const_int 1)))] 775 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 776 "kcrsa16\t%0, %1, %2" 777 [(set_attr "type" "dalu")] 778) 779 780(define_expand "ukcrsa16_1" 781 [(match_operand:V2HI 0 "register_operand" "") 782 (match_operand:V2HI 1 "register_operand" "") 783 (match_operand:V2HI 2 "register_operand" "")] 784 "NDS32_EXT_DSP_P ()" 785{ 786 if (TARGET_BIG_ENDIAN) 787 emit_insn (gen_ukcrsa16_1_be (operands[0], operands[1], operands[2])); 788 else 789 emit_insn (gen_ukcrsa16_1_le (operands[0], operands[1], operands[2])); 790 DONE; 791}) 792 793(define_insn "ukcrsa16_1_le" 794 [(set (match_operand:V2HI 0 "register_operand" "=r") 795 (vec_merge:V2HI 796 (vec_duplicate:V2HI 797 (us_minus:HI 798 (vec_select:HI 799 (match_operand:V2HI 1 "register_operand" " r") 800 (parallel [(const_int 1)])) 801 (vec_select:HI 802 (match_operand:V2HI 2 "register_operand" " r") 803 (parallel [(const_int 0)])))) 804 (vec_duplicate:V2HI 805 (us_plus:HI 806 (vec_select:HI 807 (match_dup 1) 808 (parallel [(const_int 0)])) 809 (vec_select:HI 810 (match_dup 2) 811 (parallel [(const_int 1)])))) 812 (const_int 2)))] 813 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 814 "ukcrsa16\t%0, %1, %2" 815 [(set_attr "type" "dalu")] 816) 817 818(define_insn "ukcrsa16_1_be" 819 [(set (match_operand:V2HI 0 "register_operand" "=r") 820 (vec_merge:V2HI 821 (vec_duplicate:V2HI 822 (us_minus:HI 823 (vec_select:HI 824 (match_operand:V2HI 1 "register_operand" " r") 825 (parallel [(const_int 0)])) 826 (vec_select:HI 827 (match_operand:V2HI 2 "register_operand" " r") 828 (parallel [(const_int 1)])))) 829 (vec_duplicate:V2HI 830 (us_plus:HI 831 (vec_select:HI 832 (match_dup 1) 833 (parallel [(const_int 1)])) 834 (vec_select:HI 835 (match_dup 2) 836 (parallel [(const_int 0)])))) 837 (const_int 1)))] 838 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 839 "ukcrsa16\t%0, %1, %2" 840 [(set_attr "type" "dalu")] 841) 842 843(define_expand "rcras16_1" 844 [(match_operand:V2HI 0 "register_operand" "") 845 (match_operand:V2HI 1 "register_operand" "") 846 (match_operand:V2HI 2 "register_operand" "")] 847 "NDS32_EXT_DSP_P ()" 848{ 849 if (TARGET_BIG_ENDIAN) 850 emit_insn (gen_rcras16_1_be (operands[0], operands[1], operands[2])); 851 else 852 emit_insn (gen_rcras16_1_le (operands[0], operands[1], operands[2])); 853 DONE; 854}) 855 856(define_insn "rcras16_1_le" 857 [(set (match_operand:V2HI 0 "register_operand" "=r") 858 (vec_merge:V2HI 859 (vec_duplicate:V2HI 860 (truncate:HI 861 (ashiftrt:SI 862 (minus:SI 863 (sign_extend:SI 864 (vec_select:HI 865 (match_operand:V2HI 1 "register_operand" " r") 866 (parallel [(const_int 0)]))) 867 (sign_extend:SI 868 (vec_select:HI 869 (match_operand:V2HI 2 "register_operand" " r") 870 (parallel [(const_int 1)])))) 871 (const_int 1)))) 872 (vec_duplicate:V2HI 873 (truncate:HI 874 (ashiftrt:SI 875 (plus:SI 876 (sign_extend:SI 877 (vec_select:HI 878 (match_dup 2) 879 (parallel [(const_int 0)]))) 880 (sign_extend:SI 881 (vec_select:HI 882 (match_dup 1) 883 (parallel [(const_int 1)])))) 884 (const_int 1)))) 885 (const_int 1)))] 886 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 887 "rcras16\t%0, %1, %2" 888 [(set_attr "type" "dalu")] 889) 890 891(define_insn "rcras16_1_be" 892 [(set (match_operand:V2HI 0 "register_operand" "=r") 893 (vec_merge:V2HI 894 (vec_duplicate:V2HI 895 (truncate:HI 896 (ashiftrt:SI 897 (minus:SI 898 (sign_extend:SI 899 (vec_select:HI 900 (match_operand:V2HI 1 "register_operand" " r") 901 (parallel [(const_int 1)]))) 902 (sign_extend:SI 903 (vec_select:HI 904 (match_operand:V2HI 2 "register_operand" " r") 905 (parallel [(const_int 0)])))) 906 (const_int 1)))) 907 (vec_duplicate:V2HI 908 (truncate:HI 909 (ashiftrt:SI 910 (plus:SI 911 (sign_extend:SI 912 (vec_select:HI 913 (match_dup 2) 914 (parallel [(const_int 1)]))) 915 (sign_extend:SI 916 (vec_select:HI 917 (match_dup 1) 918 (parallel [(const_int 0)])))) 919 (const_int 1)))) 920 (const_int 2)))] 921 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 922 "rcras16\t%0, %1, %2" 923 [(set_attr "type" "dalu")] 924) 925 926(define_expand "urcras16_1" 927 [(match_operand:V2HI 0 "register_operand" "") 928 (match_operand:V2HI 1 "register_operand" "") 929 (match_operand:V2HI 2 "register_operand" "")] 930 "NDS32_EXT_DSP_P ()" 931{ 932 if (TARGET_BIG_ENDIAN) 933 emit_insn (gen_urcras16_1_be (operands[0], operands[1], operands[2])); 934 else 935 emit_insn (gen_urcras16_1_le (operands[0], operands[1], operands[2])); 936 DONE; 937}) 938 939(define_insn "urcras16_1_le" 940 [(set (match_operand:V2HI 0 "register_operand" "=r") 941 (vec_merge:V2HI 942 (vec_duplicate:V2HI 943 (truncate:HI 944 (lshiftrt:SI 945 (minus:SI 946 (zero_extend:SI 947 (vec_select:HI 948 (match_operand:V2HI 1 "register_operand" " r") 949 (parallel [(const_int 0)]))) 950 (zero_extend:SI 951 (vec_select:HI 952 (match_operand:V2HI 2 "register_operand" " r") 953 (parallel [(const_int 1)])))) 954 (const_int 1)))) 955 (vec_duplicate:V2HI 956 (truncate:HI 957 (lshiftrt:SI 958 (plus:SI 959 (zero_extend:SI 960 (vec_select:HI 961 (match_dup 2) 962 (parallel [(const_int 0)]))) 963 (zero_extend:SI 964 (vec_select:HI 965 (match_dup 1) 966 (parallel [(const_int 1)])))) 967 (const_int 1)))) 968 (const_int 1)))] 969 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 970 "urcras16\t%0, %1, %2" 971 [(set_attr "type" "dalu")] 972) 973 974(define_insn "urcras16_1_be" 975 [(set (match_operand:V2HI 0 "register_operand" "=r") 976 (vec_merge:V2HI 977 (vec_duplicate:V2HI 978 (truncate:HI 979 (lshiftrt:SI 980 (minus:SI 981 (zero_extend:SI 982 (vec_select:HI 983 (match_operand:V2HI 1 "register_operand" " r") 984 (parallel [(const_int 1)]))) 985 (zero_extend:SI 986 (vec_select:HI 987 (match_operand:V2HI 2 "register_operand" " r") 988 (parallel [(const_int 0)])))) 989 (const_int 1)))) 990 (vec_duplicate:V2HI 991 (truncate:HI 992 (lshiftrt:SI 993 (plus:SI 994 (zero_extend:SI 995 (vec_select:HI 996 (match_dup 2) 997 (parallel [(const_int 1)]))) 998 (zero_extend:SI 999 (vec_select:HI 1000 (match_dup 1) 1001 (parallel [(const_int 0)])))) 1002 (const_int 1)))) 1003 (const_int 2)))] 1004 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 1005 "urcras16\t%0, %1, %2" 1006 [(set_attr "type" "dalu")] 1007) 1008 1009(define_expand "rcrsa16_1" 1010 [(match_operand:V2HI 0 "register_operand" "") 1011 (match_operand:V2HI 1 "register_operand" "") 1012 (match_operand:V2HI 2 "register_operand" "")] 1013 "NDS32_EXT_DSP_P ()" 1014{ 1015 if (TARGET_BIG_ENDIAN) 1016 emit_insn (gen_rcrsa16_1_be (operands[0], operands[1], operands[2])); 1017 else 1018 emit_insn (gen_rcrsa16_1_le (operands[0], operands[1], operands[2])); 1019 DONE; 1020}) 1021 1022(define_insn "rcrsa16_1_le" 1023 [(set (match_operand:V2HI 0 "register_operand" "=r") 1024 (vec_merge:V2HI 1025 (vec_duplicate:V2HI 1026 (truncate:HI 1027 (ashiftrt:SI 1028 (minus:SI 1029 (sign_extend:SI 1030 (vec_select:HI 1031 (match_operand:V2HI 1 "register_operand" " r") 1032 (parallel [(const_int 1)]))) 1033 (sign_extend:SI 1034 (vec_select:HI 1035 (match_operand:V2HI 2 "register_operand" " r") 1036 (parallel [(const_int 0)])))) 1037 (const_int 1)))) 1038 (vec_duplicate:V2HI 1039 (truncate:HI 1040 (ashiftrt:SI 1041 (plus:SI 1042 (sign_extend:SI 1043 (vec_select:HI 1044 (match_dup 1) 1045 (parallel [(const_int 0)]))) 1046 (sign_extend:SI 1047 (vec_select:HI 1048 (match_dup 2) 1049 (parallel [(const_int 1)])))) 1050 (const_int 1)))) 1051 (const_int 2)))] 1052 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1053 "rcrsa16\t%0, %1, %2" 1054 [(set_attr "type" "dalu")] 1055) 1056 1057(define_insn "rcrsa16_1_be" 1058 [(set (match_operand:V2HI 0 "register_operand" "=r") 1059 (vec_merge:V2HI 1060 (vec_duplicate:V2HI 1061 (truncate:HI 1062 (ashiftrt:SI 1063 (minus:SI 1064 (sign_extend:SI 1065 (vec_select:HI 1066 (match_operand:V2HI 1 "register_operand" " r") 1067 (parallel [(const_int 0)]))) 1068 (sign_extend:SI 1069 (vec_select:HI 1070 (match_operand:V2HI 2 "register_operand" " r") 1071 (parallel [(const_int 1)])))) 1072 (const_int 1)))) 1073 (vec_duplicate:V2HI 1074 (truncate:HI 1075 (ashiftrt:SI 1076 (plus:SI 1077 (sign_extend:SI 1078 (vec_select:HI 1079 (match_dup 1) 1080 (parallel [(const_int 1)]))) 1081 (sign_extend:SI 1082 (vec_select:HI 1083 (match_dup 2) 1084 (parallel [(const_int 0)])))) 1085 (const_int 1)))) 1086 (const_int 1)))] 1087 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 1088 "rcrsa16\t%0, %1, %2" 1089 [(set_attr "type" "dalu")] 1090) 1091 1092(define_expand "urcrsa16_1" 1093 [(match_operand:V2HI 0 "register_operand" "") 1094 (match_operand:V2HI 1 "register_operand" "") 1095 (match_operand:V2HI 2 "register_operand" "")] 1096 "NDS32_EXT_DSP_P ()" 1097{ 1098 if (TARGET_BIG_ENDIAN) 1099 emit_insn (gen_urcrsa16_1_be (operands[0], operands[1], operands[2])); 1100 else 1101 emit_insn (gen_urcrsa16_1_le (operands[0], operands[1], operands[2])); 1102 DONE; 1103}) 1104 1105(define_insn "urcrsa16_1_le" 1106 [(set (match_operand:V2HI 0 "register_operand" "=r") 1107 (vec_merge:V2HI 1108 (vec_duplicate:V2HI 1109 (truncate:HI 1110 (lshiftrt:SI 1111 (minus:SI 1112 (zero_extend:SI 1113 (vec_select:HI 1114 (match_operand:V2HI 1 "register_operand" " r") 1115 (parallel [(const_int 1)]))) 1116 (zero_extend:SI 1117 (vec_select:HI 1118 (match_operand:V2HI 2 "register_operand" " r") 1119 (parallel [(const_int 0)])))) 1120 (const_int 1)))) 1121 (vec_duplicate:V2HI 1122 (truncate:HI 1123 (lshiftrt:SI 1124 (plus:SI 1125 (zero_extend:SI 1126 (vec_select:HI 1127 (match_dup 1) 1128 (parallel [(const_int 0)]))) 1129 (zero_extend:SI 1130 (vec_select:HI 1131 (match_dup 2) 1132 (parallel [(const_int 1)])))) 1133 (const_int 1)))) 1134 (const_int 2)))] 1135 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1136 "urcrsa16\t%0, %1, %2" 1137 [(set_attr "type" "dalu")] 1138) 1139 1140(define_insn "urcrsa16_1_be" 1141 [(set (match_operand:V2HI 0 "register_operand" "=r") 1142 (vec_merge:V2HI 1143 (vec_duplicate:V2HI 1144 (truncate:HI 1145 (lshiftrt:SI 1146 (minus:SI 1147 (zero_extend:SI 1148 (vec_select:HI 1149 (match_operand:V2HI 1 "register_operand" " r") 1150 (parallel [(const_int 0)]))) 1151 (zero_extend:SI 1152 (vec_select:HI 1153 (match_operand:V2HI 2 "register_operand" " r") 1154 (parallel [(const_int 1)])))) 1155 (const_int 1)))) 1156 (vec_duplicate:V2HI 1157 (truncate:HI 1158 (lshiftrt:SI 1159 (plus:SI 1160 (zero_extend:SI 1161 (vec_select:HI 1162 (match_dup 1) 1163 (parallel [(const_int 1)]))) 1164 (zero_extend:SI 1165 (vec_select:HI 1166 (match_dup 2) 1167 (parallel [(const_int 0)])))) 1168 (const_int 1)))) 1169 (const_int 1)))] 1170 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 1171 "urcrsa16\t%0, %1, %2" 1172 [(set_attr "type" "dalu")] 1173) 1174 1175(define_expand "<shift>v2hi3" 1176 [(set (match_operand:V2HI 0 "register_operand" "") 1177 (shifts:V2HI (match_operand:V2HI 1 "register_operand" "") 1178 (match_operand:SI 2 "nds32_rimm4u_operand" "")))] 1179 "NDS32_EXT_DSP_P ()" 1180{ 1181 if (operands[2] == const0_rtx) 1182 { 1183 emit_move_insn (operands[0], operands[1]); 1184 DONE; 1185 } 1186}) 1187 1188(define_insn "*ashlv2hi3" 1189 [(set (match_operand:V2HI 0 "register_operand" "= r, r") 1190 (ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r") 1191 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] 1192 "NDS32_EXT_DSP_P ()" 1193 "@ 1194 slli16\t%0, %1, %2 1195 sll16\t%0, %1, %2" 1196 [(set_attr "type" "dalu,dalu") 1197 (set_attr "length" " 4, 4")]) 1198 1199(define_insn "kslli16" 1200 [(set (match_operand:V2HI 0 "register_operand" "= r, r") 1201 (ss_ashift:V2HI (match_operand:V2HI 1 "register_operand" " r, r") 1202 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] 1203 "NDS32_EXT_DSP_P ()" 1204 "@ 1205 kslli16\t%0, %1, %2 1206 ksll16\t%0, %1, %2" 1207 [(set_attr "type" "dalu,dalu") 1208 (set_attr "length" " 4, 4")]) 1209 1210(define_insn "*ashrv2hi3" 1211 [(set (match_operand:V2HI 0 "register_operand" "= r, r") 1212 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") 1213 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] 1214 "NDS32_EXT_DSP_P ()" 1215 "@ 1216 srai16\t%0, %1, %2 1217 sra16\t%0, %1, %2" 1218 [(set_attr "type" "dalu,dalu") 1219 (set_attr "length" " 4, 4")]) 1220 1221(define_insn "sra16_round" 1222 [(set (match_operand:V2HI 0 "register_operand" "= r, r") 1223 (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") 1224 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))] 1225 UNSPEC_ROUND))] 1226 "NDS32_EXT_DSP_P ()" 1227 "@ 1228 srai16.u\t%0, %1, %2 1229 sra16.u\t%0, %1, %2" 1230 [(set_attr "type" "daluround,daluround") 1231 (set_attr "length" " 4, 4")]) 1232 1233(define_insn "*lshrv2hi3" 1234 [(set (match_operand:V2HI 0 "register_operand" "= r, r") 1235 (lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") 1236 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r")))] 1237 "NDS32_EXT_DSP_P ()" 1238 "@ 1239 srli16\t%0, %1, %2 1240 srl16\t%0, %1, %2" 1241 [(set_attr "type" "dalu,dalu") 1242 (set_attr "length" " 4, 4")]) 1243 1244(define_insn "srl16_round" 1245 [(set (match_operand:V2HI 0 "register_operand" "= r, r") 1246 (unspec:V2HI [(lshiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r, r") 1247 (match_operand:SI 2 "nds32_rimm4u_operand" " Iu04, r"))] 1248 UNSPEC_ROUND))] 1249 "NDS32_EXT_DSP_P ()" 1250 "@ 1251 srli16.u\t%0, %1, %2 1252 srl16.u\t%0, %1, %2" 1253 [(set_attr "type" "daluround,daluround") 1254 (set_attr "length" " 4, 4")]) 1255 1256(define_insn "kslra16" 1257 [(set (match_operand:V2HI 0 "register_operand" "=r") 1258 (if_then_else:V2HI 1259 (lt:SI (match_operand:SI 2 "register_operand" " r") 1260 (const_int 0)) 1261 (ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r") 1262 (neg:SI (match_dup 2))) 1263 (ashift:V2HI (match_dup 1) 1264 (match_dup 2))))] 1265 "NDS32_EXT_DSP_P ()" 1266 "kslra16\t%0, %1, %2" 1267 [(set_attr "type" "dalu") 1268 (set_attr "length" "4")]) 1269 1270(define_insn "kslra16_round" 1271 [(set (match_operand:V2HI 0 "register_operand" "=r") 1272 (if_then_else:V2HI 1273 (lt:SI (match_operand:SI 2 "register_operand" " r") 1274 (const_int 0)) 1275 (unspec:V2HI [(ashiftrt:V2HI (match_operand:V2HI 1 "register_operand" " r") 1276 (neg:SI (match_dup 2)))] 1277 UNSPEC_ROUND) 1278 (ashift:V2HI (match_dup 1) 1279 (match_dup 2))))] 1280 "NDS32_EXT_DSP_P ()" 1281 "kslra16.u\t%0, %1, %2" 1282 [(set_attr "type" "daluround") 1283 (set_attr "length" "4")]) 1284 1285(define_insn "cmpeq<bits>" 1286 [(set (match_operand:SI 0 "register_operand" "=r") 1287 (unspec:SI [(eq:SI (match_operand:VQIHI 1 "register_operand" " r") 1288 (match_operand:VQIHI 2 "register_operand" " r"))] 1289 UNSPEC_VEC_COMPARE))] 1290 "NDS32_EXT_DSP_P ()" 1291 "cmpeq<bits>\t%0, %1, %2" 1292 [(set_attr "type" "dcmp") 1293 (set_attr "length" "4")]) 1294 1295(define_insn "scmplt<bits>" 1296 [(set (match_operand:SI 0 "register_operand" "=r") 1297 (unspec:SI [(lt:SI (match_operand:VQIHI 1 "register_operand" " r") 1298 (match_operand:VQIHI 2 "register_operand" " r"))] 1299 UNSPEC_VEC_COMPARE))] 1300 "NDS32_EXT_DSP_P ()" 1301 "scmplt<bits>\t%0, %1, %2" 1302 [(set_attr "type" "dcmp") 1303 (set_attr "length" "4")]) 1304 1305(define_insn "scmple<bits>" 1306 [(set (match_operand:SI 0 "register_operand" "=r") 1307 (unspec:SI [(le:SI (match_operand:VQIHI 1 "register_operand" " r") 1308 (match_operand:VQIHI 2 "register_operand" " r"))] 1309 UNSPEC_VEC_COMPARE))] 1310 "NDS32_EXT_DSP_P ()" 1311 "scmple<bits>\t%0, %1, %2" 1312 [(set_attr "type" "dcmp") 1313 (set_attr "length" "4")]) 1314 1315(define_insn "ucmplt<bits>" 1316 [(set (match_operand:SI 0 "register_operand" "=r") 1317 (unspec:SI [(ltu:SI (match_operand:VQIHI 1 "register_operand" " r") 1318 (match_operand:VQIHI 2 "register_operand" " r"))] 1319 UNSPEC_VEC_COMPARE))] 1320 "NDS32_EXT_DSP_P ()" 1321 "ucmplt<bits>\t%0, %1, %2" 1322 [(set_attr "type" "dcmp") 1323 (set_attr "length" "4")]) 1324 1325(define_insn "ucmple<bits>" 1326 [(set (match_operand:SI 0 "register_operand" "=r") 1327 (unspec:SI [(leu:SI (match_operand:VQIHI 1 "register_operand" " r") 1328 (match_operand:VQIHI 2 "register_operand" " r"))] 1329 UNSPEC_VEC_COMPARE))] 1330 "NDS32_EXT_DSP_P ()" 1331 "ucmple<bits>\t%0, %1, %2" 1332 [(set_attr "type" "dcmp") 1333 (set_attr "length" "4")]) 1334 1335(define_insn "sclip16" 1336 [(set (match_operand:V2HI 0 "register_operand" "= r") 1337 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") 1338 (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")] 1339 UNSPEC_CLIPS))] 1340 "NDS32_EXT_DSP_P ()" 1341 "sclip16\t%0, %1, %2" 1342 [(set_attr "type" "dclip") 1343 (set_attr "length" "4")]) 1344 1345(define_insn "uclip16" 1346 [(set (match_operand:V2HI 0 "register_operand" "= r") 1347 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") 1348 (match_operand:SI 2 "nds32_imm4u_operand" " Iu04")] 1349 UNSPEC_CLIP))] 1350 "NDS32_EXT_DSP_P ()" 1351 "uclip16\t%0, %1, %2" 1352 [(set_attr "type" "dclip") 1353 (set_attr "length" "4")]) 1354 1355(define_insn "khm16" 1356 [(set (match_operand:V2HI 0 "register_operand" "=r") 1357 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") 1358 (match_operand:V2HI 2 "register_operand" " r")] 1359 UNSPEC_KHM))] 1360 "NDS32_EXT_DSP_P ()" 1361 "khm16\t%0, %1, %2" 1362 [(set_attr "type" "dmul") 1363 (set_attr "length" "4")]) 1364 1365(define_insn "khmx16" 1366 [(set (match_operand:V2HI 0 "register_operand" "=r") 1367 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" " r") 1368 (match_operand:V2HI 2 "register_operand" " r")] 1369 UNSPEC_KHMX))] 1370 "NDS32_EXT_DSP_P ()" 1371 "khmx16\t%0, %1, %2" 1372 [(set_attr "type" "dmul") 1373 (set_attr "length" "4")]) 1374 1375(define_expand "vec_setv4qi" 1376 [(match_operand:V4QI 0 "register_operand" "") 1377 (match_operand:QI 1 "register_operand" "") 1378 (match_operand:SI 2 "immediate_operand" "")] 1379 "NDS32_EXT_DSP_P ()" 1380{ 1381 HOST_WIDE_INT pos = INTVAL (operands[2]); 1382 if (pos > 4) 1383 gcc_unreachable (); 1384 HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos; 1385 emit_insn (gen_vec_setv4qi_internal (operands[0], operands[1], 1386 operands[0], GEN_INT (elem))); 1387 DONE; 1388}) 1389 1390(define_expand "insb" 1391 [(match_operand:V4QI 0 "register_operand" "") 1392 (match_operand:V4QI 1 "register_operand" "") 1393 (match_operand:SI 2 "register_operand" "") 1394 (match_operand:SI 3 "const_int_operand" "")] 1395 "NDS32_EXT_DSP_P ()" 1396{ 1397 if (INTVAL (operands[3]) > 3 || INTVAL (operands[3]) < 0) 1398 gcc_unreachable (); 1399 1400 rtx src = gen_reg_rtx (QImode); 1401 1402 convert_move (src, operands[2], false); 1403 1404 HOST_WIDE_INT selector_index; 1405 /* Big endian need reverse index. */ 1406 if (TARGET_BIG_ENDIAN) 1407 selector_index = 4 - INTVAL (operands[3]) - 1; 1408 else 1409 selector_index = INTVAL (operands[3]); 1410 rtx selector = gen_int_mode (1 << selector_index, SImode); 1411 emit_insn (gen_vec_setv4qi_internal (operands[0], src, 1412 operands[1], selector)); 1413 DONE; 1414}) 1415 1416(define_expand "insvsi" 1417 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "") 1418 (match_operand:SI 1 "const_int_operand" "") 1419 (match_operand:SI 2 "nds32_insv_operand" "")) 1420 (match_operand:SI 3 "register_operand" ""))] 1421 "NDS32_EXT_DSP_P ()" 1422{ 1423 if (INTVAL (operands[1]) != 8) 1424 FAIL; 1425} 1426 [(set_attr "type" "dinsb") 1427 (set_attr "length" "4")]) 1428 1429 1430(define_insn "insvsi_internal" 1431 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 1432 (const_int 8) 1433 (match_operand:SI 1 "nds32_insv_operand" "i")) 1434 (match_operand:SI 2 "register_operand" "r"))] 1435 "NDS32_EXT_DSP_P ()" 1436 "insb\t%0, %2, %v1" 1437 [(set_attr "type" "dinsb") 1438 (set_attr "length" "4")]) 1439 1440(define_insn "insvsiqi_internal" 1441 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 1442 (const_int 8) 1443 (match_operand:SI 1 "nds32_insv_operand" "i")) 1444 (zero_extend:SI (match_operand:QI 2 "register_operand" "r")))] 1445 "NDS32_EXT_DSP_P ()" 1446 "insb\t%0, %2, %v1" 1447 [(set_attr "type" "dinsb") 1448 (set_attr "length" "4")]) 1449 1450;; Intermedium pattern for synthetize insvsiqi_internal 1451;; v0 = ((v1 & 0xff) << 8) 1452(define_insn_and_split "and0xff_s8" 1453 [(set (match_operand:SI 0 "register_operand" "=r") 1454 (and:SI (ashift:SI (match_operand:SI 1 "register_operand" "r") 1455 (const_int 8)) 1456 (const_int 65280)))] 1457 "NDS32_EXT_DSP_P () && !reload_completed" 1458 "#" 1459 "NDS32_EXT_DSP_P () && !reload_completed" 1460 [(const_int 1)] 1461{ 1462 rtx tmp = gen_reg_rtx (SImode); 1463 emit_insn (gen_ashlsi3 (tmp, operands[1], gen_int_mode (8, SImode))); 1464 emit_insn (gen_andsi3 (operands[0], tmp, gen_int_mode (0xffff, SImode))); 1465 DONE; 1466}) 1467 1468;; v0 = (v1 & 0xff00ffff) | ((v2 << 16) | 0xff0000) 1469(define_insn_and_split "insbsi2" 1470 [(set (match_operand:SI 0 "register_operand" "=r") 1471 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "0") 1472 (const_int -16711681)) 1473 (and:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") 1474 (const_int 16)) 1475 (const_int 16711680))))] 1476 "NDS32_EXT_DSP_P () && !reload_completed" 1477 "#" 1478 "NDS32_EXT_DSP_P () && !reload_completed" 1479 [(const_int 1)] 1480{ 1481 rtx tmp = gen_reg_rtx (SImode); 1482 emit_move_insn (tmp, operands[1]); 1483 emit_insn (gen_insvsi_internal (tmp, gen_int_mode(16, SImode), operands[2])); 1484 emit_move_insn (operands[0], tmp); 1485 DONE; 1486}) 1487 1488;; v0 = (v1 & 0xff00ffff) | v2 1489(define_insn_and_split "ior_and0xff00ffff_reg" 1490 [(set (match_operand:SI 0 "register_operand" "=r") 1491 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") 1492 (const_int -16711681)) 1493 (match_operand:SI 2 "register_operand" "r")))] 1494 "NDS32_EXT_DSP_P () && !reload_completed" 1495 "#" 1496 "NDS32_EXT_DSP_P () && !reload_completed" 1497 [(const_int 1)] 1498{ 1499 rtx tmp = gen_reg_rtx (SImode); 1500 emit_insn (gen_andsi3 (tmp, operands[1], gen_int_mode (0xff00ffff, SImode))); 1501 emit_insn (gen_iorsi3 (operands[0], tmp, operands[2])); 1502 DONE; 1503}) 1504 1505(define_insn "vec_setv4qi_internal" 1506 [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r") 1507 (vec_merge:V4QI 1508 (vec_duplicate:V4QI 1509 (match_operand:QI 1 "register_operand" " r, r, r, r")) 1510 (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0") 1511 (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))] 1512 "NDS32_EXT_DSP_P ()" 1513{ 1514 if (TARGET_BIG_ENDIAN) 1515 { 1516 const char *pats[] = { "insb\t%0, %1, 3", 1517 "insb\t%0, %1, 2", 1518 "insb\t%0, %1, 1", 1519 "insb\t%0, %1, 0" }; 1520 return pats[which_alternative]; 1521 } 1522 else 1523 { 1524 const char *pats[] = { "insb\t%0, %1, 0", 1525 "insb\t%0, %1, 1", 1526 "insb\t%0, %1, 2", 1527 "insb\t%0, %1, 3" }; 1528 return pats[which_alternative]; 1529 } 1530} 1531 [(set_attr "type" "dinsb") 1532 (set_attr "length" "4")]) 1533 1534(define_insn "vec_setv4qi_internal_vec" 1535 [(set (match_operand:V4QI 0 "register_operand" "= r, r, r, r") 1536 (vec_merge:V4QI 1537 (vec_duplicate:V4QI 1538 (vec_select:QI 1539 (match_operand:V4QI 1 "register_operand" " r, r, r, r") 1540 (parallel [(const_int 0)]))) 1541 (match_operand:V4QI 2 "register_operand" " 0, 0, 0, 0") 1542 (match_operand:SI 3 "nds32_imm_1_2_4_8_operand" " Iv01, Iv02, Iv04, Iv08")))] 1543 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1544 "@ 1545 insb\t%0, %1, 0 1546 insb\t%0, %1, 1 1547 insb\t%0, %1, 2 1548 insb\t%0, %1, 3" 1549 [(set_attr "type" "dinsb") 1550 (set_attr "length" "4")]) 1551 1552(define_insn "vec_mergev4qi_and_cv0_1" 1553 [(set (match_operand:V4QI 0 "register_operand" "=$l,r") 1554 (vec_merge:V4QI 1555 (vec_duplicate:V4QI 1556 (vec_select:QI 1557 (match_operand:V4QI 1 "register_operand" " l,r") 1558 (parallel [(const_int 0)]))) 1559 (const_vector:V4QI [ 1560 (const_int 0) 1561 (const_int 0) 1562 (const_int 0) 1563 (const_int 0)]) 1564 (const_int 1)))] 1565 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1566 "@ 1567 zeb33\t%0, %1 1568 zeb\t%0, %1" 1569 [(set_attr "type" "alu,alu") 1570 (set_attr "length" " 2, 4")]) 1571 1572(define_insn "vec_mergev4qi_and_cv0_2" 1573 [(set (match_operand:V4QI 0 "register_operand" "=$l,r") 1574 (vec_merge:V4QI 1575 (const_vector:V4QI [ 1576 (const_int 0) 1577 (const_int 0) 1578 (const_int 0) 1579 (const_int 0)]) 1580 (vec_duplicate:V4QI 1581 (vec_select:QI 1582 (match_operand:V4QI 1 "register_operand" " l,r") 1583 (parallel [(const_int 0)]))) 1584 (const_int 2)))] 1585 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1586 "@ 1587 zeb33\t%0, %1 1588 zeb\t%0, %1" 1589 [(set_attr "type" "alu,alu") 1590 (set_attr "length" " 2, 4")]) 1591 1592(define_insn "vec_mergeqi_and_cv0_1" 1593 [(set (match_operand:V4QI 0 "register_operand" "=$l,r") 1594 (vec_merge:V4QI 1595 (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r")) 1596 (const_vector:V4QI [ 1597 (const_int 0) 1598 (const_int 0) 1599 (const_int 0) 1600 (const_int 0)]) 1601 (const_int 1)))] 1602 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1603 "@ 1604 zeb33\t%0, %1 1605 zeb\t%0, %1" 1606 [(set_attr "type" "alu,alu") 1607 (set_attr "length" " 2, 4")]) 1608 1609(define_insn "vec_mergeqi_and_cv0_2" 1610 [(set (match_operand:V4QI 0 "register_operand" "=$l,r") 1611 (vec_merge:V4QI 1612 (const_vector:V4QI [ 1613 (const_int 0) 1614 (const_int 0) 1615 (const_int 0) 1616 (const_int 0)]) 1617 (vec_duplicate:V4QI (match_operand:QI 1 "register_operand" " l,r")) 1618 (const_int 2)))] 1619 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1620 "@ 1621 zeb33\t%0, %1 1622 zeb\t%0, %1" 1623 [(set_attr "type" "alu,alu") 1624 (set_attr "length" " 2, 4")]) 1625 1626(define_expand "vec_setv2hi" 1627 [(match_operand:V2HI 0 "register_operand" "") 1628 (match_operand:HI 1 "register_operand" "") 1629 (match_operand:SI 2 "immediate_operand" "")] 1630 "NDS32_EXT_DSP_P ()" 1631{ 1632 HOST_WIDE_INT pos = INTVAL (operands[2]); 1633 if (pos > 2) 1634 gcc_unreachable (); 1635 HOST_WIDE_INT elem = (HOST_WIDE_INT) 1 << pos; 1636 emit_insn (gen_vec_setv2hi_internal (operands[0], operands[1], 1637 operands[0], GEN_INT (elem))); 1638 DONE; 1639}) 1640 1641(define_insn "vec_setv2hi_internal" 1642 [(set (match_operand:V2HI 0 "register_operand" "= r, r") 1643 (vec_merge:V2HI 1644 (vec_duplicate:V2HI 1645 (match_operand:HI 1 "register_operand" " r, r")) 1646 (match_operand:V2HI 2 "register_operand" " r, r") 1647 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))] 1648 "NDS32_EXT_DSP_P ()" 1649{ 1650 if (TARGET_BIG_ENDIAN) 1651 { 1652 const char *pats[] = { "pkbb16\t%0, %1, %2", 1653 "pktb16\t%0, %2, %1" }; 1654 return pats[which_alternative]; 1655 } 1656 else 1657 { 1658 const char *pats[] = { "pktb16\t%0, %2, %1", 1659 "pkbb16\t%0, %1, %2" }; 1660 return pats[which_alternative]; 1661 } 1662} 1663 [(set_attr "type" "dpack") 1664 (set_attr "length" "4")]) 1665 1666(define_insn "vec_mergev2hi_and_cv0_1" 1667 [(set (match_operand:V2HI 0 "register_operand" "=$l,r") 1668 (vec_merge:V2HI 1669 (vec_duplicate:V2HI 1670 (vec_select:HI 1671 (match_operand:V2HI 1 "register_operand" " l,r") 1672 (parallel [(const_int 0)]))) 1673 (const_vector:V2HI [ 1674 (const_int 0) 1675 (const_int 0)]) 1676 (const_int 1)))] 1677 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1678 "@ 1679 zeh33\t%0, %1 1680 zeh\t%0, %1" 1681 [(set_attr "type" "alu,alu") 1682 (set_attr "length" " 2, 4")]) 1683 1684(define_insn "vec_mergev2hi_and_cv0_2" 1685 [(set (match_operand:V2HI 0 "register_operand" "=$l,r") 1686 (vec_merge:V2HI 1687 (const_vector:V2HI [ 1688 (const_int 0) 1689 (const_int 0)]) 1690 (vec_duplicate:V2HI 1691 (vec_select:HI 1692 (match_operand:V2HI 1 "register_operand" " l,r") 1693 (parallel [(const_int 0)]))) 1694 (const_int 2)))] 1695 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1696 "@ 1697 zeh33\t%0, %1 1698 zeh\t%0, %1" 1699 [(set_attr "type" "alu,alu") 1700 (set_attr "length" " 2, 4")]) 1701 1702(define_insn "vec_mergehi_and_cv0_1" 1703 [(set (match_operand:V2HI 0 "register_operand" "=$l,r") 1704 (vec_merge:V2HI 1705 (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r")) 1706 (const_vector:V2HI [ 1707 (const_int 0) 1708 (const_int 0)]) 1709 (const_int 1)))] 1710 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1711 "@ 1712 zeh33\t%0, %1 1713 zeh\t%0, %1" 1714 [(set_attr "type" "alu,alu") 1715 (set_attr "length" " 2, 4")]) 1716 1717(define_insn "vec_mergehi_and_cv0_2" 1718 [(set (match_operand:V2HI 0 "register_operand" "=$l,r") 1719 (vec_merge:V2HI 1720 (const_vector:V2HI [ 1721 (const_int 0) 1722 (const_int 0)]) 1723 (vec_duplicate:V2HI (match_operand:HI 1 "register_operand" " l,r")) 1724 (const_int 2)))] 1725 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1726 "@ 1727 zeh33\t%0, %1 1728 zeh\t%0, %1" 1729 [(set_attr "type" "alu,alu") 1730 (set_attr "length" " 2, 4")]) 1731 1732(define_expand "pkbb" 1733 [(match_operand:V2HI 0 "register_operand") 1734 (match_operand:V2HI 1 "register_operand") 1735 (match_operand:V2HI 2 "register_operand")] 1736 "NDS32_EXT_DSP_P ()" 1737{ 1738 if (TARGET_BIG_ENDIAN) 1739 { 1740 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], 1741 GEN_INT (1), GEN_INT (1), GEN_INT (1))); 1742 } 1743 else 1744 { 1745 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], 1746 GEN_INT (2), GEN_INT (0), GEN_INT (0))); 1747 } 1748 DONE; 1749}) 1750 1751(define_insn "pkbbsi_1" 1752 [(set (match_operand:SI 0 "register_operand" "=r") 1753 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") 1754 (const_int 65535)) 1755 (ashift:SI (match_operand:SI 2 "register_operand" "r") 1756 (const_int 16))))] 1757 "NDS32_EXT_DSP_P ()" 1758 "pkbb16\t%0, %2, %1" 1759 [(set_attr "type" "dpack") 1760 (set_attr "length" "4")]) 1761 1762(define_insn "pkbbsi_2" 1763 [(set (match_operand:SI 0 "register_operand" "=r") 1764 (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") 1765 (const_int 16)) 1766 (and:SI (match_operand:SI 1 "register_operand" "r") 1767 (const_int 65535))))] 1768 "NDS32_EXT_DSP_P ()" 1769 "pkbb16\t%0, %2, %1" 1770 [(set_attr "type" "dpack") 1771 (set_attr "length" "4")]) 1772 1773(define_insn "pkbbsi_3" 1774 [(set (match_operand:SI 0 "register_operand" "=r") 1775 (ior:SI (zero_extend:SI (match_operand:HI 1 "register_operand" "r")) 1776 (ashift:SI (match_operand:SI 2 "register_operand" "r") 1777 (const_int 16))))] 1778 "NDS32_EXT_DSP_P ()" 1779 "pkbb16\t%0, %2, %1" 1780 [(set_attr "type" "dpack") 1781 (set_attr "length" "4")]) 1782 1783(define_insn "pkbbsi_4" 1784 [(set (match_operand:SI 0 "register_operand" "=r") 1785 (ior:SI (ashift:SI (match_operand:SI 2 "register_operand" "r") 1786 (const_int 16)) 1787 (zero_extend:SI (match_operand:HI 1 "register_operand" "r"))))] 1788 "NDS32_EXT_DSP_P ()" 1789 "pkbb16\t%0, %2, %1" 1790 [(set_attr "type" "dpack") 1791 (set_attr "length" "4")]) 1792 1793;; v0 = (v1 & 0xffff0000) | (v2 & 0xffff) 1794(define_insn "pktbsi_1" 1795 [(set (match_operand:SI 0 "register_operand" "=r") 1796 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") 1797 (const_int -65536)) 1798 (zero_extend:SI (match_operand:HI 2 "register_operand" "r"))))] 1799 "NDS32_EXT_DSP_P ()" 1800 "pktb16\t%0, %1, %2" 1801 [(set_attr "type" "dpack") 1802 (set_attr "length" "4")]) 1803 1804(define_insn "pktbsi_2" 1805 [(set (match_operand:SI 0 "register_operand" "=r") 1806 (ior:SI (and:SI (match_operand:SI 1 "register_operand" "r") 1807 (const_int -65536)) 1808 (and:SI (match_operand:SI 2 "register_operand" "r") 1809 (const_int 65535))))] 1810 "NDS32_EXT_DSP_P ()" 1811 "pktb16\t%0, %1, %2" 1812 [(set_attr "type" "alu") 1813 (set_attr "length" "4")]) 1814 1815(define_insn "pktbsi_3" 1816 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 1817 (const_int 16 ) 1818 (const_int 0)) 1819 (match_operand:SI 1 "register_operand" " r"))] 1820 "NDS32_EXT_DSP_P ()" 1821 "pktb16\t%0, %0, %1" 1822 [(set_attr "type" "dpack") 1823 (set_attr "length" "4")]) 1824 1825(define_insn "pktbsi_4" 1826 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+r") 1827 (const_int 16 ) 1828 (const_int 0)) 1829 (zero_extend:SI (match_operand:HI 1 "register_operand" " r")))] 1830 "NDS32_EXT_DSP_P ()" 1831 "pktb16\t%0, %0, %1" 1832 [(set_attr "type" "dpack") 1833 (set_attr "length" "4")]) 1834 1835(define_insn "pkttsi" 1836 [(set (match_operand:SI 0 "register_operand" "=r") 1837 (ior:SI (and:SI (match_operand:SI 1 "register_operand" " r") 1838 (const_int -65536)) 1839 (lshiftrt:SI (match_operand:SI 2 "register_operand" " r") 1840 (const_int 16))))] 1841 "NDS32_EXT_DSP_P ()" 1842 "pktt16\t%0, %1, %2" 1843 [(set_attr "type" "dpack") 1844 (set_attr "length" "4")]) 1845 1846(define_expand "pkbt" 1847 [(match_operand:V2HI 0 "register_operand") 1848 (match_operand:V2HI 1 "register_operand") 1849 (match_operand:V2HI 2 "register_operand")] 1850 "NDS32_EXT_DSP_P ()" 1851{ 1852 if (TARGET_BIG_ENDIAN) 1853 { 1854 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], 1855 GEN_INT (1), GEN_INT (1), GEN_INT (0))); 1856 } 1857 else 1858 { 1859 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], 1860 GEN_INT (2), GEN_INT (0), GEN_INT (1))); 1861 } 1862 DONE; 1863}) 1864 1865(define_expand "pktt" 1866 [(match_operand:V2HI 0 "register_operand") 1867 (match_operand:V2HI 1 "register_operand") 1868 (match_operand:V2HI 2 "register_operand")] 1869 "NDS32_EXT_DSP_P ()" 1870{ 1871 if (TARGET_BIG_ENDIAN) 1872 { 1873 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], 1874 GEN_INT (1), GEN_INT (0), GEN_INT (0))); 1875 } 1876 else 1877 { 1878 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], 1879 GEN_INT (2), GEN_INT (1), GEN_INT (1))); 1880 } 1881 DONE; 1882}) 1883 1884(define_expand "pktb" 1885 [(match_operand:V2HI 0 "register_operand") 1886 (match_operand:V2HI 1 "register_operand") 1887 (match_operand:V2HI 2 "register_operand")] 1888 "NDS32_EXT_DSP_P ()" 1889{ 1890 if (TARGET_BIG_ENDIAN) 1891 { 1892 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], 1893 GEN_INT (1), GEN_INT (0), GEN_INT (1))); 1894 } 1895 else 1896 { 1897 emit_insn (gen_vec_mergevv (operands[0], operands[1], operands[2], 1898 GEN_INT (2), GEN_INT (1), GEN_INT (0))); 1899 } 1900 DONE; 1901}) 1902 1903(define_insn "vec_mergerr" 1904 [(set (match_operand:V2HI 0 "register_operand" "= r, r") 1905 (vec_merge:V2HI 1906 (vec_duplicate:V2HI 1907 (match_operand:HI 1 "register_operand" " r, r")) 1908 (vec_duplicate:V2HI 1909 (match_operand:HI 2 "register_operand" " r, r")) 1910 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))] 1911 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1912 "@ 1913 pkbb16\t%0, %2, %1 1914 pkbb16\t%0, %1, %2" 1915 [(set_attr "type" "dpack") 1916 (set_attr "length" "4")]) 1917 1918 1919(define_insn "vec_merge" 1920 [(set (match_operand:V2HI 0 "register_operand" "= r, r") 1921 (vec_merge:V2HI 1922 (match_operand:V2HI 1 "register_operand" " r, r") 1923 (match_operand:V2HI 2 "register_operand" " r, r") 1924 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv02")))] 1925 "NDS32_EXT_DSP_P ()" 1926{ 1927 if (TARGET_BIG_ENDIAN) 1928 { 1929 const char *pats[] = { "pktb16\t%0, %1, %2", 1930 "pktb16\t%0, %2, %1" }; 1931 return pats[which_alternative]; 1932 } 1933 else 1934 { 1935 const char *pats[] = { "pktb16\t%0, %2, %1", 1936 "pktb16\t%0, %1, %2" }; 1937 return pats[which_alternative]; 1938 } 1939} 1940 [(set_attr "type" "dpack") 1941 (set_attr "length" "4")]) 1942 1943(define_insn "vec_mergerv" 1944 [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r") 1945 (vec_merge:V2HI 1946 (vec_duplicate:V2HI 1947 (match_operand:HI 1 "register_operand" " r, r, r, r")) 1948 (vec_duplicate:V2HI 1949 (vec_select:HI 1950 (match_operand:V2HI 2 "register_operand" " r, r, r, r") 1951 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")]))) 1952 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))] 1953 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1954 "@ 1955 pkbb16\t%0, %2, %1 1956 pktb16\t%0, %2, %1 1957 pkbb16\t%0, %1, %2 1958 pkbt16\t%0, %1, %2" 1959 [(set_attr "type" "dpack") 1960 (set_attr "length" "4")]) 1961 1962(define_insn "vec_mergevr" 1963 [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r") 1964 (vec_merge:V2HI 1965 (vec_duplicate:V2HI 1966 (vec_select:HI 1967 (match_operand:V2HI 1 "register_operand" " r, r, r, r") 1968 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv00, Iv01")]))) 1969 (vec_duplicate:V2HI 1970 (match_operand:HI 2 "register_operand" " r, r, r, r")) 1971 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv02, Iv02")))] 1972 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 1973 "@ 1974 pkbb16\t%0, %2, %1 1975 pkbt16\t%0, %2, %1 1976 pkbb16\t%0, %1, %2 1977 pktb16\t%0, %1, %2" 1978 [(set_attr "type" "dpack") 1979 (set_attr "length" "4")]) 1980 1981(define_insn "vec_mergevv" 1982 [(set (match_operand:V2HI 0 "register_operand" "= r, r, r, r, r, r, r, r") 1983 (vec_merge:V2HI 1984 (vec_duplicate:V2HI 1985 (vec_select:HI 1986 (match_operand:V2HI 1 "register_operand" " r, r, r, r, r, r, r, r") 1987 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01")]))) 1988 (vec_duplicate:V2HI 1989 (vec_select:HI 1990 (match_operand:V2HI 2 "register_operand" " r, r, r, r, r, r, r, r") 1991 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00, Iv00, Iv01, Iv01, Iv00")]))) 1992 (match_operand:SI 3 "nds32_imm_1_2_operand" " Iv01, Iv01, Iv01, Iv01, Iv02, Iv02, Iv02, Iv02")))] 1993 "NDS32_EXT_DSP_P ()" 1994{ 1995 if (TARGET_BIG_ENDIAN) 1996 { 1997 const char *pats[] = { "pktt16\t%0, %1, %2", 1998 "pktb16\t%0, %1, %2", 1999 "pkbb16\t%0, %1, %2", 2000 "pkbt16\t%0, %1, %2", 2001 "pktt16\t%0, %2, %1", 2002 "pkbt16\t%0, %2, %1", 2003 "pkbb16\t%0, %2, %1", 2004 "pktb16\t%0, %2, %1" }; 2005 return pats[which_alternative]; 2006 } 2007 else 2008 { 2009 const char *pats[] = { "pkbb16\t%0, %2, %1", 2010 "pktb16\t%0, %2, %1", 2011 "pktt16\t%0, %2, %1", 2012 "pkbt16\t%0, %2, %1", 2013 "pkbb16\t%0, %1, %2", 2014 "pkbt16\t%0, %1, %2", 2015 "pktt16\t%0, %1, %2", 2016 "pktb16\t%0, %1, %2" }; 2017 return pats[which_alternative]; 2018 } 2019} 2020 [(set_attr "type" "dpack") 2021 (set_attr "length" "4")]) 2022 2023(define_expand "vec_extractv4qi" 2024 [(set (match_operand:QI 0 "register_operand" "") 2025 (vec_select:QI 2026 (match_operand:V4QI 1 "nonimmediate_operand" "") 2027 (parallel [(match_operand:SI 2 "const_int_operand" "")])))] 2028 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2029{ 2030 if (INTVAL (operands[2]) != 0 2031 && INTVAL (operands[2]) != 1 2032 && INTVAL (operands[2]) != 2 2033 && INTVAL (operands[2]) != 3) 2034 gcc_unreachable (); 2035 2036 if (INTVAL (operands[2]) != 0 && MEM_P (operands[0])) 2037 FAIL; 2038}) 2039 2040(define_insn "vec_extractv4qi0" 2041 [(set (match_operand:QI 0 "register_operand" "=l,r,r") 2042 (vec_select:QI 2043 (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m") 2044 (parallel [(const_int 0)])))] 2045 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2046{ 2047 switch (which_alternative) 2048 { 2049 case 0: 2050 return "zeb33\t%0, %1"; 2051 case 1: 2052 return "zeb\t%0, %1"; 2053 case 2: 2054 return nds32_output_32bit_load (operands, 1); 2055 default: 2056 gcc_unreachable (); 2057 } 2058} 2059 [(set_attr "type" "alu") 2060 (set_attr "length" "4")]) 2061 2062(define_insn "vec_extractv4qi0_ze" 2063 [(set (match_operand:SI 0 "register_operand" "=l,r,r") 2064 (zero_extend:SI 2065 (vec_select:QI 2066 (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m") 2067 (parallel [(const_int 0)]))))] 2068 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2069{ 2070 switch (which_alternative) 2071 { 2072 case 0: 2073 return "zeb33\t%0, %1"; 2074 case 1: 2075 return "zeb\t%0, %1"; 2076 case 2: 2077 return nds32_output_32bit_load (operands, 1); 2078 default: 2079 gcc_unreachable (); 2080 } 2081} 2082 [(set_attr "type" "alu") 2083 (set_attr "length" "4")]) 2084 2085(define_insn "vec_extractv4qi0_se" 2086 [(set (match_operand:SI 0 "register_operand" "=l,r,r") 2087 (sign_extend:SI 2088 (vec_select:QI 2089 (match_operand:V4QI 1 "nonimmediate_operand" " l,r,m") 2090 (parallel [(const_int 0)]))))] 2091 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2092{ 2093 switch (which_alternative) 2094 { 2095 case 0: 2096 return "seb33\t%0, %1"; 2097 case 1: 2098 return "seb\t%0, %1"; 2099 case 2: 2100 return nds32_output_32bit_load_s (operands, 1); 2101 default: 2102 gcc_unreachable (); 2103 } 2104} 2105 [(set_attr "type" "alu") 2106 (set_attr "length" "4")]) 2107 2108(define_insn_and_split "vec_extractv4qi1" 2109 [(set (match_operand:QI 0 "register_operand" "=r") 2110 (vec_select:QI 2111 (match_operand:V4QI 1 "register_operand" " r") 2112 (parallel [(const_int 1)])))] 2113 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 2114 "#" 2115 "NDS32_EXT_DSP_P () && !reload_completed" 2116 [(const_int 1)] 2117{ 2118 rtx tmp = gen_reg_rtx (V4QImode); 2119 emit_insn (gen_rotrv4qi_1 (tmp, operands[1])); 2120 emit_insn (gen_vec_extractv4qi0 (operands[0], tmp)); 2121 DONE; 2122} 2123 [(set_attr "type" "alu") 2124 (set_attr "length" "4")]) 2125 2126(define_insn_and_split "vec_extractv4qi2" 2127 [(set (match_operand:QI 0 "register_operand" "=r") 2128 (vec_select:QI 2129 (match_operand:V4QI 1 "register_operand" " r") 2130 (parallel [(const_int 2)])))] 2131 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 2132 "#" 2133 "NDS32_EXT_DSP_P () && !reload_completed" 2134 [(const_int 1)] 2135{ 2136 rtx tmp = gen_reg_rtx (V4QImode); 2137 emit_insn (gen_rotrv4qi_2 (tmp, operands[1])); 2138 emit_insn (gen_vec_extractv4qi0 (operands[0], tmp)); 2139 DONE; 2140} 2141 [(set_attr "type" "alu") 2142 (set_attr "length" "4")]) 2143 2144(define_insn_and_split "vec_extractv4qi3" 2145 [(set (match_operand:QI 0 "register_operand" "=r") 2146 (vec_select:QI 2147 (match_operand:V4QI 1 "register_operand" " r") 2148 (parallel [(const_int 3)])))] 2149 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 2150 "#" 2151 "NDS32_EXT_DSP_P () && !reload_completed" 2152 [(const_int 1)] 2153{ 2154 rtx tmp = gen_reg_rtx (V4QImode); 2155 emit_insn (gen_rotrv4qi_3 (tmp, operands[1])); 2156 emit_insn (gen_vec_extractv4qi0 (operands[0], tmp)); 2157 DONE; 2158} 2159 [(set_attr "type" "alu") 2160 (set_attr "length" "4")]) 2161 2162(define_insn "vec_extractv4qi3_se" 2163 [(set (match_operand:SI 0 "register_operand" "=$d,r") 2164 (sign_extend:SI 2165 (vec_select:QI 2166 (match_operand:V4QI 1 "register_operand" " 0,r") 2167 (parallel [(const_int 3)]))))] 2168 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2169 "@ 2170 srai45\t%0, 24 2171 srai\t%0, %1, 24" 2172 [(set_attr "type" "alu,alu") 2173 (set_attr "length" " 2, 4")]) 2174 2175(define_insn "vec_extractv4qi3_ze" 2176 [(set (match_operand:SI 0 "register_operand" "=$d,r") 2177 (zero_extend:SI 2178 (vec_select:QI 2179 (match_operand:V4QI 1 "register_operand" " 0,r") 2180 (parallel [(const_int 3)]))))] 2181 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2182 "@ 2183 srli45\t%0, 24 2184 srli\t%0, %1, 24" 2185 [(set_attr "type" "alu,alu") 2186 (set_attr "length" " 2, 4")]) 2187 2188(define_insn_and_split "vec_extractv4qihi0" 2189 [(set (match_operand:HI 0 "register_operand" "=r") 2190 (sign_extend:HI 2191 (vec_select:QI 2192 (match_operand:V4QI 1 "register_operand" " r") 2193 (parallel [(const_int 0)]))))] 2194 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 2195 "#" 2196 "NDS32_EXT_DSP_P () && !reload_completed" 2197 [(const_int 1)] 2198{ 2199 rtx tmp = gen_reg_rtx (QImode); 2200 emit_insn (gen_vec_extractv4qi0 (tmp, operands[1])); 2201 emit_insn (gen_extendqihi2 (operands[0], tmp)); 2202 DONE; 2203} 2204 [(set_attr "type" "alu") 2205 (set_attr "length" "4")]) 2206 2207(define_insn_and_split "vec_extractv4qihi1" 2208 [(set (match_operand:HI 0 "register_operand" "=r") 2209 (sign_extend:HI 2210 (vec_select:QI 2211 (match_operand:V4QI 1 "register_operand" " r") 2212 (parallel [(const_int 1)]))))] 2213 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 2214 "#" 2215 "NDS32_EXT_DSP_P () && !reload_completed" 2216 [(const_int 1)] 2217{ 2218 rtx tmp = gen_reg_rtx (QImode); 2219 emit_insn (gen_vec_extractv4qi1 (tmp, operands[1])); 2220 emit_insn (gen_extendqihi2 (operands[0], tmp)); 2221 DONE; 2222} 2223 [(set_attr "type" "alu") 2224 (set_attr "length" "4")]) 2225 2226(define_insn_and_split "vec_extractv4qihi2" 2227 [(set (match_operand:HI 0 "register_operand" "=r") 2228 (sign_extend:HI 2229 (vec_select:QI 2230 (match_operand:V4QI 1 "register_operand" " r") 2231 (parallel [(const_int 2)]))))] 2232 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 2233 "#" 2234 "NDS32_EXT_DSP_P () && !reload_completed" 2235 [(const_int 1)] 2236{ 2237 rtx tmp = gen_reg_rtx (QImode); 2238 emit_insn (gen_vec_extractv4qi2 (tmp, operands[1])); 2239 emit_insn (gen_extendqihi2 (operands[0], tmp)); 2240 DONE; 2241} 2242 [(set_attr "type" "alu") 2243 (set_attr "length" "4")]) 2244 2245(define_insn_and_split "vec_extractv4qihi3" 2246 [(set (match_operand:HI 0 "register_operand" "=r") 2247 (sign_extend:HI 2248 (vec_select:QI 2249 (match_operand:V4QI 1 "register_operand" " r") 2250 (parallel [(const_int 3)]))))] 2251 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 2252 "#" 2253 "NDS32_EXT_DSP_P () && !reload_completed" 2254 [(const_int 1)] 2255{ 2256 rtx tmp = gen_reg_rtx (QImode); 2257 emit_insn (gen_vec_extractv4qi3 (tmp, operands[1])); 2258 emit_insn (gen_extendqihi2 (operands[0], tmp)); 2259 DONE; 2260} 2261 [(set_attr "type" "alu") 2262 (set_attr "length" "4")]) 2263 2264(define_expand "vec_extractv2hi" 2265 [(set (match_operand:HI 0 "register_operand" "") 2266 (vec_select:HI 2267 (match_operand:V2HI 1 "nonimmediate_operand" "") 2268 (parallel [(match_operand:SI 2 "const_int_operand" "")])))] 2269 "NDS32_EXT_DSP_P ()" 2270{ 2271 if (INTVAL (operands[2]) != 0 2272 && INTVAL (operands[2]) != 1) 2273 gcc_unreachable (); 2274 2275 if (INTVAL (operands[2]) != 0 && MEM_P (operands[0])) 2276 FAIL; 2277}) 2278 2279(define_insn "vec_extractv2hi0" 2280 [(set (match_operand:HI 0 "register_operand" "=$l,r,r") 2281 (vec_select:HI 2282 (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m") 2283 (parallel [(const_int 0)])))] 2284 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2285{ 2286 switch (which_alternative) 2287 { 2288 case 0: 2289 return "seh33\t%0, %1"; 2290 case 1: 2291 return "seh\t%0, %1"; 2292 case 2: 2293 return nds32_output_32bit_load_s (operands, 2); 2294 2295 default: 2296 gcc_unreachable (); 2297 } 2298} 2299 [(set_attr "type" "alu,alu,load") 2300 (set_attr "length" " 2, 4, 4")]) 2301 2302(define_insn "vec_extractv2hi0_ze" 2303 [(set (match_operand:SI 0 "register_operand" "=$l, r,$ l, *r") 2304 (zero_extend:SI 2305 (vec_select:HI 2306 (match_operand:V2HI 1 "nonimmediate_operand" " l, r, U33, m") 2307 (parallel [(const_int 0)]))))] 2308 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2309{ 2310 switch (which_alternative) 2311 { 2312 case 0: 2313 return "zeh33\t%0, %1"; 2314 case 1: 2315 return "zeh\t%0, %1"; 2316 case 2: 2317 return nds32_output_16bit_load (operands, 2); 2318 case 3: 2319 return nds32_output_32bit_load (operands, 2); 2320 2321 default: 2322 gcc_unreachable (); 2323 } 2324} 2325 [(set_attr "type" "alu,alu,load,load") 2326 (set_attr "length" " 2, 4, 2, 4")]) 2327 2328(define_insn "vec_extractv2hi0_se" 2329 [(set (match_operand:SI 0 "register_operand" "=$l, r, r") 2330 (sign_extend:SI 2331 (vec_select:HI 2332 (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m") 2333 (parallel [(const_int 0)]))))] 2334 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2335{ 2336 switch (which_alternative) 2337 { 2338 case 0: 2339 return "seh33\t%0, %1"; 2340 case 1: 2341 return "seh\t%0, %1"; 2342 case 2: 2343 return nds32_output_32bit_load_s (operands, 2); 2344 2345 default: 2346 gcc_unreachable (); 2347 } 2348} 2349 [(set_attr "type" "alu,alu,load") 2350 (set_attr "length" " 2, 4, 4")]) 2351 2352(define_insn "vec_extractv2hi0_be" 2353 [(set (match_operand:HI 0 "register_operand" "=$d,r") 2354 (vec_select:HI 2355 (match_operand:V2HI 1 "register_operand" " 0,r") 2356 (parallel [(const_int 0)])))] 2357 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2358 "@ 2359 srai45\t%0, 16 2360 srai\t%0, %1, 16" 2361 [(set_attr "type" "alu,alu") 2362 (set_attr "length" " 2, 4")]) 2363 2364(define_insn "vec_extractv2hi1" 2365 [(set (match_operand:HI 0 "register_operand" "=$d,r") 2366 (vec_select:HI 2367 (match_operand:V2HI 1 "register_operand" " 0,r") 2368 (parallel [(const_int 1)])))] 2369 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2370 "@ 2371 srai45\t%0, 16 2372 srai\t%0, %1, 16" 2373 [(set_attr "type" "alu,alu") 2374 (set_attr "length" " 2, 4")]) 2375 2376(define_insn "vec_extractv2hi1_se" 2377 [(set (match_operand:SI 0 "register_operand" "=$d,r") 2378 (sign_extend:SI 2379 (vec_select:HI 2380 (match_operand:V2HI 1 "register_operand" " 0,r") 2381 (parallel [(const_int 1)]))))] 2382 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2383 "@ 2384 srai45\t%0, 16 2385 srai\t%0, %1, 16" 2386 [(set_attr "type" "alu,alu") 2387 (set_attr "length" " 2, 4")]) 2388 2389(define_insn "vec_extractv2hi1_ze" 2390 [(set (match_operand:SI 0 "register_operand" "=$d,r") 2391 (zero_extend:SI 2392 (vec_select:HI 2393 (match_operand:V2HI 1 "register_operand" " 0,r") 2394 (parallel [(const_int 1)]))))] 2395 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2396 "@ 2397 srli45\t%0, 16 2398 srli\t%0, %1, 16" 2399 [(set_attr "type" "alu,alu") 2400 (set_attr "length" " 2, 4")]) 2401 2402(define_insn "vec_extractv2hi1_be" 2403 [(set (match_operand:HI 0 "register_operand" "=$l,r,r") 2404 (vec_select:HI 2405 (match_operand:V2HI 1 "nonimmediate_operand" " l,r,m") 2406 (parallel [(const_int 1)])))] 2407 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2408{ 2409 switch (which_alternative) 2410 { 2411 case 0: 2412 return "seh33\t%0, %1"; 2413 case 1: 2414 return "seh\t%0, %1"; 2415 case 2: 2416 return nds32_output_32bit_load_s (operands, 2); 2417 2418 default: 2419 gcc_unreachable (); 2420 } 2421} 2422 [(set_attr "type" "alu,alu,load") 2423 (set_attr "length" " 2, 4, 4")]) 2424 2425(define_insn "<su>mul16" 2426 [(set (match_operand:V2SI 0 "register_operand" "=r") 2427 (mult:V2SI (extend:V2SI (match_operand:V2HI 1 "register_operand" "%r")) 2428 (extend:V2SI (match_operand:V2HI 2 "register_operand" " r"))))] 2429 "NDS32_EXT_DSP_P ()" 2430 "<su>mul16\t%0, %1, %2" 2431 [(set_attr "type" "dmul") 2432 (set_attr "length" "4")]) 2433 2434(define_insn "<su>mulx16" 2435 [(set (match_operand:V2SI 0 "register_operand" "=r") 2436 (vec_merge:V2SI 2437 (vec_duplicate:V2SI 2438 (mult:SI 2439 (extend:SI 2440 (vec_select:HI 2441 (match_operand:V2HI 1 "register_operand" " r") 2442 (parallel [(const_int 0)]))) 2443 (extend:SI 2444 (vec_select:HI 2445 (match_operand:V2HI 2 "register_operand" " r") 2446 (parallel [(const_int 1)]))))) 2447 (vec_duplicate:V2SI 2448 (mult:SI 2449 (extend:SI 2450 (vec_select:HI 2451 (match_dup 1) 2452 (parallel [(const_int 1)]))) 2453 (extend:SI 2454 (vec_select:HI 2455 (match_dup 2) 2456 (parallel [(const_int 0)]))))) 2457 (const_int 1)))] 2458 "NDS32_EXT_DSP_P ()" 2459 "<su>mulx16\t%0, %1, %2" 2460 [(set_attr "type" "dmul") 2461 (set_attr "length" "4")]) 2462 2463(define_insn "rotrv2hi_1" 2464 [(set (match_operand:V2HI 0 "register_operand" "=r") 2465 (vec_select:V2HI 2466 (match_operand:V2HI 1 "register_operand" " r") 2467 (parallel [(const_int 1) (const_int 0)])))] 2468 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2469 "rotri\t%0, %1, 16" 2470 [(set_attr "type" "alu") 2471 (set_attr "length" "4")]) 2472 2473(define_insn "rotrv2hi_1_be" 2474 [(set (match_operand:V2HI 0 "register_operand" "=r") 2475 (vec_select:V2HI 2476 (match_operand:V2HI 1 "register_operand" " r") 2477 (parallel [(const_int 0) (const_int 1)])))] 2478 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2479 "rotri\t%0, %1, 16" 2480 [(set_attr "type" "alu") 2481 (set_attr "length" "4")]) 2482 2483(define_insn "rotrv4qi_1" 2484 [(set (match_operand:V4QI 0 "register_operand" "=r") 2485 (vec_select:V4QI 2486 (match_operand:V4QI 1 "register_operand" " r") 2487 (parallel [(const_int 1) (const_int 2) (const_int 3) (const_int 0)])))] 2488 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2489 "rotri\t%0, %1, 8" 2490 [(set_attr "type" "alu") 2491 (set_attr "length" "4")]) 2492 2493(define_insn "rotrv4qi_1_be" 2494 [(set (match_operand:V4QI 0 "register_operand" "=r") 2495 (vec_select:V4QI 2496 (match_operand:V4QI 1 "register_operand" " r") 2497 (parallel [(const_int 2) (const_int 1) (const_int 0) (const_int 3)])))] 2498 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2499 "rotri\t%0, %1, 8" 2500 [(set_attr "type" "alu") 2501 (set_attr "length" "4")]) 2502 2503(define_insn "rotrv4qi_2" 2504 [(set (match_operand:V4QI 0 "register_operand" "=r") 2505 (vec_select:V4QI 2506 (match_operand:V4QI 1 "register_operand" " r") 2507 (parallel [(const_int 2) (const_int 3) (const_int 0) (const_int 1)])))] 2508 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2509 "rotri\t%0, %1, 16" 2510 [(set_attr "type" "alu") 2511 (set_attr "length" "4")]) 2512 2513(define_insn "rotrv4qi_2_be" 2514 [(set (match_operand:V4QI 0 "register_operand" "=r") 2515 (vec_select:V4QI 2516 (match_operand:V4QI 1 "register_operand" " r") 2517 (parallel [(const_int 1) (const_int 0) (const_int 3) (const_int 2)])))] 2518 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2519 "rotri\t%0, %1, 16" 2520 [(set_attr "type" "alu") 2521 (set_attr "length" "4")]) 2522 2523(define_insn "rotrv4qi_3" 2524 [(set (match_operand:V4QI 0 "register_operand" "=r") 2525 (vec_select:V4QI 2526 (match_operand:V4QI 1 "register_operand" " r") 2527 (parallel [(const_int 3) (const_int 0) (const_int 1) (const_int 2)])))] 2528 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2529 "rotri\t%0, %1, 24" 2530 [(set_attr "type" "alu") 2531 (set_attr "length" "4")]) 2532 2533(define_insn "rotrv4qi_3_be" 2534 [(set (match_operand:V4QI 0 "register_operand" "=r") 2535 (vec_select:V4QI 2536 (match_operand:V4QI 1 "register_operand" " r") 2537 (parallel [(const_int 0) (const_int 3) (const_int 2) (const_int 1)])))] 2538 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2539 "rotri\t%0, %1, 24" 2540 [(set_attr "type" "alu") 2541 (set_attr "length" "4")]) 2542 2543(define_insn "v4qi_dup_10" 2544 [(set (match_operand:V4QI 0 "register_operand" "=r") 2545 (vec_select:V4QI 2546 (match_operand:V4QI 1 "register_operand" " r") 2547 (parallel [(const_int 0) (const_int 1) (const_int 0) (const_int 1)])))] 2548 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2549 "pkbb\t%0, %1, %1" 2550 [(set_attr "type" "dpack") 2551 (set_attr "length" "4")]) 2552 2553(define_insn "v4qi_dup_32" 2554 [(set (match_operand:V4QI 0 "register_operand" "=r") 2555 (vec_select:V4QI 2556 (match_operand:V4QI 1 "register_operand" " r") 2557 (parallel [(const_int 2) (const_int 3) (const_int 2) (const_int 3)])))] 2558 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2559 "pktt\t%0, %1, %1" 2560 [(set_attr "type" "dpack") 2561 (set_attr "length" "4")]) 2562 2563(define_expand "vec_unpacks_lo_v4qi" 2564 [(match_operand:V2HI 0 "register_operand" "=r") 2565 (match_operand:V4QI 1 "register_operand" " r")] 2566 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2567{ 2568 emit_insn (gen_sunpkd810 (operands[0], operands[1])); 2569 DONE; 2570}) 2571 2572(define_expand "sunpkd810" 2573 [(match_operand:V2HI 0 "register_operand") 2574 (match_operand:V4QI 1 "register_operand")] 2575 "NDS32_EXT_DSP_P ()" 2576{ 2577 if (TARGET_BIG_ENDIAN) 2578 emit_insn (gen_sunpkd810_imp_be (operands[0], operands[1])); 2579 else 2580 emit_insn (gen_sunpkd810_imp (operands[0], operands[1])); 2581 DONE; 2582}) 2583 2584(define_insn "<zs>unpkd810_imp" 2585 [(set (match_operand:V2HI 0 "register_operand" "=r") 2586 (vec_merge:V2HI 2587 (vec_duplicate:V2HI 2588 (extend:HI 2589 (vec_select:QI 2590 (match_operand:V4QI 1 "register_operand" " r") 2591 (parallel [(const_int 1)])))) 2592 (vec_duplicate:V2HI 2593 (extend:HI 2594 (vec_select:QI 2595 (match_dup 1) 2596 (parallel [(const_int 0)])))) 2597 (const_int 2)))] 2598 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2599 "<zs>unpkd810\t%0, %1" 2600 [(set_attr "type" "dpack") 2601 (set_attr "length" "4")]) 2602 2603(define_insn "<zs>unpkd810_imp_inv" 2604 [(set (match_operand:V2HI 0 "register_operand" "=r") 2605 (vec_merge:V2HI 2606 (vec_duplicate:V2HI 2607 (extend:HI 2608 (vec_select:QI 2609 (match_operand:V4QI 1 "register_operand" " r") 2610 (parallel [(const_int 0)])))) 2611 (vec_duplicate:V2HI 2612 (extend:HI 2613 (vec_select:QI 2614 (match_dup 1) 2615 (parallel [(const_int 1)])))) 2616 (const_int 1)))] 2617 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2618 "<zs>unpkd810\t%0, %1" 2619 [(set_attr "type" "dpack") 2620 (set_attr "length" "4")]) 2621 2622(define_insn "<zs>unpkd810_imp_be" 2623 [(set (match_operand:V2HI 0 "register_operand" "=r") 2624 (vec_merge:V2HI 2625 (vec_duplicate:V2HI 2626 (extend:HI 2627 (vec_select:QI 2628 (match_operand:V4QI 1 "register_operand" " r") 2629 (parallel [(const_int 2)])))) 2630 (vec_duplicate:V2HI 2631 (extend:HI 2632 (vec_select:QI 2633 (match_dup 1) 2634 (parallel [(const_int 3)])))) 2635 (const_int 1)))] 2636 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2637 "<zs>unpkd810\t%0, %1" 2638 [(set_attr "type" "dpack") 2639 (set_attr "length" "4")]) 2640 2641(define_insn "<zs>unpkd810_imp_inv_be" 2642 [(set (match_operand:V2HI 0 "register_operand" "=r") 2643 (vec_merge:V2HI 2644 (vec_duplicate:V2HI 2645 (extend:HI 2646 (vec_select:QI 2647 (match_operand:V4QI 1 "register_operand" " r") 2648 (parallel [(const_int 3)])))) 2649 (vec_duplicate:V2HI 2650 (extend:HI 2651 (vec_select:QI 2652 (match_dup 1) 2653 (parallel [(const_int 2)])))) 2654 (const_int 2)))] 2655 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2656 "<zs>unpkd810\t%0, %1" 2657 [(set_attr "type" "dpack") 2658 (set_attr "length" "4")]) 2659 2660(define_expand "sunpkd820" 2661 [(match_operand:V2HI 0 "register_operand") 2662 (match_operand:V4QI 1 "register_operand")] 2663 "NDS32_EXT_DSP_P ()" 2664{ 2665 if (TARGET_BIG_ENDIAN) 2666 emit_insn (gen_sunpkd820_imp_be (operands[0], operands[1])); 2667 else 2668 emit_insn (gen_sunpkd820_imp (operands[0], operands[1])); 2669 DONE; 2670}) 2671 2672(define_insn "<zs>unpkd820_imp" 2673 [(set (match_operand:V2HI 0 "register_operand" "=r") 2674 (vec_merge:V2HI 2675 (vec_duplicate:V2HI 2676 (extend:HI 2677 (vec_select:QI 2678 (match_operand:V4QI 1 "register_operand" " r") 2679 (parallel [(const_int 2)])))) 2680 (vec_duplicate:V2HI 2681 (extend:HI 2682 (vec_select:QI 2683 (match_dup 1) 2684 (parallel [(const_int 0)])))) 2685 (const_int 2)))] 2686 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2687 "<zs>unpkd820\t%0, %1" 2688 [(set_attr "type" "dpack") 2689 (set_attr "length" "4")]) 2690 2691(define_insn "<zs>unpkd820_imp_inv" 2692 [(set (match_operand:V2HI 0 "register_operand" "=r") 2693 (vec_merge:V2HI 2694 (vec_duplicate:V2HI 2695 (extend:HI 2696 (vec_select:QI 2697 (match_operand:V4QI 1 "register_operand" " r") 2698 (parallel [(const_int 0)])))) 2699 (vec_duplicate:V2HI 2700 (extend:HI 2701 (vec_select:QI 2702 (match_dup 1) 2703 (parallel [(const_int 2)])))) 2704 (const_int 1)))] 2705 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2706 "<zs>unpkd820\t%0, %1" 2707 [(set_attr "type" "dpack") 2708 (set_attr "length" "4")]) 2709 2710(define_insn "<zs>unpkd820_imp_be" 2711 [(set (match_operand:V2HI 0 "register_operand" "=r") 2712 (vec_merge:V2HI 2713 (vec_duplicate:V2HI 2714 (extend:HI 2715 (vec_select:QI 2716 (match_operand:V4QI 1 "register_operand" " r") 2717 (parallel [(const_int 1)])))) 2718 (vec_duplicate:V2HI 2719 (extend:HI 2720 (vec_select:QI 2721 (match_dup 1) 2722 (parallel [(const_int 3)])))) 2723 (const_int 1)))] 2724 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2725 "<zs>unpkd820\t%0, %1" 2726 [(set_attr "type" "dpack") 2727 (set_attr "length" "4")]) 2728 2729(define_insn "<zs>unpkd820_imp_inv_be" 2730 [(set (match_operand:V2HI 0 "register_operand" "=r") 2731 (vec_merge:V2HI 2732 (vec_duplicate:V2HI 2733 (extend:HI 2734 (vec_select:QI 2735 (match_operand:V4QI 1 "register_operand" " r") 2736 (parallel [(const_int 3)])))) 2737 (vec_duplicate:V2HI 2738 (extend:HI 2739 (vec_select:QI 2740 (match_dup 1) 2741 (parallel [(const_int 1)])))) 2742 (const_int 2)))] 2743 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2744 "<zs>unpkd820\t%0, %1" 2745 [(set_attr "type" "dpack") 2746 (set_attr "length" "4")]) 2747 2748(define_expand "sunpkd830" 2749 [(match_operand:V2HI 0 "register_operand") 2750 (match_operand:V4QI 1 "register_operand")] 2751 "NDS32_EXT_DSP_P ()" 2752{ 2753 if (TARGET_BIG_ENDIAN) 2754 emit_insn (gen_sunpkd830_imp_be (operands[0], operands[1])); 2755 else 2756 emit_insn (gen_sunpkd830_imp (operands[0], operands[1])); 2757 DONE; 2758}) 2759 2760(define_insn "<zs>unpkd830_imp" 2761 [(set (match_operand:V2HI 0 "register_operand" "=r") 2762 (vec_merge:V2HI 2763 (vec_duplicate:V2HI 2764 (extend:HI 2765 (vec_select:QI 2766 (match_operand:V4QI 1 "register_operand" " r") 2767 (parallel [(const_int 3)])))) 2768 (vec_duplicate:V2HI 2769 (extend:HI 2770 (vec_select:QI 2771 (match_dup 1) 2772 (parallel [(const_int 0)])))) 2773 (const_int 2)))] 2774 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2775 "<zs>unpkd830\t%0, %1" 2776 [(set_attr "type" "dpack") 2777 (set_attr "length" "4")]) 2778 2779(define_insn "<zs>unpkd830_imp_inv" 2780 [(set (match_operand:V2HI 0 "register_operand" "=r") 2781 (vec_merge:V2HI 2782 (vec_duplicate:V2HI 2783 (extend:HI 2784 (vec_select:QI 2785 (match_operand:V4QI 1 "register_operand" " r") 2786 (parallel [(const_int 0)])))) 2787 (vec_duplicate:V2HI 2788 (extend:HI 2789 (vec_select:QI 2790 (match_dup 1) 2791 (parallel [(const_int 3)])))) 2792 (const_int 1)))] 2793 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2794 "<zs>unpkd830\t%0, %1" 2795 [(set_attr "type" "dpack") 2796 (set_attr "length" "4")]) 2797 2798(define_insn "<zs>unpkd830_imp_be" 2799 [(set (match_operand:V2HI 0 "register_operand" "=r") 2800 (vec_merge:V2HI 2801 (vec_duplicate:V2HI 2802 (extend:HI 2803 (vec_select:QI 2804 (match_operand:V4QI 1 "register_operand" " r") 2805 (parallel [(const_int 0)])))) 2806 (vec_duplicate:V2HI 2807 (extend:HI 2808 (vec_select:QI 2809 (match_dup 1) 2810 (parallel [(const_int 3)])))) 2811 (const_int 1)))] 2812 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2813 "<zs>unpkd830\t%0, %1" 2814 [(set_attr "type" "dpack") 2815 (set_attr "length" "4")]) 2816 2817(define_insn "<zs>unpkd830_imp_inv_be" 2818 [(set (match_operand:V2HI 0 "register_operand" "=r") 2819 (vec_merge:V2HI 2820 (vec_duplicate:V2HI 2821 (extend:HI 2822 (vec_select:QI 2823 (match_operand:V4QI 1 "register_operand" " r") 2824 (parallel [(const_int 3)])))) 2825 (vec_duplicate:V2HI 2826 (extend:HI 2827 (vec_select:QI 2828 (match_dup 1) 2829 (parallel [(const_int 0)])))) 2830 (const_int 2)))] 2831 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2832 "<zs>unpkd830\t%0, %1" 2833 [(set_attr "type" "dpack") 2834 (set_attr "length" "4")]) 2835 2836(define_expand "sunpkd831" 2837 [(match_operand:V2HI 0 "register_operand") 2838 (match_operand:V4QI 1 "register_operand")] 2839 "NDS32_EXT_DSP_P ()" 2840{ 2841 if (TARGET_BIG_ENDIAN) 2842 emit_insn (gen_sunpkd831_imp_be (operands[0], operands[1])); 2843 else 2844 emit_insn (gen_sunpkd831_imp (operands[0], operands[1])); 2845 DONE; 2846}) 2847 2848(define_insn "<zs>unpkd831_imp" 2849 [(set (match_operand:V2HI 0 "register_operand" "=r") 2850 (vec_merge:V2HI 2851 (vec_duplicate:V2HI 2852 (extend:HI 2853 (vec_select:QI 2854 (match_operand:V4QI 1 "register_operand" " r") 2855 (parallel [(const_int 3)])))) 2856 (vec_duplicate:V2HI 2857 (extend:HI 2858 (vec_select:QI 2859 (match_dup 1) 2860 (parallel [(const_int 1)])))) 2861 (const_int 2)))] 2862 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2863 "<zs>unpkd831\t%0, %1" 2864 [(set_attr "type" "dpack") 2865 (set_attr "length" "4")]) 2866 2867(define_insn "<zs>unpkd831_imp_inv" 2868 [(set (match_operand:V2HI 0 "register_operand" "=r") 2869 (vec_merge:V2HI 2870 (vec_duplicate:V2HI 2871 (extend:HI 2872 (vec_select:QI 2873 (match_operand:V4QI 1 "register_operand" " r") 2874 (parallel [(const_int 1)])))) 2875 (vec_duplicate:V2HI 2876 (extend:HI 2877 (vec_select:QI 2878 (match_dup 1) 2879 (parallel [(const_int 3)])))) 2880 (const_int 1)))] 2881 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 2882 "<zs>unpkd831\t%0, %1" 2883 [(set_attr "type" "dpack") 2884 (set_attr "length" "4")]) 2885 2886(define_insn "<zs>unpkd831_imp_be" 2887 [(set (match_operand:V2HI 0 "register_operand" "=r") 2888 (vec_merge:V2HI 2889 (vec_duplicate:V2HI 2890 (extend:HI 2891 (vec_select:QI 2892 (match_operand:V4QI 1 "register_operand" " r") 2893 (parallel [(const_int 0)])))) 2894 (vec_duplicate:V2HI 2895 (extend:HI 2896 (vec_select:QI 2897 (match_dup 1) 2898 (parallel [(const_int 2)])))) 2899 (const_int 1)))] 2900 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2901 "<zs>unpkd831\t%0, %1" 2902 [(set_attr "type" "dpack") 2903 (set_attr "length" "4")]) 2904 2905(define_insn "<zs>unpkd831_imp_inv_be" 2906 [(set (match_operand:V2HI 0 "register_operand" "=r") 2907 (vec_merge:V2HI 2908 (vec_duplicate:V2HI 2909 (extend:HI 2910 (vec_select:QI 2911 (match_operand:V4QI 1 "register_operand" " r") 2912 (parallel [(const_int 2)])))) 2913 (vec_duplicate:V2HI 2914 (extend:HI 2915 (vec_select:QI 2916 (match_dup 1) 2917 (parallel [(const_int 0)])))) 2918 (const_int 2)))] 2919 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 2920 "<zs>unpkd831\t%0, %1" 2921 [(set_attr "type" "dpack") 2922 (set_attr "length" "4")]) 2923 2924(define_expand "zunpkd810" 2925 [(match_operand:V2HI 0 "register_operand") 2926 (match_operand:V4QI 1 "register_operand")] 2927 "NDS32_EXT_DSP_P ()" 2928{ 2929 if (TARGET_BIG_ENDIAN) 2930 emit_insn (gen_zunpkd810_imp_be (operands[0], operands[1])); 2931 else 2932 emit_insn (gen_zunpkd810_imp (operands[0], operands[1])); 2933 DONE; 2934}) 2935 2936(define_expand "zunpkd820" 2937 [(match_operand:V2HI 0 "register_operand") 2938 (match_operand:V4QI 1 "register_operand")] 2939 "NDS32_EXT_DSP_P ()" 2940{ 2941 if (TARGET_BIG_ENDIAN) 2942 emit_insn (gen_zunpkd820_imp_be (operands[0], operands[1])); 2943 else 2944 emit_insn (gen_zunpkd820_imp (operands[0], operands[1])); 2945 DONE; 2946}) 2947 2948(define_expand "zunpkd830" 2949 [(match_operand:V2HI 0 "register_operand") 2950 (match_operand:V4QI 1 "register_operand")] 2951 "NDS32_EXT_DSP_P ()" 2952{ 2953 if (TARGET_BIG_ENDIAN) 2954 emit_insn (gen_zunpkd830_imp_be (operands[0], operands[1])); 2955 else 2956 emit_insn (gen_zunpkd830_imp (operands[0], operands[1])); 2957 DONE; 2958}) 2959 2960(define_expand "zunpkd831" 2961 [(match_operand:V2HI 0 "register_operand") 2962 (match_operand:V4QI 1 "register_operand")] 2963 "NDS32_EXT_DSP_P ()" 2964{ 2965 if (TARGET_BIG_ENDIAN) 2966 emit_insn (gen_zunpkd831_imp_be (operands[0], operands[1])); 2967 else 2968 emit_insn (gen_zunpkd831_imp (operands[0], operands[1])); 2969 DONE; 2970}) 2971 2972(define_expand "smbb" 2973 [(match_operand:SI 0 "register_operand" "") 2974 (match_operand:V2HI 1 "register_operand" "") 2975 (match_operand:V2HI 2 "register_operand" "")] 2976 "NDS32_EXT_DSP_P ()" 2977{ 2978 if (TARGET_BIG_ENDIAN) 2979 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], 2980 GEN_INT (1), GEN_INT (1))); 2981 else 2982 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], 2983 GEN_INT (0), GEN_INT (0))); 2984 DONE; 2985}) 2986 2987(define_expand "smbt" 2988 [(match_operand:SI 0 "register_operand" "") 2989 (match_operand:V2HI 1 "register_operand" "") 2990 (match_operand:V2HI 2 "register_operand" "")] 2991 "NDS32_EXT_DSP_P ()" 2992{ 2993 if (TARGET_BIG_ENDIAN) 2994 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], 2995 GEN_INT (1), GEN_INT (0))); 2996 else 2997 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], 2998 GEN_INT (0), GEN_INT (1))); 2999 DONE; 3000}) 3001 3002(define_expand "smtt" 3003 [(match_operand:SI 0 "register_operand" "") 3004 (match_operand:V2HI 1 "register_operand" "") 3005 (match_operand:V2HI 2 "register_operand" "")] 3006 "NDS32_EXT_DSP_P ()" 3007{ 3008 if (TARGET_BIG_ENDIAN) 3009 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], 3010 GEN_INT (0), GEN_INT (0))); 3011 else 3012 emit_insn (gen_mulhisi3v (operands[0], operands[1], operands[2], 3013 GEN_INT (1), GEN_INT (1))); 3014 DONE; 3015}) 3016 3017(define_insn "mulhisi3v" 3018 [(set (match_operand:SI 0 "register_operand" "= r, r, r, r") 3019 (mult:SI 3020 (sign_extend:SI 3021 (vec_select:HI 3022 (match_operand:V2HI 1 "register_operand" " r, r, r, r") 3023 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) 3024 (sign_extend:SI (vec_select:HI 3025 (match_operand:V2HI 2 "register_operand" " r, r, r, r") 3026 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))))] 3027 "NDS32_EXT_DSP_P ()" 3028{ 3029 if (TARGET_BIG_ENDIAN) 3030 { 3031 const char *pats[] = { "smtt\t%0, %1, %2", 3032 "smbt\t%0, %2, %1", 3033 "smbb\t%0, %1, %2", 3034 "smbt\t%0, %1, %2" }; 3035 return pats[which_alternative]; 3036 } 3037 else 3038 { 3039 const char *pats[] = { "smbb\t%0, %1, %2", 3040 "smbt\t%0, %1, %2", 3041 "smtt\t%0, %1, %2", 3042 "smbt\t%0, %2, %1" }; 3043 return pats[which_alternative]; 3044 } 3045} 3046 [(set_attr "type" "dmul") 3047 (set_attr "length" "4")]) 3048 3049(define_expand "kmabb" 3050 [(match_operand:SI 0 "register_operand" "") 3051 (match_operand:SI 1 "register_operand" "") 3052 (match_operand:V2HI 2 "register_operand" "") 3053 (match_operand:V2HI 3 "register_operand" "")] 3054 "NDS32_EXT_DSP_P ()" 3055{ 3056 if (TARGET_BIG_ENDIAN) 3057 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], 3058 GEN_INT (1), GEN_INT (1), 3059 operands[1])); 3060 else 3061 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], 3062 GEN_INT (0), GEN_INT (0), 3063 operands[1])); 3064 DONE; 3065}) 3066 3067(define_expand "kmabt" 3068 [(match_operand:SI 0 "register_operand" "") 3069 (match_operand:SI 1 "register_operand" "") 3070 (match_operand:V2HI 2 "register_operand" "") 3071 (match_operand:V2HI 3 "register_operand" "")] 3072 "NDS32_EXT_DSP_P ()" 3073{ 3074 if (TARGET_BIG_ENDIAN) 3075 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], 3076 GEN_INT (1), GEN_INT (0), 3077 operands[1])); 3078 else 3079 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], 3080 GEN_INT (0), GEN_INT (1), 3081 operands[1])); 3082 DONE; 3083}) 3084 3085(define_expand "kmatt" 3086 [(match_operand:SI 0 "register_operand" "") 3087 (match_operand:SI 1 "register_operand" "") 3088 (match_operand:V2HI 2 "register_operand" "") 3089 (match_operand:V2HI 3 "register_operand" "")] 3090 "NDS32_EXT_DSP_P ()" 3091{ 3092 if (TARGET_BIG_ENDIAN) 3093 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], 3094 GEN_INT (0), GEN_INT (0), 3095 operands[1])); 3096 else 3097 emit_insn (gen_kma_internal (operands[0], operands[2], operands[3], 3098 GEN_INT (1), GEN_INT (1), 3099 operands[1])); 3100 DONE; 3101}) 3102 3103(define_insn "kma_internal" 3104 [(set (match_operand:SI 0 "register_operand" "= r, r, r, r") 3105 (ss_plus:SI 3106 (mult:SI 3107 (sign_extend:SI 3108 (vec_select:HI 3109 (match_operand:V2HI 1 "register_operand" " r, r, r, r") 3110 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) 3111 (sign_extend:SI 3112 (vec_select:HI 3113 (match_operand:V2HI 2 "register_operand" " r, r, r, r") 3114 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))) 3115 (match_operand:SI 5 "register_operand" " 0, 0, 0, 0")))] 3116 "NDS32_EXT_DSP_P ()" 3117{ 3118 if (TARGET_BIG_ENDIAN) 3119 { 3120 const char *pats[] = { "kmatt\t%0, %1, %2", 3121 "kmabt\t%0, %2, %1", 3122 "kmabb\t%0, %1, %2", 3123 "kmabt\t%0, %1, %2" }; 3124 return pats[which_alternative]; 3125 } 3126 else 3127 { 3128 const char *pats[] = { "kmabb\t%0, %1, %2", 3129 "kmabt\t%0, %1, %2", 3130 "kmatt\t%0, %1, %2", 3131 "kmabt\t%0, %2, %1" }; 3132 return pats[which_alternative]; 3133 } 3134} 3135 [(set_attr "type" "dmac") 3136 (set_attr "length" "4")]) 3137 3138(define_expand "smds" 3139 [(match_operand:SI 0 "register_operand" "") 3140 (match_operand:V2HI 1 "register_operand" "") 3141 (match_operand:V2HI 2 "register_operand" "")] 3142 "NDS32_EXT_DSP_P ()" 3143{ 3144 if (TARGET_BIG_ENDIAN) 3145 emit_insn (gen_smds_be (operands[0], operands[1], operands[2])); 3146 else 3147 emit_insn (gen_smds_le (operands[0], operands[1], operands[2])); 3148 DONE; 3149}) 3150 3151(define_expand "smds_le" 3152 [(set (match_operand:SI 0 "register_operand" "=r") 3153 (minus:SI 3154 (mult:SI 3155 (sign_extend:SI (vec_select:HI 3156 (match_operand:V2HI 1 "register_operand" " r") 3157 (parallel [(const_int 1)]))) 3158 (sign_extend:SI (vec_select:HI 3159 (match_operand:V2HI 2 "register_operand" " r") 3160 (parallel [(const_int 1)])))) 3161 (mult:SI 3162 (sign_extend:SI (vec_select:HI 3163 (match_dup 1) 3164 (parallel [(const_int 0)]))) 3165 (sign_extend:SI (vec_select:HI 3166 (match_dup 2) 3167 (parallel [(const_int 0)]))))))] 3168 "NDS32_EXT_DSP_P ()" 3169{ 3170}) 3171 3172(define_expand "smds_be" 3173 [(set (match_operand:SI 0 "register_operand" "=r") 3174 (minus:SI 3175 (mult:SI 3176 (sign_extend:SI (vec_select:HI 3177 (match_operand:V2HI 1 "register_operand" " r") 3178 (parallel [(const_int 0)]))) 3179 (sign_extend:SI (vec_select:HI 3180 (match_operand:V2HI 2 "register_operand" " r") 3181 (parallel [(const_int 0)])))) 3182 (mult:SI 3183 (sign_extend:SI (vec_select:HI 3184 (match_dup 1) 3185 (parallel [(const_int 1)]))) 3186 (sign_extend:SI (vec_select:HI 3187 (match_dup 2) 3188 (parallel [(const_int 1)]))))))] 3189 "NDS32_EXT_DSP_P ()" 3190{ 3191}) 3192 3193(define_expand "smdrs" 3194 [(match_operand:SI 0 "register_operand" "") 3195 (match_operand:V2HI 1 "register_operand" "") 3196 (match_operand:V2HI 2 "register_operand" "")] 3197 "NDS32_EXT_DSP_P ()" 3198{ 3199 if (TARGET_BIG_ENDIAN) 3200 emit_insn (gen_smdrs_be (operands[0], operands[1], operands[2])); 3201 else 3202 emit_insn (gen_smdrs_le (operands[0], operands[1], operands[2])); 3203 DONE; 3204}) 3205 3206(define_expand "smdrs_le" 3207 [(set (match_operand:SI 0 "register_operand" "=r") 3208 (minus:SI 3209 (mult:SI 3210 (sign_extend:SI (vec_select:HI 3211 (match_operand:V2HI 1 "register_operand" " r") 3212 (parallel [(const_int 0)]))) 3213 (sign_extend:SI (vec_select:HI 3214 (match_operand:V2HI 2 "register_operand" " r") 3215 (parallel [(const_int 0)])))) 3216 (mult:SI 3217 (sign_extend:SI (vec_select:HI 3218 (match_dup 1) 3219 (parallel [(const_int 1)]))) 3220 (sign_extend:SI (vec_select:HI 3221 (match_dup 2) 3222 (parallel [(const_int 1)]))))))] 3223 "NDS32_EXT_DSP_P ()" 3224{ 3225}) 3226 3227(define_expand "smdrs_be" 3228 [(set (match_operand:SI 0 "register_operand" "=r") 3229 (minus:SI 3230 (mult:SI 3231 (sign_extend:SI (vec_select:HI 3232 (match_operand:V2HI 1 "register_operand" " r") 3233 (parallel [(const_int 1)]))) 3234 (sign_extend:SI (vec_select:HI 3235 (match_operand:V2HI 2 "register_operand" " r") 3236 (parallel [(const_int 1)])))) 3237 (mult:SI 3238 (sign_extend:SI (vec_select:HI 3239 (match_dup 1) 3240 (parallel [(const_int 0)]))) 3241 (sign_extend:SI (vec_select:HI 3242 (match_dup 2) 3243 (parallel [(const_int 0)]))))))] 3244 "NDS32_EXT_DSP_P ()" 3245{ 3246}) 3247 3248(define_expand "smxdsv" 3249 [(match_operand:SI 0 "register_operand" "") 3250 (match_operand:V2HI 1 "register_operand" "") 3251 (match_operand:V2HI 2 "register_operand" "")] 3252 "NDS32_EXT_DSP_P ()" 3253{ 3254 if (TARGET_BIG_ENDIAN) 3255 emit_insn (gen_smxdsv_be (operands[0], operands[1], operands[2])); 3256 else 3257 emit_insn (gen_smxdsv_le (operands[0], operands[1], operands[2])); 3258 DONE; 3259}) 3260 3261 3262(define_expand "smxdsv_le" 3263 [(set (match_operand:SI 0 "register_operand" "=r") 3264 (minus:SI 3265 (mult:SI 3266 (sign_extend:SI (vec_select:HI 3267 (match_operand:V2HI 1 "register_operand" " r") 3268 (parallel [(const_int 1)]))) 3269 (sign_extend:SI (vec_select:HI 3270 (match_operand:V2HI 2 "register_operand" " r") 3271 (parallel [(const_int 0)])))) 3272 (mult:SI 3273 (sign_extend:SI (vec_select:HI 3274 (match_dup 1) 3275 (parallel [(const_int 0)]))) 3276 (sign_extend:SI (vec_select:HI 3277 (match_dup 2) 3278 (parallel [(const_int 1)]))))))] 3279 "NDS32_EXT_DSP_P ()" 3280{ 3281}) 3282 3283(define_expand "smxdsv_be" 3284 [(set (match_operand:SI 0 "register_operand" "=r") 3285 (minus:SI 3286 (mult:SI 3287 (sign_extend:SI (vec_select:HI 3288 (match_operand:V2HI 1 "register_operand" " r") 3289 (parallel [(const_int 0)]))) 3290 (sign_extend:SI (vec_select:HI 3291 (match_operand:V2HI 2 "register_operand" " r") 3292 (parallel [(const_int 1)])))) 3293 (mult:SI 3294 (sign_extend:SI (vec_select:HI 3295 (match_dup 1) 3296 (parallel [(const_int 1)]))) 3297 (sign_extend:SI (vec_select:HI 3298 (match_dup 2) 3299 (parallel [(const_int 0)]))))))] 3300 "NDS32_EXT_DSP_P ()" 3301{ 3302}) 3303 3304(define_insn "smal1" 3305 [(set (match_operand:DI 0 "register_operand" "=r") 3306 (plus:DI (match_operand:DI 1 "register_operand" " r") 3307 (sign_extend:DI 3308 (mult:SI 3309 (sign_extend:SI 3310 (vec_select:HI 3311 (match_operand:V2HI 2 "register_operand" " r") 3312 (parallel [(const_int 0)]))) 3313 (sign_extend:SI 3314 (vec_select:HI 3315 (match_dup 2) 3316 (parallel [(const_int 1)])))))))] 3317 "NDS32_EXT_DSP_P ()" 3318 "smal\t%0, %1, %2" 3319 [(set_attr "type" "dmac") 3320 (set_attr "length" "4")]) 3321 3322(define_insn "smal2" 3323 [(set (match_operand:DI 0 "register_operand" "=r") 3324 (plus:DI (match_operand:DI 1 "register_operand" " r") 3325 (mult:DI 3326 (sign_extend:DI 3327 (vec_select:HI 3328 (match_operand:V2HI 2 "register_operand" " r") 3329 (parallel [(const_int 0)]))) 3330 (sign_extend:DI 3331 (vec_select:HI 3332 (match_dup 2) 3333 (parallel [(const_int 1)]))))))] 3334 "NDS32_EXT_DSP_P ()" 3335 "smal\t%0, %1, %2" 3336 [(set_attr "type" "dmac") 3337 (set_attr "length" "4")]) 3338 3339(define_insn "smal3" 3340 [(set (match_operand:DI 0 "register_operand" "=r") 3341 (plus:DI (match_operand:DI 1 "register_operand" " r") 3342 (sign_extend:DI 3343 (mult:SI 3344 (sign_extend:SI 3345 (vec_select:HI 3346 (match_operand:V2HI 2 "register_operand" " r") 3347 (parallel [(const_int 1)]))) 3348 (sign_extend:SI 3349 (vec_select:HI 3350 (match_dup 2) 3351 (parallel [(const_int 0)])))))))] 3352 "NDS32_EXT_DSP_P ()" 3353 "smal\t%0, %1, %2" 3354 [(set_attr "type" "dmac") 3355 (set_attr "length" "4")]) 3356 3357(define_insn "smal4" 3358 [(set (match_operand:DI 0 "register_operand" "=r") 3359 (plus:DI (match_operand:DI 1 "register_operand" " r") 3360 (mult:DI 3361 (sign_extend:DI 3362 (vec_select:HI 3363 (match_operand:V2HI 2 "register_operand" " r") 3364 (parallel [(const_int 1)]))) 3365 (sign_extend:DI 3366 (vec_select:HI 3367 (match_dup 2) 3368 (parallel [(const_int 0)]))))))] 3369 "NDS32_EXT_DSP_P ()" 3370 "smal\t%0, %1, %2" 3371 [(set_attr "type" "dmac") 3372 (set_attr "length" "4")]) 3373 3374(define_insn "smal5" 3375 [(set (match_operand:DI 0 "register_operand" "=r") 3376 (plus:DI 3377 (sign_extend:DI 3378 (mult:SI 3379 (sign_extend:SI 3380 (vec_select:HI 3381 (match_operand:V2HI 2 "register_operand" " r") 3382 (parallel [(const_int 0)]))) 3383 (sign_extend:SI 3384 (vec_select:HI 3385 (match_dup 2) 3386 (parallel [(const_int 1)]))))) 3387 (match_operand:DI 1 "register_operand" " r")))] 3388 "NDS32_EXT_DSP_P ()" 3389 "smal\t%0, %1, %2" 3390 [(set_attr "type" "dmac") 3391 (set_attr "length" "4")]) 3392 3393(define_insn "smal6" 3394 [(set (match_operand:DI 0 "register_operand" "=r") 3395 (plus:DI 3396 (mult:DI 3397 (sign_extend:DI 3398 (vec_select:HI 3399 (match_operand:V2HI 2 "register_operand" " r") 3400 (parallel [(const_int 0)]))) 3401 (sign_extend:DI 3402 (vec_select:HI 3403 (match_dup 2) 3404 (parallel [(const_int 1)])))) 3405 (match_operand:DI 1 "register_operand" " r")))] 3406 "NDS32_EXT_DSP_P ()" 3407 "smal\t%0, %1, %2" 3408 [(set_attr "type" "dmac") 3409 (set_attr "length" "4")]) 3410 3411(define_insn "smal7" 3412 [(set (match_operand:DI 0 "register_operand" "=r") 3413 (plus:DI 3414 (sign_extend:DI 3415 (mult:SI 3416 (sign_extend:SI 3417 (vec_select:HI 3418 (match_operand:V2HI 2 "register_operand" " r") 3419 (parallel [(const_int 1)]))) 3420 (sign_extend:SI 3421 (vec_select:HI 3422 (match_dup 2) 3423 (parallel [(const_int 0)]))))) 3424 (match_operand:DI 1 "register_operand" " r")))] 3425 "NDS32_EXT_DSP_P ()" 3426 "smal\t%0, %1, %2" 3427 [(set_attr "type" "dmac") 3428 (set_attr "length" "4")]) 3429 3430(define_insn "smal8" 3431 [(set (match_operand:DI 0 "register_operand" "=r") 3432 (plus:DI 3433 (mult:DI 3434 (sign_extend:DI 3435 (vec_select:HI 3436 (match_operand:V2HI 2 "register_operand" " r") 3437 (parallel [(const_int 1)]))) 3438 (sign_extend:DI 3439 (vec_select:HI 3440 (match_dup 2) 3441 (parallel [(const_int 0)])))) 3442 (match_operand:DI 1 "register_operand" " r")))] 3443 "NDS32_EXT_DSP_P ()" 3444 "smal\t%0, %1, %2" 3445 [(set_attr "type" "dmac") 3446 (set_attr "length" "4")]) 3447 3448;; We need this dummy pattern for smal 3449(define_insn_and_split "extendsidi2" 3450 [(set (match_operand:DI 0 "register_operand" "") 3451 (sign_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))] 3452 "NDS32_EXT_DSP_P ()" 3453 "#" 3454 "NDS32_EXT_DSP_P ()" 3455 [(const_int 0)] 3456{ 3457 rtx high_part_dst, low_part_dst; 3458 3459 low_part_dst = nds32_di_low_part_subreg (operands[0]); 3460 high_part_dst = nds32_di_high_part_subreg (operands[0]); 3461 3462 emit_move_insn (low_part_dst, operands[1]); 3463 emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31))); 3464 DONE; 3465} 3466 [(set_attr "type" "alu") 3467 (set_attr "length" "4")]) 3468 3469;; We need this dummy pattern for usmar64/usmsr64 3470(define_insn_and_split "zero_extendsidi2" 3471 [(set (match_operand:DI 0 "register_operand" "") 3472 (zero_extend:DI (match_operand:SI 1 "nds32_move_operand" "")))] 3473 "NDS32_EXT_DSP_P ()" 3474 "#" 3475 "NDS32_EXT_DSP_P ()" 3476 [(const_int 0)] 3477{ 3478 rtx high_part_dst, low_part_dst; 3479 3480 low_part_dst = nds32_di_low_part_subreg (operands[0]); 3481 high_part_dst = nds32_di_high_part_subreg (operands[0]); 3482 3483 emit_move_insn (low_part_dst, operands[1]); 3484 emit_move_insn (high_part_dst, const0_rtx); 3485 DONE; 3486} 3487 [(set_attr "type" "alu") 3488 (set_attr "length" "4")]) 3489 3490(define_insn_and_split "extendhidi2" 3491 [(set (match_operand:DI 0 "register_operand" "") 3492 (sign_extend:DI (match_operand:HI 1 "nonimmediate_operand" "")))] 3493 "NDS32_EXT_DSP_P ()" 3494 "#" 3495 "NDS32_EXT_DSP_P ()" 3496 [(const_int 0)] 3497{ 3498 rtx high_part_dst, low_part_dst; 3499 3500 low_part_dst = nds32_di_low_part_subreg (operands[0]); 3501 high_part_dst = nds32_di_high_part_subreg (operands[0]); 3502 3503 3504 emit_insn (gen_extendhisi2 (low_part_dst, operands[1])); 3505 emit_insn (gen_ashrsi3 (high_part_dst, low_part_dst, GEN_INT (31))); 3506 DONE; 3507} 3508 [(set_attr "type" "alu") 3509 (set_attr "length" "4")]) 3510 3511(define_insn "extendqihi2" 3512 [(set (match_operand:HI 0 "register_operand" "=r") 3513 (sign_extend:HI (match_operand:QI 1 "register_operand" " r")))] 3514 "NDS32_EXT_DSP_P ()" 3515 "sunpkd820\t%0, %1" 3516 [(set_attr "type" "dpack") 3517 (set_attr "length" "4")]) 3518 3519(define_insn "smulsi3_highpart" 3520 [(set (match_operand:SI 0 "register_operand" "=r") 3521 (truncate:SI 3522 (lshiftrt:DI 3523 (mult:DI 3524 (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) 3525 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))) 3526 (const_int 32))))] 3527 "NDS32_EXT_DSP_P ()" 3528 "smmul\t%0, %1, %2" 3529 [(set_attr "type" "dmul") 3530 (set_attr "length" "4")]) 3531 3532(define_insn "smmul_round" 3533 [(set (match_operand:SI 0 "register_operand" "=r") 3534 (truncate:SI 3535 (lshiftrt:DI 3536 (unspec:DI [(mult:DI 3537 (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) 3538 (sign_extend:DI (match_operand:SI 2 "register_operand" " r")))] 3539 UNSPEC_ROUND) 3540 (const_int 32))))] 3541 "NDS32_EXT_DSP_P ()" 3542 "smmul.u\t%0, %1, %2" 3543 [(set_attr "type" "dmul") 3544 (set_attr "length" "4")]) 3545 3546(define_insn "kmmac" 3547 [(set (match_operand:SI 0 "register_operand" "=r") 3548 (ss_plus:SI (match_operand:SI 1 "register_operand" " 0") 3549 (truncate:SI 3550 (lshiftrt:DI 3551 (mult:DI 3552 (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) 3553 (sign_extend:DI (match_operand:SI 3 "register_operand" " r"))) 3554 (const_int 32)))))] 3555 "NDS32_EXT_DSP_P ()" 3556 "kmmac\t%0, %2, %3" 3557 [(set_attr "type" "dmac") 3558 (set_attr "length" "4")]) 3559 3560(define_insn "kmmac_round" 3561 [(set (match_operand:SI 0 "register_operand" "=r") 3562 (ss_plus:SI (match_operand:SI 1 "register_operand" " 0") 3563 (truncate:SI 3564 (lshiftrt:DI 3565 (unspec:DI [(mult:DI 3566 (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) 3567 (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))] 3568 UNSPEC_ROUND) 3569 (const_int 32)))))] 3570 "NDS32_EXT_DSP_P ()" 3571 "kmmac.u\t%0, %2, %3" 3572 [(set_attr "type" "dmac") 3573 (set_attr "length" "4")]) 3574 3575(define_insn "kmmsb" 3576 [(set (match_operand:SI 0 "register_operand" "=r") 3577 (ss_minus:SI (match_operand:SI 1 "register_operand" " 0") 3578 (truncate:SI 3579 (lshiftrt:DI 3580 (mult:DI 3581 (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) 3582 (sign_extend:DI (match_operand:SI 3 "register_operand" " r"))) 3583 (const_int 32)))))] 3584 "NDS32_EXT_DSP_P ()" 3585 "kmmsb\t%0, %2, %3" 3586 [(set_attr "type" "dmac") 3587 (set_attr "length" "4")]) 3588 3589(define_insn "kmmsb_round" 3590 [(set (match_operand:SI 0 "register_operand" "=r") 3591 (ss_minus:SI (match_operand:SI 1 "register_operand" " 0") 3592 (truncate:SI 3593 (lshiftrt:DI 3594 (unspec:DI [(mult:DI 3595 (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) 3596 (sign_extend:DI (match_operand:SI 3 "register_operand" " r")))] 3597 UNSPEC_ROUND) 3598 (const_int 32)))))] 3599 "NDS32_EXT_DSP_P ()" 3600 "kmmsb.u\t%0, %2, %3" 3601 [(set_attr "type" "dmac") 3602 (set_attr "length" "4")]) 3603 3604(define_insn "kwmmul" 3605 [(set (match_operand:SI 0 "register_operand" "=r") 3606 (truncate:SI 3607 (lshiftrt:DI 3608 (ss_mult:DI 3609 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2)) 3610 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2))) 3611 (const_int 32))))] 3612 "NDS32_EXT_DSP_P ()" 3613 "kwmmul\t%0, %1, %2" 3614 [(set_attr "type" "dmul") 3615 (set_attr "length" "4")]) 3616 3617(define_insn "kwmmul_round" 3618 [(set (match_operand:SI 0 "register_operand" "=r") 3619 (truncate:SI 3620 (lshiftrt:DI 3621 (unspec:DI [ 3622 (ss_mult:DI 3623 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) (const_int 2)) 3624 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" " r")) (const_int 2)))] 3625 UNSPEC_ROUND) 3626 (const_int 32))))] 3627 "NDS32_EXT_DSP_P ()" 3628 "kwmmul.u\t%0, %1, %2" 3629 [(set_attr "type" "dmul") 3630 (set_attr "length" "4")]) 3631 3632(define_expand "smmwb" 3633 [(match_operand:SI 0 "register_operand" "") 3634 (match_operand:SI 1 "register_operand" "") 3635 (match_operand:V2HI 2 "register_operand" "")] 3636 "NDS32_EXT_DSP_P ()" 3637{ 3638 if (TARGET_BIG_ENDIAN) 3639 emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1))); 3640 else 3641 emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0))); 3642 DONE; 3643}) 3644 3645(define_expand "smmwt" 3646 [(match_operand:SI 0 "register_operand" "") 3647 (match_operand:SI 1 "register_operand" "") 3648 (match_operand:V2HI 2 "register_operand" "")] 3649 "NDS32_EXT_DSP_P ()" 3650{ 3651 if (TARGET_BIG_ENDIAN) 3652 emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (0))); 3653 else 3654 emit_insn (gen_smulhisi3_highpart_1 (operands[0], operands[1], operands[2], GEN_INT (1))); 3655 DONE; 3656}) 3657 3658(define_insn "smulhisi3_highpart_1" 3659 [(set (match_operand:SI 0 "register_operand" "= r, r") 3660 (truncate:SI 3661 (lshiftrt:DI 3662 (mult:DI 3663 (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) 3664 (sign_extend:DI 3665 (vec_select:HI 3666 (match_operand:V2HI 2 "register_operand" " r, r") 3667 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")])))) 3668 (const_int 16))))] 3669 "NDS32_EXT_DSP_P ()" 3670{ 3671 if (TARGET_BIG_ENDIAN) 3672 { 3673 const char *pats[] = { "smmwt\t%0, %1, %2", 3674 "smmwb\t%0, %1, %2" }; 3675 return pats[which_alternative]; 3676 } 3677 else 3678 { 3679 const char *pats[] = { "smmwb\t%0, %1, %2", 3680 "smmwt\t%0, %1, %2" }; 3681 return pats[which_alternative]; 3682 } 3683} 3684 [(set_attr "type" "dmul") 3685 (set_attr "length" "4")]) 3686 3687(define_insn "smulhisi3_highpart_2" 3688 [(set (match_operand:SI 0 "register_operand" "= r, r") 3689 (truncate:SI 3690 (lshiftrt:DI 3691 (mult:DI 3692 (sign_extend:DI 3693 (vec_select:HI 3694 (match_operand:V2HI 1 "register_operand" " r, r") 3695 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))) 3696 (sign_extend:DI (match_operand:SI 2 "register_operand" " r, r"))) 3697 (const_int 16))))] 3698 "NDS32_EXT_DSP_P ()" 3699{ 3700 if (TARGET_BIG_ENDIAN) 3701 { 3702 const char *pats[] = { "smmwt\t%0, %1, %2", 3703 "smmwb\t%0, %1, %2" }; 3704 return pats[which_alternative]; 3705 } 3706 else 3707 { 3708 const char *pats[] = { "smmwb\t%0, %1, %2", 3709 "smmwt\t%0, %1, %2" }; 3710 return pats[which_alternative]; 3711 } 3712} 3713 [(set_attr "type" "dmul") 3714 (set_attr "length" "4")]) 3715 3716(define_expand "smmwb_round" 3717 [(match_operand:SI 0 "register_operand" "") 3718 (match_operand:SI 1 "register_operand" "") 3719 (match_operand:V2HI 2 "register_operand" "")] 3720 "NDS32_EXT_DSP_P ()" 3721{ 3722 if (TARGET_BIG_ENDIAN) 3723 emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1))); 3724 else 3725 emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0))); 3726 DONE; 3727}) 3728 3729(define_expand "smmwt_round" 3730 [(match_operand:SI 0 "register_operand" "") 3731 (match_operand:SI 1 "register_operand" "") 3732 (match_operand:V2HI 2 "register_operand" "")] 3733 "NDS32_EXT_DSP_P ()" 3734{ 3735 if (TARGET_BIG_ENDIAN) 3736 emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (0))); 3737 else 3738 emit_insn (gen_smmw_round_internal (operands[0], operands[1], operands[2], GEN_INT (1))); 3739 DONE; 3740}) 3741 3742(define_insn "smmw_round_internal" 3743 [(set (match_operand:SI 0 "register_operand" "= r, r") 3744 (truncate:SI 3745 (lshiftrt:DI 3746 (unspec:DI 3747 [(mult:DI 3748 (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) 3749 (sign_extend:DI 3750 (vec_select:HI 3751 (match_operand:V2HI 2 "register_operand" " r, r") 3752 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))] 3753 UNSPEC_ROUND) 3754 (const_int 16))))] 3755 "NDS32_EXT_DSP_P ()" 3756{ 3757 if (TARGET_BIG_ENDIAN) 3758 { 3759 const char *pats[] = { "smmwt.u\t%0, %1, %2", 3760 "smmwb.u\t%0, %1, %2" }; 3761 return pats[which_alternative]; 3762 } 3763 else 3764 { 3765 const char *pats[] = { "smmwb.u\t%0, %1, %2", 3766 "smmwt.u\t%0, %1, %2" }; 3767 return pats[which_alternative]; 3768 } 3769} 3770 [(set_attr "type" "dmul") 3771 (set_attr "length" "4")]) 3772 3773(define_expand "kmmawb" 3774 [(match_operand:SI 0 "register_operand" "") 3775 (match_operand:SI 1 "register_operand" "") 3776 (match_operand:SI 2 "register_operand" "") 3777 (match_operand:V2HI 3 "register_operand" "")] 3778 "NDS32_EXT_DSP_P ()" 3779{ 3780 if (TARGET_BIG_ENDIAN) 3781 emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); 3782 else 3783 emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); 3784 DONE; 3785}) 3786 3787(define_expand "kmmawt" 3788 [(match_operand:SI 0 "register_operand" "") 3789 (match_operand:SI 1 "register_operand" "") 3790 (match_operand:SI 2 "register_operand" "") 3791 (match_operand:V2HI 3 "register_operand" "")] 3792 "NDS32_EXT_DSP_P ()" 3793{ 3794 if (TARGET_BIG_ENDIAN) 3795 emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); 3796 else 3797 emit_insn (gen_kmmaw_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); 3798 DONE; 3799}) 3800 3801(define_insn "kmmaw_internal" 3802 [(set (match_operand:SI 0 "register_operand" "= r, r") 3803 (ss_plus:SI 3804 (match_operand:SI 4 "register_operand" " 0, 0") 3805 (truncate:SI 3806 (lshiftrt:DI 3807 (mult:DI 3808 (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) 3809 (sign_extend:DI 3810 (vec_select:HI 3811 (match_operand:V2HI 2 "register_operand" " r, r") 3812 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")])))) 3813 (const_int 16)))))] 3814 "NDS32_EXT_DSP_P ()" 3815{ 3816 if (TARGET_BIG_ENDIAN) 3817 { 3818 const char *pats[] = { "kmmawt\t%0, %1, %2", 3819 "kmmawb\t%0, %1, %2" }; 3820 return pats[which_alternative]; 3821 } 3822 else 3823 { 3824 const char *pats[] = { "kmmawb\t%0, %1, %2", 3825 "kmmawt\t%0, %1, %2" }; 3826 return pats[which_alternative]; 3827 } 3828} 3829 [(set_attr "type" "dmac") 3830 (set_attr "length" "4")]) 3831 3832(define_expand "kmmawb_round" 3833 [(match_operand:SI 0 "register_operand" "") 3834 (match_operand:SI 1 "register_operand" "") 3835 (match_operand:SI 2 "register_operand" "") 3836 (match_operand:V2HI 3 "register_operand" "")] 3837 "NDS32_EXT_DSP_P ()" 3838{ 3839 if (TARGET_BIG_ENDIAN) 3840 emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); 3841 else 3842 emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); 3843 DONE; 3844} 3845 [(set_attr "type" "alu") 3846 (set_attr "length" "4")]) 3847 3848(define_expand "kmmawt_round" 3849 [(match_operand:SI 0 "register_operand" "") 3850 (match_operand:SI 1 "register_operand" "") 3851 (match_operand:SI 2 "register_operand" "") 3852 (match_operand:V2HI 3 "register_operand" "")] 3853 "NDS32_EXT_DSP_P ()" 3854{ 3855 if (TARGET_BIG_ENDIAN) 3856 emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (0), operands[1])); 3857 else 3858 emit_insn (gen_kmmaw_round_internal (operands[0], operands[2], operands[3], GEN_INT (1), operands[1])); 3859 DONE; 3860} 3861 [(set_attr "type" "dmac") 3862 (set_attr "length" "4")]) 3863 3864 3865(define_insn "kmmaw_round_internal" 3866 [(set (match_operand:SI 0 "register_operand" "= r, r") 3867 (ss_plus:SI 3868 (match_operand:SI 4 "register_operand" " 0, 0") 3869 (truncate:SI 3870 (lshiftrt:DI 3871 (unspec:DI 3872 [(mult:DI 3873 (sign_extend:DI (match_operand:SI 1 "register_operand" " r, r")) 3874 (sign_extend:DI 3875 (vec_select:HI 3876 (match_operand:V2HI 2 "register_operand" " r, r") 3877 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iv00, Iv01")]))))] 3878 UNSPEC_ROUND) 3879 (const_int 16)))))] 3880 "NDS32_EXT_DSP_P ()" 3881{ 3882 if (TARGET_BIG_ENDIAN) 3883 { 3884 const char *pats[] = { "kmmawt.u\t%0, %1, %2", 3885 "kmmawb.u\t%0, %1, %2" }; 3886 return pats[which_alternative]; 3887 } 3888 else 3889 { 3890 const char *pats[] = { "kmmawb.u\t%0, %1, %2", 3891 "kmmawt.u\t%0, %1, %2" }; 3892 return pats[which_alternative]; 3893 } 3894} 3895 [(set_attr "type" "dmac") 3896 (set_attr "length" "4")]) 3897 3898(define_expand "smalbb" 3899 [(match_operand:DI 0 "register_operand" "") 3900 (match_operand:DI 1 "register_operand" "") 3901 (match_operand:V2HI 2 "register_operand" "") 3902 (match_operand:V2HI 3 "register_operand" "")] 3903 "NDS32_EXT_DSP_P ()" 3904{ 3905 if (TARGET_BIG_ENDIAN) 3906 emit_insn (gen_smaddhidi (operands[0], operands[2], 3907 operands[3], operands[1], 3908 GEN_INT (1), GEN_INT (1))); 3909 else 3910 emit_insn (gen_smaddhidi (operands[0], operands[2], 3911 operands[3], operands[1], 3912 GEN_INT (0), GEN_INT (0))); 3913 DONE; 3914}) 3915 3916(define_expand "smalbt" 3917 [(match_operand:DI 0 "register_operand" "") 3918 (match_operand:DI 1 "register_operand" "") 3919 (match_operand:V2HI 2 "register_operand" "") 3920 (match_operand:V2HI 3 "register_operand" "")] 3921 "NDS32_EXT_DSP_P ()" 3922{ 3923 if (TARGET_BIG_ENDIAN) 3924 emit_insn (gen_smaddhidi (operands[0], operands[2], 3925 operands[3], operands[1], 3926 GEN_INT (1), GEN_INT (0))); 3927 else 3928 emit_insn (gen_smaddhidi (operands[0], operands[2], 3929 operands[3], operands[1], 3930 GEN_INT (0), GEN_INT (1))); 3931 DONE; 3932}) 3933 3934(define_expand "smaltt" 3935 [(match_operand:DI 0 "register_operand" "") 3936 (match_operand:DI 1 "register_operand" "") 3937 (match_operand:V2HI 2 "register_operand" "") 3938 (match_operand:V2HI 3 "register_operand" "")] 3939 "NDS32_EXT_DSP_P ()" 3940{ 3941 if (TARGET_BIG_ENDIAN) 3942 emit_insn (gen_smaddhidi (operands[0], operands[2], 3943 operands[3], operands[1], 3944 GEN_INT (0), GEN_INT (0))); 3945 else 3946 emit_insn (gen_smaddhidi (operands[0], operands[2], 3947 operands[3], operands[1], 3948 GEN_INT (1), GEN_INT (1))); 3949 DONE; 3950}) 3951 3952(define_insn "smaddhidi" 3953 [(set (match_operand:DI 0 "register_operand" "= r, r, r, r") 3954 (plus:DI 3955 (match_operand:DI 3 "register_operand" " 0, 0, 0, 0") 3956 (mult:DI 3957 (sign_extend:DI 3958 (vec_select:HI 3959 (match_operand:V2HI 1 "register_operand" " r, r, r, r") 3960 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) 3961 (sign_extend:DI 3962 (vec_select:HI 3963 (match_operand:V2HI 2 "register_operand" " r, r, r, r") 3964 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")]))))))] 3965 "NDS32_EXT_DSP_P ()" 3966{ 3967 if (TARGET_BIG_ENDIAN) 3968 { 3969 const char *pats[] = { "smaltt\t%0, %1, %2", 3970 "smalbt\t%0, %2, %1", 3971 "smalbb\t%0, %1, %2", 3972 "smalbt\t%0, %1, %2" }; 3973 return pats[which_alternative]; 3974 } 3975 else 3976 { 3977 const char *pats[] = { "smalbb\t%0, %1, %2", 3978 "smalbt\t%0, %1, %2", 3979 "smaltt\t%0, %1, %2", 3980 "smalbt\t%0, %2, %1" }; 3981 return pats[which_alternative]; 3982 } 3983} 3984 [(set_attr "type" "dmac") 3985 (set_attr "length" "4")]) 3986 3987(define_insn "smaddhidi2" 3988 [(set (match_operand:DI 0 "register_operand" "= r, r, r, r") 3989 (plus:DI 3990 (mult:DI 3991 (sign_extend:DI 3992 (vec_select:HI 3993 (match_operand:V2HI 1 "register_operand" " r, r, r, r") 3994 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iv00, Iv00, Iv01, Iv01")]))) 3995 (sign_extend:DI 3996 (vec_select:HI 3997 (match_operand:V2HI 2 "register_operand" " r, r, r, r") 3998 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iv00, Iv01, Iv01, Iv00")])))) 3999 (match_operand:DI 3 "register_operand" " 0, 0, 0, 0")))] 4000 "NDS32_EXT_DSP_P ()" 4001{ 4002 if (TARGET_BIG_ENDIAN) 4003 { 4004 const char *pats[] = { "smaltt\t%0, %1, %2", 4005 "smalbt\t%0, %2, %1", 4006 "smalbb\t%0, %1, %2", 4007 "smalbt\t%0, %1, %2" }; 4008 return pats[which_alternative]; 4009 } 4010 else 4011 { 4012 const char *pats[] = { "smalbb\t%0, %1, %2", 4013 "smalbt\t%0, %1, %2", 4014 "smaltt\t%0, %1, %2", 4015 "smalbt\t%0, %2, %1" }; 4016 return pats[which_alternative]; 4017 } 4018} 4019 [(set_attr "type" "dmac") 4020 (set_attr "length" "4")]) 4021 4022(define_expand "smalda1" 4023 [(match_operand:DI 0 "register_operand" "") 4024 (match_operand:DI 1 "register_operand" "") 4025 (match_operand:V2HI 2 "register_operand" " r") 4026 (match_operand:V2HI 3 "register_operand" " r")] 4027 "NDS32_EXT_DSP_P ()" 4028{ 4029 if (TARGET_BIG_ENDIAN) 4030 emit_insn (gen_smalda1_be (operands[0], operands[1], operands[2], operands[3])); 4031 else 4032 emit_insn (gen_smalda1_le (operands[0], operands[1], operands[2], operands[3])); 4033 DONE; 4034}) 4035 4036(define_expand "smalds1" 4037 [(match_operand:DI 0 "register_operand" "") 4038 (match_operand:DI 1 "register_operand" "") 4039 (match_operand:V2HI 2 "register_operand" " r") 4040 (match_operand:V2HI 3 "register_operand" " r")] 4041 "NDS32_EXT_DSP_P ()" 4042{ 4043 if (TARGET_BIG_ENDIAN) 4044 emit_insn (gen_smalds1_be (operands[0], operands[1], operands[2], operands[3])); 4045 else 4046 emit_insn (gen_smalds1_le (operands[0], operands[1], operands[2], operands[3])); 4047 DONE; 4048}) 4049 4050(define_insn "smalda1_le" 4051 [(set (match_operand:DI 0 "register_operand" "=r") 4052 (plus:DI 4053 (match_operand:DI 1 "register_operand" " 0") 4054 (sign_extend:DI 4055 (plus:SI 4056 (mult:SI 4057 (sign_extend:SI (vec_select:HI 4058 (match_operand:V2HI 2 "register_operand" " r") 4059 (parallel [(const_int 1)]))) 4060 (sign_extend:SI (vec_select:HI 4061 (match_operand:V2HI 3 "register_operand" " r") 4062 (parallel [(const_int 1)])))) 4063 (mult:SI 4064 (sign_extend:SI (vec_select:HI 4065 (match_dup 2) 4066 (parallel [(const_int 0)]))) 4067 (sign_extend:SI (vec_select:HI 4068 (match_dup 3) 4069 (parallel [(const_int 0)]))))))))] 4070 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 4071 "smalda\t%0, %2, %3" 4072 [(set_attr "type" "dmac") 4073 (set_attr "length" "4")]) 4074 4075(define_insn "smalds1_le" 4076 [(set (match_operand:DI 0 "register_operand" "=r") 4077 (plus:DI 4078 (match_operand:DI 1 "register_operand" " 0") 4079 (sign_extend:DI 4080 (minus:SI 4081 (mult:SI 4082 (sign_extend:SI (vec_select:HI 4083 (match_operand:V2HI 2 "register_operand" " r") 4084 (parallel [(const_int 1)]))) 4085 (sign_extend:SI (vec_select:HI 4086 (match_operand:V2HI 3 "register_operand" " r") 4087 (parallel [(const_int 1)])))) 4088 (mult:SI 4089 (sign_extend:SI (vec_select:HI 4090 (match_dup 2) 4091 (parallel [(const_int 0)]))) 4092 (sign_extend:SI (vec_select:HI 4093 (match_dup 3) 4094 (parallel [(const_int 0)]))))))))] 4095 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 4096 "smalds\t%0, %2, %3" 4097 [(set_attr "type" "dmac") 4098 (set_attr "length" "4")]) 4099 4100(define_insn "smalda1_be" 4101 [(set (match_operand:DI 0 "register_operand" "=r") 4102 (plus:DI 4103 (match_operand:DI 1 "register_operand" " 0") 4104 (sign_extend:DI 4105 (plus:SI 4106 (mult:SI 4107 (sign_extend:SI (vec_select:HI 4108 (match_operand:V2HI 2 "register_operand" " r") 4109 (parallel [(const_int 0)]))) 4110 (sign_extend:SI (vec_select:HI 4111 (match_operand:V2HI 3 "register_operand" " r") 4112 (parallel [(const_int 0)])))) 4113 (mult:SI 4114 (sign_extend:SI (vec_select:HI 4115 (match_dup 2) 4116 (parallel [(const_int 1)]))) 4117 (sign_extend:SI (vec_select:HI 4118 (match_dup 3) 4119 (parallel [(const_int 1)]))))))))] 4120 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 4121 "smalda\t%0, %2, %3" 4122 [(set_attr "type" "dmac") 4123 (set_attr "length" "4")]) 4124 4125(define_insn "smalds1_be" 4126 [(set (match_operand:DI 0 "register_operand" "=r") 4127 (plus:DI 4128 (match_operand:DI 1 "register_operand" " 0") 4129 (sign_extend:DI 4130 (minus:SI 4131 (mult:SI 4132 (sign_extend:SI (vec_select:HI 4133 (match_operand:V2HI 2 "register_operand" " r") 4134 (parallel [(const_int 0)]))) 4135 (sign_extend:SI (vec_select:HI 4136 (match_operand:V2HI 3 "register_operand" " r") 4137 (parallel [(const_int 0)])))) 4138 (mult:SI 4139 (sign_extend:SI (vec_select:HI 4140 (match_dup 2) 4141 (parallel [(const_int 1)]))) 4142 (sign_extend:SI (vec_select:HI 4143 (match_dup 3) 4144 (parallel [(const_int 1)]))))))))] 4145 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 4146 "smalds\t%0, %2, %3" 4147 [(set_attr "type" "dmac") 4148 (set_attr "length" "4")]) 4149 4150(define_expand "smaldrs3" 4151 [(match_operand:DI 0 "register_operand" "") 4152 (match_operand:DI 1 "register_operand" "") 4153 (match_operand:V2HI 2 "register_operand" " r") 4154 (match_operand:V2HI 3 "register_operand" " r")] 4155 "NDS32_EXT_DSP_P ()" 4156{ 4157 if (TARGET_BIG_ENDIAN) 4158 emit_insn (gen_smaldrs3_be (operands[0], operands[1], operands[2], operands[3])); 4159 else 4160 emit_insn (gen_smaldrs3_le (operands[0], operands[1], operands[2], operands[3])); 4161 DONE; 4162}) 4163 4164(define_insn "smaldrs3_le" 4165 [(set (match_operand:DI 0 "register_operand" "=r") 4166 (plus:DI 4167 (match_operand:DI 1 "register_operand" " 0") 4168 (sign_extend:DI 4169 (minus:SI 4170 (mult:SI 4171 (sign_extend:SI (vec_select:HI 4172 (match_operand:V2HI 2 "register_operand" " r") 4173 (parallel [(const_int 0)]))) 4174 (sign_extend:SI (vec_select:HI 4175 (match_operand:V2HI 3 "register_operand" " r") 4176 (parallel [(const_int 0)])))) 4177 (mult:SI 4178 (sign_extend:SI (vec_select:HI 4179 (match_dup 2) 4180 (parallel [(const_int 1)]))) 4181 (sign_extend:SI (vec_select:HI 4182 (match_dup 3) 4183 (parallel [(const_int 1)]))))))))] 4184 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 4185 "smaldrs\t%0, %2, %3" 4186 [(set_attr "type" "dmac") 4187 (set_attr "length" "4")]) 4188 4189(define_insn "smaldrs3_be" 4190 [(set (match_operand:DI 0 "register_operand" "=r") 4191 (plus:DI 4192 (match_operand:DI 1 "register_operand" " 0") 4193 (sign_extend:DI 4194 (minus:SI 4195 (mult:SI 4196 (sign_extend:SI (vec_select:HI 4197 (match_operand:V2HI 2 "register_operand" " r") 4198 (parallel [(const_int 1)]))) 4199 (sign_extend:SI (vec_select:HI 4200 (match_operand:V2HI 3 "register_operand" " r") 4201 (parallel [(const_int 1)])))) 4202 (mult:SI 4203 (sign_extend:SI (vec_select:HI 4204 (match_dup 2) 4205 (parallel [(const_int 0)]))) 4206 (sign_extend:SI (vec_select:HI 4207 (match_dup 3) 4208 (parallel [(const_int 0)]))))))))] 4209 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 4210 "smaldrs\t%0, %2, %3" 4211 [(set_attr "type" "dmac") 4212 (set_attr "length" "4")]) 4213 4214(define_expand "smalxda1" 4215 [(match_operand:DI 0 "register_operand" "") 4216 (match_operand:DI 1 "register_operand" "") 4217 (match_operand:V2HI 2 "register_operand" " r") 4218 (match_operand:V2HI 3 "register_operand" " r")] 4219 "NDS32_EXT_DSP_P ()" 4220{ 4221 if (TARGET_BIG_ENDIAN) 4222 emit_insn (gen_smalxda1_be (operands[0], operands[1], operands[2], operands[3])); 4223 else 4224 emit_insn (gen_smalxda1_le (operands[0], operands[1], operands[2], operands[3])); 4225 DONE; 4226}) 4227 4228(define_expand "smalxds1" 4229 [(match_operand:DI 0 "register_operand" "") 4230 (match_operand:DI 1 "register_operand" "") 4231 (match_operand:V2HI 2 "register_operand" " r") 4232 (match_operand:V2HI 3 "register_operand" " r")] 4233 "NDS32_EXT_DSP_P ()" 4234{ 4235 if (TARGET_BIG_ENDIAN) 4236 emit_insn (gen_smalxds1_be (operands[0], operands[1], operands[2], operands[3])); 4237 else 4238 emit_insn (gen_smalxds1_le (operands[0], operands[1], operands[2], operands[3])); 4239 DONE; 4240}) 4241 4242(define_insn "smalxd<add_sub>1_le" 4243 [(set (match_operand:DI 0 "register_operand" "=r") 4244 (plus:DI 4245 (match_operand:DI 1 "register_operand" " 0") 4246 (sign_extend:DI 4247 (plus_minus:SI 4248 (mult:SI 4249 (sign_extend:SI (vec_select:HI 4250 (match_operand:V2HI 2 "register_operand" " r") 4251 (parallel [(const_int 1)]))) 4252 (sign_extend:SI (vec_select:HI 4253 (match_operand:V2HI 3 "register_operand" " r") 4254 (parallel [(const_int 0)])))) 4255 (mult:SI 4256 (sign_extend:SI (vec_select:HI 4257 (match_dup 2) 4258 (parallel [(const_int 0)]))) 4259 (sign_extend:SI (vec_select:HI 4260 (match_dup 3) 4261 (parallel [(const_int 1)]))))))))] 4262 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 4263 "smalxd<add_sub>\t%0, %2, %3" 4264 [(set_attr "type" "dmac") 4265 (set_attr "length" "4")]) 4266 4267 4268(define_insn "smalxd<add_sub>1_be" 4269 [(set (match_operand:DI 0 "register_operand" "=r") 4270 (plus:DI 4271 (match_operand:DI 1 "register_operand" " 0") 4272 (sign_extend:DI 4273 (plus_minus:SI 4274 (mult:SI 4275 (sign_extend:SI (vec_select:HI 4276 (match_operand:V2HI 2 "register_operand" " r") 4277 (parallel [(const_int 0)]))) 4278 (sign_extend:SI (vec_select:HI 4279 (match_operand:V2HI 3 "register_operand" " r") 4280 (parallel [(const_int 1)])))) 4281 (mult:SI 4282 (sign_extend:SI (vec_select:HI 4283 (match_dup 2) 4284 (parallel [(const_int 1)]))) 4285 (sign_extend:SI (vec_select:HI 4286 (match_dup 3) 4287 (parallel [(const_int 0)]))))))))] 4288 "NDS32_EXT_DSP_P () && TARGET_BIG_ENDIAN" 4289 "smalxd<add_sub>\t%0, %2, %3" 4290 [(set_attr "type" "dmac") 4291 (set_attr "length" "4")]) 4292 4293(define_insn "smslda1" 4294 [(set (match_operand:DI 0 "register_operand" "=r") 4295 (minus:DI 4296 (minus:DI 4297 (match_operand:DI 1 "register_operand" " 0") 4298 (sign_extend:DI 4299 (mult:SI 4300 (sign_extend:SI (vec_select:HI 4301 (match_operand:V2HI 2 "register_operand" " r") 4302 (parallel [(const_int 1)]))) 4303 (sign_extend:SI (vec_select:HI 4304 (match_operand:V2HI 3 "register_operand" " r") 4305 (parallel [(const_int 1)])))))) 4306 (sign_extend:DI 4307 (mult:SI 4308 (sign_extend:SI (vec_select:HI 4309 (match_dup 2) 4310 (parallel [(const_int 0)]))) 4311 (sign_extend:SI (vec_select:HI 4312 (match_dup 3) 4313 (parallel [(const_int 0)])))))))] 4314 "NDS32_EXT_DSP_P ()" 4315 "smslda\t%0, %2, %3" 4316 [(set_attr "type" "dmac") 4317 (set_attr "length" "4")]) 4318 4319(define_insn "smslxda1" 4320 [(set (match_operand:DI 0 "register_operand" "=r") 4321 (minus:DI 4322 (minus:DI 4323 (match_operand:DI 1 "register_operand" " 0") 4324 (sign_extend:DI 4325 (mult:SI 4326 (sign_extend:SI (vec_select:HI 4327 (match_operand:V2HI 2 "register_operand" " r") 4328 (parallel [(const_int 1)]))) 4329 (sign_extend:SI (vec_select:HI 4330 (match_operand:V2HI 3 "register_operand" " r") 4331 (parallel [(const_int 0)])))))) 4332 (sign_extend:DI 4333 (mult:SI 4334 (sign_extend:SI (vec_select:HI 4335 (match_dup 2) 4336 (parallel [(const_int 0)]))) 4337 (sign_extend:SI (vec_select:HI 4338 (match_dup 3) 4339 (parallel [(const_int 1)])))))))] 4340 "NDS32_EXT_DSP_P ()" 4341 "smslxda\t%0, %2, %3" 4342 [(set_attr "type" "dmac") 4343 (set_attr "length" "4")]) 4344 4345;; mada for synthetize smalda 4346(define_insn_and_split "mada1" 4347 [(set (match_operand:SI 0 "register_operand" "=r") 4348 (plus:SI 4349 (mult:SI 4350 (sign_extend:SI (vec_select:HI 4351 (match_operand:V2HI 1 "register_operand" "r") 4352 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) 4353 (sign_extend:SI (vec_select:HI 4354 (match_operand:V2HI 2 "register_operand" "r") 4355 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) 4356 (mult:SI 4357 (sign_extend:SI (vec_select:HI 4358 (match_dup 1) 4359 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) 4360 (sign_extend:SI (vec_select:HI 4361 (match_dup 2) 4362 (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] 4363 "NDS32_EXT_DSP_P () && !reload_completed" 4364 "#" 4365 "NDS32_EXT_DSP_P () && !reload_completed" 4366 [(const_int 1)] 4367{ 4368 rtx result0 = gen_reg_rtx (SImode); 4369 rtx result1 = gen_reg_rtx (SImode); 4370 emit_insn (gen_mulhisi3v (result0, operands[1], operands[2], 4371 operands[3], operands[4])); 4372 emit_insn (gen_mulhisi3v (result1, operands[1], operands[2], 4373 operands[5], operands[6])); 4374 emit_insn (gen_addsi3 (operands[0], result0, result1)); 4375 DONE; 4376}) 4377 4378(define_insn_and_split "mada2" 4379 [(set (match_operand:SI 0 "register_operand" "=r") 4380 (plus:SI 4381 (mult:SI 4382 (sign_extend:SI (vec_select:HI 4383 (match_operand:V2HI 1 "register_operand" "r") 4384 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) 4385 (sign_extend:SI (vec_select:HI 4386 (match_operand:V2HI 2 "register_operand" "r") 4387 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) 4388 (mult:SI 4389 (sign_extend:SI (vec_select:HI 4390 (match_dup 2) 4391 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) 4392 (sign_extend:SI (vec_select:HI 4393 (match_dup 1) 4394 (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] 4395 "NDS32_EXT_DSP_P () && !reload_completed" 4396 "#" 4397 "NDS32_EXT_DSP_P () && !reload_completed" 4398 [(const_int 1)] 4399{ 4400 rtx result0 = gen_reg_rtx (SImode); 4401 rtx result1 = gen_reg_rtx (SImode); 4402 emit_insn (gen_mulhisi3v (result0, operands[1], operands[2], 4403 operands[3], operands[4])); 4404 emit_insn (gen_mulhisi3v (result1, operands[1], operands[2], 4405 operands[6], operands[5])); 4406 emit_insn (gen_addsi3 (operands[0], result0, result1)); 4407 DONE; 4408}) 4409 4410;; sms for synthetize smalds 4411(define_insn_and_split "sms1" 4412 [(set (match_operand:SI 0 "register_operand" "= r") 4413 (minus:SI 4414 (mult:SI 4415 (sign_extend:SI (vec_select:HI 4416 (match_operand:V2HI 1 "register_operand" " r") 4417 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) 4418 (sign_extend:SI (vec_select:HI 4419 (match_operand:V2HI 2 "register_operand" " r") 4420 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) 4421 (mult:SI 4422 (sign_extend:SI (vec_select:HI 4423 (match_dup 1) 4424 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) 4425 (sign_extend:SI (vec_select:HI 4426 (match_dup 2) 4427 (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] 4428 "NDS32_EXT_DSP_P () 4429 && (!reload_completed 4430 || !nds32_need_split_sms_p (operands[3], operands[4], 4431 operands[5], operands[6]))" 4432 4433{ 4434 return nds32_output_sms (operands[3], operands[4], 4435 operands[5], operands[6]); 4436} 4437 "NDS32_EXT_DSP_P () 4438 && !reload_completed 4439 && nds32_need_split_sms_p (operands[3], operands[4], 4440 operands[5], operands[6])" 4441 [(const_int 1)] 4442{ 4443 nds32_split_sms (operands[0], operands[1], operands[2], 4444 operands[3], operands[4], 4445 operands[5], operands[6]); 4446 DONE; 4447} 4448 [(set_attr "type" "dmac") 4449 (set_attr "length" "4")]) 4450 4451(define_insn_and_split "sms2" 4452 [(set (match_operand:SI 0 "register_operand" "= r") 4453 (minus:SI 4454 (mult:SI 4455 (sign_extend:SI (vec_select:HI 4456 (match_operand:V2HI 1 "register_operand" " r") 4457 (parallel [(match_operand:SI 3 "nds32_imm_0_1_operand" " Iu01")]))) 4458 (sign_extend:SI (vec_select:HI 4459 (match_operand:V2HI 2 "register_operand" " r") 4460 (parallel [(match_operand:SI 4 "nds32_imm_0_1_operand" " Iu01")])))) 4461 (mult:SI 4462 (sign_extend:SI (vec_select:HI 4463 (match_dup 2) 4464 (parallel [(match_operand:SI 5 "nds32_imm_0_1_operand" " Iu01")]))) 4465 (sign_extend:SI (vec_select:HI 4466 (match_dup 1) 4467 (parallel [(match_operand:SI 6 "nds32_imm_0_1_operand" " Iu01")]))))))] 4468 "NDS32_EXT_DSP_P () 4469 && (!reload_completed 4470 || !nds32_need_split_sms_p (operands[3], operands[4], 4471 operands[6], operands[5]))" 4472{ 4473 return nds32_output_sms (operands[3], operands[4], 4474 operands[6], operands[5]); 4475} 4476 "NDS32_EXT_DSP_P () 4477 && !reload_completed 4478 && nds32_need_split_sms_p (operands[3], operands[4], 4479 operands[6], operands[5])" 4480 [(const_int 1)] 4481{ 4482 nds32_split_sms (operands[0], operands[1], operands[2], 4483 operands[3], operands[4], 4484 operands[6], operands[5]); 4485 DONE; 4486} 4487 [(set_attr "type" "dmac") 4488 (set_attr "length" "4")]) 4489 4490(define_insn "kmda" 4491 [(set (match_operand:SI 0 "register_operand" "=r") 4492 (ss_plus:SI 4493 (mult:SI 4494 (sign_extend:SI (vec_select:HI 4495 (match_operand:V2HI 1 "register_operand" "r") 4496 (parallel [(const_int 1)]))) 4497 (sign_extend:SI (vec_select:HI 4498 (match_operand:V2HI 2 "register_operand" "r") 4499 (parallel [(const_int 1)])))) 4500 (mult:SI 4501 (sign_extend:SI (vec_select:HI 4502 (match_dup 1) 4503 (parallel [(const_int 0)]))) 4504 (sign_extend:SI (vec_select:HI 4505 (match_dup 2) 4506 (parallel [(const_int 0)]))))))] 4507 "NDS32_EXT_DSP_P ()" 4508 "kmda\t%0, %1, %2" 4509 [(set_attr "type" "dmac") 4510 (set_attr "length" "4")]) 4511 4512(define_insn "kmxda" 4513 [(set (match_operand:SI 0 "register_operand" "=r") 4514 (ss_plus:SI 4515 (mult:SI 4516 (sign_extend:SI (vec_select:HI 4517 (match_operand:V2HI 1 "register_operand" "r") 4518 (parallel [(const_int 1)]))) 4519 (sign_extend:SI (vec_select:HI 4520 (match_operand:V2HI 2 "register_operand" "r") 4521 (parallel [(const_int 0)])))) 4522 (mult:SI 4523 (sign_extend:SI (vec_select:HI 4524 (match_dup 1) 4525 (parallel [(const_int 0)]))) 4526 (sign_extend:SI (vec_select:HI 4527 (match_dup 2) 4528 (parallel [(const_int 1)]))))))] 4529 "NDS32_EXT_DSP_P ()" 4530 "kmxda\t%0, %1, %2" 4531 [(set_attr "type" "dmac") 4532 (set_attr "length" "4")]) 4533 4534(define_insn "kmada" 4535 [(set (match_operand:SI 0 "register_operand" "=r") 4536 (ss_plus:SI 4537 (match_operand:SI 1 "register_operand" " 0") 4538 (ss_plus:SI 4539 (mult:SI 4540 (sign_extend:SI (vec_select:HI 4541 (match_operand:V2HI 2 "register_operand" " r") 4542 (parallel [(const_int 1)]))) 4543 (sign_extend:SI (vec_select:HI 4544 (match_operand:V2HI 3 "register_operand" " r") 4545 (parallel [(const_int 1)])))) 4546 (mult:SI 4547 (sign_extend:SI (vec_select:HI 4548 (match_dup 2) 4549 (parallel [(const_int 0)]))) 4550 (sign_extend:SI (vec_select:HI 4551 (match_dup 3) 4552 (parallel [(const_int 0)])))))))] 4553 "NDS32_EXT_DSP_P ()" 4554 "kmada\t%0, %2, %3" 4555 [(set_attr "type" "dmac") 4556 (set_attr "length" "4")]) 4557 4558(define_insn "kmada2" 4559 [(set (match_operand:SI 0 "register_operand" "=r") 4560 (ss_plus:SI 4561 (match_operand:SI 1 "register_operand" " 0") 4562 (ss_plus:SI 4563 (mult:SI 4564 (sign_extend:SI (vec_select:HI 4565 (match_operand:V2HI 2 "register_operand" " r") 4566 (parallel [(const_int 0)]))) 4567 (sign_extend:SI (vec_select:HI 4568 (match_operand:V2HI 3 "register_operand" " r") 4569 (parallel [(const_int 0)])))) 4570 (mult:SI 4571 (sign_extend:SI (vec_select:HI 4572 (match_dup 2) 4573 (parallel [(const_int 1)]))) 4574 (sign_extend:SI (vec_select:HI 4575 (match_dup 3) 4576 (parallel [(const_int 1)])))))))] 4577 "NDS32_EXT_DSP_P ()" 4578 "kmada\t%0, %2, %3" 4579 [(set_attr "type" "dmac") 4580 (set_attr "length" "4")]) 4581 4582(define_insn "kmaxda" 4583 [(set (match_operand:SI 0 "register_operand" "=r") 4584 (ss_plus:SI 4585 (match_operand:SI 1 "register_operand" " 0") 4586 (ss_plus:SI 4587 (mult:SI 4588 (sign_extend:SI (vec_select:HI 4589 (match_operand:V2HI 2 "register_operand" " r") 4590 (parallel [(const_int 1)]))) 4591 (sign_extend:SI (vec_select:HI 4592 (match_operand:V2HI 3 "register_operand" " r") 4593 (parallel [(const_int 0)])))) 4594 (mult:SI 4595 (sign_extend:SI (vec_select:HI 4596 (match_dup 2) 4597 (parallel [(const_int 0)]))) 4598 (sign_extend:SI (vec_select:HI 4599 (match_dup 3) 4600 (parallel [(const_int 1)])))))))] 4601 "NDS32_EXT_DSP_P ()" 4602 "kmaxda\t%0, %2, %3" 4603 [(set_attr "type" "dmac") 4604 (set_attr "length" "4")]) 4605 4606(define_insn "kmads" 4607 [(set (match_operand:SI 0 "register_operand" "=r") 4608 (ss_plus:SI 4609 (match_operand:SI 1 "register_operand" " 0") 4610 (ss_minus:SI 4611 (mult:SI 4612 (sign_extend:SI (vec_select:HI 4613 (match_operand:V2HI 2 "register_operand" " r") 4614 (parallel [(const_int 1)]))) 4615 (sign_extend:SI (vec_select:HI 4616 (match_operand:V2HI 3 "register_operand" " r") 4617 (parallel [(const_int 1)])))) 4618 (mult:SI 4619 (sign_extend:SI (vec_select:HI 4620 (match_dup 2) 4621 (parallel [(const_int 0)]))) 4622 (sign_extend:SI (vec_select:HI 4623 (match_dup 3) 4624 (parallel [(const_int 0)])))))))] 4625 "NDS32_EXT_DSP_P ()" 4626 "kmads\t%0, %2, %3" 4627 [(set_attr "type" "dmac") 4628 (set_attr "length" "4")]) 4629 4630(define_insn "kmadrs" 4631 [(set (match_operand:SI 0 "register_operand" "=r") 4632 (ss_plus:SI 4633 (match_operand:SI 1 "register_operand" " 0") 4634 (ss_minus:SI 4635 (mult:SI 4636 (sign_extend:SI (vec_select:HI 4637 (match_operand:V2HI 2 "register_operand" " r") 4638 (parallel [(const_int 0)]))) 4639 (sign_extend:SI (vec_select:HI 4640 (match_operand:V2HI 3 "register_operand" " r") 4641 (parallel [(const_int 0)])))) 4642 (mult:SI 4643 (sign_extend:SI (vec_select:HI 4644 (match_dup 2) 4645 (parallel [(const_int 1)]))) 4646 (sign_extend:SI (vec_select:HI 4647 (match_dup 3) 4648 (parallel [(const_int 1)])))))))] 4649 "NDS32_EXT_DSP_P ()" 4650 "kmadrs\t%0, %2, %3" 4651 [(set_attr "type" "dmac") 4652 (set_attr "length" "4")]) 4653 4654(define_insn "kmaxds" 4655 [(set (match_operand:SI 0 "register_operand" "=r") 4656 (ss_plus:SI 4657 (match_operand:SI 1 "register_operand" " 0") 4658 (ss_minus:SI 4659 (mult:SI 4660 (sign_extend:SI (vec_select:HI 4661 (match_operand:V2HI 2 "register_operand" " r") 4662 (parallel [(const_int 1)]))) 4663 (sign_extend:SI (vec_select:HI 4664 (match_operand:V2HI 3 "register_operand" " r") 4665 (parallel [(const_int 0)])))) 4666 (mult:SI 4667 (sign_extend:SI (vec_select:HI 4668 (match_dup 2) 4669 (parallel [(const_int 0)]))) 4670 (sign_extend:SI (vec_select:HI 4671 (match_dup 3) 4672 (parallel [(const_int 1)])))))))] 4673 "NDS32_EXT_DSP_P ()" 4674 "kmaxds\t%0, %2, %3" 4675 [(set_attr "type" "dmac") 4676 (set_attr "length" "4")]) 4677 4678(define_insn "kmsda" 4679 [(set (match_operand:SI 0 "register_operand" "=r") 4680 (ss_minus:SI 4681 (match_operand:SI 1 "register_operand" " 0") 4682 (ss_minus:SI 4683 (mult:SI 4684 (sign_extend:SI (vec_select:HI 4685 (match_operand:V2HI 2 "register_operand" " r") 4686 (parallel [(const_int 1)]))) 4687 (sign_extend:SI (vec_select:HI 4688 (match_operand:V2HI 3 "register_operand" " r") 4689 (parallel [(const_int 1)])))) 4690 (mult:SI 4691 (sign_extend:SI (vec_select:HI 4692 (match_dup 2) 4693 (parallel [(const_int 0)]))) 4694 (sign_extend:SI (vec_select:HI 4695 (match_dup 3) 4696 (parallel [(const_int 0)])))))))] 4697 "NDS32_EXT_DSP_P ()" 4698 "kmsda\t%0, %2, %3" 4699 [(set_attr "type" "dmac") 4700 (set_attr "length" "4")]) 4701 4702(define_insn "kmsxda" 4703 [(set (match_operand:SI 0 "register_operand" "=r") 4704 (ss_minus:SI 4705 (match_operand:SI 1 "register_operand" " 0") 4706 (ss_minus:SI 4707 (mult:SI 4708 (sign_extend:SI (vec_select:HI 4709 (match_operand:V2HI 2 "register_operand" " r") 4710 (parallel [(const_int 1)]))) 4711 (sign_extend:SI (vec_select:HI 4712 (match_operand:V2HI 3 "register_operand" " r") 4713 (parallel [(const_int 0)])))) 4714 (mult:SI 4715 (sign_extend:SI (vec_select:HI 4716 (match_dup 2) 4717 (parallel [(const_int 0)]))) 4718 (sign_extend:SI (vec_select:HI 4719 (match_dup 3) 4720 (parallel [(const_int 1)])))))))] 4721 "NDS32_EXT_DSP_P ()" 4722 "kmsxda\t%0, %2, %3" 4723 [(set_attr "type" "dmac") 4724 (set_attr "length" "4")]) 4725 4726;; smax[8|16] and umax[8|16] 4727(define_insn "<opcode><mode>3" 4728 [(set (match_operand:VQIHI 0 "register_operand" "=r") 4729 (sumax:VQIHI (match_operand:VQIHI 1 "register_operand" " r") 4730 (match_operand:VQIHI 2 "register_operand" " r")))] 4731 "NDS32_EXT_DSP_P ()" 4732 "<opcode><bits>\t%0, %1, %2" 4733 [(set_attr "type" "dalu") 4734 (set_attr "length" "4")]) 4735 4736;; smin[8|16] and umin[8|16] 4737(define_insn "<opcode><mode>3" 4738 [(set (match_operand:VQIHI 0 "register_operand" "=r") 4739 (sumin:VQIHI (match_operand:VQIHI 1 "register_operand" " r") 4740 (match_operand:VQIHI 2 "register_operand" " r")))] 4741 "NDS32_EXT_DSP_P ()" 4742 "<opcode><bits>\t%0, %1, %2" 4743 [(set_attr "type" "dalu") 4744 (set_attr "length" "4")]) 4745 4746(define_insn "<opcode><mode>3_bb" 4747 [(set (match_operand:<VELT> 0 "register_operand" "=r") 4748 (sumin_max:<VELT> (vec_select:<VELT> 4749 (match_operand:VQIHI 1 "register_operand" " r") 4750 (parallel [(const_int 0)])) 4751 (vec_select:<VELT> 4752 (match_operand:VQIHI 2 "register_operand" " r") 4753 (parallel [(const_int 0)]))))] 4754 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 4755 "<opcode><bits>\t%0, %1, %2" 4756 [(set_attr "type" "dalu") 4757 (set_attr "length" "4")]) 4758 4759(define_insn_and_split "<opcode><mode>3_tt" 4760 [(set (match_operand:<VELT> 0 "register_operand" "=r") 4761 (sumin_max:<VELT> (vec_select:<VELT> 4762 (match_operand:VQIHI 1 "register_operand" " r") 4763 (parallel [(const_int 1)])) 4764 (vec_select:<VELT> 4765 (match_operand:VQIHI 2 "register_operand" " r") 4766 (parallel [(const_int 1)]))))] 4767 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 4768 "#" 4769 "NDS32_EXT_DSP_P () && !reload_completed" 4770 [(const_int 0)] 4771{ 4772 rtx tmp = gen_reg_rtx (<MODE>mode); 4773 emit_insn (gen_<opcode><mode>3 (tmp, operands[1], operands[2])); 4774 emit_insn (gen_rotr<mode>_1 (tmp, tmp)); 4775 emit_move_insn (operands[0], simplify_gen_subreg (<VELT>mode, tmp, <MODE>mode, 0)); 4776 DONE; 4777} 4778 [(set_attr "type" "dalu") 4779 (set_attr "length" "4")]) 4780 4781(define_insn_and_split "<opcode>v4qi3_22" 4782 [(set (match_operand:QI 0 "register_operand" "=r") 4783 (sumin_max:QI (vec_select:QI 4784 (match_operand:V4QI 1 "register_operand" " r") 4785 (parallel [(const_int 2)])) 4786 (vec_select:QI 4787 (match_operand:V4QI 2 "register_operand" " r") 4788 (parallel [(const_int 2)]))))] 4789 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 4790 "#" 4791 "NDS32_EXT_DSP_P () && !reload_completed" 4792 [(const_int 0)] 4793{ 4794 rtx tmp = gen_reg_rtx (V4QImode); 4795 emit_insn (gen_<opcode>v4qi3 (tmp, operands[1], operands[2])); 4796 emit_insn (gen_rotrv4qi_2 (tmp, tmp)); 4797 emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0)); 4798 DONE; 4799} 4800 [(set_attr "type" "dalu") 4801 (set_attr "length" "4")]) 4802 4803(define_insn_and_split "<opcode>v4qi3_33" 4804 [(set (match_operand:QI 0 "register_operand" "=r") 4805 (sumin_max:QI (vec_select:QI 4806 (match_operand:V4QI 1 "register_operand" " r") 4807 (parallel [(const_int 3)])) 4808 (vec_select:QI 4809 (match_operand:V4QI 2 "register_operand" " r") 4810 (parallel [(const_int 3)]))))] 4811 "NDS32_EXT_DSP_P () && !reload_completed && !TARGET_BIG_ENDIAN" 4812 "#" 4813 "NDS32_EXT_DSP_P () && !reload_completed" 4814 [(const_int 0)] 4815{ 4816 rtx tmp = gen_reg_rtx (V4QImode); 4817 emit_insn (gen_<opcode>v4qi3 (tmp, operands[1], operands[2])); 4818 emit_insn (gen_rotrv4qi_3 (tmp, tmp)); 4819 emit_move_insn (operands[0], simplify_gen_subreg (QImode, tmp, V4QImode, 0)); 4820 DONE; 4821} 4822 [(set_attr "type" "dalu") 4823 (set_attr "length" "4")]) 4824 4825(define_insn_and_split "<opcode>v2hi3_bbtt" 4826 [(set (match_operand:V2HI 0 "register_operand" "=r") 4827 (vec_merge:V2HI 4828 (vec_duplicate:V2HI 4829 (sumin_max:HI (vec_select:HI 4830 (match_operand:V2HI 1 "register_operand" " r") 4831 (parallel [(const_int 1)])) 4832 (vec_select:HI 4833 (match_operand:V2HI 2 "register_operand" " r") 4834 (parallel [(const_int 1)])))) 4835 (vec_duplicate:V2HI 4836 (sumin_max:HI (vec_select:HI 4837 (match_dup:V2HI 1) 4838 (parallel [(const_int 0)])) 4839 (vec_select:HI 4840 (match_dup:V2HI 2) 4841 (parallel [(const_int 0)])))) 4842 (const_int 2)))] 4843 "NDS32_EXT_DSP_P () && !TARGET_BIG_ENDIAN" 4844 "#" 4845 "NDS32_EXT_DSP_P ()" 4846 [(const_int 0)] 4847{ 4848 emit_insn (gen_<opcode>v2hi3 (operands[0], operands[1], operands[2])); 4849 DONE; 4850} 4851 [(set_attr "type" "dalu") 4852 (set_attr "length" "4")]) 4853 4854(define_expand "abs<mode>2" 4855 [(set (match_operand:VQIHI 0 "register_operand" "=r") 4856 (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))] 4857 "NDS32_EXT_DSP_P () && TARGET_HW_ABS && !flag_wrapv" 4858{ 4859}) 4860 4861(define_insn "kabs<mode>2" 4862 [(set (match_operand:VQIHI 0 "register_operand" "=r") 4863 (ss_abs:VQIHI (match_operand:VQIHI 1 "register_operand" " r")))] 4864 "NDS32_EXT_DSP_P ()" 4865 "kabs<bits>\t%0, %1" 4866 [(set_attr "type" "dalu") 4867 (set_attr "length" "4")]) 4868 4869(define_insn "<su>mar64_1" 4870 [(set (match_operand:DI 0 "register_operand" "=r") 4871 (plus:DI 4872 (match_operand:DI 1 "register_operand" " 0") 4873 (mult:DI 4874 (extend:DI 4875 (match_operand:SI 2 "register_operand" " r")) 4876 (extend:DI 4877 (match_operand:SI 3 "register_operand" " r")))))] 4878 "NDS32_EXT_DSP_P ()" 4879 "<su>mar64\t%0, %2, %3" 4880 [(set_attr "type" "dmac") 4881 (set_attr "length" "4")]) 4882 4883(define_insn "<su>mar64_2" 4884 [(set (match_operand:DI 0 "register_operand" "=r") 4885 (plus:DI 4886 (mult:DI 4887 (extend:DI 4888 (match_operand:SI 2 "register_operand" " r")) 4889 (extend:DI 4890 (match_operand:SI 3 "register_operand" " r"))) 4891 (match_operand:DI 1 "register_operand" " 0")))] 4892 "NDS32_EXT_DSP_P ()" 4893 "<su>mar64\t%0, %2, %3" 4894 [(set_attr "type" "dmac") 4895 (set_attr "length" "4")]) 4896 4897(define_insn "<su>mar64_3" 4898 [(set (match_operand:DI 0 "register_operand" "=r") 4899 (plus:DI 4900 (match_operand:DI 1 "register_operand" " 0") 4901 (extend:DI 4902 (mult:SI 4903 (match_operand:SI 2 "register_operand" " r") 4904 (match_operand:SI 3 "register_operand" " r")))))] 4905 "NDS32_EXT_DSP_P ()" 4906 "<su>mar64\t%0, %2, %3" 4907 [(set_attr "type" "dmac") 4908 (set_attr "length" "4")]) 4909 4910(define_insn "<su>mar64_4" 4911 [(set (match_operand:DI 0 "register_operand" "=r") 4912 (plus:DI 4913 (extend:DI 4914 (mult:SI 4915 (match_operand:SI 2 "register_operand" " r") 4916 (match_operand:SI 3 "register_operand" " r"))) 4917 (match_operand:DI 1 "register_operand" " 0")))] 4918 "NDS32_EXT_DSP_P ()" 4919 "<su>mar64\t%0, %2, %3" 4920 [(set_attr "type" "dmac") 4921 (set_attr "length" "4")]) 4922 4923(define_insn "<su>msr64" 4924 [(set (match_operand:DI 0 "register_operand" "=r") 4925 (minus:DI 4926 (match_operand:DI 1 "register_operand" " 0") 4927 (mult:DI 4928 (extend:DI 4929 (match_operand:SI 2 "register_operand" " r")) 4930 (extend:DI 4931 (match_operand:SI 3 "register_operand" " r")))))] 4932 "NDS32_EXT_DSP_P ()" 4933 "<su>msr64\t%0, %2, %3" 4934 [(set_attr "type" "dmac") 4935 (set_attr "length" "4")]) 4936 4937(define_insn "<su>msr64_2" 4938 [(set (match_operand:DI 0 "register_operand" "=r") 4939 (minus:DI 4940 (match_operand:DI 1 "register_operand" " 0") 4941 (extend:DI 4942 (mult:SI 4943 (match_operand:SI 2 "register_operand" " r") 4944 (match_operand:SI 3 "register_operand" " r")))))] 4945 "NDS32_EXT_DSP_P ()" 4946 "<su>msr64\t%0, %2, %3" 4947 [(set_attr "type" "dmac") 4948 (set_attr "length" "4")]) 4949 4950;; kmar64, kmsr64, ukmar64 and ukmsr64 4951(define_insn "kmar64_1" 4952 [(set (match_operand:DI 0 "register_operand" "=r") 4953 (ss_plus:DI 4954 (match_operand:DI 1 "register_operand" " 0") 4955 (mult:DI 4956 (sign_extend:DI 4957 (match_operand:SI 2 "register_operand" " r")) 4958 (sign_extend:DI 4959 (match_operand:SI 3 "register_operand" " r")))))] 4960 "NDS32_EXT_DSP_P ()" 4961 "kmar64\t%0, %2, %3" 4962 [(set_attr "type" "dmac") 4963 (set_attr "length" "4")]) 4964 4965(define_insn "kmar64_2" 4966 [(set (match_operand:DI 0 "register_operand" "=r") 4967 (ss_plus:DI 4968 (mult:DI 4969 (sign_extend:DI 4970 (match_operand:SI 2 "register_operand" " r")) 4971 (sign_extend:DI 4972 (match_operand:SI 3 "register_operand" " r"))) 4973 (match_operand:DI 1 "register_operand" " 0")))] 4974 "NDS32_EXT_DSP_P ()" 4975 "kmar64\t%0, %2, %3" 4976 [(set_attr "type" "dmac") 4977 (set_attr "length" "4")]) 4978 4979(define_insn "kmsr64" 4980 [(set (match_operand:DI 0 "register_operand" "=r") 4981 (ss_minus:DI 4982 (match_operand:DI 1 "register_operand" " 0") 4983 (mult:DI 4984 (sign_extend:DI 4985 (match_operand:SI 2 "register_operand" " r")) 4986 (sign_extend:DI 4987 (match_operand:SI 3 "register_operand" " r")))))] 4988 "NDS32_EXT_DSP_P ()" 4989 "kmsr64\t%0, %2, %3" 4990 [(set_attr "type" "dmac") 4991 (set_attr "length" "4")]) 4992 4993(define_insn "ukmar64_1" 4994 [(set (match_operand:DI 0 "register_operand" "=r") 4995 (us_plus:DI 4996 (match_operand:DI 1 "register_operand" " 0") 4997 (mult:DI 4998 (zero_extend:DI 4999 (match_operand:SI 2 "register_operand" " r")) 5000 (zero_extend:DI 5001 (match_operand:SI 3 "register_operand" " r")))))] 5002 "NDS32_EXT_DSP_P ()" 5003 "ukmar64\t%0, %2, %3" 5004 [(set_attr "type" "dmac") 5005 (set_attr "length" "4")]) 5006 5007(define_insn "ukmar64_2" 5008 [(set (match_operand:DI 0 "register_operand" "=r") 5009 (us_plus:DI 5010 (mult:DI 5011 (zero_extend:DI 5012 (match_operand:SI 2 "register_operand" " r")) 5013 (zero_extend:DI 5014 (match_operand:SI 3 "register_operand" " r"))) 5015 (match_operand:DI 1 "register_operand" " 0")))] 5016 "NDS32_EXT_DSP_P ()" 5017 "ukmar64\t%0, %2, %3" 5018 [(set_attr "type" "dmac") 5019 (set_attr "length" "4")]) 5020 5021(define_insn "ukmsr64" 5022 [(set (match_operand:DI 0 "register_operand" "=r") 5023 (us_minus:DI 5024 (match_operand:DI 1 "register_operand" " 0") 5025 (mult:DI 5026 (zero_extend:DI 5027 (match_operand:SI 2 "register_operand" " r")) 5028 (zero_extend:DI 5029 (match_operand:SI 3 "register_operand" " r")))))] 5030 "NDS32_EXT_DSP_P ()" 5031 "ukmsr64\t%0, %2, %3" 5032 [(set_attr "type" "dmac") 5033 (set_attr "length" "4")]) 5034 5035(define_insn "bpick1" 5036 [(set (match_operand:SI 0 "register_operand" "=r") 5037 (ior:SI 5038 (and:SI 5039 (match_operand:SI 1 "register_operand" " r") 5040 (match_operand:SI 3 "register_operand" " r")) 5041 (and:SI 5042 (match_operand:SI 2 "register_operand" " r") 5043 (not:SI (match_dup 3)))))] 5044 "NDS32_EXT_DSP_P ()" 5045 "bpick\t%0, %1, %2, %3" 5046 [(set_attr "type" "dbpick") 5047 (set_attr "length" "4")]) 5048 5049(define_insn "bpick2" 5050 [(set (match_operand:SI 0 "register_operand" "=r") 5051 (ior:SI 5052 (and:SI 5053 (match_operand:SI 1 "register_operand" " r") 5054 (match_operand:SI 2 "register_operand" " r")) 5055 (and:SI 5056 (not:SI (match_dup 2)) 5057 (match_operand:SI 3 "register_operand" " r"))))] 5058 "NDS32_EXT_DSP_P ()" 5059 "bpick\t%0, %1, %3, %2" 5060 [(set_attr "type" "dbpick") 5061 (set_attr "length" "4")]) 5062 5063(define_insn "bpick3" 5064 [(set (match_operand:SI 0 "register_operand" "=r") 5065 (ior:SI 5066 (and:SI 5067 (match_operand:SI 1 "register_operand" " r") 5068 (match_operand:SI 2 "register_operand" " r")) 5069 (and:SI 5070 (match_operand:SI 3 "register_operand" " r") 5071 (not:SI (match_dup 1)))))] 5072 "NDS32_EXT_DSP_P ()" 5073 "bpick\t%0, %2, %3, %1" 5074 [(set_attr "type" "dbpick") 5075 (set_attr "length" "4")]) 5076 5077(define_insn "bpick4" 5078 [(set (match_operand:SI 0 "register_operand" "=r") 5079 (ior:SI 5080 (and:SI 5081 (match_operand:SI 1 "register_operand" " r") 5082 (match_operand:SI 2 "register_operand" " r")) 5083 (and:SI 5084 (not:SI (match_dup 1)) 5085 (match_operand:SI 3 "register_operand" " r"))))] 5086 "NDS32_EXT_DSP_P ()" 5087 "bpick\t%0, %2, %3, %1" 5088 [(set_attr "type" "dbpick") 5089 (set_attr "length" "4")]) 5090 5091(define_insn "bpick5" 5092 [(set (match_operand:SI 0 "register_operand" "=r") 5093 (ior:SI 5094 (and:SI 5095 (match_operand:SI 1 "register_operand" " r") 5096 (not:SI (match_operand:SI 2 "register_operand" " r"))) 5097 (and:SI 5098 (match_operand:SI 3 "register_operand" " r") 5099 (match_dup 2))))] 5100 "NDS32_EXT_DSP_P ()" 5101 "bpick\t%0, %3, %1, %2" 5102 [(set_attr "type" "dbpick") 5103 (set_attr "length" "4")]) 5104 5105(define_insn "bpick6" 5106 [(set (match_operand:SI 0 "register_operand" "=r") 5107 (ior:SI 5108 (and:SI 5109 (not:SI (match_operand:SI 1 "register_operand" " r")) 5110 (match_operand:SI 2 "register_operand" " r")) 5111 (and:SI 5112 (match_operand:SI 3 "register_operand" " r") 5113 (match_dup 1))))] 5114 "NDS32_EXT_DSP_P ()" 5115 "bpick\t%0, %3, %2, %1" 5116 [(set_attr "type" "dbpick") 5117 (set_attr "length" "4")]) 5118 5119(define_insn "bpick7" 5120 [(set (match_operand:SI 0 "register_operand" "=r") 5121 (ior:SI 5122 (and:SI 5123 (match_operand:SI 1 "register_operand" " r") 5124 (not:SI (match_operand:SI 2 "register_operand" " r"))) 5125 (and:SI 5126 (match_dup 2) 5127 (match_operand:SI 3 "register_operand" " r"))))] 5128 "NDS32_EXT_DSP_P ()" 5129 "bpick\t%0, %3, %1, %2" 5130 [(set_attr "type" "dbpick") 5131 (set_attr "length" "4")]) 5132 5133(define_insn "bpick8" 5134 [(set (match_operand:SI 0 "register_operand" "=r") 5135 (ior:SI 5136 (and:SI 5137 (not:SI (match_operand:SI 1 "register_operand" " r")) 5138 (match_operand:SI 2 "register_operand" " r")) 5139 (and:SI 5140 (match_dup 1) 5141 (match_operand:SI 3 "register_operand" " r"))))] 5142 "NDS32_EXT_DSP_P ()" 5143 "bpick\t%0, %3, %2, %1" 5144 [(set_attr "type" "dbpick") 5145 (set_attr "length" "4")]) 5146 5147(define_insn "sraiu" 5148 [(set (match_operand:SI 0 "register_operand" "= r, r") 5149 (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r, r") 5150 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r"))] 5151 UNSPEC_ROUND))] 5152 "NDS32_EXT_DSP_P ()" 5153 "@ 5154 srai.u\t%0, %1, %2 5155 sra.u\t%0, %1, %2" 5156 [(set_attr "type" "daluround") 5157 (set_attr "length" "4")]) 5158 5159(define_insn "kssl" 5160 [(set (match_operand:SI 0 "register_operand" "= r, r") 5161 (ss_ashift:SI (match_operand:SI 1 "register_operand" " r, r") 5162 (match_operand:SI 2 "nds32_rimm5u_operand" " Iu05, r")))] 5163 "NDS32_EXT_DSP_P ()" 5164 "@ 5165 kslli\t%0, %1, %2 5166 ksll\t%0, %1, %2" 5167 [(set_attr "type" "dalu") 5168 (set_attr "length" "4")]) 5169 5170(define_insn "kslraw_round" 5171 [(set (match_operand:SI 0 "register_operand" "=r") 5172 (if_then_else:SI 5173 (lt:SI (match_operand:SI 2 "register_operand" " r") 5174 (const_int 0)) 5175 (unspec:SI [(ashiftrt:SI (match_operand:SI 1 "register_operand" " r") 5176 (neg:SI (match_dup 2)))] 5177 UNSPEC_ROUND) 5178 (ss_ashift:SI (match_dup 1) 5179 (match_dup 2))))] 5180 "NDS32_EXT_DSP_P ()" 5181 "kslraw.u\t%0, %1, %2" 5182 [(set_attr "type" "daluround") 5183 (set_attr "length" "4")]) 5184 5185(define_insn_and_split "<shift>di3" 5186 [(set (match_operand:DI 0 "register_operand" "") 5187 (shift_rotate:DI (match_operand:DI 1 "register_operand" "") 5188 (match_operand:SI 2 "nds32_rimm6u_operand" "")))] 5189 "NDS32_EXT_DSP_P () && !reload_completed" 5190 "#" 5191 "NDS32_EXT_DSP_P () && !reload_completed" 5192 [(const_int 0)] 5193{ 5194 if (REGNO (operands[0]) == REGNO (operands[1])) 5195 { 5196 rtx tmp = gen_reg_rtx (DImode); 5197 nds32_split_<code>di3 (tmp, operands[1], operands[2]); 5198 emit_move_insn (operands[0], tmp); 5199 } 5200 else 5201 nds32_split_<code>di3 (operands[0], operands[1], operands[2]); 5202 DONE; 5203}) 5204 5205(define_insn "sclip32" 5206 [(set (match_operand:SI 0 "register_operand" "=r") 5207 (unspec:SI [(match_operand:SI 1 "register_operand" "r") 5208 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIPS_OV))] 5209 "NDS32_EXT_DSP_P ()" 5210 "sclip32\t%0, %1, %2" 5211 [(set_attr "type" "dclip") 5212 (set_attr "length" "4")] 5213) 5214 5215(define_insn "uclip32" 5216 [(set (match_operand:SI 0 "register_operand" "=r") 5217 (unspec:SI [(match_operand:SI 1 "register_operand" "r") 5218 (match_operand:SI 2 "immediate_operand" "i")] UNSPEC_CLIP_OV))] 5219 "NDS32_EXT_DSP_P ()" 5220 "uclip32\t%0, %1, %2" 5221 [(set_attr "type" "dclip") 5222 (set_attr "length" "4")] 5223) 5224 5225(define_insn "bitrev" 5226 [(set (match_operand:SI 0 "register_operand" "=r, r") 5227 (unspec:SI [(match_operand:SI 1 "register_operand" " r, r") 5228 (match_operand:SI 2 "nds32_rimm5u_operand" " r, Iu05")] 5229 UNSPEC_BITREV))] 5230 "" 5231 "@ 5232 bitrev\t%0, %1, %2 5233 bitrevi\t%0, %1, %2" 5234 [(set_attr "type" "dalu") 5235 (set_attr "length" "4")] 5236) 5237 5238;; wext, wexti 5239(define_insn "<su>wext" 5240 [(set (match_operand:SI 0 "register_operand" "=r, r") 5241 (truncate:SI 5242 (shiftrt:DI 5243 (match_operand:DI 1 "register_operand" " r, r") 5244 (match_operand:SI 2 "nds32_rimm5u_operand" " r,Iu05"))))] 5245 "NDS32_EXT_DSP_P ()" 5246 "@ 5247 wext\t%0, %1, %2 5248 wexti\t%0, %1, %2" 5249 [(set_attr "type" "dwext") 5250 (set_attr "length" "4")]) 5251 5252;; 32-bit add/sub instruction: raddw and rsubw. 5253(define_insn "r<opcode>si3" 5254 [(set (match_operand:SI 0 "register_operand" "=r") 5255 (truncate:SI 5256 (ashiftrt:DI 5257 (plus_minus:DI 5258 (sign_extend:DI (match_operand:SI 1 "register_operand" " r")) 5259 (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))) 5260 (const_int 1))))] 5261 "NDS32_EXT_DSP_P ()" 5262 "r<opcode>w\t%0, %1, %2" 5263 [(set_attr "type" "dalu") 5264 (set_attr "length" "4")]) 5265 5266;; 32-bit add/sub instruction: uraddw and ursubw. 5267(define_insn "ur<opcode>si3" 5268 [(set (match_operand:SI 0 "register_operand" "=r") 5269 (truncate:SI 5270 (lshiftrt:DI 5271 (plus_minus:DI 5272 (zero_extend:DI (match_operand:SI 1 "register_operand" " r")) 5273 (zero_extend:DI (match_operand:SI 2 "register_operand" " r"))) 5274 (const_int 1))))] 5275 "NDS32_EXT_DSP_P ()" 5276 "ur<opcode>w\t%0, %1, %2" 5277 [(set_attr "type" "dalu") 5278 (set_attr "length" "4")]) 5279