1;; GCC machine description for Matsushita MN10300 2;; Copyright (C) 1996-2018 Free Software Foundation, Inc. 3;; Contributed by Jeff Law (law@cygnus.com). 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; The original PO technology requires these to be ordered by speed, 22;; so that assigner will pick the fastest. 23 24;; See file "rtl.def" for documentation on define_insn, match_*, et. al. 25 26(define_constants [ 27 (PIC_REG 6) 28 (SP_REG 9) 29 (MDR_REG 50) 30 (CC_REG 51) 31 32 (UNSPEC_PIC 1) 33 (UNSPEC_GOT 2) 34 (UNSPEC_GOTOFF 3) 35 (UNSPEC_PLT 4) 36 (UNSPEC_GOTSYM_OFF 5) 37 38 (UNSPEC_EXT 6) 39 (UNSPEC_BSCH 7) 40 41 ;; This is used to encode LIW patterns. 42 (UNSPEC_LIW 8) 43 ;; This is for the low overhead loop instructions. 44 (UNSPEC_SETLB 9) 45]) 46 47(include "predicates.md") 48(include "constraints.md") 49 50;; Processor type. This attribute must exactly match the processor_type 51;; enumeration in mn10300.h. 52(define_attr "cpu" "mn10300,am33,am33_2,am34" 53 (const (symbol_ref "(enum attr_cpu) mn10300_tune_cpu"))) 54 55;; Used to control the "enabled" attribute on a per-instruction basis. 56(define_attr "isa" "base,am33,am33_2,am34" 57 (const_string "base")) 58 59(define_attr "enabled" "" 60 (cond [(eq_attr "isa" "base") 61 (const_int 1) 62 63 (and (eq_attr "isa" "am33") 64 (match_test "TARGET_AM33")) 65 (const_int 1) 66 67 (and (eq_attr "isa" "am33_2") 68 (match_test "TARGET_AM33_2")) 69 (const_int 1) 70 71 (and (eq_attr "isa" "am34") 72 (match_test "TARGET_AM34")) 73 (const_int 1) 74 ] 75 (const_int 0)) 76) 77 78(define_mode_iterator INT [QI HI SI]) 79 80 81;; Bundling of smaller insns into a long instruction word (LIW) 82(define_automaton "liw_bundling") 83(automata_option "ndfa") 84 85(define_cpu_unit "liw_op1_u,liw_op2_u" "liw_bundling") 86 87(define_attr "liw" "op1,op2,both,either" 88 (const_string "both")) 89;; Note: this list must match the one defined for liw_op_names[]. 90(define_attr "liw_op" "add,cmp,sub,mov,and,or,xor,asr,lsr,asl,none,max" 91 (const_string "none")) 92 93(define_insn_reservation "liw_op1" 1 94 (and (ior (eq_attr "cpu" "am33") 95 (eq_attr "cpu" "am33_2") 96 (eq_attr "cpu" "am34")) 97 (eq_attr "liw" "op1")) 98 "liw_op1_u"); 99(define_insn_reservation "liw_op2" 1 100 (and (ior (eq_attr "cpu" "am33") 101 (eq_attr "cpu" "am33_2") 102 (eq_attr "cpu" "am34")) 103 (eq_attr "liw" "op2")) 104 "liw_op2_u"); 105(define_insn_reservation "liw_both" 1 106 (and (ior (eq_attr "cpu" "am33") 107 (eq_attr "cpu" "am33_2") 108 (eq_attr "cpu" "am34")) 109 (eq_attr "liw" "both")) 110 "liw_op1_u + liw_op2_u"); 111(define_insn_reservation "liw_either" 1 112 (and (ior (eq_attr "cpu" "am33") 113 (eq_attr "cpu" "am33_2") 114 (eq_attr "cpu" "am34")) 115 (eq_attr "liw" "either")) 116 "liw_op1_u | liw_op2_u"); 117 118;; ---------------------------------------------------------------------- 119;; Pipeline description. 120;; ---------------------------------------------------------------------- 121 122;; The AM33 only has a single pipeline. It has five stages (fetch, 123;; decode, execute, memory access, writeback) each of which normally 124;; takes a single CPU clock cycle. 125 126;; The timings attribute consists of two numbers, the first is the 127;; throughput, which is the number of cycles the instruction takes 128;; to execute and generate a result. The second is the latency 129;; which is the effective number of cycles the instruction takes to 130;; execute if its result is used by the following instruction. The 131;; latency is always greater than or equal to the throughput. 132;; These values were taken from the Appendix of the "MN103E Series 133;; Instruction Manual" and the timings for the AM34. 134 135;; Note - it would be nice to use strings rather than integers for 136;; the possible values of this attribute, so that we can have the 137;; gcc build mechanism check for values that are not supported by 138;; the reservations below. But this will not work because the code 139;; in mn10300_adjust_sched_cost() needs integers not strings. 140 141(define_attr "timings" "" (const_int 11)) 142 143(define_automaton "pipelining") 144(define_cpu_unit "throughput" "pipelining") 145 146(define_insn_reservation "throughput__1_latency__1" 1 147 (eq_attr "timings" "11") "throughput") 148(define_insn_reservation "throughput__1_latency__2" 2 149 (eq_attr "timings" "12") "throughput,nothing") 150(define_insn_reservation "throughput__1_latency__3" 3 151 (eq_attr "timings" "13") "throughput,nothing*2") 152(define_insn_reservation "throughput__1_latency__4" 4 153 (eq_attr "timings" "14") "throughput,nothing*3") 154(define_insn_reservation "throughput__2_latency__2" 2 155 (eq_attr "timings" "22") "throughput*2") 156(define_insn_reservation "throughput__2_latency__3" 3 157 (eq_attr "timings" "23") "throughput*2,nothing") 158(define_insn_reservation "throughput__2_latency__4" 4 159 (eq_attr "timings" "24") "throughput*2,nothing*2") 160(define_insn_reservation "throughput__2_latency__5" 5 161 (eq_attr "timings" "25") "throughput*2,nothing*3") 162(define_insn_reservation "throughput__3_latency__3" 3 163 (eq_attr "timings" "33") "throughput*3") 164(define_insn_reservation "throughput__3_latency__7" 7 165 (eq_attr "timings" "37") "throughput*3,nothing*4") 166(define_insn_reservation "throughput__4_latency__4" 4 167 (eq_attr "timings" "44") "throughput*4") 168(define_insn_reservation "throughput__4_latency__7" 7 169 (eq_attr "timings" "47") "throughput*4,nothing*3") 170(define_insn_reservation "throughput__4_latency__8" 8 171 (eq_attr "timings" "48") "throughput*4,nothing*4") 172(define_insn_reservation "throughput__5_latency__5" 5 173 (eq_attr "timings" "55") "throughput*5") 174(define_insn_reservation "throughput__6_latency__6" 6 175 (eq_attr "timings" "66") "throughput*6") 176(define_insn_reservation "throughput__7_latency__7" 7 177 (eq_attr "timings" "77") "throughput*7") 178(define_insn_reservation "throughput__7_latency__8" 8 179 (eq_attr "timings" "78") "throughput*7,nothing") 180(define_insn_reservation "throughput__8_latency__8" 8 181 (eq_attr "timings" "88") "throughput*8") 182(define_insn_reservation "throughput__9_latency__9" 9 183 (eq_attr "timings" "99") "throughput*9") 184(define_insn_reservation "throughput__8_latency_14" 14 185 (eq_attr "timings" "814") "throughput*8,nothing*6") 186(define_insn_reservation "throughput__9_latency_10" 10 187 (eq_attr "timings" "910") "throughput*9,nothing") 188(define_insn_reservation "throughput_10_latency_10" 10 189 (eq_attr "timings" "1010") "throughput*10") 190(define_insn_reservation "throughput_12_latency_16" 16 191 (eq_attr "timings" "1216") "throughput*12,nothing*4") 192(define_insn_reservation "throughput_13_latency_13" 13 193 (eq_attr "timings" "1313") "throughput*13") 194(define_insn_reservation "throughput_14_latency_14" 14 195 (eq_attr "timings" "1414") "throughput*14") 196(define_insn_reservation "throughput_13_latency_17" 17 197 (eq_attr "timings" "1317") "throughput*13,nothing*4") 198(define_insn_reservation "throughput_23_latency_27" 27 199 (eq_attr "timings" "2327") "throughput*23,nothing*4") 200(define_insn_reservation "throughput_25_latency_31" 31 201 (eq_attr "timings" "2531") "throughput*25,nothing*6") 202(define_insn_reservation "throughput_38_latency_39" 39 203 (eq_attr "timings" "3839") "throughput*38,nothing") 204(define_insn_reservation "throughput_39_latency_40" 40 205 (eq_attr "timings" "3940") "throughput*39,nothing") 206(define_insn_reservation "throughput_40_latency_40" 40 207 (eq_attr "timings" "4040") "throughput*40") 208(define_insn_reservation "throughput_41_latency_42" 42 209 (eq_attr "timings" "4142") "throughput*41,nothing") 210(define_insn_reservation "throughput_42_latency_43" 44 211 (eq_attr "timings" "4243") "throughput*42,nothing") 212(define_insn_reservation "throughput_43_latency_44" 44 213 (eq_attr "timings" "4344") "throughput*43,nothing") 214(define_insn_reservation "throughput_45_latency_46" 46 215 (eq_attr "timings" "4546") "throughput*45,nothing") 216(define_insn_reservation "throughput_47_latency_53" 53 217 (eq_attr "timings" "4753") "throughput*47,nothing*6") 218 219;; Note - the conflict between memory load/store instructions 220;; and floating point instructions described in section 1-7-4 221;; of Chapter 3 of the MN103E Series Instruction Manual is 222;; handled by the mn10300_adjust_sched_cost function. 223 224;; ---------------------------------------------------------------------- 225;; MOVE INSTRUCTIONS 226;; ---------------------------------------------------------------------- 227 228;; movqi 229 230(define_expand "movqi" 231 [(set (match_operand:QI 0 "nonimmediate_operand") 232 (match_operand:QI 1 "general_operand"))] 233 "" 234{ 235 /* One of the ops has to be in a register. */ 236 if (!register_operand (operand0, QImode) 237 && !register_operand (operand1, QImode)) 238 operands[1] = force_reg (QImode, operand1); 239}) 240 241(define_insn "*movqi_internal" 242 [(set (match_operand:QI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d") 243 (match_operand:QI 1 "general_operand" " 0,D*r, i,m,D,d,*z"))] 244 "(register_operand (operands[0], QImode) 245 || register_operand (operands[1], QImode))" 246{ 247 switch (which_alternative) 248 { 249 case 0: 250 return ""; 251 case 1: 252 case 2: 253 case 5: 254 case 6: 255 return "mov %1,%0"; 256 case 3: 257 case 4: 258 return "movbu %1,%0"; 259 default: 260 gcc_unreachable (); 261 } 262} 263 [(set_attr_alternative "timings" 264 [(const_int 11) 265 (const_int 11) 266 (const_int 11) 267 (if_then_else (eq_attr "cpu" "am34") 268 (const_int 13) (const_int 24)) 269 (if_then_else (eq_attr "cpu" "am34") 270 (const_int 11) (const_int 22)) 271 (const_int 11) 272 (const_int 11) 273 ])] 274) 275 276;; movhi 277 278(define_expand "movhi" 279 [(set (match_operand:HI 0 "nonimmediate_operand") 280 (match_operand:HI 1 "general_operand"))] 281 "" 282{ 283 /* One of the ops has to be in a register. */ 284 if (!register_operand (operand1, HImode) 285 && !register_operand (operand0, HImode)) 286 operands[1] = force_reg (HImode, operand1); 287}) 288 289(define_insn "*movhi_internal" 290 [(set (match_operand:HI 0 "nonimmediate_operand" "=*r,D*r,D*r,D,m,*z,d") 291 (match_operand:HI 1 "general_operand" " 0, i,D*r,m,D,d,*z"))] 292 "(register_operand (operands[0], HImode) 293 || register_operand (operands[1], HImode))" 294{ 295 switch (which_alternative) 296 { 297 case 0: 298 return ""; 299 case 1: 300 /* Note that "MOV imm8,An" is already zero-extending, and is 2 bytes. 301 We have "MOV imm16,Dn" at 3 bytes. The only win for the 4 byte 302 movu is for an 8-bit unsigned move into Rn. */ 303 if (TARGET_AM33 304 && CONST_INT_P (operands[1]) 305 && IN_RANGE (INTVAL (operands[1]), 0x80, 0xff) 306 && REGNO_EXTENDED_P (REGNO (operands[0]), 1)) 307 return "movu %1,%0"; 308 /* FALLTHRU */ 309 case 5: 310 case 6: 311 case 2: 312 return "mov %1,%0"; 313 case 3: 314 case 4: 315 return "movhu %1,%0"; 316 default: 317 gcc_unreachable (); 318 } 319} 320 [(set_attr_alternative "timings" 321 [(const_int 11) 322 (const_int 11) 323 (if_then_else (eq_attr "cpu" "am34") 324 (const_int 11) (const_int 22)) 325 (if_then_else (eq_attr "cpu" "am34") 326 (const_int 13) (const_int 24)) 327 (if_then_else (eq_attr "cpu" "am34") 328 (const_int 11) (const_int 22)) 329 (if_then_else (eq_attr "cpu" "am34") 330 (const_int 11) (const_int 22)) 331 (if_then_else (eq_attr "cpu" "am34") 332 (const_int 11) (const_int 22)) 333 ])] 334) 335 336;; movsi and helpers 337 338;; We use this to handle addition of two values when one operand is the 339;; stack pointer and the other is a memory reference of some kind. Reload 340;; does not handle them correctly without this expander. 341(define_expand "reload_plus_sp_const" 342 [(set (match_operand:SI 0 "register_operand" "=r") 343 (match_operand:SI 1 "impossible_plus_operand" "")) 344 (clobber (match_operand:SI 2 "register_operand" "=&A"))] 345 "" 346{ 347 rtx dest, scratch, other; 348 349 dest = operands[0]; 350 scratch = operands[2]; 351 352 other = XEXP (operands[1], 1); 353 if (other == stack_pointer_rtx) 354 other = XEXP (operands[1], 0); 355 356 if (true_regnum (other) == true_regnum (dest)) 357 { 358 gcc_assert (true_regnum (scratch) != true_regnum (dest)); 359 emit_move_insn (scratch, stack_pointer_rtx); 360 emit_insn (gen_addsi3 (dest, dest, scratch)); 361 } 362 else if (TARGET_AM33 || REGNO_REG_CLASS (true_regnum (dest)) == ADDRESS_REGS) 363 { 364 emit_move_insn (dest, stack_pointer_rtx); 365 if (other == stack_pointer_rtx) 366 emit_insn (gen_addsi3 (dest, dest, dest)); 367 else if (other != const0_rtx) 368 emit_insn (gen_addsi3 (dest, dest, other)); 369 } 370 else 371 { 372 emit_move_insn (scratch, stack_pointer_rtx); 373 if (other == stack_pointer_rtx) 374 { 375 emit_move_insn (dest, scratch); 376 emit_insn (gen_addsi3 (dest, dest, dest)); 377 } 378 else if (other != const0_rtx) 379 { 380 emit_move_insn (dest, other); 381 emit_insn (gen_addsi3 (dest, dest, scratch)); 382 } 383 else 384 emit_move_insn (dest, scratch); 385 } 386 DONE; 387}) 388 389(define_expand "movsi" 390 [(set (match_operand:SI 0 "nonimmediate_operand") 391 (match_operand:SI 1 "general_operand"))] 392 "" 393{ 394 /* One of the ops has to be in a register. */ 395 if (!register_operand (operand1, SImode) 396 && !register_operand (operand0, SImode)) 397 operands[1] = force_reg (SImode, operand1); 398 if (flag_pic) 399 { 400 rtx temp; 401 if (SYMBOLIC_CONST_P (operands[1])) 402 { 403 if (MEM_P (operands[0])) 404 operands[1] = force_reg (Pmode, operands[1]); 405 else 406 { 407 temp = (!can_create_pseudo_p () 408 ? operands[0] 409 : gen_reg_rtx (Pmode)); 410 operands[1] = mn10300_legitimize_pic_address (operands[1], temp); 411 } 412 } 413 else if (GET_CODE (operands[1]) == CONST 414 && GET_CODE (XEXP (operands[1], 0)) == PLUS 415 && SYMBOLIC_CONST_P (XEXP (XEXP (operands[1], 0), 0))) 416 { 417 temp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (Pmode); 418 temp = mn10300_legitimize_pic_address (XEXP (XEXP (operands[1], 0), 0), 419 temp); 420 operands[1] = expand_binop (SImode, add_optab, temp, 421 XEXP (XEXP (operands[1], 0), 1), 422 (!can_create_pseudo_p () 423 ? temp 424 : gen_reg_rtx (Pmode)), 425 0, OPTAB_LIB_WIDEN); 426 } 427 } 428}) 429 430(define_insn "*movsi_internal" 431 [(set (match_operand:SI 0 "nonimmediate_operand" 432 "=r,r,r,r,m,r, A,*y,*y,*z,*d") 433 (match_operand:SI 1 "general_operand" 434 " 0,O,i,r,r,m,*y, A, i,*d,*z"))] 435 "register_operand (operands[0], SImode) 436 || register_operand (operands[1], SImode)" 437{ 438 switch (which_alternative) 439 { 440 case 0: 441 return ""; 442 case 1: /* imm-reg. */ 443 case 2: 444 /* See movhi for a discussion of sizes for 8-bit movu. Note that the 445 24-bit movu is 6 bytes, which is the same size as the full 32-bit 446 mov form for An and Dn. So again movu is only a win for Rn. */ 447 if (TARGET_AM33 448 && CONST_INT_P (operands[1]) 449 && REGNO_EXTENDED_P (REGNO (operands[0]), 1)) 450 { 451 HOST_WIDE_INT val = INTVAL (operands[1]); 452 if (IN_RANGE (val, 0x80, 0xff) 453 || IN_RANGE (val, 0x800000, 0xffffff)) 454 return "movu %1,%0"; 455 } 456 /* FALLTHRU */ 457 case 3: /* reg-reg */ 458 case 4: /* reg-mem */ 459 case 5: /* mem-reg */ 460 case 6: /* sp-reg */ 461 case 7: /* reg-sp */ 462 case 8: /* imm-sp */ 463 case 9: /* reg-mdr */ 464 case 10: /* mdr-reg */ 465 return "mov %1,%0"; 466 default: 467 gcc_unreachable (); 468 } 469} 470 [(set_attr "isa" "*,*,*,*,*,*,*,*,am33,*,*") 471 (set_attr "liw" "*,either,*,either,*,*,*,*,*,*,*") 472 (set_attr "liw_op" "mov") 473 (set_attr_alternative "timings" 474 [(const_int 11) 475 (const_int 22) 476 (const_int 22) 477 (const_int 11) 478 (if_then_else (eq_attr "cpu" "am34") 479 (const_int 11) (const_int 22)) 480 (if_then_else (eq_attr "cpu" "am34") 481 (const_int 13) (const_int 24)) 482 (if_then_else (eq_attr "cpu" "am34") 483 (const_int 11) (const_int 22)) 484 (if_then_else (eq_attr "cpu" "am34") 485 (const_int 13) (const_int 24)) 486 (const_int 11) 487 (const_int 11) 488 (const_int 11) 489 ])] 490) 491 492(define_expand "movsf" 493 [(set (match_operand:SF 0 "nonimmediate_operand") 494 (match_operand:SF 1 "general_operand"))] 495 "TARGET_AM33_2" 496{ 497 /* One of the ops has to be in a register. */ 498 if (!register_operand (operand1, SFmode) 499 && !register_operand (operand0, SFmode)) 500 operands[1] = force_reg (SFmode, operand1); 501}) 502 503(define_insn "*movsf_internal" 504 [(set (match_operand:SF 0 "nonimmediate_operand" "=rf,r,f,r,f,r,f,r,m,f,Q,z,d") 505 (match_operand:SF 1 "general_operand" " 0,F,F,r,f,f,r,m,r,Q,f,d,z"))] 506 "TARGET_AM33_2 507 && (register_operand (operands[0], SFmode) 508 || register_operand (operands[1], SFmode))" 509{ 510 switch (which_alternative) 511 { 512 case 0: 513 return ""; 514 case 1: 515 case 3: 516 case 7: 517 case 8: 518 case 11: 519 case 12: 520 return "mov %1,%0"; 521 case 2: 522 case 4: 523 case 5: 524 case 6: 525 case 9: 526 case 10: 527 return "fmov %1,%0"; 528 default: 529 gcc_unreachable (); 530 } 531} 532 [(set_attr_alternative "timings" 533 [(const_int 11) 534 (const_int 22) 535 (if_then_else (eq_attr "cpu" "am34") 536 (const_int 47) (const_int 25)) 537 (const_int 11) 538 (if_then_else (eq_attr "cpu" "am34") 539 (const_int 13) (const_int 14)) 540 (if_then_else (eq_attr "cpu" "am34") 541 (const_int 13) (const_int 12)) 542 (if_then_else (eq_attr "cpu" "am34") 543 (const_int 13) (const_int 14)) 544 (if_then_else (eq_attr "cpu" "am34") 545 (const_int 13) (const_int 24)) 546 (if_then_else (eq_attr "cpu" "am34") 547 (const_int 13) (const_int 24)) 548 (if_then_else (eq_attr "cpu" "am34") 549 (const_int 13) (const_int 24)) 550 (if_then_else (eq_attr "cpu" "am34") 551 (const_int 13) (const_int 24)) 552 (const_int 22) 553 (const_int 22) 554 ])] 555) 556 557;; If the flags register is not live, generate CLR instead of MOV 0. 558;; For MN103, this is only legal for DATA_REGS; for AM33 this is legal 559;; but not a win for ADDRESS_REGS. 560(define_peephole2 561 [(set (match_operand:INT 0 "register_operand" "") (const_int 0))] 562 "peep2_regno_dead_p (0, CC_REG) 563 && (REGNO_DATA_P (REGNO (operands[0]), 1) 564 || REGNO_EXTENDED_P (REGNO (operands[0]), 1))" 565 [(parallel [(set (match_dup 0) (const_int 0)) 566 (clobber (reg:CC CC_REG))])] 567) 568 569(define_insn "*mov<mode>_clr" 570 [(set (match_operand:INT 0 "register_operand" "=D") 571 (const_int 0)) 572 (clobber (reg:CC CC_REG))] 573 "" 574 "clr %0" 575) 576 577;; ---------------------------------------------------------------------- 578;; ADD INSTRUCTIONS 579;; ---------------------------------------------------------------------- 580 581(define_insn "addsi3" 582 [(set (match_operand:SI 0 "register_operand" "=r,r,r,!*y,!r") 583 (plus:SI (match_operand:SI 1 "register_operand" "%0,0,0, 0, r") 584 (match_operand:SI 2 "nonmemory_operand" "r,O,i, i, r"))) 585 (clobber (reg:CC CC_REG))] 586 "" 587 { return mn10300_output_add (operands, false); } 588 [(set_attr "timings" "11,11,11,11,22") 589 (set_attr "liw" "either,either,*,*,*") 590 (set_attr "liw_op" "add")] 591) 592 593;; Note that ADD IMM,SP does not set the flags, so omit that here. 594(define_insn "*addsi3_flags" 595 [(set (reg CC_REG) 596 (compare (plus:SI (match_operand:SI 1 "register_operand" "%0, r") 597 (match_operand:SI 2 "nonmemory_operand" "ri, r")) 598 (const_int 0))) 599 (set (match_operand:SI 0 "register_operand" "=r,!r") 600 (plus:SI (match_dup 1) (match_dup 2)))] 601 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)" 602 { return mn10300_output_add (operands, true); } 603 [(set_attr "timings" "11,22")] 604) 605 606;; A helper to expand the above, with the CC_MODE filled in. 607(define_expand "addsi3_flags" 608 [(parallel [(set (reg:CCZNC CC_REG) 609 (compare:CCZNC (plus:SI (match_dup 1) (match_dup 2)) 610 (const_int 0))) 611 (set (match_operand:SI 0 "register_operand") 612 (plus:SI (match_operand:SI 1 "register_operand") 613 (match_operand:SI 2 "nonmemory_operand")))])] 614 "" 615) 616 617(define_insn "addc_internal" 618 [(set (match_operand:SI 0 "register_operand" "=D,r,r") 619 (plus:SI 620 (plus:SI 621 (ltu:SI (reg:CC CC_REG) (const_int 0)) 622 (match_operand:SI 1 "register_operand" "%0,0,r")) 623 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r"))) 624 (clobber (reg:CC CC_REG))] 625 "reload_completed" 626 "@ 627 addc %2,%0 628 addc %2,%0 629 addc %2,%1,%0" 630 [(set_attr "isa" "*,am33,am33")] 631) 632 633(define_expand "adddi3" 634 [(set (match_operand:DI 0 "register_operand" "") 635 (plus:DI (match_operand:DI 1 "register_operand" "") 636 (match_operand:DI 2 "nonmemory_operand" "")))] 637 "" 638{ 639 rtx op0l, op0h, op1l, op1h, op2l, op2h; 640 641 op0l = gen_lowpart (SImode, operands[0]); 642 op1l = gen_lowpart (SImode, operands[1]); 643 op2l = gen_lowpart (SImode, operands[2]); 644 op0h = gen_highpart (SImode, operands[0]); 645 op1h = gen_highpart (SImode, operands[1]); 646 op2h = gen_highpart_mode (SImode, DImode, operands[2]); 647 648 if (!reg_or_am33_const_operand (op2h, SImode)) 649 op2h = force_reg (SImode, op2h); 650 651 emit_insn (gen_adddi3_internal (op0l, op0h, op1l, op2l, op1h, op2h)); 652 DONE; 653}) 654 655;; Note that reload only supports one commutative operand. Thus we cannot 656;; auto-swap both the high and low outputs with their matching constraints. 657;; For MN103, we're strapped for registers but thankfully the alternatives 658;; are few. For AM33, it becomes much easier to not represent the early 659;; clobber and 6 permutations of immediate and three-operand adds, but 660;; instead allocate a scratch register and do the expansion by hand. 661 662(define_insn_and_split "adddi3_internal" 663 [(set (match_operand:SI 0 "register_operand" "=r, r, r") 664 (plus:SI (match_operand:SI 2 "register_operand" "%0, 0, r") 665 (match_operand:SI 3 "nonmemory_operand" "ri,ri,ri"))) 666 (set (match_operand:SI 1 "register_operand" "=D, D, r") 667 (plus:SI 668 (plus:SI 669 (ltu:SI (plus:SI (match_dup 2) (match_dup 3)) (match_dup 2)) 670 (match_operand:SI 4 "register_operand" " 1, D, r")) 671 (match_operand:SI 5 "reg_or_am33_const_operand" " D, 1,ri"))) 672 (clobber (match_scratch:SI 6 "=X, X,&r")) 673 (clobber (reg:CC CC_REG))] 674 "" 675 "#" 676 "reload_completed" 677 [(const_int 0)] 678{ 679 rtx op0l = operands[0]; 680 rtx op0h = operands[1]; 681 rtx op1l = operands[2]; 682 rtx op2l = operands[3]; 683 rtx op1h = operands[4]; 684 rtx op2h = operands[5]; 685 rtx scratch = operands[6]; 686 rtx x; 687 688 if (reg_overlap_mentioned_p (op0l, op1h)) 689 { 690 emit_move_insn (scratch, op0l); 691 op1h = scratch; 692 if (reg_overlap_mentioned_p (op0l, op2h)) 693 op2h = scratch; 694 } 695 else if (reg_overlap_mentioned_p (op0l, op2h)) 696 { 697 emit_move_insn (scratch, op0l); 698 op2h = scratch; 699 } 700 701 if (rtx_equal_p (op0l, op1l)) 702 ; 703 else if (rtx_equal_p (op0l, op2l)) 704 x = op1l, op1l = op2l, op2l = x; 705 else 706 { 707 gcc_assert (TARGET_AM33); 708 if (!REG_P (op2l)) 709 { 710 emit_move_insn (op0l, op2l); 711 op2l = op1l; 712 op1l = op0l; 713 } 714 } 715 emit_insn (gen_addsi3_flags (op0l, op1l, op2l)); 716 717 if (rtx_equal_p (op0h, op1h)) 718 ; 719 else if (rtx_equal_p (op0h, op2h)) 720 x = op1h, op1h = op2h, op2h = x; 721 else 722 { 723 gcc_assert (TARGET_AM33); 724 if (!REG_P (op2h)) 725 { 726 emit_move_insn (op0h, op2h); 727 op2h = op1h; 728 op1h = op0h; 729 } 730 } 731 emit_insn (gen_addc_internal (op0h, op1h, op2h)); 732 DONE; 733} 734 [(set_attr "isa" "*,*,am33")] 735) 736 737;; The following pattern is generated by combine when it proves that one 738;; of the inputs to the low-part of the double-word add is zero, and thus 739;; no carry is generated into the high-part. 740 741(define_insn_and_split "*adddi3_degenerate" 742 [(set (match_operand:SI 0 "register_operand" "=&r,&r") 743 (match_operand:SI 2 "nonmemory_operand" " 0, 0")) 744 (set (match_operand:SI 1 "register_operand" "=r , r") 745 (plus:SI (match_operand:SI 3 "register_operand" "%1 , r") 746 (match_operand:SI 4 "nonmemory_operand" "ri, r"))) 747 (clobber (reg:CC CC_REG))] 748 "" 749 "#" 750 "" 751 [(const_int 0)] 752{ 753 rtx scratch = NULL_RTX; 754 if (!rtx_equal_p (operands[0], operands[2])) 755 { 756 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])); 757 if (reg_overlap_mentioned_p (operands[0], operands[3]) 758 || reg_overlap_mentioned_p (operands[0], operands[4])) 759 { 760 scratch = gen_reg_rtx (SImode); 761 emit_move_insn (scratch, operands[2]); 762 } 763 else 764 emit_move_insn (operands[0], operands[2]); 765 } 766 emit_insn (gen_addsi3 (operands[1], operands[3], operands[4])); 767 if (scratch) 768 emit_move_insn (operands[0], scratch); 769 DONE; 770}) 771 772;; ---------------------------------------------------------------------- 773;; SUBTRACT INSTRUCTIONS 774;; ---------------------------------------------------------------------- 775 776(define_insn "subsi3" 777 [(set (match_operand:SI 0 "register_operand" "=r,r,r,r") 778 (minus:SI (match_operand:SI 1 "register_operand" "0,0,0,r") 779 (match_operand:SI 2 "nonmemory_operand" "r,O,i,r"))) 780 (clobber (reg:CC CC_REG))] 781 "" 782 "@ 783 sub %2,%0 784 sub %2,%0 785 sub %2,%0 786 sub %2,%1,%0" 787 [(set_attr "isa" "*,*,*,am33") 788 (set_attr "liw" "either,either,*,*") 789 (set_attr "liw_op" "sub") 790 (set_attr "timings" "11,11,11,22")] 791) 792 793(define_insn "*subsi3_flags" 794 [(set (reg CC_REG) 795 (compare (minus:SI (match_operand:SI 1 "register_operand" "0, r") 796 (match_operand:SI 2 "nonmemory_operand" "ri,r")) 797 (const_int 0))) 798 (set (match_operand:SI 0 "register_operand" "=r, r") 799 (minus:SI (match_dup 1) (match_dup 2)))] 800 "reload_completed && mn10300_match_ccmode (insn, CCZNCmode)" 801 "@ 802 sub %2,%0 803 sub %2,%1,%0" 804 [(set_attr "isa" "*,am33") 805 (set_attr "timings" "11,22")] 806) 807 808;; A helper to expand the above, with the CC_MODE filled in. 809(define_expand "subsi3_flags" 810 [(parallel [(set (reg:CCZNC CC_REG) 811 (compare:CCZNC (minus:SI (match_dup 1) (match_dup 2)) 812 (const_int 0))) 813 (set (match_operand:SI 0 "register_operand") 814 (minus:SI (match_operand:SI 1 "register_operand") 815 (match_operand:SI 2 "nonmemory_operand")))])] 816 "" 817) 818 819(define_insn "subc_internal" 820 [(set (match_operand:SI 0 "register_operand" "=D,r,r") 821 (minus:SI 822 (minus:SI (match_operand:SI 1 "register_operand" " 0,0,r") 823 (match_operand:SI 2 "reg_or_am33_const_operand" " D,i,r")) 824 (geu:SI (reg:CC CC_REG) (const_int 0)))) 825 (clobber (reg:CC CC_REG))] 826 "reload_completed" 827 "@ 828 subc %2,%0 829 subc %2,%0 830 subc %2,%1,%0" 831 [(set_attr "isa" "*,am33,am33")] 832) 833 834(define_expand "subdi3" 835 [(set (match_operand:DI 0 "register_operand" "") 836 (minus:DI (match_operand:DI 1 "register_operand" "") 837 (match_operand:DI 2 "nonmemory_operand" "")))] 838 "" 839{ 840 rtx op0l, op0h, op1l, op1h, op2l, op2h; 841 842 op0l = gen_lowpart (SImode, operands[0]); 843 op1l = gen_lowpart (SImode, operands[1]); 844 op2l = gen_lowpart (SImode, operands[2]); 845 op0h = gen_highpart (SImode, operands[0]); 846 op1h = gen_highpart (SImode, operands[1]); 847 op2h = gen_highpart_mode (SImode, DImode, operands[2]); 848 849 if (!reg_or_am33_const_operand (op2h, SImode)) 850 op2h = force_reg (SImode, op2h); 851 852 emit_insn (gen_subdi3_internal (op0l, op0h, op1l, op1h, op2l, op2h)); 853 DONE; 854}) 855 856;; As with adddi3, the use of the scratch register helps reduce the 857;; number of permutations for AM33. 858;; ??? The early clobber on op0 avoids a reload bug wherein both output 859;; registers are set the same. Consider negate, where both op2 and op3 860;; are 0, are csed to the same input register, and reload fails to undo 861;; the cse when satisfying the matching constraints. 862 863(define_insn_and_split "subdi3_internal" 864 [(set (match_operand:SI 0 "register_operand" "=&r, r") 865 (minus:SI 866 (match_operand:SI 2 "register_operand" " 0, r") 867 (match_operand:SI 4 "nonmemory_operand" " ri,ri"))) 868 (set (match_operand:SI 1 "register_operand" "=D , r") 869 (minus:SI 870 (minus:SI 871 (match_operand:SI 3 "register_operand" " 1, r") 872 (match_operand:SI 5 "reg_or_am33_const_operand" " D,ri")) 873 (ltu:SI (match_dup 2) (match_dup 4)))) 874 (clobber (match_scratch:SI 6 "=X ,&r")) 875 (clobber (reg:CC CC_REG))] 876 "" 877 "#" 878 "reload_completed" 879 [(const_int 0)] 880{ 881 rtx op0l = operands[0]; 882 rtx op0h = operands[1]; 883 rtx op1l = operands[2]; 884 rtx op1h = operands[3]; 885 rtx op2l = operands[4]; 886 rtx op2h = operands[5]; 887 rtx scratch = operands[6]; 888 889 if (reg_overlap_mentioned_p (op0l, op1h)) 890 { 891 emit_move_insn (scratch, op0l); 892 op1h = scratch; 893 if (reg_overlap_mentioned_p (op0l, op2h)) 894 op2h = scratch; 895 } 896 else if (reg_overlap_mentioned_p (op0l, op2h)) 897 { 898 emit_move_insn (scratch, op0l); 899 op2h = scratch; 900 } 901 902 if (!rtx_equal_p (op0l, op1l)) 903 { 904 gcc_assert (TARGET_AM33); 905 if (!REG_P (op2l)) 906 { 907 emit_move_insn (op0l, op1l); 908 op1l = op0l; 909 } 910 } 911 emit_insn (gen_subsi3_flags (op0l, op1l, op2l)); 912 913 if (!rtx_equal_p (op0h, op1h)) 914 { 915 gcc_assert (TARGET_AM33); 916 if (!REG_P (op2h)) 917 { 918 emit_move_insn (op0h, op1h); 919 op1h = op0h; 920 } 921 } 922 emit_insn (gen_subc_internal (op0h, op1h, op2h)); 923 DONE; 924} 925 [(set_attr "isa" "*,am33")] 926) 927 928;; The following pattern is generated by combine when it proves that one 929;; of the inputs to the low-part of the double-word sub is zero, and thus 930;; no carry is generated into the high-part. 931 932(define_insn_and_split "*subdi3_degenerate" 933 [(set (match_operand:SI 0 "register_operand" "=&r,&r") 934 (match_operand:SI 2 "nonmemory_operand" " 0, 0")) 935 (set (match_operand:SI 1 "register_operand" "=r , r") 936 (minus:SI (match_operand:SI 3 "register_operand" " 1, r") 937 (match_operand:SI 4 "nonmemory_operand" " ri, r"))) 938 (clobber (reg:CC CC_REG))] 939 "" 940 "#" 941 "" 942 [(const_int 0)] 943{ 944 rtx scratch = NULL_RTX; 945 if (!rtx_equal_p (operands[0], operands[2])) 946 { 947 gcc_assert (!reg_overlap_mentioned_p (operands[0], operands[1])); 948 if (reg_overlap_mentioned_p (operands[0], operands[3]) 949 || reg_overlap_mentioned_p (operands[0], operands[4])) 950 { 951 scratch = gen_reg_rtx (SImode); 952 emit_move_insn (scratch, operands[2]); 953 } 954 else 955 emit_move_insn (operands[0], operands[2]); 956 } 957 emit_insn (gen_subsi3 (operands[1], operands[3], operands[4])); 958 if (scratch) 959 emit_move_insn (operands[0], scratch); 960 DONE; 961}) 962 963(define_insn_and_split "negsi2" 964 [(set (match_operand:SI 0 "register_operand" "=D,&r") 965 (neg:SI (match_operand:SI 1 "register_operand" " 0, r"))) 966 (clobber (reg:CC CC_REG))] 967 "" 968 "#" 969 "&& reload_completed" 970 [(const_int 0)] 971{ 972 /* Recall that twos-compliment is ones-compliment plus one. When 973 allocated in DATA_REGS this is 2+1 bytes; otherwise (for am33) 974 this is 3+3 bytes. 975 976 For AM33, it would have been possible to load zero and use the 977 three-address subtract to have a total size of 3+4*N bytes for 978 multiple negations, plus increased throughput. Not attempted here. */ 979 980 if (true_regnum (operands[0]) == true_regnum (operands[1])) 981 { 982 emit_insn (gen_one_cmplsi2 (operands[0], operands[0])); 983 emit_insn (gen_addsi3 (operands[0], operands[0], const1_rtx)); 984 } 985 else 986 { 987 emit_move_insn (operands[0], const0_rtx); 988 emit_insn (gen_subsi3 (operands[0], operands[0], operands[1])); 989 } 990 DONE; 991}) 992 993;; ---------------------------------------------------------------------- 994;; MULTIPLY INSTRUCTIONS 995;; ---------------------------------------------------------------------- 996 997;; ??? Note that AM33 has a third multiply variant that puts the high part 998;; into the MDRQ register, however this variant also constrains the inputs 999;; to be in DATA_REGS and thus isn't as helpful as it might be considering 1000;; the existence of the 4-operand multiply. Nor is there a set of divide 1001;; insns that use MDRQ. Given that there is an IMM->MDRQ insn, this would 1002;; have been very handy for starting udivmodsi4... 1003 1004(define_expand "mulsidi3" 1005 [(set (match_operand:DI 0 "register_operand" "") 1006 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) 1007 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))] 1008 "" 1009{ 1010 emit_insn (gen_mulsidi3_internal (gen_lowpart (SImode, operands[0]), 1011 gen_highpart (SImode, operands[0]), 1012 operands[1], operands[2])); 1013 DONE; 1014}) 1015 1016(define_insn "mulsidi3_internal" 1017 [(set (match_operand:SI 0 "register_operand" "=D,r") 1018 (mult:SI (match_operand:SI 2 "register_operand" "%0,r") 1019 (match_operand:SI 3 "register_operand" " D,r"))) 1020 (set (match_operand:SI 1 "register_operand" "=z,r") 1021 (truncate:SI 1022 (ashiftrt:DI 1023 (mult:DI (sign_extend:DI (match_dup 2)) 1024 (sign_extend:DI (match_dup 3))) 1025 (const_int 32)))) 1026 (clobber (reg:CC CC_REG))] 1027 "" 1028{ 1029 if (which_alternative == 1) 1030 return "mul %2,%3,%1,%0"; 1031 else if (TARGET_MULT_BUG) 1032 return "nop\;nop\;mul %3,%0"; 1033 else 1034 return "mul %3,%0"; 1035} 1036 [(set_attr "isa" "*,am33") 1037 (set (attr "timings") 1038 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] 1039) 1040 1041(define_expand "umulsidi3" 1042 [(set (match_operand:DI 0 "register_operand" "") 1043 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) 1044 (zero_extend:DI (match_operand:SI 2 "register_operand" "")))) 1045 (clobber (reg:CC CC_REG))] 1046 "" 1047{ 1048 emit_insn (gen_umulsidi3_internal (gen_lowpart (SImode, operands[0]), 1049 gen_highpart (SImode, operands[0]), 1050 operands[1], operands[2])); 1051 DONE; 1052}) 1053 1054(define_insn "umulsidi3_internal" 1055 [(set (match_operand:SI 0 "register_operand" "=D,r") 1056 (mult:SI (match_operand:SI 2 "register_operand" "%0,r") 1057 (match_operand:SI 3 "register_operand" " D,r"))) 1058 (set (match_operand:SI 1 "register_operand" "=z,r") 1059 (truncate:SI 1060 (lshiftrt:DI 1061 (mult:DI (zero_extend:DI (match_dup 2)) 1062 (zero_extend:DI (match_dup 3))) 1063 (const_int 32)))) 1064 (clobber (reg:CC CC_REG))] 1065 "" 1066{ 1067 if (which_alternative == 1) 1068 return "mulu %2,%3,%1,%0"; 1069 else if (TARGET_MULT_BUG) 1070 return "nop\;nop\;mulu %3,%0"; 1071 else 1072 return "mulu %3,%0"; 1073} 1074 [(set_attr "isa" "*,am33") 1075 (set (attr "timings") 1076 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] 1077) 1078 1079(define_expand "mulsi3" 1080 [(parallel [(set (match_operand:SI 0 "register_operand") 1081 (mult:SI (match_operand:SI 1 "register_operand") 1082 (match_operand:SI 2 "reg_or_am33_const_operand"))) 1083 (clobber (match_scratch:SI 3)) 1084 (clobber (reg:CC CC_REG))])] 1085 "" 1086) 1087 1088(define_insn "*mulsi3" 1089 [(set (match_operand:SI 0 "register_operand" "=D, r,r") 1090 (mult:SI (match_operand:SI 2 "register_operand" "%0, 0,r") 1091 (match_operand:SI 3 "reg_or_am33_const_operand" " D,ri,r"))) 1092 (clobber (match_scratch:SI 1 "=z, z,r")) 1093 (clobber (reg:CC CC_REG))] 1094 "" 1095{ 1096 if (which_alternative == 2) 1097 return "mul %2,%3,%1,%0"; 1098 else if (TARGET_MULT_BUG) 1099 return "nop\;nop\;mul %3,%0"; 1100 else 1101 return "mul %3,%0"; 1102} 1103 [(set_attr "isa" "*,am33,am33") 1104 (set (attr "timings") 1105 (if_then_else (eq_attr "cpu" "am34") (const_int 24) (const_int 23)))] 1106) 1107 1108(define_expand "udivmodsi4" 1109 [(parallel [(set (match_operand:SI 0 "register_operand") 1110 (udiv:SI (match_operand:SI 1 "register_operand") 1111 (match_operand:SI 2 "register_operand"))) 1112 (set (match_operand:SI 3 "register_operand") 1113 (umod:SI (match_dup 1) (match_dup 2))) 1114 (use (const_int 0)) 1115 (clobber (reg:CC CC_REG))])] 1116 "" 1117) 1118 1119;; Note the trick to get reload to put the zero into the MDR register, 1120;; rather than exposing the load early and letting CSE or someone try 1121;; to share the zeros between division insns. Which tends to result 1122;; in sequences like 0->r0->d0->mdr. 1123 1124(define_insn "*udivmodsi4" 1125 [(set (match_operand:SI 0 "register_operand" "=D") 1126 (udiv:SI (match_operand:SI 2 "register_operand" " 0") 1127 (match_operand:SI 3 "register_operand" " D"))) 1128 (set (match_operand:SI 1 "register_operand" "=z") 1129 (umod:SI (match_dup 2) (match_dup 3))) 1130 (use (match_operand:SI 4 "nonmemory_operand" " 1")) 1131 (clobber (reg:CC CC_REG))] 1132 "" 1133 "divu %3,%0" 1134 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1135 (const_int 3839) (const_int 4243)))] 1136) 1137 1138(define_expand "divmodsi4" 1139 [(parallel [(set (match_operand:SI 0 "register_operand" "") 1140 (div:SI (match_operand:SI 1 "register_operand" "") 1141 (match_operand:SI 2 "register_operand" ""))) 1142 (set (match_operand:SI 3 "register_operand" "") 1143 (mod:SI (match_dup 1) (match_dup 2))) 1144 (use (match_dup 4)) 1145 (clobber (reg:CC CC_REG))])] 1146 "" 1147{ 1148 operands[4] = gen_reg_rtx (SImode); 1149 emit_insn (gen_ext_internal (operands[4], operands[1])); 1150}) 1151 1152;; ??? Ideally we'd represent this via shift, but it seems like adding a 1153;; special-case pattern for (ashiftrt x 31) is just as likely to result 1154;; in poor register allocation choices. 1155(define_insn "ext_internal" 1156 [(set (match_operand:SI 0 "register_operand" "=z") 1157 (unspec:SI [(match_operand:SI 1 "register_operand" "D")] UNSPEC_EXT))] 1158 "" 1159 "ext %1" 1160) 1161 1162(define_insn "*divmodsi4" 1163 [(set (match_operand:SI 0 "register_operand" "=D") 1164 (div:SI (match_operand:SI 2 "register_operand" " 0") 1165 (match_operand:SI 3 "register_operand" " D"))) 1166 (set (match_operand:SI 1 "register_operand" "=z") 1167 (mod:SI (match_dup 2) (match_dup 3))) 1168 (use (match_operand:SI 4 "register_operand" " 1")) 1169 (clobber (reg:CC CC_REG))] 1170 "" 1171 "div %3,%0"; 1172 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1173 (const_int 3839) (const_int 4243)))] 1174) 1175 1176 1177;; ---------------------------------------------------------------------- 1178;; AND INSTRUCTIONS 1179;; ---------------------------------------------------------------------- 1180 1181(define_insn "andsi3" 1182 [(set (match_operand:SI 0 "register_operand" "=D,D,r") 1183 (and:SI (match_operand:SI 1 "register_operand" "%0,0,r") 1184 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) 1185 (clobber (reg:CC CC_REG))] 1186 "" 1187 "@ 1188 and %2,%0 1189 and %2,%0 1190 and %2,%1,%0" 1191 [(set_attr "isa" "*,*,am33") 1192 (set_attr "liw" "*,op1,*") 1193 (set_attr "liw_op" "and") 1194 (set_attr "timings" "22,11,11")] 1195) 1196 1197(define_insn "*andsi3_flags" 1198 [(set (reg CC_REG) 1199 (compare (and:SI (match_operand:SI 1 "register_operand" "%0,0,r") 1200 (match_operand:SI 2 "nonmemory_operand" " i,D,r")) 1201 (const_int 0))) 1202 (set (match_operand:SI 0 "register_operand" "=D,D,r") 1203 (and:SI (match_dup 1) (match_dup 2)))] 1204 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" 1205 "@ 1206 and %2,%0 1207 and %2,%0 1208 and %2,%1,%0" 1209 [(set_attr "isa" "*,*,am33") 1210 (set_attr "timings" "22,11,11")] 1211) 1212 1213;; Make sure we generate extensions instead of ANDs. 1214 1215(define_split 1216 [(parallel [(set (match_operand:SI 0 "register_operand" "") 1217 (and:SI (match_operand:SI 1 "register_operand" "") 1218 (const_int 255))) 1219 (clobber (reg:CC CC_REG))])] 1220 "" 1221 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))] 1222 { operands[1] = gen_lowpart (QImode, operands[1]); } 1223) 1224 1225(define_split 1226 [(parallel [(set (match_operand:SI 0 "register_operand" "") 1227 (and:SI (match_operand:SI 1 "register_operand" "") 1228 (const_int 65535))) 1229 (clobber (reg:CC CC_REG))])] 1230 "" 1231 [(set (match_dup 0) (zero_extend:SI (match_dup 1)))] 1232 { operands[1] = gen_lowpart (HImode, operands[1]); } 1233) 1234 1235;; Split AND by an appropriate constant into two shifts. Recall that 1236;; operations with a full 32-bit immediate require an extra cycle, so 1237;; this is a size optimization with no speed penalty. This only applies 1238;; do DATA_REGS; the shift insns that AM33 adds are too large for a win. 1239 1240(define_split 1241 [(parallel [(set (match_operand:SI 0 "register_operand" "") 1242 (and:SI (match_dup 0) 1243 (match_operand:SI 1 "const_int_operand" ""))) 1244 (clobber (reg:CC CC_REG))])] 1245 "reload_completed 1246 && REGNO_DATA_P (true_regnum (operands[0]), 1) 1247 && mn10300_split_and_operand_count (operands[1]) != 0" 1248 [(const_int 0)] 1249{ 1250 int count = mn10300_split_and_operand_count (operands[1]); 1251 if (count > 0) 1252 { 1253 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (count))); 1254 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (count))); 1255 } 1256 else 1257 { 1258 emit_insn (gen_ashlsi3 (operands[0], operands[0], GEN_INT (-count))); 1259 emit_insn (gen_lshrsi3 (operands[0], operands[0], GEN_INT (-count))); 1260 } 1261 DONE; 1262}) 1263 1264;; ---------------------------------------------------------------------- 1265;; OR INSTRUCTIONS 1266;; ---------------------------------------------------------------------- 1267 1268(define_insn "iorsi3" 1269 [(set (match_operand:SI 0 "register_operand" "=D,D,r") 1270 (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r") 1271 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) 1272 (clobber (reg:CC CC_REG))] 1273 "" 1274 "@ 1275 or %2,%0 1276 or %2,%0 1277 or %2,%1,%0" 1278 [(set_attr "isa" "*,*,am33") 1279 (set_attr "liw" "*,op1,*") 1280 (set_attr "liw_op" "or") 1281 (set_attr "timings" "22,11,11")] 1282) 1283 1284(define_insn "*iorsi3_flags" 1285 [(set (reg CC_REG) 1286 (compare (ior:SI (match_operand:SI 1 "register_operand" "%0,0,r") 1287 (match_operand:SI 2 "nonmemory_operand" " i,D,r")) 1288 (const_int 0))) 1289 (set (match_operand:SI 0 "register_operand" "=D,D,r") 1290 (ior:SI (match_dup 1) (match_dup 2)))] 1291 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" 1292 "@ 1293 or %2,%0 1294 or %2,%0 1295 or %2,%1,%0" 1296 [(set_attr "isa" "*,*,am33") 1297 (set_attr "timings" "22,11,11")] 1298) 1299 1300;; ---------------------------------------------------------------------- 1301;; XOR INSTRUCTIONS 1302;; ---------------------------------------------------------------------- 1303 1304(define_insn "xorsi3" 1305 [(set (match_operand:SI 0 "register_operand" "=D,D,r") 1306 (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r") 1307 (match_operand:SI 2 "nonmemory_operand" " i,D,r"))) 1308 (clobber (reg:CC CC_REG))] 1309 "" 1310 "@ 1311 xor %2,%0 1312 xor %2,%0 1313 xor %2,%1,%0" 1314 [(set_attr "isa" "*,*,am33") 1315 (set_attr "liw" "*,op1,*") 1316 (set_attr "liw_op" "xor") 1317 (set_attr "timings" "22,11,11")] 1318) 1319 1320(define_insn "*xorsi3_flags" 1321 [(set (reg CC_REG) 1322 (compare (xor:SI (match_operand:SI 1 "register_operand" "%0,0,r") 1323 (match_operand:SI 2 "nonmemory_operand" " i,D,r")) 1324 (const_int 0))) 1325 (set (match_operand:SI 0 "register_operand" "=D,D,r") 1326 (xor:SI (match_dup 1) (match_dup 2)))] 1327 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" 1328 "@ 1329 xor %2,%0 1330 xor %2,%0 1331 xor %2,%1,%0" 1332 [(set_attr "isa" "*,*,am33") 1333 (set_attr "timings" "22,11,11")] 1334) 1335 1336;; ---------------------------------------------------------------------- 1337;; NOT INSTRUCTIONS 1338;; ---------------------------------------------------------------------- 1339 1340(define_insn "one_cmplsi2" 1341 [(set (match_operand:SI 0 "register_operand" "=D") 1342 (not:SI (match_operand:SI 1 "register_operand" " 0"))) 1343 (clobber (reg:CC CC_REG))] 1344 "" 1345 "not %0" 1346) 1347 1348(define_insn "*one_cmplsi2_flags" 1349 [(set (reg CC_REG) 1350 (compare (not:SI (match_operand:SI 1 "register_operand" "0")) 1351 (const_int 0))) 1352 (set (match_operand:SI 0 "register_operand" "=D") 1353 (not:SI (match_dup 1)))] 1354 "reload_completed && mn10300_match_ccmode (insn, CCZNmode)" 1355 "not %0" 1356) 1357 1358;; ---------------------------------------------------------------------- 1359;; COMPARE AND BRANCH INSTRUCTIONS 1360;; ---------------------------------------------------------------------- 1361 1362;; We expand the comparison into a single insn so that it will not be split 1363;; up by reload. 1364(define_expand "cbranchsi4" 1365 [(set (pc) 1366 (if_then_else 1367 (match_operator 0 "ordered_comparison_operator" 1368 [(match_operand:SI 1 "register_operand") 1369 (match_operand:SI 2 "nonmemory_operand")]) 1370 (label_ref (match_operand 3 "")) 1371 (pc)))] 1372 "" 1373 "" 1374) 1375 1376(define_insn_and_split "*cbranchsi4_cmp" 1377 [(set (pc) 1378 (if_then_else (match_operator 3 "ordered_comparison_operator" 1379 [(match_operand:SI 0 "register_operand" "r") 1380 (match_operand:SI 1 "nonmemory_operand" "ri")]) 1381 (match_operand 2 "label_ref_operand" "") 1382 (pc)))] 1383 "" 1384 "#" 1385 "reload_completed" 1386 [(const_int 0)] 1387{ 1388 mn10300_split_cbranch (CCmode, operands[3], operands[2]); 1389 DONE; 1390}) 1391 1392(define_insn "cmpsi" 1393 [(set (reg CC_REG) 1394 (compare (match_operand:SI 0 "register_operand" "r,r,r") 1395 (match_operand:SI 1 "nonmemory_operand" "r,O,i")))] 1396 "reload_completed" 1397{ 1398 /* The operands of CMP must be distinct registers. In the case where 1399 we've failed to optimize the comparison of a register to itself, we 1400 must use another method to set the Z flag. We can achieve this 1401 effect with a BTST 0,D0. This will not alter the contents of D0; 1402 the use of d0 is arbitrary; any data register would work. */ 1403 if (rtx_equal_p (operands[0], operands[1])) 1404 return "btst 0,d0"; 1405 else 1406 return "cmp %1,%0"; 1407} 1408 [(set_attr_alternative "timings" 1409 [(if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22)) 1410 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22)) 1411 (if_then_else (eq_attr "cpu" "am34") (const_int 11) (const_int 22))]) 1412 (set_attr "liw" "either,either,*") 1413 (set_attr "liw_op" "cmp")] 1414) 1415 1416(define_insn "*integer_conditional_branch" 1417 [(set (pc) 1418 (if_then_else (match_operator 0 "comparison_operator" 1419 [(match_operand 2 "int_mode_flags" "") 1420 (const_int 0)]) 1421 (label_ref (match_operand 1 "" "")) 1422 (pc)))] 1423 "reload_completed" 1424 "b%b0 %1" 1425) 1426 1427(define_insn_and_split "*cbranchsi4_btst" 1428 [(set (pc) 1429 (if_then_else 1430 (match_operator 3 "CCZN_comparison_operator" 1431 [(and:SI (match_operand:SI 0 "register_operand" "D") 1432 (match_operand:SI 1 "immediate_operand" "i")) 1433 (const_int 0)]) 1434 (match_operand 2 "label_ref_operand" "") 1435 (pc)))] 1436 "" 1437 "#" 1438 "reload_completed" 1439 [(const_int 0)] 1440{ 1441 mn10300_split_cbranch (CCZNmode, operands[3], operands[2]); 1442 DONE; 1443}) 1444 1445(define_insn "*btstsi" 1446 [(set (reg:CCZN CC_REG) 1447 (compare:CCZN 1448 (and:SI (match_operand:SI 0 "register_operand" "D") 1449 (match_operand:SI 1 "immediate_operand" "i")) 1450 (const_int 0)))] 1451 "reload_completed" 1452 "btst %1,%0" 1453) 1454 1455(define_expand "cbranchsf4" 1456 [(set (pc) 1457 (if_then_else 1458 (match_operator 0 "ordered_comparison_operator" 1459 [(match_operand:SF 1 "register_operand") 1460 (match_operand:SF 2 "nonmemory_operand")]) 1461 (label_ref (match_operand 3 "")) 1462 (pc)))] 1463 "TARGET_AM33_2" 1464 "" 1465) 1466 1467(define_insn_and_split "*cbranchsf4_cmp" 1468 [(set (pc) 1469 (if_then_else (match_operator 3 "ordered_comparison_operator" 1470 [(match_operand:SF 0 "register_operand" "f") 1471 (match_operand:SF 1 "nonmemory_operand" "fF")]) 1472 (match_operand 2 "label_ref_operand" "") 1473 (pc))) 1474 ] 1475 "TARGET_AM33_2" 1476 "#" 1477 "&& reload_completed" 1478 [(const_int 0)] 1479{ 1480 mn10300_split_cbranch (CC_FLOATmode, operands[3], operands[2]); 1481 DONE; 1482}) 1483 1484(define_insn "*am33_cmpsf" 1485 [(set (reg:CC_FLOAT CC_REG) 1486 (compare:CC_FLOAT (match_operand:SF 0 "register_operand" "f") 1487 (match_operand:SF 1 "nonmemory_operand" "fF")))] 1488 "TARGET_AM33_2 && reload_completed" 1489 "fcmp %1, %0" 1490 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1491 (const_int 17) (const_int 25)))] 1492) 1493 1494(define_insn "*float_conditional_branch" 1495 [(set (pc) 1496 (if_then_else (match_operator 0 "comparison_operator" 1497 [(reg:CC_FLOAT CC_REG) (const_int 0)]) 1498 (label_ref (match_operand 1 "" "")) 1499 (pc)))] 1500 "TARGET_AM33_2 && reload_completed" 1501 "fb%b0 %1" 1502 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1503 (const_int 44) (const_int 33)))] 1504) 1505 1506;; Unconditional and other jump instructions. 1507 1508(define_insn "jump" 1509 [(set (pc) 1510 (label_ref (match_operand 0 "" "")))] 1511 "" 1512 "jmp %l0" 1513 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1514 (const_int 11) (const_int 44)))] 1515) 1516 1517(define_insn "indirect_jump" 1518 [(set (pc) (match_operand:SI 0 "register_operand" "a"))] 1519 "" 1520 "jmp (%0)" 1521 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1522 (const_int 11) (const_int 33)))] 1523) 1524 1525(define_expand "builtin_setjmp_receiver" 1526 [(match_operand 0 "" "")] 1527 "flag_pic" 1528{ 1529 emit_insn (gen_load_pic ()); 1530 DONE; 1531}) 1532 1533(define_expand "casesi" 1534 [(match_operand:SI 0 "register_operand") 1535 (match_operand:SI 1 "immediate_operand") 1536 (match_operand:SI 2 "immediate_operand") 1537 (match_operand 3 "" "") (match_operand 4 "")] 1538 "" 1539{ 1540 rtx table = gen_reg_rtx (SImode); 1541 rtx index = gen_reg_rtx (SImode); 1542 rtx addr = gen_reg_rtx (Pmode); 1543 rtx test; 1544 1545 emit_move_insn (table, gen_rtx_LABEL_REF (VOIDmode, operands[3])); 1546 emit_insn (gen_addsi3 (index, operands[0], GEN_INT (- INTVAL (operands[1])))); 1547 test = gen_rtx_fmt_ee (GTU, VOIDmode, index, operands[2]); 1548 emit_jump_insn (gen_cbranchsi4 (test, index, operands[2], operands[4])); 1549 1550 emit_insn (gen_ashlsi3 (index, index, const2_rtx)); 1551 emit_move_insn (addr, gen_rtx_MEM (SImode, 1552 gen_rtx_PLUS (SImode, table, index))); 1553 if (flag_pic) 1554 emit_insn (gen_addsi3 (addr, addr, table)); 1555 1556 emit_jump_insn (gen_tablejump (addr, operands[3])); 1557 DONE; 1558}) 1559 1560(define_insn "tablejump" 1561 [(set (pc) (match_operand:SI 0 "register_operand" "a")) 1562 (use (label_ref (match_operand 1 "" "")))] 1563 "" 1564 "jmp (%0)" 1565 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1566 (const_int 11) (const_int 33)))] 1567) 1568 1569;; Call subroutine with no return value. 1570 1571(define_expand "call" 1572 [(call (match_operand:QI 0 "general_operand") 1573 (match_operand:SI 1 "general_operand"))] 1574 "" 1575{ 1576 rtx fn = XEXP (operands[0], 0); 1577 1578 if (flag_pic && GET_CODE (fn) == SYMBOL_REF) 1579 { 1580 if (MN10300_GLOBAL_P (fn)) 1581 { 1582 /* The PLT code won't run on AM30, but then, there's no 1583 shared library support for AM30 either, so we just assume 1584 the linker is going to adjust all @PLT relocs to the 1585 actual symbols. */ 1586 emit_use (pic_offset_table_rtx); 1587 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT); 1588 } 1589 else 1590 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC); 1591 } 1592 if (! call_address_operand (fn, VOIDmode)) 1593 fn = force_reg (SImode, fn); 1594 1595 XEXP (operands[0], 0) = fn; 1596}) 1597 1598(define_insn "*call_internal" 1599 [(call (mem:QI (match_operand:SI 0 "call_address_operand" "a,S")) 1600 (match_operand:SI 1 "" ""))] 1601 "" 1602 "@ 1603 calls %C0 1604 call %C0,[],0" 1605 [(set_attr_alternative "timings" 1606 [(if_then_else (eq_attr "cpu" "am34") 1607 (const_int 33) (const_int 44)) 1608 (if_then_else (eq_attr "cpu" "am34") 1609 (const_int 55) (const_int 33)) 1610 ]) 1611 ] 1612) 1613 1614;; Call subroutine, returning value in operand 0 1615;; (which must be a hard register). 1616 1617(define_expand "call_value" 1618 [(set (match_operand 0 "") 1619 (call (match_operand:QI 1 "general_operand") 1620 (match_operand:SI 2 "general_operand")))] 1621 "" 1622{ 1623 rtx fn = XEXP (operands[1], 0); 1624 1625 if (flag_pic && GET_CODE (fn) == SYMBOL_REF) 1626 { 1627 if (MN10300_GLOBAL_P (fn)) 1628 { 1629 /* The PLT code won't run on AM30, but then, there's no 1630 shared library support for AM30 either, so we just assume 1631 the linker is going to adjust all @PLT relocs to the 1632 actual symbols. */ 1633 emit_use (pic_offset_table_rtx); 1634 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PLT); 1635 } 1636 else 1637 fn = gen_rtx_UNSPEC (SImode, gen_rtvec (1, fn), UNSPEC_PIC); 1638 } 1639 if (! call_address_operand (fn, VOIDmode)) 1640 fn = force_reg (SImode, fn); 1641 1642 XEXP (operands[1], 0) = fn; 1643}) 1644 1645(define_insn "call_value_internal" 1646 [(set (match_operand 0 "" "") 1647 (call (mem:QI (match_operand:SI 1 "call_address_operand" "a,S")) 1648 (match_operand:SI 2 "" "")))] 1649 "" 1650 "@ 1651 calls %C1 1652 call %C1,[],0" 1653 [(set_attr_alternative "timings" 1654 [(if_then_else (eq_attr "cpu" "am34") 1655 (const_int 33) (const_int 44)) 1656 (if_then_else (eq_attr "cpu" "am34") 1657 (const_int 55) (const_int 33)) 1658 ]) 1659 ] 1660) 1661 1662(define_expand "untyped_call" 1663 [(parallel [(call (match_operand 0 "") 1664 (const_int 0)) 1665 (match_operand 1 "") 1666 (match_operand 2 "")])] 1667 "" 1668{ 1669 int i; 1670 1671 emit_call_insn (gen_call (operands[0], const0_rtx)); 1672 1673 for (i = 0; i < XVECLEN (operands[2], 0); i++) 1674 { 1675 rtx set = XVECEXP (operands[2], 0, i); 1676 emit_move_insn (SET_DEST (set), SET_SRC (set)); 1677 } 1678 DONE; 1679}) 1680 1681(define_insn "nop" 1682 [(const_int 0)] 1683 "" 1684 "nop" 1685) 1686 1687;; ---------------------------------------------------------------------- 1688;; EXTEND INSTRUCTIONS 1689;; ---------------------------------------------------------------------- 1690 1691(define_insn "zero_extendqisi2" 1692 [(set (match_operand:SI 0 "register_operand" "=D,D,r") 1693 (zero_extend:SI 1694 (match_operand:QI 1 "nonimmediate_operand" " 0,m,r")))] 1695 "" 1696 "@ 1697 extbu %0 1698 movbu %1,%0 1699 extbu %1,%0" 1700 [(set_attr "isa" "*,*,am33") 1701 (set_attr_alternative "timings" 1702 [(const_int 11) 1703 (if_then_else (eq_attr "cpu" "am34") 1704 (const_int 13) (const_int 24)) 1705 (const_int 11) 1706 ])] 1707) 1708 1709(define_insn "zero_extendhisi2" 1710 [(set (match_operand:SI 0 "register_operand" "=D,D,r") 1711 (zero_extend:SI 1712 (match_operand:HI 1 "nonimmediate_operand" " 0,m,r")))] 1713 "" 1714 "@ 1715 exthu %0 1716 movhu %1,%0 1717 exthu %1,%0" 1718 [(set_attr "isa" "*,*,am33") 1719 (set_attr_alternative "timings" 1720 [(const_int 11) 1721 (if_then_else (eq_attr "cpu" "am34") 1722 (const_int 13) (const_int 24)) 1723 (const_int 11)])] 1724) 1725 1726(define_insn "extendqisi2" 1727 [(set (match_operand:SI 0 "register_operand" "=D,r") 1728 (sign_extend:SI 1729 (match_operand:QI 1 "register_operand" "0,r")))] 1730 "" 1731 "@ 1732 extb %0 1733 extb %1,%0" 1734 [(set_attr "isa" "*,am33")] 1735) 1736 1737(define_insn "extendhisi2" 1738 [(set (match_operand:SI 0 "register_operand" "=D,r") 1739 (sign_extend:SI 1740 (match_operand:HI 1 "register_operand" "0,r")))] 1741 "" 1742 "@ 1743 exth %0 1744 exth %1,%0" 1745 [(set_attr "isa" "*,am33")] 1746) 1747 1748;; ---------------------------------------------------------------------- 1749;; SHIFTS 1750;; ---------------------------------------------------------------------- 1751 1752(define_insn "ashlsi3" 1753 [(set (match_operand:SI 0 "register_operand" "=r,D,d,d,D,D,D,r") 1754 (ashift:SI 1755 (match_operand:SI 1 "register_operand" " 0,0,0,0,0,0,0,r") 1756 (match_operand:QI 2 "nonmemory_operand" " J,K,M,L,D,O,i,r"))) 1757 (clobber (reg:CC CC_REG))] 1758 "" 1759 "@ 1760 add %0,%0 1761 asl2 %0 1762 asl2 %0\;add %0,%0 1763 asl2 %0\;asl2 %0 1764 asl %S2,%0 1765 asl %S2,%0 1766 asl %S2,%0 1767 asl %2,%1,%0" 1768 [(set_attr "isa" "*,*,*,*,*,*,*,am33") 1769 (set_attr "liw" "op2,op2,op2,op2,op2,op2,*,*") 1770 (set_attr "liw_op" "asl") 1771 (set_attr "timings" "11,11,22,22,11,11,11,11")] 1772) 1773 1774(define_insn "lshrsi3" 1775 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r") 1776 (lshiftrt:SI 1777 (match_operand:SI 1 "register_operand" "0,0,0,r") 1778 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r"))) 1779 (clobber (reg:CC CC_REG))] 1780 "" 1781 "@ 1782 lsr %S2,%0 1783 lsr %S2,%0 1784 lsr %S2,%0 1785 lsr %2,%1,%0" 1786 [(set_attr "isa" "*,*,*,am33") 1787 (set_attr "liw" "op2,op2,*,*") 1788 (set_attr "liw_op" "lsr")] 1789) 1790 1791(define_insn "ashrsi3" 1792 [(set (match_operand:SI 0 "register_operand" "=D,D,D,r") 1793 (ashiftrt:SI 1794 (match_operand:SI 1 "register_operand" "0,0,0,r") 1795 (match_operand:QI 2 "nonmemory_operand" "D,O,i,r"))) 1796 (clobber (reg:CC CC_REG))] 1797 "" 1798 "@ 1799 asr %S2,%0 1800 asr %S2,%0 1801 asr %S2,%0 1802 asr %2,%1,%0" 1803 [(set_attr "isa" "*,*,*,am33") 1804 (set_attr "liw" "op2,op2,*,*") 1805 (set_attr "liw_op" "asr")] 1806) 1807 1808;; ---------------------------------------------------------------------- 1809;; MISCELLANEOUS 1810;; ---------------------------------------------------------------------- 1811 1812;; Note the use of the (const_int 0) when generating the insn that matches 1813;; the bsch pattern. This ensures that the destination register is 1814;; initialised with 0 which will make the BSCH instruction set searching 1815;; at bit 31. 1816;; 1817;; The XOR in the instruction sequence below is there because the BSCH 1818;; instruction returns the bit number of the highest set bit and we want 1819;; the number of zero bits above that bit. The AM33 does not have a 1820;; reverse subtraction instruction, but we can use a simple xor instead 1821;; since we know that the top 27 bits are clear. 1822(define_expand "clzsi2" 1823 [(parallel [(set (match_operand:SI 0 "register_operand") 1824 (unspec:SI [(match_operand:SI 1 "register_operand") 1825 (const_int 0)] UNSPEC_BSCH)) 1826 (clobber (reg:CC CC_REG))]) 1827 (parallel [(set (match_dup 0) 1828 (xor:SI (match_dup 0) 1829 (const_int 31))) 1830 (clobber (reg:CC CC_REG))])] 1831 "TARGET_AM33" 1832) 1833 1834(define_insn "*bsch" 1835 [(set (match_operand:SI 0 "register_operand" "=r") 1836 (unspec:SI [(match_operand:SI 1 "register_operand" "r") 1837 (match_operand:SI 2 "nonmemory_operand" "0")] 1838 UNSPEC_BSCH)) 1839 (clobber (reg:CC CC_REG))] 1840 "TARGET_AM33" 1841 "bsch %1, %0" 1842) 1843 1844;; ---------------------------------------------------------------------- 1845;; FP INSTRUCTIONS 1846;; ---------------------------------------------------------------------- 1847 1848(define_insn "abssf2" 1849 [(set (match_operand:SF 0 "register_operand" "=f,f") 1850 (abs:SF (match_operand:SF 1 "register_operand" "0,?f")))] 1851 "TARGET_AM33_2" 1852 "@ 1853 fabs %0 1854 fabs %1, %0" 1855 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1856 (const_int 17) (const_int 14)))] 1857) 1858 1859(define_insn "negsf2" 1860 [(set (match_operand:SF 0 "register_operand" "=f,f") 1861 (neg:SF (match_operand:SF 1 "register_operand" "0,?f")))] 1862 "TARGET_AM33_2" 1863 "@ 1864 fneg %0 1865 fneg %1, %0" 1866 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1867 (const_int 17) (const_int 14)))] 1868) 1869 1870(define_expand "sqrtsf2" 1871 [(set (match_operand:SF 0 "register_operand" "") 1872 (sqrt:SF (match_operand:SF 1 "register_operand" "")))] 1873 "TARGET_AM33_2 && flag_unsafe_math_optimizations" 1874{ 1875 rtx scratch = gen_reg_rtx (SFmode); 1876 emit_insn (gen_rsqrtsf2 (scratch, operands[1], CONST1_RTX (SFmode))); 1877 emit_insn (gen_divsf3 (operands[0], force_reg (SFmode, CONST1_RTX (SFmode)), 1878 scratch)); 1879 DONE; 1880}) 1881 1882(define_insn "rsqrtsf2" 1883 [(set (match_operand:SF 0 "register_operand" "=f,f") 1884 (div:SF (match_operand:SF 2 "const_1f_operand" "F,F") 1885 (sqrt:SF (match_operand:SF 1 "register_operand" "0,?f")))) 1886 (clobber (reg:CC_FLOAT CC_REG))] 1887 "TARGET_AM33_2" 1888 "@ 1889 frsqrt %0 1890 frsqrt %1, %0" 1891 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1892 (const_int 4753) (const_int 2327)))] 1893) 1894 1895(define_insn "addsf3" 1896 [(set (match_operand:SF 0 "register_operand" "=f,f") 1897 (plus:SF (match_operand:SF 1 "register_operand" "%0,f") 1898 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) 1899 (clobber (reg:CC_FLOAT CC_REG))] 1900 "TARGET_AM33_2" 1901 "@ 1902 fadd %2, %0 1903 fadd %2, %1, %0" 1904 [(set_attr_alternative "timings" 1905 [(if_then_else (eq_attr "cpu" "am34") 1906 (const_int 17) (const_int 14)) 1907 (if_then_else (eq_attr "cpu" "am34") 1908 (const_int 17) (const_int 25)) 1909 ])] 1910) 1911 1912(define_insn "subsf3" 1913 [(set (match_operand:SF 0 "register_operand" "=f,f") 1914 (minus:SF (match_operand:SF 1 "register_operand" "0,f") 1915 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) 1916 (clobber (reg:CC_FLOAT CC_REG))] 1917 "TARGET_AM33_2" 1918 "@ 1919 fsub %2, %0 1920 fsub %2, %1, %0" 1921 [(set_attr_alternative "timings" 1922 [(if_then_else (eq_attr "cpu" "am34") 1923 (const_int 17) (const_int 14)) 1924 (if_then_else (eq_attr "cpu" "am34") 1925 (const_int 17) (const_int 25)) 1926 ])] 1927) 1928 1929(define_insn "mulsf3" 1930 [(set (match_operand:SF 0 "register_operand" "=f,f") 1931 (mult:SF (match_operand:SF 1 "register_operand" "%0,f") 1932 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) 1933 (clobber (reg:CC_FLOAT CC_REG)) 1934 ] 1935 "TARGET_AM33_2" 1936 "@ 1937 fmul %2, %0 1938 fmul %2, %1, %0" 1939 [(set_attr_alternative "timings" 1940 [(if_then_else (eq_attr "cpu" "am34") 1941 (const_int 17) (const_int 14)) 1942 (if_then_else (eq_attr "cpu" "am34") 1943 (const_int 17) (const_int 25)) 1944 ])] 1945) 1946 1947(define_insn "divsf3" 1948 [(set (match_operand:SF 0 "register_operand" "=f,f") 1949 (div:SF (match_operand:SF 1 "register_operand" "0,f") 1950 (match_operand:SF 2 "nonmemory_operand" "f,?fF"))) 1951 (clobber (reg:CC_FLOAT CC_REG))] 1952 "TARGET_AM33_2" 1953 "@ 1954 fdiv %2, %0 1955 fdiv %2, %1, %0" 1956 [(set_attr_alternative "timings" 1957 [(if_then_else (eq_attr "cpu" "am34") 1958 (const_int 2531) (const_int 1216)) 1959 (if_then_else (eq_attr "cpu" "am34") 1960 (const_int 2531) (const_int 1317)) 1961 ])] 1962) 1963 1964(define_insn "fmasf4" 1965 [(set (match_operand:SF 0 "register_operand" "=c") 1966 (fma:SF (match_operand:SF 1 "register_operand" "f") 1967 (match_operand:SF 2 "register_operand" "f") 1968 (match_operand:SF 3 "register_operand" "f"))) 1969 (clobber (reg:CC_FLOAT CC_REG)) 1970 ] 1971 "TARGET_AM33_2" 1972 "fmadd %1, %2, %3, %0" 1973 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1974 (const_int 17) (const_int 24)))] 1975) 1976 1977(define_insn "fmssf4" 1978 [(set (match_operand:SF 0 "register_operand" "=c") 1979 (fma:SF (match_operand:SF 1 "register_operand" "f") 1980 (match_operand:SF 2 "register_operand" "f") 1981 (neg:SF (match_operand:SF 3 "register_operand" "f")))) 1982 (clobber (reg:CC_FLOAT CC_REG)) 1983 ] 1984 "TARGET_AM33_2" 1985 "fmsub %1, %2, %3, %0" 1986 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 1987 (const_int 17) (const_int 24)))] 1988) 1989 1990(define_insn "fnmasf4" 1991 [(set (match_operand:SF 0 "register_operand" "=c") 1992 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) 1993 (match_operand:SF 2 "register_operand" "f") 1994 (match_operand:SF 3 "register_operand" "f"))) 1995 (clobber (reg:CC_FLOAT CC_REG)) 1996 ] 1997 "TARGET_AM33_2" 1998 "fnmadd %1, %2, %3, %0" 1999 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 2000 (const_int 17) (const_int 24)))] 2001) 2002 2003(define_insn "fnmssf4" 2004 [(set (match_operand:SF 0 "register_operand" "=c") 2005 (fma:SF (neg:SF (match_operand:SF 1 "register_operand" "f")) 2006 (match_operand:SF 2 "register_operand" "f") 2007 (neg:SF (match_operand:SF 3 "register_operand" "f")))) 2008 (clobber (reg:CC_FLOAT CC_REG)) 2009 ] 2010 "TARGET_AM33_2" 2011 "fnmsub %1, %2, %3, %0" 2012 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 2013 (const_int 17) (const_int 24)))] 2014) 2015 2016;; ---------------------------------------------------------------------- 2017;; PROLOGUE/EPILOGUE 2018;; ---------------------------------------------------------------------- 2019(define_expand "prologue" 2020 [(const_int 0)] 2021 "" 2022 { mn10300_expand_prologue (); DONE; } 2023) 2024 2025(define_expand "epilogue" 2026 [(return)] 2027 "" 2028 { mn10300_expand_epilogue (); DONE; } 2029) 2030 2031(define_insn "return" 2032 [(return)] 2033 "mn10300_can_use_rets_insn ()" 2034{ 2035 /* The RETF insn is 4 cycles faster than RETS, though 1 byte larger. */ 2036 if (optimize_insn_for_speed_p () && mn10300_can_use_retf_insn ()) 2037 return "retf [],0"; 2038 else 2039 return "rets"; 2040}) 2041 2042(define_insn "return_ret" 2043 [(return) 2044 (use (match_operand:SI 0 "const_int_operand" ""))] 2045 "" 2046{ 2047 /* The RETF insn is up to 3 cycles faster than RET. */ 2048 fputs ((mn10300_can_use_retf_insn () ? "\tretf " : "\tret "), asm_out_file); 2049 mn10300_print_reg_list (asm_out_file, mn10300_get_live_callee_saved_regs (NULL)); 2050 fprintf (asm_out_file, ",%d\n", (int) INTVAL (operands[0])); 2051 return ""; 2052}) 2053 2054;; This instruction matches one generated by mn10300_gen_multiple_store() 2055(define_insn "store_movm" 2056 [(match_parallel 0 "mn10300_store_multiple_operation" 2057 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_operand 1 "" "")))])] 2058 "" 2059{ 2060 fputs ("\tmovm ", asm_out_file); 2061 mn10300_print_reg_list (asm_out_file, 2062 mn10300_store_multiple_regs (operands[0])); 2063 fprintf (asm_out_file, ",(sp)\n"); 2064 return ""; 2065} 2066 ;; Assume that no more than 8 registers will be pushed. 2067 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 2068 (const_int 99) (const_int 88)))] 2069) 2070 2071(define_expand "load_pic" 2072 [(const_int 0)] 2073 "flag_pic" 2074{ 2075 if (TARGET_AM33) 2076 emit_insn (gen_am33_load_pic (pic_offset_table_rtx)); 2077 else if (mn10300_frame_size () == 0) 2078 emit_insn (gen_mn10300_load_pic0 (pic_offset_table_rtx)); 2079 else 2080 emit_insn (gen_mn10300_load_pic1 (pic_offset_table_rtx)); 2081 DONE; 2082}) 2083 2084(define_insn "am33_load_pic" 2085 [(set (match_operand:SI 0 "register_operand" "=a") 2086 (unspec:SI [(const_int 0)] UNSPEC_GOT)) 2087 (clobber (reg:CC CC_REG))] 2088 "TARGET_AM33" 2089{ 2090 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); 2091 return ".LPIC%=:\;mov pc,%0\;add %1-(.LPIC%=-.),%0"; 2092} 2093 [(set_attr "timings" "33")] 2094) 2095 2096;; Load pic register with push/pop of stack. 2097(define_insn "mn10300_load_pic0" 2098 [(set (match_operand:SI 0 "register_operand" "=a") 2099 (unspec:SI [(const_int 0)] UNSPEC_GOT)) 2100 (clobber (reg:SI MDR_REG)) 2101 (clobber (reg:CC CC_REG))] 2102 "" 2103{ 2104 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); 2105 return ("add -4,sp\;" 2106 "calls .LPIC%=\n" 2107 ".LPIC%=:\;" 2108 "movm (sp),[%0]\;" 2109 "add %1-(.LPIC%=-.),%0"); 2110} 2111 [(set_attr "timings" "88")] 2112) 2113 2114;; Load pic register re-using existing stack space. 2115(define_insn "mn10300_load_pic1" 2116 [(set (match_operand:SI 0 "register_operand" "=a") 2117 (unspec:SI [(const_int 0)] UNSPEC_GOT)) 2118 (clobber (mem:SI (reg:SI SP_REG))) 2119 (clobber (reg:SI MDR_REG)) 2120 (clobber (reg:CC CC_REG))] 2121 "" 2122{ 2123 operands[1] = gen_rtx_SYMBOL_REF (VOIDmode, GOT_SYMBOL_NAME); 2124 return ("calls .LPIC%=\n" 2125 ".LPIC%=:\;" 2126 "mov (sp),%0\;" 2127 "add %1-(.LPIC%=-.),%0"); 2128} 2129 [(set_attr "timings" "66")] 2130) 2131 2132;; The mode on operand 3 has been deliberately omitted because it 2133;; can be either SI (for arithmetic operations) or QI (for shifts). 2134(define_insn "liw" 2135 [(set (match_operand:SI 0 "register_operand" "=r") 2136 (unspec:SI [(match_dup 0) 2137 (match_operand 2 "liw_operand" "rO") 2138 (match_operand:SI 4 "const_int_operand" "")] 2139 UNSPEC_LIW)) 2140 (set (match_operand:SI 1 "register_operand" "=r") 2141 (unspec:SI [(match_dup 1) 2142 (match_operand 3 "liw_operand" "rO") 2143 (match_operand:SI 5 "const_int_operand" "")] 2144 UNSPEC_LIW))] 2145 "TARGET_ALLOW_LIW" 2146 "%W4_%W5 %2, %0, %3, %1" 2147 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 2148 (const_int 13) (const_int 12)))] 2149) 2150 2151;; The mode on operand 1 has been deliberately omitted because it 2152;; can be either SI (for arithmetic operations) or QI (for shifts). 2153(define_insn "cmp_liw" 2154 [(set (reg:CC CC_REG) 2155 (compare:CC (match_operand:SI 2 "register_operand" "r") 2156 (match_operand 3 "liw_operand" "rO"))) 2157 (set (match_operand:SI 0 "register_operand" "=r") 2158 (unspec:SI [(match_dup 0) 2159 (match_operand 1 "liw_operand" "rO") 2160 (match_operand:SI 4 "const_int_operand" "")] 2161 UNSPEC_LIW))] 2162 "TARGET_ALLOW_LIW" 2163 "cmp_%W4 %3, %2, %1, %0" 2164 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 2165 (const_int 13) (const_int 12)))] 2166) 2167 2168(define_insn "liw_cmp" 2169 [(set (match_operand:SI 0 "register_operand" "=r") 2170 (unspec:SI [(match_dup 0) 2171 (match_operand 1 "liw_operand" "rO") 2172 (match_operand:SI 4 "const_int_operand" "")] 2173 UNSPEC_LIW)) 2174 (set (reg:CC CC_REG) 2175 (compare:CC (match_operand:SI 2 "register_operand" "r") 2176 (match_operand 3 "liw_operand" "rO")))] 2177 "TARGET_ALLOW_LIW" 2178 "%W4_cmp %1, %0, %3, %2" 2179 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") 2180 (const_int 13) (const_int 12)))] 2181) 2182 2183;; Note - in theory the doloop patterns could be used here to express 2184;; the SETLB and Lcc instructions. In practice this does not work because 2185;; the acceptable forms of the doloop patterns do not include UNSPECs 2186;; and without them gcc's basic block reordering code can duplicate the 2187;; doloop_end pattern, leading to bogus multiple decrements of the loop 2188;; counter. 2189 2190(define_insn "setlb" 2191 [(unspec [(const_int 0)] UNSPEC_SETLB)] 2192 "TARGET_AM33 && TARGET_ALLOW_SETLB" 2193 "setlb" 2194) 2195 2196(define_insn "Lcc" 2197 [(set (pc) 2198 (if_then_else (match_operator 0 "comparison_operator" 2199 [(reg:CC CC_REG) (const_int 0)]) 2200 (label_ref (match_operand 1 "" "")) 2201 (pc))) 2202 (unspec [(const_int 1)] UNSPEC_SETLB)] 2203 "TARGET_AM33 && TARGET_ALLOW_SETLB" 2204 "L%b0 # loop back to: %1" 2205) 2206 2207(define_insn "FLcc" 2208 [(set (pc) 2209 (if_then_else (match_operator 0 "comparison_operator" 2210 [(reg:CC_FLOAT CC_REG) (const_int 0)]) 2211 (label_ref (match_operand 1 "" "")) 2212 (pc))) 2213 (unspec [(const_int 2)] UNSPEC_SETLB)] 2214 "TARGET_AM33_2 && TARGET_ALLOW_SETLB" 2215 "FL%b0 # loop back to: %1" 2216 [(set (attr "timings") (if_then_else (eq_attr "cpu" "am34") (const_int 44) (const_int 11)))] 2217) 2218