1;; Octeon pipeline description. 2;; Copyright (C) 2008 3;; Free Software Foundation, Inc. 4 5;; This file is part of GCC. 6 7;; GCC is free software; you can redistribute it and/or modify 8;; it under the terms of the GNU General Public License as published by 9;; the Free Software Foundation; either version 3, or (at your option) 10;; any later version. 11 12;; GCC is distributed in the hope that it will be useful, 13;; but WITHOUT ANY WARRANTY; without even the implied warranty of 14;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15;; GNU General Public License for more details. 16 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20;; Copyright (C) 2004, 2005, 2006 Cavium Networks. 21 22 23;; Octeon is a dual-issue processor that can issue all instructions on 24;; pipe0 and a subset on pipe1. 25 26(define_automaton "octeon_main, octeon_mult") 27 28(define_cpu_unit "octeon_pipe0" "octeon_main") 29(define_cpu_unit "octeon_pipe1" "octeon_main") 30(define_cpu_unit "octeon_mult" "octeon_mult") 31 32(define_insn_reservation "octeon_arith" 1 33 (and (eq_attr "cpu" "octeon") 34 (eq_attr "type" "arith,const,logical,move,shift,signext,slt,nop")) 35 "octeon_pipe0 | octeon_pipe1") 36 37(define_insn_reservation "octeon_condmove" 2 38 (and (eq_attr "cpu" "octeon") 39 (eq_attr "type" "condmove")) 40 "octeon_pipe0 | octeon_pipe1") 41 42(define_insn_reservation "octeon_load" 2 43 (and (eq_attr "cpu" "octeon") 44 (eq_attr "type" "load,prefetch,mtc,mfc")) 45 "octeon_pipe0") 46 47(define_insn_reservation "octeon_store" 1 48 (and (eq_attr "cpu" "octeon") 49 (eq_attr "type" "store")) 50 "octeon_pipe0") 51 52(define_insn_reservation "octeon_brj" 1 53 (and (eq_attr "cpu" "octeon") 54 (eq_attr "type" "branch,jump,call,trap")) 55 "octeon_pipe0") 56 57(define_insn_reservation "octeon_imul3" 5 58 (and (eq_attr "cpu" "octeon") 59 (eq_attr "type" "imul3,pop,clz")) 60 "(octeon_pipe0 | octeon_pipe1) + octeon_mult") 61 62(define_insn_reservation "octeon_imul" 2 63 (and (eq_attr "cpu" "octeon") 64 (eq_attr "type" "imul,mthilo")) 65 "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult") 66 67(define_insn_reservation "octeon_mfhilo" 5 68 (and (eq_attr "cpu" "octeon") 69 (eq_attr "type" "mfhilo")) 70 "(octeon_pipe0 | octeon_pipe1) + octeon_mult") 71 72(define_insn_reservation "octeon_imadd" 4 73 (and (eq_attr "cpu" "octeon") 74 (eq_attr "type" "imadd")) 75 "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*3") 76 77(define_insn_reservation "octeon_idiv" 72 78 (and (eq_attr "cpu" "octeon") 79 (eq_attr "type" "idiv")) 80 "(octeon_pipe0 | octeon_pipe1) + octeon_mult, octeon_mult*71") 81 82;; Assume both pipes are needed for unknown and multiple-instruction 83;; patterns. 84 85(define_insn_reservation "octeon_unknown" 1 86 (and (eq_attr "cpu" "octeon") 87 (eq_attr "type" "unknown,multi")) 88 "octeon_pipe0 + octeon_pipe1") 89