1; Options for the MIPS port of the compiler 2; 3; Copyright (C) 2005-2013 Free Software Foundation, Inc. 4; 5; This file is part of GCC. 6; 7; GCC is free software; you can redistribute it and/or modify it under 8; the terms of the GNU General Public License as published by the Free 9; Software Foundation; either version 3, or (at your option) any later 10; version. 11; 12; GCC is distributed in the hope that it will be useful, but WITHOUT 13; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15; License for more details. 16; 17; You should have received a copy of the GNU General Public License 18; along with GCC; see the file COPYING3. If not see 19; <http://www.gnu.org/licenses/>. 20 21HeaderInclude 22config/mips/mips-opts.h 23 24EB 25Driver 26 27EL 28Driver 29 30mabi= 31Target RejectNegative Joined Enum(mips_abi) Var(mips_abi) Init(MIPS_ABI_DEFAULT) 32-mabi=ABI Generate code that conforms to the given ABI 33 34Enum 35Name(mips_abi) Type(int) 36Known MIPS ABIs (for use with the -mabi= option): 37 38EnumValue 39Enum(mips_abi) String(32) Value(ABI_32) 40 41EnumValue 42Enum(mips_abi) String(o64) Value(ABI_O64) 43 44EnumValue 45Enum(mips_abi) String(n32) Value(ABI_N32) 46 47EnumValue 48Enum(mips_abi) String(64) Value(ABI_64) 49 50EnumValue 51Enum(mips_abi) String(eabi) Value(ABI_EABI) 52 53mabicalls 54Target Report Mask(ABICALLS) 55Generate code that can be used in SVR4-style dynamic objects 56 57mmad 58Target Report Var(TARGET_MAD) 59Use PMC-style 'mad' instructions 60 61march= 62Target RejectNegative Joined Var(mips_arch_option) ToLower Enum(mips_arch_opt_value) 63-march=ISA Generate code for the given ISA 64 65mbranch-cost= 66Target RejectNegative Joined UInteger Var(mips_branch_cost) 67-mbranch-cost=COST Set the cost of branches to roughly COST instructions 68 69mbranch-likely 70Target Report Mask(BRANCHLIKELY) 71Use Branch Likely instructions, overriding the architecture default 72 73mflip-mips16 74Target Report Var(TARGET_FLIP_MIPS16) 75Switch on/off MIPS16 ASE on alternating functions for compiler testing 76 77mcheck-zero-division 78Target Report Mask(CHECK_ZERO_DIV) 79Trap on integer divide by zero 80 81mcode-readable= 82Target RejectNegative Joined Enum(mips_code_readable_setting) Var(mips_code_readable) Init(CODE_READABLE_YES) 83-mcode-readable=SETTING Specify when instructions are allowed to access code 84 85Enum 86Name(mips_code_readable_setting) Type(enum mips_code_readable_setting) 87Valid arguments to -mcode-readable=: 88 89EnumValue 90Enum(mips_code_readable_setting) String(yes) Value(CODE_READABLE_YES) 91 92EnumValue 93Enum(mips_code_readable_setting) String(pcrel) Value(CODE_READABLE_PCREL) 94 95EnumValue 96Enum(mips_code_readable_setting) String(no) Value(CODE_READABLE_NO) 97 98mdivide-breaks 99Target Report RejectNegative Mask(DIVIDE_BREAKS) 100Use branch-and-break sequences to check for integer divide by zero 101 102mdivide-traps 103Target Report RejectNegative InverseMask(DIVIDE_BREAKS, DIVIDE_TRAPS) 104Use trap instructions to check for integer divide by zero 105 106mdmx 107Target Report RejectNegative Var(TARGET_MDMX) 108Allow the use of MDMX instructions 109 110mdouble-float 111Target Report RejectNegative InverseMask(SINGLE_FLOAT, DOUBLE_FLOAT) 112Allow hardware floating-point instructions to cover both 32-bit and 64-bit operations 113 114mdsp 115Target Report Mask(DSP) 116Use MIPS-DSP instructions 117 118mdspr2 119Target Report Mask(DSPR2) 120Use MIPS-DSP REV 2 instructions 121 122mdebug 123Target Var(TARGET_DEBUG_MODE) Undocumented 124 125mdebugd 126Target Var(TARGET_DEBUG_D_MODE) Undocumented 127 128meb 129Target Report RejectNegative Mask(BIG_ENDIAN) 130Use big-endian byte order 131 132mel 133Target Report RejectNegative InverseMask(BIG_ENDIAN, LITTLE_ENDIAN) 134Use little-endian byte order 135 136membedded-data 137Target Report Var(TARGET_EMBEDDED_DATA) 138Use ROM instead of RAM 139 140mexplicit-relocs 141Target Report Mask(EXPLICIT_RELOCS) 142Use NewABI-style %reloc() assembly operators 143 144mextern-sdata 145Target Report Var(TARGET_EXTERN_SDATA) Init(1) 146Use -G for data that is not defined by the current object 147 148mfix-24k 149Target Report Var(TARGET_FIX_24K) 150Work around certain 24K errata 151 152mfix-r4000 153Target Report Mask(FIX_R4000) 154Work around certain R4000 errata 155 156mfix-r4400 157Target Report Mask(FIX_R4400) 158Work around certain R4400 errata 159 160mfix-r10000 161Target Report Mask(FIX_R10000) 162Work around certain R10000 errata 163 164mfix-sb1 165Target Report Var(TARGET_FIX_SB1) 166Work around errata for early SB-1 revision 2 cores 167 168mfix-vr4120 169Target Report Var(TARGET_FIX_VR4120) 170Work around certain VR4120 errata 171 172mfix-vr4130 173Target Report Var(TARGET_FIX_VR4130) 174Work around VR4130 mflo/mfhi errata 175 176mfix4300 177Target Report Var(TARGET_4300_MUL_FIX) 178Work around an early 4300 hardware bug 179 180mfp-exceptions 181Target Report Mask(FP_EXCEPTIONS) 182FP exceptions are enabled 183 184mfp32 185Target Report RejectNegative InverseMask(FLOAT64) 186Use 32-bit floating-point registers 187 188mfp64 189Target Report RejectNegative Mask(FLOAT64) 190Use 64-bit floating-point registers 191 192mflush-func= 193Target RejectNegative Joined Var(mips_cache_flush_func) Init(CACHE_FLUSH_FUNC) 194-mflush-func=FUNC Use FUNC to flush the cache before calling stack trampolines 195 196mfused-madd 197Target Report Mask(FUSED_MADD) 198Generate floating-point multiply-add instructions 199 200mgp32 201Target Report RejectNegative InverseMask(64BIT) 202Use 32-bit general registers 203 204mgp64 205Target Report RejectNegative Mask(64BIT) 206Use 64-bit general registers 207 208mgpopt 209Target Report Var(TARGET_GPOPT) Init(1) 210Use GP-relative addressing to access small data 211 212mplt 213Target Report Var(TARGET_PLT) 214When generating -mabicalls code, allow executables to use PLTs and copy relocations 215 216mhard-float 217Target Report RejectNegative InverseMask(SOFT_FLOAT_ABI, HARD_FLOAT_ABI) 218Allow the use of hardware floating-point ABI and instructions 219 220minterlink-mips16 221Target Report Var(TARGET_INTERLINK_MIPS16) Init(0) 222Generate code that can be safely linked with MIPS16 code. 223 224mips 225Target RejectNegative Joined ToLower Enum(mips_mips_opt_value) Var(mips_isa_option) 226-mipsN Generate code for ISA level N 227 228mips16 229Target Report RejectNegative Mask(MIPS16) 230Generate MIPS16 code 231 232mips3d 233Target Report RejectNegative Mask(MIPS3D) 234Use MIPS-3D instructions 235 236mllsc 237Target Report Mask(LLSC) 238Use ll, sc and sync instructions 239 240mlocal-sdata 241Target Report Var(TARGET_LOCAL_SDATA) Init(1) 242Use -G for object-local data 243 244mlong-calls 245Target Report Var(TARGET_LONG_CALLS) 246Use indirect calls 247 248mlong32 249Target Report RejectNegative InverseMask(LONG64, LONG32) 250Use a 32-bit long type 251 252mlong64 253Target Report RejectNegative Mask(LONG64) 254Use a 64-bit long type 255 256mmcount-ra-address 257Target Report Var(TARGET_MCOUNT_RA_ADDRESS) 258Pass the address of the ra save location to _mcount in $12 259 260mmemcpy 261Target Report Mask(MEMCPY) 262Don't optimize block moves 263 264mmt 265Target Report Var(TARGET_MT) 266Allow the use of MT instructions 267 268mno-float 269Target Report RejectNegative Var(TARGET_NO_FLOAT) Condition(TARGET_SUPPORTS_NO_FLOAT) 270Prevent the use of all floating-point operations 271 272mmcu 273Target Report Var(TARGET_MCU) 274Use MCU instructions 275 276mno-flush-func 277Target RejectNegative 278Do not use a cache-flushing function before calling stack trampolines 279 280mno-mdmx 281Target Report RejectNegative Var(TARGET_MDMX, 0) 282Do not use MDMX instructions 283 284mno-mips16 285Target Report RejectNegative InverseMask(MIPS16) 286Generate normal-mode code 287 288mno-mips3d 289Target Report RejectNegative InverseMask(MIPS3D) 290Do not use MIPS-3D instructions 291 292mpaired-single 293Target Report Mask(PAIRED_SINGLE_FLOAT) 294Use paired-single floating-point instructions 295 296mr10k-cache-barrier= 297Target Joined RejectNegative Enum(mips_r10k_cache_barrier_setting) Var(mips_r10k_cache_barrier) Init(R10K_CACHE_BARRIER_NONE) 298-mr10k-cache-barrier=SETTING Specify when r10k cache barriers should be inserted 299 300Enum 301Name(mips_r10k_cache_barrier_setting) Type(enum mips_r10k_cache_barrier_setting) 302Valid arguments to -mr10k-cache-barrier=: 303 304EnumValue 305Enum(mips_r10k_cache_barrier_setting) String(load-store) Value(R10K_CACHE_BARRIER_LOAD_STORE) 306 307EnumValue 308Enum(mips_r10k_cache_barrier_setting) String(store) Value(R10K_CACHE_BARRIER_STORE) 309 310EnumValue 311Enum(mips_r10k_cache_barrier_setting) String(none) Value(R10K_CACHE_BARRIER_NONE) 312 313mrelax-pic-calls 314Target Report Mask(RELAX_PIC_CALLS) 315Try to allow the linker to turn PIC calls into direct calls 316 317mshared 318Target Report Var(TARGET_SHARED) Init(1) 319When generating -mabicalls code, make the code suitable for use in shared libraries 320 321msingle-float 322Target Report RejectNegative Mask(SINGLE_FLOAT) 323Restrict the use of hardware floating-point instructions to 32-bit operations 324 325msmartmips 326Target Report Mask(SMARTMIPS) 327Use SmartMIPS instructions 328 329msoft-float 330Target Report RejectNegative Mask(SOFT_FLOAT_ABI) 331Prevent the use of all hardware floating-point instructions 332 333msplit-addresses 334Target Report Mask(SPLIT_ADDRESSES) 335Optimize lui/addiu address loads 336 337msym32 338Target Report Var(TARGET_SYM32) 339Assume all symbols have 32-bit values 340 341msynci 342Target Report Mask(SYNCI) 343Use synci instruction to invalidate i-cache 344 345mtune= 346Target RejectNegative Joined Var(mips_tune_option) ToLower Enum(mips_arch_opt_value) 347-mtune=PROCESSOR Optimize the output for PROCESSOR 348 349muninit-const-in-rodata 350Target Report Var(TARGET_UNINIT_CONST_IN_RODATA) 351Put uninitialized constants in ROM (needs -membedded-data) 352 353mvr4130-align 354Target Report Mask(VR4130_ALIGN) 355Perform VR4130-specific alignment optimizations 356 357mxgot 358Target Report Var(TARGET_XGOT) 359Lift restrictions on GOT size 360 361noasmopt 362Driver 363