1;; Copyright (C) 2007-2013 Free Software Foundation, Inc. 2;; 3;; This file is part of GCC. 4;; 5;; GCC is free software; you can redistribute it and/or modify 6;; it under the terms of the GNU General Public License as published by 7;; the Free Software Foundation; either version 3, or (at your option) 8;; any later version. 9;; 10;; GCC is distributed in the hope that it will be useful, 11;; but WITHOUT ANY WARRANTY; without even the implied warranty of 12;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13;; GNU General Public License for more details. 14;; 15;; You should have received a copy of the GNU General Public License 16;; along with GCC; see the file COPYING3. If not see 17;; <http://www.gnu.org/licenses/>. 18;; 19; MIPS DSP ASE REV 2 Revision 0.02 11/24/2006 20 21(define_c_enum "unspec" [ 22 UNSPEC_ABSQ_S_QB 23 UNSPEC_ADDU_PH 24 UNSPEC_ADDU_S_PH 25 UNSPEC_ADDUH_QB 26 UNSPEC_ADDUH_R_QB 27 UNSPEC_APPEND 28 UNSPEC_BALIGN 29 UNSPEC_CMPGDU_EQ_QB 30 UNSPEC_CMPGDU_LT_QB 31 UNSPEC_CMPGDU_LE_QB 32 UNSPEC_DPA_W_PH 33 UNSPEC_DPS_W_PH 34 UNSPEC_MADD 35 UNSPEC_MADDU 36 UNSPEC_MSUB 37 UNSPEC_MSUBU 38 UNSPEC_MUL_PH 39 UNSPEC_MUL_S_PH 40 UNSPEC_MULQ_RS_W 41 UNSPEC_MULQ_S_PH 42 UNSPEC_MULQ_S_W 43 UNSPEC_MULSA_W_PH 44 UNSPEC_MULT 45 UNSPEC_MULTU 46 UNSPEC_PRECR_QB_PH 47 UNSPEC_PRECR_SRA_PH_W 48 UNSPEC_PRECR_SRA_R_PH_W 49 UNSPEC_PREPEND 50 UNSPEC_SHRA_QB 51 UNSPEC_SHRA_R_QB 52 UNSPEC_SHRL_PH 53 UNSPEC_SUBU_PH 54 UNSPEC_SUBU_S_PH 55 UNSPEC_SUBUH_QB 56 UNSPEC_SUBUH_R_QB 57 UNSPEC_ADDQH_PH 58 UNSPEC_ADDQH_R_PH 59 UNSPEC_ADDQH_W 60 UNSPEC_ADDQH_R_W 61 UNSPEC_SUBQH_PH 62 UNSPEC_SUBQH_R_PH 63 UNSPEC_SUBQH_W 64 UNSPEC_SUBQH_R_W 65 UNSPEC_DPAX_W_PH 66 UNSPEC_DPSX_W_PH 67 UNSPEC_DPAQX_S_W_PH 68 UNSPEC_DPAQX_SA_W_PH 69 UNSPEC_DPSQX_S_W_PH 70 UNSPEC_DPSQX_SA_W_PH 71]) 72 73(define_insn "mips_absq_s_qb" 74 [(parallel 75 [(set (match_operand:V4QI 0 "register_operand" "=d") 76 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG")] 77 UNSPEC_ABSQ_S_QB)) 78 (set (reg:CCDSP CCDSP_OU_REGNUM) 79 (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S_QB))])] 80 "ISA_HAS_DSPR2" 81 "absq_s.qb\t%0,%z1" 82 [(set_attr "type" "dspalusat") 83 (set_attr "mode" "SI")]) 84 85(define_insn "mips_addu_ph" 86 [(parallel 87 [(set (match_operand:V2HI 0 "register_operand" "=d") 88 (plus:V2HI (match_operand:V2HI 1 "reg_or_0_operand" "dYG") 89 (match_operand:V2HI 2 "reg_or_0_operand" "dYG"))) 90 (set (reg:CCDSP CCDSP_OU_REGNUM) 91 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_PH))])] 92 "ISA_HAS_DSPR2" 93 "addu.ph\t%0,%z1,%z2" 94 [(set_attr "type" "dspalu") 95 (set_attr "mode" "SI")]) 96 97(define_insn "mips_addu_s_ph" 98 [(parallel 99 [(set (match_operand:V2HI 0 "register_operand" "=d") 100 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 101 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 102 UNSPEC_ADDU_S_PH)) 103 (set (reg:CCDSP CCDSP_OU_REGNUM) 104 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDU_S_PH))])] 105 "ISA_HAS_DSPR2" 106 "addu_s.ph\t%0,%z1,%z2" 107 [(set_attr "type" "dspalusat") 108 (set_attr "mode" "SI")]) 109 110(define_insn "mips_adduh_qb" 111 [(set (match_operand:V4QI 0 "register_operand" "=d") 112 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") 113 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] 114 UNSPEC_ADDUH_QB))] 115 "ISA_HAS_DSPR2" 116 "adduh.qb\t%0,%z1,%z2" 117 [(set_attr "type" "dspalu") 118 (set_attr "mode" "SI")]) 119 120(define_insn "mips_adduh_r_qb" 121 [(set (match_operand:V4QI 0 "register_operand" "=d") 122 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") 123 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] 124 UNSPEC_ADDUH_R_QB))] 125 "ISA_HAS_DSPR2" 126 "adduh_r.qb\t%0,%z1,%z2" 127 [(set_attr "type" "dspalusat") 128 (set_attr "mode" "SI")]) 129 130(define_insn "mips_append" 131 [(set (match_operand:SI 0 "register_operand" "=d") 132 (unspec:SI [(match_operand:SI 1 "register_operand" "0") 133 (match_operand:SI 2 "reg_or_0_operand" "dJ") 134 (match_operand:SI 3 "const_int_operand" "n")] 135 UNSPEC_APPEND))] 136 "ISA_HAS_DSPR2" 137{ 138 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31) 139 operands[2] = GEN_INT (INTVAL (operands[2]) & 31); 140 return "append\t%0,%z2,%3"; 141} 142 [(set_attr "type" "dspalu") 143 (set_attr "mode" "SI")]) 144 145(define_insn "mips_balign" 146 [(set (match_operand:SI 0 "register_operand" "=d") 147 (unspec:SI [(match_operand:SI 1 "register_operand" "0") 148 (match_operand:SI 2 "reg_or_0_operand" "dJ") 149 (match_operand:SI 3 "const_int_operand" "n")] 150 UNSPEC_BALIGN))] 151 "ISA_HAS_DSPR2" 152{ 153 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 3) 154 operands[2] = GEN_INT (INTVAL (operands[2]) & 3); 155 return "balign\t%0,%z2,%3"; 156} 157 [(set_attr "type" "dspalu") 158 (set_attr "mode" "SI")]) 159 160(define_insn "mips_cmpgdu_eq_qb" 161 [(parallel 162 [(set (match_operand:SI 0 "register_operand" "=d") 163 (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") 164 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] 165 UNSPEC_CMPGDU_EQ_QB)) 166 (set (reg:CCDSP CCDSP_CC_REGNUM) 167 (unspec:CCDSP [(match_dup 1) (match_dup 2) 168 (reg:CCDSP CCDSP_CC_REGNUM)] 169 UNSPEC_CMPGDU_EQ_QB))])] 170 "ISA_HAS_DSPR2" 171 "cmpgdu.eq.qb\t%0,%z1,%z2" 172 [(set_attr "type" "dspalu") 173 (set_attr "mode" "SI")]) 174 175(define_insn "mips_cmpgdu_lt_qb" 176 [(parallel 177 [(set (match_operand:SI 0 "register_operand" "=d") 178 (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") 179 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] 180 UNSPEC_CMPGDU_LT_QB)) 181 (set (reg:CCDSP CCDSP_CC_REGNUM) 182 (unspec:CCDSP [(match_dup 1) (match_dup 2) 183 (reg:CCDSP CCDSP_CC_REGNUM)] 184 UNSPEC_CMPGDU_LT_QB))])] 185 "ISA_HAS_DSPR2" 186 "cmpgdu.lt.qb\t%0,%z1,%z2" 187 [(set_attr "type" "dspalu") 188 (set_attr "mode" "SI")]) 189 190(define_insn "mips_cmpgdu_le_qb" 191 [(parallel 192 [(set (match_operand:SI 0 "register_operand" "=d") 193 (unspec:SI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") 194 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] 195 UNSPEC_CMPGDU_LE_QB)) 196 (set (reg:CCDSP CCDSP_CC_REGNUM) 197 (unspec:CCDSP [(match_dup 1) (match_dup 2) 198 (reg:CCDSP CCDSP_CC_REGNUM)] 199 UNSPEC_CMPGDU_LE_QB))])] 200 "ISA_HAS_DSPR2" 201 "cmpgdu.le.qb\t%0,%z1,%z2" 202 [(set_attr "type" "dspalu") 203 (set_attr "mode" "SI")]) 204 205(define_insn "mips_dpa_w_ph" 206 [(set (match_operand:DI 0 "register_operand" "=a") 207 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 208 (match_operand:V2HI 2 "reg_or_0_operand" "dYG") 209 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 210 UNSPEC_DPA_W_PH))] 211 "ISA_HAS_DSPR2 && !TARGET_64BIT" 212 "dpa.w.ph\t%q0,%z2,%z3" 213 [(set_attr "type" "dspmac") 214 (set_attr "accum_in" "1") 215 (set_attr "mode" "SI")]) 216 217(define_insn "mips_dps_w_ph" 218 [(set (match_operand:DI 0 "register_operand" "=a") 219 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 220 (match_operand:V2HI 2 "reg_or_0_operand" "dYG") 221 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 222 UNSPEC_DPS_W_PH))] 223 "ISA_HAS_DSPR2 && !TARGET_64BIT" 224 "dps.w.ph\t%q0,%z2,%z3" 225 [(set_attr "type" "dspmac") 226 (set_attr "accum_in" "1") 227 (set_attr "mode" "SI")]) 228 229(define_insn "mulv2hi3" 230 [(parallel 231 [(set (match_operand:V2HI 0 "register_operand" "=d") 232 (mult:V2HI (match_operand:V2HI 1 "register_operand" "d") 233 (match_operand:V2HI 2 "register_operand" "d"))) 234 (set (reg:CCDSP CCDSP_OU_REGNUM) 235 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_PH)) 236 (clobber (match_scratch:DI 3 "=x"))])] 237 "ISA_HAS_DSPR2" 238 "mul.ph\t%0,%1,%2" 239 [(set_attr "type" "imul3") 240 (set_attr "mode" "SI")]) 241 242(define_insn "mips_mul_s_ph" 243 [(parallel 244 [(set (match_operand:V2HI 0 "register_operand" "=d") 245 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 246 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 247 UNSPEC_MUL_S_PH)) 248 (set (reg:CCDSP CCDSP_OU_REGNUM) 249 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MUL_S_PH)) 250 (clobber (match_scratch:DI 3 "=x"))])] 251 "ISA_HAS_DSPR2" 252 "mul_s.ph\t%0,%z1,%z2" 253 [(set_attr "type" "imul3") 254 (set_attr "mode" "SI")]) 255 256(define_insn "mips_mulq_rs_w" 257 [(parallel 258 [(set (match_operand:SI 0 "register_operand" "=d") 259 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") 260 (match_operand:SI 2 "reg_or_0_operand" "dJ")] 261 UNSPEC_MULQ_RS_W)) 262 (set (reg:CCDSP CCDSP_OU_REGNUM) 263 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_W)) 264 (clobber (match_scratch:DI 3 "=x"))])] 265 "ISA_HAS_DSPR2" 266 "mulq_rs.w\t%0,%z1,%z2" 267 [(set_attr "type" "imul3") 268 (set_attr "mode" "SI")]) 269 270(define_insn "mips_mulq_s_ph" 271 [(parallel 272 [(set (match_operand:V2HI 0 "register_operand" "=d") 273 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 274 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 275 UNSPEC_MULQ_S_PH)) 276 (set (reg:CCDSP CCDSP_OU_REGNUM) 277 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_PH)) 278 (clobber (match_scratch:DI 3 "=x"))])] 279 "ISA_HAS_DSPR2" 280 "mulq_s.ph\t%0,%z1,%z2" 281 [(set_attr "type" "imul3") 282 (set_attr "mode" "SI")]) 283 284(define_insn "mips_mulq_s_w" 285 [(parallel 286 [(set (match_operand:SI 0 "register_operand" "=d") 287 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") 288 (match_operand:SI 2 "reg_or_0_operand" "dJ")] 289 UNSPEC_MULQ_S_W)) 290 (set (reg:CCDSP CCDSP_OU_REGNUM) 291 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_S_W)) 292 (clobber (match_scratch:DI 3 "=x"))])] 293 "ISA_HAS_DSPR2" 294 "mulq_s.w\t%0,%z1,%z2" 295 [(set_attr "type" "imul3") 296 (set_attr "mode" "SI")]) 297 298(define_insn "mips_mulsa_w_ph" 299 [(set (match_operand:DI 0 "register_operand" "=a") 300 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 301 (match_operand:V2HI 2 "reg_or_0_operand" "dYG") 302 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 303 UNSPEC_MULSA_W_PH))] 304 "ISA_HAS_DSPR2 && !TARGET_64BIT" 305 "mulsa.w.ph\t%q0,%z2,%z3" 306 [(set_attr "type" "dspmac") 307 (set_attr "accum_in" "1") 308 (set_attr "mode" "SI")]) 309 310(define_insn "mips_precr_qb_ph" 311 [(set (match_operand:V4QI 0 "register_operand" "=d") 312 (unspec:V4QI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 313 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 314 UNSPEC_PRECR_QB_PH))] 315 "ISA_HAS_DSPR2" 316 "precr.qb.ph\t%0,%z1,%z2" 317 [(set_attr "type" "dspalu") 318 (set_attr "mode" "SI")]) 319 320(define_insn "mips_precr_sra_ph_w" 321 [(set (match_operand:V2HI 0 "register_operand" "=d") 322 (unspec:V2HI [(match_operand:SI 1 "register_operand" "0") 323 (match_operand:SI 2 "reg_or_0_operand" "dJ") 324 (match_operand:SI 3 "const_int_operand" "n")] 325 UNSPEC_PRECR_SRA_PH_W))] 326 "ISA_HAS_DSPR2" 327{ 328 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31) 329 operands[2] = GEN_INT (INTVAL (operands[2]) & 31); 330 return "precr_sra.ph.w\t%0,%z2,%3"; 331} 332 [(set_attr "type" "dspalu") 333 (set_attr "mode" "SI")]) 334 335(define_insn "mips_precr_sra_r_ph_w" 336 [(set (match_operand:V2HI 0 "register_operand" "=d") 337 (unspec:V2HI [(match_operand:SI 1 "register_operand" "0") 338 (match_operand:SI 2 "reg_or_0_operand" "dJ") 339 (match_operand:SI 3 "const_int_operand" "n")] 340 UNSPEC_PRECR_SRA_R_PH_W))] 341 "ISA_HAS_DSPR2" 342{ 343 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31) 344 operands[2] = GEN_INT (INTVAL (operands[2]) & 31); 345 return "precr_sra_r.ph.w\t%0,%z2,%3"; 346} 347 [(set_attr "type" "dspalu") 348 (set_attr "mode" "SI")]) 349 350(define_insn "mips_prepend" 351 [(set (match_operand:SI 0 "register_operand" "=d") 352 (unspec:SI [(match_operand:SI 1 "register_operand" "0") 353 (match_operand:SI 2 "reg_or_0_operand" "dJ") 354 (match_operand:SI 3 "const_int_operand" "n")] 355 UNSPEC_PREPEND))] 356 "ISA_HAS_DSPR2" 357{ 358 if (INTVAL (operands[3]) & ~(unsigned HOST_WIDE_INT) 31) 359 operands[3] = GEN_INT (INTVAL (operands[3]) & 31); 360 return "prepend\t%0,%z2,%3"; 361} 362 [(set_attr "type" "dspalu") 363 (set_attr "mode" "SI")]) 364 365(define_insn "mips_shra_qb" 366 [(set (match_operand:V4QI 0 "register_operand" "=d,d") 367 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG") 368 (match_operand:SI 2 "arith_operand" "I,d")] 369 UNSPEC_SHRA_QB))] 370 "ISA_HAS_DSPR2" 371{ 372 if (which_alternative == 0) 373 { 374 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7) 375 operands[2] = GEN_INT (INTVAL (operands[2]) & 7); 376 return "shra.qb\t%0,%z1,%2"; 377 } 378 return "shrav.qb\t%0,%z1,%2"; 379} 380 [(set_attr "type" "dspalu") 381 (set_attr "mode" "SI")]) 382 383 384(define_insn "mips_shra_r_qb" 385 [(set (match_operand:V4QI 0 "register_operand" "=d,d") 386 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG,dYG") 387 (match_operand:SI 2 "arith_operand" "I,d")] 388 UNSPEC_SHRA_R_QB))] 389 "ISA_HAS_DSPR2" 390{ 391 if (which_alternative == 0) 392 { 393 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 7) 394 operands[2] = GEN_INT (INTVAL (operands[2]) & 7); 395 return "shra_r.qb\t%0,%z1,%2"; 396 } 397 return "shrav_r.qb\t%0,%z1,%2"; 398} 399 [(set_attr "type" "dspalu") 400 (set_attr "mode" "SI")]) 401 402(define_insn "mips_shrl_ph" 403 [(set (match_operand:V2HI 0 "register_operand" "=d,d") 404 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG,dYG") 405 (match_operand:SI 2 "arith_operand" "I,d")] 406 UNSPEC_SHRL_PH))] 407 "ISA_HAS_DSPR2" 408{ 409 if (which_alternative == 0) 410 { 411 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 15) 412 operands[2] = GEN_INT (INTVAL (operands[2]) & 15); 413 return "shrl.ph\t%0,%z1,%2"; 414 } 415 return "shrlv.ph\t%0,%z1,%2"; 416} 417 [(set_attr "type" "dspalu") 418 (set_attr "mode" "SI")]) 419 420(define_insn "mips_subu_ph" 421 [(parallel 422 [(set (match_operand:V2HI 0 "register_operand" "=d") 423 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 424 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 425 UNSPEC_SUBU_PH)) 426 (set (reg:CCDSP CCDSP_OU_REGNUM) 427 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_PH))])] 428 "ISA_HAS_DSPR2" 429 "subu.ph\t%0,%z1,%z2" 430 [(set_attr "type" "dspalu") 431 (set_attr "mode" "SI")]) 432 433(define_insn "mips_subu_s_ph" 434 [(parallel 435 [(set (match_operand:V2HI 0 "register_operand" "=d") 436 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 437 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 438 UNSPEC_SUBU_S_PH)) 439 (set (reg:CCDSP CCDSP_OU_REGNUM) 440 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBU_S_PH))])] 441 "ISA_HAS_DSPR2" 442 "subu_s.ph\t%0,%z1,%z2" 443 [(set_attr "type" "dspalusat") 444 (set_attr "mode" "SI")]) 445 446(define_insn "mips_subuh_qb" 447 [(set (match_operand:V4QI 0 "register_operand" "=d") 448 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") 449 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] 450 UNSPEC_SUBUH_QB))] 451 "ISA_HAS_DSPR2" 452 "subuh.qb\t%0,%z1,%z2" 453 [(set_attr "type" "dspalu") 454 (set_attr "mode" "SI")]) 455 456(define_insn "mips_subuh_r_qb" 457 [(set (match_operand:V4QI 0 "register_operand" "=d") 458 (unspec:V4QI [(match_operand:V4QI 1 "reg_or_0_operand" "dYG") 459 (match_operand:V4QI 2 "reg_or_0_operand" "dYG")] 460 UNSPEC_SUBUH_R_QB))] 461 "ISA_HAS_DSPR2" 462 "subuh_r.qb\t%0,%z1,%z2" 463 [(set_attr "type" "dspalu") 464 (set_attr "mode" "SI")]) 465 466(define_insn "mips_addqh_ph" 467 [(set (match_operand:V2HI 0 "register_operand" "=d") 468 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 469 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 470 UNSPEC_ADDQH_PH))] 471 "ISA_HAS_DSPR2" 472 "addqh.ph\t%0,%z1,%z2" 473 [(set_attr "type" "dspalu") 474 (set_attr "mode" "SI")]) 475 476(define_insn "mips_addqh_r_ph" 477 [(set (match_operand:V2HI 0 "register_operand" "=d") 478 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 479 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 480 UNSPEC_ADDQH_R_PH))] 481 "ISA_HAS_DSPR2" 482 "addqh_r.ph\t%0,%z1,%z2" 483 [(set_attr "type" "dspalu") 484 (set_attr "mode" "SI")]) 485 486(define_insn "mips_addqh_w" 487 [(set (match_operand:SI 0 "register_operand" "=d") 488 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") 489 (match_operand:SI 2 "reg_or_0_operand" "dJ")] 490 UNSPEC_ADDQH_W))] 491 "ISA_HAS_DSPR2" 492 "addqh.w\t%0,%z1,%z2" 493 [(set_attr "type" "dspalu") 494 (set_attr "mode" "SI")]) 495 496(define_insn "mips_addqh_r_w" 497 [(set (match_operand:SI 0 "register_operand" "=d") 498 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") 499 (match_operand:SI 2 "reg_or_0_operand" "dJ")] 500 UNSPEC_ADDQH_R_W))] 501 "ISA_HAS_DSPR2" 502 "addqh_r.w\t%0,%z1,%z2" 503 [(set_attr "type" "dspalu") 504 (set_attr "mode" "SI")]) 505 506(define_insn "mips_subqh_ph" 507 [(set (match_operand:V2HI 0 "register_operand" "=d") 508 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 509 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 510 UNSPEC_SUBQH_PH))] 511 "ISA_HAS_DSPR2" 512 "subqh.ph\t%0,%z1,%z2" 513 [(set_attr "type" "dspalu") 514 (set_attr "mode" "SI")]) 515 516(define_insn "mips_subqh_r_ph" 517 [(set (match_operand:V2HI 0 "register_operand" "=d") 518 (unspec:V2HI [(match_operand:V2HI 1 "reg_or_0_operand" "dYG") 519 (match_operand:V2HI 2 "reg_or_0_operand" "dYG")] 520 UNSPEC_SUBQH_R_PH))] 521 "ISA_HAS_DSPR2" 522 "subqh_r.ph\t%0,%z1,%z2" 523 [(set_attr "type" "dspalu") 524 (set_attr "mode" "SI")]) 525 526(define_insn "mips_subqh_w" 527 [(set (match_operand:SI 0 "register_operand" "=d") 528 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") 529 (match_operand:SI 2 "reg_or_0_operand" "dJ")] 530 UNSPEC_SUBQH_W))] 531 "ISA_HAS_DSPR2" 532 "subqh.w\t%0,%z1,%z2" 533 [(set_attr "type" "dspalu") 534 (set_attr "mode" "SI")]) 535 536(define_insn "mips_subqh_r_w" 537 [(set (match_operand:SI 0 "register_operand" "=d") 538 (unspec:SI [(match_operand:SI 1 "reg_or_0_operand" "dJ") 539 (match_operand:SI 2 "reg_or_0_operand" "dJ")] 540 UNSPEC_SUBQH_R_W))] 541 "ISA_HAS_DSPR2" 542 "subqh_r.w\t%0,%z1,%z2" 543 [(set_attr "type" "dspalu") 544 (set_attr "mode" "SI")]) 545 546(define_insn "mips_dpax_w_ph" 547 [(set (match_operand:DI 0 "register_operand" "=a") 548 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 549 (match_operand:V2HI 2 "reg_or_0_operand" "dYG") 550 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 551 UNSPEC_DPAX_W_PH))] 552 "ISA_HAS_DSPR2 && !TARGET_64BIT" 553 "dpax.w.ph\t%q0,%z2,%z3" 554 [(set_attr "type" "dspmac") 555 (set_attr "accum_in" "1") 556 (set_attr "mode" "SI")]) 557 558(define_insn "mips_dpsx_w_ph" 559 [(set (match_operand:DI 0 "register_operand" "=a") 560 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 561 (match_operand:V2HI 2 "reg_or_0_operand" "dYG") 562 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 563 UNSPEC_DPSX_W_PH))] 564 "ISA_HAS_DSPR2 && !TARGET_64BIT" 565 "dpsx.w.ph\t%q0,%z2,%z3" 566 [(set_attr "type" "dspmac") 567 (set_attr "accum_in" "1") 568 (set_attr "mode" "SI")]) 569 570(define_insn "mips_dpaqx_s_w_ph" 571 [(parallel 572 [(set (match_operand:DI 0 "register_operand" "=a") 573 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 574 (match_operand:V2HI 2 "reg_or_0_operand" "dYG") 575 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 576 UNSPEC_DPAQX_S_W_PH)) 577 (set (reg:CCDSP CCDSP_OU_REGNUM) 578 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 579 UNSPEC_DPAQX_S_W_PH))])] 580 "ISA_HAS_DSPR2 && !TARGET_64BIT" 581 "dpaqx_s.w.ph\t%q0,%z2,%z3" 582 [(set_attr "type" "dspmac") 583 (set_attr "accum_in" "1") 584 (set_attr "mode" "SI")]) 585 586(define_insn "mips_dpaqx_sa_w_ph" 587 [(parallel 588 [(set (match_operand:DI 0 "register_operand" "=a") 589 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 590 (match_operand:V2HI 2 "reg_or_0_operand" "dYG") 591 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 592 UNSPEC_DPAQX_SA_W_PH)) 593 (set (reg:CCDSP CCDSP_OU_REGNUM) 594 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 595 UNSPEC_DPAQX_SA_W_PH))])] 596 "ISA_HAS_DSPR2 && !TARGET_64BIT" 597 "dpaqx_sa.w.ph\t%q0,%z2,%z3" 598 [(set_attr "type" "dspmacsat") 599 (set_attr "accum_in" "1") 600 (set_attr "mode" "SI")]) 601 602(define_insn "mips_dpsqx_s_w_ph" 603 [(parallel 604 [(set (match_operand:DI 0 "register_operand" "=a") 605 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 606 (match_operand:V2HI 2 "reg_or_0_operand" "dYG") 607 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 608 UNSPEC_DPSQX_S_W_PH)) 609 (set (reg:CCDSP CCDSP_OU_REGNUM) 610 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 611 UNSPEC_DPSQX_S_W_PH))])] 612 "ISA_HAS_DSPR2 && !TARGET_64BIT" 613 "dpsqx_s.w.ph\t%q0,%z2,%z3" 614 [(set_attr "type" "dspmac") 615 (set_attr "accum_in" "1") 616 (set_attr "mode" "SI")]) 617 618(define_insn "mips_dpsqx_sa_w_ph" 619 [(parallel 620 [(set (match_operand:DI 0 "register_operand" "=a") 621 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 622 (match_operand:V2HI 2 "reg_or_0_operand" "dYG") 623 (match_operand:V2HI 3 "reg_or_0_operand" "dYG")] 624 UNSPEC_DPSQX_SA_W_PH)) 625 (set (reg:CCDSP CCDSP_OU_REGNUM) 626 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 627 UNSPEC_DPSQX_SA_W_PH))])] 628 "ISA_HAS_DSPR2 && !TARGET_64BIT" 629 "dpsqx_sa.w.ph\t%q0,%z2,%z3" 630 [(set_attr "type" "dspmacsat") 631 (set_attr "accum_in" "1") 632 (set_attr "mode" "SI")]) 633