1;; Copyright (C) 2005, 2006, 2007, 2008 Free Software Foundation, Inc. 2;; 3;; This file is part of GCC. 4;; 5;; GCC is free software; you can redistribute it and/or modify 6;; it under the terms of the GNU General Public License as published by 7;; the Free Software Foundation; either version 3, or (at your option) 8;; any later version. 9;; 10;; GCC is distributed in the hope that it will be useful, 11;; but WITHOUT ANY WARRANTY; without even the implied warranty of 12;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13;; GNU General Public License for more details. 14;; 15;; You should have received a copy of the GNU General Public License 16;; along with GCC; see the file COPYING3. If not see 17;; <http://www.gnu.org/licenses/>. 18 19(define_constants 20 [(CCDSP_PO_REGNUM 182) 21 (CCDSP_SC_REGNUM 183) 22 (CCDSP_CA_REGNUM 184) 23 (CCDSP_OU_REGNUM 185) 24 (CCDSP_CC_REGNUM 186) 25 (CCDSP_EF_REGNUM 187)]) 26 27;; This mode iterator allows si, v2hi, v4qi for all possible modes in DSP ASE. 28(define_mode_iterator DSP [(SI "ISA_HAS_DSP") 29 (V2HI "ISA_HAS_DSP") 30 (V4QI "ISA_HAS_DSP")]) 31 32;; This mode iterator allows v2hi, v4qi for vector/SIMD data. 33(define_mode_iterator DSPV [(V2HI "ISA_HAS_DSP") 34 (V4QI "ISA_HAS_DSP")]) 35 36;; This mode iterator allows si, v2hi for Q31 and V2Q15 fixed-point data. 37(define_mode_iterator DSPQ [(SI "ISA_HAS_DSP") 38 (V2HI "ISA_HAS_DSP")]) 39 40;; DSP instructions use q for fixed-point data, and u for integer in the infix. 41(define_mode_attr dspfmt1 [(SI "q") (V2HI "q") (V4QI "u")]) 42 43;; DSP instructions use nothing for fixed-point data, and u for integer in 44;; the infix. 45(define_mode_attr dspfmt1_1 [(SI "") (V2HI "") (V4QI "u")]) 46 47;; DSP instructions use w, ph, qb in the postfix. 48(define_mode_attr dspfmt2 [(SI "w") (V2HI "ph") (V4QI "qb")]) 49 50;; DSP shift masks for SI, V2HI, V4QI. 51(define_mode_attr dspshift_mask [(SI "0x1f") (V2HI "0xf") (V4QI "0x7")]) 52 53;; MIPS DSP ASE Revision 0.98 3/24/2005 54;; Table 2-1. MIPS DSP ASE Instructions: Arithmetic 55;; ADDQ* 56(define_insn "add<DSPV:mode>3" 57 [(parallel 58 [(set (match_operand:DSPV 0 "register_operand" "=d") 59 (plus:DSPV (match_operand:DSPV 1 "register_operand" "d") 60 (match_operand:DSPV 2 "register_operand" "d"))) 61 (set (reg:CCDSP CCDSP_OU_REGNUM) 62 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ))])] 63 "" 64 "add<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 65 [(set_attr "type" "arith") 66 (set_attr "mode" "SI")]) 67 68(define_insn "mips_add<DSP:dspfmt1>_s_<DSP:dspfmt2>" 69 [(parallel 70 [(set (match_operand:DSP 0 "register_operand" "=d") 71 (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 72 (match_operand:DSP 2 "register_operand" "d")] 73 UNSPEC_ADDQ_S)) 74 (set (reg:CCDSP CCDSP_OU_REGNUM) 75 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDQ_S))])] 76 "" 77 "add<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 78 [(set_attr "type" "arith") 79 (set_attr "mode" "SI")]) 80 81;; SUBQ* 82(define_insn "sub<DSPV:mode>3" 83 [(parallel 84 [(set (match_operand:DSPV 0 "register_operand" "=d") 85 (minus:DSPV (match_operand:DSPV 1 "register_operand" "d") 86 (match_operand:DSPV 2 "register_operand" "d"))) 87 (set (reg:CCDSP CCDSP_OU_REGNUM) 88 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ))])] 89 "ISA_HAS_DSP" 90 "sub<DSPV:dspfmt1>.<DSPV:dspfmt2>\t%0,%1,%2" 91 [(set_attr "type" "arith") 92 (set_attr "mode" "SI")]) 93 94(define_insn "mips_sub<DSP:dspfmt1>_s_<DSP:dspfmt2>" 95 [(parallel 96 [(set (match_operand:DSP 0 "register_operand" "=d") 97 (unspec:DSP [(match_operand:DSP 1 "register_operand" "d") 98 (match_operand:DSP 2 "register_operand" "d")] 99 UNSPEC_SUBQ_S)) 100 (set (reg:CCDSP CCDSP_OU_REGNUM) 101 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SUBQ_S))])] 102 "ISA_HAS_DSP" 103 "sub<DSP:dspfmt1>_s.<DSP:dspfmt2>\t%0,%1,%2" 104 [(set_attr "type" "arith") 105 (set_attr "mode" "SI")]) 106 107;; ADDSC 108(define_insn "mips_addsc" 109 [(parallel 110 [(set (match_operand:SI 0 "register_operand" "=d") 111 (unspec:SI [(match_operand:SI 1 "register_operand" "d") 112 (match_operand:SI 2 "register_operand" "d")] 113 UNSPEC_ADDSC)) 114 (set (reg:CCDSP CCDSP_CA_REGNUM) 115 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDSC))])] 116 "ISA_HAS_DSP" 117 "addsc\t%0,%1,%2" 118 [(set_attr "type" "arith") 119 (set_attr "mode" "SI")]) 120 121;; ADDWC 122(define_insn "mips_addwc" 123 [(parallel 124 [(set (match_operand:SI 0 "register_operand" "=d") 125 (unspec:SI [(match_operand:SI 1 "register_operand" "d") 126 (match_operand:SI 2 "register_operand" "d") 127 (reg:CCDSP CCDSP_CA_REGNUM)] 128 UNSPEC_ADDWC)) 129 (set (reg:CCDSP CCDSP_OU_REGNUM) 130 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_ADDWC))])] 131 "ISA_HAS_DSP" 132 "addwc\t%0,%1,%2" 133 [(set_attr "type" "arith") 134 (set_attr "mode" "SI")]) 135 136;; MODSUB 137(define_insn "mips_modsub" 138 [(set (match_operand:SI 0 "register_operand" "=d") 139 (unspec:SI [(match_operand:SI 1 "register_operand" "d") 140 (match_operand:SI 2 "register_operand" "d")] 141 UNSPEC_MODSUB))] 142 "ISA_HAS_DSP" 143 "modsub\t%0,%1,%2" 144 [(set_attr "type" "arith") 145 (set_attr "mode" "SI")]) 146 147;; RADDU* 148(define_insn "mips_raddu_w_qb" 149 [(set (match_operand:SI 0 "register_operand" "=d") 150 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d")] 151 UNSPEC_RADDU_W_QB))] 152 "ISA_HAS_DSP" 153 "raddu.w.qb\t%0,%1" 154 [(set_attr "type" "arith") 155 (set_attr "mode" "SI")]) 156 157;; ABSQ* 158(define_insn "mips_absq_s_<DSPQ:dspfmt2>" 159 [(parallel 160 [(set (match_operand:DSPQ 0 "register_operand" "=d") 161 (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d")] 162 UNSPEC_ABSQ_S)) 163 (set (reg:CCDSP CCDSP_OU_REGNUM) 164 (unspec:CCDSP [(match_dup 1)] UNSPEC_ABSQ_S))])] 165 "ISA_HAS_DSP" 166 "absq_s.<DSPQ:dspfmt2>\t%0,%1" 167 [(set_attr "type" "arith") 168 (set_attr "mode" "SI")]) 169 170;; PRECRQ* 171(define_insn "mips_precrq_qb_ph" 172 [(set (match_operand:V4QI 0 "register_operand" "=d") 173 (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 174 (match_operand:V2HI 2 "register_operand" "d")] 175 UNSPEC_PRECRQ_QB_PH))] 176 "ISA_HAS_DSP" 177 "precrq.qb.ph\t%0,%1,%2" 178 [(set_attr "type" "arith") 179 (set_attr "mode" "SI")]) 180 181(define_insn "mips_precrq_ph_w" 182 [(set (match_operand:V2HI 0 "register_operand" "=d") 183 (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 184 (match_operand:SI 2 "register_operand" "d")] 185 UNSPEC_PRECRQ_PH_W))] 186 "ISA_HAS_DSP" 187 "precrq.ph.w\t%0,%1,%2" 188 [(set_attr "type" "arith") 189 (set_attr "mode" "SI")]) 190 191(define_insn "mips_precrq_rs_ph_w" 192 [(parallel 193 [(set (match_operand:V2HI 0 "register_operand" "=d") 194 (unspec:V2HI [(match_operand:SI 1 "register_operand" "d") 195 (match_operand:SI 2 "register_operand" "d")] 196 UNSPEC_PRECRQ_RS_PH_W)) 197 (set (reg:CCDSP CCDSP_OU_REGNUM) 198 (unspec:CCDSP [(match_dup 1) (match_dup 2)] 199 UNSPEC_PRECRQ_RS_PH_W))])] 200 "ISA_HAS_DSP" 201 "precrq_rs.ph.w\t%0,%1,%2" 202 [(set_attr "type" "arith") 203 (set_attr "mode" "SI")]) 204 205;; PRECRQU* 206(define_insn "mips_precrqu_s_qb_ph" 207 [(parallel 208 [(set (match_operand:V4QI 0 "register_operand" "=d") 209 (unspec:V4QI [(match_operand:V2HI 1 "register_operand" "d") 210 (match_operand:V2HI 2 "register_operand" "d")] 211 UNSPEC_PRECRQU_S_QB_PH)) 212 (set (reg:CCDSP CCDSP_OU_REGNUM) 213 (unspec:CCDSP [(match_dup 1) (match_dup 2)] 214 UNSPEC_PRECRQU_S_QB_PH))])] 215 "ISA_HAS_DSP" 216 "precrqu_s.qb.ph\t%0,%1,%2" 217 [(set_attr "type" "arith") 218 (set_attr "mode" "SI")]) 219 220;; PRECEQ* 221(define_insn "mips_preceq_w_phl" 222 [(set (match_operand:SI 0 "register_operand" "=d") 223 (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 224 UNSPEC_PRECEQ_W_PHL))] 225 "ISA_HAS_DSP" 226 "preceq.w.phl\t%0,%1" 227 [(set_attr "type" "arith") 228 (set_attr "mode" "SI")]) 229 230(define_insn "mips_preceq_w_phr" 231 [(set (match_operand:SI 0 "register_operand" "=d") 232 (unspec:SI [(match_operand:V2HI 1 "register_operand" "d")] 233 UNSPEC_PRECEQ_W_PHR))] 234 "ISA_HAS_DSP" 235 "preceq.w.phr\t%0,%1" 236 [(set_attr "type" "arith") 237 (set_attr "mode" "SI")]) 238 239;; PRECEQU* 240(define_insn "mips_precequ_ph_qbl" 241 [(set (match_operand:V2HI 0 "register_operand" "=d") 242 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 243 UNSPEC_PRECEQU_PH_QBL))] 244 "ISA_HAS_DSP" 245 "precequ.ph.qbl\t%0,%1" 246 [(set_attr "type" "arith") 247 (set_attr "mode" "SI")]) 248 249(define_insn "mips_precequ_ph_qbr" 250 [(set (match_operand:V2HI 0 "register_operand" "=d") 251 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 252 UNSPEC_PRECEQU_PH_QBR))] 253 "ISA_HAS_DSP" 254 "precequ.ph.qbr\t%0,%1" 255 [(set_attr "type" "arith") 256 (set_attr "mode" "SI")]) 257 258(define_insn "mips_precequ_ph_qbla" 259 [(set (match_operand:V2HI 0 "register_operand" "=d") 260 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 261 UNSPEC_PRECEQU_PH_QBLA))] 262 "ISA_HAS_DSP" 263 "precequ.ph.qbla\t%0,%1" 264 [(set_attr "type" "arith") 265 (set_attr "mode" "SI")]) 266 267(define_insn "mips_precequ_ph_qbra" 268 [(set (match_operand:V2HI 0 "register_operand" "=d") 269 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 270 UNSPEC_PRECEQU_PH_QBRA))] 271 "ISA_HAS_DSP" 272 "precequ.ph.qbra\t%0,%1" 273 [(set_attr "type" "arith") 274 (set_attr "mode" "SI")]) 275 276;; PRECEU* 277(define_insn "mips_preceu_ph_qbl" 278 [(set (match_operand:V2HI 0 "register_operand" "=d") 279 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 280 UNSPEC_PRECEU_PH_QBL))] 281 "ISA_HAS_DSP" 282 "preceu.ph.qbl\t%0,%1" 283 [(set_attr "type" "arith") 284 (set_attr "mode" "SI")]) 285 286(define_insn "mips_preceu_ph_qbr" 287 [(set (match_operand:V2HI 0 "register_operand" "=d") 288 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 289 UNSPEC_PRECEU_PH_QBR))] 290 "ISA_HAS_DSP" 291 "preceu.ph.qbr\t%0,%1" 292 [(set_attr "type" "arith") 293 (set_attr "mode" "SI")]) 294 295(define_insn "mips_preceu_ph_qbla" 296 [(set (match_operand:V2HI 0 "register_operand" "=d") 297 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 298 UNSPEC_PRECEU_PH_QBLA))] 299 "ISA_HAS_DSP" 300 "preceu.ph.qbla\t%0,%1" 301 [(set_attr "type" "arith") 302 (set_attr "mode" "SI")]) 303 304(define_insn "mips_preceu_ph_qbra" 305 [(set (match_operand:V2HI 0 "register_operand" "=d") 306 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d")] 307 UNSPEC_PRECEU_PH_QBRA))] 308 "ISA_HAS_DSP" 309 "preceu.ph.qbra\t%0,%1" 310 [(set_attr "type" "arith") 311 (set_attr "mode" "SI")]) 312 313;; Table 2-2. MIPS DSP ASE Instructions: Shift 314;; SHLL* 315(define_insn "mips_shll_<DSPV:dspfmt2>" 316 [(parallel 317 [(set (match_operand:DSPV 0 "register_operand" "=d,d") 318 (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d,d") 319 (match_operand:SI 2 "arith_operand" "I,d")] 320 UNSPEC_SHLL)) 321 (set (reg:CCDSP CCDSP_OU_REGNUM) 322 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL))])] 323 "ISA_HAS_DSP" 324{ 325 if (which_alternative == 0) 326 { 327 if (INTVAL (operands[2]) 328 & ~(unsigned HOST_WIDE_INT) <DSPV:dspshift_mask>) 329 operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPV:dspshift_mask>); 330 return "shll.<DSPV:dspfmt2>\t%0,%1,%2"; 331 } 332 return "shllv.<DSPV:dspfmt2>\t%0,%1,%2"; 333} 334 [(set_attr "type" "shift") 335 (set_attr "mode" "SI")]) 336 337(define_insn "mips_shll_s_<DSPQ:dspfmt2>" 338 [(parallel 339 [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 340 (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 341 (match_operand:SI 2 "arith_operand" "I,d")] 342 UNSPEC_SHLL_S)) 343 (set (reg:CCDSP CCDSP_OU_REGNUM) 344 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_SHLL_S))])] 345 "ISA_HAS_DSP" 346{ 347 if (which_alternative == 0) 348 { 349 if (INTVAL (operands[2]) 350 & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 351 operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 352 return "shll_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 353 } 354 return "shllv_s.<DSPQ:dspfmt2>\t%0,%1,%2"; 355} 356 [(set_attr "type" "shift") 357 (set_attr "mode" "SI")]) 358 359;; SHRL* 360(define_insn "mips_shrl_qb" 361 [(set (match_operand:V4QI 0 "register_operand" "=d,d") 362 (unspec:V4QI [(match_operand:V4QI 1 "register_operand" "d,d") 363 (match_operand:SI 2 "arith_operand" "I,d")] 364 UNSPEC_SHRL_QB))] 365 "ISA_HAS_DSP" 366{ 367 if (which_alternative == 0) 368 { 369 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x7) 370 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x7); 371 return "shrl.qb\t%0,%1,%2"; 372 } 373 return "shrlv.qb\t%0,%1,%2"; 374} 375 [(set_attr "type" "shift") 376 (set_attr "mode" "SI")]) 377 378;; SHRA* 379(define_insn "mips_shra_ph" 380 [(set (match_operand:V2HI 0 "register_operand" "=d,d") 381 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d,d") 382 (match_operand:SI 2 "arith_operand" "I,d")] 383 UNSPEC_SHRA_PH))] 384 "ISA_HAS_DSP" 385{ 386 if (which_alternative == 0) 387 { 388 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0xf) 389 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xf); 390 return "shra.ph\t%0,%1,%2"; 391 } 392 return "shrav.ph\t%0,%1,%2"; 393} 394 [(set_attr "type" "shift") 395 (set_attr "mode" "SI")]) 396 397(define_insn "mips_shra_r_<DSPQ:dspfmt2>" 398 [(set (match_operand:DSPQ 0 "register_operand" "=d,d") 399 (unspec:DSPQ [(match_operand:DSPQ 1 "register_operand" "d,d") 400 (match_operand:SI 2 "arith_operand" "I,d")] 401 UNSPEC_SHRA_R))] 402 "ISA_HAS_DSP" 403{ 404 if (which_alternative == 0) 405 { 406 if (INTVAL (operands[2]) 407 & ~(unsigned HOST_WIDE_INT) <DSPQ:dspshift_mask>) 408 operands[2] = GEN_INT (INTVAL (operands[2]) & <DSPQ:dspshift_mask>); 409 return "shra_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 410 } 411 return "shrav_r.<DSPQ:dspfmt2>\t%0,%1,%2"; 412} 413 [(set_attr "type" "shift") 414 (set_attr "mode" "SI")]) 415 416;; Table 2-3. MIPS DSP ASE Instructions: Multiply 417;; MULEU* 418(define_insn "mips_muleu_s_ph_qbl" 419 [(parallel 420 [(set (match_operand:V2HI 0 "register_operand" "=d") 421 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 422 (match_operand:V2HI 2 "register_operand" "d")] 423 UNSPEC_MULEU_S_PH_QBL)) 424 (set (reg:CCDSP CCDSP_OU_REGNUM) 425 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBL)) 426 (clobber (match_scratch:DI 3 "=x"))])] 427 "ISA_HAS_DSP" 428 "muleu_s.ph.qbl\t%0,%1,%2" 429 [(set_attr "type" "imul3") 430 (set_attr "mode" "SI")]) 431 432(define_insn "mips_muleu_s_ph_qbr" 433 [(parallel 434 [(set (match_operand:V2HI 0 "register_operand" "=d") 435 (unspec:V2HI [(match_operand:V4QI 1 "register_operand" "d") 436 (match_operand:V2HI 2 "register_operand" "d")] 437 UNSPEC_MULEU_S_PH_QBR)) 438 (set (reg:CCDSP CCDSP_OU_REGNUM) 439 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEU_S_PH_QBR)) 440 (clobber (match_scratch:DI 3 "=x"))])] 441 "ISA_HAS_DSP" 442 "muleu_s.ph.qbr\t%0,%1,%2" 443 [(set_attr "type" "imul3") 444 (set_attr "mode" "SI")]) 445 446;; MULQ* 447(define_insn "mips_mulq_rs_ph" 448 [(parallel 449 [(set (match_operand:V2HI 0 "register_operand" "=d") 450 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 451 (match_operand:V2HI 2 "register_operand" "d")] 452 UNSPEC_MULQ_RS_PH)) 453 (set (reg:CCDSP CCDSP_OU_REGNUM) 454 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULQ_RS_PH)) 455 (clobber (match_scratch:DI 3 "=x"))])] 456 "ISA_HAS_DSP" 457 "mulq_rs.ph\t%0,%1,%2" 458 [(set_attr "type" "imul3") 459 (set_attr "mode" "SI")]) 460 461;; MULEQ* 462(define_insn "mips_muleq_s_w_phl" 463 [(parallel 464 [(set (match_operand:SI 0 "register_operand" "=d") 465 (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 466 (match_operand:V2HI 2 "register_operand" "d")] 467 UNSPEC_MULEQ_S_W_PHL)) 468 (set (reg:CCDSP CCDSP_OU_REGNUM) 469 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHL)) 470 (clobber (match_scratch:DI 3 "=x"))])] 471 "ISA_HAS_DSP" 472 "muleq_s.w.phl\t%0,%1,%2" 473 [(set_attr "type" "imul3") 474 (set_attr "mode" "SI")]) 475 476(define_insn "mips_muleq_s_w_phr" 477 [(parallel 478 [(set (match_operand:SI 0 "register_operand" "=d") 479 (unspec:SI [(match_operand:V2HI 1 "register_operand" "d") 480 (match_operand:V2HI 2 "register_operand" "d")] 481 UNSPEC_MULEQ_S_W_PHR)) 482 (set (reg:CCDSP CCDSP_OU_REGNUM) 483 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_MULEQ_S_W_PHR)) 484 (clobber (match_scratch:DI 3 "=x"))])] 485 "ISA_HAS_DSP" 486 "muleq_s.w.phr\t%0,%1,%2" 487 [(set_attr "type" "imul3") 488 (set_attr "mode" "SI")]) 489 490;; DPAU* 491(define_insn "mips_dpau_h_qbl" 492 [(set (match_operand:DI 0 "register_operand" "=a") 493 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 494 (match_operand:V4QI 2 "register_operand" "d") 495 (match_operand:V4QI 3 "register_operand" "d")] 496 UNSPEC_DPAU_H_QBL))] 497 "ISA_HAS_DSP && !TARGET_64BIT" 498 "dpau.h.qbl\t%q0,%2,%3" 499 [(set_attr "type" "imadd") 500 (set_attr "mode" "SI")]) 501 502(define_insn "mips_dpau_h_qbr" 503 [(set (match_operand:DI 0 "register_operand" "=a") 504 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 505 (match_operand:V4QI 2 "register_operand" "d") 506 (match_operand:V4QI 3 "register_operand" "d")] 507 UNSPEC_DPAU_H_QBR))] 508 "ISA_HAS_DSP && !TARGET_64BIT" 509 "dpau.h.qbr\t%q0,%2,%3" 510 [(set_attr "type" "imadd") 511 (set_attr "mode" "SI")]) 512 513;; DPSU* 514(define_insn "mips_dpsu_h_qbl" 515 [(set (match_operand:DI 0 "register_operand" "=a") 516 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 517 (match_operand:V4QI 2 "register_operand" "d") 518 (match_operand:V4QI 3 "register_operand" "d")] 519 UNSPEC_DPSU_H_QBL))] 520 "ISA_HAS_DSP && !TARGET_64BIT" 521 "dpsu.h.qbl\t%q0,%2,%3" 522 [(set_attr "type" "imadd") 523 (set_attr "mode" "SI")]) 524 525(define_insn "mips_dpsu_h_qbr" 526 [(set (match_operand:DI 0 "register_operand" "=a") 527 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 528 (match_operand:V4QI 2 "register_operand" "d") 529 (match_operand:V4QI 3 "register_operand" "d")] 530 UNSPEC_DPSU_H_QBR))] 531 "ISA_HAS_DSP && !TARGET_64BIT" 532 "dpsu.h.qbr\t%q0,%2,%3" 533 [(set_attr "type" "imadd") 534 (set_attr "mode" "SI")]) 535 536;; DPAQ* 537(define_insn "mips_dpaq_s_w_ph" 538 [(parallel 539 [(set (match_operand:DI 0 "register_operand" "=a") 540 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 541 (match_operand:V2HI 2 "register_operand" "d") 542 (match_operand:V2HI 3 "register_operand" "d")] 543 UNSPEC_DPAQ_S_W_PH)) 544 (set (reg:CCDSP CCDSP_OU_REGNUM) 545 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 546 UNSPEC_DPAQ_S_W_PH))])] 547 "ISA_HAS_DSP && !TARGET_64BIT" 548 "dpaq_s.w.ph\t%q0,%2,%3" 549 [(set_attr "type" "imadd") 550 (set_attr "mode" "SI")]) 551 552;; DPSQ* 553(define_insn "mips_dpsq_s_w_ph" 554 [(parallel 555 [(set (match_operand:DI 0 "register_operand" "=a") 556 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 557 (match_operand:V2HI 2 "register_operand" "d") 558 (match_operand:V2HI 3 "register_operand" "d")] 559 UNSPEC_DPSQ_S_W_PH)) 560 (set (reg:CCDSP CCDSP_OU_REGNUM) 561 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 562 UNSPEC_DPSQ_S_W_PH))])] 563 "ISA_HAS_DSP && !TARGET_64BIT" 564 "dpsq_s.w.ph\t%q0,%2,%3" 565 [(set_attr "type" "imadd") 566 (set_attr "mode" "SI")]) 567 568;; MULSAQ* 569(define_insn "mips_mulsaq_s_w_ph" 570 [(parallel 571 [(set (match_operand:DI 0 "register_operand" "=a") 572 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 573 (match_operand:V2HI 2 "register_operand" "d") 574 (match_operand:V2HI 3 "register_operand" "d")] 575 UNSPEC_MULSAQ_S_W_PH)) 576 (set (reg:CCDSP CCDSP_OU_REGNUM) 577 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 578 UNSPEC_MULSAQ_S_W_PH))])] 579 "ISA_HAS_DSP && !TARGET_64BIT" 580 "mulsaq_s.w.ph\t%q0,%2,%3" 581 [(set_attr "type" "imadd") 582 (set_attr "mode" "SI")]) 583 584;; DPAQ* 585(define_insn "mips_dpaq_sa_l_w" 586 [(parallel 587 [(set (match_operand:DI 0 "register_operand" "=a") 588 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 589 (match_operand:SI 2 "register_operand" "d") 590 (match_operand:SI 3 "register_operand" "d")] 591 UNSPEC_DPAQ_SA_L_W)) 592 (set (reg:CCDSP CCDSP_OU_REGNUM) 593 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 594 UNSPEC_DPAQ_SA_L_W))])] 595 "ISA_HAS_DSP && !TARGET_64BIT" 596 "dpaq_sa.l.w\t%q0,%2,%3" 597 [(set_attr "type" "imadd") 598 (set_attr "mode" "SI")]) 599 600;; DPSQ* 601(define_insn "mips_dpsq_sa_l_w" 602 [(parallel 603 [(set (match_operand:DI 0 "register_operand" "=a") 604 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 605 (match_operand:SI 2 "register_operand" "d") 606 (match_operand:SI 3 "register_operand" "d")] 607 UNSPEC_DPSQ_SA_L_W)) 608 (set (reg:CCDSP CCDSP_OU_REGNUM) 609 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 610 UNSPEC_DPSQ_SA_L_W))])] 611 "ISA_HAS_DSP && !TARGET_64BIT" 612 "dpsq_sa.l.w\t%q0,%2,%3" 613 [(set_attr "type" "imadd") 614 (set_attr "mode" "SI")]) 615 616;; MAQ* 617(define_insn "mips_maq_s_w_phl" 618 [(parallel 619 [(set (match_operand:DI 0 "register_operand" "=a") 620 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 621 (match_operand:V2HI 2 "register_operand" "d") 622 (match_operand:V2HI 3 "register_operand" "d")] 623 UNSPEC_MAQ_S_W_PHL)) 624 (set (reg:CCDSP CCDSP_OU_REGNUM) 625 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 626 UNSPEC_MAQ_S_W_PHL))])] 627 "ISA_HAS_DSP && !TARGET_64BIT" 628 "maq_s.w.phl\t%q0,%2,%3" 629 [(set_attr "type" "imadd") 630 (set_attr "mode" "SI")]) 631 632(define_insn "mips_maq_s_w_phr" 633 [(parallel 634 [(set (match_operand:DI 0 "register_operand" "=a") 635 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 636 (match_operand:V2HI 2 "register_operand" "d") 637 (match_operand:V2HI 3 "register_operand" "d")] 638 UNSPEC_MAQ_S_W_PHR)) 639 (set (reg:CCDSP CCDSP_OU_REGNUM) 640 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 641 UNSPEC_MAQ_S_W_PHR))])] 642 "ISA_HAS_DSP && !TARGET_64BIT" 643 "maq_s.w.phr\t%q0,%2,%3" 644 [(set_attr "type" "imadd") 645 (set_attr "mode" "SI")]) 646 647;; MAQ_SA* 648(define_insn "mips_maq_sa_w_phl" 649 [(parallel 650 [(set (match_operand:DI 0 "register_operand" "=a") 651 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 652 (match_operand:V2HI 2 "register_operand" "d") 653 (match_operand:V2HI 3 "register_operand" "d")] 654 UNSPEC_MAQ_SA_W_PHL)) 655 (set (reg:CCDSP CCDSP_OU_REGNUM) 656 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 657 UNSPEC_MAQ_SA_W_PHL))])] 658 "ISA_HAS_DSP && !TARGET_64BIT" 659 "maq_sa.w.phl\t%q0,%2,%3" 660 [(set_attr "type" "imadd") 661 (set_attr "mode" "SI")]) 662 663(define_insn "mips_maq_sa_w_phr" 664 [(parallel 665 [(set (match_operand:DI 0 "register_operand" "=a") 666 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 667 (match_operand:V2HI 2 "register_operand" "d") 668 (match_operand:V2HI 3 "register_operand" "d")] 669 UNSPEC_MAQ_SA_W_PHR)) 670 (set (reg:CCDSP CCDSP_OU_REGNUM) 671 (unspec:CCDSP [(match_dup 1) (match_dup 2) (match_dup 3)] 672 UNSPEC_MAQ_SA_W_PHR))])] 673 "ISA_HAS_DSP && !TARGET_64BIT" 674 "maq_sa.w.phr\t%q0,%2,%3" 675 [(set_attr "type" "imadd") 676 (set_attr "mode" "SI")]) 677 678;; Table 2-4. MIPS DSP ASE Instructions: General Bit/Manipulation 679;; BITREV 680(define_insn "mips_bitrev" 681 [(set (match_operand:SI 0 "register_operand" "=d") 682 (unspec:SI [(match_operand:SI 1 "register_operand" "d")] 683 UNSPEC_BITREV))] 684 "ISA_HAS_DSP" 685 "bitrev\t%0,%1" 686 [(set_attr "type" "arith") 687 (set_attr "mode" "SI")]) 688 689;; INSV 690(define_insn "mips_insv" 691 [(set (match_operand:SI 0 "register_operand" "=d") 692 (unspec:SI [(match_operand:SI 1 "register_operand" "0") 693 (match_operand:SI 2 "register_operand" "d") 694 (reg:CCDSP CCDSP_SC_REGNUM) 695 (reg:CCDSP CCDSP_PO_REGNUM)] 696 UNSPEC_INSV))] 697 "ISA_HAS_DSP" 698 "insv\t%0,%2" 699 [(set_attr "type" "arith") 700 (set_attr "mode" "SI")]) 701 702;; REPL* 703(define_insn "mips_repl_qb" 704 [(set (match_operand:V4QI 0 "register_operand" "=d,d") 705 (unspec:V4QI [(match_operand:SI 1 "arith_operand" "I,d")] 706 UNSPEC_REPL_QB))] 707 "ISA_HAS_DSP" 708{ 709 if (which_alternative == 0) 710 { 711 if (INTVAL (operands[1]) & ~(unsigned HOST_WIDE_INT) 0xff) 712 operands[1] = GEN_INT (INTVAL (operands[1]) & 0xff); 713 return "repl.qb\t%0,%1"; 714 } 715 return "replv.qb\t%0,%1"; 716} 717 [(set_attr "type" "arith") 718 (set_attr "mode" "SI")]) 719 720(define_insn "mips_repl_ph" 721 [(set (match_operand:V2HI 0 "register_operand" "=d,d") 722 (unspec:V2HI [(match_operand:SI 1 "reg_imm10_operand" "YB,d")] 723 UNSPEC_REPL_PH))] 724 "ISA_HAS_DSP" 725 "@ 726 repl.ph\t%0,%1 727 replv.ph\t%0,%1" 728 [(set_attr "type" "arith") 729 (set_attr "mode" "SI")]) 730 731;; Table 2-5. MIPS DSP ASE Instructions: Compare-Pick 732;; CMPU.* CMP.* 733(define_insn "mips_cmp<DSPV:dspfmt1_1>_eq_<DSPV:dspfmt2>" 734 [(set (reg:CCDSP CCDSP_CC_REGNUM) 735 (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 736 (match_operand:DSPV 1 "register_operand" "d") 737 (reg:CCDSP CCDSP_CC_REGNUM)] 738 UNSPEC_CMP_EQ))] 739 "ISA_HAS_DSP" 740 "cmp<DSPV:dspfmt1_1>.eq.<DSPV:dspfmt2>\t%0,%1" 741 [(set_attr "type" "arith") 742 (set_attr "mode" "SI")]) 743 744(define_insn "mips_cmp<DSPV:dspfmt1_1>_lt_<DSPV:dspfmt2>" 745 [(set (reg:CCDSP CCDSP_CC_REGNUM) 746 (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 747 (match_operand:DSPV 1 "register_operand" "d") 748 (reg:CCDSP CCDSP_CC_REGNUM)] 749 UNSPEC_CMP_LT))] 750 "ISA_HAS_DSP" 751 "cmp<DSPV:dspfmt1_1>.lt.<DSPV:dspfmt2>\t%0,%1" 752 [(set_attr "type" "arith") 753 (set_attr "mode" "SI")]) 754 755(define_insn "mips_cmp<DSPV:dspfmt1_1>_le_<DSPV:dspfmt2>" 756 [(set (reg:CCDSP CCDSP_CC_REGNUM) 757 (unspec:CCDSP [(match_operand:DSPV 0 "register_operand" "d") 758 (match_operand:DSPV 1 "register_operand" "d") 759 (reg:CCDSP CCDSP_CC_REGNUM)] 760 UNSPEC_CMP_LE))] 761 "ISA_HAS_DSP" 762 "cmp<DSPV:dspfmt1_1>.le.<DSPV:dspfmt2>\t%0,%1" 763 [(set_attr "type" "arith") 764 (set_attr "mode" "SI")]) 765 766(define_insn "mips_cmpgu_eq_qb" 767 [(set (match_operand:SI 0 "register_operand" "=d") 768 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 769 (match_operand:V4QI 2 "register_operand" "d")] 770 UNSPEC_CMPGU_EQ_QB))] 771 "ISA_HAS_DSP" 772 "cmpgu.eq.qb\t%0,%1,%2" 773 [(set_attr "type" "arith") 774 (set_attr "mode" "SI")]) 775 776(define_insn "mips_cmpgu_lt_qb" 777 [(set (match_operand:SI 0 "register_operand" "=d") 778 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 779 (match_operand:V4QI 2 "register_operand" "d")] 780 UNSPEC_CMPGU_LT_QB))] 781 "ISA_HAS_DSP" 782 "cmpgu.lt.qb\t%0,%1,%2" 783 [(set_attr "type" "arith") 784 (set_attr "mode" "SI")]) 785 786(define_insn "mips_cmpgu_le_qb" 787 [(set (match_operand:SI 0 "register_operand" "=d") 788 (unspec:SI [(match_operand:V4QI 1 "register_operand" "d") 789 (match_operand:V4QI 2 "register_operand" "d")] 790 UNSPEC_CMPGU_LE_QB))] 791 "ISA_HAS_DSP" 792 "cmpgu.le.qb\t%0,%1,%2" 793 [(set_attr "type" "arith") 794 (set_attr "mode" "SI")]) 795 796;; PICK* 797(define_insn "mips_pick_<DSPV:dspfmt2>" 798 [(set (match_operand:DSPV 0 "register_operand" "=d") 799 (unspec:DSPV [(match_operand:DSPV 1 "register_operand" "d") 800 (match_operand:DSPV 2 "register_operand" "d") 801 (reg:CCDSP CCDSP_CC_REGNUM)] 802 UNSPEC_PICK))] 803 "ISA_HAS_DSP" 804 "pick.<DSPV:dspfmt2>\t%0,%1,%2" 805 [(set_attr "type" "arith") 806 (set_attr "mode" "SI")]) 807 808;; PACKRL* 809(define_insn "mips_packrl_ph" 810 [(set (match_operand:V2HI 0 "register_operand" "=d") 811 (unspec:V2HI [(match_operand:V2HI 1 "register_operand" "d") 812 (match_operand:V2HI 2 "register_operand" "d")] 813 UNSPEC_PACKRL_PH))] 814 "ISA_HAS_DSP" 815 "packrl.ph\t%0,%1,%2" 816 [(set_attr "type" "arith") 817 (set_attr "mode" "SI")]) 818 819;; Table 2-6. MIPS DSP ASE Instructions: Accumulator and DSPControl Access 820;; EXTR* 821(define_insn "mips_extr_w" 822 [(parallel 823 [(set (match_operand:SI 0 "register_operand" "=d,d") 824 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 825 (match_operand:SI 2 "arith_operand" "I,d")] 826 UNSPEC_EXTR_W)) 827 (set (reg:CCDSP CCDSP_OU_REGNUM) 828 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_W))])] 829 "ISA_HAS_DSP && !TARGET_64BIT" 830{ 831 if (which_alternative == 0) 832 { 833 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 834 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 835 return "extr.w\t%0,%q1,%2"; 836 } 837 return "extrv.w\t%0,%q1,%2"; 838} 839 [(set_attr "type" "mfhilo") 840 (set_attr "mode" "SI")]) 841 842(define_insn "mips_extr_r_w" 843 [(parallel 844 [(set (match_operand:SI 0 "register_operand" "=d,d") 845 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 846 (match_operand:SI 2 "arith_operand" "I,d")] 847 UNSPEC_EXTR_R_W)) 848 (set (reg:CCDSP CCDSP_OU_REGNUM) 849 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_R_W))])] 850 "ISA_HAS_DSP && !TARGET_64BIT" 851{ 852 if (which_alternative == 0) 853 { 854 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 855 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 856 return "extr_r.w\t%0,%q1,%2"; 857 } 858 return "extrv_r.w\t%0,%q1,%2"; 859} 860 [(set_attr "type" "mfhilo") 861 (set_attr "mode" "SI")]) 862 863(define_insn "mips_extr_rs_w" 864 [(parallel 865 [(set (match_operand:SI 0 "register_operand" "=d,d") 866 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 867 (match_operand:SI 2 "arith_operand" "I,d")] 868 UNSPEC_EXTR_RS_W)) 869 (set (reg:CCDSP CCDSP_OU_REGNUM) 870 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_RS_W))])] 871 "ISA_HAS_DSP && !TARGET_64BIT" 872{ 873 if (which_alternative == 0) 874 { 875 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 876 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 877 return "extr_rs.w\t%0,%q1,%2"; 878 } 879 return "extrv_rs.w\t%0,%q1,%2"; 880} 881 [(set_attr "type" "mfhilo") 882 (set_attr "mode" "SI")]) 883 884;; EXTR*_S.H 885(define_insn "mips_extr_s_h" 886 [(parallel 887 [(set (match_operand:SI 0 "register_operand" "=d,d") 888 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 889 (match_operand:SI 2 "arith_operand" "I,d")] 890 UNSPEC_EXTR_S_H)) 891 (set (reg:CCDSP CCDSP_OU_REGNUM) 892 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTR_S_H))])] 893 "ISA_HAS_DSP && !TARGET_64BIT" 894{ 895 if (which_alternative == 0) 896 { 897 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 898 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 899 return "extr_s.h\t%0,%q1,%2"; 900 } 901 return "extrv_s.h\t%0,%q1,%2"; 902} 903 [(set_attr "type" "mfhilo") 904 (set_attr "mode" "SI")]) 905 906;; EXTP* 907(define_insn "mips_extp" 908 [(parallel 909 [(set (match_operand:SI 0 "register_operand" "=d,d") 910 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 911 (match_operand:SI 2 "arith_operand" "I,d") 912 (reg:CCDSP CCDSP_PO_REGNUM)] 913 UNSPEC_EXTP)) 914 (set (reg:CCDSP CCDSP_EF_REGNUM) 915 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTP))])] 916 "ISA_HAS_DSP && !TARGET_64BIT" 917{ 918 if (which_alternative == 0) 919 { 920 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 921 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 922 return "extp\t%0,%q1,%2"; 923 } 924 return "extpv\t%0,%q1,%2"; 925} 926 [(set_attr "type" "mfhilo") 927 (set_attr "mode" "SI")]) 928 929(define_insn "mips_extpdp" 930 [(parallel 931 [(set (match_operand:SI 0 "register_operand" "=d,d") 932 (unspec:SI [(match_operand:DI 1 "register_operand" "a,a") 933 (match_operand:SI 2 "arith_operand" "I,d") 934 (reg:CCDSP CCDSP_PO_REGNUM)] 935 UNSPEC_EXTPDP)) 936 (set (reg:CCDSP CCDSP_PO_REGNUM) 937 (unspec:CCDSP [(match_dup 1) (match_dup 2) 938 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_EXTPDP)) 939 (set (reg:CCDSP CCDSP_EF_REGNUM) 940 (unspec:CCDSP [(match_dup 1) (match_dup 2)] UNSPEC_EXTPDP))])] 941 "ISA_HAS_DSP && !TARGET_64BIT" 942{ 943 if (which_alternative == 0) 944 { 945 if (INTVAL (operands[2]) & ~(unsigned HOST_WIDE_INT) 0x1f) 946 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); 947 return "extpdp\t%0,%q1,%2"; 948 } 949 return "extpdpv\t%0,%q1,%2"; 950} 951 [(set_attr "type" "mfhilo") 952 (set_attr "mode" "SI")]) 953 954;; SHILO* 955(define_insn "mips_shilo" 956 [(set (match_operand:DI 0 "register_operand" "=a,a") 957 (unspec:DI [(match_operand:DI 1 "register_operand" "0,0") 958 (match_operand:SI 2 "arith_operand" "I,d")] 959 UNSPEC_SHILO))] 960 "ISA_HAS_DSP && !TARGET_64BIT" 961{ 962 if (which_alternative == 0) 963 { 964 if (INTVAL (operands[2]) < -32 || INTVAL (operands[2]) > 31) 965 operands[2] = GEN_INT (INTVAL (operands[2]) & 0x3f); 966 return "shilo\t%q0,%2"; 967 } 968 return "shilov\t%q0,%2"; 969} 970 [(set_attr "type" "mfhilo") 971 (set_attr "mode" "SI")]) 972 973;; MTHLIP* 974(define_insn "mips_mthlip" 975 [(parallel 976 [(set (match_operand:DI 0 "register_operand" "=a") 977 (unspec:DI [(match_operand:DI 1 "register_operand" "0") 978 (match_operand:SI 2 "register_operand" "d") 979 (reg:CCDSP CCDSP_PO_REGNUM)] 980 UNSPEC_MTHLIP)) 981 (set (reg:CCDSP CCDSP_PO_REGNUM) 982 (unspec:CCDSP [(match_dup 1) (match_dup 2) 983 (reg:CCDSP CCDSP_PO_REGNUM)] UNSPEC_MTHLIP))])] 984 "ISA_HAS_DSP && !TARGET_64BIT" 985 "mthlip\t%2,%q0" 986 [(set_attr "type" "mfhilo") 987 (set_attr "mode" "SI")]) 988 989;; WRDSP 990(define_insn "mips_wrdsp" 991 [(parallel 992 [(set (reg:CCDSP CCDSP_PO_REGNUM) 993 (unspec:CCDSP [(match_operand:SI 0 "register_operand" "d") 994 (match_operand:SI 1 "const_uimm6_operand" "YA")] 995 UNSPEC_WRDSP)) 996 (set (reg:CCDSP CCDSP_SC_REGNUM) 997 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 998 (set (reg:CCDSP CCDSP_CA_REGNUM) 999 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1000 (set (reg:CCDSP CCDSP_OU_REGNUM) 1001 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1002 (set (reg:CCDSP CCDSP_CC_REGNUM) 1003 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP)) 1004 (set (reg:CCDSP CCDSP_EF_REGNUM) 1005 (unspec:CCDSP [(match_dup 0) (match_dup 1)] UNSPEC_WRDSP))])] 1006 "ISA_HAS_DSP" 1007 "wrdsp\t%0,%1" 1008 [(set_attr "type" "arith") 1009 (set_attr "mode" "SI")]) 1010 1011;; RDDSP 1012(define_insn "mips_rddsp" 1013 [(set (match_operand:SI 0 "register_operand" "=d") 1014 (unspec:SI [(match_operand:SI 1 "const_uimm6_operand" "YA") 1015 (reg:CCDSP CCDSP_PO_REGNUM) 1016 (reg:CCDSP CCDSP_SC_REGNUM) 1017 (reg:CCDSP CCDSP_CA_REGNUM) 1018 (reg:CCDSP CCDSP_OU_REGNUM) 1019 (reg:CCDSP CCDSP_CC_REGNUM) 1020 (reg:CCDSP CCDSP_EF_REGNUM)] 1021 UNSPEC_RDDSP))] 1022 "ISA_HAS_DSP" 1023 "rddsp\t%0,%1" 1024 [(set_attr "type" "arith") 1025 (set_attr "mode" "SI")]) 1026 1027;; Table 2-7. MIPS DSP ASE Instructions: Indexed-Load 1028;; L*X 1029(define_expand "mips_lbux" 1030 [(match_operand:SI 0 "register_operand") 1031 (match_operand 1 "pmode_register_operand") 1032 (match_operand:SI 2 "register_operand")] 1033 "ISA_HAS_DSP" 1034{ 1035 operands[2] = convert_to_mode (Pmode, operands[2], false); 1036 if (Pmode == SImode) 1037 emit_insn (gen_mips_lbux_si (operands[0], operands[1], operands[2])); 1038 else 1039 emit_insn (gen_mips_lbux_di (operands[0], operands[1], operands[2])); 1040 DONE; 1041}) 1042 1043(define_insn "mips_lbux_<mode>" 1044 [(set (match_operand:SI 0 "register_operand" "=d") 1045 (zero_extend:SI 1046 (mem:QI (plus:P (match_operand:P 1 "register_operand" "d") 1047 (match_operand:P 2 "register_operand" "d")))))] 1048 "ISA_HAS_DSP" 1049 "lbux\t%0,%2(%1)" 1050 [(set_attr "type" "load") 1051 (set_attr "mode" "SI")]) 1052 1053(define_expand "mips_lhx" 1054 [(match_operand:SI 0 "register_operand") 1055 (match_operand 1 "pmode_register_operand") 1056 (match_operand:SI 2 "register_operand")] 1057 "ISA_HAS_DSP" 1058{ 1059 operands[2] = convert_to_mode (Pmode, operands[2], false); 1060 if (Pmode == SImode) 1061 emit_insn (gen_mips_lhx_si (operands[0], operands[1], operands[2])); 1062 else 1063 emit_insn (gen_mips_lhx_di (operands[0], operands[1], operands[2])); 1064 DONE; 1065}) 1066 1067(define_insn "mips_lhx_<mode>" 1068 [(set (match_operand:SI 0 "register_operand" "=d") 1069 (sign_extend:SI 1070 (mem:HI (plus:P (match_operand:P 1 "register_operand" "d") 1071 (match_operand:P 2 "register_operand" "d")))))] 1072 "ISA_HAS_DSP" 1073 "lhx\t%0,%2(%1)" 1074 [(set_attr "type" "load") 1075 (set_attr "mode" "SI")]) 1076 1077(define_expand "mips_lwx" 1078 [(match_operand:SI 0 "register_operand") 1079 (match_operand 1 "pmode_register_operand") 1080 (match_operand:SI 2 "register_operand")] 1081 "ISA_HAS_DSP" 1082{ 1083 operands[2] = convert_to_mode (Pmode, operands[2], false); 1084 if (Pmode == SImode) 1085 emit_insn (gen_mips_lwx_si (operands[0], operands[1], operands[2])); 1086 else 1087 emit_insn (gen_mips_lwx_di (operands[0], operands[1], operands[2])); 1088 DONE; 1089}) 1090 1091(define_insn "mips_lwx_<mode>" 1092 [(set (match_operand:SI 0 "register_operand" "=d") 1093 (mem:SI (plus:P (match_operand:P 1 "register_operand" "d") 1094 (match_operand:P 2 "register_operand" "d"))))] 1095 "ISA_HAS_DSP" 1096 "lwx\t%0,%2(%1)" 1097 [(set_attr "type" "load") 1098 (set_attr "mode" "SI")]) 1099 1100;; Table 2-8. MIPS DSP ASE Instructions: Branch 1101;; BPOSGE32 1102(define_insn "mips_bposge" 1103 [(set (pc) 1104 (if_then_else (ge (reg:CCDSP CCDSP_PO_REGNUM) 1105 (match_operand:SI 1 "immediate_operand" "I")) 1106 (label_ref (match_operand 0 "" "")) 1107 (pc)))] 1108 "ISA_HAS_DSP" 1109 "%*bposge%1\t%0%/" 1110 [(set_attr "type" "branch")]) 1111 1112