1;;- Machine description for GNU compiler, Motorola 68000 Version 2;; Copyright (C) 1987-2013 Free Software Foundation, Inc. 3 4;; This file is part of GCC. 5 6;; GCC is free software; you can redistribute it and/or modify 7;; it under the terms of the GNU General Public License as published by 8;; the Free Software Foundation; either version 3, or (at your option) 9;; any later version. 10 11;; GCC is distributed in the hope that it will be useful, 12;; but WITHOUT ANY WARRANTY; without even the implied warranty of 13;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14;; GNU General Public License for more details. 15 16;; You should have received a copy of the GNU General Public License 17;; along with GCC; see the file COPYING3. If not see 18;; <http://www.gnu.org/licenses/>. 19 20;;- Information about MCF5200 port. 21 22;;- The MCF5200 "ColdFire" architecture is a reduced version of the 23;;- 68k ISA. Differences include reduced support for byte and word 24;;- operands and the removal of BCD, bitfield, rotate, and integer 25;;- divide instructions. The TARGET_COLDFIRE flag turns the use of the 26;;- removed opcodes and addressing modes off. 27;;- 28 29 30;;- instruction definitions 31 32;;- @@The original PO technology requires these to be ordered by speed, 33;;- @@ so that assigner will pick the fastest. 34 35;;- See file "rtl.def" for documentation on define_insn, match_*, et. al. 36 37;;- When naming insn's (operand 0 of define_insn) be careful about using 38;;- names from other targets machine descriptions. 39 40;;- cpp macro #define NOTICE_UPDATE_CC in file tm.h handles condition code 41;;- updates for most instructions. 42 43;;- Operand classes for the register allocator: 44;;- 'a' one of the address registers can be used. 45;;- 'd' one of the data registers can be used. 46;;- 'f' one of the m68881/fpu registers can be used 47;;- 'r' either a data or an address register can be used. 48 49;;- Immediate Floating point operator constraints 50;;- 'G' a floating point constant that is *NOT* one of the standard 51;; 68881 constant values (to force calling output_move_const_double 52;; to get it from rom if it is a 68881 constant). 53;; 54;; See the functions standard_XXX_constant_p in output-m68k.c for more 55;; info. 56 57;;- Immediate integer operand constraints: 58;;- 'I' 1 .. 8 59;;- 'J' -32768 .. 32767 60;;- 'K' all integers EXCEPT -128 .. 127 61;;- 'L' -8 .. -1 62;;- 'M' all integers EXCEPT -256 .. 255 63;;- 'N' 24 .. 31 64;;- 'O' 16 65;;- 'P' 8 .. 15 66 67;;- Assembler specs: 68;;- "%." size separator ("." or "") move%.l d0,d1 69;;- "%-" push operand "sp@-" move%.l d0,%- 70;;- "%+" pop operand "sp@+" move%.l d0,%+ 71;;- "%@" top of stack "sp@" move%.l d0,%@ 72;;- "%!" fpcr register 73;;- "%$" single-precision fp specifier ("s" or "") f%$add.x fp0,fp1 74;;- "%&" double-precision fp specifier ("d" or "") f%&add.x fp0,fp1 75 76;;- Information about 68040 port. 77 78;;- The 68040 executes all 68030 and 68881/2 instructions, but some must 79;;- be emulated in software by the OS. It is faster to avoid these 80;;- instructions and issue a library call rather than trapping into 81;;- the kernel. The affected instructions are fintrz and fscale. The 82;;- TUNE_68040 flag turns the use of the opcodes off. 83 84;;- The '040 also implements a set of new floating-point instructions 85;;- which specify the rounding precision in the opcode. This finally 86;;- permit the 68k series to be truly IEEE compliant, and solves all 87;;- issues of excess precision accumulating in the extended registers. 88;;- By default, GCC does not use these instructions, since such code will 89;;- not run on an '030. To use these instructions, use the -m68040-only 90;;- switch. 91 92;;- These new instructions aren't directly in the md. They are brought 93;;- into play by defining "%$" and "%&" to expand to "s" and "d" rather 94;;- than "". 95 96;;- Information about 68060 port. 97 98;;- The 68060 executes all 68030 and 68881/2 instructions, but some must 99;;- be emulated in software by the OS. It is faster to avoid these 100;;- instructions and issue a library call rather than trapping into 101;;- the kernel. The affected instructions are: divs.l <ea>,Dr:Dq; 102;;- divu.l <ea>,Dr:Dq; muls.l <ea>,Dr:Dq; mulu.l <ea>,Dr:Dq; and 103;;- fscale. The TUNE_68060 flag turns the use of the opcodes off. 104 105;;- Some of these insn's are composites of several m68000 op codes. 106;;- The assembler (or final @@??) insures that the appropriate one is 107;;- selected. 108 109;; UNSPEC usage: 110 111(define_constants 112 [(UNSPEC_SIN 1) 113 (UNSPEC_COS 2) 114 (UNSPEC_GOT 3) 115 (UNSPEC_IB 4) 116 (UNSPEC_TIE 5) 117 (UNSPEC_RELOC16 6) 118 (UNSPEC_RELOC32 7) 119 ]) 120 121;; UNSPEC_VOLATILE usage: 122 123(define_constants 124 [(UNSPECV_BLOCKAGE 0) 125 (UNSPECV_CAS_1 1) 126 (UNSPECV_CAS_2 2) 127 (UNSPECV_TAS_1 3) 128 (UNSPECV_TAS_2 4) 129 ]) 130 131;; Registers by name. 132(define_constants 133 [(D0_REG 0) 134 (A0_REG 8) 135 (A1_REG 9) 136 (PIC_REG 13) 137 (A6_REG 14) 138 (SP_REG 15) 139 (FP0_REG 16) 140 ]) 141 142(include "predicates.md") 143(include "constraints.md") 144 145;; :::::::::::::::::::: 146;; :: 147;; :: Attributes 148;; :: 149;; :::::::::::::::::::: 150 151;; Processor type. 152(define_attr "cpu" "cfv1, cfv2, cfv3, cfv4, unknown" 153 (const (symbol_ref "m68k_sched_cpu"))) 154 155;; MAC type. 156(define_attr "mac" "no, cf_mac, cf_emac" 157 (const (symbol_ref "m68k_sched_mac"))) 158 159;; Instruction type for use in scheduling description. 160;; _l and _w suffixes indicate size of the operands of instruction. 161;; alu - usual arithmetic or logic instruction. 162;; aluq - arithmetic or logic instruction which has a quick immediate (the one 163;; that is encoded in the instruction word) for its Y operand. 164;; alux - Arithmetic instruction that uses carry bit (e.g., addx and subx). 165;; bcc - conditional branch. 166;; bitr - bit operation that only updates flags. 167;; bitrw - bit operation that updates flags and output operand. 168;; bra, bsr, clr, cmp, div, ext - corresponding instruction. 169;; falu, fbcc, fcmp, fdiv, fmove, fmul, fneg, fsqrt, ftst - corresponding 170;; instruction. 171;; ib - fake instruction to subscribe slots in ColdFire V1,V2,V3 instruction 172;; buffer. 173;; ignore - fake instruction. 174;; jmp, jsr, lea, link, mov3q, move, moveq, mul - corresponding instruction. 175;; mvsz - mvs or mvz instruction. 176;; neg, nop, pea, rts, scc - corresponding instruction. 177;; shift - arithmetic or logical shift instruction. 178;; trap, tst, unlk - corresponding instruction. 179(define_attr "type" 180 "alu_l,aluq_l,alux_l,bcc,bitr,bitrw,bra,bsr,clr,clr_l,cmp,cmp_l, 181 div_w,div_l,ext, 182 falu,fbcc,fcmp,fdiv,fmove,fmul,fneg,fsqrt,ftst, 183 ib,ignore, 184 jmp,jsr,lea,link,mov3q_l,move,move_l,moveq_l,mul_w,mul_l,mvsz,neg_l,nop, 185 pea,rts,scc,shift, 186 trap,tst,tst_l,unlk, 187 unknown" 188 (const_string "unknown")) 189 190;; Index of the X or Y operand in recog_data.operand[]. 191;; Should be used only within opx_type and opy_type. 192(define_attr "opx" "" (const_int 0)) 193(define_attr "opy" "" (const_int 1)) 194 195;; Type of the Y operand. 196;; See m68k.c: enum attr_op_type. 197(define_attr "opy_type" 198 "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l" 199 (cond [(eq_attr "type" "ext,fbcc,ftst,neg_l,bcc,bra,bsr,clr,clr_l,ib,ignore, 200 jmp,jsr,nop,rts,scc,trap,tst,tst_l, 201 unlk,unknown") (const_string "none") 202 (eq_attr "type" "lea,pea") 203 (symbol_ref "m68k_sched_attr_opy_type (insn, 1)")] 204 (symbol_ref "m68k_sched_attr_opy_type (insn, 0)"))) 205 206;; Type of the X operand. 207;; See m68k.c: enum attr_op_type. 208(define_attr "opx_type" 209 "none,Rn,FPn,mem1,mem234,mem5,mem6,mem7,imm_q,imm_w,imm_l" 210 (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk, 211 unknown") (const_string "none") 212 (eq_attr "type" "pea") (const_string "mem1") 213 (eq_attr "type" "jmp,jsr") 214 (symbol_ref "m68k_sched_attr_opx_type (insn, 1)")] 215 (symbol_ref "m68k_sched_attr_opx_type (insn, 0)"))) 216 217;; Access to the X operand: none, read, write, read/write, unknown. 218;; Access to the Y operand is either none (if opy_type is none) 219;; or read otherwise. 220(define_attr "opx_access" "none, r, w, rw" 221 (cond [(eq_attr "type" "ib,ignore,nop,rts,trap,unlk, 222 unknown") (const_string "none") 223 (eq_attr "type" "bcc,bra,bsr,bitr,cmp,cmp_l,fbcc,fcmp,ftst, 224 jmp,jsr,tst,tst_l") (const_string "r") 225 (eq_attr "type" "clr,clr_l,fneg,fmove,lea, 226 mov3q_l,move,move_l,moveq_l,mvsz, 227 pea,scc") (const_string "w") 228 (eq_attr "type" "alu_l,aluq_l,alux_l,bitrw,div_w,div_l,ext, 229 falu,fdiv,fmul,fsqrt,link,mul_w,mul_l, 230 neg_l,shift") (const_string "rw")] 231 ;; Should never be used. 232 (symbol_ref "(gcc_unreachable (), OPX_ACCESS_NONE)"))) 233 234;; Memory accesses of the insn. 235;; 00 - no memory references 236;; 10 - memory is read 237;; i0 - indexed memory is read 238;; 01 - memory is written 239;; 0i - indexed memory is written 240;; 11 - memory is read, memory is written 241;; i1 - indexed memory is read, memory is written 242;; 1i - memory is read, indexed memory is written 243(define_attr "op_mem" "00, 10, i0, 01, 0i, 11, i1, 1i" 244 (symbol_ref "m68k_sched_attr_op_mem (insn)")) 245 246;; Instruction size in words. 247(define_attr "size" "1,2,3" 248 (symbol_ref "m68k_sched_attr_size (insn)")) 249 250;; Alternative is OK for ColdFire. 251(define_attr "ok_for_coldfire" "yes,no" (const_string "yes")) 252 253;; Define 'enabled' attribute. 254(define_attr "enabled" "" 255 (cond [(and (match_test "TARGET_COLDFIRE") 256 (eq_attr "ok_for_coldfire" "no")) 257 (const_int 0)] 258 (const_int 1))) 259 260;; Mode macros for integer operations. 261(define_mode_iterator I [QI HI SI]) 262(define_mode_attr sz [(QI "%.b") (HI "%.w") (SI "%.l")]) 263 264;; Mode macros for floating point operations. 265;; Valid floating point modes 266(define_mode_iterator FP [SF DF (XF "TARGET_68881")]) 267;; Mnemonic infix to round result 268(define_mode_attr round [(SF "%$") (DF "%&") (XF "")]) 269;; Mnemonic infix to round result for mul or div instruction 270(define_mode_attr round_mul [(SF "sgl") (DF "%&") (XF "")]) 271;; Suffix specifying source operand format 272(define_mode_attr prec [(SF "s") (DF "d") (XF "x")]) 273;; Allowable D registers 274(define_mode_attr dreg [(SF "d") (DF "") (XF "")]) 275;; Allowable 68881 constant constraints 276(define_mode_attr const [(SF "F") (DF "G") (XF "")]) 277 278 279(define_insn_and_split "*movdf_internal" 280 [(set (match_operand:DF 0 "push_operand" "=m, m") 281 (match_operand:DF 1 "general_operand" "f, ro<>E"))] 282 "" 283 "@ 284 fmove%.d %f1,%0 285 #" 286 "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 1)" 287 [(const_int 0)] 288{ 289 m68k_emit_move_double (operands); 290 DONE; 291} 292 [(set_attr "type" "fmove,*")]) 293 294(define_insn_and_split "pushdi" 295 [(set (match_operand:DI 0 "push_operand" "=m") 296 (match_operand:DI 1 "general_operand" "ro<>Fi"))] 297 "" 298 "#" 299 "&& reload_completed" 300 [(const_int 0)] 301{ 302 m68k_emit_move_double (operands); 303 DONE; 304}) 305 306;; We don't want to allow a constant operand for test insns because 307;; (set (cc0) (const_int foo)) has no mode information. Such insns will 308;; be folded while optimizing anyway. 309 310(define_insn "tstdi" 311 [(set (cc0) 312 (compare (match_operand:DI 0 "nonimmediate_operand" "am,d") 313 (const_int 0))) 314 (clobber (match_scratch:SI 1 "=X,d")) 315 (clobber (match_scratch:DI 2 "=d,X"))] 316 "" 317{ 318 if (which_alternative == 0) 319 { 320 rtx xoperands[2]; 321 322 xoperands[0] = operands[2]; 323 xoperands[1] = operands[0]; 324 output_move_double (xoperands); 325 cc_status.flags |= CC_REVERSED; /*|*/ 326 return "neg%.l %R2\;negx%.l %2"; 327 } 328 if (find_reg_note (insn, REG_DEAD, operands[0])) 329 { 330 cc_status.flags |= CC_REVERSED; /*|*/ 331 return "neg%.l %R0\;negx%.l %0"; 332 } 333 else 334 /* 335 'sub' clears %1, and also clears the X cc bit 336 'tst' sets the Z cc bit according to the low part of the DImode operand 337 'subx %1' (i.e. subx #0) acts as a (non-existent) tstx on the high part. 338 */ 339 return "sub%.l %1,%1\;tst%.l %R0\;subx%.l %1,%0"; 340}) 341 342;; If you think that the 68020 does not support tstl a0, 343;; reread page B-167 of the 68020 manual more carefully. 344(define_insn "*tstsi_internal_68020_cf" 345 [(set (cc0) 346 (compare (match_operand:SI 0 "nonimmediate_operand" "rm") 347 (const_int 0)))] 348 "TARGET_68020 || TARGET_COLDFIRE" 349 "tst%.l %0" 350 [(set_attr "type" "tst_l")]) 351 352;; On an address reg, cmpw may replace cmpl. 353(define_insn "*tstsi_internal" 354 [(set (cc0) 355 (compare (match_operand:SI 0 "nonimmediate_operand" "dm,r") 356 (const_int 0)))] 357 "!(TARGET_68020 || TARGET_COLDFIRE)" 358 "@ 359 tst%.l %0 360 cmp%.w #0,%0" 361 [(set_attr "type" "tst_l,cmp")]) 362 363;; This can't use an address register, because comparisons 364;; with address registers as second operand always test the whole word. 365(define_insn "*tsthi_internal" 366 [(set (cc0) 367 (compare (match_operand:HI 0 "nonimmediate_operand" "dm") 368 (const_int 0)))] 369 "" 370 "tst%.w %0" 371 [(set_attr "type" "tst")]) 372 373(define_insn "*tstqi_internal" 374 [(set (cc0) 375 (compare (match_operand:QI 0 "nonimmediate_operand" "dm") 376 (const_int 0)))] 377 "" 378 "tst%.b %0" 379 [(set_attr "type" "tst")]) 380 381(define_insn "tst<mode>_68881" 382 [(set (cc0) 383 (compare (match_operand:FP 0 "general_operand" "f<FP:dreg>m") 384 (match_operand:FP 1 "const0_operand" "H")))] 385 "TARGET_68881" 386{ 387 cc_status.flags = CC_IN_68881; 388 if (FP_REG_P (operands[0])) 389 return "ftst%.x %0"; 390 return "ftst%.<FP:prec> %0"; 391} 392 [(set_attr "type" "ftst")]) 393 394(define_insn "tst<mode>_cf" 395 [(set (cc0) 396 (compare (match_operand:FP 0 "general_operand" "f<FP:dreg><Q>U") 397 (match_operand:FP 1 "const0_operand" "H")))] 398 "TARGET_COLDFIRE_FPU" 399{ 400 cc_status.flags = CC_IN_68881; 401 if (FP_REG_P (operands[0])) 402 return "ftst%.d %0"; 403 return "ftst%.<FP:prec> %0"; 404} 405 [(set_attr "type" "ftst")]) 406 407 408;; compare instructions. 409 410(define_insn "*cmpdi_internal" 411 [(set (cc0) 412 (compare (match_operand:DI 1 "nonimmediate_operand" "0,d") 413 (match_operand:DI 2 "general_operand" "d,0"))) 414 (clobber (match_scratch:DI 0 "=d,d"))] 415 "" 416{ 417 if (rtx_equal_p (operands[0], operands[1])) 418 return "sub%.l %R2,%R0\;subx%.l %2,%0"; 419 else 420 { 421 cc_status.flags |= CC_REVERSED; /*|*/ 422 return "sub%.l %R1,%R0\;subx%.l %1,%0"; 423 } 424}) 425 426(define_insn "cmpdi" 427 [(set (cc0) 428 (compare (match_operand:DI 0 "nonimmediate_operand") 429 (match_operand:DI 1 "general_operand"))) 430 (clobber (match_scratch:DI 2))] 431 "" 432 "") 433 434 435(define_expand "cbranchdi4" 436 [(set (pc) 437 (if_then_else (match_operator 0 "ordered_comparison_operator" 438 [(match_operand:DI 1 "nonimmediate_operand") 439 (match_operand:DI 2 "general_operand")]) 440 (label_ref (match_operand 3 "")) 441 (pc)))] 442 "" 443{ 444 if (operands[2] == const0_rtx) 445 emit_insn (gen_tstdi (operands[1])); 446 else 447 emit_insn (gen_cmpdi (operands[1], operands[2])); 448 operands[1] = cc0_rtx; 449 operands[2] = const0_rtx; 450}) 451 452(define_expand "cstoredi4" 453 [(set (match_operand:QI 0 "register_operand") 454 (match_operator:QI 1 "ordered_comparison_operator" 455 [(match_operand:DI 2 "nonimmediate_operand") 456 (match_operand:DI 3 "general_operand")]))] 457 "" 458{ 459 if (operands[3] == const0_rtx) 460 emit_insn (gen_tstdi (operands[2])); 461 else 462 emit_insn (gen_cmpdi (operands[2], operands[3])); 463 operands[2] = cc0_rtx; 464 operands[3] = const0_rtx; 465}) 466 467 468(define_expand "cbranchsi4" 469 [(set (cc0) 470 (compare (match_operand:SI 1 "nonimmediate_operand" "") 471 (match_operand:SI 2 "general_operand" ""))) 472 (set (pc) 473 (if_then_else (match_operator 0 "ordered_comparison_operator" 474 [(cc0) (const_int 0)]) 475 (label_ref (match_operand 3 "")) 476 (pc)))] 477 "" 478 "") 479 480(define_expand "cstoresi4" 481 [(set (cc0) 482 (compare (match_operand:SI 2 "nonimmediate_operand" "") 483 (match_operand:SI 3 "general_operand" ""))) 484 (set (match_operand:QI 0 "register_operand") 485 (match_operator:QI 1 "ordered_comparison_operator" 486 [(cc0) (const_int 0)]))] 487 "" 488 "") 489 490 491;; A composite of the cmp, cmpa, cmpi & cmpm m68000 op codes. 492(define_insn "" 493 [(set (cc0) 494 (compare (match_operand:SI 0 "nonimmediate_operand" "rKT,rKs,mSr,mSa,>") 495 (match_operand:SI 1 "general_src_operand" "mSr,mSa,KTr,Ksr,>")))] 496 "!TARGET_COLDFIRE" 497{ 498 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 499 return "cmpm%.l %1,%0"; 500 if (REG_P (operands[1]) 501 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 502 { 503 cc_status.flags |= CC_REVERSED; /*|*/ 504 return "cmp%.l %d0,%d1"; 505 } 506 if (ADDRESS_REG_P (operands[0]) 507 && GET_CODE (operands[1]) == CONST_INT 508 && INTVAL (operands[1]) < 0x8000 509 && INTVAL (operands[1]) >= -0x8000) 510 return "cmp%.w %1,%0"; 511 return "cmp%.l %d1,%d0"; 512}) 513 514(define_insn "*cmpsi_cf" 515 [(set (cc0) 516 (compare (match_operand:SI 0 "nonimmediate_operand" "mrKs,r") 517 (match_operand:SI 1 "general_operand" "r,mrKs")))] 518 "TARGET_COLDFIRE" 519{ 520 if (REG_P (operands[1]) 521 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 522 { 523 cc_status.flags |= CC_REVERSED; /*|*/ 524 return "cmp%.l %d0,%d1"; 525 } 526 return "cmp%.l %d1,%d0"; 527} 528 [(set_attr "type" "cmp_l")]) 529 530(define_expand "cbranchhi4" 531 [(set (cc0) 532 (compare (match_operand:HI 1 "nonimmediate_src_operand" "") 533 (match_operand:HI 2 "m68k_subword_comparison_operand" ""))) 534 (set (pc) 535 (if_then_else (match_operator 0 "ordered_comparison_operator" 536 [(cc0) (const_int 0)]) 537 (label_ref (match_operand 3 "")) 538 (pc)))] 539 "" 540 "") 541 542(define_expand "cstorehi4" 543 [(set (cc0) 544 (compare (match_operand:HI 2 "nonimmediate_operand" "") 545 (match_operand:HI 3 "m68k_subword_comparison_operand" ""))) 546 (set (match_operand:QI 0 "register_operand") 547 (match_operator:QI 1 "ordered_comparison_operator" 548 [(cc0) (const_int 0)]))] 549 "" 550 "") 551 552(define_insn "" 553 [(set (cc0) 554 (compare (match_operand:HI 0 "nonimmediate_src_operand" "rnmS,d,n,mS,>") 555 (match_operand:HI 1 "general_src_operand" "d,rnmS,mS,n,>")))] 556 "!TARGET_COLDFIRE" 557{ 558 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 559 return "cmpm%.w %1,%0"; 560 if ((REG_P (operands[1]) && !ADDRESS_REG_P (operands[1])) 561 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 562 { 563 cc_status.flags |= CC_REVERSED; /*|*/ 564 return "cmp%.w %d0,%d1"; 565 } 566 return "cmp%.w %d1,%d0"; 567}) 568 569(define_expand "cbranchqi4" 570 [(set (cc0) 571 (compare (match_operand:QI 1 "nonimmediate_src_operand" "") 572 (match_operand:QI 2 "m68k_subword_comparison_operand" ""))) 573 (set (pc) 574 (if_then_else (match_operator 0 "ordered_comparison_operator" 575 [(cc0) (const_int 0)]) 576 (label_ref (match_operand 3 "")) 577 (pc)))] 578 "" 579 "") 580 581(define_expand "cstoreqi4" 582 [(set (cc0) 583 (compare (match_operand:QI 2 "nonimmediate_src_operand" "") 584 (match_operand:QI 3 "m68k_subword_comparison_operand" ""))) 585 (set (match_operand:QI 0 "register_operand") 586 (match_operator:QI 1 "ordered_comparison_operator" 587 [(cc0) (const_int 0)]))] 588 "" 589 "") 590 591(define_insn "" 592 [(set (cc0) 593 (compare (match_operand:QI 0 "nonimmediate_src_operand" "dn,dmS,>") 594 (match_operand:QI 1 "general_src_operand" "dmS,nd,>")))] 595 "!TARGET_COLDFIRE" 596{ 597 if (GET_CODE (operands[0]) == MEM && GET_CODE (operands[1]) == MEM) 598 return "cmpm%.b %1,%0"; 599 if (REG_P (operands[1]) 600 || (!REG_P (operands[0]) && GET_CODE (operands[0]) != MEM)) 601 { 602 cc_status.flags |= CC_REVERSED; /*|*/ 603 return "cmp%.b %d0,%d1"; 604 } 605 return "cmp%.b %d1,%d0"; 606}) 607 608(define_expand "cbranch<mode>4" 609 [(set (cc0) 610 (compare (match_operand:FP 1 "register_operand" "") 611 (match_operand:FP 2 "fp_src_operand" ""))) 612 (set (pc) 613 (if_then_else (match_operator 0 "comparison_operator" 614 [(cc0) (const_int 0)]) 615 (label_ref (match_operand 3 "")) 616 (pc)))] 617 "TARGET_HARD_FLOAT" 618 "") 619 620(define_expand "cstore<mode>4" 621 [(set (cc0) 622 (compare (match_operand:FP 2 "register_operand" "") 623 (match_operand:FP 3 "fp_src_operand" ""))) 624 (set (match_operand:QI 0 "register_operand") 625 (match_operator:QI 1 "m68k_cstore_comparison_operator" 626 [(cc0) (const_int 0)]))] 627 "TARGET_HARD_FLOAT && !(TUNE_68060 || TARGET_COLDFIRE_FPU)" 628 "if (TARGET_COLDFIRE && operands[2] != const0_rtx) 629 FAIL;") 630 631(define_insn "*cmp<mode>_68881" 632 [(set (cc0) 633 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg>mF") 634 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg>mF,f")))] 635 "TARGET_68881 636 && (register_operand (operands[0], <MODE>mode) 637 || register_operand (operands[1], <MODE>mode))" 638 "@ 639 fcmp%.x %1,%0 640 fcmp%.<FP:prec> %f1,%0 641 fcmp%.<FP:prec> %0,%f1" 642 [(set_attr "type" "fcmp")]) 643 644(define_insn "*cmp<mode>_cf" 645 [(set (cc0) 646 (compare (match_operand:FP 0 "fp_src_operand" "f,f,<FP:dreg><Q>U") 647 (match_operand:FP 1 "fp_src_operand" "f,<FP:dreg><Q>U,f")))] 648 "TARGET_COLDFIRE_FPU 649 && (register_operand (operands[0], <MODE>mode) 650 || register_operand (operands[1], <MODE>mode))" 651 "@ 652 fcmp%.d %1,%0 653 fcmp%.<FP:prec> %f1,%0 654 fcmp%.<FP:prec> %0,%f1" 655 [(set_attr "type" "fcmp")]) 656 657;; Recognizers for btst instructions. 658 659;; ColdFire/5200 only allows "<Q>" type addresses when the bit position is 660;; specified as a constant, so we must disable all patterns that may extract 661;; from a MEM at a constant bit position if we can't use this as a constraint. 662 663(define_insn "" 664 [(set 665 (cc0) 666 (compare (zero_extract:SI (match_operand:QI 0 "memory_src_operand" "oS") 667 (const_int 1) 668 (minus:SI (const_int 7) 669 (match_operand:SI 1 "general_operand" "di"))) 670 (const_int 0)))] 671 "!TARGET_COLDFIRE" 672{ 673 return output_btst (operands, operands[1], operands[0], insn, 7); 674}) 675 676;; This is the same as the above pattern except for the constraints. The 'i' 677;; has been deleted. 678 679(define_insn "" 680 [(set 681 (cc0) 682 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") 683 (const_int 1) 684 (minus:SI (const_int 7) 685 (match_operand:SI 1 "general_operand" "d"))) 686 (const_int 0)))] 687 "TARGET_COLDFIRE" 688{ 689 return output_btst (operands, operands[1], operands[0], insn, 7); 690}) 691 692(define_insn "" 693 [(set 694 (cc0) 695 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") 696 (const_int 1) 697 (minus:SI (const_int 31) 698 (match_operand:SI 1 "general_operand" "di"))) 699 (const_int 0)))] 700 "" 701{ 702 return output_btst (operands, operands[1], operands[0], insn, 31); 703}) 704 705;; The following two patterns are like the previous two 706;; except that they use the fact that bit-number operands 707;; are automatically masked to 3 or 5 bits. 708 709(define_insn "" 710 [(set 711 (cc0) 712 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") 713 (const_int 1) 714 (minus:SI (const_int 7) 715 (and:SI 716 (match_operand:SI 1 "register_operand" "d") 717 (const_int 7)))) 718 (const_int 0)))] 719 "" 720{ 721 return output_btst (operands, operands[1], operands[0], insn, 7); 722}) 723 724(define_insn "" 725 [(set 726 (cc0) 727 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") 728 (const_int 1) 729 (minus:SI (const_int 31) 730 (and:SI 731 (match_operand:SI 1 "register_operand" "d") 732 (const_int 31)))) 733 (const_int 0)))] 734 "" 735{ 736 return output_btst (operands, operands[1], operands[0], insn, 31); 737}) 738 739;; Nonoffsettable mem refs are ok in this one pattern 740;; since we don't try to adjust them. 741(define_insn "" 742 [(set 743 (cc0) 744 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "m") 745 (const_int 1) 746 (match_operand:SI 1 "const_int_operand" "n")) 747 (const_int 0)))] 748 "(unsigned) INTVAL (operands[1]) < 8 && !TARGET_COLDFIRE" 749{ 750 operands[1] = GEN_INT (7 - INTVAL (operands[1])); 751 return output_btst (operands, operands[1], operands[0], insn, 7); 752}) 753 754(define_insn "" 755 [(set 756 (cc0) 757 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "do") 758 (const_int 1) 759 (match_operand:SI 1 "const_int_operand" "n")) 760 (const_int 0)))] 761 "!TARGET_COLDFIRE" 762{ 763 if (GET_CODE (operands[0]) == MEM) 764 { 765 operands[0] = adjust_address (operands[0], QImode, 766 INTVAL (operands[1]) / 8); 767 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8); 768 return output_btst (operands, operands[1], operands[0], insn, 7); 769 } 770 operands[1] = GEN_INT (31 - INTVAL (operands[1])); 771 return output_btst (operands, operands[1], operands[0], insn, 31); 772}) 773 774;; This is the same as the above pattern except for the constraints. 775;; The 'o' has been replaced with 'Q'. 776 777(define_insn "" 778 [(set 779 (cc0) 780 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "dQ") 781 (const_int 1) 782 (match_operand:SI 1 "const_int_operand" "n")) 783 (const_int 0)))] 784 "TARGET_COLDFIRE" 785{ 786 if (GET_CODE (operands[0]) == MEM) 787 { 788 operands[0] = adjust_address (operands[0], QImode, 789 INTVAL (operands[1]) / 8); 790 operands[1] = GEN_INT (7 - INTVAL (operands[1]) % 8); 791 return output_btst (operands, operands[1], operands[0], insn, 7); 792 } 793 operands[1] = GEN_INT (31 - INTVAL (operands[1])); 794 return output_btst (operands, operands[1], operands[0], insn, 31); 795}) 796 797 798;; move instructions 799 800;; A special case in which it is not desirable 801;; to reload the constant into a data register. 802(define_insn "pushexthisi_const" 803 [(set (match_operand:SI 0 "push_operand" "=m,m,m") 804 (match_operand:SI 1 "const_int_operand" "C0,R,J"))] 805 "INTVAL (operands[1]) >= -0x8000 && INTVAL (operands[1]) < 0x8000" 806 "@ 807 clr%.l %0 808 mov3q%.l %1,%- 809 pea %a1" 810 [(set_attr "type" "clr_l,mov3q_l,pea")]) 811 812;This is never used. 813;(define_insn "swapsi" 814; [(set (match_operand:SI 0 "nonimmediate_operand" "+r") 815; (match_operand:SI 1 "general_operand" "+r")) 816; (set (match_dup 1) (match_dup 0))] 817; "" 818; "exg %1,%0") 819 820;; Special case of fullword move when source is zero for 68000_10. 821;; moveq is faster on the 68000. 822(define_insn "*movsi_const0_68000_10" 823 [(set (match_operand:SI 0 "movsi_const0_operand" "=d,a,g") 824 (const_int 0))] 825 "TUNE_68000_10" 826 "@ 827 moveq #0,%0 828 sub%.l %0,%0 829 clr%.l %0" 830 [(set_attr "type" "moveq_l,alu_l,clr_l") 831 (set_attr "opy" "*,0,*")]) 832 833;; Special case of fullword move when source is zero for 68040_60. 834;; On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 835(define_insn "*movsi_const0_68040_60" 836 [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g") 837 (const_int 0))] 838 "TUNE_68040_60" 839{ 840 if (which_alternative == 0) 841 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0"; 842 else if (which_alternative == 1) 843 return "clr%.l %0"; 844 else 845 { 846 gcc_unreachable (); 847 return ""; 848 } 849} 850 [(set_attr "type" "lea,clr_l")]) 851 852;; Special case of fullword move when source is zero. 853(define_insn "*movsi_const0" 854 [(set (match_operand:SI 0 "movsi_const0_operand" "=a,g") 855 (const_int 0))] 856 "!(TUNE_68000_10 || TUNE_68040_60)" 857 "@ 858 sub%.l %0,%0 859 clr%.l %0" 860 [(set_attr "type" "alu_l,clr_l") 861 (set_attr "opy" "0,*")]) 862 863;; General case of fullword move. 864;; 865;; This is the main "hook" for PIC code. When generating 866;; PIC, movsi is responsible for determining when the source address 867;; needs PIC relocation and appropriately calling legitimize_pic_address 868;; to perform the actual relocation. 869;; 870;; In both the PIC and non-PIC cases the patterns generated will 871;; matched by the next define_insn. 872(define_expand "movsi" 873 [(set (match_operand:SI 0 "" "") 874 (match_operand:SI 1 "" ""))] 875 "" 876{ 877 rtx tmp, base, offset; 878 879 /* Recognize the case where operand[1] is a reference to thread-local 880 data and load its address to a register. */ 881 if (!TARGET_PCREL && m68k_tls_reference_p (operands[1], false)) 882 { 883 rtx tmp = operands[1]; 884 rtx addend = NULL; 885 886 if (GET_CODE (tmp) == CONST && GET_CODE (XEXP (tmp, 0)) == PLUS) 887 { 888 addend = XEXP (XEXP (tmp, 0), 1); 889 tmp = XEXP (XEXP (tmp, 0), 0); 890 } 891 892 gcc_assert (GET_CODE (tmp) == SYMBOL_REF); 893 gcc_assert (SYMBOL_REF_TLS_MODEL (tmp) != 0); 894 895 tmp = m68k_legitimize_tls_address (tmp); 896 897 if (addend) 898 { 899 if (!REG_P (tmp)) 900 { 901 rtx reg; 902 903 reg = gen_reg_rtx (Pmode); 904 emit_move_insn (reg, tmp); 905 tmp = reg; 906 } 907 908 tmp = gen_rtx_PLUS (SImode, tmp, addend); 909 } 910 911 operands[1] = tmp; 912 } 913 else if (flag_pic && !TARGET_PCREL && symbolic_operand (operands[1], SImode)) 914 { 915 /* The source is an address which requires PIC relocation. 916 Call legitimize_pic_address with the source, mode, and a relocation 917 register (a new pseudo, or the final destination if reload_in_progress 918 is set). Then fall through normally */ 919 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode); 920 operands[1] = legitimize_pic_address (operands[1], SImode, temp); 921 } 922 else if (flag_pic && TARGET_PCREL && ! reload_in_progress) 923 { 924 /* Don't allow writes to memory except via a register; 925 the m68k doesn't consider PC-relative addresses to be writable. */ 926 if (symbolic_operand (operands[0], SImode)) 927 operands[0] = force_reg (SImode, XEXP (operands[0], 0)); 928 else if (GET_CODE (operands[0]) == MEM 929 && symbolic_operand (XEXP (operands[0], 0), SImode)) 930 operands[0] = gen_rtx_MEM (SImode, 931 force_reg (SImode, XEXP (operands[0], 0))); 932 } 933 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) 934 { 935 split_const (operands[1], &base, &offset); 936 if (GET_CODE (base) == SYMBOL_REF 937 && !offset_within_block_p (base, INTVAL (offset))) 938 { 939 tmp = !can_create_pseudo_p () ? operands[0] : gen_reg_rtx (SImode); 940 emit_move_insn (tmp, base); 941 emit_insn (gen_addsi3 (operands[0], tmp, offset)); 942 DONE; 943 } 944 } 945}) 946 947;; General case of fullword move. 948(define_insn "*movsi_m68k" 949 ;; Notes: make sure no alternative allows g vs g. 950 ;; We don't allow f-regs since fixed point cannot go in them. 951 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<") 952 (match_operand:SI 1 "general_src_operand" "damSnT,n,i"))] 953 "!TARGET_COLDFIRE && reload_completed" 954{ 955 return output_move_simode (operands); 956}) 957 958;; Before reload is completed the register constraints 959;; force integer constants in range for a moveq to be reloaded 960;; if they are headed for memory. 961(define_insn "*movsi_m68k2" 962 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d,a<") 963 (match_operand:SI 1 "general_src_operand" "damSKT,n,i"))] 964 965 "!TARGET_COLDFIRE" 966{ 967 return output_move_simode (operands); 968}) 969 970;; ColdFire move instructions can have at most one operand of mode >= 6. 971(define_insn "*movsi_cf" 972 [(set (match_operand:SI 0 "nonimmediate_operand" "=g,d, d, d, d, d, a,Ap, a, r<Q>,g, U") 973 (match_operand:SI 1 "general_operand" " R,CQ,CW,CZ,CS,Ci,J,J Cs,Cs, g, Rr<Q>,U"))] 974 "TARGET_COLDFIRE" 975{ 976 switch (which_alternative) 977 { 978 case 0: 979 return "mov3q%.l %1,%0"; 980 981 case 1: 982 return "moveq %1,%0"; 983 984 case 2: 985 { 986 unsigned u = INTVAL (operands[1]); 987 988 operands[1] = GEN_INT ((u << 16) | (u >> 16)); /*|*/ 989 return "moveq %1,%0\n\tswap %0"; 990 } 991 992 case 3: 993 return "mvz%.w %1,%0"; 994 995 case 4: 996 return "mvs%.w %1,%0"; 997 998 case 5: 999 return "move%.l %1,%0"; 1000 1001 case 6: 1002 return "move%.w %1,%0"; 1003 1004 case 7: 1005 return "pea %a1"; 1006 1007 case 8: 1008 return "lea %a1,%0"; 1009 1010 case 9: 1011 case 10: 1012 case 11: 1013 return "move%.l %1,%0"; 1014 1015 default: 1016 gcc_unreachable (); 1017 return ""; 1018 } 1019} 1020 [(set_attr "type" "mov3q_l,moveq_l,*,mvsz,mvsz,move_l,move,pea,lea,move_l,move_l,move_l")]) 1021 1022;; Special case of fullword move, where we need to get a non-GOT PIC 1023;; reference into an address register. 1024(define_insn "" 1025 [(set (match_operand:SI 0 "nonimmediate_operand" "=a<") 1026 (match_operand:SI 1 "pcrel_address" ""))] 1027 "TARGET_PCREL" 1028{ 1029 if (push_operand (operands[0], SImode)) 1030 return "pea %a1"; 1031 return "lea %a1,%0"; 1032}) 1033 1034(define_expand "movhi" 1035 [(set (match_operand:HI 0 "nonimmediate_operand" "") 1036 (match_operand:HI 1 "general_operand" ""))] 1037 "" 1038 "") 1039 1040(define_insn "" 1041 [(set (match_operand:HI 0 "nonimmediate_operand" "=g") 1042 (match_operand:HI 1 "general_src_operand" "gS"))] 1043 "!TARGET_COLDFIRE" 1044 "* return output_move_himode (operands);") 1045 1046(define_insn "" 1047 [(set (match_operand:HI 0 "nonimmediate_operand" "=r<Q>,g,U") 1048 (match_operand:HI 1 "general_operand" "g,r<Q>,U"))] 1049 "TARGET_COLDFIRE" 1050 "* return output_move_himode (operands);") 1051 1052(define_expand "movstricthi" 1053 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "")) 1054 (match_operand:HI 1 "general_src_operand" ""))] 1055 "" 1056 "") 1057 1058(define_insn "" 1059 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) 1060 (match_operand:HI 1 "general_src_operand" "rmSn"))] 1061 "!TARGET_COLDFIRE" 1062 "* return output_move_stricthi (operands);") 1063 1064(define_insn "" 1065 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+d,m")) 1066 (match_operand:HI 1 "general_src_operand" "rmn,r"))] 1067 "TARGET_COLDFIRE" 1068 "* return output_move_stricthi (operands);") 1069 1070(define_expand "movqi" 1071 [(set (match_operand:QI 0 "nonimmediate_operand" "") 1072 (match_operand:QI 1 "general_src_operand" ""))] 1073 "" 1074 "") 1075 1076(define_insn "" 1077 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,*a,m") 1078 (match_operand:QI 1 "general_src_operand" "dmSi*a,di*a,dmSi"))] 1079 "!TARGET_COLDFIRE" 1080 "* return output_move_qimode (operands);") 1081 1082(define_insn "" 1083 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>,dm,U,d*a") 1084 (match_operand:QI 1 "general_src_operand" "dmi,d<Q>,U,di*a"))] 1085 "TARGET_COLDFIRE" 1086 "* return output_move_qimode (operands);") 1087 1088(define_expand "movstrictqi" 1089 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "")) 1090 (match_operand:QI 1 "general_src_operand" ""))] 1091 "" 1092 "") 1093 1094(define_insn "" 1095 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) 1096 (match_operand:QI 1 "general_src_operand" "dmSn"))] 1097 "!TARGET_COLDFIRE" 1098 "* return output_move_strictqi (operands);") 1099 1100(define_insn "*movstrictqi_cf" 1101 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+d, Ac, d,m")) 1102 (match_operand:QI 1 "general_src_operand" "C0,C0, dmn,d"))] 1103 "TARGET_COLDFIRE" 1104 "@ 1105 clr%.b %0 1106 clr%.b %0 1107 move%.b %1,%0 1108 move%.b %1,%0" 1109 [(set_attr "type" "clr,clr,move,move")]) 1110 1111(define_expand "pushqi1" 1112 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2))) 1113 (set (mem:QI (plus:SI (reg:SI SP_REG) (const_int 1))) 1114 (match_operand:QI 0 "general_operand" ""))] 1115 "!TARGET_COLDFIRE" 1116 "") 1117 1118(define_expand "reload_insf" 1119 [(set (match_operand:SF 0 "nonimmediate_operand" "=f") 1120 (match_operand:SF 1 "general_operand" "mf")) 1121 (clobber (match_operand:SI 2 "register_operand" "=&a"))] 1122 "TARGET_COLDFIRE_FPU" 1123{ 1124 if (emit_move_sequence (operands, SFmode, operands[2])) 1125 DONE; 1126 1127 /* We don't want the clobber emitted, so handle this ourselves. */ 1128 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 1129 DONE; 1130}) 1131 1132(define_expand "reload_outsf" 1133 [(set (match_operand:SF 0 "general_operand" "") 1134 (match_operand:SF 1 "register_operand" "f")) 1135 (clobber (match_operand:SI 2 "register_operand" "=&a"))] 1136 "TARGET_COLDFIRE_FPU" 1137{ 1138 if (emit_move_sequence (operands, SFmode, operands[2])) 1139 DONE; 1140 1141 /* We don't want the clobber emitted, so handle this ourselves. */ 1142 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 1143 DONE; 1144}) 1145 1146(define_expand "movsf" 1147 [(set (match_operand:SF 0 "nonimmediate_operand" "") 1148 (match_operand:SF 1 "general_operand" ""))] 1149 "" 1150 "") 1151 1152(define_insn "" 1153 [(set (match_operand:SF 0 "nonimmediate_operand" "=rmf") 1154 (match_operand:SF 1 "general_operand" "rmfF"))] 1155 "!TARGET_COLDFIRE" 1156{ 1157 if (FP_REG_P (operands[0])) 1158 { 1159 if (FP_REG_P (operands[1])) 1160 return "f%$move%.x %1,%0"; 1161 else if (ADDRESS_REG_P (operands[1])) 1162 return "move%.l %1,%-\;f%$move%.s %+,%0"; 1163 else if (GET_CODE (operands[1]) == CONST_DOUBLE) 1164 return output_move_const_single (operands); 1165 return "f%$move%.s %f1,%0"; 1166 } 1167 if (FP_REG_P (operands[1])) 1168 { 1169 if (ADDRESS_REG_P (operands[0])) 1170 return "fmove%.s %1,%-\;move%.l %+,%0"; 1171 return "fmove%.s %f1,%0"; 1172 } 1173 if (operands[1] == CONST0_RTX (SFmode) 1174 /* clr insns on 68000 read before writing. */ 1175 && ((TARGET_68010 || TARGET_COLDFIRE) 1176 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) 1177 { 1178 if (ADDRESS_REG_P (operands[0])) 1179 { 1180 /* On the '040, 'subl an,an' takes 2 clocks while lea takes only 1 */ 1181 if (TUNE_68040_60) 1182 return MOTOROLA ? "lea 0.w,%0" : "lea 0:w,%0"; 1183 else 1184 return "sub%.l %0,%0"; 1185 } 1186 /* moveq is faster on the 68000. */ 1187 if (DATA_REG_P (operands[0]) && TUNE_68000_10) 1188 return "moveq #0,%0"; 1189 return "clr%.l %0"; 1190 } 1191 return "move%.l %1,%0"; 1192}) 1193 1194(define_insn "movsf_cf_soft" 1195 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>,g,U") 1196 (match_operand:SF 1 "general_operand" "g,r<Q>,U"))] 1197 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU" 1198 "move%.l %1,%0" 1199 [(set_attr "type" "move_l")]) 1200 1201;; SFmode MEMs are restricted to modes 2-4 if TARGET_COLDFIRE_FPU. 1202;; The move instructions can handle all combinations. 1203(define_insn "movsf_cf_hard" 1204 [(set (match_operand:SF 0 "nonimmediate_operand" "=r<Q>U, f, f,mr,f,r<Q>,f 1205,m") 1206 (match_operand:SF 1 "general_operand" " f, r<Q>U,f,rm,F,F, m 1207,f"))] 1208 "TARGET_COLDFIRE_FPU" 1209{ 1210 if (which_alternative == 4 || which_alternative == 5) { 1211 rtx xoperands[2]; 1212 REAL_VALUE_TYPE r; 1213 long l; 1214 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); 1215 REAL_VALUE_TO_TARGET_SINGLE (r, l); 1216 xoperands[0] = operands[0]; 1217 xoperands[1] = GEN_INT (l); 1218 if (which_alternative == 5) { 1219 if (l == 0) { 1220 if (ADDRESS_REG_P (xoperands[0])) 1221 output_asm_insn ("sub%.l %0,%0", xoperands); 1222 else 1223 output_asm_insn ("clr%.l %0", xoperands); 1224 } else 1225 if (GET_CODE (operands[0]) == MEM 1226 && symbolic_operand (XEXP (operands[0], 0), SImode)) 1227 output_asm_insn ("move%.l %1,%-;move%.l %+,%0", xoperands); 1228 else 1229 output_asm_insn ("move%.l %1,%0", xoperands); 1230 return ""; 1231 } 1232 if (l != 0) 1233 output_asm_insn ("move%.l %1,%-;fsmove%.s %+,%0", xoperands); 1234 else 1235 output_asm_insn ("clr%.l %-;fsmove%.s %+,%0", xoperands); 1236 return ""; 1237 } 1238 if (FP_REG_P (operands[0])) 1239 { 1240 if (ADDRESS_REG_P (operands[1])) 1241 return "move%.l %1,%-;fsmove%.s %+,%0"; 1242 if (FP_REG_P (operands[1])) 1243 return "fsmove%.d %1,%0"; 1244 return "fsmove%.s %f1,%0"; 1245 } 1246 if (FP_REG_P (operands[1])) 1247 { 1248 if (ADDRESS_REG_P (operands[0])) 1249 return "fmove%.s %1,%-;move%.l %+,%0"; 1250 return "fmove%.s %f1,%0"; 1251 } 1252 if (operands[1] == CONST0_RTX (SFmode)) 1253 { 1254 if (ADDRESS_REG_P (operands[0])) 1255 return "sub%.l %0,%0"; 1256 return "clr%.l %0"; 1257 } 1258 return "move%.l %1,%0"; 1259}) 1260 1261(define_expand "reload_indf" 1262 [(set (match_operand:DF 0 "nonimmediate_operand" "=f") 1263 (match_operand:DF 1 "general_operand" "mf")) 1264 (clobber (match_operand:SI 2 "register_operand" "=&a"))] 1265 "TARGET_COLDFIRE_FPU" 1266{ 1267 if (emit_move_sequence (operands, DFmode, operands[2])) 1268 DONE; 1269 1270 /* We don't want the clobber emitted, so handle this ourselves. */ 1271 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 1272 DONE; 1273}) 1274 1275(define_expand "reload_outdf" 1276 [(set (match_operand:DF 0 "general_operand" "") 1277 (match_operand:DF 1 "register_operand" "f")) 1278 (clobber (match_operand:SI 2 "register_operand" "=&a"))] 1279 "TARGET_COLDFIRE_FPU" 1280{ 1281 if (emit_move_sequence (operands, DFmode, operands[2])) 1282 DONE; 1283 1284 /* We don't want the clobber emitted, so handle this ourselves. */ 1285 emit_insn (gen_rtx_SET (VOIDmode, operands[0], operands[1])); 1286 DONE; 1287}) 1288 1289(define_expand "movdf" 1290 [(set (match_operand:DF 0 "nonimmediate_operand" "") 1291 (match_operand:DF 1 "general_operand" ""))] 1292 "" 1293{ 1294 if (TARGET_COLDFIRE_FPU) 1295 if (emit_move_sequence (operands, DFmode, 0)) 1296 DONE; 1297}) 1298 1299(define_insn "" 1300 [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,rf,rf,&rof<>") 1301 (match_operand:DF 1 "general_operand" "*rf,m,0,*rofE<>"))] 1302; [(set (match_operand:DF 0 "nonimmediate_operand" "=rm,&rf,&rof<>") 1303; (match_operand:DF 1 "general_operand" "rf,m,rofF<>"))] 1304 "!TARGET_COLDFIRE" 1305{ 1306 if (FP_REG_P (operands[0])) 1307 { 1308 if (FP_REG_P (operands[1])) 1309 return "f%&move%.x %1,%0"; 1310 if (REG_P (operands[1])) 1311 { 1312 rtx xoperands[2]; 1313 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 1314 output_asm_insn ("move%.l %1,%-", xoperands); 1315 output_asm_insn ("move%.l %1,%-", operands); 1316 return "f%&move%.d %+,%0"; 1317 } 1318 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1319 return output_move_const_double (operands); 1320 return "f%&move%.d %f1,%0"; 1321 } 1322 else if (FP_REG_P (operands[1])) 1323 { 1324 if (REG_P (operands[0])) 1325 { 1326 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands); 1327 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1328 return "move%.l %+,%0"; 1329 } 1330 else 1331 return "fmove%.d %f1,%0"; 1332 } 1333 return output_move_double (operands); 1334}) 1335 1336(define_insn_and_split "movdf_cf_soft" 1337 [(set (match_operand:DF 0 "nonimmediate_operand" "=r,g") 1338 (match_operand:DF 1 "general_operand" "g,r"))] 1339 "TARGET_COLDFIRE && !TARGET_COLDFIRE_FPU" 1340 "#" 1341 "&& reload_completed" 1342 [(const_int 0)] 1343{ 1344 m68k_emit_move_double (operands); 1345 DONE; 1346}) 1347 1348(define_insn "movdf_cf_hard" 1349 [(set (match_operand:DF 0 "nonimmediate_operand" "=f, <Q>U,r,f,r,r,m,f") 1350 (match_operand:DF 1 "general_operand" " f<Q>U,f, f,r,r,m,r,E"))] 1351 "TARGET_COLDFIRE_FPU" 1352{ 1353 rtx xoperands[3]; 1354 REAL_VALUE_TYPE r; 1355 long l[2]; 1356 1357 switch (which_alternative) 1358 { 1359 default: 1360 return "fdmove%.d %1,%0"; 1361 case 1: 1362 return "fmove%.d %1,%0"; 1363 case 2: 1364 return "fmove%.d %1,%-;move%.l %+,%0;move%.l %+,%R0"; 1365 case 3: 1366 return "move%.l %R1,%-;move%.l %1,%-;fdmove%.d %+,%0"; 1367 case 4: case 5: case 6: 1368 return output_move_double (operands); 1369 case 7: 1370 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); 1371 REAL_VALUE_TO_TARGET_DOUBLE (r, l); 1372 xoperands[0] = operands[0]; 1373 xoperands[1] = GEN_INT (l[0]); 1374 xoperands[2] = GEN_INT (l[1]); 1375 if (operands[1] == CONST0_RTX (DFmode)) 1376 output_asm_insn ("clr%.l %-;clr%.l %-;fdmove%.d %+,%0", 1377 xoperands); 1378 else 1379 if (l[1] == 0) 1380 output_asm_insn ("clr%.l %-;move%.l %1,%-;fdmove%.d %+,%0", 1381 xoperands); 1382 else 1383 output_asm_insn ("move%.l %2,%-;move%.l %1,%-;fdmove%.d %+,%0", 1384 xoperands); 1385 return ""; 1386 } 1387}) 1388 1389;; ??? The XFmode patterns are schizophrenic about whether constants are 1390;; allowed. Most but not all have predicates and constraint that disallow 1391;; constants. Most but not all have output templates that handle constants. 1392;; See also TARGET_LEGITIMATE_CONSTANT_P. 1393 1394(define_expand "movxf" 1395 [(set (match_operand:XF 0 "nonimmediate_operand" "") 1396 (match_operand:XF 1 "general_operand" ""))] 1397 "" 1398{ 1399 /* We can't rewrite operands during reload. */ 1400 if (! reload_in_progress) 1401 { 1402 if (CONSTANT_P (operands[1])) 1403 { 1404 operands[1] = force_const_mem (XFmode, operands[1]); 1405 if (! memory_address_p (XFmode, XEXP (operands[1], 0))) 1406 operands[1] = adjust_address (operands[1], XFmode, 0); 1407 } 1408 if (flag_pic && TARGET_PCREL) 1409 { 1410 /* Don't allow writes to memory except via a register; the 1411 m68k doesn't consider PC-relative addresses to be writable. */ 1412 if (GET_CODE (operands[0]) == MEM 1413 && symbolic_operand (XEXP (operands[0], 0), SImode)) 1414 operands[0] = gen_rtx_MEM (XFmode, 1415 force_reg (SImode, XEXP (operands[0], 0))); 1416 } 1417 } 1418}) 1419 1420(define_insn "" 1421 [(set (match_operand:XF 0 "nonimmediate_operand" "=f,m,f,!r,!f,!r,m,!r") 1422 (match_operand:XF 1 "nonimmediate_operand" "m,f,f,f,r,!r,!r,m"))] 1423 "TARGET_68881" 1424{ 1425 if (FP_REG_P (operands[0])) 1426 { 1427 if (FP_REG_P (operands[1])) 1428 return "fmove%.x %1,%0"; 1429 if (REG_P (operands[1])) 1430 { 1431 rtx xoperands[2]; 1432 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); 1433 output_asm_insn ("move%.l %1,%-", xoperands); 1434 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 1435 output_asm_insn ("move%.l %1,%-", xoperands); 1436 output_asm_insn ("move%.l %1,%-", operands); 1437 return "fmove%.x %+,%0"; 1438 } 1439 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1440 return "fmove%.x %1,%0"; 1441 return "fmove%.x %f1,%0"; 1442 } 1443 if (FP_REG_P (operands[1])) 1444 { 1445 if (REG_P (operands[0])) 1446 { 1447 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands); 1448 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1449 output_asm_insn ("move%.l %+,%0", operands); 1450 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1451 return "move%.l %+,%0"; 1452 } 1453 /* Must be memory destination. */ 1454 return "fmove%.x %f1,%0"; 1455 } 1456 return output_move_double (operands); 1457}) 1458 1459(define_insn "" 1460 [(set (match_operand:XF 0 "nonimmediate_operand" "=rm,rf,&rof<>") 1461 (match_operand:XF 1 "nonimmediate_operand" "rf,m,rof<>"))] 1462 "! TARGET_68881 && ! TARGET_COLDFIRE" 1463{ 1464 if (FP_REG_P (operands[0])) 1465 { 1466 if (FP_REG_P (operands[1])) 1467 return "fmove%.x %1,%0"; 1468 if (REG_P (operands[1])) 1469 { 1470 rtx xoperands[2]; 1471 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); 1472 output_asm_insn ("move%.l %1,%-", xoperands); 1473 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 1474 output_asm_insn ("move%.l %1,%-", xoperands); 1475 output_asm_insn ("move%.l %1,%-", operands); 1476 return "fmove%.x %+,%0"; 1477 } 1478 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1479 return "fmove%.x %1,%0"; 1480 return "fmove%.x %f1,%0"; 1481 } 1482 if (FP_REG_P (operands[1])) 1483 { 1484 if (REG_P (operands[0])) 1485 { 1486 output_asm_insn ("fmove%.x %f1,%-\;move%.l %+,%0", operands); 1487 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1488 output_asm_insn ("move%.l %+,%0", operands); 1489 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1490 return "move%.l %+,%0"; 1491 } 1492 else 1493 return "fmove%.x %f1,%0"; 1494 } 1495 return output_move_double (operands); 1496}) 1497 1498(define_insn "" 1499 [(set (match_operand:XF 0 "nonimmediate_operand" "=r,g") 1500 (match_operand:XF 1 "nonimmediate_operand" "g,r"))] 1501 "! TARGET_68881 && TARGET_COLDFIRE" 1502 "* return output_move_double (operands);") 1503 1504(define_expand "movdi" 1505 ;; Let's see if it really still needs to handle fp regs, and, if so, why. 1506 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1507 (match_operand:DI 1 "general_operand" ""))] 1508 "" 1509 "") 1510 1511;; movdi can apply to fp regs in some cases 1512(define_insn "" 1513 ;; Let's see if it really still needs to handle fp regs, and, if so, why. 1514 [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,r,&ro<>") 1515 (match_operand:DI 1 "general_operand" "rF,m,roi<>F"))] 1516; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&r,&ro<>,!&rm,!&f") 1517; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF"))] 1518; [(set (match_operand:DI 0 "nonimmediate_operand" "=rm,&rf,&ro<>,!&rm,!&f") 1519; (match_operand:DI 1 "general_operand" "r,m,roi<>,fF,rfF"))] 1520 "!TARGET_COLDFIRE" 1521{ 1522 if (FP_REG_P (operands[0])) 1523 { 1524 if (FP_REG_P (operands[1])) 1525 return "fmove%.x %1,%0"; 1526 if (REG_P (operands[1])) 1527 { 1528 rtx xoperands[2]; 1529 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 1530 output_asm_insn ("move%.l %1,%-", xoperands); 1531 output_asm_insn ("move%.l %1,%-", operands); 1532 return "fmove%.d %+,%0"; 1533 } 1534 if (GET_CODE (operands[1]) == CONST_DOUBLE) 1535 return output_move_const_double (operands); 1536 return "fmove%.d %f1,%0"; 1537 } 1538 else if (FP_REG_P (operands[1])) 1539 { 1540 if (REG_P (operands[0])) 1541 { 1542 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands); 1543 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1544 return "move%.l %+,%0"; 1545 } 1546 else 1547 return "fmove%.d %f1,%0"; 1548 } 1549 return output_move_double (operands); 1550}) 1551 1552(define_insn "" 1553 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,g") 1554 (match_operand:DI 1 "general_operand" "g,r"))] 1555 "TARGET_COLDFIRE" 1556 "* return output_move_double (operands);") 1557 1558;; Thus goes after the move instructions 1559;; because the move instructions are better (require no spilling) 1560;; when they can apply. It goes before the add/sub insns 1561;; so we will prefer it to them. 1562 1563(define_insn "pushasi" 1564 [(set (match_operand:SI 0 "push_operand" "=m") 1565 (match_operand:SI 1 "address_operand" "p"))] 1566 "" 1567 "pea %a1" 1568 [(set_attr "type" "pea")]) 1569 1570;; truncation instructions 1571(define_insn "truncsiqi2" 1572 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d") 1573 (truncate:QI 1574 (match_operand:SI 1 "general_src_operand" "doJS,i")))] 1575 "" 1576{ 1577 if (GET_CODE (operands[0]) == REG) 1578 { 1579 /* Must clear condition codes, since the move.l bases them on 1580 the entire 32 bits, not just the desired 8 bits. */ 1581 CC_STATUS_INIT; 1582 return "move%.l %1,%0"; 1583 } 1584 if (GET_CODE (operands[1]) == MEM) 1585 operands[1] = adjust_address (operands[1], QImode, 3); 1586 return "move%.b %1,%0"; 1587}) 1588 1589(define_insn "trunchiqi2" 1590 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,d") 1591 (truncate:QI 1592 (match_operand:HI 1 "general_src_operand" "doJS,i")))] 1593 "" 1594{ 1595 if (GET_CODE (operands[0]) == REG 1596 && (GET_CODE (operands[1]) == MEM 1597 || GET_CODE (operands[1]) == CONST_INT)) 1598 { 1599 /* Must clear condition codes, since the move.w bases them on 1600 the entire 16 bits, not just the desired 8 bits. */ 1601 CC_STATUS_INIT; 1602 return "move%.w %1,%0"; 1603 } 1604 if (GET_CODE (operands[0]) == REG) 1605 { 1606 /* Must clear condition codes, since the move.l bases them on 1607 the entire 32 bits, not just the desired 8 bits. */ 1608 CC_STATUS_INIT; 1609 return "move%.l %1,%0"; 1610 } 1611 if (GET_CODE (operands[1]) == MEM) 1612 operands[1] = adjust_address (operands[1], QImode, 1); 1613 return "move%.b %1,%0"; 1614}) 1615 1616(define_insn "truncsihi2" 1617 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm,d") 1618 (truncate:HI 1619 (match_operand:SI 1 "general_src_operand" "roJS,i")))] 1620 "" 1621{ 1622 if (GET_CODE (operands[0]) == REG) 1623 { 1624 /* Must clear condition codes, since the move.l bases them on 1625 the entire 32 bits, not just the desired 8 bits. */ 1626 CC_STATUS_INIT; 1627 return "move%.l %1,%0"; 1628 } 1629 if (GET_CODE (operands[1]) == MEM) 1630 operands[1] = adjust_address (operands[1], QImode, 2); 1631 return "move%.w %1,%0"; 1632}) 1633 1634;; zero extension instructions 1635 1636;; two special patterns to match various post_inc/pre_dec patterns 1637(define_insn_and_split "*zero_extend_inc" 1638 [(set (match_operand 0 "post_inc_operand" "") 1639 (zero_extend (match_operand 1 "register_operand" "")))] 1640 "GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT && 1641 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT && 1642 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2" 1643 "#" 1644 "" 1645 [(set (match_dup 0) 1646 (const_int 0)) 1647 (set (match_dup 0) 1648 (match_dup 1))] 1649{ 1650 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0); 1651}) 1652 1653(define_insn_and_split "*zero_extend_dec" 1654 [(set (match_operand 0 "pre_dec_operand" "") 1655 (zero_extend (match_operand 1 "register_operand" "")))] 1656 "(GET_MODE (operands[0]) != HImode || XEXP (XEXP (operands[0], 0), 0) != stack_pointer_rtx) && 1657 GET_MODE_CLASS (GET_MODE (operands[0])) == MODE_INT && 1658 GET_MODE_CLASS (GET_MODE (operands[1])) == MODE_INT && 1659 GET_MODE_SIZE (GET_MODE (operands[0])) == GET_MODE_SIZE (GET_MODE (operands[1])) * 2" 1660 "#" 1661 "" 1662 [(set (match_dup 0) 1663 (match_dup 1)) 1664 (set (match_dup 0) 1665 (const_int 0))] 1666{ 1667 operands[0] = adjust_address (operands[0], GET_MODE (operands[1]), 0); 1668}) 1669 1670(define_insn_and_split "zero_extendqidi2" 1671 [(set (match_operand:DI 0 "register_operand" "") 1672 (zero_extend:DI (match_operand:QI 1 "nonimmediate_src_operand" "")))] 1673 "" 1674 "#" 1675 "" 1676 [(set (match_dup 2) 1677 (zero_extend:SI (match_dup 1))) 1678 (set (match_dup 3) 1679 (const_int 0))] 1680{ 1681 operands[2] = gen_lowpart (SImode, operands[0]); 1682 operands[3] = gen_highpart (SImode, operands[0]); 1683}) 1684 1685(define_insn_and_split "zero_extendhidi2" 1686 [(set (match_operand:DI 0 "register_operand" "") 1687 (zero_extend:DI (match_operand:HI 1 "nonimmediate_src_operand" "")))] 1688 "" 1689 "#" 1690 "" 1691 [(set (match_dup 2) 1692 (zero_extend:SI (match_dup 1))) 1693 (set (match_dup 3) 1694 (const_int 0))] 1695{ 1696 operands[2] = gen_lowpart (SImode, operands[0]); 1697 operands[3] = gen_highpart (SImode, operands[0]); 1698}) 1699 1700(define_expand "zero_extendsidi2" 1701 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1702 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))] 1703 "" 1704{ 1705 if (GET_CODE (operands[0]) == MEM 1706 && GET_CODE (operands[1]) == MEM) 1707 operands[1] = force_reg (SImode, operands[1]); 1708}) 1709 1710(define_insn_and_split "*zero_extendsidi2" 1711 [(set (match_operand:DI 0 "nonimmediate_operand" "") 1712 (zero_extend:DI (match_operand:SI 1 "nonimmediate_src_operand" "")))] 1713 "GET_CODE (operands[0]) != MEM || GET_CODE (operands[1]) != MEM" 1714 "#" 1715 "" 1716 [(set (match_dup 2) 1717 (match_dup 1)) 1718 (set (match_dup 3) 1719 (const_int 0))] 1720{ 1721 operands[2] = gen_lowpart (SImode, operands[0]); 1722 operands[3] = gen_highpart (SImode, operands[0]); 1723}) 1724 1725(define_insn "*zero_extendhisi2_cf" 1726 [(set (match_operand:SI 0 "register_operand" "=d") 1727 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] 1728 "ISA_HAS_MVS_MVZ" 1729 "mvz%.w %1,%0" 1730 [(set_attr "type" "mvsz")]) 1731 1732(define_insn "zero_extendhisi2" 1733 [(set (match_operand:SI 0 "register_operand" "=d") 1734 (zero_extend:SI (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] 1735 "" 1736 "#") 1737 1738(define_expand "zero_extendqihi2" 1739 [(set (match_operand:HI 0 "register_operand" "") 1740 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "")))] 1741 "!TARGET_COLDFIRE" 1742 "") 1743 1744(define_insn "*zero_extendqihi2" 1745 [(set (match_operand:HI 0 "register_operand" "=d") 1746 (zero_extend:HI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))] 1747 "!TARGET_COLDFIRE" 1748 "#") 1749 1750(define_insn "*zero_extendqisi2_cfv4" 1751 [(set (match_operand:SI 0 "register_operand" "=d") 1752 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))] 1753 "ISA_HAS_MVS_MVZ" 1754 "mvz%.b %1,%0" 1755 [(set_attr "type" "mvsz")]) 1756 1757(define_insn "zero_extendqisi2" 1758 [(set (match_operand:SI 0 "register_operand" "=d") 1759 (zero_extend:SI (match_operand:QI 1 "nonimmediate_src_operand" "dmS")))] 1760 "" 1761 "#") 1762 1763;; these two pattern split everything else which isn't matched by 1764;; something else above 1765(define_split 1766 [(set (match_operand 0 "register_operand" "") 1767 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))] 1768 "!ISA_HAS_MVS_MVZ 1769 && reload_completed 1770 && reg_mentioned_p (operands[0], operands[1])" 1771 [(set (strict_low_part (match_dup 2)) 1772 (match_dup 1)) 1773 (set (match_dup 0) 1774 (match_op_dup 4 [(match_dup 0) (match_dup 3)]))] 1775{ 1776 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]); 1777 operands[3] = GEN_INT (GET_MODE_MASK (GET_MODE (operands[1]))); 1778 operands[4] = gen_rtx_AND (GET_MODE (operands[0]), operands[0], operands[3]); 1779}) 1780 1781(define_split 1782 [(set (match_operand 0 "register_operand" "") 1783 (zero_extend (match_operand 1 "nonimmediate_src_operand" "")))] 1784 "!ISA_HAS_MVS_MVZ && reload_completed" 1785 [(set (match_dup 0) 1786 (const_int 0)) 1787 (set (strict_low_part (match_dup 2)) 1788 (match_dup 1))] 1789{ 1790 operands[2] = gen_lowpart (GET_MODE (operands[1]), operands[0]); 1791}) 1792 1793;; sign extension instructions 1794 1795(define_insn "extendqidi2" 1796 [(set (match_operand:DI 0 "nonimmediate_operand" "=d") 1797 (sign_extend:DI (match_operand:QI 1 "general_src_operand" "rmS")))] 1798 "" 1799{ 1800 CC_STATUS_INIT; 1801 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1802 if (ISA_HAS_MVS_MVZ) 1803 return "mvs%.b %1,%2\;smi %0\;extb%.l %0"; 1804 if (TARGET_68020 || TARGET_COLDFIRE) 1805 { 1806 if (ADDRESS_REG_P (operands[1])) 1807 return "move%.w %1,%2\;extb%.l %2\;smi %0\;extb%.l %0"; 1808 else 1809 return "move%.b %1,%2\;extb%.l %2\;smi %0\;extb%.l %0"; 1810 } 1811 else 1812 { 1813 if (ADDRESS_REG_P (operands[1])) 1814 return "move%.w %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0"; 1815 else 1816 return "move%.b %1,%2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0\;smi %0"; 1817 } 1818}) 1819 1820(define_insn "extendhidi2" 1821 [(set (match_operand:DI 0 "nonimmediate_operand" "=d") 1822 (sign_extend:DI 1823 (match_operand:HI 1 "general_src_operand" "rmS")))] 1824 "" 1825{ 1826 CC_STATUS_INIT; 1827 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1828 if (ISA_HAS_MVS_MVZ) 1829 return "mvs%.w %1,%2\;smi %0\;extb%.l %0"; 1830 if (TARGET_68020 || TARGET_COLDFIRE) 1831 return "move%.w %1,%2\;ext%.l %2\;smi %0\;extb%.l %0"; 1832 else 1833 return "move%.w %1,%2\;ext%.l %2\;smi %0\;ext%.w %0\;ext%.l %0"; 1834}) 1835 1836(define_insn "extendsidi2" 1837 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o,o,<") 1838 (sign_extend:DI 1839 (match_operand:SI 1 "nonimmediate_src_operand" "rm,rm,r<Q>,rm"))) 1840 (clobber (match_scratch:SI 2 "=X,d,d,d"))] 1841 "" 1842{ 1843 CC_STATUS_INIT; 1844 1845 if (which_alternative == 0) 1846 /* Handle alternative 0. */ 1847 { 1848 if (TARGET_68020 || TARGET_COLDFIRE) 1849 return "move%.l %1,%R0\;smi %0\;extb%.l %0"; 1850 else 1851 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0"; 1852 } 1853 1854 /* Handle alternatives 1, 2 and 3. We don't need to adjust address by 4 1855 in alternative 3 because autodecrement will do that for us. */ 1856 operands[3] = adjust_address (operands[0], SImode, 1857 which_alternative == 3 ? 0 : 4); 1858 operands[0] = adjust_address (operands[0], SImode, 0); 1859 1860 if (TARGET_68020 || TARGET_COLDFIRE) 1861 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0"; 1862 else 1863 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0"; 1864} 1865 [(set_attr "ok_for_coldfire" "yes,no,yes,yes")]) 1866 1867;; Special case when one can avoid register clobbering, copy and test 1868;; Maybe there is a way to make that the general case, by forcing the 1869;; result of the SI tree to be in the lower register of the DI target 1870 1871(define_insn "extendplussidi" 1872 [(set (match_operand:DI 0 "register_operand" "=d") 1873 (sign_extend:DI (plus:SI (match_operand:SI 1 "general_operand" "%rmn") 1874 (match_operand:SI 2 "general_operand" "rmn"))))] 1875 "" 1876{ 1877 CC_STATUS_INIT; 1878 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1879 if (GET_CODE (operands[1]) == CONST_INT 1880 && (unsigned) INTVAL (operands[1]) > 8) 1881 { 1882 rtx tmp = operands[1]; 1883 1884 operands[1] = operands[2]; 1885 operands[2] = tmp; 1886 } 1887 if (GET_CODE (operands[1]) == REG 1888 && REGNO (operands[1]) == REGNO (operands[3])) 1889 output_asm_insn ("add%.l %2,%3", operands); 1890 else 1891 output_asm_insn ("move%.l %2,%3\;add%.l %1,%3", operands); 1892 if (TARGET_68020 || TARGET_COLDFIRE) 1893 return "smi %0\;extb%.l %0"; 1894 else 1895 return "smi %0\;ext%.w %0\;ext%.l %0"; 1896}) 1897 1898(define_expand "extendhisi2" 1899 [(set (match_operand:SI 0 "nonimmediate_operand" "") 1900 (sign_extend:SI 1901 (match_operand:HI 1 "nonimmediate_src_operand" "")))] 1902 "" 1903 "") 1904 1905(define_insn "*cfv4_extendhisi2" 1906 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 1907 (sign_extend:SI 1908 (match_operand:HI 1 "nonimmediate_src_operand" "rmS")))] 1909 "ISA_HAS_MVS_MVZ" 1910 "mvs%.w %1,%0" 1911 [(set_attr "type" "mvsz")]) 1912 1913(define_insn "*68k_extendhisi2" 1914 [(set (match_operand:SI 0 "nonimmediate_operand" "=*d,a") 1915 (sign_extend:SI 1916 (match_operand:HI 1 "nonimmediate_src_operand" "0,rmS")))] 1917 "!ISA_HAS_MVS_MVZ" 1918 "@ 1919 ext%.l %0 1920 move%.w %1,%0" 1921 [(set_attr "type" "ext,move")]) 1922 1923(define_insn "extendqihi2" 1924 [(set (match_operand:HI 0 "nonimmediate_operand" "=d") 1925 (sign_extend:HI (match_operand:QI 1 "nonimmediate_operand" "0")))] 1926 "" 1927 "ext%.w %0" 1928 [(set_attr "type" "ext")]) 1929 1930(define_expand "extendqisi2" 1931 [(set (match_operand:SI 0 "nonimmediate_operand" "") 1932 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "")))] 1933 "TARGET_68020 || TARGET_COLDFIRE" 1934 "") 1935 1936(define_insn "*cfv4_extendqisi2" 1937 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 1938 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "rms")))] 1939 "ISA_HAS_MVS_MVZ" 1940 "mvs%.b %1,%0" 1941 [(set_attr "type" "mvsz")]) 1942 1943(define_insn "*68k_extendqisi2" 1944 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 1945 (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "0")))] 1946 "TARGET_68020 || (TARGET_COLDFIRE && !ISA_HAS_MVS_MVZ)" 1947 "extb%.l %0" 1948 [(set_attr "type" "ext")]) 1949 1950;; Conversions between float and double. 1951 1952(define_expand "extendsfdf2" 1953 [(set (match_operand:DF 0 "nonimmediate_operand" "") 1954 (float_extend:DF 1955 (match_operand:SF 1 "general_operand" "")))] 1956 "TARGET_HARD_FLOAT" 1957 "") 1958 1959(define_insn "" 1960 [(set (match_operand:DF 0 "nonimmediate_operand" "=*fdm,f") 1961 (float_extend:DF 1962 (match_operand:SF 1 "general_operand" "f,dmF")))] 1963 "TARGET_68881" 1964{ 1965 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) 1966 { 1967 if (REGNO (operands[0]) == REGNO (operands[1])) 1968 { 1969 /* Extending float to double in an fp-reg is a no-op. 1970 NOTICE_UPDATE_CC has already assumed that the 1971 cc will be set. So cancel what it did. */ 1972 cc_status = cc_prev_status; 1973 return ""; 1974 } 1975 return "f%&move%.x %1,%0"; 1976 } 1977 if (FP_REG_P (operands[0])) 1978 return "f%&move%.s %f1,%0"; 1979 if (DATA_REG_P (operands[0]) && FP_REG_P (operands[1])) 1980 { 1981 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands); 1982 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 1983 return "move%.l %+,%0"; 1984 } 1985 return "fmove%.d %f1,%0"; 1986}) 1987 1988(define_insn "extendsfdf2_cf" 1989 [(set (match_operand:DF 0 "nonimmediate_operand" "=f,f") 1990 (float_extend:DF 1991 (match_operand:SF 1 "general_operand" "f,<Q>U")))] 1992 "TARGET_COLDFIRE_FPU" 1993{ 1994 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) 1995 { 1996 if (REGNO (operands[0]) == REGNO (operands[1])) 1997 { 1998 /* Extending float to double in an fp-reg is a no-op. 1999 NOTICE_UPDATE_CC has already assumed that the 2000 cc will be set. So cancel what it did. */ 2001 cc_status = cc_prev_status; 2002 return ""; 2003 } 2004 return "fdmove%.d %1,%0"; 2005 } 2006 return "fdmove%.s %f1,%0"; 2007}) 2008 2009;; This cannot output into an f-reg because there is no way to be 2010;; sure of truncating in that case. 2011(define_expand "truncdfsf2" 2012 [(set (match_operand:SF 0 "nonimmediate_operand" "") 2013 (float_truncate:SF 2014 (match_operand:DF 1 "general_operand" "")))] 2015 "TARGET_HARD_FLOAT" 2016 "") 2017 2018;; On the '040 we can truncate in a register accurately and easily. 2019(define_insn "" 2020 [(set (match_operand:SF 0 "nonimmediate_operand" "=f") 2021 (float_truncate:SF 2022 (match_operand:DF 1 "general_operand" "fmG")))] 2023 "TARGET_68881 && TARGET_68040" 2024{ 2025 if (FP_REG_P (operands[1])) 2026 return "f%$move%.x %1,%0"; 2027 return "f%$move%.d %f1,%0"; 2028}) 2029 2030(define_insn "truncdfsf2_cf" 2031 [(set (match_operand:SF 0 "nonimmediate_operand" "=f,d<Q>U") 2032 (float_truncate:SF 2033 (match_operand:DF 1 "general_operand" "<Q>U,f")))] 2034 "TARGET_COLDFIRE_FPU" 2035 "@ 2036 fsmove%.d %1,%0 2037 fmove%.s %1,%0" 2038 [(set_attr "type" "fmove")]) 2039 2040(define_insn "*truncdfsf2_68881" 2041 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm") 2042 (float_truncate:SF 2043 (match_operand:DF 1 "general_operand" "f")))] 2044 "TARGET_68881" 2045 "fmove%.s %f1,%0" 2046 [(set_attr "type" "fmove")]) 2047 2048;; Conversion between fixed point and floating point. 2049;; Note that among the fix-to-float insns 2050;; the ones that start with SImode come first. 2051;; That is so that an operand that is a CONST_INT 2052;; (and therefore lacks a specific machine mode). 2053;; will be recognized as SImode (which is always valid) 2054;; rather than as QImode or HImode. 2055 2056(define_expand "floatsi<mode>2" 2057 [(set (match_operand:FP 0 "nonimmediate_operand" "") 2058 (float:FP (match_operand:SI 1 "general_operand" "")))] 2059 "TARGET_HARD_FLOAT" 2060 "") 2061 2062(define_insn "floatsi<mode>2_68881" 2063 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2064 (float:FP (match_operand:SI 1 "general_operand" "dmi")))] 2065 "TARGET_68881" 2066 "f<FP:round>move%.l %1,%0" 2067 [(set_attr "type" "fmove")]) 2068 2069(define_insn "floatsi<mode>2_cf" 2070 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2071 (float:FP (match_operand:SI 1 "general_operand" "d<Q>U")))] 2072 "TARGET_COLDFIRE_FPU" 2073 "f<FP:prec>move%.l %1,%0" 2074 [(set_attr "type" "fmove")]) 2075 2076 2077(define_expand "floathi<mode>2" 2078 [(set (match_operand:FP 0 "nonimmediate_operand" "") 2079 (float:FP (match_operand:HI 1 "general_operand" "")))] 2080 "TARGET_HARD_FLOAT" 2081 "") 2082 2083(define_insn "floathi<mode>2_68881" 2084 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2085 (float:FP (match_operand:HI 1 "general_operand" "dmn")))] 2086 "TARGET_68881" 2087 "fmove%.w %1,%0" 2088 [(set_attr "type" "fmove")]) 2089 2090(define_insn "floathi<mode>2_cf" 2091 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2092 (float:FP (match_operand:HI 1 "general_operand" "d<Q>U")))] 2093 "TARGET_COLDFIRE_FPU" 2094 "fmove%.w %1,%0" 2095 [(set_attr "type" "fmove")]) 2096 2097 2098(define_expand "floatqi<mode>2" 2099 [(set (match_operand:FP 0 "nonimmediate_operand" "") 2100 (float:FP (match_operand:QI 1 "general_operand" "")))] 2101 "TARGET_HARD_FLOAT" 2102 "") 2103 2104(define_insn "floatqi<mode>2_68881" 2105 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2106 (float:FP (match_operand:QI 1 "general_operand" "dmn")))] 2107 "TARGET_68881" 2108 "fmove%.b %1,%0" 2109 [(set_attr "type" "fmove")]) 2110 2111(define_insn "floatqi<mode>2_cf" 2112 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2113 (float:FP (match_operand:QI 1 "general_operand" "d<Q>U")))] 2114 "TARGET_COLDFIRE_FPU" 2115 "fmove%.b %1,%0" 2116 [(set_attr "type" "fmove")]) 2117 2118 2119;; New routines to convert floating-point values to integers 2120;; to be used on the '040. These should be faster than trapping 2121;; into the kernel to emulate fintrz. They should also be faster 2122;; than calling the subroutines fixsfsi or fixdfsi. 2123 2124(define_insn "fix_truncdfsi2" 2125 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") 2126 (fix:SI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 2127 (clobber (match_scratch:SI 2 "=d")) 2128 (clobber (match_scratch:SI 3 "=d"))] 2129 "TARGET_68881 && TUNE_68040" 2130{ 2131 CC_STATUS_INIT; 2132 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.l %1,%0\;fmovem%.l %2,%!"; 2133}) 2134 2135(define_insn "fix_truncdfhi2" 2136 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") 2137 (fix:HI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 2138 (clobber (match_scratch:SI 2 "=d")) 2139 (clobber (match_scratch:SI 3 "=d"))] 2140 "TARGET_68881 && TUNE_68040" 2141{ 2142 CC_STATUS_INIT; 2143 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.w %1,%0\;fmovem%.l %2,%!"; 2144}) 2145 2146(define_insn "fix_truncdfqi2" 2147 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") 2148 (fix:QI (fix:DF (match_operand:DF 1 "register_operand" "f")))) 2149 (clobber (match_scratch:SI 2 "=d")) 2150 (clobber (match_scratch:SI 3 "=d"))] 2151 "TARGET_68881 && TUNE_68040" 2152{ 2153 CC_STATUS_INIT; 2154 return "fmovem%.l %!,%2\;moveq #16,%3\;or%.l %2,%3\;and%.w #-33,%3\;fmovem%.l %3,%!\;fmove%.b %1,%0\;fmovem%.l %2,%!"; 2155}) 2156 2157;; Convert a float to a float whose value is an integer. 2158;; This is the first stage of converting it to an integer type. 2159 2160(define_expand "ftrunc<mode>2" 2161 [(set (match_operand:FP 0 "nonimmediate_operand" "") 2162 (fix:FP (match_operand:FP 1 "general_operand" "")))] 2163 "TARGET_HARD_FLOAT && !TUNE_68040" 2164 "") 2165 2166(define_insn "ftrunc<mode>2_68881" 2167 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2168 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))] 2169 "TARGET_68881 && !TUNE_68040" 2170{ 2171 if (FP_REG_P (operands[1])) 2172 return "fintrz%.x %f1,%0"; 2173 return "fintrz%.<FP:prec> %f1,%0"; 2174} 2175 [(set_attr "type" "falu")]) 2176 2177(define_insn "ftrunc<mode>2_cf" 2178 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2179 (fix:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))] 2180 "TARGET_COLDFIRE_FPU" 2181{ 2182 if (FP_REG_P (operands[1])) 2183 return "fintrz%.d %f1,%0"; 2184 return "fintrz%.<FP:prec> %f1,%0"; 2185} 2186 [(set_attr "type" "falu")]) 2187 2188;; Convert a float whose value is an integer 2189;; to an actual integer. Second stage of converting float to integer type. 2190(define_expand "fix<mode>qi2" 2191 [(set (match_operand:QI 0 "nonimmediate_operand" "") 2192 (fix:QI (match_operand:FP 1 "general_operand" "")))] 2193 "TARGET_HARD_FLOAT" 2194 "") 2195 2196(define_insn "fix<mode>qi2_68881" 2197 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") 2198 (fix:QI (match_operand:FP 1 "general_operand" "f")))] 2199 "TARGET_68881" 2200 "fmove%.b %1,%0" 2201 [(set_attr "type" "fmove")]) 2202 2203(define_insn "fix<mode>qi2_cf" 2204 [(set (match_operand:QI 0 "nonimmediate_operand" "=d<Q>U") 2205 (fix:QI (match_operand:FP 1 "general_operand" "f")))] 2206 "TARGET_COLDFIRE_FPU" 2207 "fmove%.b %1,%0" 2208 [(set_attr "type" "fmove")]) 2209 2210(define_expand "fix<mode>hi2" 2211 [(set (match_operand:HI 0 "nonimmediate_operand" "") 2212 (fix:HI (match_operand:FP 1 "general_operand" "")))] 2213 "TARGET_HARD_FLOAT" 2214 "") 2215 2216(define_insn "fix<mode>hi2_68881" 2217 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") 2218 (fix:HI (match_operand:FP 1 "general_operand" "f")))] 2219 "TARGET_68881" 2220 "fmove%.w %1,%0" 2221 [(set_attr "type" "fmove")]) 2222 2223(define_insn "fix<mode>hi2_cf" 2224 [(set (match_operand:HI 0 "nonimmediate_operand" "=d<Q>U") 2225 (fix:HI (match_operand:FP 1 "general_operand" "f")))] 2226 "TARGET_COLDFIRE_FPU" 2227 "fmove%.w %1,%0" 2228 [(set_attr "type" "fmove")]) 2229 2230(define_expand "fix<mode>si2" 2231 [(set (match_operand:SI 0 "nonimmediate_operand" "") 2232 (fix:SI (match_operand:FP 1 "general_operand" "")))] 2233 "TARGET_HARD_FLOAT" 2234 "") 2235 2236(define_insn "fix<mode>si2_68881" 2237 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") 2238 (fix:SI (match_operand:FP 1 "general_operand" "f")))] 2239 "TARGET_68881" 2240 "fmove%.l %1,%0" 2241 [(set_attr "type" "fmove")]) 2242 2243(define_insn "fix<mode>si2_cf" 2244 [(set (match_operand:SI 0 "nonimmediate_operand" "=d<Q>U") 2245 (fix:SI (match_operand:FP 1 "general_operand" "f")))] 2246 "TARGET_COLDFIRE_FPU" 2247 "fmove%.l %1,%0" 2248 [(set_attr "type" "fmove")]) 2249 2250 2251;; add instructions 2252 2253(define_insn "adddi_lshrdi_63" 2254 [(set (match_operand:DI 0 "nonimmediate_operand" "=d") 2255 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "rm") 2256 (const_int 63)) 2257 (match_dup 1))) 2258 (clobber (match_scratch:SI 2 "=d"))] 2259 "" 2260{ 2261 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 2262 if (REG_P (operands[1]) && REGNO (operands[1]) == REGNO (operands[0])) 2263 return 2264 "move%.l %1,%2\;add%.l %2,%2\;subx%.l %2,%2\;sub%.l %2,%3\;subx%.l %2,%0"; 2265 if (GET_CODE (operands[1]) == REG) 2266 operands[4] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 2267 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC 2268 || GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) 2269 operands[4] = operands[1]; 2270 else 2271 operands[4] = adjust_address (operands[1], SImode, 4); 2272 if (GET_CODE (operands[1]) == MEM 2273 && GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) 2274 output_asm_insn ("move%.l %4,%3", operands); 2275 output_asm_insn ("move%.l %1,%0\;smi %2", operands); 2276 if (TARGET_68020 || TARGET_COLDFIRE) 2277 output_asm_insn ("extb%.l %2", operands); 2278 else 2279 output_asm_insn ("ext%.w %2\;ext%.l %2", operands); 2280 if (GET_CODE (operands[1]) != MEM 2281 || GET_CODE (XEXP (operands[1], 0)) != PRE_DEC) 2282 output_asm_insn ("move%.l %4,%3", operands); 2283 return "sub%.l %2,%3\;subx%.l %2,%0"; 2284}) 2285 2286(define_insn "adddi_sexthishl32" 2287 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d") 2288 (plus:DI (ashift:DI (sign_extend:DI 2289 (match_operand:HI 1 "general_operand" "rm,rm,rm,rm")) 2290 (const_int 32)) 2291 (match_operand:DI 2 "general_operand" "0,0,0,0"))) 2292 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))] 2293 "!TARGET_COLDFIRE" 2294{ 2295 CC_STATUS_INIT; 2296 if (ADDRESS_REG_P (operands[0])) 2297 return "add%.w %1,%0"; 2298 else if (ADDRESS_REG_P (operands[3])) 2299 return "move%.w %1,%3\;add%.l %3,%0"; 2300 else 2301 return "move%.w %1,%3\;ext%.l %3\;add%.l %3,%0"; 2302}) 2303 2304(define_insn "*adddi_dilshr32" 2305 [(set (match_operand:DI 0 "nonimmediate_operand" "=d,o") 2306 (plus:DI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro,d") 2307 (const_int 32)) 2308 (match_operand:DI 2 "general_operand" "0,0")))] 2309 "!TARGET_COLDFIRE" 2310{ 2311 CC_STATUS_INIT; 2312 if (GET_CODE (operands[0]) == REG) 2313 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 2314 else 2315 operands[2] = adjust_address (operands[0], SImode, 4); 2316 return "add%.l %1,%2\;negx%.l %0\;neg%.l %0"; 2317}) 2318 2319(define_insn "*adddi_dilshr32_cf" 2320 [(set (match_operand:DI 0 "register_operand" "=d") 2321 (plus:DI (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "ro") 2322 (const_int 32)) 2323 (match_operand:DI 2 "register_operand" "0")))] 2324 "TARGET_COLDFIRE" 2325{ 2326 CC_STATUS_INIT; 2327 return "add%.l %1,%R0\;negx%.l %0\;neg%.l %0"; 2328}) 2329 2330(define_insn "adddi_dishl32" 2331 [(set (match_operand:DI 0 "nonimmediate_operand" "=r,o") 2332;; (plus:DI (match_operand:DI 2 "general_operand" "%0") 2333;; (ashift:DI (match_operand:DI 1 "general_operand" "ro") 2334;; (const_int 32))))] 2335 (plus:DI (ashift:DI (match_operand:DI 1 "general_operand" "ro,d") 2336 (const_int 32)) 2337 (match_operand:DI 2 "general_operand" "0,0")))] 2338 "" 2339{ 2340 CC_STATUS_INIT; 2341 if (GET_CODE (operands[1]) == REG) 2342 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 2343 else 2344 operands[1] = adjust_address (operands[1], SImode, 4); 2345 return "add%.l %1,%0"; 2346} 2347 [(set_attr "type" "alu_l")]) 2348 2349(define_insn "adddi3" 2350 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d") 2351 (plus:DI (match_operand:DI 1 "general_operand" "%0,0,0,0") 2352 (match_operand:DI 2 "general_operand" "d,no>,d,a"))) 2353 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))] 2354 "" 2355{ 2356 if (DATA_REG_P (operands[0])) 2357 { 2358 if (DATA_REG_P (operands[2])) 2359 return "add%.l %R2,%R0\;addx%.l %2,%0"; 2360 else if (GET_CODE (operands[2]) == MEM 2361 && GET_CODE (XEXP (operands[2], 0)) == POST_INC) 2362 return "move%.l %2,%3\;add%.l %2,%R0\;addx%.l %3,%0"; 2363 else 2364 { 2365 rtx high, low; 2366 rtx xoperands[2]; 2367 2368 if (GET_CODE (operands[2]) == REG) 2369 { 2370 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 2371 high = operands[2]; 2372 } 2373 else if (CONSTANT_P (operands[2])) 2374 split_double (operands[2], &high, &low); 2375 else 2376 { 2377 low = adjust_address (operands[2], SImode, 4); 2378 high = operands[2]; 2379 } 2380 2381 operands[1] = low, operands[2] = high; 2382 xoperands[0] = operands[3]; 2383 if (GET_CODE (operands[1]) == CONST_INT 2384 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0) 2385 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1); 2386 else 2387 xoperands[1] = operands[2]; 2388 2389 output_asm_insn (output_move_simode (xoperands), xoperands); 2390 if (GET_CODE (operands[1]) == CONST_INT) 2391 { 2392 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) 2393 return "addq%.l %1,%R0\;addx%.l %3,%0"; 2394 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0) 2395 { 2396 operands[1] = GEN_INT (-INTVAL (operands[1])); 2397 return "subq%.l %1,%R0\;subx%.l %3,%0"; 2398 } 2399 } 2400 return "add%.l %1,%R0\;addx%.l %3,%0"; 2401 } 2402 } 2403 else 2404 { 2405 gcc_assert (GET_CODE (operands[0]) == MEM); 2406 CC_STATUS_INIT; 2407 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) 2408 { 2409 operands[1] = gen_rtx_MEM (SImode, 2410 plus_constant (Pmode, 2411 XEXP(operands[0], 0), -8)); 2412 return "move%.l %0,%3\;add%.l %R2,%0\;addx%.l %2,%3\;move%.l %3,%1"; 2413 } 2414 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 2415 { 2416 operands[1] = XEXP(operands[0], 0); 2417 return "add%.l %R2,%0\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%1"; 2418 } 2419 else 2420 { 2421 operands[1] = adjust_address (operands[0], SImode, 4); 2422 return "add%.l %R2,%1\;move%.l %0,%3\;addx%.l %2,%3\;move%.l %3,%0"; 2423 } 2424 } 2425}) 2426 2427(define_insn "addsi_lshrsi_31" 2428 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,dm,d<Q>") 2429 (plus:SI (lshiftrt:SI (match_operand:SI 1 "general_operand" "rm,r<Q>,rm") 2430 (const_int 31)) 2431 (match_dup 1)))] 2432 "" 2433{ 2434 operands[2] = operands[0]; 2435 operands[3] = gen_label_rtx(); 2436 if (GET_CODE (operands[0]) == MEM) 2437 { 2438 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) 2439 operands[0] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0)); 2440 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 2441 operands[2] = gen_rtx_MEM (SImode, XEXP (XEXP (operands[0], 0), 0)); 2442 } 2443 output_asm_insn ("move%.l %1,%0", operands); 2444 output_asm_insn ("jpl %l3", operands); 2445 output_asm_insn ("addq%.l #1,%2", operands); 2446 (*targetm.asm_out.internal_label) (asm_out_file, "L", 2447 CODE_LABEL_NUMBER (operands[3])); 2448 return ""; 2449} 2450 [(set_attr "ok_for_coldfire" "no,yes,yes")]) 2451 2452(define_expand "addsi3" 2453 [(set (match_operand:SI 0 "nonimmediate_operand" "") 2454 (plus:SI (match_operand:SI 1 "general_operand" "") 2455 (match_operand:SI 2 "general_src_operand" "")))] 2456 "" 2457 "") 2458 2459;; Note that the middle two alternatives are near-duplicates 2460;; in order to handle insns generated by reload. 2461;; This is needed since they are not themselves reloaded, 2462;; so commutativity won't apply to them. 2463(define_insn "*addsi3_internal" 2464 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,?a,?a,d,a") 2465 (plus:SI (match_operand:SI 1 "general_operand" "%0,a,rJK,0,0") 2466 (match_operand:SI 2 "general_src_operand" "dIKLT,rJK,a,mSrIKLT,mSrIKLs")))] 2467 2468 2469 "! TARGET_COLDFIRE" 2470 "* return output_addsi3 (operands);") 2471 2472(define_insn_and_split "*addsi3_5200" 2473 [(set (match_operand:SI 0 "nonimmediate_operand" "=mr,mr,a, m,r, ?a, ?a,?a,?a") 2474 (plus:SI (match_operand:SI 1 "general_operand" "%0, 0, 0, 0,0, a, a, r, a") 2475 (match_operand:SI 2 "general_src_operand" " I, L, JCu,d,mrKi,Cj, r, a, JCu")))] 2476 "TARGET_COLDFIRE" 2477{ 2478 switch (which_alternative) 2479 { 2480 case 0: 2481 return "addq%.l %2,%0"; 2482 2483 case 1: 2484 operands[2] = GEN_INT (- INTVAL (operands[2])); 2485 return "subq%.l %2,%0"; 2486 2487 case 3: 2488 case 4: 2489 return "add%.l %2,%0"; 2490 2491 case 5: 2492 /* move%.l %2,%0\n\tadd%.l %1,%0 */ 2493 return "#"; 2494 2495 case 6: 2496 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; 2497 2498 case 7: 2499 return MOTOROLA ? "lea (%2,%1.l),%0" : "lea %2@(0,%1:l),%0"; 2500 2501 case 2: 2502 case 8: 2503 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; 2504 2505 default: 2506 gcc_unreachable (); 2507 return ""; 2508 } 2509} 2510 "&& reload_completed && (extract_constrain_insn_cached (insn), which_alternative == 5) && !operands_match_p (operands[0], operands[1])" 2511 [(set (match_dup 0) 2512 (match_dup 2)) 2513 (set (match_dup 0) 2514 (plus:SI (match_dup 0) 2515 (match_dup 1)))] 2516 "" 2517 [(set_attr "type" "aluq_l,aluq_l,lea, alu_l,alu_l,*,lea, lea, lea") 2518 (set_attr "opy" "2, 2, *, 2, 2, *,*, *, *") 2519 (set_attr "opy_type" "*, *, mem5,*, *, *,mem6,mem6,mem5")]) 2520 2521(define_insn "" 2522 [(set (match_operand:SI 0 "nonimmediate_operand" "=a") 2523 (plus:SI (match_operand:SI 1 "general_operand" "0") 2524 (sign_extend:SI 2525 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))] 2526 "!TARGET_COLDFIRE" 2527 "add%.w %2,%0") 2528 2529(define_insn "addhi3" 2530 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r") 2531 (plus:HI (match_operand:HI 1 "general_operand" "%0,0") 2532 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))] 2533 "!TARGET_COLDFIRE" 2534{ 2535 if (GET_CODE (operands[2]) == CONST_INT) 2536 { 2537 /* If the constant would be a negative number when interpreted as 2538 HImode, make it negative. This is usually, but not always, done 2539 elsewhere in the compiler. First check for constants out of range, 2540 which could confuse us. */ 2541 2542 if (INTVAL (operands[2]) >= 32768) 2543 operands[2] = GEN_INT (INTVAL (operands[2]) - 65536); 2544 2545 if (INTVAL (operands[2]) > 0 2546 && INTVAL (operands[2]) <= 8) 2547 return "addq%.w %2,%0"; 2548 if (INTVAL (operands[2]) < 0 2549 && INTVAL (operands[2]) >= -8) 2550 { 2551 operands[2] = GEN_INT (- INTVAL (operands[2])); 2552 return "subq%.w %2,%0"; 2553 } 2554 /* On the CPU32 it is faster to use two addqw instructions to 2555 add a small integer (8 < N <= 16) to a register. 2556 Likewise for subqw. */ 2557 if (TUNE_CPU32 && REG_P (operands[0])) 2558 { 2559 if (INTVAL (operands[2]) > 8 2560 && INTVAL (operands[2]) <= 16) 2561 { 2562 operands[2] = GEN_INT (INTVAL (operands[2]) - 8); 2563 return "addq%.w #8,%0\;addq%.w %2,%0"; 2564 } 2565 if (INTVAL (operands[2]) < -8 2566 && INTVAL (operands[2]) >= -16) 2567 { 2568 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); 2569 return "subq%.w #8,%0\;subq%.w %2,%0"; 2570 } 2571 } 2572 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040) 2573 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; 2574 } 2575 return "add%.w %2,%0"; 2576}) 2577 2578;; These insns must use MATCH_DUP instead of the more expected 2579;; use of a matching constraint because the "output" here is also 2580;; an input, so you can't use the matching constraint. That also means 2581;; that you can't use the "%", so you need patterns with the matched 2582;; operand in both positions. 2583 2584(define_insn "" 2585 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) 2586 (plus:HI (match_dup 0) 2587 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))] 2588 "!TARGET_COLDFIRE" 2589{ 2590 if (GET_CODE (operands[1]) == CONST_INT) 2591 { 2592 /* If the constant would be a negative number when interpreted as 2593 HImode, make it negative. This is usually, but not always, done 2594 elsewhere in the compiler. First check for constants out of range, 2595 which could confuse us. */ 2596 2597 if (INTVAL (operands[1]) >= 32768) 2598 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536); 2599 2600 if (INTVAL (operands[1]) > 0 2601 && INTVAL (operands[1]) <= 8) 2602 return "addq%.w %1,%0"; 2603 if (INTVAL (operands[1]) < 0 2604 && INTVAL (operands[1]) >= -8) 2605 { 2606 operands[1] = GEN_INT (- INTVAL (operands[1])); 2607 return "subq%.w %1,%0"; 2608 } 2609 /* On the CPU32 it is faster to use two addqw instructions to 2610 add a small integer (8 < N <= 16) to a register. 2611 Likewise for subqw. */ 2612 if (TUNE_CPU32 && REG_P (operands[0])) 2613 { 2614 if (INTVAL (operands[1]) > 8 2615 && INTVAL (operands[1]) <= 16) 2616 { 2617 operands[1] = GEN_INT (INTVAL (operands[1]) - 8); 2618 return "addq%.w #8,%0\;addq%.w %1,%0"; 2619 } 2620 if (INTVAL (operands[1]) < -8 2621 && INTVAL (operands[1]) >= -16) 2622 { 2623 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8); 2624 return "subq%.w #8,%0\;subq%.w %1,%0"; 2625 } 2626 } 2627 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040) 2628 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0"; 2629 } 2630 return "add%.w %1,%0"; 2631}) 2632 2633(define_insn "" 2634 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) 2635 (plus:HI (match_operand:HI 1 "general_src_operand" "dn,rmSn") 2636 (match_dup 0)))] 2637 "!TARGET_COLDFIRE" 2638{ 2639 if (GET_CODE (operands[1]) == CONST_INT) 2640 { 2641 /* If the constant would be a negative number when interpreted as 2642 HImode, make it negative. This is usually, but not always, done 2643 elsewhere in the compiler. First check for constants out of range, 2644 which could confuse us. */ 2645 2646 if (INTVAL (operands[1]) >= 32768) 2647 operands[1] = GEN_INT (INTVAL (operands[1]) - 65536); 2648 2649 if (INTVAL (operands[1]) > 0 2650 && INTVAL (operands[1]) <= 8) 2651 return "addq%.w %1,%0"; 2652 if (INTVAL (operands[1]) < 0 2653 && INTVAL (operands[1]) >= -8) 2654 { 2655 operands[1] = GEN_INT (- INTVAL (operands[1])); 2656 return "subq%.w %1,%0"; 2657 } 2658 /* On the CPU32 it is faster to use two addqw instructions to 2659 add a small integer (8 < N <= 16) to a register. 2660 Likewise for subqw. */ 2661 if (TUNE_CPU32 && REG_P (operands[0])) 2662 { 2663 if (INTVAL (operands[1]) > 8 2664 && INTVAL (operands[1]) <= 16) 2665 { 2666 operands[1] = GEN_INT (INTVAL (operands[1]) - 8); 2667 return "addq%.w #8,%0\;addq%.w %1,%0"; 2668 } 2669 if (INTVAL (operands[1]) < -8 2670 && INTVAL (operands[1]) >= -16) 2671 { 2672 operands[1] = GEN_INT (- INTVAL (operands[1]) - 8); 2673 return "subq%.w #8,%0\;subq%.w %1,%0"; 2674 } 2675 } 2676 if (ADDRESS_REG_P (operands[0]) && !TUNE_68040) 2677 return MOTOROLA ? "lea (%c1,%0),%0" : "lea %0@(%c1),%0"; 2678 } 2679 return "add%.w %1,%0"; 2680}) 2681 2682(define_insn "addqi3" 2683 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") 2684 (plus:QI (match_operand:QI 1 "general_operand" "%0,0") 2685 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] 2686 "!TARGET_COLDFIRE" 2687{ 2688 if (GET_CODE (operands[2]) == CONST_INT) 2689 { 2690 if (INTVAL (operands[2]) >= 128) 2691 operands[2] = GEN_INT (INTVAL (operands[2]) - 256); 2692 2693 if (INTVAL (operands[2]) > 0 2694 && INTVAL (operands[2]) <= 8) 2695 return "addq%.b %2,%0"; 2696 if (INTVAL (operands[2]) < 0 && INTVAL (operands[2]) >= -8) 2697 { 2698 operands[2] = GEN_INT (- INTVAL (operands[2])); 2699 return "subq%.b %2,%0"; 2700 } 2701 } 2702 return "add%.b %2,%0"; 2703}) 2704 2705(define_insn "" 2706 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) 2707 (plus:QI (match_dup 0) 2708 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] 2709 "!TARGET_COLDFIRE" 2710{ 2711 if (GET_CODE (operands[1]) == CONST_INT) 2712 { 2713 if (INTVAL (operands[1]) >= 128) 2714 operands[1] = GEN_INT (INTVAL (operands[1]) - 256); 2715 2716 if (INTVAL (operands[1]) > 0 2717 && INTVAL (operands[1]) <= 8) 2718 return "addq%.b %1,%0"; 2719 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) 2720 { 2721 operands[1] = GEN_INT (- INTVAL (operands[1])); 2722 return "subq%.b %1,%0"; 2723 } 2724 } 2725 return "add%.b %1,%0"; 2726}) 2727 2728(define_insn "" 2729 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) 2730 (plus:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") 2731 (match_dup 0)))] 2732 "!TARGET_COLDFIRE" 2733{ 2734 if (GET_CODE (operands[1]) == CONST_INT) 2735 { 2736 if (INTVAL (operands[1]) >= 128) 2737 operands[1] = GEN_INT (INTVAL (operands[1]) - 256); 2738 2739 if (INTVAL (operands[1]) > 0 2740 && INTVAL (operands[1]) <= 8) 2741 return "addq%.b %1,%0"; 2742 if (INTVAL (operands[1]) < 0 && INTVAL (operands[1]) >= -8) 2743 { 2744 operands[1] = GEN_INT (- INTVAL (operands[1])); 2745 return "subq%.b %1,%0"; 2746 } 2747 } 2748 return "add%.b %1,%0"; 2749}) 2750 2751(define_expand "add<mode>3" 2752 [(set (match_operand:FP 0 "nonimmediate_operand" "") 2753 (plus:FP (match_operand:FP 1 "general_operand" "") 2754 (match_operand:FP 2 "general_operand" "")))] 2755 "TARGET_HARD_FLOAT" 2756 "") 2757 2758(define_insn "add<mode>3_floatsi_68881" 2759 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2760 (plus:FP (float:FP (match_operand:SI 2 "general_operand" "dmi")) 2761 (match_operand:FP 1 "general_operand" "0")))] 2762 "TARGET_68881" 2763 "f<FP:round>add%.l %2,%0" 2764 [(set_attr "type" "falu") 2765 (set_attr "opy" "2")]) 2766 2767(define_insn "add<mode>3_floathi_68881" 2768 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2769 (plus:FP (float:FP (match_operand:HI 2 "general_operand" "dmn")) 2770 (match_operand:FP 1 "general_operand" "0")))] 2771 "TARGET_68881" 2772 "f<FP:round>add%.w %2,%0" 2773 [(set_attr "type" "falu") 2774 (set_attr "opy" "2")]) 2775 2776(define_insn "add<mode>3_floatqi_68881" 2777 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2778 (plus:FP (float:FP (match_operand:QI 2 "general_operand" "dmn")) 2779 (match_operand:FP 1 "general_operand" "0")))] 2780 "TARGET_68881" 2781 "f<FP:round>add%.b %2,%0" 2782 [(set_attr "type" "falu") 2783 (set_attr "opy" "2")]) 2784 2785(define_insn "add<mode>3_68881" 2786 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2787 (plus:FP (match_operand:FP 1 "general_operand" "%0") 2788 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))] 2789 "TARGET_68881" 2790{ 2791 if (FP_REG_P (operands[2])) 2792 return "f<FP:round>add%.x %2,%0"; 2793 return "f<FP:round>add%.<FP:prec> %f2,%0"; 2794} 2795 [(set_attr "type" "falu") 2796 (set_attr "opy" "2")]) 2797 2798(define_insn "add<mode>3_cf" 2799 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2800 (plus:FP (match_operand:FP 1 "general_operand" "%0") 2801 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))] 2802 "TARGET_COLDFIRE_FPU" 2803{ 2804 if (FP_REG_P (operands[2])) 2805 return "f<FP:prec>add%.d %2,%0"; 2806 return "f<FP:prec>add%.<FP:prec> %2,%0"; 2807} 2808 [(set_attr "type" "falu") 2809 (set_attr "opy" "2")]) 2810 2811;; subtract instructions 2812 2813(define_insn "subdi_sexthishl32" 2814 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,a,*d,*d") 2815 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0") 2816 (ashift:DI (sign_extend:DI (match_operand:HI 2 "general_operand" "rm,rm,rm,rm")) 2817 (const_int 32)))) 2818 (clobber (match_scratch:SI 3 "=&d,X,a,?d"))] 2819 "!TARGET_COLDFIRE" 2820{ 2821 CC_STATUS_INIT; 2822 if (ADDRESS_REG_P (operands[0])) 2823 return "sub%.w %2,%0"; 2824 else if (ADDRESS_REG_P (operands[3])) 2825 return "move%.w %2,%3\;sub%.l %3,%0"; 2826 else 2827 return "move%.w %2,%3\;ext%.l %3\;sub%.l %3,%0"; 2828}) 2829 2830(define_insn "subdi_dishl32" 2831 [(set (match_operand:DI 0 "nonimmediate_operand" "+ro") 2832 (minus:DI (match_dup 0) 2833 (ashift:DI (match_operand:DI 1 "general_operand" "ro") 2834 (const_int 32))))] 2835 "" 2836{ 2837 CC_STATUS_INIT; 2838 if (GET_CODE (operands[1]) == REG) 2839 operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 2840 else 2841 operands[1] = adjust_address (operands[1], SImode, 4); 2842 return "sub%.l %1,%0"; 2843} 2844 [(set_attr "type" "alu_l")]) 2845 2846(define_insn "subdi3" 2847 [(set (match_operand:DI 0 "nonimmediate_operand" "=o<>,d,d,d") 2848 (minus:DI (match_operand:DI 1 "general_operand" "0,0,0,0") 2849 (match_operand:DI 2 "general_operand" "d,no>,d,a"))) 2850 (clobber (match_scratch:SI 3 "=&d,&d,X,&d"))] 2851 "" 2852{ 2853 if (DATA_REG_P (operands[0])) 2854 { 2855 if (DATA_REG_P (operands[2])) 2856 return "sub%.l %R2,%R0\;subx%.l %2,%0"; 2857 else if (GET_CODE (operands[2]) == MEM 2858 && GET_CODE (XEXP (operands[2], 0)) == POST_INC) 2859 { 2860 return "move%.l %2,%3\;sub%.l %2,%R0\;subx%.l %3,%0"; 2861 } 2862 else 2863 { 2864 rtx high, low; 2865 rtx xoperands[2]; 2866 2867 if (GET_CODE (operands[2]) == REG) 2868 { 2869 low = gen_rtx_REG (SImode, REGNO (operands[2]) + 1); 2870 high = operands[2]; 2871 } 2872 else if (CONSTANT_P (operands[2])) 2873 split_double (operands[2], &high, &low); 2874 else 2875 { 2876 low = adjust_address (operands[2], SImode, 4); 2877 high = operands[2]; 2878 } 2879 2880 operands[1] = low, operands[2] = high; 2881 xoperands[0] = operands[3]; 2882 if (GET_CODE (operands[1]) == CONST_INT 2883 && INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0) 2884 xoperands[1] = GEN_INT (-INTVAL (operands[2]) - 1); 2885 else 2886 xoperands[1] = operands[2]; 2887 2888 output_asm_insn (output_move_simode (xoperands), xoperands); 2889 if (GET_CODE (operands[1]) == CONST_INT) 2890 { 2891 if (INTVAL (operands[1]) > 0 && INTVAL (operands[1]) <= 8) 2892 return "subq%.l %1,%R0\;subx%.l %3,%0"; 2893 else if (INTVAL (operands[1]) >= -8 && INTVAL (operands[1]) < 0) 2894 { 2895 operands[1] = GEN_INT (-INTVAL (operands[1])); 2896 return "addq%.l %1,%R0\;addx%.l %3,%0"; 2897 } 2898 } 2899 return "sub%.l %1,%R0\;subx%.l %3,%0"; 2900 } 2901 } 2902 else 2903 { 2904 gcc_assert (GET_CODE (operands[0]) == MEM); 2905 CC_STATUS_INIT; 2906 if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) 2907 { 2908 operands[1] 2909 = gen_rtx_MEM (SImode, plus_constant (Pmode, 2910 XEXP (operands[0], 0), -8)); 2911 return "move%.l %0,%3\;sub%.l %R2,%0\;subx%.l %2,%3\;move%.l %3,%1"; 2912 } 2913 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 2914 { 2915 operands[1] = XEXP(operands[0], 0); 2916 return "sub%.l %R2,%0\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%1"; 2917 } 2918 else 2919 { 2920 operands[1] = adjust_address (operands[0], SImode, 4); 2921 return "sub%.l %R2,%1\;move%.l %0,%3\;subx%.l %2,%3\;move%.l %3,%0"; 2922 } 2923 } 2924}) 2925 2926(define_insn "subsi3" 2927 [(set (match_operand:SI 0 "nonimmediate_operand" "=mda,m,d,a") 2928 (minus:SI (match_operand:SI 1 "general_operand" "0,0,0,0") 2929 (match_operand:SI 2 "general_src_operand" "I,dT,mSrT,mSrs")))] 2930 "" 2931 "@ 2932 subq%.l %2, %0 2933 sub%.l %2,%0 2934 sub%.l %2,%0 2935 sub%.l %2,%0" 2936 [(set_attr "type" "aluq_l,alu_l,alu_l,alu_l") 2937 (set_attr "opy" "2")]) 2938 2939(define_insn "" 2940 [(set (match_operand:SI 0 "nonimmediate_operand" "=a") 2941 (minus:SI (match_operand:SI 1 "general_operand" "0") 2942 (sign_extend:SI 2943 (match_operand:HI 2 "nonimmediate_src_operand" "rmS"))))] 2944 "!TARGET_COLDFIRE" 2945 "sub%.w %2,%0") 2946 2947(define_insn "subhi3" 2948 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,r") 2949 (minus:HI (match_operand:HI 1 "general_operand" "0,0") 2950 (match_operand:HI 2 "general_src_operand" "dn,rmSn")))] 2951 "!TARGET_COLDFIRE" 2952 "sub%.w %2,%0") 2953 2954(define_insn "" 2955 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) 2956 (minus:HI (match_dup 0) 2957 (match_operand:HI 1 "general_src_operand" "dn,rmSn")))] 2958 "!TARGET_COLDFIRE" 2959 "sub%.w %1,%0") 2960 2961(define_insn "subqi3" 2962 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") 2963 (minus:QI (match_operand:QI 1 "general_operand" "0,0") 2964 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] 2965 "!TARGET_COLDFIRE" 2966 "sub%.b %2,%0") 2967 2968(define_insn "" 2969 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) 2970 (minus:QI (match_dup 0) 2971 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] 2972 "!TARGET_COLDFIRE" 2973 "sub%.b %1,%0") 2974 2975(define_expand "sub<mode>3" 2976 [(set (match_operand:FP 0 "nonimmediate_operand" "") 2977 (minus:FP (match_operand:FP 1 "general_operand" "") 2978 (match_operand:FP 2 "general_operand" "")))] 2979 "TARGET_HARD_FLOAT" 2980 "") 2981 2982(define_insn "sub<mode>3_floatsi_68881" 2983 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2984 (minus:FP (match_operand:FP 1 "general_operand" "0") 2985 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))] 2986 "TARGET_68881" 2987 "f<FP:round>sub%.l %2,%0" 2988 [(set_attr "type" "falu") 2989 (set_attr "opy" "2")]) 2990 2991(define_insn "sub<mode>3_floathi_68881" 2992 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 2993 (minus:FP (match_operand:FP 1 "general_operand" "0") 2994 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))] 2995 "TARGET_68881" 2996 "f<FP:round>sub%.w %2,%0" 2997 [(set_attr "type" "falu") 2998 (set_attr "opy" "2")]) 2999 3000(define_insn "sub<mode>3_floatqi_68881" 3001 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3002 (minus:FP (match_operand:FP 1 "general_operand" "0") 3003 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))] 3004 "TARGET_68881" 3005 "f<FP:round>sub%.b %2,%0" 3006 [(set_attr "type" "falu") 3007 (set_attr "opy" "2")]) 3008 3009(define_insn "sub<mode>3_68881" 3010 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3011 (minus:FP (match_operand:FP 1 "general_operand" "0") 3012 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))] 3013 "TARGET_68881" 3014{ 3015 if (FP_REG_P (operands[2])) 3016 return "f<FP:round>sub%.x %2,%0"; 3017 return "f<FP:round>sub%.<FP:prec> %f2,%0"; 3018} 3019 [(set_attr "type" "falu") 3020 (set_attr "opy" "2")]) 3021 3022(define_insn "sub<mode>3_cf" 3023 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3024 (minus:FP (match_operand:FP 1 "general_operand" "0") 3025 (match_operand:FP 2 "general_operand" "f<FP:dreg><Q>U")))] 3026 "TARGET_COLDFIRE_FPU" 3027{ 3028 if (FP_REG_P (operands[2])) 3029 return "f<FP:prec>sub%.d %2,%0"; 3030 return "f<FP:prec>sub%.<FP:prec> %2,%0"; 3031} 3032 [(set_attr "type" "falu") 3033 (set_attr "opy" "2")]) 3034 3035;; multiply instructions 3036 3037(define_insn "mulhi3" 3038 [(set (match_operand:HI 0 "nonimmediate_operand" "=d") 3039 (mult:HI (match_operand:HI 1 "general_operand" "%0") 3040 (match_operand:HI 2 "general_src_operand" "dmSn")))] 3041 "" 3042{ 3043 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0"; 3044} 3045 [(set_attr "type" "mul_w") 3046 (set_attr "opy" "2")]) 3047 3048(define_insn "mulhisi3" 3049 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3050 (mult:SI (sign_extend:SI 3051 (match_operand:HI 1 "nonimmediate_operand" "%0")) 3052 (sign_extend:SI 3053 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))] 3054 "" 3055{ 3056 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0"; 3057} 3058 [(set_attr "type" "mul_w") 3059 (set_attr "opy" "2")]) 3060 3061(define_insn "*mulhisisi3_s" 3062 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3063 (mult:SI (sign_extend:SI 3064 (match_operand:HI 1 "nonimmediate_operand" "%0")) 3065 (match_operand:SI 2 "const_int_operand" "n")))] 3066 "INTVAL (operands[2]) >= -0x8000 && INTVAL (operands[2]) <= 0x7fff" 3067{ 3068 return MOTOROLA ? "muls%.w %2,%0" : "muls %2,%0"; 3069} 3070 [(set_attr "type" "mul_w") 3071 (set_attr "opy" "2")]) 3072 3073(define_expand "mulsi3" 3074 [(set (match_operand:SI 0 "nonimmediate_operand" "") 3075 (mult:SI (match_operand:SI 1 "general_operand" "") 3076 (match_operand:SI 2 "general_operand" "")))] 3077 "TARGET_68020 || TARGET_COLDFIRE" 3078 "") 3079 3080(define_insn "*mulsi3_68020" 3081 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3082 (mult:SI (match_operand:SI 1 "general_operand" "%0") 3083 (match_operand:SI 2 "general_src_operand" "dmSTK")))] 3084 3085 "TARGET_68020" 3086 "muls%.l %2,%0" 3087 [(set_attr "type" "mul_l") 3088 (set_attr "opy" "2")]) 3089 3090(define_insn "*mulsi3_cf" 3091 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3092 (mult:SI (match_operand:SI 1 "general_operand" "%0") 3093 (match_operand:SI 2 "general_operand" "d<Q>")))] 3094 "TARGET_COLDFIRE" 3095 "muls%.l %2,%0" 3096 [(set_attr "type" "mul_l") 3097 (set_attr "opy" "2")]) 3098 3099(define_insn "umulhisi3" 3100 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3101 (mult:SI (zero_extend:SI 3102 (match_operand:HI 1 "nonimmediate_operand" "%0")) 3103 (zero_extend:SI 3104 (match_operand:HI 2 "nonimmediate_src_operand" "dmS"))))] 3105 "" 3106{ 3107 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0"; 3108} 3109 [(set_attr "type" "mul_w") 3110 (set_attr "opy" "2")]) 3111 3112(define_insn "*mulhisisi3_z" 3113 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3114 (mult:SI (zero_extend:SI 3115 (match_operand:HI 1 "nonimmediate_operand" "%0")) 3116 (match_operand:SI 2 "const_int_operand" "n")))] 3117 "INTVAL (operands[2]) >= 0 && INTVAL (operands[2]) <= 0xffff" 3118{ 3119 return MOTOROLA ? "mulu%.w %2,%0" : "mulu %2,%0"; 3120} 3121 [(set_attr "type" "mul_w") 3122 (set_attr "opy" "2")]) 3123 3124;; We need a separate DEFINE_EXPAND for u?mulsidi3 to be able to use the 3125;; proper matching constraint. This is because the matching is between 3126;; the high-numbered word of the DImode operand[0] and operand[1]. 3127;; 3128;; Note: life_analysis() does not keep track of the individual halves of the 3129;; DImode register. To prevent spurious liveness before the u?mulsidi3 insn 3130;; (which causes "uninitialized variable" warnings), we explicitly clobber 3131;; the DImode register. 3132(define_expand "umulsidi3" 3133 [(set (match_operand:DI 0 "register_operand" "") 3134 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) 3135 (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))] 3136 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3137 "") 3138 3139(define_insn_and_split "*umulsidi3_split" 3140 [(set (match_operand:DI 0 "register_operand" "") 3141 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) 3142 (zero_extend:DI (match_operand:SI 2 "register_operand" ""))))] 3143 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3144 "#" 3145 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3146 [(clobber (match_dup 0)) 3147 (parallel 3148 [(set (subreg:SI (match_dup 0) 4) 3149 (mult:SI (match_dup 1) (match_dup 2))) 3150 (set (subreg:SI (match_dup 0) 0) 3151 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 3152 (zero_extend:DI (match_dup 2))) 3153 (const_int 32))))])] 3154 "") 3155 3156(define_insn "" 3157 [(set (match_operand:SI 0 "register_operand" "=d") 3158 (mult:SI (match_operand:SI 1 "register_operand" "%0") 3159 (match_operand:SI 2 "nonimmediate_operand" "dm"))) 3160 (set (match_operand:SI 3 "register_operand" "=d") 3161 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 3162 (zero_extend:DI (match_dup 2))) 3163 (const_int 32))))] 3164 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3165 "mulu%.l %2,%3:%0") 3166 3167; Match immediate case. For 2.4 only match things < 2^31. 3168; It's tricky with larger values in these patterns since we need to match 3169; values between the two parallel multiplies, between a CONST_DOUBLE and 3170; a CONST_INT. 3171(define_insn "" 3172 [(set (match_operand:SI 0 "register_operand" "=d") 3173 (mult:SI (match_operand:SI 1 "register_operand" "%0") 3174 (match_operand:SI 2 "const_int_operand" "n"))) 3175 (set (match_operand:SI 3 "register_operand" "=d") 3176 (truncate:SI (lshiftrt:DI (mult:DI (zero_extend:DI (match_dup 1)) 3177 (match_dup 2)) 3178 (const_int 32))))] 3179 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE 3180 && (unsigned) INTVAL (operands[2]) <= 0x7fffffff" 3181 "mulu%.l %2,%3:%0") 3182 3183(define_expand "mulsidi3" 3184 [(set (match_operand:DI 0 "register_operand" "") 3185 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) 3186 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))] 3187 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3188 "") 3189 3190(define_insn_and_split "*mulsidi3_split" 3191 [(set (match_operand:DI 0 "register_operand" "") 3192 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) 3193 (sign_extend:DI (match_operand:SI 2 "register_operand" ""))))] 3194 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3195 "#" 3196 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3197 [(clobber (match_dup 0)) 3198 (parallel 3199 [(set (subreg:SI (match_dup 0) 4) 3200 (mult:SI (match_dup 1) (match_dup 2))) 3201 (set (subreg:SI (match_dup 0) 0) 3202 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 3203 (sign_extend:DI (match_dup 2))) 3204 (const_int 32))))])] 3205 "") 3206 3207(define_insn "" 3208 [(set (match_operand:SI 0 "register_operand" "=d") 3209 (mult:SI (match_operand:SI 1 "register_operand" "%0") 3210 (match_operand:SI 2 "nonimmediate_operand" "dm"))) 3211 (set (match_operand:SI 3 "register_operand" "=d") 3212 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 3213 (sign_extend:DI (match_dup 2))) 3214 (const_int 32))))] 3215 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3216 "muls%.l %2,%3:%0") 3217 3218(define_insn "" 3219 [(set (match_operand:SI 0 "register_operand" "=d") 3220 (mult:SI (match_operand:SI 1 "register_operand" "%0") 3221 (match_operand:SI 2 "const_int_operand" "n"))) 3222 (set (match_operand:SI 3 "register_operand" "=d") 3223 (truncate:SI (lshiftrt:DI (mult:DI (sign_extend:DI (match_dup 1)) 3224 (match_dup 2)) 3225 (const_int 32))))] 3226 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3227 "muls%.l %2,%3:%0") 3228 3229(define_expand "umulsi3_highpart" 3230 [(parallel 3231 [(set (match_operand:SI 0 "register_operand" "") 3232 (truncate:SI 3233 (lshiftrt:DI 3234 (mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "")) 3235 (zero_extend:DI (match_operand:SI 2 "general_operand" ""))) 3236 (const_int 32)))) 3237 (clobber (match_dup 3))])] 3238 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3239{ 3240 operands[3] = gen_reg_rtx (SImode); 3241 3242 if (GET_CODE (operands[2]) == CONST_INT) 3243 { 3244 operands[2] = immed_double_const (INTVAL (operands[2]) & 0xffffffff, 3245 0, DImode); 3246 3247 /* We have to adjust the operand order for the matching constraints. */ 3248 emit_insn (gen_const_umulsi3_highpart (operands[0], operands[3], 3249 operands[1], operands[2])); 3250 DONE; 3251 } 3252}) 3253 3254(define_insn "" 3255 [(set (match_operand:SI 0 "register_operand" "=d") 3256 (truncate:SI 3257 (lshiftrt:DI 3258 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "%1")) 3259 (zero_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) 3260 (const_int 32)))) 3261 (clobber (match_operand:SI 1 "register_operand" "=d"))] 3262 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3263 "mulu%.l %3,%0:%1") 3264 3265(define_insn "const_umulsi3_highpart" 3266 [(set (match_operand:SI 0 "register_operand" "=d") 3267 (truncate:SI 3268 (lshiftrt:DI 3269 (mult:DI (zero_extend:DI (match_operand:SI 2 "register_operand" "1")) 3270 (match_operand:DI 3 "const_uint32_operand" "n")) 3271 (const_int 32)))) 3272 (clobber (match_operand:SI 1 "register_operand" "=d"))] 3273 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3274 "mulu%.l %3,%0:%1") 3275 3276(define_expand "smulsi3_highpart" 3277 [(parallel 3278 [(set (match_operand:SI 0 "register_operand" "") 3279 (truncate:SI 3280 (lshiftrt:DI 3281 (mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "")) 3282 (sign_extend:DI (match_operand:SI 2 "general_operand" ""))) 3283 (const_int 32)))) 3284 (clobber (match_dup 3))])] 3285 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3286{ 3287 operands[3] = gen_reg_rtx (SImode); 3288 if (GET_CODE (operands[2]) == CONST_INT) 3289 { 3290 /* We have to adjust the operand order for the matching constraints. */ 3291 emit_insn (gen_const_smulsi3_highpart (operands[0], operands[3], 3292 operands[1], operands[2])); 3293 DONE; 3294 } 3295}) 3296 3297(define_insn "" 3298 [(set (match_operand:SI 0 "register_operand" "=d") 3299 (truncate:SI 3300 (lshiftrt:DI 3301 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "%1")) 3302 (sign_extend:DI (match_operand:SI 3 "nonimmediate_operand" "dm"))) 3303 (const_int 32)))) 3304 (clobber (match_operand:SI 1 "register_operand" "=d"))] 3305 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3306 "muls%.l %3,%0:%1") 3307 3308(define_insn "const_smulsi3_highpart" 3309 [(set (match_operand:SI 0 "register_operand" "=d") 3310 (truncate:SI 3311 (lshiftrt:DI 3312 (mult:DI (sign_extend:DI (match_operand:SI 2 "register_operand" "1")) 3313 (match_operand:DI 3 "const_sint32_operand" "n")) 3314 (const_int 32)))) 3315 (clobber (match_operand:SI 1 "register_operand" "=d"))] 3316 "TARGET_68020 && !TUNE_68060 && !TARGET_COLDFIRE" 3317 "muls%.l %3,%0:%1") 3318 3319(define_expand "mul<mode>3" 3320 [(set (match_operand:FP 0 "nonimmediate_operand" "") 3321 (mult:FP (match_operand:FP 1 "general_operand" "") 3322 (match_operand:FP 2 "general_operand" "")))] 3323 "TARGET_HARD_FLOAT" 3324 "") 3325 3326(define_insn "mul<mode>3_floatsi_68881" 3327 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3328 (mult:FP (float:FP (match_operand:SI 2 "general_operand" "dmi")) 3329 (match_operand:FP 1 "general_operand" "0")))] 3330 "TARGET_68881" 3331{ 3332 return TARGET_68040 3333 ? "f<FP:round>mul%.l %2,%0" 3334 : "f<FP:round_mul>mul%.l %2,%0"; 3335} 3336 [(set_attr "type" "fmul") 3337 (set_attr "opy" "2")]) 3338 3339(define_insn "mul<mode>3_floathi_68881" 3340 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3341 (mult:FP (float:FP (match_operand:HI 2 "general_operand" "dmn")) 3342 (match_operand:FP 1 "general_operand" "0")))] 3343 "TARGET_68881" 3344{ 3345 return TARGET_68040 3346 ? "f<FP:round>mul%.w %2,%0" 3347 : "f<FP:round_mul>mul%.w %2,%0"; 3348} 3349 [(set_attr "type" "fmul") 3350 (set_attr "opy" "2")]) 3351 3352(define_insn "mul<mode>3_floatqi_68881" 3353 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3354 (mult:FP (float:FP (match_operand:QI 2 "general_operand" "dmn")) 3355 (match_operand:FP 1 "general_operand" "0")))] 3356 "TARGET_68881" 3357{ 3358 return TARGET_68040 3359 ? "f<FP:round>mul%.b %2,%0" 3360 : "f<FP:round_mul>mul%.b %2,%0"; 3361} 3362 [(set_attr "type" "fmul") 3363 (set_attr "opy" "2")]) 3364 3365(define_insn "muldf_68881" 3366 [(set (match_operand:DF 0 "nonimmediate_operand" "=f") 3367 (mult:DF (match_operand:DF 1 "general_operand" "%0") 3368 (match_operand:DF 2 "general_operand" "fmG")))] 3369 "TARGET_68881" 3370{ 3371 if (GET_CODE (operands[2]) == CONST_DOUBLE 3372 && floating_exact_log2 (operands[2]) && !TUNE_68040_60) 3373 { 3374 int i = floating_exact_log2 (operands[2]); 3375 operands[2] = GEN_INT (i); 3376 return "fscale%.l %2,%0"; 3377 } 3378 if (REG_P (operands[2])) 3379 return "f%&mul%.x %2,%0"; 3380 return "f%&mul%.d %f2,%0"; 3381}) 3382 3383(define_insn "mulsf_68881" 3384 [(set (match_operand:SF 0 "nonimmediate_operand" "=f") 3385 (mult:SF (match_operand:SF 1 "general_operand" "%0") 3386 (match_operand:SF 2 "general_operand" "fdmF")))] 3387 "TARGET_68881" 3388{ 3389 if (FP_REG_P (operands[2])) 3390 return (TARGET_68040 3391 ? "fsmul%.x %2,%0" 3392 : "fsglmul%.x %2,%0"); 3393 return (TARGET_68040 3394 ? "fsmul%.s %f2,%0" 3395 : "fsglmul%.s %f2,%0"); 3396}) 3397 3398(define_insn "mulxf3_68881" 3399 [(set (match_operand:XF 0 "nonimmediate_operand" "=f") 3400 (mult:XF (match_operand:XF 1 "nonimmediate_operand" "%0") 3401 (match_operand:XF 2 "nonimmediate_operand" "fm")))] 3402 "TARGET_68881" 3403{ 3404 return "fmul%.x %f2,%0"; 3405}) 3406 3407(define_insn "fmul<mode>3_cf" 3408 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3409 (mult:FP (match_operand:FP 1 "general_operand" "%0") 3410 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))] 3411 "TARGET_COLDFIRE_FPU" 3412{ 3413 if (FP_REG_P (operands[2])) 3414 return "f<FP:prec>mul%.d %2,%0"; 3415 return "f<FP:prec>mul%.<FP:prec> %2,%0"; 3416} 3417 [(set_attr "type" "fmul") 3418 (set_attr "opy" "2")]) 3419 3420;; divide instructions 3421 3422(define_expand "div<mode>3" 3423 [(set (match_operand:FP 0 "nonimmediate_operand" "") 3424 (div:FP (match_operand:FP 1 "general_operand" "") 3425 (match_operand:FP 2 "general_operand" "")))] 3426 "TARGET_HARD_FLOAT" 3427 "") 3428 3429(define_insn "div<mode>3_floatsi_68881" 3430 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3431 (div:FP (match_operand:FP 1 "general_operand" "0") 3432 (float:FP (match_operand:SI 2 "general_operand" "dmi"))))] 3433 "TARGET_68881" 3434{ 3435 return TARGET_68040 3436 ? "f<FP:round>div%.l %2,%0" 3437 : "f<FP:round_mul>div%.l %2,%0"; 3438}) 3439 3440(define_insn "div<mode>3_floathi_68881" 3441 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3442 (div:FP (match_operand:FP 1 "general_operand" "0") 3443 (float:FP (match_operand:HI 2 "general_operand" "dmn"))))] 3444 "TARGET_68881" 3445{ 3446 return TARGET_68040 3447 ? "f<FP:round>div%.w %2,%0" 3448 : "f<FP:round_mul>div%.w %2,%0"; 3449}) 3450 3451(define_insn "div<mode>3_floatqi_68881" 3452 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3453 (div:FP (match_operand:FP 1 "general_operand" "0") 3454 (float:FP (match_operand:QI 2 "general_operand" "dmn"))))] 3455 "TARGET_68881" 3456{ 3457 return TARGET_68040 3458 ? "f<FP:round>div%.b %2,%0" 3459 : "f<FP:round_mul>div%.b %2,%0"; 3460}) 3461 3462(define_insn "div<mode>3_68881" 3463 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3464 (div:FP (match_operand:FP 1 "general_operand" "0") 3465 (match_operand:FP 2 "general_operand" "f<FP:dreg>m<FP:const>")))] 3466 "TARGET_68881" 3467{ 3468 if (FP_REG_P (operands[2])) 3469 return (TARGET_68040 3470 ? "f<FP:round>div%.x %2,%0" 3471 : "f<FP:round_mul>div%.x %2,%0"); 3472 return (TARGET_68040 3473 ? "f<FP:round>div%.<FP:prec> %f2,%0" 3474 : "f<FP:round_mul>div%.<FP:prec> %f2,%0"); 3475}) 3476 3477(define_insn "div<mode>3_cf" 3478 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 3479 (div:FP (match_operand:FP 1 "general_operand" "0") 3480 (match_operand:FP 2 "general_operand" "f<Q>U<FP:dreg>")))] 3481 "TARGET_COLDFIRE_FPU" 3482{ 3483 if (FP_REG_P (operands[2])) 3484 return "f<FP:prec>div%.d %2,%0"; 3485 return "f<FP:prec>div%.<FP:prec> %2,%0"; 3486} 3487 [(set_attr "type" "fdiv") 3488 (set_attr "opy" "2")]) 3489 3490;; Remainder instructions. 3491 3492(define_expand "divmodsi4" 3493 [(parallel 3494 [(set (match_operand:SI 0 "nonimmediate_operand" "") 3495 (div:SI (match_operand:SI 1 "general_operand" "") 3496 (match_operand:SI 2 "general_src_operand" ""))) 3497 (set (match_operand:SI 3 "nonimmediate_operand" "") 3498 (mod:SI (match_dup 1) (match_dup 2)))])] 3499 "TARGET_68020 || TARGET_CF_HWDIV" 3500 "") 3501 3502(define_insn "" 3503 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3504 (div:SI (match_operand:SI 1 "general_operand" "0") 3505 (match_operand:SI 2 "general_src_operand" "d<Q>U"))) 3506 (set (match_operand:SI 3 "nonimmediate_operand" "=&d") 3507 (mod:SI (match_dup 1) (match_dup 2)))] 3508 "TARGET_CF_HWDIV" 3509{ 3510 if (find_reg_note (insn, REG_UNUSED, operands[3])) 3511 return "divs%.l %2,%0"; 3512 else if (find_reg_note (insn, REG_UNUSED, operands[0])) 3513 return "rems%.l %2,%3:%0"; 3514 else 3515 return "rems%.l %2,%3:%0\;divs%.l %2,%0"; 3516} 3517 [(set_attr "type" "div_l") 3518 (set_attr "opy" "2")]) 3519 3520(define_insn "" 3521 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3522 (div:SI (match_operand:SI 1 "general_operand" "0") 3523 (match_operand:SI 2 "general_src_operand" "dmSTK"))) 3524 (set (match_operand:SI 3 "nonimmediate_operand" "=d") 3525 (mod:SI (match_dup 1) (match_dup 2)))] 3526 "TARGET_68020" 3527{ 3528 if (find_reg_note (insn, REG_UNUSED, operands[3])) 3529 return "divs%.l %2,%0"; 3530 else 3531 return "divsl%.l %2,%3:%0"; 3532}) 3533 3534(define_expand "udivmodsi4" 3535 [(parallel 3536 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3537 (udiv:SI (match_operand:SI 1 "general_operand" "0") 3538 (match_operand:SI 2 "general_src_operand" "dmSTK"))) 3539 (set (match_operand:SI 3 "nonimmediate_operand" "=d") 3540 (umod:SI (match_dup 1) (match_dup 2)))])] 3541 "TARGET_68020 || TARGET_CF_HWDIV" 3542 "") 3543 3544(define_insn "" 3545 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3546 (udiv:SI (match_operand:SI 1 "general_operand" "0") 3547 (match_operand:SI 2 "general_src_operand" "d<Q>U"))) 3548 (set (match_operand:SI 3 "nonimmediate_operand" "=&d") 3549 (umod:SI (match_dup 1) (match_dup 2)))] 3550 "TARGET_CF_HWDIV" 3551{ 3552 if (find_reg_note (insn, REG_UNUSED, operands[3])) 3553 return "divu%.l %2,%0"; 3554 else if (find_reg_note (insn, REG_UNUSED, operands[0])) 3555 return "remu%.l %2,%3:%0"; 3556 else 3557 return "remu%.l %2,%3:%0\;divu%.l %2,%0"; 3558} 3559 [(set_attr "type" "div_l") 3560 (set_attr "opy" "2")]) 3561 3562(define_insn "" 3563 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3564 (udiv:SI (match_operand:SI 1 "general_operand" "0") 3565 (match_operand:SI 2 "general_src_operand" "dmSTK"))) 3566 (set (match_operand:SI 3 "nonimmediate_operand" "=d") 3567 (umod:SI (match_dup 1) (match_dup 2)))] 3568 "TARGET_68020 && !TARGET_COLDFIRE" 3569{ 3570 if (find_reg_note (insn, REG_UNUSED, operands[3])) 3571 return "divu%.l %2,%0"; 3572 else 3573 return "divul%.l %2,%3:%0"; 3574}) 3575 3576(define_insn "divmodhi4" 3577 [(set (match_operand:HI 0 "nonimmediate_operand" "=d") 3578 (div:HI (match_operand:HI 1 "general_operand" "0") 3579 (match_operand:HI 2 "general_src_operand" "dmSKT"))) 3580 (set (match_operand:HI 3 "nonimmediate_operand" "=d") 3581 (mod:HI (match_dup 1) (match_dup 2)))] 3582 "!TARGET_COLDFIRE || TARGET_CF_HWDIV" 3583{ 3584 output_asm_insn (MOTOROLA ? 3585 "ext%.l %0\;divs%.w %2,%0" : 3586 "extl %0\;divs %2,%0", 3587 operands); 3588 if (!find_reg_note(insn, REG_UNUSED, operands[3])) 3589 { 3590 CC_STATUS_INIT; 3591 return "move%.l %0,%3\;swap %3"; 3592 } 3593 else 3594 return ""; 3595}) 3596 3597(define_insn "udivmodhi4" 3598 [(set (match_operand:HI 0 "nonimmediate_operand" "=d") 3599 (udiv:HI (match_operand:HI 1 "general_operand" "0") 3600 (match_operand:HI 2 "general_src_operand" "dmSKT"))) 3601 (set (match_operand:HI 3 "nonimmediate_operand" "=d") 3602 (umod:HI (match_dup 1) (match_dup 2)))] 3603 "!TARGET_COLDFIRE || TARGET_CF_HWDIV" 3604{ 3605 if (ISA_HAS_MVS_MVZ) 3606 output_asm_insn (MOTOROLA ? 3607 "mvz%.w %0,%0\;divu%.w %2,%0" : 3608 "mvz%.w %0,%0\;divu %2,%0", 3609 operands); 3610 else 3611 output_asm_insn (MOTOROLA ? 3612 "and%.l #0xFFFF,%0\;divu%.w %2,%0" : 3613 "and%.l #0xFFFF,%0\;divu %2,%0", 3614 operands); 3615 3616 if (!find_reg_note(insn, REG_UNUSED, operands[3])) 3617 { 3618 CC_STATUS_INIT; 3619 return "move%.l %0,%3\;swap %3"; 3620 } 3621 else 3622 return ""; 3623}) 3624 3625;; logical-and instructions 3626 3627;; Prevent AND from being made with sp. This doesn't exist in the machine 3628;; and reload will cause inefficient code. Since sp is a FIXED_REG, we 3629;; can't allocate pseudos into it. 3630 3631(define_expand "andsi3" 3632 [(set (match_operand:SI 0 "not_sp_operand" "") 3633 (and:SI (match_operand:SI 1 "general_operand" "") 3634 (match_operand:SI 2 "general_src_operand" "")))] 3635 "" 3636 "") 3637 3638;; produced by split operations after reload finished 3639(define_insn "*andsi3_split" 3640 [(set (match_operand:SI 0 "register_operand" "=d") 3641 (and:SI (match_operand:SI 1 "register_operand" "0") 3642 (match_operand:SI 2 "const_int_operand" "i")))] 3643 "reload_completed && !TARGET_COLDFIRE" 3644{ 3645 return output_andsi3 (operands); 3646}) 3647 3648(define_insn "andsi3_internal" 3649 [(set (match_operand:SI 0 "not_sp_operand" "=m,d") 3650 (and:SI (match_operand:SI 1 "general_operand" "%0,0") 3651 (match_operand:SI 2 "general_src_operand" "dKT,dmSM")))] 3652 "!TARGET_COLDFIRE" 3653{ 3654 return output_andsi3 (operands); 3655}) 3656 3657(define_insn "andsi3_5200" 3658 [(set (match_operand:SI 0 "not_sp_operand" "=m,d") 3659 (and:SI (match_operand:SI 1 "general_operand" "%0,0") 3660 (match_operand:SI 2 "general_src_operand" "d,dmsK")))] 3661 "TARGET_COLDFIRE" 3662{ 3663 if (ISA_HAS_MVS_MVZ 3664 && DATA_REG_P (operands[0]) 3665 && GET_CODE (operands[2]) == CONST_INT) 3666 { 3667 if (INTVAL (operands[2]) == 0x000000ff) 3668 return "mvz%.b %0,%0"; 3669 else if (INTVAL (operands[2]) == 0x0000ffff) 3670 return "mvz%.w %0,%0"; 3671 } 3672 return output_andsi3 (operands); 3673}) 3674 3675(define_insn "andhi3" 3676 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d") 3677 (and:HI (match_operand:HI 1 "general_operand" "%0,0") 3678 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))] 3679 "!TARGET_COLDFIRE" 3680 "and%.w %2,%0") 3681 3682(define_insn "" 3683 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) 3684 (and:HI (match_dup 0) 3685 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))] 3686 "!TARGET_COLDFIRE" 3687 "and%.w %1,%0") 3688 3689(define_insn "" 3690 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) 3691 (and:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn") 3692 (match_dup 0)))] 3693 "!TARGET_COLDFIRE" 3694 "and%.w %1,%0") 3695 3696(define_insn "andqi3" 3697 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") 3698 (and:QI (match_operand:QI 1 "general_operand" "%0,0") 3699 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] 3700 "!TARGET_COLDFIRE" 3701 "and%.b %2,%0") 3702 3703(define_insn "" 3704 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) 3705 (and:QI (match_dup 0) 3706 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] 3707 "!TARGET_COLDFIRE" 3708 "and%.b %1,%0") 3709 3710(define_insn "" 3711 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) 3712 (and:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") 3713 (match_dup 0)))] 3714 "!TARGET_COLDFIRE" 3715 "and%.b %1,%0") 3716 3717;; inclusive-or instructions 3718 3719(define_insn "iordi_zext" 3720 [(set (match_operand:DI 0 "nonimmediate_operand" "=o,d") 3721 (ior:DI (zero_extend:DI (match_operand 1 "general_operand" "dn,dmn")) 3722 (match_operand:DI 2 "general_operand" "0,0")))] 3723 "!TARGET_COLDFIRE" 3724{ 3725 int byte_mode; 3726 3727 CC_STATUS_INIT; 3728 if (GET_CODE (operands[0]) == REG) 3729 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 3730 else 3731 operands[0] = adjust_address (operands[0], SImode, 4); 3732 if (GET_MODE (operands[1]) == SImode) 3733 return "or%.l %1,%0"; 3734 byte_mode = (GET_MODE (operands[1]) == QImode); 3735 if (GET_CODE (operands[0]) == MEM) 3736 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode, 3737 byte_mode ? 3 : 2); 3738 if (byte_mode) 3739 return "or%.b %1,%0"; 3740 else 3741 return "or%.w %1,%0"; 3742}) 3743 3744(define_expand "iorsi3" 3745 [(set (match_operand:SI 0 "nonimmediate_operand" "") 3746 (ior:SI (match_operand:SI 1 "general_operand" "") 3747 (match_operand:SI 2 "general_src_operand" "")))] 3748 "" 3749 "") 3750 3751(define_insn "iorsi3_internal" 3752 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d") 3753 (ior:SI (match_operand:SI 1 "general_operand" "%0,0") 3754 (match_operand:SI 2 "general_src_operand" "dKT,dmSMT")))] 3755 "! TARGET_COLDFIRE" 3756{ 3757 return output_iorsi3 (operands); 3758}) 3759 3760(define_insn "iorsi3_5200" 3761 [(set (match_operand:SI 0 "nonimmediate_operand" "=m,d") 3762 (ior:SI (match_operand:SI 1 "general_operand" "%0,0") 3763 (match_operand:SI 2 "general_src_operand" "d,dmsK")))] 3764 "TARGET_COLDFIRE" 3765{ 3766 return output_iorsi3 (operands); 3767}) 3768 3769(define_insn "iorhi3" 3770 [(set (match_operand:HI 0 "nonimmediate_operand" "=m,d") 3771 (ior:HI (match_operand:HI 1 "general_operand" "%0,0") 3772 (match_operand:HI 2 "general_src_operand" "dn,dmSn")))] 3773 "!TARGET_COLDFIRE" 3774 "or%.w %2,%0") 3775 3776(define_insn "" 3777 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) 3778 (ior:HI (match_dup 0) 3779 (match_operand:HI 1 "general_src_operand" "dn,dmSn")))] 3780 "!TARGET_COLDFIRE" 3781 "or%.w %1,%0") 3782 3783(define_insn "" 3784 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+m,d")) 3785 (ior:HI (match_operand:HI 1 "general_src_operand" "dn,dmSn") 3786 (match_dup 0)))] 3787 "!TARGET_COLDFIRE" 3788 "or%.w %1,%0") 3789 3790(define_insn "iorqi3" 3791 [(set (match_operand:QI 0 "nonimmediate_operand" "=m,d") 3792 (ior:QI (match_operand:QI 1 "general_operand" "%0,0") 3793 (match_operand:QI 2 "general_src_operand" "dn,dmSn")))] 3794 "!TARGET_COLDFIRE" 3795 "or%.b %2,%0") 3796 3797(define_insn "" 3798 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) 3799 (ior:QI (match_dup 0) 3800 (match_operand:QI 1 "general_src_operand" "dn,dmSn")))] 3801 "!TARGET_COLDFIRE" 3802 "or%.b %1,%0") 3803 3804(define_insn "" 3805 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+m,d")) 3806 (ior:QI (match_operand:QI 1 "general_src_operand" "dn,dmSn") 3807 (match_dup 0)))] 3808 "!TARGET_COLDFIRE" 3809 "or%.b %1,%0") 3810 3811;; On all 68k models, this makes faster code in a special case. 3812;; See also ashlsi_16, ashrsi_16 and lshrsi_16. 3813 3814(define_insn "iorsi_zexthi_ashl16" 3815 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d") 3816 (ior:SI (zero_extend:SI (match_operand:HI 1 "general_operand" "rmn")) 3817 (ashift:SI (match_operand:SI 2 "general_operand" "or") 3818 (const_int 16))))] 3819 "" 3820{ 3821 CC_STATUS_INIT; 3822 if (GET_CODE (operands[2]) != REG) 3823 operands[2] = adjust_address (operands[2], HImode, 2); 3824 if (GET_CODE (operands[2]) != REG 3825 || REGNO (operands[2]) != REGNO (operands[0])) 3826 output_asm_insn ("move%.w %2,%0", operands); 3827 return "swap %0\;mov%.w %1,%0"; 3828}) 3829 3830(define_insn "iorsi_zext" 3831 [(set (match_operand:SI 0 "nonimmediate_operand" "=o,d") 3832 (ior:SI (zero_extend:SI (match_operand 1 "general_operand" "dn,dmn")) 3833 (match_operand:SI 2 "general_operand" "0,0")))] 3834 "!TARGET_COLDFIRE" 3835{ 3836 int byte_mode; 3837 3838 CC_STATUS_INIT; 3839 byte_mode = (GET_MODE (operands[1]) == QImode); 3840 if (GET_CODE (operands[0]) == MEM) 3841 operands[0] = adjust_address (operands[0], byte_mode ? QImode : HImode, 3842 byte_mode ? 3 : 2); 3843 if (byte_mode) 3844 return "or%.b %1,%0"; 3845 else 3846 return "or%.w %1,%0"; 3847}) 3848 3849;; xor instructions 3850 3851(define_expand "xorsi3" 3852 [(set (match_operand:SI 0 "nonimmediate_operand" "") 3853 (xor:SI (match_operand:SI 1 "general_operand" "") 3854 (match_operand:SI 2 "general_operand" "")))] 3855 "" 3856 "") 3857 3858(define_insn "xorsi3_internal" 3859 [(set (match_operand:SI 0 "nonimmediate_operand" "=do,m") 3860 (xor:SI (match_operand:SI 1 "general_operand" "%0,0") 3861 (match_operand:SI 2 "general_operand" "di,dKT")))] 3862 3863 "!TARGET_COLDFIRE" 3864{ 3865 return output_xorsi3 (operands); 3866}) 3867 3868(define_insn "xorsi3_5200" 3869 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm,d") 3870 (xor:SI (match_operand:SI 1 "general_operand" "%0,0") 3871 (match_operand:SI 2 "general_operand" "d,Ks")))] 3872 "TARGET_COLDFIRE" 3873{ 3874 return output_xorsi3 (operands); 3875}) 3876 3877(define_insn "xorhi3" 3878 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") 3879 (xor:HI (match_operand:HI 1 "general_operand" "%0") 3880 (match_operand:HI 2 "general_operand" "dn")))] 3881 "!TARGET_COLDFIRE" 3882 "eor%.w %2,%0") 3883 3884(define_insn "" 3885 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) 3886 (xor:HI (match_dup 0) 3887 (match_operand:HI 1 "general_operand" "dn")))] 3888 "!TARGET_COLDFIRE" 3889 "eor%.w %1,%0") 3890 3891(define_insn "" 3892 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) 3893 (xor:HI (match_operand:HI 1 "general_operand" "dn") 3894 (match_dup 0)))] 3895 "!TARGET_COLDFIRE" 3896 "eor%.w %1,%0") 3897 3898(define_insn "xorqi3" 3899 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") 3900 (xor:QI (match_operand:QI 1 "general_operand" "%0") 3901 (match_operand:QI 2 "general_operand" "dn")))] 3902 "!TARGET_COLDFIRE" 3903 "eor%.b %2,%0") 3904 3905(define_insn "" 3906 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) 3907 (xor:QI (match_dup 0) 3908 (match_operand:QI 1 "general_operand" "dn")))] 3909 "!TARGET_COLDFIRE" 3910 "eor%.b %1,%0") 3911 3912(define_insn "" 3913 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) 3914 (xor:QI (match_operand:QI 1 "general_operand" "dn") 3915 (match_dup 0)))] 3916 "!TARGET_COLDFIRE" 3917 "eor%.b %1,%0") 3918 3919;; negation instructions 3920 3921(define_expand "negdi2" 3922 [(set (match_operand:DI 0 "nonimmediate_operand" "") 3923 (neg:DI (match_operand:DI 1 "general_operand" "")))] 3924 "" 3925{ 3926 if (TARGET_COLDFIRE) 3927 emit_insn (gen_negdi2_5200 (operands[0], operands[1])); 3928 else 3929 emit_insn (gen_negdi2_internal (operands[0], operands[1])); 3930 DONE; 3931}) 3932 3933(define_insn "negdi2_internal" 3934 [(set (match_operand:DI 0 "nonimmediate_operand" "=<,do,!*a") 3935 (neg:DI (match_operand:DI 1 "general_operand" "0,0,0")))] 3936 "!TARGET_COLDFIRE" 3937{ 3938 if (which_alternative == 0) 3939 return "neg%.l %0\;negx%.l %0"; 3940 if (GET_CODE (operands[0]) == REG) 3941 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 3942 else 3943 operands[1] = adjust_address (operands[0], SImode, 4); 3944 if (ADDRESS_REG_P (operands[0])) 3945 return "exg %/d0,%1\;neg%.l %/d0\;exg %/d0,%1\;exg %/d0,%0\;negx%.l %/d0\;exg %/d0,%0"; 3946 else 3947 return "neg%.l %1\;negx%.l %0"; 3948}) 3949 3950(define_insn "negdi2_5200" 3951 [(set (match_operand:DI 0 "nonimmediate_operand" "=d") 3952 (neg:DI (match_operand:DI 1 "general_operand" "0")))] 3953 "TARGET_COLDFIRE" 3954{ 3955 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 3956 return "neg%.l %1\;negx%.l %0"; 3957}) 3958 3959(define_expand "negsi2" 3960 [(set (match_operand:SI 0 "nonimmediate_operand" "") 3961 (neg:SI (match_operand:SI 1 "general_operand" "")))] 3962 "" 3963{ 3964 if (TARGET_COLDFIRE) 3965 emit_insn (gen_negsi2_5200 (operands[0], operands[1])); 3966 else 3967 emit_insn (gen_negsi2_internal (operands[0], operands[1])); 3968 DONE; 3969}) 3970 3971(define_insn "negsi2_internal" 3972 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") 3973 (neg:SI (match_operand:SI 1 "general_operand" "0")))] 3974 "!TARGET_COLDFIRE" 3975 "neg%.l %0" 3976 [(set_attr "type" "neg_l")]) 3977 3978(define_insn "negsi2_5200" 3979 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 3980 (neg:SI (match_operand:SI 1 "general_operand" "0")))] 3981 "TARGET_COLDFIRE" 3982 "neg%.l %0" 3983 [(set_attr "type" "neg_l")]) 3984 3985(define_insn "neghi2" 3986 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") 3987 (neg:HI (match_operand:HI 1 "general_operand" "0")))] 3988 "!TARGET_COLDFIRE" 3989 "neg%.w %0") 3990 3991(define_insn "" 3992 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) 3993 (neg:HI (match_dup 0)))] 3994 "!TARGET_COLDFIRE" 3995 "neg%.w %0") 3996 3997(define_insn "negqi2" 3998 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") 3999 (neg:QI (match_operand:QI 1 "general_operand" "0")))] 4000 "!TARGET_COLDFIRE" 4001 "neg%.b %0") 4002 4003(define_insn "" 4004 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) 4005 (neg:QI (match_dup 0)))] 4006 "!TARGET_COLDFIRE" 4007 "neg%.b %0") 4008 4009;; If using software floating point, just flip the sign bit. 4010 4011(define_expand "negsf2" 4012 [(set (match_operand:SF 0 "nonimmediate_operand" "") 4013 (neg:SF (match_operand:SF 1 "general_operand" "")))] 4014 "" 4015{ 4016 if (!TARGET_HARD_FLOAT) 4017 { 4018 rtx result; 4019 rtx target; 4020 4021 target = operand_subword_force (operands[0], 0, SFmode); 4022 result = expand_binop (SImode, xor_optab, 4023 operand_subword_force (operands[1], 0, SFmode), 4024 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN); 4025 gcc_assert (result); 4026 4027 if (result != target) 4028 emit_move_insn (result, target); 4029 4030 /* Make a place for REG_EQUAL. */ 4031 emit_move_insn (operands[0], operands[0]); 4032 DONE; 4033 } 4034}) 4035 4036(define_expand "negdf2" 4037 [(set (match_operand:DF 0 "nonimmediate_operand" "") 4038 (neg:DF (match_operand:DF 1 "general_operand" "")))] 4039 "" 4040{ 4041 if (!TARGET_HARD_FLOAT) 4042 { 4043 rtx result; 4044 rtx target; 4045 rtx insns; 4046 4047 start_sequence (); 4048 target = operand_subword (operands[0], 0, 1, DFmode); 4049 result = expand_binop (SImode, xor_optab, 4050 operand_subword_force (operands[1], 0, DFmode), 4051 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN); 4052 gcc_assert (result); 4053 4054 if (result != target) 4055 emit_move_insn (result, target); 4056 4057 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), 4058 operand_subword_force (operands[1], 1, DFmode)); 4059 4060 insns = get_insns (); 4061 end_sequence (); 4062 4063 emit_insn (insns); 4064 DONE; 4065 } 4066}) 4067 4068(define_expand "negxf2" 4069 [(set (match_operand:XF 0 "nonimmediate_operand" "") 4070 (neg:XF (match_operand:XF 1 "nonimmediate_operand" "")))] 4071 "" 4072{ 4073 if (!TARGET_68881) 4074 { 4075 rtx result; 4076 rtx target; 4077 rtx insns; 4078 4079 start_sequence (); 4080 target = operand_subword (operands[0], 0, 1, XFmode); 4081 result = expand_binop (SImode, xor_optab, 4082 operand_subword_force (operands[1], 0, XFmode), 4083 GEN_INT (-2147483647 - 1), target, 0, OPTAB_WIDEN); 4084 gcc_assert (result); 4085 4086 if (result != target) 4087 emit_move_insn (result, target); 4088 4089 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode), 4090 operand_subword_force (operands[1], 1, XFmode)); 4091 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode), 4092 operand_subword_force (operands[1], 2, XFmode)); 4093 4094 insns = get_insns (); 4095 end_sequence (); 4096 4097 emit_insn (insns); 4098 DONE; 4099 } 4100}) 4101 4102(define_insn "neg<mode>2_68881" 4103 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d") 4104 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))] 4105 "TARGET_68881" 4106{ 4107 if (DATA_REG_P (operands[0])) 4108 { 4109 operands[1] = GEN_INT (31); 4110 return "bchg %1,%0"; 4111 } 4112 if (FP_REG_P (operands[1])) 4113 return "f<FP:round>neg%.x %1,%0"; 4114 return "f<FP:round>neg%.<FP:prec> %f1,%0"; 4115}) 4116 4117(define_insn "neg<mode>2_cf" 4118 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d") 4119 (neg:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))] 4120 "TARGET_COLDFIRE_FPU" 4121{ 4122 if (DATA_REG_P (operands[0])) 4123 { 4124 operands[1] = GEN_INT (31); 4125 return "bchg %1,%0"; 4126 } 4127 if (FP_REG_P (operands[1])) 4128 return "f<FP:prec>neg%.d %1,%0"; 4129 return "f<FP:prec>neg%.<FP:prec> %1,%0"; 4130}) 4131 4132;; Sqrt instruction for the 68881 4133 4134(define_expand "sqrt<mode>2" 4135 [(set (match_operand:FP 0 "nonimmediate_operand" "") 4136 (sqrt:FP (match_operand:FP 1 "general_operand" "")))] 4137 "TARGET_HARD_FLOAT" 4138 "") 4139 4140(define_insn "sqrt<mode>2_68881" 4141 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 4142 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m")))] 4143 "TARGET_68881" 4144{ 4145 if (FP_REG_P (operands[1])) 4146 return "f<FP:round>sqrt%.x %1,%0"; 4147 return "f<FP:round>sqrt%.<FP:prec> %1,%0"; 4148} 4149 [(set_attr "type" "fsqrt")]) 4150 4151(define_insn "sqrt<mode>2_cf" 4152 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 4153 (sqrt:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U")))] 4154 "TARGET_COLDFIRE_FPU" 4155{ 4156 if (FP_REG_P (operands[1])) 4157 return "f<FP:prec>sqrt%.d %1,%0"; 4158 return "f<FP:prec>sqrt%.<FP:prec> %1,%0"; 4159} 4160 [(set_attr "type" "fsqrt")]) 4161;; Absolute value instructions 4162;; If using software floating point, just zero the sign bit. 4163 4164(define_expand "abssf2" 4165 [(set (match_operand:SF 0 "nonimmediate_operand" "") 4166 (abs:SF (match_operand:SF 1 "general_operand" "")))] 4167 "" 4168{ 4169 if (!TARGET_HARD_FLOAT) 4170 { 4171 rtx result; 4172 rtx target; 4173 4174 target = operand_subword_force (operands[0], 0, SFmode); 4175 result = expand_binop (SImode, and_optab, 4176 operand_subword_force (operands[1], 0, SFmode), 4177 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN); 4178 gcc_assert (result); 4179 4180 if (result != target) 4181 emit_move_insn (result, target); 4182 4183 /* Make a place for REG_EQUAL. */ 4184 emit_move_insn (operands[0], operands[0]); 4185 DONE; 4186 } 4187}) 4188 4189(define_expand "absdf2" 4190 [(set (match_operand:DF 0 "nonimmediate_operand" "") 4191 (abs:DF (match_operand:DF 1 "general_operand" "")))] 4192 "" 4193{ 4194 if (!TARGET_HARD_FLOAT) 4195 { 4196 rtx result; 4197 rtx target; 4198 rtx insns; 4199 4200 start_sequence (); 4201 target = operand_subword (operands[0], 0, 1, DFmode); 4202 result = expand_binop (SImode, and_optab, 4203 operand_subword_force (operands[1], 0, DFmode), 4204 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN); 4205 gcc_assert (result); 4206 4207 if (result != target) 4208 emit_move_insn (result, target); 4209 4210 emit_move_insn (operand_subword (operands[0], 1, 1, DFmode), 4211 operand_subword_force (operands[1], 1, DFmode)); 4212 4213 insns = get_insns (); 4214 end_sequence (); 4215 4216 emit_insn (insns); 4217 DONE; 4218 } 4219}) 4220 4221(define_expand "absxf2" 4222 [(set (match_operand:XF 0 "nonimmediate_operand" "") 4223 (abs:XF (match_operand:XF 1 "nonimmediate_operand" "")))] 4224 "" 4225{ 4226 if (!TARGET_68881) 4227 { 4228 rtx result; 4229 rtx target; 4230 rtx insns; 4231 4232 start_sequence (); 4233 target = operand_subword (operands[0], 0, 1, XFmode); 4234 result = expand_binop (SImode, and_optab, 4235 operand_subword_force (operands[1], 0, XFmode), 4236 GEN_INT (0x7fffffff), target, 0, OPTAB_WIDEN); 4237 gcc_assert (result); 4238 4239 if (result != target) 4240 emit_move_insn (result, target); 4241 4242 emit_move_insn (operand_subword (operands[0], 1, 1, XFmode), 4243 operand_subword_force (operands[1], 1, XFmode)); 4244 emit_move_insn (operand_subword (operands[0], 2, 1, XFmode), 4245 operand_subword_force (operands[1], 2, XFmode)); 4246 4247 insns = get_insns (); 4248 end_sequence (); 4249 4250 emit_insn (insns); 4251 DONE; 4252 } 4253}) 4254 4255(define_insn "abs<mode>2_68881" 4256 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d") 4257 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg>m<FP:const>,0")))] 4258 "TARGET_68881" 4259{ 4260 if (DATA_REG_P (operands[0])) 4261 { 4262 operands[1] = GEN_INT (31); 4263 return "bclr %1,%0"; 4264 } 4265 if (FP_REG_P (operands[1])) 4266 return "f<FP:round>abs%.x %1,%0"; 4267 return "f<FP:round>abs%.<FP:prec> %f1,%0"; 4268}) 4269 4270(define_insn "abs<mode>2_cf" 4271 [(set (match_operand:FP 0 "nonimmediate_operand" "=f,d") 4272 (abs:FP (match_operand:FP 1 "general_operand" "f<FP:dreg><Q>U,0")))] 4273 "TARGET_COLDFIRE_FPU" 4274{ 4275 if (DATA_REG_P (operands[0])) 4276 { 4277 operands[1] = GEN_INT (31); 4278 return "bclr %1,%0"; 4279 } 4280 if (FP_REG_P (operands[1])) 4281 return "f<FP:prec>abs%.d %1,%0"; 4282 return "f<FP:prec>abs%.<FP:prec> %1,%0"; 4283} 4284 [(set_attr "type" "bitrw,fneg")]) 4285 4286;; bit indexing instructions 4287 4288(define_expand "clzsi2" 4289 [(set (match_operand:SI 0 "register_operand" "") 4290 (clz:SI (match_operand:SI 1 "general_operand" "")))] 4291 "ISA_HAS_FF1 || (TARGET_68020 && TARGET_BITFIELD)" 4292{ 4293 if (ISA_HAS_FF1) 4294 operands[1] = force_reg (SImode, operands[1]); 4295}) 4296 4297(define_insn "*clzsi2_68k" 4298 [(set (match_operand:SI 0 "register_operand" "=d") 4299 (clz:SI (match_operand:SI 1 "general_operand" "do")))] 4300 "TARGET_68020 && TARGET_BITFIELD" 4301{ 4302 CC_STATUS_INIT; 4303 return "bfffo %1{#0:#0},%0"; 4304}) 4305 4306;; ColdFire ff1 instruction implements clz. 4307(define_insn "*clzsi2_cf" 4308 [(set (match_operand:SI 0 "register_operand" "=d") 4309 (clz:SI (match_operand:SI 1 "register_operand" "0")))] 4310 "ISA_HAS_FF1" 4311{ 4312 CC_STATUS_INIT; 4313 return "ff1 %0"; 4314} 4315 [(set_attr "type" "ext")]) 4316 4317;; one complement instructions 4318 4319(define_expand "one_cmplsi2" 4320 [(set (match_operand:SI 0 "nonimmediate_operand" "") 4321 (not:SI (match_operand:SI 1 "general_operand" "")))] 4322 "" 4323{ 4324 if (TARGET_COLDFIRE) 4325 emit_insn (gen_one_cmplsi2_5200 (operands[0], operands[1])); 4326 else 4327 emit_insn (gen_one_cmplsi2_internal (operands[0], operands[1])); 4328 DONE; 4329}) 4330 4331(define_insn "one_cmplsi2_internal" 4332 [(set (match_operand:SI 0 "nonimmediate_operand" "=dm") 4333 (not:SI (match_operand:SI 1 "general_operand" "0")))] 4334 "!TARGET_COLDFIRE" 4335 "not%.l %0") 4336 4337(define_insn "one_cmplsi2_5200" 4338 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 4339 (not:SI (match_operand:SI 1 "general_operand" "0")))] 4340 "TARGET_COLDFIRE" 4341 "not%.l %0" 4342 [(set_attr "type" "neg_l")]) 4343 4344(define_insn "one_cmplhi2" 4345 [(set (match_operand:HI 0 "nonimmediate_operand" "=dm") 4346 (not:HI (match_operand:HI 1 "general_operand" "0")))] 4347 "!TARGET_COLDFIRE" 4348 "not%.w %0") 4349 4350(define_insn "" 4351 [(set (strict_low_part (match_operand:HI 0 "nonimmediate_operand" "+dm")) 4352 (not:HI (match_dup 0)))] 4353 "!TARGET_COLDFIRE" 4354 "not%.w %0") 4355 4356(define_insn "one_cmplqi2" 4357 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") 4358 (not:QI (match_operand:QI 1 "general_operand" "0")))] 4359 "!TARGET_COLDFIRE" 4360 "not%.b %0") 4361 4362(define_insn "" 4363 [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" "+dm")) 4364 (not:QI (match_dup 0)))] 4365 "!TARGET_COLDFIRE" 4366 "not%.b %0") 4367 4368;; arithmetic shift instructions 4369;; We don't need the shift memory by 1 bit instruction 4370 4371(define_insn "ashldi_extsi" 4372 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro") 4373 (ashift:DI 4374 (match_operator:DI 2 "extend_operator" 4375 [(match_operand:SI 1 "general_operand" "rm")]) 4376 (const_int 32)))] 4377 "" 4378{ 4379 CC_STATUS_INIT; 4380 if (GET_CODE (operands[0]) == REG) 4381 operands[2] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 4382 else 4383 operands[2] = adjust_address (operands[0], SImode, 4); 4384 if (ADDRESS_REG_P (operands[0])) 4385 return "move%.l %1,%0\;sub%.l %2,%2"; 4386 else 4387 return "move%.l %1,%0\;clr%.l %2"; 4388}) 4389 4390(define_insn "ashldi_sexthi" 4391 [(set (match_operand:DI 0 "nonimmediate_operand" "=m,a*d") 4392 (ashift:DI (sign_extend:DI (match_operand:HI 1 "general_operand" "rm,rm")) 4393 (const_int 32))) 4394 (clobber (match_scratch:SI 2 "=a,X"))] 4395 "" 4396{ 4397 CC_STATUS_INIT; 4398 if (GET_CODE (operands[0]) == MEM) 4399 { 4400 if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 4401 return "clr%.l %0\;move%.w %1,%2\;move%.l %2,%0"; 4402 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) 4403 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %0"; 4404 else 4405 { 4406 operands[3] = adjust_address (operands[0], SImode, 4); 4407 return "move%.w %1,%2\;move%.l %2,%0\;clr%.l %3"; 4408 } 4409 } 4410 else if (DATA_REG_P (operands[0])) 4411 return "move%.w %1,%0\;ext%.l %0\;clr%.l %R0"; 4412 else 4413 return "move%.w %1,%0\;sub%.l %R0,%R0"; 4414}) 4415 4416(define_insn "*ashldi3_const1" 4417 [(set (match_operand:DI 0 "register_operand" "=d") 4418 (ashift:DI (match_operand:DI 1 "register_operand" "0") 4419 (const_int 1)))] 4420 "!TARGET_COLDFIRE" 4421 "add%.l %R0,%R0\;addx%.l %0,%0") 4422 4423(define_split 4424 [(set (match_operand:DI 0 "register_operand" "") 4425 (ashift:DI (match_operand:DI 1 "register_operand" "") 4426 (const_int 2)))] 4427 "reload_completed && !TARGET_COLDFIRE" 4428 [(set (match_dup 0) 4429 (ashift:DI (match_dup 1) (const_int 1))) 4430 (set (match_dup 0) 4431 (ashift:DI (match_dup 0) (const_int 1)))] 4432 "") 4433 4434(define_split 4435 [(set (match_operand:DI 0 "register_operand" "") 4436 (ashift:DI (match_operand:DI 1 "register_operand" "") 4437 (const_int 3)))] 4438 "reload_completed && !TARGET_COLDFIRE" 4439 [(set (match_dup 0) 4440 (ashift:DI (match_dup 1) (const_int 2))) 4441 (set (match_dup 0) 4442 (ashift:DI (match_dup 0) (const_int 1)))] 4443 "") 4444 4445(define_split 4446 [(set (match_operand:DI 0 "register_operand" "") 4447 (ashift:DI (match_operand:DI 1 "register_operand" "") 4448 (const_int 8)))] 4449 "reload_completed && !TARGET_COLDFIRE" 4450 [(set (match_dup 2) 4451 (rotate:SI (match_dup 2) (const_int 8))) 4452 (set (match_dup 3) 4453 (rotate:SI (match_dup 3) (const_int 8))) 4454 (set (strict_low_part (subreg:QI (match_dup 0) 3)) 4455 (subreg:QI (match_dup 0) 7)) 4456 (set (strict_low_part (subreg:QI (match_dup 0) 7)) 4457 (const_int 0))] 4458{ 4459 operands[2] = gen_highpart (SImode, operands[0]); 4460 operands[3] = gen_lowpart (SImode, operands[0]); 4461}) 4462 4463(define_split 4464 [(set (match_operand:DI 0 "register_operand" "") 4465 (ashift:DI (match_operand:DI 1 "register_operand" "") 4466 (const_int 16)))] 4467 "reload_completed && !TARGET_COLDFIRE" 4468 [(set (match_dup 2) 4469 (rotate:SI (match_dup 2) (const_int 16))) 4470 (set (match_dup 3) 4471 (rotate:SI (match_dup 3) (const_int 16))) 4472 (set (strict_low_part (subreg:HI (match_dup 0) 2)) 4473 (subreg:HI (match_dup 0) 6)) 4474 (set (strict_low_part (subreg:HI (match_dup 0) 6)) 4475 (const_int 0))] 4476{ 4477 operands[2] = gen_highpart (SImode, operands[0]); 4478 operands[3] = gen_lowpart (SImode, operands[0]); 4479}) 4480 4481(define_split 4482 [(set (match_operand:DI 0 "pre_dec_operand" "") 4483 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "") 4484 (const_int 32)))] 4485 "reload_completed" 4486 [(set (match_dup 0) (const_int 0)) 4487 (set (match_dup 0) (match_dup 1))] 4488{ 4489 operands[0] = adjust_address(operands[0], SImode, 0); 4490 operands[1] = gen_lowpart(SImode, operands[1]); 4491}) 4492 4493(define_split 4494 [(set (match_operand:DI 0 "post_inc_operand" "") 4495 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "") 4496 (const_int 32)))] 4497 "reload_completed" 4498 [(set (match_dup 0) (match_dup 1)) 4499 (set (match_dup 0) (const_int 0))] 4500{ 4501 operands[0] = adjust_address(operands[0], SImode, 0); 4502 operands[1] = gen_lowpart(SImode, operands[1]); 4503}) 4504 4505(define_insn_and_split "*ashldi3_const32" 4506 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>") 4507 (ashift:DI (match_operand:DI 1 "nonimmediate_operand" "ro") 4508 (const_int 32)))] 4509 "" 4510 "#" 4511 "&& reload_completed" 4512 [(set (match_dup 4) (match_dup 3)) 4513 (set (match_dup 2) (const_int 0))] 4514 "split_di(operands, 2, operands + 2, operands + 4);") 4515 4516(define_split 4517 [(set (match_operand:DI 0 "register_operand" "") 4518 (ashift:DI (match_operand:DI 1 "register_operand" "") 4519 (match_operand 2 "const_int_operand" "")))] 4520 "reload_completed && !TARGET_COLDFIRE 4521 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40" 4522 [(set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 2))) 4523 (set (match_dup 3) (match_dup 4)) 4524 (set (match_dup 4) (const_int 0))] 4525{ 4526 operands[2] = GEN_INT (INTVAL (operands[2]) - 32); 4527 operands[3] = gen_highpart (SImode, operands[0]); 4528 operands[4] = gen_lowpart (SImode, operands[0]); 4529}) 4530 4531(define_split 4532 [(set (match_operand:DI 0 "register_operand" "") 4533 (ashift:DI (match_operand:DI 1 "register_operand" "") 4534 (const_int 48)))] 4535 "reload_completed && !TARGET_COLDFIRE" 4536 [(set (match_dup 2) (match_dup 3)) 4537 (set (match_dup 2) 4538 (rotate:SI (match_dup 2) (const_int 16))) 4539 (set (match_dup 3) (const_int 0)) 4540 (set (strict_low_part (subreg:HI (match_dup 0) 2)) 4541 (const_int 0))] 4542{ 4543 operands[2] = gen_highpart (SImode, operands[0]); 4544 operands[3] = gen_lowpart (SImode, operands[0]); 4545}) 4546 4547(define_split 4548 [(set (match_operand:DI 0 "register_operand" "") 4549 (ashift:DI (match_operand:DI 1 "register_operand" "") 4550 (match_operand 2 "const_int_operand" "")))] 4551 "reload_completed && !TARGET_COLDFIRE 4552 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 63" 4553 [(set (match_dup 3) (match_dup 2)) 4554 (set (match_dup 4) (ashift:SI (match_dup 4) (match_dup 3))) 4555 (set (match_dup 3) (match_dup 4)) 4556 (set (match_dup 4) (const_int 0))] 4557{ 4558 operands[2] = GEN_INT (INTVAL (operands[2]) - 32); 4559 operands[3] = gen_highpart (SImode, operands[0]); 4560 operands[4] = gen_lowpart (SImode, operands[0]); 4561}) 4562 4563(define_insn "*ashldi3" 4564 [(set (match_operand:DI 0 "register_operand" "=d") 4565 (ashift:DI (match_operand:DI 1 "register_operand" "0") 4566 (match_operand 2 "const_int_operand" "n")))] 4567 "!TARGET_COLDFIRE 4568 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) 4569 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 4570 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" 4571 "#") 4572 4573(define_expand "ashldi3" 4574 [(set (match_operand:DI 0 "register_operand" "") 4575 (ashift:DI (match_operand:DI 1 "register_operand" "") 4576 (match_operand 2 "const_int_operand" "")))] 4577 "!TARGET_COLDFIRE" 4578{ 4579 /* ??? This is a named pattern like this is not allowed to FAIL based 4580 on its operands. */ 4581 if (GET_CODE (operands[2]) != CONST_INT 4582 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) 4583 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 4584 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) 4585 FAIL; 4586}) 4587 4588;; On most 68k models, this makes faster code in a special case. 4589 4590(define_insn "ashlsi_16" 4591 [(set (match_operand:SI 0 "register_operand" "=d") 4592 (ashift:SI (match_operand:SI 1 "register_operand" "0") 4593 (const_int 16)))] 4594 "!TUNE_68060" 4595{ 4596 CC_STATUS_INIT; 4597 return "swap %0\;clr%.w %0"; 4598}) 4599 4600;; ashift patterns : use lsl instead of asl, because lsl always clears the 4601;; overflow bit, so we must not set CC_NO_OVERFLOW. 4602 4603;; On the 68000, this makes faster code in a special case. 4604 4605(define_insn "ashlsi_17_24" 4606 [(set (match_operand:SI 0 "register_operand" "=d") 4607 (ashift:SI (match_operand:SI 1 "register_operand" "0") 4608 (match_operand:SI 2 "const_int_operand" "n")))] 4609 "TUNE_68000_10 4610 && INTVAL (operands[2]) > 16 4611 && INTVAL (operands[2]) <= 24" 4612{ 4613 CC_STATUS_INIT; 4614 4615 operands[2] = GEN_INT (INTVAL (operands[2]) - 16); 4616 return "lsl%.w %2,%0\;swap %0\;clr%.w %0"; 4617}) 4618 4619(define_insn "ashlsi3" 4620 [(set (match_operand:SI 0 "register_operand" "=d") 4621 (ashift:SI (match_operand:SI 1 "register_operand" "0") 4622 (match_operand:SI 2 "general_operand" "dI")))] 4623 "" 4624{ 4625 if (operands[2] == const1_rtx) 4626 { 4627 cc_status.flags = CC_NO_OVERFLOW; 4628 return "add%.l %0,%0"; 4629 } 4630 return "lsl%.l %2,%0"; 4631}) 4632 4633(define_insn "ashlhi3" 4634 [(set (match_operand:HI 0 "register_operand" "=d") 4635 (ashift:HI (match_operand:HI 1 "register_operand" "0") 4636 (match_operand:HI 2 "general_operand" "dI")))] 4637 "!TARGET_COLDFIRE" 4638 "lsl%.w %2,%0") 4639 4640(define_insn "" 4641 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 4642 (ashift:HI (match_dup 0) 4643 (match_operand:HI 1 "general_operand" "dI")))] 4644 "!TARGET_COLDFIRE" 4645 "lsl%.w %1,%0") 4646 4647(define_insn "ashlqi3" 4648 [(set (match_operand:QI 0 "register_operand" "=d") 4649 (ashift:QI (match_operand:QI 1 "register_operand" "0") 4650 (match_operand:QI 2 "general_operand" "dI")))] 4651 "!TARGET_COLDFIRE" 4652 "lsl%.b %2,%0") 4653 4654(define_insn "" 4655 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 4656 (ashift:QI (match_dup 0) 4657 (match_operand:QI 1 "general_operand" "dI")))] 4658 "!TARGET_COLDFIRE" 4659 "lsl%.b %1,%0") 4660 4661;; On most 68k models, this makes faster code in a special case. 4662 4663(define_insn "ashrsi_16" 4664 [(set (match_operand:SI 0 "register_operand" "=d") 4665 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 4666 (const_int 16)))] 4667 "!TUNE_68060" 4668 "swap %0\;ext%.l %0") 4669 4670;; On the 68000, this makes faster code in a special case. 4671 4672(define_insn "" 4673 [(set (match_operand:SI 0 "register_operand" "=d") 4674 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 4675 (match_operand:SI 2 "const_int_operand" "n")))] 4676 "TUNE_68000_10 4677 && INTVAL (operands[2]) > 16 4678 && INTVAL (operands[2]) <= 24" 4679{ 4680 operands[2] = GEN_INT (INTVAL (operands[2]) - 16); 4681 return "swap %0\;asr%.w %2,%0\;ext%.l %0"; 4682}) 4683 4684(define_insn "subreghi1ashrdi_const32" 4685 [(set (match_operand:HI 0 "nonimmediate_operand" "=rm") 4686 (subreg:HI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro") 4687 (const_int 32)) 6))] 4688 "" 4689{ 4690 if (GET_CODE (operands[1]) != REG) 4691 operands[1] = adjust_address (operands[1], HImode, 2); 4692 return "move%.w %1,%0"; 4693} 4694 [(set_attr "type" "move")]) 4695 4696(define_insn "subregsi1ashrdi_const32" 4697 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 4698 (subreg:SI (ashiftrt:DI (match_operand:DI 1 "general_operand" "ro") 4699 (const_int 32)) 4))] 4700 "" 4701{ 4702 return "move%.l %1,%0"; 4703} 4704 [(set_attr "type" "move_l")]) 4705 4706(define_insn "*ashrdi3_const1" 4707 [(set (match_operand:DI 0 "register_operand" "=d") 4708 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 4709 (const_int 1)))] 4710 "!TARGET_COLDFIRE" 4711{ 4712 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 4713 return "asr%.l #1,%0\;roxr%.l #1,%1"; 4714}) 4715 4716(define_split 4717 [(set (match_operand:DI 0 "register_operand" "") 4718 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 4719 (const_int 2)))] 4720 "reload_completed && !TARGET_COLDFIRE" 4721 [(set (match_dup 0) 4722 (ashiftrt:DI (match_dup 1) (const_int 1))) 4723 (set (match_dup 0) 4724 (ashiftrt:DI (match_dup 0) (const_int 1)))] 4725 "") 4726 4727(define_split 4728 [(set (match_operand:DI 0 "register_operand" "") 4729 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 4730 (const_int 3)))] 4731 "reload_completed && !TARGET_COLDFIRE" 4732 [(set (match_dup 0) 4733 (ashiftrt:DI (match_dup 1) (const_int 2))) 4734 (set (match_dup 0) 4735 (ashiftrt:DI (match_dup 0) (const_int 1)))] 4736 "") 4737 4738(define_split 4739 [(set (match_operand:DI 0 "register_operand" "") 4740 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 4741 (const_int 8)))] 4742 "reload_completed && !TARGET_COLDFIRE" 4743 [(set (strict_low_part (subreg:QI (match_dup 0) 7)) 4744 (subreg:QI (match_dup 0) 3)) 4745 (set (match_dup 2) 4746 (ashiftrt:SI (match_dup 2) (const_int 8))) 4747 (set (match_dup 3) 4748 (rotatert:SI (match_dup 3) (const_int 8)))] 4749{ 4750 operands[2] = gen_highpart (SImode, operands[0]); 4751 operands[3] = gen_lowpart (SImode, operands[0]); 4752}) 4753 4754(define_split 4755 [(set (match_operand:DI 0 "register_operand" "") 4756 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 4757 (const_int 16)))] 4758 "reload_completed && !TARGET_COLDFIRE" 4759 [(set (strict_low_part (subreg:HI (match_dup 0) 6)) 4760 (subreg:HI (match_dup 0) 2)) 4761 (set (match_dup 2) 4762 (rotate:SI (match_dup 2) (const_int 16))) 4763 (set (match_dup 3) 4764 (rotate:SI (match_dup 3) (const_int 16))) 4765 (set (match_dup 2) 4766 (sign_extend:SI (subreg:HI (match_dup 2) 2)))] 4767{ 4768 operands[2] = gen_highpart (SImode, operands[0]); 4769 operands[3] = gen_lowpart (SImode, operands[0]); 4770}) 4771 4772(define_insn "*ashrdi_const32" 4773 [(set (match_operand:DI 0 "register_operand" "=d") 4774 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro") 4775 (const_int 32)))] 4776 "" 4777{ 4778 CC_STATUS_INIT; 4779 if (TARGET_68020) 4780 return "move%.l %1,%R0\;smi %0\;extb%.l %0"; 4781 else 4782 return "move%.l %1,%R0\;smi %0\;ext%.w %0\;ext%.l %0"; 4783}) 4784 4785(define_insn "*ashrdi_const32_mem" 4786 [(set (match_operand:DI 0 "memory_operand" "=o,<") 4787 (ashiftrt:DI (match_operand:DI 1 "nonimmediate_src_operand" "ro,ro") 4788 (const_int 32))) 4789 (clobber (match_scratch:SI 2 "=d,d"))] 4790 "" 4791{ 4792 CC_STATUS_INIT; 4793 operands[3] = adjust_address (operands[0], SImode, 4794 which_alternative == 0 ? 4 : 0); 4795 operands[0] = adjust_address (operands[0], SImode, 0); 4796 if (TARGET_68020 || TARGET_COLDFIRE) 4797 return "move%.l %1,%3\;smi %2\;extb%.l %2\;move%.l %2,%0"; 4798 else 4799 return "move%.l %1,%3\;smi %2\;ext%.w %2\;ext%.l %2\;move%.l %2,%0"; 4800}) 4801 4802(define_split 4803 [(set (match_operand:DI 0 "register_operand" "") 4804 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 4805 (const_int 63)))] 4806 "reload_completed && !TARGET_COLDFIRE" 4807 [(set (match_dup 3) 4808 (ashiftrt:SI (match_dup 3) (const_int 31))) 4809 (set (match_dup 2) 4810 (match_dup 3))] 4811 "split_di(operands, 1, operands + 2, operands + 3);") 4812 4813;; The predicate below must be general_operand, because ashrdi3 allows that 4814(define_insn "ashrdi_const" 4815 [(set (match_operand:DI 0 "register_operand" "=d") 4816 (ashiftrt:DI (match_operand:DI 1 "register_operand" "0") 4817 (match_operand 2 "const_int_operand" "n")))] 4818 "!TARGET_COLDFIRE 4819 && ((INTVAL (operands[2]) >= 1 && INTVAL (operands[2]) <= 3) 4820 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 4821 || INTVAL (operands[2]) == 31 4822 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63))" 4823{ 4824 operands[1] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 4825 CC_STATUS_INIT; 4826 if (INTVAL (operands[2]) == 48) 4827 return "swap %0\;ext%.l %0\;move%.l %0,%1\;smi %0\;ext%.w %0"; 4828 if (INTVAL (operands[2]) == 31) 4829 return "add%.l %1,%1\;addx%.l %0,%0\;move%.l %0,%1\;subx%.l %0,%0"; 4830 if (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63) 4831 { 4832 operands[2] = GEN_INT (INTVAL (operands[2]) - 32); 4833 output_asm_insn (INTVAL (operands[2]) <= 8 ? "asr%.l %2,%0" : 4834 "moveq %2,%1\;asr%.l %1,%0", operands); 4835 output_asm_insn ("mov%.l %0,%1\;smi %0", operands); 4836 return INTVAL (operands[2]) >= 15 ? "ext%.w %d0" : 4837 TARGET_68020 ? "extb%.l %0" : "ext%.w %0\;ext%.l %0"; 4838 } 4839 return "#"; 4840}) 4841 4842(define_expand "ashrdi3" 4843 [(set (match_operand:DI 0 "register_operand" "") 4844 (ashiftrt:DI (match_operand:DI 1 "register_operand" "") 4845 (match_operand 2 "const_int_operand" "")))] 4846 "!TARGET_COLDFIRE" 4847{ 4848 /* ??? This is a named pattern like this is not allowed to FAIL based 4849 on its operands. */ 4850 if (GET_CODE (operands[2]) != CONST_INT 4851 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) 4852 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 4853 && (INTVAL (operands[2]) < 31 || INTVAL (operands[2]) > 63))) 4854 FAIL; 4855}) 4856 4857;; On all 68k models, this makes faster code in a special case. 4858 4859(define_insn "ashrsi_31" 4860 [(set (match_operand:SI 0 "register_operand" "=d") 4861 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 4862 (const_int 31)))] 4863 "" 4864{ 4865 return "add%.l %0,%0\;subx%.l %0,%0"; 4866}) 4867 4868(define_insn "ashrsi3" 4869 [(set (match_operand:SI 0 "register_operand" "=d") 4870 (ashiftrt:SI (match_operand:SI 1 "register_operand" "0") 4871 (match_operand:SI 2 "general_operand" "dI")))] 4872 "" 4873 "asr%.l %2,%0" 4874 [(set_attr "type" "shift") 4875 (set_attr "opy" "2")]) 4876 4877(define_insn "ashrhi3" 4878 [(set (match_operand:HI 0 "register_operand" "=d") 4879 (ashiftrt:HI (match_operand:HI 1 "register_operand" "0") 4880 (match_operand:HI 2 "general_operand" "dI")))] 4881 "!TARGET_COLDFIRE" 4882 "asr%.w %2,%0") 4883 4884(define_insn "" 4885 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 4886 (ashiftrt:HI (match_dup 0) 4887 (match_operand:HI 1 "general_operand" "dI")))] 4888 "!TARGET_COLDFIRE" 4889 "asr%.w %1,%0") 4890 4891(define_insn "ashrqi3" 4892 [(set (match_operand:QI 0 "register_operand" "=d") 4893 (ashiftrt:QI (match_operand:QI 1 "register_operand" "0") 4894 (match_operand:QI 2 "general_operand" "dI")))] 4895 "!TARGET_COLDFIRE" 4896 "asr%.b %2,%0") 4897 4898(define_insn "" 4899 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 4900 (ashiftrt:QI (match_dup 0) 4901 (match_operand:QI 1 "general_operand" "dI")))] 4902 "!TARGET_COLDFIRE" 4903 "asr%.b %1,%0") 4904 4905;; logical shift instructions 4906 4907;; commented out because of reload problems in 950612-1.c 4908;;(define_insn "" 4909;; [(set (cc0) 4910;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro") 4911;; (const_int 32)) 4)) 4912;; (set (match_operand:SI 1 "nonimmediate_operand" "=dm") 4913;; (subreg:SI (lshiftrt:DI (match_dup 0) 4914;; (const_int 32)) 4))] 4915;; "" 4916;;{ 4917;; return "move%.l %0,%1"; 4918;;}) 4919;; 4920;;(define_insn "" 4921;; [(set (cc0) 4922;; (subreg:SI (lshiftrt:DI (match_operand:DI 0 "general_operand" "ro") 4923;; (const_int 32)) 0)) 4924;; (set (match_operand:DI 1 "nonimmediate_operand" "=do") 4925;; (lshiftrt:DI (match_dup 0) 4926;; (const_int 32)))] 4927;; "" 4928;;{ 4929;; if (GET_CODE (operands[1]) == REG) 4930;; operands[2] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 4931;; else 4932;; operands[2] = adjust_address (operands[1], SImode, 4); 4933;; return "move%.l %0,%2\;clr%.l %1"; 4934;;}) 4935 4936(define_insn "subreg1lshrdi_const32" 4937 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 4938 (subreg:SI (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro") 4939 (const_int 32)) 4))] 4940 "" 4941 "move%.l %1,%0" 4942 [(set_attr "type" "move_l")]) 4943 4944(define_insn "*lshrdi3_const1" 4945 [(set (match_operand:DI 0 "register_operand" "=d") 4946 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 4947 (const_int 1)))] 4948 "!TARGET_COLDFIRE" 4949 "lsr%.l #1,%0\;roxr%.l #1,%R0") 4950 4951(define_split 4952 [(set (match_operand:DI 0 "register_operand" "") 4953 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 4954 (const_int 2)))] 4955 "reload_completed && !TARGET_COLDFIRE" 4956 [(set (match_dup 0) 4957 (lshiftrt:DI (match_dup 1) (const_int 1))) 4958 (set (match_dup 0) 4959 (lshiftrt:DI (match_dup 0) (const_int 1)))] 4960 "") 4961 4962(define_split 4963 [(set (match_operand:DI 0 "register_operand" "") 4964 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 4965 (const_int 3)))] 4966 "reload_completed && !TARGET_COLDFIRE" 4967 [(set (match_dup 0) 4968 (lshiftrt:DI (match_dup 1) (const_int 2))) 4969 (set (match_dup 0) 4970 (lshiftrt:DI (match_dup 0) (const_int 1)))] 4971 "") 4972 4973(define_split 4974 [(set (match_operand:DI 0 "register_operand" "") 4975 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 4976 (const_int 8)))] 4977 "reload_completed && !TARGET_COLDFIRE" 4978 [(set (strict_low_part (subreg:QI (match_dup 0) 7)) 4979 (subreg:QI (match_dup 0) 3)) 4980 (set (match_dup 2) 4981 (lshiftrt:SI (match_dup 2) (const_int 8))) 4982 (set (match_dup 3) 4983 (rotatert:SI (match_dup 3) (const_int 8)))] 4984{ 4985 operands[2] = gen_highpart (SImode, operands[0]); 4986 operands[3] = gen_lowpart (SImode, operands[0]); 4987}) 4988 4989(define_split 4990 [(set (match_operand:DI 0 "register_operand" "") 4991 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 4992 (const_int 16)))] 4993 "reload_completed && !TARGET_COLDFIRE" 4994 [(set (strict_low_part (subreg:HI (match_dup 0) 6)) 4995 (subreg:HI (match_dup 0) 2)) 4996 (set (strict_low_part (subreg:HI (match_dup 0) 2)) 4997 (const_int 0)) 4998 (set (match_dup 3) 4999 (rotate:SI (match_dup 3) (const_int 16))) 5000 (set (match_dup 2) 5001 (rotate:SI (match_dup 2) (const_int 16)))] 5002{ 5003 operands[2] = gen_highpart (SImode, operands[0]); 5004 operands[3] = gen_lowpart (SImode, operands[0]); 5005}) 5006 5007(define_split 5008 [(set (match_operand:DI 0 "pre_dec_operand" "") 5009 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "") 5010 (const_int 32)))] 5011 "reload_completed" 5012 [(set (match_dup 0) (match_dup 1)) 5013 (set (match_dup 0) (const_int 0))] 5014{ 5015 operands[0] = adjust_address(operands[0], SImode, 0); 5016 operands[1] = gen_highpart(SImode, operands[1]); 5017}) 5018 5019(define_split 5020 [(set (match_operand:DI 0 "post_inc_operand" "") 5021 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "") 5022 (const_int 32)))] 5023 "reload_completed" 5024 [(set (match_dup 0) (const_int 0)) 5025 (set (match_dup 0) (match_dup 1))] 5026{ 5027 operands[0] = adjust_address(operands[0], SImode, 0); 5028 operands[1] = gen_highpart(SImode, operands[1]); 5029}) 5030 5031(define_split 5032 [(set (match_operand:DI 0 "nonimmediate_operand" "") 5033 (lshiftrt:DI (match_operand:DI 1 "nonimmediate_operand" "") 5034 (const_int 32)))] 5035 "reload_completed" 5036 [(set (match_dup 2) (match_dup 5)) 5037 (set (match_dup 4) (const_int 0))] 5038 "split_di(operands, 2, operands + 2, operands + 4);") 5039 5040(define_insn "*lshrdi_const32" 5041 [(set (match_operand:DI 0 "nonimmediate_operand" "=ro<>") 5042 (lshiftrt:DI (match_operand:DI 1 "general_operand" "ro") 5043 (const_int 32)))] 5044 "" 5045 "#") 5046 5047(define_split 5048 [(set (match_operand:DI 0 "register_operand" "") 5049 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 5050 (match_operand 2 "const_int_operand" "")))] 5051 "reload_completed && !TARGET_COLDFIRE 5052 && INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 40" 5053 [(set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 2))) 5054 (set (match_dup 4) (match_dup 3)) 5055 (set (match_dup 3) (const_int 0))] 5056{ 5057 operands[2] = GEN_INT (INTVAL (operands[2]) - 32); 5058 operands[3] = gen_highpart (SImode, operands[0]); 5059 operands[4] = gen_lowpart (SImode, operands[0]); 5060}) 5061 5062(define_split 5063 [(set (match_operand:DI 0 "register_operand" "") 5064 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 5065 (const_int 48)))] 5066 "reload_completed" 5067 [(set (match_dup 3) (match_dup 2)) 5068 (set (strict_low_part (subreg:HI (match_dup 0) 6)) 5069 (const_int 0)) 5070 (set (match_dup 2) (const_int 0)) 5071 (set (match_dup 3) 5072 (rotate:SI (match_dup 3) (const_int 16)))] 5073{ 5074 operands[2] = gen_highpart (SImode, operands[0]); 5075 operands[3] = gen_lowpart (SImode, operands[0]); 5076}) 5077 5078(define_split 5079 [(set (match_operand:DI 0 "register_operand" "") 5080 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 5081 (match_operand 2 "const_int_operand" "")))] 5082 "reload_completed && !TARGET_COLDFIRE 5083 && INTVAL (operands[2]) > 40 && INTVAL (operands[2]) <= 62" 5084 [(set (match_dup 4) (match_dup 2)) 5085 (set (match_dup 3) (lshiftrt:SI (match_dup 3) (match_dup 4))) 5086 (set (match_dup 4) (match_dup 3)) 5087 (set (match_dup 3) (const_int 0))] 5088{ 5089 operands[2] = GEN_INT (INTVAL (operands[2]) - 32); 5090 operands[3] = gen_highpart (SImode, operands[0]); 5091 operands[4] = gen_lowpart (SImode, operands[0]); 5092}) 5093 5094(define_insn "*lshrdi_const63" 5095 [(set (match_operand:DI 0 "register_operand" "=d") 5096 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 5097 (const_int 63)))] 5098 "" 5099 "add%.l %0,%0\;clr%.l %0\;clr%.l %R1\;addx%.l %R1,%R1") 5100 5101(define_insn "*lshrdi3_const" 5102 [(set (match_operand:DI 0 "register_operand" "=d") 5103 (lshiftrt:DI (match_operand:DI 1 "register_operand" "0") 5104 (match_operand 2 "const_int_operand" "n")))] 5105 "(!TARGET_COLDFIRE 5106 && ((INTVAL (operands[2]) >= 2 && INTVAL (operands[2]) <= 3) 5107 || INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16 5108 || (INTVAL (operands[2]) > 32 && INTVAL (operands[2]) <= 63)))" 5109 "#") 5110 5111(define_expand "lshrdi3" 5112 [(set (match_operand:DI 0 "register_operand" "") 5113 (lshiftrt:DI (match_operand:DI 1 "register_operand" "") 5114 (match_operand 2 "const_int_operand" "")))] 5115 "!TARGET_COLDFIRE" 5116{ 5117 /* ??? This is a named pattern like this is not allowed to FAIL based 5118 on its operands. */ 5119 if (GET_CODE (operands[2]) != CONST_INT 5120 || ((INTVAL (operands[2]) < 1 || INTVAL (operands[2]) > 3) 5121 && INTVAL (operands[2]) != 8 && INTVAL (operands[2]) != 16 5122 && (INTVAL (operands[2]) < 32 || INTVAL (operands[2]) > 63))) 5123 FAIL; 5124}) 5125 5126;; On all 68k models, this makes faster code in a special case. 5127 5128(define_insn "lshrsi_31" 5129 [(set (match_operand:SI 0 "register_operand" "=d") 5130 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 5131 (const_int 31)))] 5132 "" 5133{ 5134 return "add%.l %0,%0\;subx%.l %0,%0\;neg%.l %0"; 5135}) 5136 5137;; On most 68k models, this makes faster code in a special case. 5138 5139(define_insn "lshrsi_16" 5140 [(set (match_operand:SI 0 "register_operand" "=d") 5141 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 5142 (const_int 16)))] 5143 "!TUNE_68060" 5144{ 5145 CC_STATUS_INIT; 5146 return "clr%.w %0\;swap %0"; 5147}) 5148 5149;; On the 68000, this makes faster code in a special case. 5150 5151(define_insn "lshrsi_17_24" 5152 [(set (match_operand:SI 0 "register_operand" "=d") 5153 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 5154 (match_operand:SI 2 "const_int_operand" "n")))] 5155 "TUNE_68000_10 5156 && INTVAL (operands[2]) > 16 5157 && INTVAL (operands[2]) <= 24" 5158{ 5159 /* I think lsr%.w sets the CC properly. */ 5160 operands[2] = GEN_INT (INTVAL (operands[2]) - 16); 5161 return "clr%.w %0\;swap %0\;lsr%.w %2,%0"; 5162}) 5163 5164(define_insn "lshrsi3" 5165 [(set (match_operand:SI 0 "register_operand" "=d") 5166 (lshiftrt:SI (match_operand:SI 1 "register_operand" "0") 5167 (match_operand:SI 2 "general_operand" "dI")))] 5168 "" 5169 "lsr%.l %2,%0" 5170 [(set_attr "type" "shift") 5171 (set_attr "opy" "2")]) 5172 5173(define_insn "lshrhi3" 5174 [(set (match_operand:HI 0 "register_operand" "=d") 5175 (lshiftrt:HI (match_operand:HI 1 "register_operand" "0") 5176 (match_operand:HI 2 "general_operand" "dI")))] 5177 "!TARGET_COLDFIRE" 5178 "lsr%.w %2,%0") 5179 5180(define_insn "" 5181 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 5182 (lshiftrt:HI (match_dup 0) 5183 (match_operand:HI 1 "general_operand" "dI")))] 5184 "!TARGET_COLDFIRE" 5185 "lsr%.w %1,%0") 5186 5187(define_insn "lshrqi3" 5188 [(set (match_operand:QI 0 "register_operand" "=d") 5189 (lshiftrt:QI (match_operand:QI 1 "register_operand" "0") 5190 (match_operand:QI 2 "general_operand" "dI")))] 5191 "!TARGET_COLDFIRE" 5192 "lsr%.b %2,%0") 5193 5194(define_insn "" 5195 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 5196 (lshiftrt:QI (match_dup 0) 5197 (match_operand:QI 1 "general_operand" "dI")))] 5198 "!TARGET_COLDFIRE" 5199 "lsr%.b %1,%0") 5200 5201;; rotate instructions 5202 5203(define_insn "rotlsi_16" 5204 [(set (match_operand:SI 0 "register_operand" "=d") 5205 (rotate:SI (match_operand:SI 1 "register_operand" "0") 5206 (const_int 16)))] 5207 "" 5208 "swap %0" 5209 [(set_attr "type" "shift")]) 5210 5211(define_insn "rotlsi3" 5212 [(set (match_operand:SI 0 "register_operand" "=d") 5213 (rotate:SI (match_operand:SI 1 "register_operand" "0") 5214 (match_operand:SI 2 "general_operand" "dINO")))] 5215 "!TARGET_COLDFIRE" 5216{ 5217 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) == 16) 5218 return "swap %0"; 5219 else if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 16) 5220 { 5221 operands[2] = GEN_INT (32 - INTVAL (operands[2])); 5222 return "ror%.l %2,%0"; 5223 } 5224 else 5225 return "rol%.l %2,%0"; 5226}) 5227 5228(define_insn "rotlhi3" 5229 [(set (match_operand:HI 0 "register_operand" "=d") 5230 (rotate:HI (match_operand:HI 1 "register_operand" "0") 5231 (match_operand:HI 2 "general_operand" "dIP")))] 5232 "!TARGET_COLDFIRE" 5233{ 5234 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) 5235 { 5236 operands[2] = GEN_INT (16 - INTVAL (operands[2])); 5237 return "ror%.w %2,%0"; 5238 } 5239 else 5240 return "rol%.w %2,%0"; 5241}) 5242 5243(define_insn "" 5244 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 5245 (rotate:HI (match_dup 0) 5246 (match_operand:HI 1 "general_operand" "dIP")))] 5247 "!TARGET_COLDFIRE" 5248{ 5249 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 8) 5250 { 5251 operands[2] = GEN_INT (16 - INTVAL (operands[2])); 5252 return "ror%.w %2,%0"; 5253 } 5254 else 5255 return "rol%.w %2,%0"; 5256}) 5257 5258(define_insn "rotlqi3" 5259 [(set (match_operand:QI 0 "register_operand" "=d") 5260 (rotate:QI (match_operand:QI 1 "register_operand" "0") 5261 (match_operand:QI 2 "general_operand" "dI")))] 5262 "!TARGET_COLDFIRE" 5263{ 5264 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) 5265 { 5266 operands[2] = GEN_INT (8 - INTVAL (operands[2])); 5267 return "ror%.b %2,%0"; 5268 } 5269 else 5270 return "rol%.b %2,%0"; 5271}) 5272 5273(define_insn "" 5274 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 5275 (rotate:QI (match_dup 0) 5276 (match_operand:QI 1 "general_operand" "dI")))] 5277 "!TARGET_COLDFIRE" 5278{ 5279 if (GET_CODE (operands[2]) == CONST_INT && INTVAL (operands[2]) >= 4) 5280 { 5281 operands[2] = GEN_INT (8 - INTVAL (operands[2])); 5282 return "ror%.b %2,%0"; 5283 } 5284 else 5285 return "rol%.b %2,%0"; 5286}) 5287 5288(define_insn "rotrsi3" 5289 [(set (match_operand:SI 0 "register_operand" "=d") 5290 (rotatert:SI (match_operand:SI 1 "register_operand" "0") 5291 (match_operand:SI 2 "general_operand" "dI")))] 5292 "!TARGET_COLDFIRE" 5293 "ror%.l %2,%0") 5294 5295(define_insn "rotrhi3" 5296 [(set (match_operand:HI 0 "register_operand" "=d") 5297 (rotatert:HI (match_operand:HI 1 "register_operand" "0") 5298 (match_operand:HI 2 "general_operand" "dI")))] 5299 "!TARGET_COLDFIRE" 5300 "ror%.w %2,%0") 5301 5302(define_insn "rotrhi_lowpart" 5303 [(set (strict_low_part (match_operand:HI 0 "register_operand" "+d")) 5304 (rotatert:HI (match_dup 0) 5305 (match_operand:HI 1 "general_operand" "dI")))] 5306 "!TARGET_COLDFIRE" 5307 "ror%.w %1,%0") 5308 5309(define_insn "rotrqi3" 5310 [(set (match_operand:QI 0 "register_operand" "=d") 5311 (rotatert:QI (match_operand:QI 1 "register_operand" "0") 5312 (match_operand:QI 2 "general_operand" "dI")))] 5313 "!TARGET_COLDFIRE" 5314 "ror%.b %2,%0") 5315 5316(define_insn "" 5317 [(set (strict_low_part (match_operand:QI 0 "register_operand" "+d")) 5318 (rotatert:QI (match_dup 0) 5319 (match_operand:QI 1 "general_operand" "dI")))] 5320 "!TARGET_COLDFIRE" 5321 "ror%.b %1,%0") 5322 5323(define_expand "bswapsi2" 5324 [(set (match_operand:SI 0 "register_operand") 5325 (bswap:SI (match_operand:SI 1 "register_operand")))] 5326 "!TARGET_COLDFIRE" 5327{ 5328 rtx x = operands[0]; 5329 emit_move_insn (x, operands[1]); 5330 emit_insn (gen_rotrhi_lowpart (gen_lowpart (HImode, x), GEN_INT (8))); 5331 emit_insn (gen_rotlsi3 (x, x, GEN_INT (16))); 5332 emit_insn (gen_rotrhi_lowpart (gen_lowpart (HImode, x), GEN_INT (8))); 5333 DONE; 5334}) 5335 5336 5337;; Bit set/clear in memory byte. 5338 5339;; set bit, bit number is int 5340(define_insn "bsetmemqi" 5341 [(set (match_operand:QI 0 "memory_operand" "+m") 5342 (ior:QI (subreg:QI (ashift:SI (const_int 1) 5343 (match_operand:SI 1 "general_operand" "d")) 3) 5344 (match_dup 0)))] 5345 "" 5346{ 5347 CC_STATUS_INIT; 5348 return "bset %1,%0"; 5349} 5350 [(set_attr "type" "bitrw")]) 5351 5352;; set bit, bit number is (sign/zero)_extended from HImode/QImode 5353(define_insn "*bsetmemqi_ext" 5354 [(set (match_operand:QI 0 "memory_operand" "+m") 5355 (ior:QI (subreg:QI (ashift:SI (const_int 1) 5356 (match_operator:SI 2 "extend_operator" 5357 [(match_operand 1 "general_operand" "d")])) 3) 5358 (match_dup 0)))] 5359 "" 5360{ 5361 CC_STATUS_INIT; 5362 return "bset %1,%0"; 5363} 5364 [(set_attr "type" "bitrw")]) 5365 5366;; clear bit, bit number is int 5367(define_insn "bclrmemqi" 5368 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m") 5369 (const_int 1) 5370 (minus:SI (const_int 7) 5371 (match_operand:SI 1 "general_operand" "d"))) 5372 (const_int 0))] 5373 "" 5374{ 5375 CC_STATUS_INIT; 5376 return "bclr %1,%0"; 5377} 5378 [(set_attr "type" "bitrw")]) 5379 5380;; clear bit, bit number is (sign/zero)_extended from HImode/QImode 5381(define_insn "*bclrmemqi_ext" 5382 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+m") 5383 (const_int 1) 5384 (minus:SI (const_int 7) 5385 (match_operator:SI 2 "extend_operator" 5386 [(match_operand 1 "general_operand" "d")]))) 5387 (const_int 0))] 5388 "" 5389{ 5390 CC_STATUS_INIT; 5391 return "bclr %1,%0"; 5392} 5393 [(set_attr "type" "bitrw")]) 5394 5395;; Special cases of bit-field insns which we should 5396;; recognize in preference to the general case. 5397;; These handle aligned 8-bit and 16-bit fields, 5398;; which can usually be done with move instructions. 5399 5400; 5401; Special case for 32-bit field in memory. This only occurs when 32-bit 5402; alignment of structure members is specified. 5403; 5404; The move is allowed to be odd byte aligned, because that's still faster 5405; than an odd byte aligned bit-field instruction. 5406; 5407(define_insn "*insv_32_mem" 5408 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5409 (const_int 32) 5410 (match_operand:SI 1 "const_int_operand" "n")) 5411 (match_operand:SI 2 "general_src_operand" "rmSi"))] 5412 "TARGET_68020 && TARGET_BITFIELD 5413 && (INTVAL (operands[1]) % 8) == 0 5414 && ! mode_dependent_address_p (XEXP (operands[0], 0), 5415 MEM_ADDR_SPACE (operands[0]))" 5416{ 5417 operands[0] 5418 = adjust_address (operands[0], SImode, INTVAL (operands[1]) / 8); 5419 5420 return "move%.l %2,%0"; 5421}) 5422 5423(define_insn "*insv_8_16_reg" 5424 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") 5425 (match_operand:SI 1 "const_int_operand" "n") 5426 (match_operand:SI 2 "const_int_operand" "n")) 5427 (match_operand:SI 3 "register_operand" "d"))] 5428 "TARGET_68020 && TARGET_BITFIELD 5429 && (INTVAL (operands[1]) == 8 || INTVAL (operands[1]) == 16) 5430 && INTVAL (operands[2]) % INTVAL (operands[1]) == 0" 5431{ 5432 if (INTVAL (operands[1]) + INTVAL (operands[2]) != 32) 5433 return "bfins %3,%0{%b2:%b1}"; 5434 5435 if (INTVAL (operands[1]) == 8) 5436 return "move%.b %3,%0"; 5437 return "move%.w %3,%0"; 5438}) 5439 5440 5441; 5442; Special case for 32-bit field in memory. This only occurs when 32-bit 5443; alignment of structure members is specified. 5444; 5445; The move is allowed to be odd byte aligned, because that's still faster 5446; than an odd byte aligned bit-field instruction. 5447; 5448(define_insn "*extzv_32_mem" 5449 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 5450 (zero_extract:SI (match_operand:QI 1 "memory_src_operand" "oS") 5451 (const_int 32) 5452 (match_operand:SI 2 "const_int_operand" "n")))] 5453 "TARGET_68020 && TARGET_BITFIELD 5454 && (INTVAL (operands[2]) % 8) == 0 5455 && ! mode_dependent_address_p (XEXP (operands[1], 0), 5456 MEM_ADDR_SPACE (operands[1]))" 5457{ 5458 operands[1] 5459 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8); 5460 5461 return "move%.l %1,%0"; 5462}) 5463 5464(define_insn "*extzv_8_16_reg" 5465 [(set (match_operand:SI 0 "nonimmediate_operand" "=&d") 5466 (zero_extract:SI (match_operand:SI 1 "register_operand" "d") 5467 (match_operand:SI 2 "const_int_operand" "n") 5468 (match_operand:SI 3 "const_int_operand" "n")))] 5469 "TARGET_68020 && TARGET_BITFIELD 5470 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 5471 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0" 5472{ 5473 cc_status.flags |= CC_NOT_NEGATIVE; 5474 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) 5475 return "bfextu %1{%b3:%b2},%0"; 5476 5477 output_asm_insn ("clr%.l %0", operands); 5478 if (INTVAL (operands[2]) == 8) 5479 return "move%.b %1,%0"; 5480 return "move%.w %1,%0"; 5481}) 5482 5483; 5484; Special case for 32-bit field in memory. This only occurs when 32-bit 5485; alignment of structure members is specified. 5486; 5487; The move is allowed to be odd byte aligned, because that's still faster 5488; than an odd byte aligned bit-field instruction. 5489; 5490(define_insn "*extv_32_mem" 5491 [(set (match_operand:SI 0 "nonimmediate_operand" "=rm") 5492 (sign_extract:SI (match_operand:QI 1 "memory_src_operand" "oS") 5493 (const_int 32) 5494 (match_operand:SI 2 "const_int_operand" "n")))] 5495 "TARGET_68020 && TARGET_BITFIELD 5496 && (INTVAL (operands[2]) % 8) == 0 5497 && ! mode_dependent_address_p (XEXP (operands[1], 0), 5498 MEM_ADDR_SPACE (operands[1]))" 5499{ 5500 operands[1] 5501 = adjust_address (operands[1], SImode, INTVAL (operands[2]) / 8); 5502 5503 return "move%.l %1,%0"; 5504}) 5505 5506(define_insn "*extv_8_16_reg" 5507 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 5508 (sign_extract:SI (match_operand:SI 1 "register_operand" "d") 5509 (match_operand:SI 2 "const_int_operand" "n") 5510 (match_operand:SI 3 "const_int_operand" "n")))] 5511 "TARGET_68020 && TARGET_BITFIELD 5512 && (INTVAL (operands[2]) == 8 || INTVAL (operands[2]) == 16) 5513 && INTVAL (operands[3]) % INTVAL (operands[2]) == 0" 5514{ 5515 if (INTVAL (operands[2]) + INTVAL (operands[3]) != 32) 5516 return "bfexts %1{%b3:%b2},%0"; 5517 5518 if (INTVAL (operands[2]) == 8) 5519 return "move%.b %1,%0\;extb%.l %0"; 5520 return "move%.w %1,%0\;ext%.l %0"; 5521}) 5522 5523;; Bit-field instructions, general cases. 5524;; "o,d" constraint causes a nonoffsettable memref to match the "o" 5525;; so that its address is reloaded. 5526 5527(define_expand "extv" 5528 [(set (match_operand:SI 0 "register_operand" "") 5529 (sign_extract:SI (match_operand:SI 1 "general_operand" "") 5530 (match_operand:SI 2 "const_int_operand" "") 5531 (match_operand:SI 3 "const_int_operand" "")))] 5532 "TARGET_68020 && TARGET_BITFIELD" 5533 "") 5534 5535(define_insn "*extv_bfexts_mem" 5536 [(set (match_operand:SI 0 "register_operand" "=d") 5537 (sign_extract:SI (match_operand:QI 1 "memory_operand" "o") 5538 (match_operand:SI 2 "nonmemory_operand" "dn") 5539 (match_operand:SI 3 "nonmemory_operand" "dn")))] 5540 "TARGET_68020 && TARGET_BITFIELD" 5541 "bfexts %1{%b3:%b2},%0") 5542 5543(define_expand "extzv" 5544 [(set (match_operand:SI 0 "register_operand" "") 5545 (zero_extract:SI (match_operand:SI 1 "general_operand" "") 5546 (match_operand:SI 2 "const_int_operand" "") 5547 (match_operand:SI 3 "const_int_operand" "")))] 5548 "TARGET_68020 && TARGET_BITFIELD" 5549 "") 5550 5551(define_insn "*extzv_bfextu_mem" 5552 [(set (match_operand:SI 0 "register_operand" "=d") 5553 (zero_extract:SI (match_operand:QI 1 "memory_operand" "o") 5554 (match_operand:SI 2 "nonmemory_operand" "dn") 5555 (match_operand:SI 3 "nonmemory_operand" "dn")))] 5556 "TARGET_68020 && TARGET_BITFIELD" 5557{ 5558 if (GET_CODE (operands[2]) == CONST_INT) 5559 { 5560 if (INTVAL (operands[2]) != 32) 5561 cc_status.flags |= CC_NOT_NEGATIVE; 5562 } 5563 else 5564 { 5565 CC_STATUS_INIT; 5566 } 5567 return "bfextu %1{%b3:%b2},%0"; 5568}) 5569 5570(define_insn "*insv_bfchg_mem" 5571 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5572 (match_operand:SI 1 "nonmemory_operand" "dn") 5573 (match_operand:SI 2 "nonmemory_operand" "dn")) 5574 (xor:SI (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)) 5575 (match_operand 3 "const_int_operand" "n")))] 5576 "TARGET_68020 && TARGET_BITFIELD 5577 && (INTVAL (operands[3]) == -1 5578 || (GET_CODE (operands[1]) == CONST_INT 5579 && (~ INTVAL (operands[3]) & ((1 << INTVAL (operands[1]))- 1)) == 0))" 5580{ 5581 CC_STATUS_INIT; 5582 return "bfchg %0{%b2:%b1}"; 5583}) 5584 5585(define_insn "*insv_bfclr_mem" 5586 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5587 (match_operand:SI 1 "nonmemory_operand" "dn") 5588 (match_operand:SI 2 "nonmemory_operand" "dn")) 5589 (const_int 0))] 5590 "TARGET_68020 && TARGET_BITFIELD" 5591{ 5592 CC_STATUS_INIT; 5593 return "bfclr %0{%b2:%b1}"; 5594}) 5595 5596(define_insn "*insv_bfset_mem" 5597 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5598 (match_operand:SI 1 "general_operand" "dn") 5599 (match_operand:SI 2 "general_operand" "dn")) 5600 (const_int -1))] 5601 "TARGET_68020 && TARGET_BITFIELD" 5602{ 5603 CC_STATUS_INIT; 5604 return "bfset %0{%b2:%b1}"; 5605}) 5606 5607(define_expand "insv" 5608 [(set (zero_extract:SI (match_operand:SI 0 "nonimmediate_operand" "") 5609 (match_operand:SI 1 "const_int_operand" "") 5610 (match_operand:SI 2 "const_int_operand" "")) 5611 (match_operand:SI 3 "register_operand" ""))] 5612 "TARGET_68020 && TARGET_BITFIELD" 5613 "") 5614 5615(define_insn "*insv_bfins_mem" 5616 [(set (zero_extract:SI (match_operand:QI 0 "memory_operand" "+o") 5617 (match_operand:SI 1 "nonmemory_operand" "dn") 5618 (match_operand:SI 2 "nonmemory_operand" "dn")) 5619 (match_operand:SI 3 "register_operand" "d"))] 5620 "TARGET_68020 && TARGET_BITFIELD" 5621 "bfins %3,%0{%b2:%b1}") 5622 5623;; Now recognize bit-field insns that operate on registers 5624;; (or at least were intended to do so). 5625 5626(define_insn "*extv_bfexts_reg" 5627 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 5628 (sign_extract:SI (match_operand:SI 1 "register_operand" "d") 5629 (match_operand:SI 2 "const_int_operand" "n") 5630 (match_operand:SI 3 "const_int_operand" "n")))] 5631 "TARGET_68020 && TARGET_BITFIELD" 5632 "bfexts %1{%b3:%b2},%0") 5633 5634(define_insn "*extv_bfextu_reg" 5635 [(set (match_operand:SI 0 "nonimmediate_operand" "=d") 5636 (zero_extract:SI (match_operand:SI 1 "register_operand" "d") 5637 (match_operand:SI 2 "const_int_operand" "n") 5638 (match_operand:SI 3 "const_int_operand" "n")))] 5639 "TARGET_68020 && TARGET_BITFIELD" 5640{ 5641 if (GET_CODE (operands[2]) == CONST_INT) 5642 { 5643 if (INTVAL (operands[2]) != 32) 5644 cc_status.flags |= CC_NOT_NEGATIVE; 5645 } 5646 else 5647 { 5648 CC_STATUS_INIT; 5649 } 5650 return "bfextu %1{%b3:%b2},%0"; 5651}) 5652 5653(define_insn "*insv_bfclr_reg" 5654 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") 5655 (match_operand:SI 1 "const_int_operand" "n") 5656 (match_operand:SI 2 "const_int_operand" "n")) 5657 (const_int 0))] 5658 "TARGET_68020 && TARGET_BITFIELD" 5659{ 5660 CC_STATUS_INIT; 5661 return "bfclr %0{%b2:%b1}"; 5662}) 5663 5664(define_insn "*insv_bfset_reg" 5665 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") 5666 (match_operand:SI 1 "const_int_operand" "n") 5667 (match_operand:SI 2 "const_int_operand" "n")) 5668 (const_int -1))] 5669 "TARGET_68020 && TARGET_BITFIELD" 5670{ 5671 CC_STATUS_INIT; 5672 return "bfset %0{%b2:%b1}"; 5673}) 5674 5675(define_insn "*insv_bfins_reg" 5676 [(set (zero_extract:SI (match_operand:SI 0 "register_operand" "+d") 5677 (match_operand:SI 1 "const_int_operand" "n") 5678 (match_operand:SI 2 "const_int_operand" "n")) 5679 (match_operand:SI 3 "register_operand" "d"))] 5680 "TARGET_68020 && TARGET_BITFIELD" 5681{ 5682#if 0 5683 /* These special cases are now recognized by a specific pattern. */ 5684 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT 5685 && INTVAL (operands[1]) == 16 && INTVAL (operands[2]) == 16) 5686 return "move%.w %3,%0"; 5687 if (GET_CODE (operands[1]) == CONST_INT && GET_CODE (operands[2]) == CONST_INT 5688 && INTVAL (operands[1]) == 24 && INTVAL (operands[2]) == 8) 5689 return "move%.b %3,%0"; 5690#endif 5691 return "bfins %3,%0{%b2:%b1}"; 5692}) 5693 5694;; Special patterns for optimizing bit-field instructions. 5695 5696(define_insn "*tst_bftst_mem" 5697 [(set (cc0) 5698 (compare (zero_extract:SI (match_operand:QI 0 "memory_operand" "o") 5699 (match_operand:SI 1 "const_int_operand" "n") 5700 (match_operand:SI 2 "general_operand" "dn")) 5701 (const_int 0)))] 5702 "TARGET_68020 && TARGET_BITFIELD" 5703{ 5704 if (operands[1] == const1_rtx 5705 && GET_CODE (operands[2]) == CONST_INT) 5706 { 5707 int width = GET_CODE (operands[0]) == REG ? 31 : 7; 5708 return output_btst (operands, 5709 GEN_INT (width - INTVAL (operands[2])), 5710 operands[0], insn, 1000); 5711 /* Pass 1000 as SIGNPOS argument so that btst will 5712 not think we are testing the sign bit for an `and' 5713 and assume that nonzero implies a negative result. */ 5714 } 5715 if (INTVAL (operands[1]) != 32) 5716 cc_status.flags = CC_NOT_NEGATIVE; 5717 return "bftst %0{%b2:%b1}"; 5718}) 5719 5720 5721;;; now handle the register cases 5722(define_insn "*tst_bftst_reg" 5723 [(set (cc0) 5724 (compare (zero_extract:SI (match_operand:SI 0 "register_operand" "d") 5725 (match_operand:SI 1 "const_int_operand" "n") 5726 (match_operand:SI 2 "general_operand" "dn")) 5727 (const_int 0)))] 5728 "TARGET_68020 && TARGET_BITFIELD" 5729{ 5730 if (operands[1] == const1_rtx 5731 && GET_CODE (operands[2]) == CONST_INT) 5732 { 5733 int width = GET_CODE (operands[0]) == REG ? 31 : 7; 5734 return output_btst (operands, GEN_INT (width - INTVAL (operands[2])), 5735 operands[0], insn, 1000); 5736 /* Pass 1000 as SIGNPOS argument so that btst will 5737 not think we are testing the sign bit for an `and' 5738 and assume that nonzero implies a negative result. */ 5739 } 5740 if (INTVAL (operands[1]) != 32) 5741 cc_status.flags = CC_NOT_NEGATIVE; 5742 return "bftst %0{%b2:%b1}"; 5743}) 5744 5745(define_insn "scc0_di" 5746 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm") 5747 (match_operator 1 "ordered_comparison_operator" 5748 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] 5749 "! TARGET_COLDFIRE" 5750{ 5751 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); 5752}) 5753 5754(define_insn "scc0_di_5200" 5755 [(set (match_operand:QI 0 "nonimmediate_operand" "=d") 5756 (match_operator 1 "ordered_comparison_operator" 5757 [(match_operand:DI 2 "general_operand" "ro") (const_int 0)]))] 5758 "TARGET_COLDFIRE" 5759{ 5760 return output_scc_di (operands[1], operands[2], const0_rtx, operands[0]); 5761}) 5762 5763(define_insn "scc_di" 5764 [(set (match_operand:QI 0 "nonimmediate_operand" "=dm,dm") 5765 (match_operator 1 "ordered_comparison_operator" 5766 [(match_operand:DI 2 "general_operand" "ro,r") 5767 (match_operand:DI 3 "general_operand" "r,ro")]))] 5768 "! TARGET_COLDFIRE" 5769{ 5770 return output_scc_di (operands[1], operands[2], operands[3], operands[0]); 5771}) 5772 5773(define_insn "scc_di_5200" 5774 [(set (match_operand:QI 0 "nonimmediate_operand" "=d,d") 5775 (match_operator 1 "ordered_comparison_operator" 5776 [(match_operand:DI 2 "general_operand" "ro,r") 5777 (match_operand:DI 3 "general_operand" "r,ro")]))] 5778 "TARGET_COLDFIRE" 5779{ 5780 return output_scc_di (operands[1], operands[2], operands[3], operands[0]); 5781}) 5782 5783;; Note that operand 0 of an SCC insn is supported in the hardware as 5784;; memory, but we cannot allow it to be in memory in case the address 5785;; needs to be reloaded. 5786 5787(define_insn "" 5788 [(set (match_operand:QI 0 "register_operand" "=d") 5789 (eq:QI (cc0) (const_int 0)))] 5790 "" 5791{ 5792 cc_status = cc_prev_status; 5793 OUTPUT_JUMP ("seq %0", "fseq %0", "seq %0"); 5794}) 5795 5796(define_insn "" 5797 [(set (match_operand:QI 0 "register_operand" "=d") 5798 (ne:QI (cc0) (const_int 0)))] 5799 "" 5800{ 5801 cc_status = cc_prev_status; 5802 OUTPUT_JUMP ("sne %0", "fsne %0", "sne %0"); 5803}) 5804 5805(define_insn "" 5806 [(set (match_operand:QI 0 "register_operand" "=d") 5807 (gt:QI (cc0) (const_int 0)))] 5808 "" 5809{ 5810 cc_status = cc_prev_status; 5811 OUTPUT_JUMP ("sgt %0", "fsgt %0", 0); 5812}) 5813 5814(define_insn "" 5815 [(set (match_operand:QI 0 "register_operand" "=d") 5816 (gtu:QI (cc0) (const_int 0)))] 5817 "" 5818{ 5819 cc_status = cc_prev_status; 5820 return "shi %0"; 5821}) 5822 5823(define_insn "" 5824 [(set (match_operand:QI 0 "register_operand" "=d") 5825 (lt:QI (cc0) (const_int 0)))] 5826 "" 5827{ 5828 cc_status = cc_prev_status; 5829 OUTPUT_JUMP ("slt %0", "fslt %0", "smi %0"); 5830}) 5831 5832(define_insn "" 5833 [(set (match_operand:QI 0 "register_operand" "=d") 5834 (ltu:QI (cc0) (const_int 0)))] 5835 "" 5836{ 5837 cc_status = cc_prev_status; 5838 return "scs %0"; 5839}) 5840 5841(define_insn "" 5842 [(set (match_operand:QI 0 "register_operand" "=d") 5843 (ge:QI (cc0) (const_int 0)))] 5844 "" 5845{ 5846 cc_status = cc_prev_status; 5847 OUTPUT_JUMP ("sge %0", "fsge %0", "spl %0"); 5848}) 5849 5850(define_insn "*scc" 5851 [(set (match_operand:QI 0 "register_operand" "=d") 5852 (geu:QI (cc0) (const_int 0)))] 5853 "" 5854{ 5855 cc_status = cc_prev_status; 5856 return "scc %0"; 5857} 5858 [(set_attr "type" "scc")]) 5859 5860(define_insn "" 5861 [(set (match_operand:QI 0 "register_operand" "=d") 5862 (le:QI (cc0) (const_int 0)))] 5863 "" 5864{ 5865 cc_status = cc_prev_status; 5866 OUTPUT_JUMP ("sle %0", "fsle %0", 0); 5867}) 5868 5869(define_insn "*sls" 5870 [(set (match_operand:QI 0 "register_operand" "=d") 5871 (leu:QI (cc0) (const_int 0)))] 5872 "" 5873{ 5874 cc_status = cc_prev_status; 5875 return "sls %0"; 5876} 5877 [(set_attr "type" "scc")]) 5878 5879(define_insn "*sordered_1" 5880 [(set (match_operand:QI 0 "register_operand" "=d") 5881 (ordered:QI (cc0) (const_int 0)))] 5882 "TARGET_68881 && !TUNE_68060" 5883{ 5884 cc_status = cc_prev_status; 5885 return "fsor %0"; 5886}) 5887 5888(define_insn "*sunordered_1" 5889 [(set (match_operand:QI 0 "register_operand" "=d") 5890 (unordered:QI (cc0) (const_int 0)))] 5891 "TARGET_68881 && !TUNE_68060" 5892{ 5893 cc_status = cc_prev_status; 5894 return "fsun %0"; 5895}) 5896 5897(define_insn "*suneq_1" 5898 [(set (match_operand:QI 0 "register_operand" "=d") 5899 (uneq:QI (cc0) (const_int 0)))] 5900 "TARGET_68881 && !TUNE_68060" 5901{ 5902 cc_status = cc_prev_status; 5903 return "fsueq %0"; 5904}) 5905 5906(define_insn "*sunge_1" 5907 [(set (match_operand:QI 0 "register_operand" "=d") 5908 (unge:QI (cc0) (const_int 0)))] 5909 "TARGET_68881 && !TUNE_68060" 5910{ 5911 cc_status = cc_prev_status; 5912 return "fsuge %0"; 5913}) 5914 5915(define_insn "*sungt_1" 5916 [(set (match_operand:QI 0 "register_operand" "=d") 5917 (ungt:QI (cc0) (const_int 0)))] 5918 "TARGET_68881 && !TUNE_68060" 5919{ 5920 cc_status = cc_prev_status; 5921 return "fsugt %0"; 5922}) 5923 5924(define_insn "*sunle_1" 5925 [(set (match_operand:QI 0 "register_operand" "=d") 5926 (unle:QI (cc0) (const_int 0)))] 5927 "TARGET_68881 && !TUNE_68060" 5928{ 5929 cc_status = cc_prev_status; 5930 return "fsule %0"; 5931}) 5932 5933(define_insn "*sunlt_1" 5934 [(set (match_operand:QI 0 "register_operand" "=d") 5935 (unlt:QI (cc0) (const_int 0)))] 5936 "TARGET_68881 && !TUNE_68060" 5937{ 5938 cc_status = cc_prev_status; 5939 return "fsult %0"; 5940}) 5941 5942(define_insn "*sltgt_1" 5943 [(set (match_operand:QI 0 "register_operand" "=d") 5944 (ltgt:QI (cc0) (const_int 0)))] 5945 "TARGET_68881 && !TUNE_68060" 5946{ 5947 cc_status = cc_prev_status; 5948 return "fsogl %0"; 5949}) 5950 5951(define_insn "*fsogt_1" 5952 [(set (match_operand:QI 0 "register_operand" "=d") 5953 (not:QI (unle:QI (cc0) (const_int 0))))] 5954 "TARGET_68881 && !TUNE_68060" 5955{ 5956 cc_status = cc_prev_status; 5957 return "fsogt %0"; 5958}) 5959 5960(define_insn "*fsoge_1" 5961 [(set (match_operand:QI 0 "register_operand" "=d") 5962 (not:QI (unlt:QI (cc0) (const_int 0))))] 5963 "TARGET_68881 && !TUNE_68060" 5964{ 5965 cc_status = cc_prev_status; 5966 return "fsoge %0"; 5967}) 5968 5969(define_insn "*fsolt_1" 5970 [(set (match_operand:QI 0 "register_operand" "=d") 5971 (not:QI (unge:QI (cc0) (const_int 0))))] 5972 "TARGET_68881 && !TUNE_68060" 5973{ 5974 cc_status = cc_prev_status; 5975 return "fsolt %0"; 5976}) 5977 5978(define_insn "*fsole_1" 5979 [(set (match_operand:QI 0 "register_operand" "=d") 5980 (not:QI (ungt:QI (cc0) (const_int 0))))] 5981 "TARGET_68881 && !TUNE_68060" 5982{ 5983 cc_status = cc_prev_status; 5984 return "fsole %0"; 5985}) 5986 5987;; Basic conditional jump instructions. 5988 5989(define_insn "beq0_di" 5990 [(set (pc) 5991 (if_then_else (eq (match_operand:DI 0 "general_operand" "d*ao,<>") 5992 (const_int 0)) 5993 (label_ref (match_operand 1 "" ",")) 5994 (pc))) 5995 (clobber (match_scratch:SI 2 "=d,d"))] 5996 "" 5997{ 5998 CC_STATUS_INIT; 5999 if (which_alternative == 1) 6000 return "move%.l %0,%2\;or%.l %0,%2\;jeq %l1"; 6001 if ((cc_prev_status.value1 6002 && rtx_equal_p (cc_prev_status.value1, operands[0])) 6003 || (cc_prev_status.value2 6004 && rtx_equal_p (cc_prev_status.value2, operands[0]))) 6005 { 6006 cc_status = cc_prev_status; 6007 return "jeq %l1"; 6008 } 6009 if (GET_CODE (operands[0]) == REG) 6010 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 6011 else 6012 operands[3] = adjust_address (operands[0], SImode, 4); 6013 if (! ADDRESS_REG_P (operands[0])) 6014 { 6015 if (reg_overlap_mentioned_p (operands[2], operands[0])) 6016 { 6017 if (reg_overlap_mentioned_p (operands[2], operands[3])) 6018 return "or%.l %0,%2\;jeq %l1"; 6019 else 6020 return "or%.l %3,%2\;jeq %l1"; 6021 } 6022 return "move%.l %0,%2\;or%.l %3,%2\;jeq %l1"; 6023 } 6024 operands[4] = gen_label_rtx(); 6025 if (TARGET_68020 || TARGET_COLDFIRE) 6026 output_asm_insn ("tst%.l %0\;jne %l4\;tst%.l %3\;jeq %l1", operands); 6027 else 6028 output_asm_insn ("cmp%.w #0,%0\;jne %l4\;cmp%.w #0,%3\;jeq %l1", operands); 6029 (*targetm.asm_out.internal_label) (asm_out_file, "L", 6030 CODE_LABEL_NUMBER (operands[4])); 6031 return ""; 6032}) 6033 6034(define_insn "bne0_di" 6035 [(set (pc) 6036 (if_then_else (ne (match_operand:DI 0 "general_operand" "do,*a") 6037 (const_int 0)) 6038 (label_ref (match_operand 1 "" ",")) 6039 (pc))) 6040 (clobber (match_scratch:SI 2 "=d,X"))] 6041 "" 6042{ 6043 if ((cc_prev_status.value1 6044 && rtx_equal_p (cc_prev_status.value1, operands[0])) 6045 || (cc_prev_status.value2 6046 && rtx_equal_p (cc_prev_status.value2, operands[0]))) 6047 { 6048 cc_status = cc_prev_status; 6049 return "jne %l1"; 6050 } 6051 CC_STATUS_INIT; 6052 if (GET_CODE (operands[0]) == REG) 6053 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 6054 else 6055 operands[3] = adjust_address (operands[0], SImode, 4); 6056 if (!ADDRESS_REG_P (operands[0])) 6057 { 6058 if (reg_overlap_mentioned_p (operands[2], operands[0])) 6059 { 6060 if (reg_overlap_mentioned_p (operands[2], operands[3])) 6061 return "or%.l %0,%2\;jne %l1"; 6062 else 6063 return "or%.l %3,%2\;jne %l1"; 6064 } 6065 return "move%.l %0,%2\;or%.l %3,%2\;jne %l1"; 6066 } 6067 if (TARGET_68020 || TARGET_COLDFIRE) 6068 return "tst%.l %0\;jne %l1\;tst%.l %3\;jne %l1"; 6069 else 6070 return "cmp%.w #0,%0\;jne %l1\;cmp%.w #0,%3\;jne %l1"; 6071}) 6072 6073(define_insn "bge0_di" 6074 [(set (pc) 6075 (if_then_else (ge (match_operand:DI 0 "general_operand" "ro") 6076 (const_int 0)) 6077 (label_ref (match_operand 1 "" "")) 6078 (pc)))] 6079 "" 6080{ 6081 if ((cc_prev_status.value1 6082 && rtx_equal_p (cc_prev_status.value1, operands[0])) 6083 || (cc_prev_status.value2 6084 && rtx_equal_p (cc_prev_status.value2, operands[0]))) 6085 { 6086 cc_status = cc_prev_status; 6087 return cc_status.flags & CC_REVERSED ? "jle %l1" : "jpl %l1"; 6088 } 6089 CC_STATUS_INIT; 6090 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) 6091 output_asm_insn("tst%.l %0", operands); 6092 else 6093 { 6094 /* On an address reg, cmpw may replace cmpl. */ 6095 output_asm_insn("cmp%.w #0,%0", operands); 6096 } 6097 return "jpl %l1"; 6098}) 6099 6100(define_insn "blt0_di" 6101 [(set (pc) 6102 (if_then_else (lt (match_operand:DI 0 "general_operand" "ro") 6103 (const_int 0)) 6104 (label_ref (match_operand 1 "" "")) 6105 (pc)))] 6106 "" 6107{ 6108 if ((cc_prev_status.value1 6109 && rtx_equal_p (cc_prev_status.value1, operands[0])) 6110 || (cc_prev_status.value2 6111 && rtx_equal_p (cc_prev_status.value2, operands[0]))) 6112 { 6113 cc_status = cc_prev_status; 6114 return cc_status.flags & CC_REVERSED ? "jgt %l1" : "jmi %l1"; 6115 } 6116 CC_STATUS_INIT; 6117 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (operands[0])) 6118 output_asm_insn("tst%.l %0", operands); 6119 else 6120 { 6121 /* On an address reg, cmpw may replace cmpl. */ 6122 output_asm_insn("cmp%.w #0,%0", operands); 6123 } 6124 return "jmi %l1"; 6125}) 6126 6127(define_insn "beq" 6128 [(set (pc) 6129 (if_then_else (eq (cc0) 6130 (const_int 0)) 6131 (label_ref (match_operand 0 "" "")) 6132 (pc)))] 6133 "" 6134{ 6135 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0"); 6136} 6137 [(set_attr "type" "bcc")]) 6138 6139(define_insn "bne" 6140 [(set (pc) 6141 (if_then_else (ne (cc0) 6142 (const_int 0)) 6143 (label_ref (match_operand 0 "" "")) 6144 (pc)))] 6145 "" 6146{ 6147 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0"); 6148} 6149 [(set_attr "type" "bcc")]) 6150 6151(define_insn "bgt" 6152 [(set (pc) 6153 (if_then_else (gt (cc0) 6154 (const_int 0)) 6155 (label_ref (match_operand 0 "" "")) 6156 (pc)))] 6157 "" 6158{ 6159 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6160 { 6161 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6162 return 0; 6163 } 6164 6165 OUTPUT_JUMP ("jgt %l0", "fjgt %l0", 0); 6166} 6167 [(set_attr "type" "bcc")]) 6168 6169(define_insn "bgtu" 6170 [(set (pc) 6171 (if_then_else (gtu (cc0) 6172 (const_int 0)) 6173 (label_ref (match_operand 0 "" "")) 6174 (pc)))] 6175 "" 6176{ 6177 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6178 { 6179 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6180 return 0; 6181 } 6182 6183 return "jhi %l0"; 6184} 6185 [(set_attr "type" "bcc")]) 6186 6187(define_insn "blt" 6188 [(set (pc) 6189 (if_then_else (lt (cc0) 6190 (const_int 0)) 6191 (label_ref (match_operand 0 "" "")) 6192 (pc)))] 6193 "" 6194{ 6195 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6196 { 6197 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6198 return 0; 6199 } 6200 6201 OUTPUT_JUMP ("jlt %l0", "fjlt %l0", "jmi %l0"); 6202} 6203 [(set_attr "type" "bcc")]) 6204 6205(define_insn "bltu" 6206 [(set (pc) 6207 (if_then_else (ltu (cc0) 6208 (const_int 0)) 6209 (label_ref (match_operand 0 "" "")) 6210 (pc)))] 6211 "" 6212{ 6213 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6214 { 6215 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6216 return 0; 6217 } 6218 6219 return "jcs %l0"; 6220} 6221 [(set_attr "type" "bcc")]) 6222 6223(define_insn "bge" 6224 [(set (pc) 6225 (if_then_else (ge (cc0) 6226 (const_int 0)) 6227 (label_ref (match_operand 0 "" "")) 6228 (pc)))] 6229 "" 6230{ 6231 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6232 { 6233 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6234 return 0; 6235 } 6236 6237 OUTPUT_JUMP ("jge %l0", "fjge %l0", "jpl %l0"); 6238}) 6239 6240(define_insn "bgeu" 6241 [(set (pc) 6242 (if_then_else (geu (cc0) 6243 (const_int 0)) 6244 (label_ref (match_operand 0 "" "")) 6245 (pc)))] 6246 "" 6247{ 6248 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6249 { 6250 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6251 return 0; 6252 } 6253 6254 return "jcc %l0"; 6255} 6256 [(set_attr "type" "bcc")]) 6257 6258(define_insn "ble" 6259 [(set (pc) 6260 (if_then_else (le (cc0) 6261 (const_int 0)) 6262 (label_ref (match_operand 0 "" "")) 6263 (pc)))] 6264 "" 6265{ 6266 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6267 { 6268 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6269 return 0; 6270 } 6271 6272 OUTPUT_JUMP ("jle %l0", "fjle %l0", 0); 6273} 6274 [(set_attr "type" "bcc")]) 6275 6276(define_insn "bleu" 6277 [(set (pc) 6278 (if_then_else (leu (cc0) 6279 (const_int 0)) 6280 (label_ref (match_operand 0 "" "")) 6281 (pc)))] 6282 "" 6283{ 6284 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6285 { 6286 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6287 return 0; 6288 } 6289 6290 return "jls %l0"; 6291} 6292 [(set_attr "type" "bcc")]) 6293 6294(define_insn "bordered" 6295 [(set (pc) 6296 (if_then_else (ordered (cc0) (const_int 0)) 6297 (label_ref (match_operand 0 "" "")) 6298 (pc)))] 6299 "TARGET_HARD_FLOAT" 6300{ 6301 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6302 return "fjor %l0"; 6303} 6304 [(set_attr "type" "fbcc")]) 6305 6306(define_insn "bunordered" 6307 [(set (pc) 6308 (if_then_else (unordered (cc0) (const_int 0)) 6309 (label_ref (match_operand 0 "" "")) 6310 (pc)))] 6311 "TARGET_HARD_FLOAT" 6312{ 6313 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6314 return "fjun %l0"; 6315} 6316 [(set_attr "type" "fbcc")]) 6317 6318(define_insn "buneq" 6319 [(set (pc) 6320 (if_then_else (uneq (cc0) (const_int 0)) 6321 (label_ref (match_operand 0 "" "")) 6322 (pc)))] 6323 "TARGET_HARD_FLOAT" 6324{ 6325 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6326 return "fjueq %l0"; 6327} 6328 [(set_attr "type" "fbcc")]) 6329 6330(define_insn "bunge" 6331 [(set (pc) 6332 (if_then_else (unge (cc0) (const_int 0)) 6333 (label_ref (match_operand 0 "" "")) 6334 (pc)))] 6335 "TARGET_HARD_FLOAT" 6336{ 6337 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6338 return "fjuge %l0"; 6339} 6340 [(set_attr "type" "fbcc")]) 6341 6342(define_insn "bungt" 6343 [(set (pc) 6344 (if_then_else (ungt (cc0) (const_int 0)) 6345 (label_ref (match_operand 0 "" "")) 6346 (pc)))] 6347 "TARGET_HARD_FLOAT" 6348{ 6349 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6350 return "fjugt %l0"; 6351} 6352 [(set_attr "type" "fbcc")]) 6353 6354(define_insn "bunle" 6355 [(set (pc) 6356 (if_then_else (unle (cc0) (const_int 0)) 6357 (label_ref (match_operand 0 "" "")) 6358 (pc)))] 6359 "TARGET_HARD_FLOAT" 6360{ 6361 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6362 return "fjule %l0"; 6363} 6364 [(set_attr "type" "fbcc")]) 6365 6366(define_insn "bunlt" 6367 [(set (pc) 6368 (if_then_else (unlt (cc0) (const_int 0)) 6369 (label_ref (match_operand 0 "" "")) 6370 (pc)))] 6371 "TARGET_HARD_FLOAT" 6372{ 6373 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6374 return "fjult %l0"; 6375} 6376 [(set_attr "type" "fbcc")]) 6377 6378(define_insn "bltgt" 6379 [(set (pc) 6380 (if_then_else (ltgt (cc0) (const_int 0)) 6381 (label_ref (match_operand 0 "" "")) 6382 (pc)))] 6383 "TARGET_HARD_FLOAT" 6384{ 6385 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6386 return "fjogl %l0"; 6387} 6388 [(set_attr "type" "fbcc")]) 6389 6390;; Negated conditional jump instructions. 6391 6392(define_insn "*beq_rev" 6393 [(set (pc) 6394 (if_then_else (eq (cc0) 6395 (const_int 0)) 6396 (pc) 6397 (label_ref (match_operand 0 "" ""))))] 6398 "" 6399{ 6400 OUTPUT_JUMP ("jne %l0", "fjne %l0", "jne %l0"); 6401} 6402 [(set_attr "type" "bcc")]) 6403 6404(define_insn "*bne_rev" 6405 [(set (pc) 6406 (if_then_else (ne (cc0) 6407 (const_int 0)) 6408 (pc) 6409 (label_ref (match_operand 0 "" ""))))] 6410 "" 6411{ 6412 OUTPUT_JUMP ("jeq %l0", "fjeq %l0", "jeq %l0"); 6413} 6414 [(set_attr "type" "bcc")]) 6415 6416(define_insn "*bgt_rev" 6417 [(set (pc) 6418 (if_then_else (gt (cc0) 6419 (const_int 0)) 6420 (pc) 6421 (label_ref (match_operand 0 "" ""))))] 6422 "" 6423{ 6424 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6425 { 6426 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6427 return 0; 6428 } 6429 6430 OUTPUT_JUMP ("jle %l0", "fjngt %l0", 0); 6431} 6432 [(set_attr "type" "bcc")]) 6433 6434(define_insn "*bgtu_rev" 6435 [(set (pc) 6436 (if_then_else (gtu (cc0) 6437 (const_int 0)) 6438 (pc) 6439 (label_ref (match_operand 0 "" ""))))] 6440 "" 6441{ 6442 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6443 { 6444 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6445 return 0; 6446 } 6447 6448 return "jls %l0"; 6449} 6450 [(set_attr "type" "bcc")]) 6451 6452(define_insn "*blt_rev" 6453 [(set (pc) 6454 (if_then_else (lt (cc0) 6455 (const_int 0)) 6456 (pc) 6457 (label_ref (match_operand 0 "" ""))))] 6458 "" 6459{ 6460 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6461 { 6462 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6463 return 0; 6464 } 6465 6466 OUTPUT_JUMP ("jge %l0", "fjnlt %l0", "jpl %l0"); 6467} 6468 [(set_attr "type" "bcc")]) 6469 6470(define_insn "*bltu_rev" 6471 [(set (pc) 6472 (if_then_else (ltu (cc0) 6473 (const_int 0)) 6474 (pc) 6475 (label_ref (match_operand 0 "" ""))))] 6476 "" 6477{ 6478 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6479 { 6480 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6481 return 0; 6482 } 6483 6484 return "jcc %l0"; 6485} 6486 [(set_attr "type" "bcc")]) 6487 6488(define_insn "*bge_rev" 6489 [(set (pc) 6490 (if_then_else (ge (cc0) 6491 (const_int 0)) 6492 (pc) 6493 (label_ref (match_operand 0 "" ""))))] 6494 "" 6495{ 6496 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6497 { 6498 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6499 return 0; 6500 } 6501 6502 OUTPUT_JUMP ("jlt %l0", "fjnge %l0", "jmi %l0"); 6503} 6504 [(set_attr "type" "bcc")]) 6505 6506(define_insn "*bgeu_rev" 6507 [(set (pc) 6508 (if_then_else (geu (cc0) 6509 (const_int 0)) 6510 (pc) 6511 (label_ref (match_operand 0 "" ""))))] 6512 "" 6513{ 6514 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6515 { 6516 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6517 return 0; 6518 } 6519 6520 return "jcs %l0"; 6521} 6522 [(set_attr "type" "bcc")]) 6523 6524(define_insn "*ble_rev" 6525 [(set (pc) 6526 (if_then_else (le (cc0) 6527 (const_int 0)) 6528 (pc) 6529 (label_ref (match_operand 0 "" ""))))] 6530 "" 6531{ 6532 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6533 { 6534 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6535 return 0; 6536 } 6537 6538 OUTPUT_JUMP ("jgt %l0", "fjnle %l0", 0); 6539} 6540 [(set_attr "type" "bcc")]) 6541 6542(define_insn "*bleu_rev" 6543 [(set (pc) 6544 (if_then_else (leu (cc0) 6545 (const_int 0)) 6546 (pc) 6547 (label_ref (match_operand 0 "" ""))))] 6548 "" 6549{ 6550 if ((cc_status.flags & CC_OVERFLOW_UNUSABLE) != 0) 6551 { 6552 cc_status.flags &= ~CC_OVERFLOW_UNUSABLE; 6553 return 0; 6554 } 6555 6556 return "jhi %l0"; 6557} 6558 [(set_attr "type" "bcc")]) 6559 6560(define_insn "*bordered_rev" 6561 [(set (pc) 6562 (if_then_else (ordered (cc0) (const_int 0)) 6563 (pc) 6564 (label_ref (match_operand 0 "" ""))))] 6565 "TARGET_HARD_FLOAT" 6566{ 6567 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6568 return "fjun %l0"; 6569} 6570 [(set_attr "type" "fbcc")]) 6571 6572(define_insn "*bunordered_rev" 6573 [(set (pc) 6574 (if_then_else (unordered (cc0) (const_int 0)) 6575 (pc) 6576 (label_ref (match_operand 0 "" ""))))] 6577 "TARGET_HARD_FLOAT" 6578{ 6579 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6580 return "fjor %l0"; 6581} 6582 [(set_attr "type" "fbcc")]) 6583 6584(define_insn "*buneq_rev" 6585 [(set (pc) 6586 (if_then_else (uneq (cc0) (const_int 0)) 6587 (pc) 6588 (label_ref (match_operand 0 "" ""))))] 6589 "TARGET_HARD_FLOAT" 6590{ 6591 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6592 return "fjogl %l0"; 6593} 6594 [(set_attr "type" "fbcc")]) 6595 6596(define_insn "*bunge_rev" 6597 [(set (pc) 6598 (if_then_else (unge (cc0) (const_int 0)) 6599 (pc) 6600 (label_ref (match_operand 0 "" ""))))] 6601 "TARGET_HARD_FLOAT" 6602{ 6603 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6604 return "fjolt %l0"; 6605} 6606 [(set_attr "type" "fbcc")]) 6607 6608(define_insn "*bungt_rev" 6609 [(set (pc) 6610 (if_then_else (ungt (cc0) (const_int 0)) 6611 (pc) 6612 (label_ref (match_operand 0 "" ""))))] 6613 "TARGET_HARD_FLOAT" 6614{ 6615 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6616 return "fjole %l0"; 6617} 6618 [(set_attr "type" "fbcc")]) 6619 6620(define_insn "*bunle_rev" 6621 [(set (pc) 6622 (if_then_else (unle (cc0) (const_int 0)) 6623 (pc) 6624 (label_ref (match_operand 0 "" ""))))] 6625 "TARGET_HARD_FLOAT" 6626{ 6627 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6628 return "fjogt %l0"; 6629} 6630 [(set_attr "type" "fbcc")]) 6631 6632(define_insn "*bunlt_rev" 6633 [(set (pc) 6634 (if_then_else (unlt (cc0) (const_int 0)) 6635 (pc) 6636 (label_ref (match_operand 0 "" ""))))] 6637 "TARGET_HARD_FLOAT" 6638{ 6639 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6640 return "fjoge %l0"; 6641} 6642 [(set_attr "type" "fbcc")]) 6643 6644(define_insn "*bltgt_rev" 6645 [(set (pc) 6646 (if_then_else (ltgt (cc0) (const_int 0)) 6647 (pc) 6648 (label_ref (match_operand 0 "" ""))))] 6649 "TARGET_HARD_FLOAT" 6650{ 6651 gcc_assert (cc_prev_status.flags & CC_IN_68881); 6652 return "fjueq %l0"; 6653} 6654 [(set_attr "type" "fbcc")]) 6655 6656;; Unconditional and other jump instructions 6657(define_insn "jump" 6658 [(set (pc) 6659 (label_ref (match_operand 0 "" "")))] 6660 "" 6661 "jra %l0" 6662 [(set_attr "type" "bra")]) 6663 6664(define_expand "tablejump" 6665 [(parallel [(set (pc) (match_operand 0 "" "")) 6666 (use (label_ref (match_operand 1 "" "")))])] 6667 "" 6668{ 6669#if CASE_VECTOR_PC_RELATIVE 6670 operands[0] = gen_rtx_PLUS (SImode, pc_rtx, 6671 gen_rtx_SIGN_EXTEND (SImode, operands[0])); 6672#endif 6673}) 6674 6675;; Jump to variable address from dispatch table of absolute addresses. 6676(define_insn "*tablejump_internal" 6677 [(set (pc) (match_operand:SI 0 "register_operand" "a")) 6678 (use (label_ref (match_operand 1 "" "")))] 6679 "" 6680{ 6681 return MOTOROLA ? "jmp (%0)" : "jmp %0@"; 6682} 6683 [(set_attr "type" "jmp")]) 6684 6685;; Jump to variable address from dispatch table of relative addresses. 6686(define_insn "" 6687 [(set (pc) 6688 (plus:SI (pc) 6689 (sign_extend:SI (match_operand:HI 0 "register_operand" "r")))) 6690 (use (label_ref (match_operand 1 "" "")))] 6691 "" 6692{ 6693#ifdef ASM_RETURN_CASE_JUMP 6694 ASM_RETURN_CASE_JUMP; 6695#else 6696 if (TARGET_COLDFIRE) 6697 { 6698 if (ADDRESS_REG_P (operands[0])) 6699 return MOTOROLA ? "jmp (2,pc,%0.l)" : "jmp pc@(2,%0:l)"; 6700 else if (MOTOROLA) 6701 return "ext%.l %0\;jmp (2,pc,%0.l)"; 6702 else 6703 return "extl %0\;jmp pc@(2,%0:l)"; 6704 } 6705 else 6706 return MOTOROLA ? "jmp (2,pc,%0.w)" : "jmp pc@(2,%0:w)"; 6707#endif 6708}) 6709 6710;; Decrement-and-branch insns. 6711(define_insn "*dbne_hi" 6712 [(set (pc) 6713 (if_then_else 6714 (ne (match_operand:HI 0 "nonimmediate_operand" "+d*g") 6715 (const_int 0)) 6716 (label_ref (match_operand 1 "" "")) 6717 (pc))) 6718 (set (match_dup 0) 6719 (plus:HI (match_dup 0) 6720 (const_int -1)))] 6721 "!TARGET_COLDFIRE" 6722{ 6723 CC_STATUS_INIT; 6724 if (DATA_REG_P (operands[0])) 6725 return "dbra %0,%l1"; 6726 if (GET_CODE (operands[0]) == MEM) 6727 return "subq%.w #1,%0\;jcc %l1"; 6728 return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1"; 6729}) 6730 6731(define_insn "*dbne_si" 6732 [(set (pc) 6733 (if_then_else 6734 (ne (match_operand:SI 0 "nonimmediate_operand" "+d*g") 6735 (const_int 0)) 6736 (label_ref (match_operand 1 "" "")) 6737 (pc))) 6738 (set (match_dup 0) 6739 (plus:SI (match_dup 0) 6740 (const_int -1)))] 6741 "!TARGET_COLDFIRE" 6742{ 6743 CC_STATUS_INIT; 6744 if (DATA_REG_P (operands[0])) 6745 return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1"; 6746 if (GET_CODE (operands[0]) == MEM) 6747 return "subq%.l #1,%0\;jcc %l1"; 6748 return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1"; 6749}) 6750 6751;; Two dbra patterns that use REG_NOTES info generated by strength_reduce. 6752 6753(define_insn "*dbge_hi" 6754 [(set (pc) 6755 (if_then_else 6756 (ge (plus:HI (match_operand:HI 0 "nonimmediate_operand" "+d*am") 6757 (const_int -1)) 6758 (const_int 0)) 6759 (label_ref (match_operand 1 "" "")) 6760 (pc))) 6761 (set (match_dup 0) 6762 (plus:HI (match_dup 0) 6763 (const_int -1)))] 6764 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)" 6765{ 6766 CC_STATUS_INIT; 6767 if (DATA_REG_P (operands[0])) 6768 return "dbra %0,%l1"; 6769 if (GET_CODE (operands[0]) == MEM) 6770 return "subq%.w #1,%0\;jcc %l1"; 6771 return "subq%.w #1,%0\;cmp%.w #-1,%0\;jne %l1"; 6772}) 6773 6774(define_expand "decrement_and_branch_until_zero" 6775 [(parallel [(set (pc) 6776 (if_then_else 6777 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "") 6778 (const_int -1)) 6779 (const_int 0)) 6780 (label_ref (match_operand 1 "" "")) 6781 (pc))) 6782 (set (match_dup 0) 6783 (plus:SI (match_dup 0) 6784 (const_int -1)))])] 6785 "" 6786 "") 6787 6788(define_insn "*dbge_si" 6789 [(set (pc) 6790 (if_then_else 6791 (ge (plus:SI (match_operand:SI 0 "nonimmediate_operand" "+d*am") 6792 (const_int -1)) 6793 (const_int 0)) 6794 (label_ref (match_operand 1 "" "")) 6795 (pc))) 6796 (set (match_dup 0) 6797 (plus:SI (match_dup 0) 6798 (const_int -1)))] 6799 "!TARGET_COLDFIRE && find_reg_note (insn, REG_NONNEG, 0)" 6800{ 6801 CC_STATUS_INIT; 6802 if (DATA_REG_P (operands[0])) 6803 return "dbra %0,%l1\;clr%.w %0\;subq%.l #1,%0\;jcc %l1"; 6804 if (GET_CODE (operands[0]) == MEM) 6805 return "subq%.l #1,%0\;jcc %l1"; 6806 return "subq%.l #1,%0\;cmp%.l #-1,%0\;jne %l1"; 6807}) 6808 6809(define_expand "sibcall" 6810 [(call (match_operand:QI 0 "memory_operand" "") 6811 (match_operand:SI 1 "general_operand" ""))] 6812 "" 6813{ 6814 operands[0] = m68k_legitimize_sibcall_address (operands[0]); 6815}) 6816 6817(define_insn "*sibcall" 6818 [(call (mem:QI (match_operand:SI 0 "sibcall_operand" "")) 6819 (match_operand:SI 1 "general_operand" ""))] 6820 "SIBLING_CALL_P (insn)" 6821{ 6822 return output_sibcall (operands[0]); 6823}) 6824 6825(define_expand "sibcall_value" 6826 [(set (match_operand 0 "" "") 6827 (call (match_operand:QI 1 "memory_operand" "") 6828 (match_operand:SI 2 "general_operand" "")))] 6829 "" 6830{ 6831 operands[1] = m68k_legitimize_sibcall_address (operands[1]); 6832}) 6833 6834(define_insn "*sibcall_value" 6835 [(set (match_operand 0 "" "=rf,rf") 6836 (call (mem:QI (match_operand:SI 1 "sibcall_operand" "")) 6837 (match_operand:SI 2 "general_operand" "")))] 6838 "SIBLING_CALL_P (insn)" 6839{ 6840 operands[0] = operands[1]; 6841 return output_sibcall (operands[0]); 6842}) 6843 6844;; Call subroutine with no return value. 6845(define_expand "call" 6846 [(call (match_operand:QI 0 "memory_operand" "") 6847 (match_operand:SI 1 "general_operand" ""))] 6848 ;; Operand 1 not really used on the m68000. 6849 "" 6850{ 6851 operands[0] = m68k_legitimize_call_address (operands[0]); 6852}) 6853 6854(define_insn "*call" 6855 [(call (mem:QI (match_operand:SI 0 "call_operand" "a,W")) 6856 (match_operand:SI 1 "general_operand" "g,g"))] 6857 ;; Operand 1 not really used on the m68000. 6858 "!SIBLING_CALL_P (insn)" 6859{ 6860 return output_call (operands[0]); 6861} 6862 [(set_attr "type" "jsr")]) 6863 6864;; Call subroutine, returning value in operand 0 6865;; (which must be a hard register). 6866(define_expand "call_value" 6867 [(set (match_operand 0 "" "") 6868 (call (match_operand:QI 1 "memory_operand" "") 6869 (match_operand:SI 2 "general_operand" "")))] 6870 ;; Operand 2 not really used on the m68000. 6871 "" 6872{ 6873 operands[1] = m68k_legitimize_call_address (operands[1]); 6874}) 6875 6876(define_insn "*non_symbolic_call_value" 6877 [(set (match_operand 0 "" "=rf,rf") 6878 (call (mem:QI (match_operand:SI 1 "non_symbolic_call_operand" "a,W")) 6879 (match_operand:SI 2 "general_operand" "g,g")))] 6880 ;; Operand 2 not really used on the m68000. 6881 "!SIBLING_CALL_P (insn)" 6882 "jsr %a1" 6883 [(set_attr "type" "jsr") 6884 (set_attr "opx" "1")]) 6885 6886(define_insn "*symbolic_call_value_jsr" 6887 [(set (match_operand 0 "" "=rf,rf") 6888 (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W")) 6889 (match_operand:SI 2 "general_operand" "g,g")))] 6890 ;; Operand 2 not really used on the m68000. 6891 "!SIBLING_CALL_P (insn) && m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_JSR" 6892{ 6893 operands[0] = operands[1]; 6894 return m68k_symbolic_call; 6895} 6896 [(set_attr "type" "jsr") 6897 (set_attr "opx" "1")]) 6898 6899(define_insn "*symbolic_call_value_bsr" 6900 [(set (match_operand 0 "" "=rf,rf") 6901 (call (mem:QI (match_operand:SI 1 "symbolic_operand" "a,W")) 6902 (match_operand:SI 2 "general_operand" "g,g")))] 6903 ;; Operand 2 not really used on the m68000. 6904 "!SIBLING_CALL_P (insn) 6905 && (m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_C 6906 || m68k_symbolic_call_var == M68K_SYMBOLIC_CALL_BSR_P)" 6907{ 6908 operands[0] = operands[1]; 6909 return m68k_symbolic_call; 6910} 6911 [(set_attr "type" "bsr") 6912 (set_attr "opx" "1")]) 6913 6914;; Call subroutine returning any type. 6915 6916(define_expand "untyped_call" 6917 [(parallel [(call (match_operand 0 "" "") 6918 (const_int 0)) 6919 (match_operand 1 "" "") 6920 (match_operand 2 "" "")])] 6921 "NEEDS_UNTYPED_CALL" 6922{ 6923 int i; 6924 6925 emit_call_insn (GEN_CALL (operands[0], const0_rtx, NULL, const0_rtx)); 6926 6927 for (i = 0; i < XVECLEN (operands[2], 0); i++) 6928 { 6929 rtx set = XVECEXP (operands[2], 0, i); 6930 emit_move_insn (SET_DEST (set), SET_SRC (set)); 6931 } 6932 6933 /* The optimizer does not know that the call sets the function value 6934 registers we stored in the result block. We avoid problems by 6935 claiming that all hard registers are used and clobbered at this 6936 point. */ 6937 emit_insn (gen_blockage ()); 6938 6939 DONE; 6940}) 6941 6942;; UNSPEC_VOLATILE is considered to use and clobber all hard registers and 6943;; all of memory. This blocks insns from being moved across this point. 6944 6945(define_insn "blockage" 6946 [(unspec_volatile [(const_int 0)] UNSPECV_BLOCKAGE)] 6947 "" 6948 "") 6949 6950(define_insn "nop" 6951 [(const_int 0)] 6952 "" 6953 "nop" 6954 [(set_attr "type" "nop")]) 6955 6956(define_expand "prologue" 6957 [(const_int 0)] 6958 "" 6959{ 6960 m68k_expand_prologue (); 6961 DONE; 6962}) 6963 6964(define_expand "epilogue" 6965 [(return)] 6966 "" 6967{ 6968 m68k_expand_epilogue (false); 6969 DONE; 6970}) 6971 6972(define_expand "sibcall_epilogue" 6973 [(return)] 6974 "" 6975{ 6976 m68k_expand_epilogue (true); 6977 DONE; 6978}) 6979 6980;; Used for frameless functions which save no regs and allocate no locals. 6981(define_expand "return" 6982 [(return)] 6983 "m68k_use_return_insn ()" 6984 "") 6985 6986(define_insn "*return" 6987 [(return)] 6988 "" 6989{ 6990 switch (m68k_get_function_kind (current_function_decl)) 6991 { 6992 case m68k_fk_interrupt_handler: 6993 return "rte"; 6994 6995 case m68k_fk_interrupt_thread: 6996 return "sleep"; 6997 6998 default: 6999 if (crtl->args.pops_args) 7000 { 7001 operands[0] = GEN_INT (crtl->args.pops_args); 7002 return "rtd %0"; 7003 } 7004 else 7005 return "rts"; 7006 } 7007} 7008 [(set_attr "type" "rts")]) 7009 7010(define_insn "*m68k_store_multiple" 7011 [(match_parallel 0 "" [(match_operand 1 "")])] 7012 "m68k_movem_pattern_p (operands[0], NULL, 0, true)" 7013{ 7014 return m68k_output_movem (operands, operands[0], 0, true); 7015}) 7016 7017(define_insn "*m68k_store_multiple_automod" 7018 [(match_parallel 0 "" 7019 [(set (match_operand:SI 1 "register_operand" "=a") 7020 (plus:SI (match_operand:SI 2 "register_operand" "1") 7021 (match_operand:SI 3 "const_int_operand")))])] 7022 "m68k_movem_pattern_p (operands[0], operands[1], INTVAL (operands[3]), true)" 7023{ 7024 return m68k_output_movem (operands, operands[0], INTVAL (operands[3]), true); 7025}) 7026 7027(define_insn "*m68k_load_multiple" 7028 [(match_parallel 0 "" [(match_operand 1 "")])] 7029 "m68k_movem_pattern_p (operands[0], NULL, 0, false)" 7030{ 7031 return m68k_output_movem (operands, operands[0], 0, false); 7032}) 7033 7034(define_insn "*m68k_load_multiple_automod" 7035 [(match_parallel 0 "" 7036 [(set (match_operand:SI 1 "register_operand" "=a") 7037 (plus:SI (match_operand:SI 2 "register_operand" "1") 7038 (match_operand:SI 3 "const_int_operand")))])] 7039 "m68k_movem_pattern_p (operands[0], operands[1], 7040 INTVAL (operands[3]), false)" 7041{ 7042 return m68k_output_movem (operands, operands[0], 7043 INTVAL (operands[3]), false); 7044}) 7045 7046(define_expand "link" 7047 [(parallel 7048 [(set (match_operand:SI 0 "register_operand") 7049 (plus:SI (reg:SI SP_REG) (const_int -4))) 7050 (set (match_dup 2) 7051 (match_dup 0)) 7052 (set (reg:SI SP_REG) 7053 (plus:SI (reg:SI SP_REG) 7054 (match_operand:SI 1 "const_int_operand")))])] 7055 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004" 7056{ 7057 operands[2] = gen_frame_mem (SImode, 7058 plus_constant (Pmode, stack_pointer_rtx, -4)); 7059}) 7060 7061(define_insn "*link" 7062 [(set (match_operand:SI 0 "register_operand" "+r") 7063 (plus:SI (reg:SI SP_REG) (const_int -4))) 7064 (set (mem:SI (plus:SI (reg:SI SP_REG) (const_int -4))) 7065 (match_dup 0)) 7066 (set (reg:SI SP_REG) 7067 (plus:SI (reg:SI SP_REG) 7068 (match_operand:SI 1 "const_int_operand")))] 7069 "TARGET_68020 || INTVAL (operands[1]) >= -0x8004" 7070{ 7071 operands[1] = GEN_INT (INTVAL (operands[1]) + 4); 7072 if (!MOTOROLA) 7073 return "link %0,%1"; 7074 else if (INTVAL (operands[1]) >= -0x8000) 7075 return "link.w %0,%1"; 7076 else 7077 return "link.l %0,%1"; 7078} 7079 [(set_attr "type" "link")]) 7080 7081(define_expand "unlink" 7082 [(parallel 7083 [(set (match_operand:SI 0 "register_operand") 7084 (match_dup 1)) 7085 (set (reg:SI SP_REG) 7086 (plus:SI (match_dup 0) 7087 (const_int 4)))])] 7088 "" 7089{ 7090 operands[1] = gen_frame_mem (SImode, copy_rtx (operands[0])); 7091}) 7092 7093(define_insn "*unlink" 7094 [(set (match_operand:SI 0 "register_operand" "+r") 7095 (mem:SI (match_dup 0))) 7096 (set (reg:SI SP_REG) 7097 (plus:SI (match_dup 0) 7098 (const_int 4)))] 7099 "" 7100 "unlk %0" 7101 [(set_attr "type" "unlk")]) 7102 7103(define_insn "load_got" 7104 [(set (match_operand:SI 0 "register_operand" "=a") 7105 (unspec:SI [(const_int 0)] UNSPEC_GOT))] 7106 "" 7107{ 7108 if (TARGET_ID_SHARED_LIBRARY) 7109 { 7110 operands[1] = gen_rtx_REG (Pmode, PIC_REG); 7111 return MOTOROLA ? "move.l %?(%1),%0" : "movel %1@(%?), %0"; 7112 } 7113 else if (MOTOROLA) 7114 { 7115 if (TARGET_COLDFIRE) 7116 /* Load the full 32-bit PC-relative offset of 7117 _GLOBAL_OFFSET_TABLE_ into the PIC register, then use it to 7118 calculate the absolute value. The offset and "lea" 7119 operation word together occupy 6 bytes. */ 7120 return ("move.l #_GLOBAL_OFFSET_TABLE_@GOTPC, %0\n\t" 7121 "lea (-6, %%pc, %0), %0"); 7122 else 7123 return "lea (%%pc, _GLOBAL_OFFSET_TABLE_@GOTPC), %0"; 7124 } 7125 else 7126 return ("movel #_GLOBAL_OFFSET_TABLE_, %0\n\t" 7127 "lea %%pc@(0,%0:l),%0"); 7128}) 7129 7130(define_insn "indirect_jump" 7131 [(set (pc) (match_operand:SI 0 "address_operand" "p"))] 7132 "" 7133 "jmp %a0" 7134 [(set_attr "type" "jmp")]) 7135 7136;; This should not be used unless the add/sub insns can't be. 7137 7138(define_insn "*lea" 7139 [(set (match_operand:SI 0 "nonimmediate_operand" "=a") 7140 (match_operand:QI 1 "address_operand" "p"))] 7141 "" 7142 "lea %a1,%0") 7143 7144;; This is the first machine-dependent peephole optimization. 7145;; It is useful when a floating value is returned from a function call 7146;; and then is moved into an FP register. 7147;; But it is mainly intended to test the support for these optimizations. 7148 7149(define_peephole2 7150 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) 7151 (set (match_operand:DF 0 "register_operand" "") 7152 (match_operand:DF 1 "register_operand" ""))] 7153 "FP_REG_P (operands[0]) && !FP_REG_P (operands[1])" 7154 [(set (mem:SI (reg:SI SP_REG)) (match_dup 1)) 7155 (set (mem:SI (pre_dec:SI (reg:SI SP_REG))) (match_dup 2)) 7156 (set (match_dup 0) (mem:DF (post_inc:SI (reg:SI SP_REG))))] 7157 "split_di(operands + 1, 1, operands + 1, operands + 2);") 7158 7159;; Optimize a stack-adjust followed by a push of an argument. 7160;; This is said to happen frequently with -msoft-float 7161;; when there are consecutive library calls. 7162 7163(define_peephole2 7164 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) 7165 (set (match_operand:SF 0 "push_operand" "") 7166 (match_operand:SF 1 "general_operand" ""))] 7167 "!reg_mentioned_p (stack_pointer_rtx, operands[0])" 7168 [(set (match_dup 0) (match_dup 1))] 7169 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);") 7170 7171(define_peephole2 7172 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) 7173 (match_operand:SI 0 "const_int_operand" ""))) 7174 (set (match_operand:SF 1 "push_operand" "") 7175 (match_operand:SF 2 "general_operand" ""))] 7176 "INTVAL (operands[0]) > 4 7177 && !reg_mentioned_p (stack_pointer_rtx, operands[2])" 7178 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0))) 7179 (set (match_dup 1) (match_dup 2))] 7180{ 7181 operands[0] = GEN_INT (INTVAL (operands[0]) - 4); 7182 operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx); 7183}) 7184 7185;; Speed up stack adjust followed by a fullword fixedpoint push. 7186;; Constant operands need special care, as replacing a "pea X.w" with 7187;; "move.l #X,(%sp)" is often not a win. 7188 7189;; Already done by the previous csa pass, left as reference. 7190(define_peephole2 7191 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 4))) 7192 (set (match_operand:SI 0 "push_operand" "") 7193 (match_operand:SI 1 "general_operand" ""))] 7194 "!reg_mentioned_p (stack_pointer_rtx, operands[1])" 7195 [(set (match_dup 0) (match_dup 1))] 7196 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);") 7197 7198;; Try to use moveq, after stack push has been changed into a simple move. 7199(define_peephole2 7200 [(match_scratch:SI 2 "d") 7201 (set (match_operand:SI 0 "memory_operand" "") 7202 (match_operand:SI 1 "const_int_operand" ""))] 7203 "GET_CODE (XEXP (operands[0], 0)) != PRE_DEC 7204 && INTVAL (operands[1]) != 0 7205 && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f) 7206 && !valid_mov3q_const (INTVAL (operands[1]))" 7207 [(set (match_dup 2) (match_dup 1)) 7208 (set (match_dup 0) (match_dup 2))]) 7209 7210;; This sequence adds an instruction, but is two bytes shorter. 7211(define_peephole2 7212 [(match_scratch:SI 2 "d") 7213 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 12))) 7214 (set (match_operand:SI 0 "push_operand" "") 7215 (match_operand:SI 1 "const_int_operand" ""))] 7216 "INTVAL (operands[1]) != 0 7217 && IN_RANGE (INTVAL (operands[1]), -0x80, 0x7f) 7218 && !valid_mov3q_const (INTVAL (operands[1]))" 7219 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int 8))) 7220 (set (match_dup 2) (match_dup 1)) 7221 (set (match_dup 0) (match_dup 2))] 7222 "operands[0] = replace_equiv_address (operands[0], stack_pointer_rtx);") 7223 7224;; Changing pea X.w into a move.l is no real win here. 7225(define_peephole2 7226 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) 7227 (match_operand:SI 0 "const_int_operand" ""))) 7228 (set (match_operand:SI 1 "push_operand" "") 7229 (match_operand:SI 2 "general_operand" ""))] 7230 "INTVAL (operands[0]) > 4 7231 && !reg_mentioned_p (stack_pointer_rtx, operands[2]) 7232 && !(CONST_INT_P (operands[2]) && INTVAL (operands[2]) != 0 7233 && IN_RANGE (INTVAL (operands[2]), -0x8000, 0x7fff) 7234 && !valid_mov3q_const (INTVAL (operands[2])))" 7235 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (match_dup 0))) 7236 (set (match_dup 1) (match_dup 2))] 7237{ 7238 operands[0] = GEN_INT (INTVAL (operands[0]) - 4); 7239 operands[1] = replace_equiv_address (operands[1], stack_pointer_rtx); 7240}) 7241 7242;; Speed up pushing a single byte/two bytes but leaving four bytes of space 7243;; (which differs slightly between m680x0 and ColdFire). 7244 7245(define_peephole2 7246 [(set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -4))) 7247 (set (match_operand:QI 0 "memory_operand" "") 7248 (match_operand:QI 1 "register_operand" ""))] 7249 "!reg_mentioned_p (stack_pointer_rtx, operands[1]) 7250 && GET_CODE (XEXP (operands[0], 0)) == PLUS 7251 && rtx_equal_p (XEXP (XEXP (operands[0], 0), 0), stack_pointer_rtx) 7252 && CONST_INT_P (XEXP (XEXP (operands[0], 0), 1)) 7253 && INTVAL (XEXP (XEXP (operands[0], 0), 1)) == 3" 7254 [(set (match_dup 0) (match_dup 1))] 7255{ 7256 rtx addr = gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx); 7257 operands[0] = adjust_automodify_address (operands[0], SImode, addr, -3); 7258 operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0); 7259}) 7260 7261(define_peephole2 7262 [(set (match_operand:QI 0 "push_operand" "") 7263 (match_operand:QI 1 "register_operand" "")) 7264 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -3)))] 7265 "!reg_mentioned_p (stack_pointer_rtx, operands[1])" 7266 [(set (match_dup 0) (match_dup 1))] 7267{ 7268 operands[0] = adjust_automodify_address (operands[0], SImode, 7269 XEXP (operands[0], 0), -3); 7270 operands[1] = simplify_gen_subreg (SImode, operands[1], QImode, 0); 7271}) 7272 7273(define_peephole2 7274 [(set (match_operand:HI 0 "push_operand" "") 7275 (match_operand:HI 1 "register_operand" "")) 7276 (set (reg:SI SP_REG) (plus:SI (reg:SI SP_REG) (const_int -2)))] 7277 "!reg_mentioned_p (stack_pointer_rtx, operands[1])" 7278 [(set (match_dup 0) (match_dup 1))] 7279{ 7280 operands[0] = adjust_automodify_address (operands[0], SImode, 7281 XEXP (operands[0], 0), -2); 7282 operands[1] = simplify_gen_subreg (SImode, operands[1], HImode, 0); 7283}) 7284 7285;; Optimize a series of strict_low_part assignments 7286 7287(define_peephole2 7288 [(set (match_operand:SI 0 "register_operand" "") 7289 (const_int 0)) 7290 (set (strict_low_part (match_operand:HI 1 "register_operand" "")) 7291 (match_operand:HI 2 "general_operand" ""))] 7292 "REGNO (operands[0]) == REGNO (operands[1]) 7293 && strict_low_part_peephole_ok (HImode, insn, operands[0])" 7294 [(set (strict_low_part (match_dup 1)) (match_dup 2))] 7295 "") 7296 7297(define_peephole2 7298 [(set (match_operand:SI 0 "register_operand" "") 7299 (const_int 0)) 7300 (set (strict_low_part (match_operand:QI 1 "register_operand" "")) 7301 (match_operand:QI 2 "general_operand" ""))] 7302 "REGNO (operands[0]) == REGNO (operands[1]) 7303 && strict_low_part_peephole_ok (QImode, insn, operands[0])" 7304 [(set (strict_low_part (match_dup 1)) (match_dup 2))] 7305 "") 7306 7307;; dbCC peepholes 7308;; 7309;; Turns 7310;; loop: 7311;; [ ... ] 7312;; jCC label ; abnormal loop termination 7313;; dbra dN, loop ; normal loop termination 7314;; 7315;; Into 7316;; loop: 7317;; [ ... ] 7318;; dbCC dN, loop 7319;; jCC label 7320;; 7321;; Which moves the jCC condition outside the inner loop for free. 7322;; 7323 7324(define_peephole 7325 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" 7326 [(cc0) (const_int 0)]) 7327 (label_ref (match_operand 2 "" "")) 7328 (pc))) 7329 (parallel 7330 [(set (pc) 7331 (if_then_else 7332 (ne (match_operand:HI 0 "register_operand" "") 7333 (const_int 0)) 7334 (label_ref (match_operand 1 "" "")) 7335 (pc))) 7336 (set (match_dup 0) 7337 (plus:HI (match_dup 0) 7338 (const_int -1)))])] 7339 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" 7340{ 7341 CC_STATUS_INIT; 7342 output_dbcc_and_branch (operands); 7343 return ""; 7344}) 7345 7346(define_peephole 7347 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" 7348 [(cc0) (const_int 0)]) 7349 (label_ref (match_operand 2 "" "")) 7350 (pc))) 7351 (parallel 7352 [(set (pc) 7353 (if_then_else 7354 (ne (match_operand:SI 0 "register_operand" "") 7355 (const_int 0)) 7356 (label_ref (match_operand 1 "" "")) 7357 (pc))) 7358 (set (match_dup 0) 7359 (plus:SI (match_dup 0) 7360 (const_int -1)))])] 7361 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" 7362{ 7363 CC_STATUS_INIT; 7364 output_dbcc_and_branch (operands); 7365 return ""; 7366}) 7367 7368(define_peephole 7369 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" 7370 [(cc0) (const_int 0)]) 7371 (label_ref (match_operand 2 "" "")) 7372 (pc))) 7373 (parallel 7374 [(set (pc) 7375 (if_then_else 7376 (ge (plus:HI (match_operand:HI 0 "register_operand" "") 7377 (const_int -1)) 7378 (const_int 0)) 7379 (label_ref (match_operand 1 "" "")) 7380 (pc))) 7381 (set (match_dup 0) 7382 (plus:HI (match_dup 0) 7383 (const_int -1)))])] 7384 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" 7385{ 7386 CC_STATUS_INIT; 7387 output_dbcc_and_branch (operands); 7388 return ""; 7389}) 7390 7391(define_peephole 7392 [(set (pc) (if_then_else (match_operator 3 "valid_dbcc_comparison_p" 7393 [(cc0) (const_int 0)]) 7394 (label_ref (match_operand 2 "" "")) 7395 (pc))) 7396 (parallel 7397 [(set (pc) 7398 (if_then_else 7399 (ge (plus:SI (match_operand:SI 0 "register_operand" "") 7400 (const_int -1)) 7401 (const_int 0)) 7402 (label_ref (match_operand 1 "" "")) 7403 (pc))) 7404 (set (match_dup 0) 7405 (plus:SI (match_dup 0) 7406 (const_int -1)))])] 7407 "!TARGET_COLDFIRE && DATA_REG_P (operands[0]) && ! flags_in_68881 ()" 7408{ 7409 CC_STATUS_INIT; 7410 output_dbcc_and_branch (operands); 7411 return ""; 7412}) 7413 7414 7415(define_insn "extendsfxf2" 7416 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f") 7417 (float_extend:XF (match_operand:SF 1 "general_operand" "f,rmF")))] 7418 "TARGET_68881" 7419{ 7420 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) 7421 { 7422 if (REGNO (operands[0]) == REGNO (operands[1])) 7423 { 7424 /* Extending float to double in an fp-reg is a no-op. 7425 NOTICE_UPDATE_CC has already assumed that the 7426 cc will be set. So cancel what it did. */ 7427 cc_status = cc_prev_status; 7428 return ""; 7429 } 7430 return "f%$move%.x %1,%0"; 7431 } 7432 if (FP_REG_P (operands[0])) 7433 { 7434 if (FP_REG_P (operands[1])) 7435 return "f%$move%.x %1,%0"; 7436 else if (ADDRESS_REG_P (operands[1])) 7437 return "move%.l %1,%-\;f%$move%.s %+,%0"; 7438 else if (GET_CODE (operands[1]) == CONST_DOUBLE) 7439 return output_move_const_single (operands); 7440 return "f%$move%.s %f1,%0"; 7441 } 7442 return "fmove%.x %f1,%0"; 7443}) 7444 7445 7446(define_insn "extenddfxf2" 7447 [(set (match_operand:XF 0 "nonimmediate_operand" "=fm,f") 7448 (float_extend:XF 7449 (match_operand:DF 1 "general_operand" "f,rmE")))] 7450 "TARGET_68881" 7451{ 7452 if (FP_REG_P (operands[0]) && FP_REG_P (operands[1])) 7453 { 7454 if (REGNO (operands[0]) == REGNO (operands[1])) 7455 { 7456 /* Extending float to double in an fp-reg is a no-op. 7457 NOTICE_UPDATE_CC has already assumed that the 7458 cc will be set. So cancel what it did. */ 7459 cc_status = cc_prev_status; 7460 return ""; 7461 } 7462 return "fmove%.x %1,%0"; 7463 } 7464 if (FP_REG_P (operands[0])) 7465 { 7466 if (REG_P (operands[1])) 7467 { 7468 rtx xoperands[2]; 7469 xoperands[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 7470 output_asm_insn ("move%.l %1,%-", xoperands); 7471 output_asm_insn ("move%.l %1,%-", operands); 7472 return "f%&move%.d %+,%0"; 7473 } 7474 if (GET_CODE (operands[1]) == CONST_DOUBLE) 7475 return output_move_const_double (operands); 7476 return "f%&move%.d %f1,%0"; 7477 } 7478 return "fmove%.x %f1,%0"; 7479}) 7480 7481(define_insn "truncxfdf2" 7482 [(set (match_operand:DF 0 "nonimmediate_operand" "=m,!r") 7483 (float_truncate:DF 7484 (match_operand:XF 1 "general_operand" "f,f")))] 7485 "TARGET_68881" 7486{ 7487 if (REG_P (operands[0])) 7488 { 7489 output_asm_insn ("fmove%.d %f1,%-\;move%.l %+,%0", operands); 7490 operands[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 7491 return "move%.l %+,%0"; 7492 } 7493 return "fmove%.d %f1,%0"; 7494}) 7495 7496(define_insn "truncxfsf2" 7497 [(set (match_operand:SF 0 "nonimmediate_operand" "=dm") 7498 (float_truncate:SF 7499 (match_operand:XF 1 "general_operand" "f")))] 7500 "TARGET_68881" 7501 "fmove%.s %f1,%0") 7502 7503(define_insn "sin<mode>2" 7504 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 7505 (unspec:FP 7506 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_SIN))] 7507 "TARGET_68881 && flag_unsafe_math_optimizations" 7508{ 7509 if (FP_REG_P (operands[1])) 7510 return "fsin%.x %1,%0"; 7511 else 7512 return "fsin%.<FP:prec> %1,%0"; 7513}) 7514 7515(define_insn "cos<mode>2" 7516 [(set (match_operand:FP 0 "nonimmediate_operand" "=f") 7517 (unspec:FP 7518 [(match_operand:FP 1 "general_operand" "f<FP:dreg>m")] UNSPEC_COS))] 7519 "TARGET_68881 && flag_unsafe_math_optimizations" 7520{ 7521 if (FP_REG_P (operands[1])) 7522 return "fcos%.x %1,%0"; 7523 else 7524 return "fcos%.<FP:prec> %1,%0"; 7525}) 7526 7527;; Unconditional traps are assumed to have (const_int 1) for the condition. 7528(define_insn "trap" 7529 [(trap_if (const_int 1) (const_int 7))] 7530 "" 7531 "trap #7" 7532 [(set_attr "type" "trap")]) 7533 7534(define_expand "ctrapdi4" 7535 [(trap_if (match_operator 0 "ordered_comparison_operator" 7536 [(cc0) (const_int 0)]) 7537 (match_operand:SI 3 "const1_operand" ""))] 7538 "TARGET_68020" 7539{ 7540 if (operands[2] == const0_rtx) 7541 emit_insn (gen_tstdi (operands[1])); 7542 else 7543 emit_insn (gen_cmpdi (operands[1], operands[2])); 7544 operands[1] = cc0_rtx; 7545 operands[2] = const0_rtx; 7546}) 7547 7548(define_expand "ctrapsi4" 7549 [(set (cc0) 7550 (compare (match_operand:SI 1 "nonimmediate_operand" "") 7551 (match_operand:SI 2 "general_operand" ""))) 7552 (trap_if (match_operator 0 "ordered_comparison_operator" 7553 [(cc0) (const_int 0)]) 7554 (match_operand:SI 3 "const1_operand" ""))] 7555 "TARGET_68020" 7556 "") 7557 7558(define_expand "ctraphi4" 7559 [(set (cc0) 7560 (compare (match_operand:HI 1 "nonimmediate_src_operand" "") 7561 (match_operand:HI 2 "general_src_operand" ""))) 7562 (trap_if (match_operator 0 "ordered_comparison_operator" 7563 [(cc0) (const_int 0)]) 7564 (match_operand:SI 3 "const1_operand" ""))] 7565 "TARGET_68020" 7566 "") 7567 7568(define_expand "ctrapqi4" 7569 [(set (cc0) 7570 (compare (match_operand:QI 1 "nonimmediate_src_operand" "") 7571 (match_operand:QI 2 "general_src_operand" ""))) 7572 (trap_if (match_operator 0 "ordered_comparison_operator" 7573 [(cc0) (const_int 0)]) 7574 (match_operand:SI 3 "const1_operand" ""))] 7575 "TARGET_68020" 7576 "") 7577 7578(define_insn "*conditional_trap" 7579 [(trap_if (match_operator 0 "ordered_comparison_operator" 7580 [(cc0) (const_int 0)]) 7581 (match_operand:SI 1 "const1_operand" "I"))] 7582 "TARGET_68020 && ! flags_in_68881 ()" 7583{ 7584 switch (GET_CODE (operands[0])) 7585 { 7586 case EQ: return "trapeq"; 7587 case NE: return "trapne"; 7588 case GT: return "trapgt"; 7589 case GTU: return "traphi"; 7590 case LT: return "traplt"; 7591 case LTU: return "trapcs"; 7592 case GE: return "trapge"; 7593 case GEU: return "trapcc"; 7594 case LE: return "traple"; 7595 case LEU: return "trapls"; 7596 default: gcc_unreachable (); 7597 } 7598}) 7599 7600;; These are to prevent the scheduler from moving stores to the frame 7601;; before the stack adjustment. 7602(define_insn "stack_tie" 7603 [(set (mem:BLK (scratch)) 7604 (unspec:BLK [(match_operand:SI 0 "register_operand" "r") 7605 (match_operand:SI 1 "register_operand" "r")] 7606 UNSPEC_TIE))] 7607 "" 7608 "" 7609 [(set_attr "type" "ignore")]) 7610 7611;; Instruction that subscribes one word in ColdFire instruction buffer. 7612;; This instruction is used within scheduler only and should not appear 7613;; in the instruction stream. 7614(define_insn "ib" 7615 [(unspec [(const_int 0)] UNSPEC_IB)] 7616 "" 7617 "#" 7618 [(set_attr "type" "ib")]) 7619 7620(include "cf.md") 7621(include "sync.md") 7622