1 /* Definitions of target machine for GCC for Motorola 680x0/ColdFire. 2 Copyright (C) 1987, 1988, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 3 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 4 Free Software Foundation, Inc. 5 6 This file is part of GCC. 7 8 GCC is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3, or (at your option) 11 any later version. 12 13 GCC is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with GCC; see the file COPYING3. If not see 20 <http://www.gnu.org/licenses/>. */ 21 22 /* We need to have MOTOROLA always defined (either 0 or 1) because we use 23 if-statements and ?: on it. This way we have compile-time error checking 24 for both the MOTOROLA and MIT code paths. We do rely on the host compiler 25 to optimize away all constant tests. */ 26 #if MOTOROLA /* Use the Motorola assembly syntax. */ 27 # define TARGET_VERSION fprintf (stderr, " (68k, Motorola syntax)") 28 #else 29 # define MOTOROLA 0 /* Use the MIT assembly syntax. */ 30 # define TARGET_VERSION fprintf (stderr, " (68k, MIT syntax)") 31 #endif 32 33 /* Handle --with-cpu default option from configure script. */ 34 #define OPTION_DEFAULT_SPECS \ 35 { "cpu", "%{!mc68000:%{!m68000:%{!m68302:%{!m68010:%{!mc68020:%{!m68020:\ 36 %{!m68030:%{!m68040:%{!m68020-40:%{!m68020-60:%{!m68060:%{!mcpu32:\ 37 %{!m68332:%{!m5200:%{!m5206e:%{!m528x:%{!m5307:%{!m5407:%{!mcfv4e:\ 38 %{!mcpu=*:%{!march=*:-%(VALUE)}}}}}}}}}}}}}}}}}}}}}" }, 39 40 /* Pass flags to gas indicating which type of processor we have. This 41 can be simplified when we can rely on the assembler supporting .cpu 42 and .arch directives. */ 43 44 #define ASM_CPU_SPEC "\ 45 %{m68851}%{mno-68851} %{m68881}%{mno-68881} %{msoft-float:-mno-float} \ 46 %{m68000}%{m68302}%{mc68000}%{m68010}%{m68020}%{mc68020}%{m68030}\ 47 %{m68040}%{m68020-40:-m68040}%{m68020-60:-m68040}\ 48 %{m68060}%{mcpu32}%{m68332}%{m5200}%{m5206e}%{m528x}%{m5307}%{m5407}%{mcfv4e}\ 49 %{mcpu=*:-mcpu=%*}%{march=*:-march=%*}\ 50 " 51 #define ASM_PCREL_SPEC "%{fPIC|fpic|mpcrel:--pcrel} \ 52 %{msep-data|mid-shared-library:--pcrel} \ 53 " 54 55 #define ASM_SPEC "%(asm_cpu_spec) %(asm_pcrel_spec)" 56 57 #define EXTRA_SPECS \ 58 { "asm_cpu_spec", ASM_CPU_SPEC }, \ 59 { "asm_pcrel_spec", ASM_PCREL_SPEC }, \ 60 SUBTARGET_EXTRA_SPECS 61 62 #define SUBTARGET_EXTRA_SPECS 63 64 /* Note that some other tm.h files include this one and then override 65 many of the definitions that relate to assembler syntax. */ 66 67 #define TARGET_CPU_CPP_BUILTINS() \ 68 do \ 69 { \ 70 builtin_define ("__m68k__"); \ 71 builtin_define_std ("mc68000"); \ 72 /* The other mc680x0 macros have traditionally been derived \ 73 from the tuning setting. For example, -m68020-60 defines \ 74 m68060, even though it generates pure 68020 code. */ \ 75 switch (m68k_tune) \ 76 { \ 77 case u68010: \ 78 builtin_define_std ("mc68010"); \ 79 break; \ 80 \ 81 case u68020: \ 82 builtin_define_std ("mc68020"); \ 83 break; \ 84 \ 85 case u68030: \ 86 builtin_define_std ("mc68030"); \ 87 break; \ 88 \ 89 case u68040: \ 90 builtin_define_std ("mc68040"); \ 91 break; \ 92 \ 93 case u68060: \ 94 builtin_define_std ("mc68060"); \ 95 break; \ 96 \ 97 case u68020_60: \ 98 builtin_define_std ("mc68060"); \ 99 /* Fall through. */ \ 100 case u68020_40: \ 101 builtin_define_std ("mc68040"); \ 102 builtin_define_std ("mc68030"); \ 103 builtin_define_std ("mc68020"); \ 104 break; \ 105 \ 106 case ucpu32: \ 107 builtin_define_std ("mc68332"); \ 108 builtin_define_std ("mcpu32"); \ 109 builtin_define_std ("mc68020"); \ 110 break; \ 111 \ 112 case ucfv1: \ 113 builtin_define ("__mcfv1__"); \ 114 break; \ 115 \ 116 case ucfv2: \ 117 builtin_define ("__mcfv2__"); \ 118 break; \ 119 \ 120 case ucfv3: \ 121 builtin_define ("__mcfv3__"); \ 122 break; \ 123 \ 124 case ucfv4: \ 125 builtin_define ("__mcfv4__"); \ 126 break; \ 127 \ 128 case ucfv4e: \ 129 builtin_define ("__mcfv4e__"); \ 130 break; \ 131 \ 132 case ucfv5: \ 133 builtin_define ("__mcfv5__"); \ 134 break; \ 135 \ 136 default: \ 137 break; \ 138 } \ 139 \ 140 if (TARGET_68881) \ 141 builtin_define ("__HAVE_68881__"); \ 142 \ 143 if (TARGET_COLDFIRE) \ 144 { \ 145 const char *tmp; \ 146 \ 147 tmp = m68k_cpp_cpu_ident ("cf"); \ 148 if (tmp) \ 149 builtin_define (tmp); \ 150 tmp = m68k_cpp_cpu_family ("cf"); \ 151 if (tmp) \ 152 builtin_define (tmp); \ 153 builtin_define ("__mcoldfire__"); \ 154 \ 155 if (TARGET_ISAC) \ 156 builtin_define ("__mcfisac__"); \ 157 else if (TARGET_ISAB) \ 158 { \ 159 builtin_define ("__mcfisab__"); \ 160 /* ISA_B: Legacy 5407 defines. */ \ 161 builtin_define ("__mcf5400__"); \ 162 builtin_define ("__mcf5407__"); \ 163 } \ 164 else if (TARGET_ISAAPLUS) \ 165 { \ 166 builtin_define ("__mcfisaaplus__"); \ 167 /* ISA_A+: legacy defines. */ \ 168 builtin_define ("__mcf528x__"); \ 169 builtin_define ("__mcf5200__"); \ 170 } \ 171 else \ 172 { \ 173 builtin_define ("__mcfisaa__"); \ 174 /* ISA_A: legacy defines. */ \ 175 switch (m68k_tune) \ 176 { \ 177 case ucfv2: \ 178 builtin_define ("__mcf5200__"); \ 179 break; \ 180 \ 181 case ucfv3: \ 182 builtin_define ("__mcf5307__"); \ 183 builtin_define ("__mcf5300__"); \ 184 break; \ 185 \ 186 default: \ 187 break; \ 188 } \ 189 } \ 190 } \ 191 \ 192 if (TARGET_COLDFIRE_FPU) \ 193 builtin_define ("__mcffpu__"); \ 194 \ 195 if (TARGET_CF_HWDIV) \ 196 builtin_define ("__mcfhwdiv__"); \ 197 \ 198 if (TARGET_FIDOA) \ 199 builtin_define ("__mfido__"); \ 200 \ 201 builtin_assert ("cpu=m68k"); \ 202 builtin_assert ("machine=m68k"); \ 203 } \ 204 while (0) 205 206 /* Classify the groups of pseudo-ops used to assemble QI, HI and SI 207 quantities. */ 208 #define INT_OP_STANDARD 0 /* .byte, .short, .long */ 209 #define INT_OP_DOT_WORD 1 /* .byte, .word, .long */ 210 #define INT_OP_NO_DOT 2 /* byte, short, long */ 211 #define INT_OP_DC 3 /* dc.b, dc.w, dc.l */ 212 213 /* Set the default. */ 214 #define INT_OP_GROUP INT_OP_DOT_WORD 215 216 /* Bit values used by m68k-devices.def to identify processor capabilities. */ 217 #define FL_BITFIELD (1 << 0) /* Support bitfield instructions. */ 218 #define FL_68881 (1 << 1) /* (Default) support for 68881/2. */ 219 #define FL_COLDFIRE (1 << 2) /* ColdFire processor. */ 220 #define FL_CF_HWDIV (1 << 3) /* ColdFire hardware divide supported. */ 221 #define FL_CF_MAC (1 << 4) /* ColdFire MAC unit supported. */ 222 #define FL_CF_EMAC (1 << 5) /* ColdFire eMAC unit supported. */ 223 #define FL_CF_EMAC_B (1 << 6) /* ColdFire eMAC-B unit supported. */ 224 #define FL_CF_USP (1 << 7) /* ColdFire User Stack Pointer supported. */ 225 #define FL_CF_FPU (1 << 8) /* ColdFire FPU supported. */ 226 #define FL_ISA_68000 (1 << 9) 227 #define FL_ISA_68010 (1 << 10) 228 #define FL_ISA_68020 (1 << 11) 229 #define FL_ISA_68040 (1 << 12) 230 #define FL_ISA_A (1 << 13) 231 #define FL_ISA_APLUS (1 << 14) 232 #define FL_ISA_B (1 << 15) 233 #define FL_ISA_C (1 << 16) 234 #define FL_FIDOA (1 << 17) 235 #define FL_MMU 0 /* Used by multilib machinery. */ 236 #define FL_UCLINUX 0 /* Used by multilib machinery. */ 237 238 #define TARGET_68010 ((m68k_cpu_flags & FL_ISA_68010) != 0) 239 #define TARGET_68020 ((m68k_cpu_flags & FL_ISA_68020) != 0) 240 #define TARGET_68040 ((m68k_cpu_flags & FL_ISA_68040) != 0) 241 #define TARGET_COLDFIRE ((m68k_cpu_flags & FL_COLDFIRE) != 0) 242 #define TARGET_COLDFIRE_FPU (m68k_fpu == FPUTYPE_COLDFIRE) 243 #define TARGET_68881 (m68k_fpu == FPUTYPE_68881) 244 #define TARGET_FIDOA ((m68k_cpu_flags & FL_FIDOA) != 0) 245 246 /* Size (in bytes) of FPU registers. */ 247 #define TARGET_FP_REG_SIZE (TARGET_COLDFIRE ? 8 : 12) 248 249 #define TARGET_ISAAPLUS ((m68k_cpu_flags & FL_ISA_APLUS) != 0) 250 #define TARGET_ISAB ((m68k_cpu_flags & FL_ISA_B) != 0) 251 #define TARGET_ISAC ((m68k_cpu_flags & FL_ISA_C) != 0) 252 253 /* Some instructions are common to more than one ISA. */ 254 #define ISA_HAS_MVS_MVZ (TARGET_ISAB || TARGET_ISAC) 255 #define ISA_HAS_FF1 (TARGET_ISAAPLUS || TARGET_ISAC) 256 257 #define TUNE_68000 (m68k_tune == u68000) 258 #define TUNE_68010 (m68k_tune == u68010) 259 #define TUNE_68000_10 (TUNE_68000 || TUNE_68010) 260 #define TUNE_68030 (m68k_tune == u68030 \ 261 || m68k_tune == u68020_40 \ 262 || m68k_tune == u68020_60) 263 #define TUNE_68040 (m68k_tune == u68040 \ 264 || m68k_tune == u68020_40 \ 265 || m68k_tune == u68020_60) 266 #define TUNE_68060 (m68k_tune == u68060 || m68k_tune == u68020_60) 267 #define TUNE_68040_60 (TUNE_68040 || TUNE_68060) 268 #define TUNE_CPU32 (m68k_tune == ucpu32) 269 #define TUNE_CFV1 (m68k_tune == ucfv1) 270 #define TUNE_CFV2 (m68k_tune == ucfv2) 271 #define TUNE_CFV3 (m68k_tune == ucfv3) 272 #define TUNE_CFV4 (m68k_tune == ucfv4 || m68k_tune == ucfv4e) 273 274 #define TUNE_MAC ((m68k_tune_flags & FL_CF_MAC) != 0) 275 #define TUNE_EMAC ((m68k_tune_flags & FL_CF_EMAC) != 0) 276 277 #define OVERRIDE_OPTIONS override_options() 278 279 /* These are meant to be redefined in the host dependent files */ 280 #define SUBTARGET_OVERRIDE_OPTIONS 281 282 /* target machine storage layout */ 283 284 /* "long double" is the same as "double" on ColdFire and fido 285 targets. */ 286 287 #define LONG_DOUBLE_TYPE_SIZE \ 288 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 64 : 80) 289 290 /* We need to know the size of long double at compile-time in libgcc2. */ 291 292 #if defined(__mcoldfire__) || defined(__mfido__) 293 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 64 294 #else 295 #define LIBGCC2_LONG_DOUBLE_TYPE_SIZE 80 296 #endif 297 298 /* Set the value of FLT_EVAL_METHOD in float.h. When using 68040 fp 299 instructions, we get proper intermediate rounding, otherwise we 300 get extended precision results. */ 301 #define TARGET_FLT_EVAL_METHOD ((TARGET_68040 || ! TARGET_68881) ? 0 : 2) 302 303 #define BITS_BIG_ENDIAN 1 304 #define BYTES_BIG_ENDIAN 1 305 #define WORDS_BIG_ENDIAN 1 306 307 #define UNITS_PER_WORD 4 308 309 #define PARM_BOUNDARY (TARGET_SHORT ? 16 : 32) 310 #define STACK_BOUNDARY 16 311 #define FUNCTION_BOUNDARY 16 312 #define EMPTY_FIELD_BOUNDARY 16 313 /* ColdFire and fido strongly prefer a 32-bit aligned stack. */ 314 #define PREFERRED_STACK_BOUNDARY \ 315 ((TARGET_COLDFIRE || TARGET_FIDOA) ? 32 : 16) 316 317 /* No data type wants to be aligned rounder than this. 318 Most published ABIs say that ints should be aligned on 16-bit 319 boundaries, but CPUs with 32-bit busses get better performance 320 aligned on 32-bit boundaries. */ 321 #define BIGGEST_ALIGNMENT (TARGET_ALIGN_INT ? 32 : 16) 322 323 #define STRICT_ALIGNMENT (TARGET_STRICT_ALIGNMENT) 324 #define M68K_HONOR_TARGET_STRICT_ALIGNMENT 1 325 326 #define DWARF_CIE_DATA_ALIGNMENT -2 327 328 #define INT_TYPE_SIZE (TARGET_SHORT ? 16 : 32) 329 330 /* Define these to avoid dependence on meaning of `int'. */ 331 #define WCHAR_TYPE "long int" 332 #define WCHAR_TYPE_SIZE 32 333 334 /* Maximum number of library IDs we permit with -mid-shared-library. */ 335 #define MAX_LIBRARY_ID 255 336 337 338 /* Standard register usage. */ 339 340 /* For the m68k, we give the data registers numbers 0-7, 341 the address registers numbers 010-017 (8-15), 342 and the 68881 floating point registers numbers 020-027 (16-23). 343 We also have a fake `arg-pointer' register 030 (24) used for 344 register elimination. */ 345 #define FIRST_PSEUDO_REGISTER 25 346 347 /* All m68k targets (except AmigaOS) use %a5 as the PIC register */ 348 #define PIC_OFFSET_TABLE_REGNUM \ 349 (!flag_pic ? INVALID_REGNUM \ 350 : reload_completed ? REGNO (pic_offset_table_rtx) \ 351 : PIC_REG) 352 353 /* 1 for registers that have pervasive standard uses 354 and are not available for the register allocator. 355 On the m68k, only the stack pointer is such. 356 Our fake arg-pointer is obviously fixed as well. */ 357 #define FIXED_REGISTERS \ 358 {/* Data registers. */ \ 359 0, 0, 0, 0, 0, 0, 0, 0, \ 360 \ 361 /* Address registers. */ \ 362 0, 0, 0, 0, 0, 0, 0, 1, \ 363 \ 364 /* Floating point registers \ 365 (if available). */ \ 366 0, 0, 0, 0, 0, 0, 0, 0, \ 367 \ 368 /* Arg pointer. */ \ 369 1 } 370 371 /* 1 for registers not available across function calls. 372 These must include the FIXED_REGISTERS and also any 373 registers that can be used without being saved. 374 The latter must include the registers where values are returned 375 and the register where structure-value addresses are passed. 376 Aside from that, you can include as many other registers as you like. */ 377 #define CALL_USED_REGISTERS \ 378 {/* Data registers. */ \ 379 1, 1, 0, 0, 0, 0, 0, 0, \ 380 \ 381 /* Address registers. */ \ 382 1, 1, 0, 0, 0, 0, 0, 1, \ 383 \ 384 /* Floating point registers \ 385 (if available). */ \ 386 1, 1, 0, 0, 0, 0, 0, 0, \ 387 \ 388 /* Arg pointer. */ \ 389 1 } 390 391 #define REG_ALLOC_ORDER \ 392 { /* d0/d1/a0/a1 */ \ 393 0, 1, 8, 9, \ 394 /* d2-d7 */ \ 395 2, 3, 4, 5, 6, 7, \ 396 /* a2-a7/arg */ \ 397 10, 11, 12, 13, 14, 15, 24, \ 398 /* fp0-fp7 */ \ 399 16, 17, 18, 19, 20, 21, 22, 23\ 400 } 401 402 403 /* Make sure everything's fine if we *don't* have a given processor. 404 This assumes that putting a register in fixed_regs will keep the 405 compiler's mitts completely off it. We don't bother to zero it out 406 of register classes. */ 407 #define CONDITIONAL_REGISTER_USAGE \ 408 { \ 409 int i; \ 410 HARD_REG_SET x; \ 411 if (!TARGET_HARD_FLOAT) \ 412 { \ 413 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); \ 414 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) \ 415 if (TEST_HARD_REG_BIT (x, i)) \ 416 fixed_regs[i] = call_used_regs[i] = 1; \ 417 } \ 418 if (flag_pic) \ 419 fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; \ 420 } 421 422 /* On the m68k, ordinary registers hold 32 bits worth; 423 for the 68881 registers, a single register is always enough for 424 anything that can be stored in them at all. */ 425 #define HARD_REGNO_NREGS(REGNO, MODE) \ 426 ((REGNO) >= 16 ? GET_MODE_NUNITS (MODE) \ 427 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 428 429 /* A C expression that is nonzero if hard register NEW_REG can be 430 considered for use as a rename register for OLD_REG register. */ 431 432 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 433 m68k_hard_regno_rename_ok (OLD_REG, NEW_REG) 434 435 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 436 m68k_regno_mode_ok ((REGNO), (MODE)) 437 438 #define SECONDARY_RELOAD_CLASS(CLASS, MODE, X) \ 439 m68k_secondary_reload_class (CLASS, MODE, X) 440 441 #define MODES_TIEABLE_P(MODE1, MODE2) \ 442 (! TARGET_HARD_FLOAT \ 443 || ((GET_MODE_CLASS (MODE1) == MODE_FLOAT \ 444 || GET_MODE_CLASS (MODE1) == MODE_COMPLEX_FLOAT) \ 445 == (GET_MODE_CLASS (MODE2) == MODE_FLOAT \ 446 || GET_MODE_CLASS (MODE2) == MODE_COMPLEX_FLOAT))) 447 448 /* Specify the registers used for certain standard purposes. 449 The values of these macros are register numbers. */ 450 451 #define STACK_POINTER_REGNUM SP_REG 452 453 /* Most m68k targets use %a6 as a frame pointer. The AmigaOS 454 ABI uses %a6 for shared library calls, therefore the frame 455 pointer is shifted to %a5 on this target. */ 456 #define FRAME_POINTER_REGNUM A6_REG 457 458 /* Base register for access to arguments of the function. 459 * This isn't a hardware register. It will be eliminated to the 460 * stack pointer or frame pointer. 461 */ 462 #define ARG_POINTER_REGNUM 24 463 464 #define STATIC_CHAIN_REGNUM A0_REG 465 #define M68K_STATIC_CHAIN_REG_NAME REGISTER_PREFIX "a0" 466 467 /* Register in which address to store a structure value 468 is passed to a function. */ 469 #define M68K_STRUCT_VALUE_REGNUM A1_REG 470 471 472 473 /* The m68k has three kinds of registers, so eight classes would be 474 a complete set. One of them is not needed. */ 475 enum reg_class { 476 NO_REGS, DATA_REGS, 477 ADDR_REGS, FP_REGS, 478 GENERAL_REGS, DATA_OR_FP_REGS, 479 ADDR_OR_FP_REGS, ALL_REGS, 480 LIM_REG_CLASSES }; 481 482 #define N_REG_CLASSES (int) LIM_REG_CLASSES 483 484 #define REG_CLASS_NAMES \ 485 { "NO_REGS", "DATA_REGS", \ 486 "ADDR_REGS", "FP_REGS", \ 487 "GENERAL_REGS", "DATA_OR_FP_REGS", \ 488 "ADDR_OR_FP_REGS", "ALL_REGS" } 489 490 #define REG_CLASS_CONTENTS \ 491 { \ 492 {0x00000000}, /* NO_REGS */ \ 493 {0x000000ff}, /* DATA_REGS */ \ 494 {0x0100ff00}, /* ADDR_REGS */ \ 495 {0x00ff0000}, /* FP_REGS */ \ 496 {0x0100ffff}, /* GENERAL_REGS */ \ 497 {0x00ff00ff}, /* DATA_OR_FP_REGS */ \ 498 {0x01ffff00}, /* ADDR_OR_FP_REGS */ \ 499 {0x01ffffff}, /* ALL_REGS */ \ 500 } 501 502 extern enum reg_class regno_reg_class[]; 503 #define REGNO_REG_CLASS(REGNO) (regno_reg_class[(REGNO)]) 504 #define INDEX_REG_CLASS GENERAL_REGS 505 #define BASE_REG_CLASS ADDR_REGS 506 507 #define PREFERRED_RELOAD_CLASS(X,CLASS) \ 508 m68k_preferred_reload_class (X, CLASS) 509 510 /* On the m68k, this is the size of MODE in words, 511 except in the FP regs, where a single reg is always enough. */ 512 #define CLASS_MAX_NREGS(CLASS, MODE) \ 513 ((CLASS) == FP_REGS ? 1 \ 514 : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)) 515 516 /* Moves between fp regs and other regs are two insns. */ 517 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) \ 518 ((((CLASS1) == FP_REGS) != ((CLASS2) == FP_REGS)) ? 4 : 2) 519 520 #define IRA_COVER_CLASSES \ 521 { \ 522 ALL_REGS, LIM_REG_CLASSES \ 523 } 524 525 /* Stack layout; function entry, exit and calling. */ 526 527 #define STACK_GROWS_DOWNWARD 1 528 #define FRAME_GROWS_DOWNWARD 1 529 #define STARTING_FRAME_OFFSET 0 530 531 /* On the 680x0, sp@- in a byte insn really pushes a word. 532 On the ColdFire, sp@- in a byte insn pushes just a byte. */ 533 #define PUSH_ROUNDING(BYTES) (TARGET_COLDFIRE ? BYTES : ((BYTES) + 1) & ~1) 534 535 #define FIRST_PARM_OFFSET(FNDECL) 8 536 537 /* On the 68000, the RTS insn cannot pop anything. 538 On the 68010, the RTD insn may be used to pop them if the number 539 of args is fixed, but if the number is variable then the caller 540 must pop them all. RTD can't be used for library calls now 541 because the library is compiled with the Unix compiler. 542 Use of RTD is a selectable option, since it is incompatible with 543 standard Unix calling sequences. If the option is not selected, 544 the caller must always pop the args. */ 545 #define RETURN_POPS_ARGS(FUNDECL,FUNTYPE,SIZE) \ 546 ((TARGET_RTD && (!(FUNDECL) || TREE_CODE (FUNDECL) != IDENTIFIER_NODE) \ 547 && (TYPE_ARG_TYPES (FUNTYPE) == 0 \ 548 || (TREE_VALUE (tree_last (TYPE_ARG_TYPES (FUNTYPE))) \ 549 == void_type_node))) \ 550 ? (SIZE) : 0) 551 552 /* On the m68k the return value defaults to D0. */ 553 #define FUNCTION_VALUE(VALTYPE, FUNC) \ 554 gen_rtx_REG (TYPE_MODE (VALTYPE), D0_REG) 555 556 /* On the m68k the return value defaults to D0. */ 557 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, D0_REG) 558 559 /* On the m68k, D0 is usually the only register used. */ 560 #define FUNCTION_VALUE_REGNO_P(N) ((N) == D0_REG) 561 562 /* Define this to be true when FUNCTION_VALUE_REGNO_P is true for 563 more than one register. 564 XXX This macro is m68k specific and used only for m68kemb.h. */ 565 #define NEEDS_UNTYPED_CALL 0 566 567 /* On the m68k, all arguments are usually pushed on the stack. */ 568 #define FUNCTION_ARG_REGNO_P(N) 0 569 570 /* On the m68k, this is a single integer, which is a number of bytes 571 of arguments scanned so far. */ 572 #define CUMULATIVE_ARGS int 573 574 /* On the m68k, the offset starts at 0. */ 575 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 576 ((CUM) = 0) 577 578 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 579 ((CUM) += ((MODE) != BLKmode \ 580 ? (GET_MODE_SIZE (MODE) + 3) & ~3 \ 581 : (int_size_in_bytes (TYPE) + 3) & ~3)) 582 583 /* On the m68k all args are always pushed. */ 584 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) 0 585 586 #define FUNCTION_PROFILER(FILE, LABELNO) \ 587 asm_fprintf (FILE, "\tlea %LLP%d,%Ra0\n\tjsr mcount\n", (LABELNO)) 588 589 #define EXIT_IGNORE_STACK 1 590 591 /* Output assembler code for a block containing the constant parts 592 of a trampoline, leaving space for the variable parts. 593 594 On the m68k, the trampoline looks like this: 595 movl #STATIC,a0 596 jmp FUNCTION 597 598 WARNING: Targets that may run on 68040+ cpus must arrange for 599 the instruction cache to be flushed. Previous incarnations of 600 the m68k trampoline code attempted to get around this by either 601 using an out-of-line transfer function or pc-relative data, but 602 the fact remains that the code to jump to the transfer function 603 or the code to load the pc-relative data needs to be flushed 604 just as much as the "variable" portion of the trampoline. 605 Recognizing that a cache flush is going to be required anyway, 606 dispense with such notions and build a smaller trampoline. 607 608 Since more instructions are required to move a template into 609 place than to create it on the spot, don't use a template. */ 610 611 #define TRAMPOLINE_SIZE 12 612 #define TRAMPOLINE_ALIGNMENT 16 613 614 /* Targets redefine this to invoke code to either flush the cache, 615 or enable stack execution (or both). */ 616 #ifndef FINALIZE_TRAMPOLINE 617 #define FINALIZE_TRAMPOLINE(TRAMP) 618 #endif 619 620 /* This is the library routine that is used to transfer control from the 621 trampoline to the actual nested function. It is defined for backward 622 compatibility, for linking with object code that used the old trampoline 623 definition. 624 625 A colon is used with no explicit operands to cause the template string 626 to be scanned for %-constructs. 627 628 The function name __transfer_from_trampoline is not actually used. 629 The function definition just permits use of "asm with operands" 630 (though the operand list is empty). */ 631 #define TRANSFER_FROM_TRAMPOLINE \ 632 void \ 633 __transfer_from_trampoline () \ 634 { \ 635 register char *a0 asm (M68K_STATIC_CHAIN_REG_NAME); \ 636 asm (GLOBAL_ASM_OP "___trampoline"); \ 637 asm ("___trampoline:"); \ 638 asm volatile ("move%.l %0,%@" : : "m" (a0[22])); \ 639 asm volatile ("move%.l %1,%0" : "=a" (a0) : "m" (a0[18])); \ 640 asm ("rts":); \ 641 } 642 643 /* There are two registers that can always be eliminated on the m68k. 644 The frame pointer and the arg pointer can be replaced by either the 645 hard frame pointer or to the stack pointer, depending upon the 646 circumstances. The hard frame pointer is not used before reload and 647 so it is not eligible for elimination. */ 648 #define ELIMINABLE_REGS \ 649 {{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 650 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }, \ 651 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }} 652 653 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 654 (OFFSET) = m68k_initial_elimination_offset(FROM, TO) 655 656 /* Addressing modes, and classification of registers for them. */ 657 658 #define HAVE_POST_INCREMENT 1 659 #define HAVE_PRE_DECREMENT 1 660 661 /* Macros to check register numbers against specific register classes. */ 662 663 /* True for data registers, D0 through D7. */ 664 #define DATA_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 7) 665 666 /* True for address registers, A0 through A7. */ 667 #define ADDRESS_REGNO_P(REGNO) IN_RANGE (REGNO, 8, 15) 668 669 /* True for integer registers, D0 through D7 and A0 through A7. */ 670 #define INT_REGNO_P(REGNO) IN_RANGE (REGNO, 0, 15) 671 672 /* True for floating point registers, FP0 through FP7. */ 673 #define FP_REGNO_P(REGNO) IN_RANGE (REGNO, 16, 23) 674 675 #define REGNO_OK_FOR_INDEX_P(REGNO) \ 676 (INT_REGNO_P (REGNO) \ 677 || INT_REGNO_P (reg_renumber[REGNO])) 678 679 #define REGNO_OK_FOR_BASE_P(REGNO) \ 680 (ADDRESS_REGNO_P (REGNO) \ 681 || ADDRESS_REGNO_P (reg_renumber[REGNO])) 682 683 #define REGNO_OK_FOR_INDEX_NONSTRICT_P(REGNO) \ 684 (INT_REGNO_P (REGNO) \ 685 || REGNO == ARG_POINTER_REGNUM \ 686 || REGNO >= FIRST_PSEUDO_REGISTER) 687 688 #define REGNO_OK_FOR_BASE_NONSTRICT_P(REGNO) \ 689 (ADDRESS_REGNO_P (REGNO) \ 690 || REGNO == ARG_POINTER_REGNUM \ 691 || REGNO >= FIRST_PSEUDO_REGISTER) 692 693 /* Now macros that check whether X is a register and also, 694 strictly, whether it is in a specified class. 695 696 These macros are specific to the m68k, and may be used only 697 in code for printing assembler insns and in conditions for 698 define_optimization. */ 699 700 /* 1 if X is a data register. */ 701 #define DATA_REG_P(X) (REG_P (X) && DATA_REGNO_P (REGNO (X))) 702 703 /* 1 if X is an fp register. */ 704 #define FP_REG_P(X) (REG_P (X) && FP_REGNO_P (REGNO (X))) 705 706 /* 1 if X is an address register */ 707 #define ADDRESS_REG_P(X) (REG_P (X) && ADDRESS_REGNO_P (REGNO (X))) 708 709 /* True if SYMBOL + OFFSET constants must refer to something within 710 SYMBOL's section. */ 711 #ifndef M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 712 #define M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 713 #endif 714 715 #define MAX_REGS_PER_ADDRESS 2 716 717 #define CONSTANT_ADDRESS_P(X) \ 718 ((GET_CODE (X) == LABEL_REF || GET_CODE (X) == SYMBOL_REF \ 719 || GET_CODE (X) == CONST_INT || GET_CODE (X) == CONST \ 720 || GET_CODE (X) == HIGH) \ 721 && LEGITIMATE_CONSTANT_P (X)) 722 723 /* Nonzero if the constant value X is a legitimate general operand. 724 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. */ 725 #define LEGITIMATE_CONSTANT_P(X) \ 726 (GET_MODE (X) != XFmode \ 727 && !m68k_illegitimate_symbolic_constant_p (X)) 728 729 #ifndef REG_OK_STRICT 730 #define REG_STRICT_P 0 731 #else 732 #define REG_STRICT_P 1 733 #endif 734 735 #define LEGITIMATE_PIC_OPERAND_P(X) \ 736 (!symbolic_operand (X, VOIDmode) \ 737 || (TARGET_PCREL && REG_STRICT_P) \ 738 || m68k_tls_reference_p (X, true)) 739 740 #define REG_OK_FOR_BASE_P(X) \ 741 m68k_legitimate_base_reg_p (X, REG_STRICT_P) 742 743 #define REG_OK_FOR_INDEX_P(X) \ 744 m68k_legitimate_index_reg_p (X, REG_STRICT_P) 745 746 747 /* This address is OK as it stands. */ 748 #define PIC_CASE_VECTOR_ADDRESS(index) index 749 #define CASE_VECTOR_MODE HImode 750 #define CASE_VECTOR_PC_RELATIVE 1 751 752 #define DEFAULT_SIGNED_CHAR 1 753 #define MOVE_MAX 4 754 #define SLOW_BYTE_ACCESS 0 755 756 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 757 758 /* The ColdFire FF1 instruction returns 32 for zero. */ 759 #define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 760 761 #define STORE_FLAG_VALUE (-1) 762 763 #define Pmode SImode 764 #define FUNCTION_MODE QImode 765 766 767 /* Tell final.c how to eliminate redundant test instructions. */ 768 769 /* Here we define machine-dependent flags and fields in cc_status 770 (see `conditions.h'). */ 771 772 /* Set if the cc value is actually in the 68881, so a floating point 773 conditional branch must be output. */ 774 #define CC_IN_68881 04000 775 776 /* On the 68000, all the insns to store in an address register fail to 777 set the cc's. However, in some cases these instructions can make it 778 possibly invalid to use the saved cc's. In those cases we clear out 779 some or all of the saved cc's so they won't be used. */ 780 #define NOTICE_UPDATE_CC(EXP,INSN) notice_update_cc (EXP, INSN) 781 782 /* The shift instructions always clear the overflow bit. */ 783 #define CC_OVERFLOW_UNUSABLE 01000 784 785 /* The shift instructions use the carry bit in a way not compatible with 786 conditional branches. conditions.h uses CC_NO_OVERFLOW for this purpose. 787 Rename it to something more understandable. */ 788 #define CC_NO_CARRY CC_NO_OVERFLOW 789 790 #define OUTPUT_JUMP(NORMAL, FLOAT, NO_OV) \ 791 do { if (cc_prev_status.flags & CC_IN_68881) \ 792 return FLOAT; \ 793 if (cc_prev_status.flags & CC_NO_OVERFLOW) \ 794 return NO_OV; \ 795 return NORMAL; } while (0) 796 797 /* Control the assembler format that we output. */ 798 799 #define ASM_APP_ON "#APP\n" 800 #define ASM_APP_OFF "#NO_APP\n" 801 #define TEXT_SECTION_ASM_OP "\t.text" 802 #define DATA_SECTION_ASM_OP "\t.data" 803 #define GLOBAL_ASM_OP "\t.globl\t" 804 #define REGISTER_PREFIX "" 805 #define LOCAL_LABEL_PREFIX "" 806 #define USER_LABEL_PREFIX "_" 807 #define IMMEDIATE_PREFIX "#" 808 809 #define REGISTER_NAMES \ 810 {REGISTER_PREFIX"d0", REGISTER_PREFIX"d1", REGISTER_PREFIX"d2", \ 811 REGISTER_PREFIX"d3", REGISTER_PREFIX"d4", REGISTER_PREFIX"d5", \ 812 REGISTER_PREFIX"d6", REGISTER_PREFIX"d7", \ 813 REGISTER_PREFIX"a0", REGISTER_PREFIX"a1", REGISTER_PREFIX"a2", \ 814 REGISTER_PREFIX"a3", REGISTER_PREFIX"a4", REGISTER_PREFIX"a5", \ 815 REGISTER_PREFIX"a6", REGISTER_PREFIX"sp", \ 816 REGISTER_PREFIX"fp0", REGISTER_PREFIX"fp1", REGISTER_PREFIX"fp2", \ 817 REGISTER_PREFIX"fp3", REGISTER_PREFIX"fp4", REGISTER_PREFIX"fp5", \ 818 REGISTER_PREFIX"fp6", REGISTER_PREFIX"fp7", REGISTER_PREFIX"argptr" } 819 820 #define M68K_FP_REG_NAME REGISTER_PREFIX"fp" 821 822 /* Return a register name by index, handling %fp nicely. 823 We don't replace %fp for targets that don't map it to %a6 824 since it may confuse GAS. */ 825 #define M68K_REGNAME(r) ( \ 826 ((FRAME_POINTER_REGNUM == A6_REG) \ 827 && ((r) == FRAME_POINTER_REGNUM) \ 828 && frame_pointer_needed) ? \ 829 M68K_FP_REG_NAME : reg_names[(r)]) 830 831 /* On the Sun-3, the floating point registers have numbers 832 18 to 25, not 16 to 23 as they do in the compiler. */ 833 #define DBX_REGISTER_NUMBER(REGNO) ((REGNO) < 16 ? (REGNO) : (REGNO) + 2) 834 835 /* Before the prologue, RA is at 0(%sp). */ 836 #define INCOMING_RETURN_ADDR_RTX \ 837 gen_rtx_MEM (VOIDmode, gen_rtx_REG (VOIDmode, STACK_POINTER_REGNUM)) 838 839 /* After the prologue, RA is at 4(AP) in the current frame. */ 840 #define RETURN_ADDR_RTX(COUNT, FRAME) \ 841 ((COUNT) == 0 \ 842 ? gen_rtx_MEM (Pmode, plus_constant (arg_pointer_rtx, UNITS_PER_WORD)) \ 843 : gen_rtx_MEM (Pmode, plus_constant (FRAME, UNITS_PER_WORD))) 844 845 /* We must not use the DBX register numbers for the DWARF 2 CFA column 846 numbers because that maps to numbers beyond FIRST_PSEUDO_REGISTER. 847 Instead use the identity mapping. */ 848 #define DWARF_FRAME_REGNUM(REG) \ 849 (INT_REGNO_P (REG) || FP_REGNO_P (REG) ? (REG) : INVALID_REGNUM) 850 851 /* The return column was originally 24, but gcc used 25 for a while too. 852 Define both registers 24 and 25 as Pmode ones and use 24 in our own 853 unwind information. */ 854 #define DWARF_FRAME_REGISTERS 25 855 #define DWARF_FRAME_RETURN_COLUMN 24 856 #define DWARF_ALT_FRAME_RETURN_COLUMN 25 857 858 /* Before the prologue, the top of the frame is at 4(%sp). */ 859 #define INCOMING_FRAME_SP_OFFSET 4 860 861 /* All registers are live on exit from an interrupt routine. */ 862 #define EPILOGUE_USES(REGNO) \ 863 (reload_completed \ 864 && (m68k_get_function_kind (current_function_decl) \ 865 == m68k_fk_interrupt_handler)) 866 867 /* Describe how we implement __builtin_eh_return. */ 868 #define EH_RETURN_DATA_REGNO(N) \ 869 ((N) < 2 ? (N) : INVALID_REGNUM) 870 #define EH_RETURN_STACKADJ_RTX gen_rtx_REG (Pmode, A0_REG) 871 #define EH_RETURN_HANDLER_RTX \ 872 gen_rtx_MEM (Pmode, \ 873 gen_rtx_PLUS (Pmode, arg_pointer_rtx, \ 874 plus_constant (EH_RETURN_STACKADJ_RTX, \ 875 UNITS_PER_WORD))) 876 877 /* Select a format to encode pointers in exception handling data. CODE 878 is 0 for data, 1 for code labels, 2 for function pointers. GLOBAL is 879 true if the symbol may be affected by dynamic relocations. 880 881 TARGET_ID_SHARED_LIBRARY and TARGET_SEP_DATA are designed to support 882 a read-only text segment without imposing a fixed gap between the 883 text and data segments. As a result, the text segment cannot refer 884 to anything in the data segment, even in PC-relative form. Because 885 .eh_frame refers to both code and data, it follows that .eh_frame 886 must be in the data segment itself, and that the offset between 887 .eh_frame and code will not be a link-time constant. 888 889 In theory, we could create a read-only .eh_frame by using DW_EH_PE_pcrel 890 | DW_EH_PE_indirect for all code references. However, gcc currently 891 handles indirect references using a per-TU constant pool. This means 892 that if a function and its eh_frame are removed by the linker, the 893 eh_frame's indirect references to the removed function will not be 894 removed, leading to an unresolved symbol error. 895 896 It isn't clear that any -msep-data or -mid-shared-library target 897 would benefit from a read-only .eh_frame anyway. In particular, 898 no known target that supports these options has a feature like 899 PT_GNU_RELRO. Without any such feature to motivate them, indirect 900 references would be unnecessary bloat, so we simply use an absolute 901 pointer for code and global references. We still use pc-relative 902 references to data, as this avoids a relocation. */ 903 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE, GLOBAL) \ 904 (flag_pic \ 905 && !((TARGET_ID_SHARED_LIBRARY || TARGET_SEP_DATA) \ 906 && ((GLOBAL) || (CODE))) \ 907 ? ((GLOBAL) ? DW_EH_PE_indirect : 0) | DW_EH_PE_pcrel | DW_EH_PE_sdata4 \ 908 : DW_EH_PE_absptr) 909 910 #define ASM_OUTPUT_LABELREF(FILE,NAME) \ 911 asm_fprintf (FILE, "%U%s", NAME) 912 913 #define ASM_GENERATE_INTERNAL_LABEL(LABEL,PREFIX,NUM) \ 914 sprintf (LABEL, "*%s%s%ld", LOCAL_LABEL_PREFIX, PREFIX, (long)(NUM)) 915 916 #define ASM_OUTPUT_REG_PUSH(FILE,REGNO) \ 917 asm_fprintf (FILE, (MOTOROLA \ 918 ? "\tmove.l %s,-(%Rsp)\n" \ 919 : "\tmovel %s,%Rsp@-\n"), \ 920 reg_names[REGNO]) 921 922 #define ASM_OUTPUT_REG_POP(FILE,REGNO) \ 923 asm_fprintf (FILE, (MOTOROLA \ 924 ? "\tmove.l (%Rsp)+,%s\n" \ 925 : "\tmovel %Rsp@+,%s\n"), \ 926 reg_names[REGNO]) 927 928 /* The m68k does not use absolute case-vectors, but we must define this macro 929 anyway. */ 930 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 931 asm_fprintf (FILE, "\t.long %LL%d\n", VALUE) 932 933 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL) \ 934 asm_fprintf (FILE, "\t.word %LL%d-%LL%d\n", VALUE, REL) 935 936 /* We don't have a way to align to more than a two-byte boundary, so do the 937 best we can and don't complain. */ 938 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 939 if ((LOG) >= 1) \ 940 fprintf (FILE, "\t.even\n"); 941 942 #ifdef HAVE_GAS_BALIGN_AND_P2ALIGN 943 /* Use "move.l %a4,%a4" to advance within code. */ 944 #define ASM_OUTPUT_ALIGN_WITH_NOP(FILE,LOG) \ 945 if ((LOG) > 0) \ 946 fprintf ((FILE), "\t.balignw %u,0x284c\n", 1 << (LOG)); 947 #endif 948 949 #define ASM_OUTPUT_SKIP(FILE,SIZE) \ 950 fprintf (FILE, "\t.skip %u\n", (int)(SIZE)) 951 952 #define ASM_OUTPUT_COMMON(FILE, NAME, SIZE, ROUNDED) \ 953 ( fputs (".comm ", (FILE)), \ 954 assemble_name ((FILE), (NAME)), \ 955 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 956 957 #define ASM_OUTPUT_LOCAL(FILE, NAME, SIZE, ROUNDED) \ 958 ( fputs (".lcomm ", (FILE)), \ 959 assemble_name ((FILE), (NAME)), \ 960 fprintf ((FILE), ",%u\n", (int)(ROUNDED))) 961 962 #define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 963 m68k_final_prescan_insn (INSN, OPVEC, NOPERANDS) 964 965 /* On the 68000, we use several CODE characters: 966 '.' for dot needed in Motorola-style opcode names. 967 '-' for an operand pushing on the stack: 968 sp@-, -(sp) or -(%sp) depending on the style of syntax. 969 '+' for an operand pushing on the stack: 970 sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 971 '@' for a reference to the top word on the stack: 972 sp@, (sp) or (%sp) depending on the style of syntax. 973 '#' for an immediate operand prefix (# in MIT and Motorola syntax 974 but & in SGS syntax). 975 '!' for the fpcr register (used in some float-to-fixed conversions). 976 '$' for the letter `s' in an op code, but only on the 68040. 977 '&' for the letter `d' in an op code, but only on the 68040. 978 '/' for register prefix needed by longlong.h. 979 '?' for m68k_library_id_string 980 981 'b' for byte insn (no effect, on the Sun; this is for the ISI). 982 'd' to force memory addressing to be absolute, not relative. 983 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 984 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 985 or print pair of registers as rx:ry. */ 986 987 #define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 988 ((CODE) == '.' || (CODE) == '#' || (CODE) == '-' \ 989 || (CODE) == '+' || (CODE) == '@' || (CODE) == '!' \ 990 || (CODE) == '$' || (CODE) == '&' || (CODE) == '/' || (CODE) == '?') 991 992 993 /* See m68k.c for the m68k specific codes. */ 994 #define PRINT_OPERAND(FILE, X, CODE) print_operand (FILE, X, CODE) 995 996 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) print_operand_address (FILE, ADDR) 997 998 #define OUTPUT_ADDR_CONST_EXTRA(FILE, X, FAIL) \ 999 do { \ 1000 if (! m68k_output_addr_const_extra (FILE, (X))) \ 1001 goto FAIL; \ 1002 } while (0); 1003 1004 /* Values used in the MICROARCH argument to M68K_DEVICE. */ 1005 enum uarch_type 1006 { 1007 u68000, 1008 u68010, 1009 u68020, 1010 u68020_40, 1011 u68020_60, 1012 u68030, 1013 u68040, 1014 u68060, 1015 ucpu32, 1016 ucfv1, 1017 ucfv2, 1018 ucfv3, 1019 ucfv4, 1020 ucfv4e, 1021 ucfv5, 1022 unk_arch 1023 }; 1024 1025 /* An enumeration of all supported target devices. */ 1026 enum target_device 1027 { 1028 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ 1029 ENUM_VALUE, 1030 #include "m68k-devices.def" 1031 #undef M68K_DEVICE 1032 unk_device 1033 }; 1034 1035 enum fpu_type 1036 { 1037 FPUTYPE_NONE, 1038 FPUTYPE_68881, 1039 FPUTYPE_COLDFIRE 1040 }; 1041 1042 enum m68k_function_kind 1043 { 1044 m68k_fk_normal_function, 1045 m68k_fk_interrupt_handler, 1046 m68k_fk_interrupt_thread 1047 }; 1048 1049 /* Variables in m68k.c; see there for details. */ 1050 extern const char *m68k_library_id_string; 1051 extern enum target_device m68k_cpu; 1052 extern enum uarch_type m68k_tune; 1053 extern enum fpu_type m68k_fpu; 1054 extern unsigned int m68k_cpu_flags; 1055 extern unsigned int m68k_tune_flags; 1056 extern const char *m68k_symbolic_call; 1057 extern const char *m68k_symbolic_jump; 1058 1059 enum M68K_SYMBOLIC_CALL { M68K_SYMBOLIC_CALL_NONE, M68K_SYMBOLIC_CALL_JSR, 1060 M68K_SYMBOLIC_CALL_BSR_C, M68K_SYMBOLIC_CALL_BSR_P }; 1061 1062 extern enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var; 1063 1064 /* ??? HOST_WIDE_INT is not being defined for auto-generated files. 1065 Workaround that. */ 1066 #ifdef HOST_WIDE_INT 1067 typedef enum { MOVL, SWAP, NEGW, NOTW, NOTB, MOVQ, MVS, MVZ } 1068 M68K_CONST_METHOD; 1069 1070 extern M68K_CONST_METHOD m68k_const_method (HOST_WIDE_INT); 1071 #endif 1072 1073 extern void m68k_emit_move_double (rtx [2]); 1074 1075 extern int m68k_sched_address_bypass_p (rtx, rtx); 1076 extern int m68k_sched_indexed_address_bypass_p (rtx, rtx); 1077 1078 #define CPU_UNITS_QUERY 1 1079