1 /* Subroutines for insn-output.c for Motorola 68000 family. 2 Copyright (C) 1987-2015 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify 7 it under the terms of the GNU General Public License as published by 8 the Free Software Foundation; either version 3, or (at your option) 9 any later version. 10 11 GCC is distributed in the hope that it will be useful, 12 but WITHOUT ANY WARRANTY; without even the implied warranty of 13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 GNU General Public License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "tm.h" 24 #include "hash-set.h" 25 #include "machmode.h" 26 #include "vec.h" 27 #include "double-int.h" 28 #include "input.h" 29 #include "alias.h" 30 #include "symtab.h" 31 #include "wide-int.h" 32 #include "inchash.h" 33 #include "tree.h" 34 #include "fold-const.h" 35 #include "calls.h" 36 #include "stor-layout.h" 37 #include "varasm.h" 38 #include "rtl.h" 39 #include "hard-reg-set.h" 40 #include "function.h" 41 #include "regs.h" 42 #include "insn-config.h" 43 #include "conditions.h" 44 #include "output.h" 45 #include "insn-attr.h" 46 #include "recog.h" 47 #include "diagnostic-core.h" 48 #include "hashtab.h" 49 #include "flags.h" 50 #include "statistics.h" 51 #include "real.h" 52 #include "fixed-value.h" 53 #include "expmed.h" 54 #include "dojump.h" 55 #include "explow.h" 56 #include "emit-rtl.h" 57 #include "stmt.h" 58 #include "expr.h" 59 #include "reload.h" 60 #include "tm_p.h" 61 #include "target.h" 62 #include "target-def.h" 63 #include "debug.h" 64 #include "dominance.h" 65 #include "cfg.h" 66 #include "cfgrtl.h" 67 #include "cfganal.h" 68 #include "lcm.h" 69 #include "cfgbuild.h" 70 #include "cfgcleanup.h" 71 #include "predict.h" 72 #include "basic-block.h" 73 #include "df.h" 74 /* ??? Need to add a dependency between m68k.o and sched-int.h. */ 75 #include "sched-int.h" 76 #include "insn-codes.h" 77 #include "ggc.h" 78 #include "opts.h" 79 #include "optabs.h" 80 #include "builtins.h" 81 #include "rtl-iter.h" 82 83 enum reg_class regno_reg_class[] = 84 { 85 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, 86 DATA_REGS, DATA_REGS, DATA_REGS, DATA_REGS, 87 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, 88 ADDR_REGS, ADDR_REGS, ADDR_REGS, ADDR_REGS, 89 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 90 FP_REGS, FP_REGS, FP_REGS, FP_REGS, 91 ADDR_REGS 92 }; 93 94 95 /* The minimum number of integer registers that we want to save with the 96 movem instruction. Using two movel instructions instead of a single 97 moveml is about 15% faster for the 68020 and 68030 at no expense in 98 code size. */ 99 #define MIN_MOVEM_REGS 3 100 101 /* The minimum number of floating point registers that we want to save 102 with the fmovem instruction. */ 103 #define MIN_FMOVEM_REGS 1 104 105 /* Structure describing stack frame layout. */ 106 struct m68k_frame 107 { 108 /* Stack pointer to frame pointer offset. */ 109 HOST_WIDE_INT offset; 110 111 /* Offset of FPU registers. */ 112 HOST_WIDE_INT foffset; 113 114 /* Frame size in bytes (rounded up). */ 115 HOST_WIDE_INT size; 116 117 /* Data and address register. */ 118 int reg_no; 119 unsigned int reg_mask; 120 121 /* FPU registers. */ 122 int fpu_no; 123 unsigned int fpu_mask; 124 125 /* Offsets relative to ARG_POINTER. */ 126 HOST_WIDE_INT frame_pointer_offset; 127 HOST_WIDE_INT stack_pointer_offset; 128 129 /* Function which the above information refers to. */ 130 int funcdef_no; 131 }; 132 133 /* Current frame information calculated by m68k_compute_frame_layout(). */ 134 static struct m68k_frame current_frame; 135 136 /* Structure describing an m68k address. 137 138 If CODE is UNKNOWN, the address is BASE + INDEX * SCALE + OFFSET, 139 with null fields evaluating to 0. Here: 140 141 - BASE satisfies m68k_legitimate_base_reg_p 142 - INDEX satisfies m68k_legitimate_index_reg_p 143 - OFFSET satisfies m68k_legitimate_constant_address_p 144 145 INDEX is either HImode or SImode. The other fields are SImode. 146 147 If CODE is PRE_DEC, the address is -(BASE). If CODE is POST_INC, 148 the address is (BASE)+. */ 149 struct m68k_address { 150 enum rtx_code code; 151 rtx base; 152 rtx index; 153 rtx offset; 154 int scale; 155 }; 156 157 static int m68k_sched_adjust_cost (rtx_insn *, rtx, rtx_insn *, int); 158 static int m68k_sched_issue_rate (void); 159 static int m68k_sched_variable_issue (FILE *, int, rtx_insn *, int); 160 static void m68k_sched_md_init_global (FILE *, int, int); 161 static void m68k_sched_md_finish_global (FILE *, int); 162 static void m68k_sched_md_init (FILE *, int, int); 163 static void m68k_sched_dfa_pre_advance_cycle (void); 164 static void m68k_sched_dfa_post_advance_cycle (void); 165 static int m68k_sched_first_cycle_multipass_dfa_lookahead (void); 166 167 static bool m68k_can_eliminate (const int, const int); 168 static void m68k_conditional_register_usage (void); 169 static bool m68k_legitimate_address_p (machine_mode, rtx, bool); 170 static void m68k_option_override (void); 171 static void m68k_override_options_after_change (void); 172 static rtx find_addr_reg (rtx); 173 static const char *singlemove_string (rtx *); 174 static void m68k_output_mi_thunk (FILE *, tree, HOST_WIDE_INT, 175 HOST_WIDE_INT, tree); 176 static rtx m68k_struct_value_rtx (tree, int); 177 static tree m68k_handle_fndecl_attribute (tree *node, tree name, 178 tree args, int flags, 179 bool *no_add_attrs); 180 static void m68k_compute_frame_layout (void); 181 static bool m68k_save_reg (unsigned int regno, bool interrupt_handler); 182 static bool m68k_ok_for_sibcall_p (tree, tree); 183 static bool m68k_tls_symbol_p (rtx); 184 static rtx m68k_legitimize_address (rtx, rtx, machine_mode); 185 static bool m68k_rtx_costs (rtx, int, int, int, int *, bool); 186 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT 187 static bool m68k_return_in_memory (const_tree, const_tree); 188 #endif 189 static void m68k_output_dwarf_dtprel (FILE *, int, rtx) ATTRIBUTE_UNUSED; 190 static void m68k_trampoline_init (rtx, tree, rtx); 191 static int m68k_return_pops_args (tree, tree, int); 192 static rtx m68k_delegitimize_address (rtx); 193 static void m68k_function_arg_advance (cumulative_args_t, machine_mode, 194 const_tree, bool); 195 static rtx m68k_function_arg (cumulative_args_t, machine_mode, 196 const_tree, bool); 197 static bool m68k_cannot_force_const_mem (machine_mode mode, rtx x); 198 static bool m68k_output_addr_const_extra (FILE *, rtx); 199 static void m68k_init_sync_libfuncs (void) ATTRIBUTE_UNUSED; 200 201 /* Initialize the GCC target structure. */ 202 203 #if INT_OP_GROUP == INT_OP_DOT_WORD 204 #undef TARGET_ASM_ALIGNED_HI_OP 205 #define TARGET_ASM_ALIGNED_HI_OP "\t.word\t" 206 #endif 207 208 #if INT_OP_GROUP == INT_OP_NO_DOT 209 #undef TARGET_ASM_BYTE_OP 210 #define TARGET_ASM_BYTE_OP "\tbyte\t" 211 #undef TARGET_ASM_ALIGNED_HI_OP 212 #define TARGET_ASM_ALIGNED_HI_OP "\tshort\t" 213 #undef TARGET_ASM_ALIGNED_SI_OP 214 #define TARGET_ASM_ALIGNED_SI_OP "\tlong\t" 215 #endif 216 217 #if INT_OP_GROUP == INT_OP_DC 218 #undef TARGET_ASM_BYTE_OP 219 #define TARGET_ASM_BYTE_OP "\tdc.b\t" 220 #undef TARGET_ASM_ALIGNED_HI_OP 221 #define TARGET_ASM_ALIGNED_HI_OP "\tdc.w\t" 222 #undef TARGET_ASM_ALIGNED_SI_OP 223 #define TARGET_ASM_ALIGNED_SI_OP "\tdc.l\t" 224 #endif 225 226 #undef TARGET_ASM_UNALIGNED_HI_OP 227 #define TARGET_ASM_UNALIGNED_HI_OP TARGET_ASM_ALIGNED_HI_OP 228 #undef TARGET_ASM_UNALIGNED_SI_OP 229 #define TARGET_ASM_UNALIGNED_SI_OP TARGET_ASM_ALIGNED_SI_OP 230 231 #undef TARGET_ASM_OUTPUT_MI_THUNK 232 #define TARGET_ASM_OUTPUT_MI_THUNK m68k_output_mi_thunk 233 #undef TARGET_ASM_CAN_OUTPUT_MI_THUNK 234 #define TARGET_ASM_CAN_OUTPUT_MI_THUNK hook_bool_const_tree_hwi_hwi_const_tree_true 235 236 #undef TARGET_ASM_FILE_START_APP_OFF 237 #define TARGET_ASM_FILE_START_APP_OFF true 238 239 #undef TARGET_LEGITIMIZE_ADDRESS 240 #define TARGET_LEGITIMIZE_ADDRESS m68k_legitimize_address 241 242 #undef TARGET_SCHED_ADJUST_COST 243 #define TARGET_SCHED_ADJUST_COST m68k_sched_adjust_cost 244 245 #undef TARGET_SCHED_ISSUE_RATE 246 #define TARGET_SCHED_ISSUE_RATE m68k_sched_issue_rate 247 248 #undef TARGET_SCHED_VARIABLE_ISSUE 249 #define TARGET_SCHED_VARIABLE_ISSUE m68k_sched_variable_issue 250 251 #undef TARGET_SCHED_INIT_GLOBAL 252 #define TARGET_SCHED_INIT_GLOBAL m68k_sched_md_init_global 253 254 #undef TARGET_SCHED_FINISH_GLOBAL 255 #define TARGET_SCHED_FINISH_GLOBAL m68k_sched_md_finish_global 256 257 #undef TARGET_SCHED_INIT 258 #define TARGET_SCHED_INIT m68k_sched_md_init 259 260 #undef TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE 261 #define TARGET_SCHED_DFA_PRE_ADVANCE_CYCLE m68k_sched_dfa_pre_advance_cycle 262 263 #undef TARGET_SCHED_DFA_POST_ADVANCE_CYCLE 264 #define TARGET_SCHED_DFA_POST_ADVANCE_CYCLE m68k_sched_dfa_post_advance_cycle 265 266 #undef TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD 267 #define TARGET_SCHED_FIRST_CYCLE_MULTIPASS_DFA_LOOKAHEAD \ 268 m68k_sched_first_cycle_multipass_dfa_lookahead 269 270 #undef TARGET_OPTION_OVERRIDE 271 #define TARGET_OPTION_OVERRIDE m68k_option_override 272 273 #undef TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE 274 #define TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE m68k_override_options_after_change 275 276 #undef TARGET_RTX_COSTS 277 #define TARGET_RTX_COSTS m68k_rtx_costs 278 279 #undef TARGET_ATTRIBUTE_TABLE 280 #define TARGET_ATTRIBUTE_TABLE m68k_attribute_table 281 282 #undef TARGET_PROMOTE_PROTOTYPES 283 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true 284 285 #undef TARGET_STRUCT_VALUE_RTX 286 #define TARGET_STRUCT_VALUE_RTX m68k_struct_value_rtx 287 288 #undef TARGET_CANNOT_FORCE_CONST_MEM 289 #define TARGET_CANNOT_FORCE_CONST_MEM m68k_cannot_force_const_mem 290 291 #undef TARGET_FUNCTION_OK_FOR_SIBCALL 292 #define TARGET_FUNCTION_OK_FOR_SIBCALL m68k_ok_for_sibcall_p 293 294 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT 295 #undef TARGET_RETURN_IN_MEMORY 296 #define TARGET_RETURN_IN_MEMORY m68k_return_in_memory 297 #endif 298 299 #ifdef HAVE_AS_TLS 300 #undef TARGET_HAVE_TLS 301 #define TARGET_HAVE_TLS (true) 302 303 #undef TARGET_ASM_OUTPUT_DWARF_DTPREL 304 #define TARGET_ASM_OUTPUT_DWARF_DTPREL m68k_output_dwarf_dtprel 305 #endif 306 307 #undef TARGET_LEGITIMATE_ADDRESS_P 308 #define TARGET_LEGITIMATE_ADDRESS_P m68k_legitimate_address_p 309 310 #undef TARGET_CAN_ELIMINATE 311 #define TARGET_CAN_ELIMINATE m68k_can_eliminate 312 313 #undef TARGET_CONDITIONAL_REGISTER_USAGE 314 #define TARGET_CONDITIONAL_REGISTER_USAGE m68k_conditional_register_usage 315 316 #undef TARGET_TRAMPOLINE_INIT 317 #define TARGET_TRAMPOLINE_INIT m68k_trampoline_init 318 319 #undef TARGET_RETURN_POPS_ARGS 320 #define TARGET_RETURN_POPS_ARGS m68k_return_pops_args 321 322 #undef TARGET_DELEGITIMIZE_ADDRESS 323 #define TARGET_DELEGITIMIZE_ADDRESS m68k_delegitimize_address 324 325 #undef TARGET_FUNCTION_ARG 326 #define TARGET_FUNCTION_ARG m68k_function_arg 327 328 #undef TARGET_FUNCTION_ARG_ADVANCE 329 #define TARGET_FUNCTION_ARG_ADVANCE m68k_function_arg_advance 330 331 #undef TARGET_LEGITIMATE_CONSTANT_P 332 #define TARGET_LEGITIMATE_CONSTANT_P m68k_legitimate_constant_p 333 334 #undef TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA 335 #define TARGET_ASM_OUTPUT_ADDR_CONST_EXTRA m68k_output_addr_const_extra 336 337 /* The value stored by TAS. */ 338 #undef TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 339 #define TARGET_ATOMIC_TEST_AND_SET_TRUEVAL 128 340 341 static const struct attribute_spec m68k_attribute_table[] = 342 { 343 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, 344 affects_type_identity } */ 345 { "interrupt", 0, 0, true, false, false, m68k_handle_fndecl_attribute, 346 false }, 347 { "interrupt_handler", 0, 0, true, false, false, 348 m68k_handle_fndecl_attribute, false }, 349 { "interrupt_thread", 0, 0, true, false, false, 350 m68k_handle_fndecl_attribute, false }, 351 { NULL, 0, 0, false, false, false, NULL, false } 352 }; 353 354 struct gcc_target targetm = TARGET_INITIALIZER; 355 356 /* Base flags for 68k ISAs. */ 357 #define FL_FOR_isa_00 FL_ISA_68000 358 #define FL_FOR_isa_10 (FL_FOR_isa_00 | FL_ISA_68010) 359 /* FL_68881 controls the default setting of -m68881. gcc has traditionally 360 generated 68881 code for 68020 and 68030 targets unless explicitly told 361 not to. */ 362 #define FL_FOR_isa_20 (FL_FOR_isa_10 | FL_ISA_68020 \ 363 | FL_BITFIELD | FL_68881 | FL_CAS) 364 #define FL_FOR_isa_40 (FL_FOR_isa_20 | FL_ISA_68040) 365 #define FL_FOR_isa_cpu32 (FL_FOR_isa_10 | FL_ISA_68020) 366 367 /* Base flags for ColdFire ISAs. */ 368 #define FL_FOR_isa_a (FL_COLDFIRE | FL_ISA_A) 369 #define FL_FOR_isa_aplus (FL_FOR_isa_a | FL_ISA_APLUS | FL_CF_USP) 370 /* Note ISA_B doesn't necessarily include USP (user stack pointer) support. */ 371 #define FL_FOR_isa_b (FL_FOR_isa_a | FL_ISA_B | FL_CF_HWDIV) 372 /* ISA_C is not upwardly compatible with ISA_B. */ 373 #define FL_FOR_isa_c (FL_FOR_isa_a | FL_ISA_C | FL_CF_USP) 374 375 enum m68k_isa 376 { 377 /* Traditional 68000 instruction sets. */ 378 isa_00, 379 isa_10, 380 isa_20, 381 isa_40, 382 isa_cpu32, 383 /* ColdFire instruction set variants. */ 384 isa_a, 385 isa_aplus, 386 isa_b, 387 isa_c, 388 isa_max 389 }; 390 391 /* Information about one of the -march, -mcpu or -mtune arguments. */ 392 struct m68k_target_selection 393 { 394 /* The argument being described. */ 395 const char *name; 396 397 /* For -mcpu, this is the device selected by the option. 398 For -mtune and -march, it is a representative device 399 for the microarchitecture or ISA respectively. */ 400 enum target_device device; 401 402 /* The M68K_DEVICE fields associated with DEVICE. See the comment 403 in m68k-devices.def for details. FAMILY is only valid for -mcpu. */ 404 const char *family; 405 enum uarch_type microarch; 406 enum m68k_isa isa; 407 unsigned long flags; 408 }; 409 410 /* A list of all devices in m68k-devices.def. Used for -mcpu selection. */ 411 static const struct m68k_target_selection all_devices[] = 412 { 413 #define M68K_DEVICE(NAME,ENUM_VALUE,FAMILY,MULTILIB,MICROARCH,ISA,FLAGS) \ 414 { NAME, ENUM_VALUE, FAMILY, u##MICROARCH, ISA, FLAGS | FL_FOR_##ISA }, 415 #include "m68k-devices.def" 416 #undef M68K_DEVICE 417 { NULL, unk_device, NULL, unk_arch, isa_max, 0 } 418 }; 419 420 /* A list of all ISAs, mapping each one to a representative device. 421 Used for -march selection. */ 422 static const struct m68k_target_selection all_isas[] = 423 { 424 #define M68K_ISA(NAME,DEVICE,MICROARCH,ISA,FLAGS) \ 425 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS }, 426 #include "m68k-isas.def" 427 #undef M68K_ISA 428 { NULL, unk_device, NULL, unk_arch, isa_max, 0 } 429 }; 430 431 /* A list of all microarchitectures, mapping each one to a representative 432 device. Used for -mtune selection. */ 433 static const struct m68k_target_selection all_microarchs[] = 434 { 435 #define M68K_MICROARCH(NAME,DEVICE,MICROARCH,ISA,FLAGS) \ 436 { NAME, DEVICE, NULL, u##MICROARCH, ISA, FLAGS }, 437 #include "m68k-microarchs.def" 438 #undef M68K_MICROARCH 439 { NULL, unk_device, NULL, unk_arch, isa_max, 0 } 440 }; 441 442 /* The entries associated with the -mcpu, -march and -mtune settings, 443 or null for options that have not been used. */ 444 const struct m68k_target_selection *m68k_cpu_entry; 445 const struct m68k_target_selection *m68k_arch_entry; 446 const struct m68k_target_selection *m68k_tune_entry; 447 448 /* Which CPU we are generating code for. */ 449 enum target_device m68k_cpu; 450 451 /* Which microarchitecture to tune for. */ 452 enum uarch_type m68k_tune; 453 454 /* Which FPU to use. */ 455 enum fpu_type m68k_fpu; 456 457 /* The set of FL_* flags that apply to the target processor. */ 458 unsigned int m68k_cpu_flags; 459 460 /* The set of FL_* flags that apply to the processor to be tuned for. */ 461 unsigned int m68k_tune_flags; 462 463 /* Asm templates for calling or jumping to an arbitrary symbolic address, 464 or NULL if such calls or jumps are not supported. The address is held 465 in operand 0. */ 466 const char *m68k_symbolic_call; 467 const char *m68k_symbolic_jump; 468 469 /* Enum variable that corresponds to m68k_symbolic_call values. */ 470 enum M68K_SYMBOLIC_CALL m68k_symbolic_call_var; 471 472 473 /* Implement TARGET_OPTION_OVERRIDE. */ 474 475 static void 476 m68k_option_override (void) 477 { 478 const struct m68k_target_selection *entry; 479 unsigned long target_mask; 480 481 if (global_options_set.x_m68k_arch_option) 482 m68k_arch_entry = &all_isas[m68k_arch_option]; 483 484 if (global_options_set.x_m68k_cpu_option) 485 m68k_cpu_entry = &all_devices[(int) m68k_cpu_option]; 486 487 if (global_options_set.x_m68k_tune_option) 488 m68k_tune_entry = &all_microarchs[(int) m68k_tune_option]; 489 490 /* User can choose: 491 492 -mcpu= 493 -march= 494 -mtune= 495 496 -march=ARCH should generate code that runs any processor 497 implementing architecture ARCH. -mcpu=CPU should override -march 498 and should generate code that runs on processor CPU, making free 499 use of any instructions that CPU understands. -mtune=UARCH applies 500 on top of -mcpu or -march and optimizes the code for UARCH. It does 501 not change the target architecture. */ 502 if (m68k_cpu_entry) 503 { 504 /* Complain if the -march setting is for a different microarchitecture, 505 or includes flags that the -mcpu setting doesn't. */ 506 if (m68k_arch_entry 507 && (m68k_arch_entry->microarch != m68k_cpu_entry->microarch 508 || (m68k_arch_entry->flags & ~m68k_cpu_entry->flags) != 0)) 509 warning (0, "-mcpu=%s conflicts with -march=%s", 510 m68k_cpu_entry->name, m68k_arch_entry->name); 511 512 entry = m68k_cpu_entry; 513 } 514 else 515 entry = m68k_arch_entry; 516 517 if (!entry) 518 entry = all_devices + TARGET_CPU_DEFAULT; 519 520 m68k_cpu_flags = entry->flags; 521 522 /* Use the architecture setting to derive default values for 523 certain flags. */ 524 target_mask = 0; 525 526 /* ColdFire is lenient about alignment. */ 527 if (!TARGET_COLDFIRE) 528 target_mask |= MASK_STRICT_ALIGNMENT; 529 530 if ((m68k_cpu_flags & FL_BITFIELD) != 0) 531 target_mask |= MASK_BITFIELD; 532 if ((m68k_cpu_flags & FL_CF_HWDIV) != 0) 533 target_mask |= MASK_CF_HWDIV; 534 if ((m68k_cpu_flags & (FL_68881 | FL_CF_FPU)) != 0) 535 target_mask |= MASK_HARD_FLOAT; 536 target_flags |= target_mask & ~target_flags_explicit; 537 538 /* Set the directly-usable versions of the -mcpu and -mtune settings. */ 539 m68k_cpu = entry->device; 540 if (m68k_tune_entry) 541 { 542 m68k_tune = m68k_tune_entry->microarch; 543 m68k_tune_flags = m68k_tune_entry->flags; 544 } 545 #ifdef M68K_DEFAULT_TUNE 546 else if (!m68k_cpu_entry && !m68k_arch_entry) 547 { 548 enum target_device dev; 549 dev = all_microarchs[M68K_DEFAULT_TUNE].device; 550 m68k_tune_flags = all_devices[dev].flags; 551 } 552 #endif 553 else 554 { 555 m68k_tune = entry->microarch; 556 m68k_tune_flags = entry->flags; 557 } 558 559 /* Set the type of FPU. */ 560 m68k_fpu = (!TARGET_HARD_FLOAT ? FPUTYPE_NONE 561 : (m68k_cpu_flags & FL_COLDFIRE) != 0 ? FPUTYPE_COLDFIRE 562 : FPUTYPE_68881); 563 564 /* Sanity check to ensure that msep-data and mid-sahred-library are not 565 * both specified together. Doing so simply doesn't make sense. 566 */ 567 if (TARGET_SEP_DATA && TARGET_ID_SHARED_LIBRARY) 568 error ("cannot specify both -msep-data and -mid-shared-library"); 569 570 /* If we're generating code for a separate A5 relative data segment, 571 * we've got to enable -fPIC as well. This might be relaxable to 572 * -fpic but it hasn't been tested properly. 573 */ 574 if (TARGET_SEP_DATA || TARGET_ID_SHARED_LIBRARY) 575 flag_pic = 2; 576 577 /* -mpcrel -fPIC uses 32-bit pc-relative displacements. Raise an 578 error if the target does not support them. */ 579 if (TARGET_PCREL && !TARGET_68020 && flag_pic == 2) 580 error ("-mpcrel -fPIC is not currently supported on selected cpu"); 581 582 /* ??? A historic way of turning on pic, or is this intended to 583 be an embedded thing that doesn't have the same name binding 584 significance that it does on hosted ELF systems? */ 585 if (TARGET_PCREL && flag_pic == 0) 586 flag_pic = 1; 587 588 if (!flag_pic) 589 { 590 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_JSR; 591 592 m68k_symbolic_jump = "jra %a0"; 593 } 594 else if (TARGET_ID_SHARED_LIBRARY) 595 /* All addresses must be loaded from the GOT. */ 596 ; 597 else if (TARGET_68020 || TARGET_ISAB || TARGET_ISAC) 598 { 599 if (TARGET_PCREL) 600 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_C; 601 else 602 m68k_symbolic_call_var = M68K_SYMBOLIC_CALL_BSR_P; 603 604 if (TARGET_ISAC) 605 /* No unconditional long branch */; 606 else if (TARGET_PCREL) 607 m68k_symbolic_jump = "bra%.l %c0"; 608 else 609 m68k_symbolic_jump = "bra%.l %p0"; 610 /* Turn off function cse if we are doing PIC. We always want 611 function call to be done as `bsr foo@PLTPC'. */ 612 /* ??? It's traditional to do this for -mpcrel too, but it isn't 613 clear how intentional that is. */ 614 flag_no_function_cse = 1; 615 } 616 617 switch (m68k_symbolic_call_var) 618 { 619 case M68K_SYMBOLIC_CALL_JSR: 620 m68k_symbolic_call = "jsr %a0"; 621 break; 622 623 case M68K_SYMBOLIC_CALL_BSR_C: 624 m68k_symbolic_call = "bsr%.l %c0"; 625 break; 626 627 case M68K_SYMBOLIC_CALL_BSR_P: 628 m68k_symbolic_call = "bsr%.l %p0"; 629 break; 630 631 case M68K_SYMBOLIC_CALL_NONE: 632 gcc_assert (m68k_symbolic_call == NULL); 633 break; 634 635 default: 636 gcc_unreachable (); 637 } 638 639 #ifndef ASM_OUTPUT_ALIGN_WITH_NOP 640 if (align_labels > 2) 641 { 642 warning (0, "-falign-labels=%d is not supported", align_labels); 643 align_labels = 0; 644 } 645 if (align_loops > 2) 646 { 647 warning (0, "-falign-loops=%d is not supported", align_loops); 648 align_loops = 0; 649 } 650 #endif 651 652 if (stack_limit_rtx != NULL_RTX && !TARGET_68020) 653 { 654 warning (0, "-fstack-limit- options are not supported on this cpu"); 655 stack_limit_rtx = NULL_RTX; 656 } 657 658 SUBTARGET_OVERRIDE_OPTIONS; 659 660 /* Setup scheduling options. */ 661 if (TUNE_CFV1) 662 m68k_sched_cpu = CPU_CFV1; 663 else if (TUNE_CFV2) 664 m68k_sched_cpu = CPU_CFV2; 665 else if (TUNE_CFV3) 666 m68k_sched_cpu = CPU_CFV3; 667 else if (TUNE_CFV4) 668 m68k_sched_cpu = CPU_CFV4; 669 else 670 { 671 m68k_sched_cpu = CPU_UNKNOWN; 672 flag_schedule_insns = 0; 673 flag_schedule_insns_after_reload = 0; 674 flag_modulo_sched = 0; 675 flag_live_range_shrinkage = 0; 676 } 677 678 if (m68k_sched_cpu != CPU_UNKNOWN) 679 { 680 if ((m68k_cpu_flags & (FL_CF_EMAC | FL_CF_EMAC_B)) != 0) 681 m68k_sched_mac = MAC_CF_EMAC; 682 else if ((m68k_cpu_flags & FL_CF_MAC) != 0) 683 m68k_sched_mac = MAC_CF_MAC; 684 else 685 m68k_sched_mac = MAC_NO; 686 } 687 } 688 689 /* Implement TARGET_OVERRIDE_OPTIONS_AFTER_CHANGE. */ 690 691 static void 692 m68k_override_options_after_change (void) 693 { 694 if (m68k_sched_cpu == CPU_UNKNOWN) 695 { 696 flag_schedule_insns = 0; 697 flag_schedule_insns_after_reload = 0; 698 flag_modulo_sched = 0; 699 flag_live_range_shrinkage = 0; 700 } 701 } 702 703 /* Generate a macro of the form __mPREFIX_cpu_NAME, where PREFIX is the 704 given argument and NAME is the argument passed to -mcpu. Return NULL 705 if -mcpu was not passed. */ 706 707 const char * 708 m68k_cpp_cpu_ident (const char *prefix) 709 { 710 if (!m68k_cpu_entry) 711 return NULL; 712 return concat ("__m", prefix, "_cpu_", m68k_cpu_entry->name, NULL); 713 } 714 715 /* Generate a macro of the form __mPREFIX_family_NAME, where PREFIX is the 716 given argument and NAME is the name of the representative device for 717 the -mcpu argument's family. Return NULL if -mcpu was not passed. */ 718 719 const char * 720 m68k_cpp_cpu_family (const char *prefix) 721 { 722 if (!m68k_cpu_entry) 723 return NULL; 724 return concat ("__m", prefix, "_family_", m68k_cpu_entry->family, NULL); 725 } 726 727 /* Return m68k_fk_interrupt_handler if FUNC has an "interrupt" or 728 "interrupt_handler" attribute and interrupt_thread if FUNC has an 729 "interrupt_thread" attribute. Otherwise, return 730 m68k_fk_normal_function. */ 731 732 enum m68k_function_kind 733 m68k_get_function_kind (tree func) 734 { 735 tree a; 736 737 gcc_assert (TREE_CODE (func) == FUNCTION_DECL); 738 739 a = lookup_attribute ("interrupt", DECL_ATTRIBUTES (func)); 740 if (a != NULL_TREE) 741 return m68k_fk_interrupt_handler; 742 743 a = lookup_attribute ("interrupt_handler", DECL_ATTRIBUTES (func)); 744 if (a != NULL_TREE) 745 return m68k_fk_interrupt_handler; 746 747 a = lookup_attribute ("interrupt_thread", DECL_ATTRIBUTES (func)); 748 if (a != NULL_TREE) 749 return m68k_fk_interrupt_thread; 750 751 return m68k_fk_normal_function; 752 } 753 754 /* Handle an attribute requiring a FUNCTION_DECL; arguments as in 755 struct attribute_spec.handler. */ 756 static tree 757 m68k_handle_fndecl_attribute (tree *node, tree name, 758 tree args ATTRIBUTE_UNUSED, 759 int flags ATTRIBUTE_UNUSED, 760 bool *no_add_attrs) 761 { 762 if (TREE_CODE (*node) != FUNCTION_DECL) 763 { 764 warning (OPT_Wattributes, "%qE attribute only applies to functions", 765 name); 766 *no_add_attrs = true; 767 } 768 769 if (m68k_get_function_kind (*node) != m68k_fk_normal_function) 770 { 771 error ("multiple interrupt attributes not allowed"); 772 *no_add_attrs = true; 773 } 774 775 if (!TARGET_FIDOA 776 && !strcmp (IDENTIFIER_POINTER (name), "interrupt_thread")) 777 { 778 error ("interrupt_thread is available only on fido"); 779 *no_add_attrs = true; 780 } 781 782 return NULL_TREE; 783 } 784 785 static void 786 m68k_compute_frame_layout (void) 787 { 788 int regno, saved; 789 unsigned int mask; 790 enum m68k_function_kind func_kind = 791 m68k_get_function_kind (current_function_decl); 792 bool interrupt_handler = func_kind == m68k_fk_interrupt_handler; 793 bool interrupt_thread = func_kind == m68k_fk_interrupt_thread; 794 795 /* Only compute the frame once per function. 796 Don't cache information until reload has been completed. */ 797 if (current_frame.funcdef_no == current_function_funcdef_no 798 && reload_completed) 799 return; 800 801 current_frame.size = (get_frame_size () + 3) & -4; 802 803 mask = saved = 0; 804 805 /* Interrupt thread does not need to save any register. */ 806 if (!interrupt_thread) 807 for (regno = 0; regno < 16; regno++) 808 if (m68k_save_reg (regno, interrupt_handler)) 809 { 810 mask |= 1 << (regno - D0_REG); 811 saved++; 812 } 813 current_frame.offset = saved * 4; 814 current_frame.reg_no = saved; 815 current_frame.reg_mask = mask; 816 817 current_frame.foffset = 0; 818 mask = saved = 0; 819 if (TARGET_HARD_FLOAT) 820 { 821 /* Interrupt thread does not need to save any register. */ 822 if (!interrupt_thread) 823 for (regno = 16; regno < 24; regno++) 824 if (m68k_save_reg (regno, interrupt_handler)) 825 { 826 mask |= 1 << (regno - FP0_REG); 827 saved++; 828 } 829 current_frame.foffset = saved * TARGET_FP_REG_SIZE; 830 current_frame.offset += current_frame.foffset; 831 } 832 current_frame.fpu_no = saved; 833 current_frame.fpu_mask = mask; 834 835 /* Remember what function this frame refers to. */ 836 current_frame.funcdef_no = current_function_funcdef_no; 837 } 838 839 /* Worker function for TARGET_CAN_ELIMINATE. */ 840 841 bool 842 m68k_can_eliminate (const int from ATTRIBUTE_UNUSED, const int to) 843 { 844 return (to == STACK_POINTER_REGNUM ? ! frame_pointer_needed : true); 845 } 846 847 HOST_WIDE_INT 848 m68k_initial_elimination_offset (int from, int to) 849 { 850 int argptr_offset; 851 /* The arg pointer points 8 bytes before the start of the arguments, 852 as defined by FIRST_PARM_OFFSET. This makes it coincident with the 853 frame pointer in most frames. */ 854 argptr_offset = frame_pointer_needed ? 0 : UNITS_PER_WORD; 855 if (from == ARG_POINTER_REGNUM && to == FRAME_POINTER_REGNUM) 856 return argptr_offset; 857 858 m68k_compute_frame_layout (); 859 860 gcc_assert (to == STACK_POINTER_REGNUM); 861 switch (from) 862 { 863 case ARG_POINTER_REGNUM: 864 return current_frame.offset + current_frame.size - argptr_offset; 865 case FRAME_POINTER_REGNUM: 866 return current_frame.offset + current_frame.size; 867 default: 868 gcc_unreachable (); 869 } 870 } 871 872 /* Refer to the array `regs_ever_live' to determine which registers 873 to save; `regs_ever_live[I]' is nonzero if register number I 874 is ever used in the function. This function is responsible for 875 knowing which registers should not be saved even if used. 876 Return true if we need to save REGNO. */ 877 878 static bool 879 m68k_save_reg (unsigned int regno, bool interrupt_handler) 880 { 881 if (flag_pic && regno == PIC_REG) 882 { 883 if (crtl->saves_all_registers) 884 return true; 885 if (crtl->uses_pic_offset_table) 886 return true; 887 /* Reload may introduce constant pool references into a function 888 that thitherto didn't need a PIC register. Note that the test 889 above will not catch that case because we will only set 890 crtl->uses_pic_offset_table when emitting 891 the address reloads. */ 892 if (crtl->uses_const_pool) 893 return true; 894 } 895 896 if (crtl->calls_eh_return) 897 { 898 unsigned int i; 899 for (i = 0; ; i++) 900 { 901 unsigned int test = EH_RETURN_DATA_REGNO (i); 902 if (test == INVALID_REGNUM) 903 break; 904 if (test == regno) 905 return true; 906 } 907 } 908 909 /* Fixed regs we never touch. */ 910 if (fixed_regs[regno]) 911 return false; 912 913 /* The frame pointer (if it is such) is handled specially. */ 914 if (regno == FRAME_POINTER_REGNUM && frame_pointer_needed) 915 return false; 916 917 /* Interrupt handlers must also save call_used_regs 918 if they are live or when calling nested functions. */ 919 if (interrupt_handler) 920 { 921 if (df_regs_ever_live_p (regno)) 922 return true; 923 924 if (!crtl->is_leaf && call_used_regs[regno]) 925 return true; 926 } 927 928 /* Never need to save registers that aren't touched. */ 929 if (!df_regs_ever_live_p (regno)) 930 return false; 931 932 /* Otherwise save everything that isn't call-clobbered. */ 933 return !call_used_regs[regno]; 934 } 935 936 /* Emit RTL for a MOVEM or FMOVEM instruction. BASE + OFFSET represents 937 the lowest memory address. COUNT is the number of registers to be 938 moved, with register REGNO + I being moved if bit I of MASK is set. 939 STORE_P specifies the direction of the move and ADJUST_STACK_P says 940 whether or not this is pre-decrement (if STORE_P) or post-increment 941 (if !STORE_P) operation. */ 942 943 static rtx_insn * 944 m68k_emit_movem (rtx base, HOST_WIDE_INT offset, 945 unsigned int count, unsigned int regno, 946 unsigned int mask, bool store_p, bool adjust_stack_p) 947 { 948 int i; 949 rtx body, addr, src, operands[2]; 950 machine_mode mode; 951 952 body = gen_rtx_PARALLEL (VOIDmode, rtvec_alloc (adjust_stack_p + count)); 953 mode = reg_raw_mode[regno]; 954 i = 0; 955 956 if (adjust_stack_p) 957 { 958 src = plus_constant (Pmode, base, 959 (count 960 * GET_MODE_SIZE (mode) 961 * (HOST_WIDE_INT) (store_p ? -1 : 1))); 962 XVECEXP (body, 0, i++) = gen_rtx_SET (VOIDmode, base, src); 963 } 964 965 for (; mask != 0; mask >>= 1, regno++) 966 if (mask & 1) 967 { 968 addr = plus_constant (Pmode, base, offset); 969 operands[!store_p] = gen_frame_mem (mode, addr); 970 operands[store_p] = gen_rtx_REG (mode, regno); 971 XVECEXP (body, 0, i++) 972 = gen_rtx_SET (VOIDmode, operands[0], operands[1]); 973 offset += GET_MODE_SIZE (mode); 974 } 975 gcc_assert (i == XVECLEN (body, 0)); 976 977 return emit_insn (body); 978 } 979 980 /* Make INSN a frame-related instruction. */ 981 982 static void 983 m68k_set_frame_related (rtx_insn *insn) 984 { 985 rtx body; 986 int i; 987 988 RTX_FRAME_RELATED_P (insn) = 1; 989 body = PATTERN (insn); 990 if (GET_CODE (body) == PARALLEL) 991 for (i = 0; i < XVECLEN (body, 0); i++) 992 RTX_FRAME_RELATED_P (XVECEXP (body, 0, i)) = 1; 993 } 994 995 /* Emit RTL for the "prologue" define_expand. */ 996 997 void 998 m68k_expand_prologue (void) 999 { 1000 HOST_WIDE_INT fsize_with_regs; 1001 rtx limit, src, dest; 1002 1003 m68k_compute_frame_layout (); 1004 1005 if (flag_stack_usage_info) 1006 current_function_static_stack_size 1007 = current_frame.size + current_frame.offset; 1008 1009 /* If the stack limit is a symbol, we can check it here, 1010 before actually allocating the space. */ 1011 if (crtl->limit_stack 1012 && GET_CODE (stack_limit_rtx) == SYMBOL_REF) 1013 { 1014 limit = plus_constant (Pmode, stack_limit_rtx, current_frame.size + 4); 1015 if (!m68k_legitimate_constant_p (Pmode, limit)) 1016 { 1017 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), limit); 1018 limit = gen_rtx_REG (Pmode, D0_REG); 1019 } 1020 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, 1021 stack_pointer_rtx, limit), 1022 stack_pointer_rtx, limit, 1023 const1_rtx)); 1024 } 1025 1026 fsize_with_regs = current_frame.size; 1027 if (TARGET_COLDFIRE) 1028 { 1029 /* ColdFire's move multiple instructions do not allow pre-decrement 1030 addressing. Add the size of movem saves to the initial stack 1031 allocation instead. */ 1032 if (current_frame.reg_no >= MIN_MOVEM_REGS) 1033 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); 1034 if (current_frame.fpu_no >= MIN_FMOVEM_REGS) 1035 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); 1036 } 1037 1038 if (frame_pointer_needed) 1039 { 1040 if (fsize_with_regs == 0 && TUNE_68040) 1041 { 1042 /* On the 68040, two separate moves are faster than link.w 0. */ 1043 dest = gen_frame_mem (Pmode, 1044 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); 1045 m68k_set_frame_related (emit_move_insn (dest, frame_pointer_rtx)); 1046 m68k_set_frame_related (emit_move_insn (frame_pointer_rtx, 1047 stack_pointer_rtx)); 1048 } 1049 else if (fsize_with_regs < 0x8000 || TARGET_68020) 1050 m68k_set_frame_related 1051 (emit_insn (gen_link (frame_pointer_rtx, 1052 GEN_INT (-4 - fsize_with_regs)))); 1053 else 1054 { 1055 m68k_set_frame_related 1056 (emit_insn (gen_link (frame_pointer_rtx, GEN_INT (-4)))); 1057 m68k_set_frame_related 1058 (emit_insn (gen_addsi3 (stack_pointer_rtx, 1059 stack_pointer_rtx, 1060 GEN_INT (-fsize_with_regs)))); 1061 } 1062 1063 /* If the frame pointer is needed, emit a special barrier that 1064 will prevent the scheduler from moving stores to the frame 1065 before the stack adjustment. */ 1066 emit_insn (gen_stack_tie (stack_pointer_rtx, frame_pointer_rtx)); 1067 } 1068 else if (fsize_with_regs != 0) 1069 m68k_set_frame_related 1070 (emit_insn (gen_addsi3 (stack_pointer_rtx, 1071 stack_pointer_rtx, 1072 GEN_INT (-fsize_with_regs)))); 1073 1074 if (current_frame.fpu_mask) 1075 { 1076 gcc_assert (current_frame.fpu_no >= MIN_FMOVEM_REGS); 1077 if (TARGET_68881) 1078 m68k_set_frame_related 1079 (m68k_emit_movem (stack_pointer_rtx, 1080 current_frame.fpu_no * -GET_MODE_SIZE (XFmode), 1081 current_frame.fpu_no, FP0_REG, 1082 current_frame.fpu_mask, true, true)); 1083 else 1084 { 1085 int offset; 1086 1087 /* If we're using moveml to save the integer registers, 1088 the stack pointer will point to the bottom of the moveml 1089 save area. Find the stack offset of the first FP register. */ 1090 if (current_frame.reg_no < MIN_MOVEM_REGS) 1091 offset = 0; 1092 else 1093 offset = current_frame.reg_no * GET_MODE_SIZE (SImode); 1094 m68k_set_frame_related 1095 (m68k_emit_movem (stack_pointer_rtx, offset, 1096 current_frame.fpu_no, FP0_REG, 1097 current_frame.fpu_mask, true, false)); 1098 } 1099 } 1100 1101 /* If the stack limit is not a symbol, check it here. 1102 This has the disadvantage that it may be too late... */ 1103 if (crtl->limit_stack) 1104 { 1105 if (REG_P (stack_limit_rtx)) 1106 emit_insn (gen_ctrapsi4 (gen_rtx_LTU (VOIDmode, stack_pointer_rtx, 1107 stack_limit_rtx), 1108 stack_pointer_rtx, stack_limit_rtx, 1109 const1_rtx)); 1110 1111 else if (GET_CODE (stack_limit_rtx) != SYMBOL_REF) 1112 warning (0, "stack limit expression is not supported"); 1113 } 1114 1115 if (current_frame.reg_no < MIN_MOVEM_REGS) 1116 { 1117 /* Store each register separately in the same order moveml does. */ 1118 int i; 1119 1120 for (i = 16; i-- > 0; ) 1121 if (current_frame.reg_mask & (1 << i)) 1122 { 1123 src = gen_rtx_REG (SImode, D0_REG + i); 1124 dest = gen_frame_mem (SImode, 1125 gen_rtx_PRE_DEC (Pmode, stack_pointer_rtx)); 1126 m68k_set_frame_related (emit_insn (gen_movsi (dest, src))); 1127 } 1128 } 1129 else 1130 { 1131 if (TARGET_COLDFIRE) 1132 /* The required register save space has already been allocated. 1133 The first register should be stored at (%sp). */ 1134 m68k_set_frame_related 1135 (m68k_emit_movem (stack_pointer_rtx, 0, 1136 current_frame.reg_no, D0_REG, 1137 current_frame.reg_mask, true, false)); 1138 else 1139 m68k_set_frame_related 1140 (m68k_emit_movem (stack_pointer_rtx, 1141 current_frame.reg_no * -GET_MODE_SIZE (SImode), 1142 current_frame.reg_no, D0_REG, 1143 current_frame.reg_mask, true, true)); 1144 } 1145 1146 if (!TARGET_SEP_DATA 1147 && crtl->uses_pic_offset_table) 1148 emit_insn (gen_load_got (pic_offset_table_rtx)); 1149 } 1150 1151 /* Return true if a simple (return) instruction is sufficient for this 1152 instruction (i.e. if no epilogue is needed). */ 1153 1154 bool 1155 m68k_use_return_insn (void) 1156 { 1157 if (!reload_completed || frame_pointer_needed || get_frame_size () != 0) 1158 return false; 1159 1160 m68k_compute_frame_layout (); 1161 return current_frame.offset == 0; 1162 } 1163 1164 /* Emit RTL for the "epilogue" or "sibcall_epilogue" define_expand; 1165 SIBCALL_P says which. 1166 1167 The function epilogue should not depend on the current stack pointer! 1168 It should use the frame pointer only, if there is a frame pointer. 1169 This is mandatory because of alloca; we also take advantage of it to 1170 omit stack adjustments before returning. */ 1171 1172 void 1173 m68k_expand_epilogue (bool sibcall_p) 1174 { 1175 HOST_WIDE_INT fsize, fsize_with_regs; 1176 bool big, restore_from_sp; 1177 1178 m68k_compute_frame_layout (); 1179 1180 fsize = current_frame.size; 1181 big = false; 1182 restore_from_sp = false; 1183 1184 /* FIXME : crtl->is_leaf below is too strong. 1185 What we really need to know there is if there could be pending 1186 stack adjustment needed at that point. */ 1187 restore_from_sp = (!frame_pointer_needed 1188 || (!cfun->calls_alloca && crtl->is_leaf)); 1189 1190 /* fsize_with_regs is the size we need to adjust the sp when 1191 popping the frame. */ 1192 fsize_with_regs = fsize; 1193 if (TARGET_COLDFIRE && restore_from_sp) 1194 { 1195 /* ColdFire's move multiple instructions do not allow post-increment 1196 addressing. Add the size of movem loads to the final deallocation 1197 instead. */ 1198 if (current_frame.reg_no >= MIN_MOVEM_REGS) 1199 fsize_with_regs += current_frame.reg_no * GET_MODE_SIZE (SImode); 1200 if (current_frame.fpu_no >= MIN_FMOVEM_REGS) 1201 fsize_with_regs += current_frame.fpu_no * GET_MODE_SIZE (DFmode); 1202 } 1203 1204 if (current_frame.offset + fsize >= 0x8000 1205 && !restore_from_sp 1206 && (current_frame.reg_mask || current_frame.fpu_mask)) 1207 { 1208 if (TARGET_COLDFIRE 1209 && (current_frame.reg_no >= MIN_MOVEM_REGS 1210 || current_frame.fpu_no >= MIN_FMOVEM_REGS)) 1211 { 1212 /* ColdFire's move multiple instructions do not support the 1213 (d8,Ax,Xi) addressing mode, so we're as well using a normal 1214 stack-based restore. */ 1215 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), 1216 GEN_INT (-(current_frame.offset + fsize))); 1217 emit_insn (gen_addsi3 (stack_pointer_rtx, 1218 gen_rtx_REG (Pmode, A1_REG), 1219 frame_pointer_rtx)); 1220 restore_from_sp = true; 1221 } 1222 else 1223 { 1224 emit_move_insn (gen_rtx_REG (Pmode, A1_REG), GEN_INT (-fsize)); 1225 fsize = 0; 1226 big = true; 1227 } 1228 } 1229 1230 if (current_frame.reg_no < MIN_MOVEM_REGS) 1231 { 1232 /* Restore each register separately in the same order moveml does. */ 1233 int i; 1234 HOST_WIDE_INT offset; 1235 1236 offset = current_frame.offset + fsize; 1237 for (i = 0; i < 16; i++) 1238 if (current_frame.reg_mask & (1 << i)) 1239 { 1240 rtx addr; 1241 1242 if (big) 1243 { 1244 /* Generate the address -OFFSET(%fp,%a1.l). */ 1245 addr = gen_rtx_REG (Pmode, A1_REG); 1246 addr = gen_rtx_PLUS (Pmode, addr, frame_pointer_rtx); 1247 addr = plus_constant (Pmode, addr, -offset); 1248 } 1249 else if (restore_from_sp) 1250 addr = gen_rtx_POST_INC (Pmode, stack_pointer_rtx); 1251 else 1252 addr = plus_constant (Pmode, frame_pointer_rtx, -offset); 1253 emit_move_insn (gen_rtx_REG (SImode, D0_REG + i), 1254 gen_frame_mem (SImode, addr)); 1255 offset -= GET_MODE_SIZE (SImode); 1256 } 1257 } 1258 else if (current_frame.reg_mask) 1259 { 1260 if (big) 1261 m68k_emit_movem (gen_rtx_PLUS (Pmode, 1262 gen_rtx_REG (Pmode, A1_REG), 1263 frame_pointer_rtx), 1264 -(current_frame.offset + fsize), 1265 current_frame.reg_no, D0_REG, 1266 current_frame.reg_mask, false, false); 1267 else if (restore_from_sp) 1268 m68k_emit_movem (stack_pointer_rtx, 0, 1269 current_frame.reg_no, D0_REG, 1270 current_frame.reg_mask, false, 1271 !TARGET_COLDFIRE); 1272 else 1273 m68k_emit_movem (frame_pointer_rtx, 1274 -(current_frame.offset + fsize), 1275 current_frame.reg_no, D0_REG, 1276 current_frame.reg_mask, false, false); 1277 } 1278 1279 if (current_frame.fpu_no > 0) 1280 { 1281 if (big) 1282 m68k_emit_movem (gen_rtx_PLUS (Pmode, 1283 gen_rtx_REG (Pmode, A1_REG), 1284 frame_pointer_rtx), 1285 -(current_frame.foffset + fsize), 1286 current_frame.fpu_no, FP0_REG, 1287 current_frame.fpu_mask, false, false); 1288 else if (restore_from_sp) 1289 { 1290 if (TARGET_COLDFIRE) 1291 { 1292 int offset; 1293 1294 /* If we used moveml to restore the integer registers, the 1295 stack pointer will still point to the bottom of the moveml 1296 save area. Find the stack offset of the first FP 1297 register. */ 1298 if (current_frame.reg_no < MIN_MOVEM_REGS) 1299 offset = 0; 1300 else 1301 offset = current_frame.reg_no * GET_MODE_SIZE (SImode); 1302 m68k_emit_movem (stack_pointer_rtx, offset, 1303 current_frame.fpu_no, FP0_REG, 1304 current_frame.fpu_mask, false, false); 1305 } 1306 else 1307 m68k_emit_movem (stack_pointer_rtx, 0, 1308 current_frame.fpu_no, FP0_REG, 1309 current_frame.fpu_mask, false, true); 1310 } 1311 else 1312 m68k_emit_movem (frame_pointer_rtx, 1313 -(current_frame.foffset + fsize), 1314 current_frame.fpu_no, FP0_REG, 1315 current_frame.fpu_mask, false, false); 1316 } 1317 1318 if (frame_pointer_needed) 1319 emit_insn (gen_unlink (frame_pointer_rtx)); 1320 else if (fsize_with_regs) 1321 emit_insn (gen_addsi3 (stack_pointer_rtx, 1322 stack_pointer_rtx, 1323 GEN_INT (fsize_with_regs))); 1324 1325 if (crtl->calls_eh_return) 1326 emit_insn (gen_addsi3 (stack_pointer_rtx, 1327 stack_pointer_rtx, 1328 EH_RETURN_STACKADJ_RTX)); 1329 1330 if (!sibcall_p) 1331 emit_jump_insn (ret_rtx); 1332 } 1333 1334 /* Return true if X is a valid comparison operator for the dbcc 1335 instruction. 1336 1337 Note it rejects floating point comparison operators. 1338 (In the future we could use Fdbcc). 1339 1340 It also rejects some comparisons when CC_NO_OVERFLOW is set. */ 1341 1342 int 1343 valid_dbcc_comparison_p_2 (rtx x, machine_mode mode ATTRIBUTE_UNUSED) 1344 { 1345 switch (GET_CODE (x)) 1346 { 1347 case EQ: case NE: case GTU: case LTU: 1348 case GEU: case LEU: 1349 return 1; 1350 1351 /* Reject some when CC_NO_OVERFLOW is set. This may be over 1352 conservative */ 1353 case GT: case LT: case GE: case LE: 1354 return ! (cc_prev_status.flags & CC_NO_OVERFLOW); 1355 default: 1356 return 0; 1357 } 1358 } 1359 1360 /* Return nonzero if flags are currently in the 68881 flag register. */ 1361 int 1362 flags_in_68881 (void) 1363 { 1364 /* We could add support for these in the future */ 1365 return cc_status.flags & CC_IN_68881; 1366 } 1367 1368 /* Return true if PARALLEL contains register REGNO. */ 1369 static bool 1370 m68k_reg_present_p (const_rtx parallel, unsigned int regno) 1371 { 1372 int i; 1373 1374 if (REG_P (parallel) && REGNO (parallel) == regno) 1375 return true; 1376 1377 if (GET_CODE (parallel) != PARALLEL) 1378 return false; 1379 1380 for (i = 0; i < XVECLEN (parallel, 0); ++i) 1381 { 1382 const_rtx x; 1383 1384 x = XEXP (XVECEXP (parallel, 0, i), 0); 1385 if (REG_P (x) && REGNO (x) == regno) 1386 return true; 1387 } 1388 1389 return false; 1390 } 1391 1392 /* Implement TARGET_FUNCTION_OK_FOR_SIBCALL_P. */ 1393 1394 static bool 1395 m68k_ok_for_sibcall_p (tree decl, tree exp) 1396 { 1397 enum m68k_function_kind kind; 1398 1399 /* We cannot use sibcalls for nested functions because we use the 1400 static chain register for indirect calls. */ 1401 if (CALL_EXPR_STATIC_CHAIN (exp)) 1402 return false; 1403 1404 if (!VOID_TYPE_P (TREE_TYPE (DECL_RESULT (cfun->decl)))) 1405 { 1406 /* Check that the return value locations are the same. For 1407 example that we aren't returning a value from the sibling in 1408 a D0 register but then need to transfer it to a A0 register. */ 1409 rtx cfun_value; 1410 rtx call_value; 1411 1412 cfun_value = FUNCTION_VALUE (TREE_TYPE (DECL_RESULT (cfun->decl)), 1413 cfun->decl); 1414 call_value = FUNCTION_VALUE (TREE_TYPE (exp), decl); 1415 1416 /* Check that the values are equal or that the result the callee 1417 function returns is superset of what the current function returns. */ 1418 if (!(rtx_equal_p (cfun_value, call_value) 1419 || (REG_P (cfun_value) 1420 && m68k_reg_present_p (call_value, REGNO (cfun_value))))) 1421 return false; 1422 } 1423 1424 kind = m68k_get_function_kind (current_function_decl); 1425 if (kind == m68k_fk_normal_function) 1426 /* We can always sibcall from a normal function, because it's 1427 undefined if it is calling an interrupt function. */ 1428 return true; 1429 1430 /* Otherwise we can only sibcall if the function kind is known to be 1431 the same. */ 1432 if (decl && m68k_get_function_kind (decl) == kind) 1433 return true; 1434 1435 return false; 1436 } 1437 1438 /* On the m68k all args are always pushed. */ 1439 1440 static rtx 1441 m68k_function_arg (cumulative_args_t cum ATTRIBUTE_UNUSED, 1442 machine_mode mode ATTRIBUTE_UNUSED, 1443 const_tree type ATTRIBUTE_UNUSED, 1444 bool named ATTRIBUTE_UNUSED) 1445 { 1446 return NULL_RTX; 1447 } 1448 1449 static void 1450 m68k_function_arg_advance (cumulative_args_t cum_v, machine_mode mode, 1451 const_tree type, bool named ATTRIBUTE_UNUSED) 1452 { 1453 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1454 1455 *cum += (mode != BLKmode 1456 ? (GET_MODE_SIZE (mode) + 3) & ~3 1457 : (int_size_in_bytes (type) + 3) & ~3); 1458 } 1459 1460 /* Convert X to a legitimate function call memory reference and return the 1461 result. */ 1462 1463 rtx 1464 m68k_legitimize_call_address (rtx x) 1465 { 1466 gcc_assert (MEM_P (x)); 1467 if (call_operand (XEXP (x, 0), VOIDmode)) 1468 return x; 1469 return replace_equiv_address (x, force_reg (Pmode, XEXP (x, 0))); 1470 } 1471 1472 /* Likewise for sibling calls. */ 1473 1474 rtx 1475 m68k_legitimize_sibcall_address (rtx x) 1476 { 1477 gcc_assert (MEM_P (x)); 1478 if (sibcall_operand (XEXP (x, 0), VOIDmode)) 1479 return x; 1480 1481 emit_move_insn (gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM), XEXP (x, 0)); 1482 return replace_equiv_address (x, gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM)); 1483 } 1484 1485 /* Convert X to a legitimate address and return it if successful. Otherwise 1486 return X. 1487 1488 For the 68000, we handle X+REG by loading X into a register R and 1489 using R+REG. R will go in an address reg and indexing will be used. 1490 However, if REG is a broken-out memory address or multiplication, 1491 nothing needs to be done because REG can certainly go in an address reg. */ 1492 1493 static rtx 1494 m68k_legitimize_address (rtx x, rtx oldx, machine_mode mode) 1495 { 1496 if (m68k_tls_symbol_p (x)) 1497 return m68k_legitimize_tls_address (x); 1498 1499 if (GET_CODE (x) == PLUS) 1500 { 1501 int ch = (x) != (oldx); 1502 int copied = 0; 1503 1504 #define COPY_ONCE(Y) if (!copied) { Y = copy_rtx (Y); copied = ch = 1; } 1505 1506 if (GET_CODE (XEXP (x, 0)) == MULT) 1507 { 1508 COPY_ONCE (x); 1509 XEXP (x, 0) = force_operand (XEXP (x, 0), 0); 1510 } 1511 if (GET_CODE (XEXP (x, 1)) == MULT) 1512 { 1513 COPY_ONCE (x); 1514 XEXP (x, 1) = force_operand (XEXP (x, 1), 0); 1515 } 1516 if (ch) 1517 { 1518 if (GET_CODE (XEXP (x, 1)) == REG 1519 && GET_CODE (XEXP (x, 0)) == REG) 1520 { 1521 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) 1522 { 1523 COPY_ONCE (x); 1524 x = force_operand (x, 0); 1525 } 1526 return x; 1527 } 1528 if (memory_address_p (mode, x)) 1529 return x; 1530 } 1531 if (GET_CODE (XEXP (x, 0)) == REG 1532 || (GET_CODE (XEXP (x, 0)) == SIGN_EXTEND 1533 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG 1534 && GET_MODE (XEXP (XEXP (x, 0), 0)) == HImode)) 1535 { 1536 rtx temp = gen_reg_rtx (Pmode); 1537 rtx val = force_operand (XEXP (x, 1), 0); 1538 emit_move_insn (temp, val); 1539 COPY_ONCE (x); 1540 XEXP (x, 1) = temp; 1541 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT 1542 && GET_CODE (XEXP (x, 0)) == REG) 1543 x = force_operand (x, 0); 1544 } 1545 else if (GET_CODE (XEXP (x, 1)) == REG 1546 || (GET_CODE (XEXP (x, 1)) == SIGN_EXTEND 1547 && GET_CODE (XEXP (XEXP (x, 1), 0)) == REG 1548 && GET_MODE (XEXP (XEXP (x, 1), 0)) == HImode)) 1549 { 1550 rtx temp = gen_reg_rtx (Pmode); 1551 rtx val = force_operand (XEXP (x, 0), 0); 1552 emit_move_insn (temp, val); 1553 COPY_ONCE (x); 1554 XEXP (x, 0) = temp; 1555 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT 1556 && GET_CODE (XEXP (x, 1)) == REG) 1557 x = force_operand (x, 0); 1558 } 1559 } 1560 1561 return x; 1562 } 1563 1564 1565 /* Output a dbCC; jCC sequence. Note we do not handle the 1566 floating point version of this sequence (Fdbcc). We also 1567 do not handle alternative conditions when CC_NO_OVERFLOW is 1568 set. It is assumed that valid_dbcc_comparison_p and flags_in_68881 will 1569 kick those out before we get here. */ 1570 1571 void 1572 output_dbcc_and_branch (rtx *operands) 1573 { 1574 switch (GET_CODE (operands[3])) 1575 { 1576 case EQ: 1577 output_asm_insn ("dbeq %0,%l1\n\tjeq %l2", operands); 1578 break; 1579 1580 case NE: 1581 output_asm_insn ("dbne %0,%l1\n\tjne %l2", operands); 1582 break; 1583 1584 case GT: 1585 output_asm_insn ("dbgt %0,%l1\n\tjgt %l2", operands); 1586 break; 1587 1588 case GTU: 1589 output_asm_insn ("dbhi %0,%l1\n\tjhi %l2", operands); 1590 break; 1591 1592 case LT: 1593 output_asm_insn ("dblt %0,%l1\n\tjlt %l2", operands); 1594 break; 1595 1596 case LTU: 1597 output_asm_insn ("dbcs %0,%l1\n\tjcs %l2", operands); 1598 break; 1599 1600 case GE: 1601 output_asm_insn ("dbge %0,%l1\n\tjge %l2", operands); 1602 break; 1603 1604 case GEU: 1605 output_asm_insn ("dbcc %0,%l1\n\tjcc %l2", operands); 1606 break; 1607 1608 case LE: 1609 output_asm_insn ("dble %0,%l1\n\tjle %l2", operands); 1610 break; 1611 1612 case LEU: 1613 output_asm_insn ("dbls %0,%l1\n\tjls %l2", operands); 1614 break; 1615 1616 default: 1617 gcc_unreachable (); 1618 } 1619 1620 /* If the decrement is to be done in SImode, then we have 1621 to compensate for the fact that dbcc decrements in HImode. */ 1622 switch (GET_MODE (operands[0])) 1623 { 1624 case SImode: 1625 output_asm_insn ("clr%.w %0\n\tsubq%.l #1,%0\n\tjpl %l1", operands); 1626 break; 1627 1628 case HImode: 1629 break; 1630 1631 default: 1632 gcc_unreachable (); 1633 } 1634 } 1635 1636 const char * 1637 output_scc_di (rtx op, rtx operand1, rtx operand2, rtx dest) 1638 { 1639 rtx loperands[7]; 1640 enum rtx_code op_code = GET_CODE (op); 1641 1642 /* This does not produce a useful cc. */ 1643 CC_STATUS_INIT; 1644 1645 /* The m68k cmp.l instruction requires operand1 to be a reg as used 1646 below. Swap the operands and change the op if these requirements 1647 are not fulfilled. */ 1648 if (GET_CODE (operand2) == REG && GET_CODE (operand1) != REG) 1649 { 1650 rtx tmp = operand1; 1651 1652 operand1 = operand2; 1653 operand2 = tmp; 1654 op_code = swap_condition (op_code); 1655 } 1656 loperands[0] = operand1; 1657 if (GET_CODE (operand1) == REG) 1658 loperands[1] = gen_rtx_REG (SImode, REGNO (operand1) + 1); 1659 else 1660 loperands[1] = adjust_address (operand1, SImode, 4); 1661 if (operand2 != const0_rtx) 1662 { 1663 loperands[2] = operand2; 1664 if (GET_CODE (operand2) == REG) 1665 loperands[3] = gen_rtx_REG (SImode, REGNO (operand2) + 1); 1666 else 1667 loperands[3] = adjust_address (operand2, SImode, 4); 1668 } 1669 loperands[4] = gen_label_rtx (); 1670 if (operand2 != const0_rtx) 1671 output_asm_insn ("cmp%.l %2,%0\n\tjne %l4\n\tcmp%.l %3,%1", loperands); 1672 else 1673 { 1674 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[0])) 1675 output_asm_insn ("tst%.l %0", loperands); 1676 else 1677 output_asm_insn ("cmp%.w #0,%0", loperands); 1678 1679 output_asm_insn ("jne %l4", loperands); 1680 1681 if (TARGET_68020 || TARGET_COLDFIRE || ! ADDRESS_REG_P (loperands[1])) 1682 output_asm_insn ("tst%.l %1", loperands); 1683 else 1684 output_asm_insn ("cmp%.w #0,%1", loperands); 1685 } 1686 1687 loperands[5] = dest; 1688 1689 switch (op_code) 1690 { 1691 case EQ: 1692 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1693 CODE_LABEL_NUMBER (loperands[4])); 1694 output_asm_insn ("seq %5", loperands); 1695 break; 1696 1697 case NE: 1698 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1699 CODE_LABEL_NUMBER (loperands[4])); 1700 output_asm_insn ("sne %5", loperands); 1701 break; 1702 1703 case GT: 1704 loperands[6] = gen_label_rtx (); 1705 output_asm_insn ("shi %5\n\tjra %l6", loperands); 1706 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1707 CODE_LABEL_NUMBER (loperands[4])); 1708 output_asm_insn ("sgt %5", loperands); 1709 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1710 CODE_LABEL_NUMBER (loperands[6])); 1711 break; 1712 1713 case GTU: 1714 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1715 CODE_LABEL_NUMBER (loperands[4])); 1716 output_asm_insn ("shi %5", loperands); 1717 break; 1718 1719 case LT: 1720 loperands[6] = gen_label_rtx (); 1721 output_asm_insn ("scs %5\n\tjra %l6", loperands); 1722 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1723 CODE_LABEL_NUMBER (loperands[4])); 1724 output_asm_insn ("slt %5", loperands); 1725 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1726 CODE_LABEL_NUMBER (loperands[6])); 1727 break; 1728 1729 case LTU: 1730 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1731 CODE_LABEL_NUMBER (loperands[4])); 1732 output_asm_insn ("scs %5", loperands); 1733 break; 1734 1735 case GE: 1736 loperands[6] = gen_label_rtx (); 1737 output_asm_insn ("scc %5\n\tjra %l6", loperands); 1738 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1739 CODE_LABEL_NUMBER (loperands[4])); 1740 output_asm_insn ("sge %5", loperands); 1741 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1742 CODE_LABEL_NUMBER (loperands[6])); 1743 break; 1744 1745 case GEU: 1746 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1747 CODE_LABEL_NUMBER (loperands[4])); 1748 output_asm_insn ("scc %5", loperands); 1749 break; 1750 1751 case LE: 1752 loperands[6] = gen_label_rtx (); 1753 output_asm_insn ("sls %5\n\tjra %l6", loperands); 1754 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1755 CODE_LABEL_NUMBER (loperands[4])); 1756 output_asm_insn ("sle %5", loperands); 1757 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1758 CODE_LABEL_NUMBER (loperands[6])); 1759 break; 1760 1761 case LEU: 1762 (*targetm.asm_out.internal_label) (asm_out_file, "L", 1763 CODE_LABEL_NUMBER (loperands[4])); 1764 output_asm_insn ("sls %5", loperands); 1765 break; 1766 1767 default: 1768 gcc_unreachable (); 1769 } 1770 return ""; 1771 } 1772 1773 const char * 1774 output_btst (rtx *operands, rtx countop, rtx dataop, rtx_insn *insn, int signpos) 1775 { 1776 operands[0] = countop; 1777 operands[1] = dataop; 1778 1779 if (GET_CODE (countop) == CONST_INT) 1780 { 1781 register int count = INTVAL (countop); 1782 /* If COUNT is bigger than size of storage unit in use, 1783 advance to the containing unit of same size. */ 1784 if (count > signpos) 1785 { 1786 int offset = (count & ~signpos) / 8; 1787 count = count & signpos; 1788 operands[1] = dataop = adjust_address (dataop, QImode, offset); 1789 } 1790 if (count == signpos) 1791 cc_status.flags = CC_NOT_POSITIVE | CC_Z_IN_NOT_N; 1792 else 1793 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N; 1794 1795 /* These three statements used to use next_insns_test_no... 1796 but it appears that this should do the same job. */ 1797 if (count == 31 1798 && next_insn_tests_no_inequality (insn)) 1799 return "tst%.l %1"; 1800 if (count == 15 1801 && next_insn_tests_no_inequality (insn)) 1802 return "tst%.w %1"; 1803 if (count == 7 1804 && next_insn_tests_no_inequality (insn)) 1805 return "tst%.b %1"; 1806 /* Try to use `movew to ccr' followed by the appropriate branch insn. 1807 On some m68k variants unfortunately that's slower than btst. 1808 On 68000 and higher, that should also work for all HImode operands. */ 1809 if (TUNE_CPU32 || TARGET_COLDFIRE || optimize_size) 1810 { 1811 if (count == 3 && DATA_REG_P (operands[1]) 1812 && next_insn_tests_no_inequality (insn)) 1813 { 1814 cc_status.flags = CC_NOT_NEGATIVE | CC_Z_IN_NOT_N | CC_NO_OVERFLOW; 1815 return "move%.w %1,%%ccr"; 1816 } 1817 if (count == 2 && DATA_REG_P (operands[1]) 1818 && next_insn_tests_no_inequality (insn)) 1819 { 1820 cc_status.flags = CC_NOT_NEGATIVE | CC_INVERTED | CC_NO_OVERFLOW; 1821 return "move%.w %1,%%ccr"; 1822 } 1823 /* count == 1 followed by bvc/bvs and 1824 count == 0 followed by bcc/bcs are also possible, but need 1825 m68k-specific CC_Z_IN_NOT_V and CC_Z_IN_NOT_C flags. */ 1826 } 1827 1828 cc_status.flags = CC_NOT_NEGATIVE; 1829 } 1830 return "btst %0,%1"; 1831 } 1832 1833 /* Return true if X is a legitimate base register. STRICT_P says 1834 whether we need strict checking. */ 1835 1836 bool 1837 m68k_legitimate_base_reg_p (rtx x, bool strict_p) 1838 { 1839 /* Allow SUBREG everywhere we allow REG. This results in better code. */ 1840 if (!strict_p && GET_CODE (x) == SUBREG) 1841 x = SUBREG_REG (x); 1842 1843 return (REG_P (x) 1844 && (strict_p 1845 ? REGNO_OK_FOR_BASE_P (REGNO (x)) 1846 : REGNO_OK_FOR_BASE_NONSTRICT_P (REGNO (x)))); 1847 } 1848 1849 /* Return true if X is a legitimate index register. STRICT_P says 1850 whether we need strict checking. */ 1851 1852 bool 1853 m68k_legitimate_index_reg_p (rtx x, bool strict_p) 1854 { 1855 if (!strict_p && GET_CODE (x) == SUBREG) 1856 x = SUBREG_REG (x); 1857 1858 return (REG_P (x) 1859 && (strict_p 1860 ? REGNO_OK_FOR_INDEX_P (REGNO (x)) 1861 : REGNO_OK_FOR_INDEX_NONSTRICT_P (REGNO (x)))); 1862 } 1863 1864 /* Return true if X is a legitimate index expression for a (d8,An,Xn) or 1865 (bd,An,Xn) addressing mode. Fill in the INDEX and SCALE fields of 1866 ADDRESS if so. STRICT_P says whether we need strict checking. */ 1867 1868 static bool 1869 m68k_decompose_index (rtx x, bool strict_p, struct m68k_address *address) 1870 { 1871 int scale; 1872 1873 /* Check for a scale factor. */ 1874 scale = 1; 1875 if ((TARGET_68020 || TARGET_COLDFIRE) 1876 && GET_CODE (x) == MULT 1877 && GET_CODE (XEXP (x, 1)) == CONST_INT 1878 && (INTVAL (XEXP (x, 1)) == 2 1879 || INTVAL (XEXP (x, 1)) == 4 1880 || (INTVAL (XEXP (x, 1)) == 8 1881 && (TARGET_COLDFIRE_FPU || !TARGET_COLDFIRE)))) 1882 { 1883 scale = INTVAL (XEXP (x, 1)); 1884 x = XEXP (x, 0); 1885 } 1886 1887 /* Check for a word extension. */ 1888 if (!TARGET_COLDFIRE 1889 && GET_CODE (x) == SIGN_EXTEND 1890 && GET_MODE (XEXP (x, 0)) == HImode) 1891 x = XEXP (x, 0); 1892 1893 if (m68k_legitimate_index_reg_p (x, strict_p)) 1894 { 1895 address->scale = scale; 1896 address->index = x; 1897 return true; 1898 } 1899 1900 return false; 1901 } 1902 1903 /* Return true if X is an illegitimate symbolic constant. */ 1904 1905 bool 1906 m68k_illegitimate_symbolic_constant_p (rtx x) 1907 { 1908 rtx base, offset; 1909 1910 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P) 1911 { 1912 split_const (x, &base, &offset); 1913 if (GET_CODE (base) == SYMBOL_REF 1914 && !offset_within_block_p (base, INTVAL (offset))) 1915 return true; 1916 } 1917 return m68k_tls_reference_p (x, false); 1918 } 1919 1920 /* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ 1921 1922 static bool 1923 m68k_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) 1924 { 1925 return m68k_illegitimate_symbolic_constant_p (x); 1926 } 1927 1928 /* Return true if X is a legitimate constant address that can reach 1929 bytes in the range [X, X + REACH). STRICT_P says whether we need 1930 strict checking. */ 1931 1932 static bool 1933 m68k_legitimate_constant_address_p (rtx x, unsigned int reach, bool strict_p) 1934 { 1935 rtx base, offset; 1936 1937 if (!CONSTANT_ADDRESS_P (x)) 1938 return false; 1939 1940 if (flag_pic 1941 && !(strict_p && TARGET_PCREL) 1942 && symbolic_operand (x, VOIDmode)) 1943 return false; 1944 1945 if (M68K_OFFSETS_MUST_BE_WITHIN_SECTIONS_P && reach > 1) 1946 { 1947 split_const (x, &base, &offset); 1948 if (GET_CODE (base) == SYMBOL_REF 1949 && !offset_within_block_p (base, INTVAL (offset) + reach - 1)) 1950 return false; 1951 } 1952 1953 return !m68k_tls_reference_p (x, false); 1954 } 1955 1956 /* Return true if X is a LABEL_REF for a jump table. Assume that unplaced 1957 labels will become jump tables. */ 1958 1959 static bool 1960 m68k_jump_table_ref_p (rtx x) 1961 { 1962 if (GET_CODE (x) != LABEL_REF) 1963 return false; 1964 1965 rtx_insn *insn = as_a <rtx_insn *> (XEXP (x, 0)); 1966 if (!NEXT_INSN (insn) && !PREV_INSN (insn)) 1967 return true; 1968 1969 insn = next_nonnote_insn (insn); 1970 return insn && JUMP_TABLE_DATA_P (insn); 1971 } 1972 1973 /* Return true if X is a legitimate address for values of mode MODE. 1974 STRICT_P says whether strict checking is needed. If the address 1975 is valid, describe its components in *ADDRESS. */ 1976 1977 static bool 1978 m68k_decompose_address (machine_mode mode, rtx x, 1979 bool strict_p, struct m68k_address *address) 1980 { 1981 unsigned int reach; 1982 1983 memset (address, 0, sizeof (*address)); 1984 1985 if (mode == BLKmode) 1986 reach = 1; 1987 else 1988 reach = GET_MODE_SIZE (mode); 1989 1990 /* Check for (An) (mode 2). */ 1991 if (m68k_legitimate_base_reg_p (x, strict_p)) 1992 { 1993 address->base = x; 1994 return true; 1995 } 1996 1997 /* Check for -(An) and (An)+ (modes 3 and 4). */ 1998 if ((GET_CODE (x) == PRE_DEC || GET_CODE (x) == POST_INC) 1999 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) 2000 { 2001 address->code = GET_CODE (x); 2002 address->base = XEXP (x, 0); 2003 return true; 2004 } 2005 2006 /* Check for (d16,An) (mode 5). */ 2007 if (GET_CODE (x) == PLUS 2008 && GET_CODE (XEXP (x, 1)) == CONST_INT 2009 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x8000, 0x8000 - reach) 2010 && m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p)) 2011 { 2012 address->base = XEXP (x, 0); 2013 address->offset = XEXP (x, 1); 2014 return true; 2015 } 2016 2017 /* Check for GOT loads. These are (bd,An,Xn) addresses if 2018 TARGET_68020 && flag_pic == 2, otherwise they are (d16,An) 2019 addresses. */ 2020 if (GET_CODE (x) == PLUS 2021 && XEXP (x, 0) == pic_offset_table_rtx) 2022 { 2023 /* As we are processing a PLUS, do not unwrap RELOC32 symbols -- 2024 they are invalid in this context. */ 2025 if (m68k_unwrap_symbol (XEXP (x, 1), false) != XEXP (x, 1)) 2026 { 2027 address->base = XEXP (x, 0); 2028 address->offset = XEXP (x, 1); 2029 return true; 2030 } 2031 } 2032 2033 /* The ColdFire FPU only accepts addressing modes 2-5. */ 2034 if (TARGET_COLDFIRE_FPU && GET_MODE_CLASS (mode) == MODE_FLOAT) 2035 return false; 2036 2037 /* Check for (xxx).w and (xxx).l. Also, in the TARGET_PCREL case, 2038 check for (d16,PC) or (bd,PC,Xn) with a suppressed index register. 2039 All these modes are variations of mode 7. */ 2040 if (m68k_legitimate_constant_address_p (x, reach, strict_p)) 2041 { 2042 address->offset = x; 2043 return true; 2044 } 2045 2046 /* Check for (d8,PC,Xn), a mode 7 form. This case is needed for 2047 tablejumps. 2048 2049 ??? do_tablejump creates these addresses before placing the target 2050 label, so we have to assume that unplaced labels are jump table 2051 references. It seems unlikely that we would ever generate indexed 2052 accesses to unplaced labels in other cases. */ 2053 if (GET_CODE (x) == PLUS 2054 && m68k_jump_table_ref_p (XEXP (x, 1)) 2055 && m68k_decompose_index (XEXP (x, 0), strict_p, address)) 2056 { 2057 address->offset = XEXP (x, 1); 2058 return true; 2059 } 2060 2061 /* Everything hereafter deals with (d8,An,Xn.SIZE*SCALE) or 2062 (bd,An,Xn.SIZE*SCALE) addresses. */ 2063 2064 if (TARGET_68020) 2065 { 2066 /* Check for a nonzero base displacement. */ 2067 if (GET_CODE (x) == PLUS 2068 && m68k_legitimate_constant_address_p (XEXP (x, 1), reach, strict_p)) 2069 { 2070 address->offset = XEXP (x, 1); 2071 x = XEXP (x, 0); 2072 } 2073 2074 /* Check for a suppressed index register. */ 2075 if (m68k_legitimate_base_reg_p (x, strict_p)) 2076 { 2077 address->base = x; 2078 return true; 2079 } 2080 2081 /* Check for a suppressed base register. Do not allow this case 2082 for non-symbolic offsets as it effectively gives gcc freedom 2083 to treat data registers as base registers, which can generate 2084 worse code. */ 2085 if (address->offset 2086 && symbolic_operand (address->offset, VOIDmode) 2087 && m68k_decompose_index (x, strict_p, address)) 2088 return true; 2089 } 2090 else 2091 { 2092 /* Check for a nonzero base displacement. */ 2093 if (GET_CODE (x) == PLUS 2094 && GET_CODE (XEXP (x, 1)) == CONST_INT 2095 && IN_RANGE (INTVAL (XEXP (x, 1)), -0x80, 0x80 - reach)) 2096 { 2097 address->offset = XEXP (x, 1); 2098 x = XEXP (x, 0); 2099 } 2100 } 2101 2102 /* We now expect the sum of a base and an index. */ 2103 if (GET_CODE (x) == PLUS) 2104 { 2105 if (m68k_legitimate_base_reg_p (XEXP (x, 0), strict_p) 2106 && m68k_decompose_index (XEXP (x, 1), strict_p, address)) 2107 { 2108 address->base = XEXP (x, 0); 2109 return true; 2110 } 2111 2112 if (m68k_legitimate_base_reg_p (XEXP (x, 1), strict_p) 2113 && m68k_decompose_index (XEXP (x, 0), strict_p, address)) 2114 { 2115 address->base = XEXP (x, 1); 2116 return true; 2117 } 2118 } 2119 return false; 2120 } 2121 2122 /* Return true if X is a legitimate address for values of mode MODE. 2123 STRICT_P says whether strict checking is needed. */ 2124 2125 bool 2126 m68k_legitimate_address_p (machine_mode mode, rtx x, bool strict_p) 2127 { 2128 struct m68k_address address; 2129 2130 return m68k_decompose_address (mode, x, strict_p, &address); 2131 } 2132 2133 /* Return true if X is a memory, describing its address in ADDRESS if so. 2134 Apply strict checking if called during or after reload. */ 2135 2136 static bool 2137 m68k_legitimate_mem_p (rtx x, struct m68k_address *address) 2138 { 2139 return (MEM_P (x) 2140 && m68k_decompose_address (GET_MODE (x), XEXP (x, 0), 2141 reload_in_progress || reload_completed, 2142 address)); 2143 } 2144 2145 /* Implement TARGET_LEGITIMATE_CONSTANT_P. */ 2146 2147 bool 2148 m68k_legitimate_constant_p (machine_mode mode, rtx x) 2149 { 2150 return mode != XFmode && !m68k_illegitimate_symbolic_constant_p (x); 2151 } 2152 2153 /* Return true if X matches the 'Q' constraint. It must be a memory 2154 with a base address and no constant offset or index. */ 2155 2156 bool 2157 m68k_matches_q_p (rtx x) 2158 { 2159 struct m68k_address address; 2160 2161 return (m68k_legitimate_mem_p (x, &address) 2162 && address.code == UNKNOWN 2163 && address.base 2164 && !address.offset 2165 && !address.index); 2166 } 2167 2168 /* Return true if X matches the 'U' constraint. It must be a base address 2169 with a constant offset and no index. */ 2170 2171 bool 2172 m68k_matches_u_p (rtx x) 2173 { 2174 struct m68k_address address; 2175 2176 return (m68k_legitimate_mem_p (x, &address) 2177 && address.code == UNKNOWN 2178 && address.base 2179 && address.offset 2180 && !address.index); 2181 } 2182 2183 /* Return GOT pointer. */ 2184 2185 static rtx 2186 m68k_get_gp (void) 2187 { 2188 if (pic_offset_table_rtx == NULL_RTX) 2189 pic_offset_table_rtx = gen_rtx_REG (Pmode, PIC_REG); 2190 2191 crtl->uses_pic_offset_table = 1; 2192 2193 return pic_offset_table_rtx; 2194 } 2195 2196 /* M68K relocations, used to distinguish GOT and TLS relocations in UNSPEC 2197 wrappers. */ 2198 enum m68k_reloc { RELOC_GOT, RELOC_TLSGD, RELOC_TLSLDM, RELOC_TLSLDO, 2199 RELOC_TLSIE, RELOC_TLSLE }; 2200 2201 #define TLS_RELOC_P(RELOC) ((RELOC) != RELOC_GOT) 2202 2203 /* Wrap symbol X into unspec representing relocation RELOC. 2204 BASE_REG - register that should be added to the result. 2205 TEMP_REG - if non-null, temporary register. */ 2206 2207 static rtx 2208 m68k_wrap_symbol (rtx x, enum m68k_reloc reloc, rtx base_reg, rtx temp_reg) 2209 { 2210 bool use_x_p; 2211 2212 use_x_p = (base_reg == pic_offset_table_rtx) ? TARGET_XGOT : TARGET_XTLS; 2213 2214 if (TARGET_COLDFIRE && use_x_p) 2215 /* When compiling with -mx{got, tls} switch the code will look like this: 2216 2217 move.l <X>@<RELOC>,<TEMP_REG> 2218 add.l <BASE_REG>,<TEMP_REG> */ 2219 { 2220 /* Wrap X in UNSPEC_??? to tip m68k_output_addr_const_extra 2221 to put @RELOC after reference. */ 2222 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)), 2223 UNSPEC_RELOC32); 2224 x = gen_rtx_CONST (Pmode, x); 2225 2226 if (temp_reg == NULL) 2227 { 2228 gcc_assert (can_create_pseudo_p ()); 2229 temp_reg = gen_reg_rtx (Pmode); 2230 } 2231 2232 emit_move_insn (temp_reg, x); 2233 emit_insn (gen_addsi3 (temp_reg, temp_reg, base_reg)); 2234 x = temp_reg; 2235 } 2236 else 2237 { 2238 x = gen_rtx_UNSPEC (Pmode, gen_rtvec (2, x, GEN_INT (reloc)), 2239 UNSPEC_RELOC16); 2240 x = gen_rtx_CONST (Pmode, x); 2241 2242 x = gen_rtx_PLUS (Pmode, base_reg, x); 2243 } 2244 2245 return x; 2246 } 2247 2248 /* Helper for m68k_unwrap_symbol. 2249 Also, if unwrapping was successful (that is if (ORIG != <return value>)), 2250 sets *RELOC_PTR to relocation type for the symbol. */ 2251 2252 static rtx 2253 m68k_unwrap_symbol_1 (rtx orig, bool unwrap_reloc32_p, 2254 enum m68k_reloc *reloc_ptr) 2255 { 2256 if (GET_CODE (orig) == CONST) 2257 { 2258 rtx x; 2259 enum m68k_reloc dummy; 2260 2261 x = XEXP (orig, 0); 2262 2263 if (reloc_ptr == NULL) 2264 reloc_ptr = &dummy; 2265 2266 /* Handle an addend. */ 2267 if ((GET_CODE (x) == PLUS || GET_CODE (x) == MINUS) 2268 && CONST_INT_P (XEXP (x, 1))) 2269 x = XEXP (x, 0); 2270 2271 if (GET_CODE (x) == UNSPEC) 2272 { 2273 switch (XINT (x, 1)) 2274 { 2275 case UNSPEC_RELOC16: 2276 orig = XVECEXP (x, 0, 0); 2277 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1)); 2278 break; 2279 2280 case UNSPEC_RELOC32: 2281 if (unwrap_reloc32_p) 2282 { 2283 orig = XVECEXP (x, 0, 0); 2284 *reloc_ptr = (enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1)); 2285 } 2286 break; 2287 2288 default: 2289 break; 2290 } 2291 } 2292 } 2293 2294 return orig; 2295 } 2296 2297 /* Unwrap symbol from UNSPEC_RELOC16 and, if unwrap_reloc32_p, 2298 UNSPEC_RELOC32 wrappers. */ 2299 2300 rtx 2301 m68k_unwrap_symbol (rtx orig, bool unwrap_reloc32_p) 2302 { 2303 return m68k_unwrap_symbol_1 (orig, unwrap_reloc32_p, NULL); 2304 } 2305 2306 /* Prescan insn before outputing assembler for it. */ 2307 2308 void 2309 m68k_final_prescan_insn (rtx_insn *insn ATTRIBUTE_UNUSED, 2310 rtx *operands, int n_operands) 2311 { 2312 int i; 2313 2314 /* Combine and, possibly, other optimizations may do good job 2315 converting 2316 (const (unspec [(symbol)])) 2317 into 2318 (const (plus (unspec [(symbol)]) 2319 (const_int N))). 2320 The problem with this is emitting @TLS or @GOT decorations. 2321 The decoration is emitted when processing (unspec), so the 2322 result would be "#symbol@TLSLE+N" instead of "#symbol+N@TLSLE". 2323 2324 It seems that the easiest solution to this is to convert such 2325 operands to 2326 (const (unspec [(plus (symbol) 2327 (const_int N))])). 2328 Note, that the top level of operand remains intact, so we don't have 2329 to patch up anything outside of the operand. */ 2330 2331 subrtx_var_iterator::array_type array; 2332 for (i = 0; i < n_operands; ++i) 2333 { 2334 rtx op; 2335 2336 op = operands[i]; 2337 2338 FOR_EACH_SUBRTX_VAR (iter, array, op, ALL) 2339 { 2340 rtx x = *iter; 2341 if (m68k_unwrap_symbol (x, true) != x) 2342 { 2343 rtx plus; 2344 2345 gcc_assert (GET_CODE (x) == CONST); 2346 plus = XEXP (x, 0); 2347 2348 if (GET_CODE (plus) == PLUS || GET_CODE (plus) == MINUS) 2349 { 2350 rtx unspec; 2351 rtx addend; 2352 2353 unspec = XEXP (plus, 0); 2354 gcc_assert (GET_CODE (unspec) == UNSPEC); 2355 addend = XEXP (plus, 1); 2356 gcc_assert (CONST_INT_P (addend)); 2357 2358 /* We now have all the pieces, rearrange them. */ 2359 2360 /* Move symbol to plus. */ 2361 XEXP (plus, 0) = XVECEXP (unspec, 0, 0); 2362 2363 /* Move plus inside unspec. */ 2364 XVECEXP (unspec, 0, 0) = plus; 2365 2366 /* Move unspec to top level of const. */ 2367 XEXP (x, 0) = unspec; 2368 } 2369 iter.skip_subrtxes (); 2370 } 2371 } 2372 } 2373 } 2374 2375 /* Move X to a register and add REG_EQUAL note pointing to ORIG. 2376 If REG is non-null, use it; generate new pseudo otherwise. */ 2377 2378 static rtx 2379 m68k_move_to_reg (rtx x, rtx orig, rtx reg) 2380 { 2381 rtx_insn *insn; 2382 2383 if (reg == NULL_RTX) 2384 { 2385 gcc_assert (can_create_pseudo_p ()); 2386 reg = gen_reg_rtx (Pmode); 2387 } 2388 2389 insn = emit_move_insn (reg, x); 2390 /* Put a REG_EQUAL note on this insn, so that it can be optimized 2391 by loop. */ 2392 set_unique_reg_note (insn, REG_EQUAL, orig); 2393 2394 return reg; 2395 } 2396 2397 /* Does the same as m68k_wrap_symbol, but returns a memory reference to 2398 GOT slot. */ 2399 2400 static rtx 2401 m68k_wrap_symbol_into_got_ref (rtx x, enum m68k_reloc reloc, rtx temp_reg) 2402 { 2403 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), temp_reg); 2404 2405 x = gen_rtx_MEM (Pmode, x); 2406 MEM_READONLY_P (x) = 1; 2407 2408 return x; 2409 } 2410 2411 /* Legitimize PIC addresses. If the address is already 2412 position-independent, we return ORIG. Newly generated 2413 position-independent addresses go to REG. If we need more 2414 than one register, we lose. 2415 2416 An address is legitimized by making an indirect reference 2417 through the Global Offset Table with the name of the symbol 2418 used as an offset. 2419 2420 The assembler and linker are responsible for placing the 2421 address of the symbol in the GOT. The function prologue 2422 is responsible for initializing a5 to the starting address 2423 of the GOT. 2424 2425 The assembler is also responsible for translating a symbol name 2426 into a constant displacement from the start of the GOT. 2427 2428 A quick example may make things a little clearer: 2429 2430 When not generating PIC code to store the value 12345 into _foo 2431 we would generate the following code: 2432 2433 movel #12345, _foo 2434 2435 When generating PIC two transformations are made. First, the compiler 2436 loads the address of foo into a register. So the first transformation makes: 2437 2438 lea _foo, a0 2439 movel #12345, a0@ 2440 2441 The code in movsi will intercept the lea instruction and call this 2442 routine which will transform the instructions into: 2443 2444 movel a5@(_foo:w), a0 2445 movel #12345, a0@ 2446 2447 2448 That (in a nutshell) is how *all* symbol and label references are 2449 handled. */ 2450 2451 rtx 2452 legitimize_pic_address (rtx orig, machine_mode mode ATTRIBUTE_UNUSED, 2453 rtx reg) 2454 { 2455 rtx pic_ref = orig; 2456 2457 /* First handle a simple SYMBOL_REF or LABEL_REF */ 2458 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) 2459 { 2460 gcc_assert (reg); 2461 2462 pic_ref = m68k_wrap_symbol_into_got_ref (orig, RELOC_GOT, reg); 2463 pic_ref = m68k_move_to_reg (pic_ref, orig, reg); 2464 } 2465 else if (GET_CODE (orig) == CONST) 2466 { 2467 rtx base; 2468 2469 /* Make sure this has not already been legitimized. */ 2470 if (m68k_unwrap_symbol (orig, true) != orig) 2471 return orig; 2472 2473 gcc_assert (reg); 2474 2475 /* legitimize both operands of the PLUS */ 2476 gcc_assert (GET_CODE (XEXP (orig, 0)) == PLUS); 2477 2478 base = legitimize_pic_address (XEXP (XEXP (orig, 0), 0), Pmode, reg); 2479 orig = legitimize_pic_address (XEXP (XEXP (orig, 0), 1), Pmode, 2480 base == reg ? 0 : reg); 2481 2482 if (GET_CODE (orig) == CONST_INT) 2483 pic_ref = plus_constant (Pmode, base, INTVAL (orig)); 2484 else 2485 pic_ref = gen_rtx_PLUS (Pmode, base, orig); 2486 } 2487 2488 return pic_ref; 2489 } 2490 2491 /* The __tls_get_addr symbol. */ 2492 static GTY(()) rtx m68k_tls_get_addr; 2493 2494 /* Return SYMBOL_REF for __tls_get_addr. */ 2495 2496 static rtx 2497 m68k_get_tls_get_addr (void) 2498 { 2499 if (m68k_tls_get_addr == NULL_RTX) 2500 m68k_tls_get_addr = init_one_libfunc ("__tls_get_addr"); 2501 2502 return m68k_tls_get_addr; 2503 } 2504 2505 /* Return libcall result in A0 instead of usual D0. */ 2506 static bool m68k_libcall_value_in_a0_p = false; 2507 2508 /* Emit instruction sequence that calls __tls_get_addr. X is 2509 the TLS symbol we are referencing and RELOC is the symbol type to use 2510 (either TLSGD or TLSLDM). EQV is the REG_EQUAL note for the sequence 2511 emitted. A pseudo register with result of __tls_get_addr call is 2512 returned. */ 2513 2514 static rtx 2515 m68k_call_tls_get_addr (rtx x, rtx eqv, enum m68k_reloc reloc) 2516 { 2517 rtx a0; 2518 rtx_insn *insns; 2519 rtx dest; 2520 2521 /* Emit the call sequence. */ 2522 start_sequence (); 2523 2524 /* FIXME: Unfortunately, emit_library_call_value does not 2525 consider (plus (%a5) (const (unspec))) to be a good enough 2526 operand for push, so it forces it into a register. The bad 2527 thing about this is that combiner, due to copy propagation and other 2528 optimizations, sometimes can not later fix this. As a consequence, 2529 additional register may be allocated resulting in a spill. 2530 For reference, see args processing loops in 2531 calls.c:emit_library_call_value_1. 2532 For testcase, see gcc.target/m68k/tls-{gd, ld}.c */ 2533 x = m68k_wrap_symbol (x, reloc, m68k_get_gp (), NULL_RTX); 2534 2535 /* __tls_get_addr() is not a libcall, but emitting a libcall_value 2536 is the simpliest way of generating a call. The difference between 2537 __tls_get_addr() and libcall is that the result is returned in D0 2538 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p 2539 which temporarily switches returning the result to A0. */ 2540 2541 m68k_libcall_value_in_a0_p = true; 2542 a0 = emit_library_call_value (m68k_get_tls_get_addr (), NULL_RTX, LCT_PURE, 2543 Pmode, 1, x, Pmode); 2544 m68k_libcall_value_in_a0_p = false; 2545 2546 insns = get_insns (); 2547 end_sequence (); 2548 2549 gcc_assert (can_create_pseudo_p ()); 2550 dest = gen_reg_rtx (Pmode); 2551 emit_libcall_block (insns, dest, a0, eqv); 2552 2553 return dest; 2554 } 2555 2556 /* The __tls_get_addr symbol. */ 2557 static GTY(()) rtx m68k_read_tp; 2558 2559 /* Return SYMBOL_REF for __m68k_read_tp. */ 2560 2561 static rtx 2562 m68k_get_m68k_read_tp (void) 2563 { 2564 if (m68k_read_tp == NULL_RTX) 2565 m68k_read_tp = init_one_libfunc ("__m68k_read_tp"); 2566 2567 return m68k_read_tp; 2568 } 2569 2570 /* Emit instruction sequence that calls __m68k_read_tp. 2571 A pseudo register with result of __m68k_read_tp call is returned. */ 2572 2573 static rtx 2574 m68k_call_m68k_read_tp (void) 2575 { 2576 rtx a0; 2577 rtx eqv; 2578 rtx_insn *insns; 2579 rtx dest; 2580 2581 start_sequence (); 2582 2583 /* __m68k_read_tp() is not a libcall, but emitting a libcall_value 2584 is the simpliest way of generating a call. The difference between 2585 __m68k_read_tp() and libcall is that the result is returned in D0 2586 instead of A0. To workaround this, we use m68k_libcall_value_in_a0_p 2587 which temporarily switches returning the result to A0. */ 2588 2589 /* Emit the call sequence. */ 2590 m68k_libcall_value_in_a0_p = true; 2591 a0 = emit_library_call_value (m68k_get_m68k_read_tp (), NULL_RTX, LCT_PURE, 2592 Pmode, 0); 2593 m68k_libcall_value_in_a0_p = false; 2594 insns = get_insns (); 2595 end_sequence (); 2596 2597 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to 2598 share the m68k_read_tp result with other IE/LE model accesses. */ 2599 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const1_rtx), UNSPEC_RELOC32); 2600 2601 gcc_assert (can_create_pseudo_p ()); 2602 dest = gen_reg_rtx (Pmode); 2603 emit_libcall_block (insns, dest, a0, eqv); 2604 2605 return dest; 2606 } 2607 2608 /* Return a legitimized address for accessing TLS SYMBOL_REF X. 2609 For explanations on instructions sequences see TLS/NPTL ABI for m68k and 2610 ColdFire. */ 2611 2612 rtx 2613 m68k_legitimize_tls_address (rtx orig) 2614 { 2615 switch (SYMBOL_REF_TLS_MODEL (orig)) 2616 { 2617 case TLS_MODEL_GLOBAL_DYNAMIC: 2618 orig = m68k_call_tls_get_addr (orig, orig, RELOC_TLSGD); 2619 break; 2620 2621 case TLS_MODEL_LOCAL_DYNAMIC: 2622 { 2623 rtx eqv; 2624 rtx a0; 2625 rtx x; 2626 2627 /* Attach a unique REG_EQUIV, to allow the RTL optimizers to 2628 share the LDM result with other LD model accesses. */ 2629 eqv = gen_rtx_UNSPEC (Pmode, gen_rtvec (1, const0_rtx), 2630 UNSPEC_RELOC32); 2631 2632 a0 = m68k_call_tls_get_addr (orig, eqv, RELOC_TLSLDM); 2633 2634 x = m68k_wrap_symbol (orig, RELOC_TLSLDO, a0, NULL_RTX); 2635 2636 if (can_create_pseudo_p ()) 2637 x = m68k_move_to_reg (x, orig, NULL_RTX); 2638 2639 orig = x; 2640 break; 2641 } 2642 2643 case TLS_MODEL_INITIAL_EXEC: 2644 { 2645 rtx a0; 2646 rtx x; 2647 2648 a0 = m68k_call_m68k_read_tp (); 2649 2650 x = m68k_wrap_symbol_into_got_ref (orig, RELOC_TLSIE, NULL_RTX); 2651 x = gen_rtx_PLUS (Pmode, x, a0); 2652 2653 if (can_create_pseudo_p ()) 2654 x = m68k_move_to_reg (x, orig, NULL_RTX); 2655 2656 orig = x; 2657 break; 2658 } 2659 2660 case TLS_MODEL_LOCAL_EXEC: 2661 { 2662 rtx a0; 2663 rtx x; 2664 2665 a0 = m68k_call_m68k_read_tp (); 2666 2667 x = m68k_wrap_symbol (orig, RELOC_TLSLE, a0, NULL_RTX); 2668 2669 if (can_create_pseudo_p ()) 2670 x = m68k_move_to_reg (x, orig, NULL_RTX); 2671 2672 orig = x; 2673 break; 2674 } 2675 2676 default: 2677 gcc_unreachable (); 2678 } 2679 2680 return orig; 2681 } 2682 2683 /* Return true if X is a TLS symbol. */ 2684 2685 static bool 2686 m68k_tls_symbol_p (rtx x) 2687 { 2688 if (!TARGET_HAVE_TLS) 2689 return false; 2690 2691 if (GET_CODE (x) != SYMBOL_REF) 2692 return false; 2693 2694 return SYMBOL_REF_TLS_MODEL (x) != 0; 2695 } 2696 2697 /* If !LEGITIMATE_P, return true if X is a TLS symbol reference, 2698 though illegitimate one. 2699 If LEGITIMATE_P, return true if X is a legitimate TLS symbol reference. */ 2700 2701 bool 2702 m68k_tls_reference_p (rtx x, bool legitimate_p) 2703 { 2704 if (!TARGET_HAVE_TLS) 2705 return false; 2706 2707 if (!legitimate_p) 2708 { 2709 subrtx_var_iterator::array_type array; 2710 FOR_EACH_SUBRTX_VAR (iter, array, x, ALL) 2711 { 2712 rtx x = *iter; 2713 2714 /* Note: this is not the same as m68k_tls_symbol_p. */ 2715 if (GET_CODE (x) == SYMBOL_REF && SYMBOL_REF_TLS_MODEL (x) != 0) 2716 return true; 2717 2718 /* Don't recurse into legitimate TLS references. */ 2719 if (m68k_tls_reference_p (x, true)) 2720 iter.skip_subrtxes (); 2721 } 2722 return false; 2723 } 2724 else 2725 { 2726 enum m68k_reloc reloc = RELOC_GOT; 2727 2728 return (m68k_unwrap_symbol_1 (x, true, &reloc) != x 2729 && TLS_RELOC_P (reloc)); 2730 } 2731 } 2732 2733 2734 2735 #define USE_MOVQ(i) ((unsigned) ((i) + 128) <= 255) 2736 2737 /* Return the type of move that should be used for integer I. */ 2738 2739 M68K_CONST_METHOD 2740 m68k_const_method (HOST_WIDE_INT i) 2741 { 2742 unsigned u; 2743 2744 if (USE_MOVQ (i)) 2745 return MOVQ; 2746 2747 /* The ColdFire doesn't have byte or word operations. */ 2748 /* FIXME: This may not be useful for the m68060 either. */ 2749 if (!TARGET_COLDFIRE) 2750 { 2751 /* if -256 < N < 256 but N is not in range for a moveq 2752 N^ff will be, so use moveq #N^ff, dreg; not.b dreg. */ 2753 if (USE_MOVQ (i ^ 0xff)) 2754 return NOTB; 2755 /* Likewise, try with not.w */ 2756 if (USE_MOVQ (i ^ 0xffff)) 2757 return NOTW; 2758 /* This is the only value where neg.w is useful */ 2759 if (i == -65408) 2760 return NEGW; 2761 } 2762 2763 /* Try also with swap. */ 2764 u = i; 2765 if (USE_MOVQ ((u >> 16) | (u << 16))) 2766 return SWAP; 2767 2768 if (TARGET_ISAB) 2769 { 2770 /* Try using MVZ/MVS with an immediate value to load constants. */ 2771 if (i >= 0 && i <= 65535) 2772 return MVZ; 2773 if (i >= -32768 && i <= 32767) 2774 return MVS; 2775 } 2776 2777 /* Otherwise, use move.l */ 2778 return MOVL; 2779 } 2780 2781 /* Return the cost of moving constant I into a data register. */ 2782 2783 static int 2784 const_int_cost (HOST_WIDE_INT i) 2785 { 2786 switch (m68k_const_method (i)) 2787 { 2788 case MOVQ: 2789 /* Constants between -128 and 127 are cheap due to moveq. */ 2790 return 0; 2791 case MVZ: 2792 case MVS: 2793 case NOTB: 2794 case NOTW: 2795 case NEGW: 2796 case SWAP: 2797 /* Constants easily generated by moveq + not.b/not.w/neg.w/swap. */ 2798 return 1; 2799 case MOVL: 2800 return 2; 2801 default: 2802 gcc_unreachable (); 2803 } 2804 } 2805 2806 static bool 2807 m68k_rtx_costs (rtx x, int code, int outer_code, int opno ATTRIBUTE_UNUSED, 2808 int *total, bool speed ATTRIBUTE_UNUSED) 2809 { 2810 switch (code) 2811 { 2812 case CONST_INT: 2813 /* Constant zero is super cheap due to clr instruction. */ 2814 if (x == const0_rtx) 2815 *total = 0; 2816 else 2817 *total = const_int_cost (INTVAL (x)); 2818 return true; 2819 2820 case CONST: 2821 case LABEL_REF: 2822 case SYMBOL_REF: 2823 *total = 3; 2824 return true; 2825 2826 case CONST_DOUBLE: 2827 /* Make 0.0 cheaper than other floating constants to 2828 encourage creating tstsf and tstdf insns. */ 2829 if (outer_code == COMPARE 2830 && (x == CONST0_RTX (SFmode) || x == CONST0_RTX (DFmode))) 2831 *total = 4; 2832 else 2833 *total = 5; 2834 return true; 2835 2836 /* These are vaguely right for a 68020. */ 2837 /* The costs for long multiply have been adjusted to work properly 2838 in synth_mult on the 68020, relative to an average of the time 2839 for add and the time for shift, taking away a little more because 2840 sometimes move insns are needed. */ 2841 /* div?.w is relatively cheaper on 68000 counted in COSTS_N_INSNS 2842 terms. */ 2843 #define MULL_COST \ 2844 (TUNE_68060 ? 2 \ 2845 : TUNE_68040 ? 5 \ 2846 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \ 2847 : (TUNE_CFV2 && TUNE_MAC) ? 4 \ 2848 : TUNE_CFV2 ? 8 \ 2849 : TARGET_COLDFIRE ? 3 : 13) 2850 2851 #define MULW_COST \ 2852 (TUNE_68060 ? 2 \ 2853 : TUNE_68040 ? 3 \ 2854 : TUNE_68000_10 ? 5 \ 2855 : (TUNE_CFV2 && TUNE_EMAC) ? 3 \ 2856 : (TUNE_CFV2 && TUNE_MAC) ? 2 \ 2857 : TUNE_CFV2 ? 8 \ 2858 : TARGET_COLDFIRE ? 2 : 8) 2859 2860 #define DIVW_COST \ 2861 (TARGET_CF_HWDIV ? 11 \ 2862 : TUNE_68000_10 || TARGET_COLDFIRE ? 12 : 27) 2863 2864 case PLUS: 2865 /* An lea costs about three times as much as a simple add. */ 2866 if (GET_MODE (x) == SImode 2867 && GET_CODE (XEXP (x, 1)) == REG 2868 && GET_CODE (XEXP (x, 0)) == MULT 2869 && GET_CODE (XEXP (XEXP (x, 0), 0)) == REG 2870 && GET_CODE (XEXP (XEXP (x, 0), 1)) == CONST_INT 2871 && (INTVAL (XEXP (XEXP (x, 0), 1)) == 2 2872 || INTVAL (XEXP (XEXP (x, 0), 1)) == 4 2873 || INTVAL (XEXP (XEXP (x, 0), 1)) == 8)) 2874 { 2875 /* lea an@(dx:l:i),am */ 2876 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 2 : 3); 2877 return true; 2878 } 2879 return false; 2880 2881 case ASHIFT: 2882 case ASHIFTRT: 2883 case LSHIFTRT: 2884 if (TUNE_68060) 2885 { 2886 *total = COSTS_N_INSNS(1); 2887 return true; 2888 } 2889 if (TUNE_68000_10) 2890 { 2891 if (GET_CODE (XEXP (x, 1)) == CONST_INT) 2892 { 2893 if (INTVAL (XEXP (x, 1)) < 16) 2894 *total = COSTS_N_INSNS (2) + INTVAL (XEXP (x, 1)) / 2; 2895 else 2896 /* We're using clrw + swap for these cases. */ 2897 *total = COSTS_N_INSNS (4) + (INTVAL (XEXP (x, 1)) - 16) / 2; 2898 } 2899 else 2900 *total = COSTS_N_INSNS (10); /* Worst case. */ 2901 return true; 2902 } 2903 /* A shift by a big integer takes an extra instruction. */ 2904 if (GET_CODE (XEXP (x, 1)) == CONST_INT 2905 && (INTVAL (XEXP (x, 1)) == 16)) 2906 { 2907 *total = COSTS_N_INSNS (2); /* clrw;swap */ 2908 return true; 2909 } 2910 if (GET_CODE (XEXP (x, 1)) == CONST_INT 2911 && !(INTVAL (XEXP (x, 1)) > 0 2912 && INTVAL (XEXP (x, 1)) <= 8)) 2913 { 2914 *total = COSTS_N_INSNS (TARGET_COLDFIRE ? 1 : 3); /* lsr #i,dn */ 2915 return true; 2916 } 2917 return false; 2918 2919 case MULT: 2920 if ((GET_CODE (XEXP (x, 0)) == ZERO_EXTEND 2921 || GET_CODE (XEXP (x, 0)) == SIGN_EXTEND) 2922 && GET_MODE (x) == SImode) 2923 *total = COSTS_N_INSNS (MULW_COST); 2924 else if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) 2925 *total = COSTS_N_INSNS (MULW_COST); 2926 else 2927 *total = COSTS_N_INSNS (MULL_COST); 2928 return true; 2929 2930 case DIV: 2931 case UDIV: 2932 case MOD: 2933 case UMOD: 2934 if (GET_MODE (x) == QImode || GET_MODE (x) == HImode) 2935 *total = COSTS_N_INSNS (DIVW_COST); /* div.w */ 2936 else if (TARGET_CF_HWDIV) 2937 *total = COSTS_N_INSNS (18); 2938 else 2939 *total = COSTS_N_INSNS (43); /* div.l */ 2940 return true; 2941 2942 case ZERO_EXTRACT: 2943 if (outer_code == COMPARE) 2944 *total = 0; 2945 return false; 2946 2947 default: 2948 return false; 2949 } 2950 } 2951 2952 /* Return an instruction to move CONST_INT OPERANDS[1] into data register 2953 OPERANDS[0]. */ 2954 2955 static const char * 2956 output_move_const_into_data_reg (rtx *operands) 2957 { 2958 HOST_WIDE_INT i; 2959 2960 i = INTVAL (operands[1]); 2961 switch (m68k_const_method (i)) 2962 { 2963 case MVZ: 2964 return "mvzw %1,%0"; 2965 case MVS: 2966 return "mvsw %1,%0"; 2967 case MOVQ: 2968 return "moveq %1,%0"; 2969 case NOTB: 2970 CC_STATUS_INIT; 2971 operands[1] = GEN_INT (i ^ 0xff); 2972 return "moveq %1,%0\n\tnot%.b %0"; 2973 case NOTW: 2974 CC_STATUS_INIT; 2975 operands[1] = GEN_INT (i ^ 0xffff); 2976 return "moveq %1,%0\n\tnot%.w %0"; 2977 case NEGW: 2978 CC_STATUS_INIT; 2979 return "moveq #-128,%0\n\tneg%.w %0"; 2980 case SWAP: 2981 { 2982 unsigned u = i; 2983 2984 operands[1] = GEN_INT ((u << 16) | (u >> 16)); 2985 return "moveq %1,%0\n\tswap %0"; 2986 } 2987 case MOVL: 2988 return "move%.l %1,%0"; 2989 default: 2990 gcc_unreachable (); 2991 } 2992 } 2993 2994 /* Return true if I can be handled by ISA B's mov3q instruction. */ 2995 2996 bool 2997 valid_mov3q_const (HOST_WIDE_INT i) 2998 { 2999 return TARGET_ISAB && (i == -1 || IN_RANGE (i, 1, 7)); 3000 } 3001 3002 /* Return an instruction to move CONST_INT OPERANDS[1] into OPERANDS[0]. 3003 I is the value of OPERANDS[1]. */ 3004 3005 static const char * 3006 output_move_simode_const (rtx *operands) 3007 { 3008 rtx dest; 3009 HOST_WIDE_INT src; 3010 3011 dest = operands[0]; 3012 src = INTVAL (operands[1]); 3013 if (src == 0 3014 && (DATA_REG_P (dest) || MEM_P (dest)) 3015 /* clr insns on 68000 read before writing. */ 3016 && ((TARGET_68010 || TARGET_COLDFIRE) 3017 || !(MEM_P (dest) && MEM_VOLATILE_P (dest)))) 3018 return "clr%.l %0"; 3019 else if (GET_MODE (dest) == SImode && valid_mov3q_const (src)) 3020 return "mov3q%.l %1,%0"; 3021 else if (src == 0 && ADDRESS_REG_P (dest)) 3022 return "sub%.l %0,%0"; 3023 else if (DATA_REG_P (dest)) 3024 return output_move_const_into_data_reg (operands); 3025 else if (ADDRESS_REG_P (dest) && IN_RANGE (src, -0x8000, 0x7fff)) 3026 { 3027 if (valid_mov3q_const (src)) 3028 return "mov3q%.l %1,%0"; 3029 return "move%.w %1,%0"; 3030 } 3031 else if (MEM_P (dest) 3032 && GET_CODE (XEXP (dest, 0)) == PRE_DEC 3033 && REGNO (XEXP (XEXP (dest, 0), 0)) == STACK_POINTER_REGNUM 3034 && IN_RANGE (src, -0x8000, 0x7fff)) 3035 { 3036 if (valid_mov3q_const (src)) 3037 return "mov3q%.l %1,%-"; 3038 return "pea %a1"; 3039 } 3040 return "move%.l %1,%0"; 3041 } 3042 3043 const char * 3044 output_move_simode (rtx *operands) 3045 { 3046 if (GET_CODE (operands[1]) == CONST_INT) 3047 return output_move_simode_const (operands); 3048 else if ((GET_CODE (operands[1]) == SYMBOL_REF 3049 || GET_CODE (operands[1]) == CONST) 3050 && push_operand (operands[0], SImode)) 3051 return "pea %a1"; 3052 else if ((GET_CODE (operands[1]) == SYMBOL_REF 3053 || GET_CODE (operands[1]) == CONST) 3054 && ADDRESS_REG_P (operands[0])) 3055 return "lea %a1,%0"; 3056 return "move%.l %1,%0"; 3057 } 3058 3059 const char * 3060 output_move_himode (rtx *operands) 3061 { 3062 if (GET_CODE (operands[1]) == CONST_INT) 3063 { 3064 if (operands[1] == const0_rtx 3065 && (DATA_REG_P (operands[0]) 3066 || GET_CODE (operands[0]) == MEM) 3067 /* clr insns on 68000 read before writing. */ 3068 && ((TARGET_68010 || TARGET_COLDFIRE) 3069 || !(GET_CODE (operands[0]) == MEM 3070 && MEM_VOLATILE_P (operands[0])))) 3071 return "clr%.w %0"; 3072 else if (operands[1] == const0_rtx 3073 && ADDRESS_REG_P (operands[0])) 3074 return "sub%.l %0,%0"; 3075 else if (DATA_REG_P (operands[0]) 3076 && INTVAL (operands[1]) < 128 3077 && INTVAL (operands[1]) >= -128) 3078 return "moveq %1,%0"; 3079 else if (INTVAL (operands[1]) < 0x8000 3080 && INTVAL (operands[1]) >= -0x8000) 3081 return "move%.w %1,%0"; 3082 } 3083 else if (CONSTANT_P (operands[1])) 3084 return "move%.l %1,%0"; 3085 return "move%.w %1,%0"; 3086 } 3087 3088 const char * 3089 output_move_qimode (rtx *operands) 3090 { 3091 /* 68k family always modifies the stack pointer by at least 2, even for 3092 byte pushes. The 5200 (ColdFire) does not do this. */ 3093 3094 /* This case is generated by pushqi1 pattern now. */ 3095 gcc_assert (!(GET_CODE (operands[0]) == MEM 3096 && GET_CODE (XEXP (operands[0], 0)) == PRE_DEC 3097 && XEXP (XEXP (operands[0], 0), 0) == stack_pointer_rtx 3098 && ! ADDRESS_REG_P (operands[1]) 3099 && ! TARGET_COLDFIRE)); 3100 3101 /* clr and st insns on 68000 read before writing. */ 3102 if (!ADDRESS_REG_P (operands[0]) 3103 && ((TARGET_68010 || TARGET_COLDFIRE) 3104 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) 3105 { 3106 if (operands[1] == const0_rtx) 3107 return "clr%.b %0"; 3108 if ((!TARGET_COLDFIRE || DATA_REG_P (operands[0])) 3109 && GET_CODE (operands[1]) == CONST_INT 3110 && (INTVAL (operands[1]) & 255) == 255) 3111 { 3112 CC_STATUS_INIT; 3113 return "st %0"; 3114 } 3115 } 3116 if (GET_CODE (operands[1]) == CONST_INT 3117 && DATA_REG_P (operands[0]) 3118 && INTVAL (operands[1]) < 128 3119 && INTVAL (operands[1]) >= -128) 3120 return "moveq %1,%0"; 3121 if (operands[1] == const0_rtx && ADDRESS_REG_P (operands[0])) 3122 return "sub%.l %0,%0"; 3123 if (GET_CODE (operands[1]) != CONST_INT && CONSTANT_P (operands[1])) 3124 return "move%.l %1,%0"; 3125 /* 68k family (including the 5200 ColdFire) does not support byte moves to 3126 from address registers. */ 3127 if (ADDRESS_REG_P (operands[0]) || ADDRESS_REG_P (operands[1])) 3128 return "move%.w %1,%0"; 3129 return "move%.b %1,%0"; 3130 } 3131 3132 const char * 3133 output_move_stricthi (rtx *operands) 3134 { 3135 if (operands[1] == const0_rtx 3136 /* clr insns on 68000 read before writing. */ 3137 && ((TARGET_68010 || TARGET_COLDFIRE) 3138 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) 3139 return "clr%.w %0"; 3140 return "move%.w %1,%0"; 3141 } 3142 3143 const char * 3144 output_move_strictqi (rtx *operands) 3145 { 3146 if (operands[1] == const0_rtx 3147 /* clr insns on 68000 read before writing. */ 3148 && ((TARGET_68010 || TARGET_COLDFIRE) 3149 || !(GET_CODE (operands[0]) == MEM && MEM_VOLATILE_P (operands[0])))) 3150 return "clr%.b %0"; 3151 return "move%.b %1,%0"; 3152 } 3153 3154 /* Return the best assembler insn template 3155 for moving operands[1] into operands[0] as a fullword. */ 3156 3157 static const char * 3158 singlemove_string (rtx *operands) 3159 { 3160 if (GET_CODE (operands[1]) == CONST_INT) 3161 return output_move_simode_const (operands); 3162 return "move%.l %1,%0"; 3163 } 3164 3165 3166 /* Output assembler or rtl code to perform a doubleword move insn 3167 with operands OPERANDS. 3168 Pointers to 3 helper functions should be specified: 3169 HANDLE_REG_ADJUST to adjust a register by a small value, 3170 HANDLE_COMPADR to compute an address and 3171 HANDLE_MOVSI to move 4 bytes. */ 3172 3173 static void 3174 handle_move_double (rtx operands[2], 3175 void (*handle_reg_adjust) (rtx, int), 3176 void (*handle_compadr) (rtx [2]), 3177 void (*handle_movsi) (rtx [2])) 3178 { 3179 enum 3180 { 3181 REGOP, OFFSOP, MEMOP, PUSHOP, POPOP, CNSTOP, RNDOP 3182 } optype0, optype1; 3183 rtx latehalf[2]; 3184 rtx middlehalf[2]; 3185 rtx xops[2]; 3186 rtx addreg0 = 0, addreg1 = 0; 3187 int dest_overlapped_low = 0; 3188 int size = GET_MODE_SIZE (GET_MODE (operands[0])); 3189 3190 middlehalf[0] = 0; 3191 middlehalf[1] = 0; 3192 3193 /* First classify both operands. */ 3194 3195 if (REG_P (operands[0])) 3196 optype0 = REGOP; 3197 else if (offsettable_memref_p (operands[0])) 3198 optype0 = OFFSOP; 3199 else if (GET_CODE (XEXP (operands[0], 0)) == POST_INC) 3200 optype0 = POPOP; 3201 else if (GET_CODE (XEXP (operands[0], 0)) == PRE_DEC) 3202 optype0 = PUSHOP; 3203 else if (GET_CODE (operands[0]) == MEM) 3204 optype0 = MEMOP; 3205 else 3206 optype0 = RNDOP; 3207 3208 if (REG_P (operands[1])) 3209 optype1 = REGOP; 3210 else if (CONSTANT_P (operands[1])) 3211 optype1 = CNSTOP; 3212 else if (offsettable_memref_p (operands[1])) 3213 optype1 = OFFSOP; 3214 else if (GET_CODE (XEXP (operands[1], 0)) == POST_INC) 3215 optype1 = POPOP; 3216 else if (GET_CODE (XEXP (operands[1], 0)) == PRE_DEC) 3217 optype1 = PUSHOP; 3218 else if (GET_CODE (operands[1]) == MEM) 3219 optype1 = MEMOP; 3220 else 3221 optype1 = RNDOP; 3222 3223 /* Check for the cases that the operand constraints are not supposed 3224 to allow to happen. Generating code for these cases is 3225 painful. */ 3226 gcc_assert (optype0 != RNDOP && optype1 != RNDOP); 3227 3228 /* If one operand is decrementing and one is incrementing 3229 decrement the former register explicitly 3230 and change that operand into ordinary indexing. */ 3231 3232 if (optype0 == PUSHOP && optype1 == POPOP) 3233 { 3234 operands[0] = XEXP (XEXP (operands[0], 0), 0); 3235 3236 handle_reg_adjust (operands[0], -size); 3237 3238 if (GET_MODE (operands[1]) == XFmode) 3239 operands[0] = gen_rtx_MEM (XFmode, operands[0]); 3240 else if (GET_MODE (operands[0]) == DFmode) 3241 operands[0] = gen_rtx_MEM (DFmode, operands[0]); 3242 else 3243 operands[0] = gen_rtx_MEM (DImode, operands[0]); 3244 optype0 = OFFSOP; 3245 } 3246 if (optype0 == POPOP && optype1 == PUSHOP) 3247 { 3248 operands[1] = XEXP (XEXP (operands[1], 0), 0); 3249 3250 handle_reg_adjust (operands[1], -size); 3251 3252 if (GET_MODE (operands[1]) == XFmode) 3253 operands[1] = gen_rtx_MEM (XFmode, operands[1]); 3254 else if (GET_MODE (operands[1]) == DFmode) 3255 operands[1] = gen_rtx_MEM (DFmode, operands[1]); 3256 else 3257 operands[1] = gen_rtx_MEM (DImode, operands[1]); 3258 optype1 = OFFSOP; 3259 } 3260 3261 /* If an operand is an unoffsettable memory ref, find a register 3262 we can increment temporarily to make it refer to the second word. */ 3263 3264 if (optype0 == MEMOP) 3265 addreg0 = find_addr_reg (XEXP (operands[0], 0)); 3266 3267 if (optype1 == MEMOP) 3268 addreg1 = find_addr_reg (XEXP (operands[1], 0)); 3269 3270 /* Ok, we can do one word at a time. 3271 Normally we do the low-numbered word first, 3272 but if either operand is autodecrementing then we 3273 do the high-numbered word first. 3274 3275 In either case, set up in LATEHALF the operands to use 3276 for the high-numbered word and in some cases alter the 3277 operands in OPERANDS to be suitable for the low-numbered word. */ 3278 3279 if (size == 12) 3280 { 3281 if (optype0 == REGOP) 3282 { 3283 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 2); 3284 middlehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 3285 } 3286 else if (optype0 == OFFSOP) 3287 { 3288 middlehalf[0] = adjust_address (operands[0], SImode, 4); 3289 latehalf[0] = adjust_address (operands[0], SImode, size - 4); 3290 } 3291 else 3292 { 3293 middlehalf[0] = adjust_address (operands[0], SImode, 0); 3294 latehalf[0] = adjust_address (operands[0], SImode, 0); 3295 } 3296 3297 if (optype1 == REGOP) 3298 { 3299 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 2); 3300 middlehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 3301 } 3302 else if (optype1 == OFFSOP) 3303 { 3304 middlehalf[1] = adjust_address (operands[1], SImode, 4); 3305 latehalf[1] = adjust_address (operands[1], SImode, size - 4); 3306 } 3307 else if (optype1 == CNSTOP) 3308 { 3309 if (GET_CODE (operands[1]) == CONST_DOUBLE) 3310 { 3311 REAL_VALUE_TYPE r; 3312 long l[3]; 3313 3314 REAL_VALUE_FROM_CONST_DOUBLE (r, operands[1]); 3315 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); 3316 operands[1] = GEN_INT (l[0]); 3317 middlehalf[1] = GEN_INT (l[1]); 3318 latehalf[1] = GEN_INT (l[2]); 3319 } 3320 else 3321 { 3322 /* No non-CONST_DOUBLE constant should ever appear 3323 here. */ 3324 gcc_assert (!CONSTANT_P (operands[1])); 3325 } 3326 } 3327 else 3328 { 3329 middlehalf[1] = adjust_address (operands[1], SImode, 0); 3330 latehalf[1] = adjust_address (operands[1], SImode, 0); 3331 } 3332 } 3333 else 3334 /* size is not 12: */ 3335 { 3336 if (optype0 == REGOP) 3337 latehalf[0] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1); 3338 else if (optype0 == OFFSOP) 3339 latehalf[0] = adjust_address (operands[0], SImode, size - 4); 3340 else 3341 latehalf[0] = adjust_address (operands[0], SImode, 0); 3342 3343 if (optype1 == REGOP) 3344 latehalf[1] = gen_rtx_REG (SImode, REGNO (operands[1]) + 1); 3345 else if (optype1 == OFFSOP) 3346 latehalf[1] = adjust_address (operands[1], SImode, size - 4); 3347 else if (optype1 == CNSTOP) 3348 split_double (operands[1], &operands[1], &latehalf[1]); 3349 else 3350 latehalf[1] = adjust_address (operands[1], SImode, 0); 3351 } 3352 3353 /* If insn is effectively movd N(REG),-(REG) then we will do the high 3354 word first. We should use the adjusted operand 1 (which is N+4(REG)) 3355 for the low word as well, to compensate for the first decrement of 3356 REG. */ 3357 if (optype0 == PUSHOP 3358 && reg_overlap_mentioned_p (XEXP (XEXP (operands[0], 0), 0), operands[1])) 3359 operands[1] = middlehalf[1] = latehalf[1]; 3360 3361 /* For (set (reg:DI N) (mem:DI ... (reg:SI N) ...)), 3362 if the upper part of reg N does not appear in the MEM, arrange to 3363 emit the move late-half first. Otherwise, compute the MEM address 3364 into the upper part of N and use that as a pointer to the memory 3365 operand. */ 3366 if (optype0 == REGOP 3367 && (optype1 == OFFSOP || optype1 == MEMOP)) 3368 { 3369 rtx testlow = gen_rtx_REG (SImode, REGNO (operands[0])); 3370 3371 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) 3372 && reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) 3373 { 3374 /* If both halves of dest are used in the src memory address, 3375 compute the address into latehalf of dest. 3376 Note that this can't happen if the dest is two data regs. */ 3377 compadr: 3378 xops[0] = latehalf[0]; 3379 xops[1] = XEXP (operands[1], 0); 3380 3381 handle_compadr (xops); 3382 if (GET_MODE (operands[1]) == XFmode) 3383 { 3384 operands[1] = gen_rtx_MEM (XFmode, latehalf[0]); 3385 middlehalf[1] = adjust_address (operands[1], DImode, size - 8); 3386 latehalf[1] = adjust_address (operands[1], DImode, size - 4); 3387 } 3388 else 3389 { 3390 operands[1] = gen_rtx_MEM (DImode, latehalf[0]); 3391 latehalf[1] = adjust_address (operands[1], DImode, size - 4); 3392 } 3393 } 3394 else if (size == 12 3395 && reg_overlap_mentioned_p (middlehalf[0], 3396 XEXP (operands[1], 0))) 3397 { 3398 /* Check for two regs used by both source and dest. 3399 Note that this can't happen if the dest is all data regs. 3400 It can happen if the dest is d6, d7, a0. 3401 But in that case, latehalf is an addr reg, so 3402 the code at compadr does ok. */ 3403 3404 if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0)) 3405 || reg_overlap_mentioned_p (latehalf[0], XEXP (operands[1], 0))) 3406 goto compadr; 3407 3408 /* JRV says this can't happen: */ 3409 gcc_assert (!addreg0 && !addreg1); 3410 3411 /* Only the middle reg conflicts; simply put it last. */ 3412 handle_movsi (operands); 3413 handle_movsi (latehalf); 3414 handle_movsi (middlehalf); 3415 3416 return; 3417 } 3418 else if (reg_overlap_mentioned_p (testlow, XEXP (operands[1], 0))) 3419 /* If the low half of dest is mentioned in the source memory 3420 address, the arrange to emit the move late half first. */ 3421 dest_overlapped_low = 1; 3422 } 3423 3424 /* If one or both operands autodecrementing, 3425 do the two words, high-numbered first. */ 3426 3427 /* Likewise, the first move would clobber the source of the second one, 3428 do them in the other order. This happens only for registers; 3429 such overlap can't happen in memory unless the user explicitly 3430 sets it up, and that is an undefined circumstance. */ 3431 3432 if (optype0 == PUSHOP || optype1 == PUSHOP 3433 || (optype0 == REGOP && optype1 == REGOP 3434 && ((middlehalf[1] && REGNO (operands[0]) == REGNO (middlehalf[1])) 3435 || REGNO (operands[0]) == REGNO (latehalf[1]))) 3436 || dest_overlapped_low) 3437 { 3438 /* Make any unoffsettable addresses point at high-numbered word. */ 3439 if (addreg0) 3440 handle_reg_adjust (addreg0, size - 4); 3441 if (addreg1) 3442 handle_reg_adjust (addreg1, size - 4); 3443 3444 /* Do that word. */ 3445 handle_movsi (latehalf); 3446 3447 /* Undo the adds we just did. */ 3448 if (addreg0) 3449 handle_reg_adjust (addreg0, -4); 3450 if (addreg1) 3451 handle_reg_adjust (addreg1, -4); 3452 3453 if (size == 12) 3454 { 3455 handle_movsi (middlehalf); 3456 3457 if (addreg0) 3458 handle_reg_adjust (addreg0, -4); 3459 if (addreg1) 3460 handle_reg_adjust (addreg1, -4); 3461 } 3462 3463 /* Do low-numbered word. */ 3464 3465 handle_movsi (operands); 3466 return; 3467 } 3468 3469 /* Normal case: do the two words, low-numbered first. */ 3470 3471 m68k_final_prescan_insn (NULL, operands, 2); 3472 handle_movsi (operands); 3473 3474 /* Do the middle one of the three words for long double */ 3475 if (size == 12) 3476 { 3477 if (addreg0) 3478 handle_reg_adjust (addreg0, 4); 3479 if (addreg1) 3480 handle_reg_adjust (addreg1, 4); 3481 3482 m68k_final_prescan_insn (NULL, middlehalf, 2); 3483 handle_movsi (middlehalf); 3484 } 3485 3486 /* Make any unoffsettable addresses point at high-numbered word. */ 3487 if (addreg0) 3488 handle_reg_adjust (addreg0, 4); 3489 if (addreg1) 3490 handle_reg_adjust (addreg1, 4); 3491 3492 /* Do that word. */ 3493 m68k_final_prescan_insn (NULL, latehalf, 2); 3494 handle_movsi (latehalf); 3495 3496 /* Undo the adds we just did. */ 3497 if (addreg0) 3498 handle_reg_adjust (addreg0, -(size - 4)); 3499 if (addreg1) 3500 handle_reg_adjust (addreg1, -(size - 4)); 3501 3502 return; 3503 } 3504 3505 /* Output assembler code to adjust REG by N. */ 3506 static void 3507 output_reg_adjust (rtx reg, int n) 3508 { 3509 const char *s; 3510 3511 gcc_assert (GET_MODE (reg) == SImode 3512 && -12 <= n && n != 0 && n <= 12); 3513 3514 switch (n) 3515 { 3516 case 12: 3517 s = "add%.l #12,%0"; 3518 break; 3519 3520 case 8: 3521 s = "addq%.l #8,%0"; 3522 break; 3523 3524 case 4: 3525 s = "addq%.l #4,%0"; 3526 break; 3527 3528 case -12: 3529 s = "sub%.l #12,%0"; 3530 break; 3531 3532 case -8: 3533 s = "subq%.l #8,%0"; 3534 break; 3535 3536 case -4: 3537 s = "subq%.l #4,%0"; 3538 break; 3539 3540 default: 3541 gcc_unreachable (); 3542 s = NULL; 3543 } 3544 3545 output_asm_insn (s, ®); 3546 } 3547 3548 /* Emit rtl code to adjust REG by N. */ 3549 static void 3550 emit_reg_adjust (rtx reg1, int n) 3551 { 3552 rtx reg2; 3553 3554 gcc_assert (GET_MODE (reg1) == SImode 3555 && -12 <= n && n != 0 && n <= 12); 3556 3557 reg1 = copy_rtx (reg1); 3558 reg2 = copy_rtx (reg1); 3559 3560 if (n < 0) 3561 emit_insn (gen_subsi3 (reg1, reg2, GEN_INT (-n))); 3562 else if (n > 0) 3563 emit_insn (gen_addsi3 (reg1, reg2, GEN_INT (n))); 3564 else 3565 gcc_unreachable (); 3566 } 3567 3568 /* Output assembler to load address OPERANDS[0] to register OPERANDS[1]. */ 3569 static void 3570 output_compadr (rtx operands[2]) 3571 { 3572 output_asm_insn ("lea %a1,%0", operands); 3573 } 3574 3575 /* Output the best assembler insn for moving operands[1] into operands[0] 3576 as a fullword. */ 3577 static void 3578 output_movsi (rtx operands[2]) 3579 { 3580 output_asm_insn (singlemove_string (operands), operands); 3581 } 3582 3583 /* Copy OP and change its mode to MODE. */ 3584 static rtx 3585 copy_operand (rtx op, machine_mode mode) 3586 { 3587 /* ??? This looks really ugly. There must be a better way 3588 to change a mode on the operand. */ 3589 if (GET_MODE (op) != VOIDmode) 3590 { 3591 if (REG_P (op)) 3592 op = gen_rtx_REG (mode, REGNO (op)); 3593 else 3594 { 3595 op = copy_rtx (op); 3596 PUT_MODE (op, mode); 3597 } 3598 } 3599 3600 return op; 3601 } 3602 3603 /* Emit rtl code for moving operands[1] into operands[0] as a fullword. */ 3604 static void 3605 emit_movsi (rtx operands[2]) 3606 { 3607 operands[0] = copy_operand (operands[0], SImode); 3608 operands[1] = copy_operand (operands[1], SImode); 3609 3610 emit_insn (gen_movsi (operands[0], operands[1])); 3611 } 3612 3613 /* Output assembler code to perform a doubleword move insn 3614 with operands OPERANDS. */ 3615 const char * 3616 output_move_double (rtx *operands) 3617 { 3618 handle_move_double (operands, 3619 output_reg_adjust, output_compadr, output_movsi); 3620 3621 return ""; 3622 } 3623 3624 /* Output rtl code to perform a doubleword move insn 3625 with operands OPERANDS. */ 3626 void 3627 m68k_emit_move_double (rtx operands[2]) 3628 { 3629 handle_move_double (operands, emit_reg_adjust, emit_movsi, emit_movsi); 3630 } 3631 3632 /* Ensure mode of ORIG, a REG rtx, is MODE. Returns either ORIG or a 3633 new rtx with the correct mode. */ 3634 3635 static rtx 3636 force_mode (machine_mode mode, rtx orig) 3637 { 3638 if (mode == GET_MODE (orig)) 3639 return orig; 3640 3641 if (REGNO (orig) >= FIRST_PSEUDO_REGISTER) 3642 abort (); 3643 3644 return gen_rtx_REG (mode, REGNO (orig)); 3645 } 3646 3647 static int 3648 fp_reg_operand (rtx op, machine_mode mode ATTRIBUTE_UNUSED) 3649 { 3650 return reg_renumber && FP_REG_P (op); 3651 } 3652 3653 /* Emit insns to move operands[1] into operands[0]. 3654 3655 Return 1 if we have written out everything that needs to be done to 3656 do the move. Otherwise, return 0 and the caller will emit the move 3657 normally. 3658 3659 Note SCRATCH_REG may not be in the proper mode depending on how it 3660 will be used. This routine is responsible for creating a new copy 3661 of SCRATCH_REG in the proper mode. */ 3662 3663 int 3664 emit_move_sequence (rtx *operands, machine_mode mode, rtx scratch_reg) 3665 { 3666 register rtx operand0 = operands[0]; 3667 register rtx operand1 = operands[1]; 3668 register rtx tem; 3669 3670 if (scratch_reg 3671 && reload_in_progress && GET_CODE (operand0) == REG 3672 && REGNO (operand0) >= FIRST_PSEUDO_REGISTER) 3673 operand0 = reg_equiv_mem (REGNO (operand0)); 3674 else if (scratch_reg 3675 && reload_in_progress && GET_CODE (operand0) == SUBREG 3676 && GET_CODE (SUBREG_REG (operand0)) == REG 3677 && REGNO (SUBREG_REG (operand0)) >= FIRST_PSEUDO_REGISTER) 3678 { 3679 /* We must not alter SUBREG_BYTE (operand0) since that would confuse 3680 the code which tracks sets/uses for delete_output_reload. */ 3681 rtx temp = gen_rtx_SUBREG (GET_MODE (operand0), 3682 reg_equiv_mem (REGNO (SUBREG_REG (operand0))), 3683 SUBREG_BYTE (operand0)); 3684 operand0 = alter_subreg (&temp, true); 3685 } 3686 3687 if (scratch_reg 3688 && reload_in_progress && GET_CODE (operand1) == REG 3689 && REGNO (operand1) >= FIRST_PSEUDO_REGISTER) 3690 operand1 = reg_equiv_mem (REGNO (operand1)); 3691 else if (scratch_reg 3692 && reload_in_progress && GET_CODE (operand1) == SUBREG 3693 && GET_CODE (SUBREG_REG (operand1)) == REG 3694 && REGNO (SUBREG_REG (operand1)) >= FIRST_PSEUDO_REGISTER) 3695 { 3696 /* We must not alter SUBREG_BYTE (operand0) since that would confuse 3697 the code which tracks sets/uses for delete_output_reload. */ 3698 rtx temp = gen_rtx_SUBREG (GET_MODE (operand1), 3699 reg_equiv_mem (REGNO (SUBREG_REG (operand1))), 3700 SUBREG_BYTE (operand1)); 3701 operand1 = alter_subreg (&temp, true); 3702 } 3703 3704 if (scratch_reg && reload_in_progress && GET_CODE (operand0) == MEM 3705 && ((tem = find_replacement (&XEXP (operand0, 0))) 3706 != XEXP (operand0, 0))) 3707 operand0 = gen_rtx_MEM (GET_MODE (operand0), tem); 3708 if (scratch_reg && reload_in_progress && GET_CODE (operand1) == MEM 3709 && ((tem = find_replacement (&XEXP (operand1, 0))) 3710 != XEXP (operand1, 0))) 3711 operand1 = gen_rtx_MEM (GET_MODE (operand1), tem); 3712 3713 /* Handle secondary reloads for loads/stores of FP registers where 3714 the address is symbolic by using the scratch register */ 3715 if (fp_reg_operand (operand0, mode) 3716 && ((GET_CODE (operand1) == MEM 3717 && ! memory_address_p (DFmode, XEXP (operand1, 0))) 3718 || ((GET_CODE (operand1) == SUBREG 3719 && GET_CODE (XEXP (operand1, 0)) == MEM 3720 && !memory_address_p (DFmode, XEXP (XEXP (operand1, 0), 0))))) 3721 && scratch_reg) 3722 { 3723 if (GET_CODE (operand1) == SUBREG) 3724 operand1 = XEXP (operand1, 0); 3725 3726 /* SCRATCH_REG will hold an address. We want 3727 it in SImode regardless of what mode it was originally given 3728 to us. */ 3729 scratch_reg = force_mode (SImode, scratch_reg); 3730 3731 /* D might not fit in 14 bits either; for such cases load D into 3732 scratch reg. */ 3733 if (!memory_address_p (Pmode, XEXP (operand1, 0))) 3734 { 3735 emit_move_insn (scratch_reg, XEXP (XEXP (operand1, 0), 1)); 3736 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand1, 0)), 3737 Pmode, 3738 XEXP (XEXP (operand1, 0), 0), 3739 scratch_reg)); 3740 } 3741 else 3742 emit_move_insn (scratch_reg, XEXP (operand1, 0)); 3743 emit_insn (gen_rtx_SET (VOIDmode, operand0, 3744 gen_rtx_MEM (mode, scratch_reg))); 3745 return 1; 3746 } 3747 else if (fp_reg_operand (operand1, mode) 3748 && ((GET_CODE (operand0) == MEM 3749 && ! memory_address_p (DFmode, XEXP (operand0, 0))) 3750 || ((GET_CODE (operand0) == SUBREG) 3751 && GET_CODE (XEXP (operand0, 0)) == MEM 3752 && !memory_address_p (DFmode, XEXP (XEXP (operand0, 0), 0)))) 3753 && scratch_reg) 3754 { 3755 if (GET_CODE (operand0) == SUBREG) 3756 operand0 = XEXP (operand0, 0); 3757 3758 /* SCRATCH_REG will hold an address and maybe the actual data. We want 3759 it in SIMODE regardless of what mode it was originally given 3760 to us. */ 3761 scratch_reg = force_mode (SImode, scratch_reg); 3762 3763 /* D might not fit in 14 bits either; for such cases load D into 3764 scratch reg. */ 3765 if (!memory_address_p (Pmode, XEXP (operand0, 0))) 3766 { 3767 emit_move_insn (scratch_reg, XEXP (XEXP (operand0, 0), 1)); 3768 emit_move_insn (scratch_reg, gen_rtx_fmt_ee (GET_CODE (XEXP (operand0, 3769 0)), 3770 Pmode, 3771 XEXP (XEXP (operand0, 0), 3772 0), 3773 scratch_reg)); 3774 } 3775 else 3776 emit_move_insn (scratch_reg, XEXP (operand0, 0)); 3777 emit_insn (gen_rtx_SET (VOIDmode, gen_rtx_MEM (mode, scratch_reg), 3778 operand1)); 3779 return 1; 3780 } 3781 /* Handle secondary reloads for loads of FP registers from constant 3782 expressions by forcing the constant into memory. 3783 3784 use scratch_reg to hold the address of the memory location. 3785 3786 The proper fix is to change PREFERRED_RELOAD_CLASS to return 3787 NO_REGS when presented with a const_int and an register class 3788 containing only FP registers. Doing so unfortunately creates 3789 more problems than it solves. Fix this for 2.5. */ 3790 else if (fp_reg_operand (operand0, mode) 3791 && CONSTANT_P (operand1) 3792 && scratch_reg) 3793 { 3794 rtx xoperands[2]; 3795 3796 /* SCRATCH_REG will hold an address and maybe the actual data. We want 3797 it in SIMODE regardless of what mode it was originally given 3798 to us. */ 3799 scratch_reg = force_mode (SImode, scratch_reg); 3800 3801 /* Force the constant into memory and put the address of the 3802 memory location into scratch_reg. */ 3803 xoperands[0] = scratch_reg; 3804 xoperands[1] = XEXP (force_const_mem (mode, operand1), 0); 3805 emit_insn (gen_rtx_SET (mode, scratch_reg, xoperands[1])); 3806 3807 /* Now load the destination register. */ 3808 emit_insn (gen_rtx_SET (mode, operand0, 3809 gen_rtx_MEM (mode, scratch_reg))); 3810 return 1; 3811 } 3812 3813 /* Now have insn-emit do whatever it normally does. */ 3814 return 0; 3815 } 3816 3817 /* Split one or more DImode RTL references into pairs of SImode 3818 references. The RTL can be REG, offsettable MEM, integer constant, or 3819 CONST_DOUBLE. "operands" is a pointer to an array of DImode RTL to 3820 split and "num" is its length. lo_half and hi_half are output arrays 3821 that parallel "operands". */ 3822 3823 void 3824 split_di (rtx operands[], int num, rtx lo_half[], rtx hi_half[]) 3825 { 3826 while (num--) 3827 { 3828 rtx op = operands[num]; 3829 3830 /* simplify_subreg refuses to split volatile memory addresses, 3831 but we still have to handle it. */ 3832 if (GET_CODE (op) == MEM) 3833 { 3834 lo_half[num] = adjust_address (op, SImode, 4); 3835 hi_half[num] = adjust_address (op, SImode, 0); 3836 } 3837 else 3838 { 3839 lo_half[num] = simplify_gen_subreg (SImode, op, 3840 GET_MODE (op) == VOIDmode 3841 ? DImode : GET_MODE (op), 4); 3842 hi_half[num] = simplify_gen_subreg (SImode, op, 3843 GET_MODE (op) == VOIDmode 3844 ? DImode : GET_MODE (op), 0); 3845 } 3846 } 3847 } 3848 3849 /* Split X into a base and a constant offset, storing them in *BASE 3850 and *OFFSET respectively. */ 3851 3852 static void 3853 m68k_split_offset (rtx x, rtx *base, HOST_WIDE_INT *offset) 3854 { 3855 *offset = 0; 3856 if (GET_CODE (x) == PLUS && GET_CODE (XEXP (x, 1)) == CONST_INT) 3857 { 3858 *offset += INTVAL (XEXP (x, 1)); 3859 x = XEXP (x, 0); 3860 } 3861 *base = x; 3862 } 3863 3864 /* Return true if PATTERN is a PARALLEL suitable for a movem or fmovem 3865 instruction. STORE_P says whether the move is a load or store. 3866 3867 If the instruction uses post-increment or pre-decrement addressing, 3868 AUTOMOD_BASE is the base register and AUTOMOD_OFFSET is the total 3869 adjustment. This adjustment will be made by the first element of 3870 PARALLEL, with the loads or stores starting at element 1. If the 3871 instruction does not use post-increment or pre-decrement addressing, 3872 AUTOMOD_BASE is null, AUTOMOD_OFFSET is 0, and the loads or stores 3873 start at element 0. */ 3874 3875 bool 3876 m68k_movem_pattern_p (rtx pattern, rtx automod_base, 3877 HOST_WIDE_INT automod_offset, bool store_p) 3878 { 3879 rtx base, mem_base, set, mem, reg, last_reg; 3880 HOST_WIDE_INT offset, mem_offset; 3881 int i, first, len; 3882 enum reg_class rclass; 3883 3884 len = XVECLEN (pattern, 0); 3885 first = (automod_base != NULL); 3886 3887 if (automod_base) 3888 { 3889 /* Stores must be pre-decrement and loads must be post-increment. */ 3890 if (store_p != (automod_offset < 0)) 3891 return false; 3892 3893 /* Work out the base and offset for lowest memory location. */ 3894 base = automod_base; 3895 offset = (automod_offset < 0 ? automod_offset : 0); 3896 } 3897 else 3898 { 3899 /* Allow any valid base and offset in the first access. */ 3900 base = NULL; 3901 offset = 0; 3902 } 3903 3904 last_reg = NULL; 3905 rclass = NO_REGS; 3906 for (i = first; i < len; i++) 3907 { 3908 /* We need a plain SET. */ 3909 set = XVECEXP (pattern, 0, i); 3910 if (GET_CODE (set) != SET) 3911 return false; 3912 3913 /* Check that we have a memory location... */ 3914 mem = XEXP (set, !store_p); 3915 if (!MEM_P (mem) || !memory_operand (mem, VOIDmode)) 3916 return false; 3917 3918 /* ...with the right address. */ 3919 if (base == NULL) 3920 { 3921 m68k_split_offset (XEXP (mem, 0), &base, &offset); 3922 /* The ColdFire instruction only allows (An) and (d16,An) modes. 3923 There are no mode restrictions for 680x0 besides the 3924 automodification rules enforced above. */ 3925 if (TARGET_COLDFIRE 3926 && !m68k_legitimate_base_reg_p (base, reload_completed)) 3927 return false; 3928 } 3929 else 3930 { 3931 m68k_split_offset (XEXP (mem, 0), &mem_base, &mem_offset); 3932 if (!rtx_equal_p (base, mem_base) || offset != mem_offset) 3933 return false; 3934 } 3935 3936 /* Check that we have a register of the required mode and class. */ 3937 reg = XEXP (set, store_p); 3938 if (!REG_P (reg) 3939 || !HARD_REGISTER_P (reg) 3940 || GET_MODE (reg) != reg_raw_mode[REGNO (reg)]) 3941 return false; 3942 3943 if (last_reg) 3944 { 3945 /* The register must belong to RCLASS and have a higher number 3946 than the register in the previous SET. */ 3947 if (!TEST_HARD_REG_BIT (reg_class_contents[rclass], REGNO (reg)) 3948 || REGNO (last_reg) >= REGNO (reg)) 3949 return false; 3950 } 3951 else 3952 { 3953 /* Work out which register class we need. */ 3954 if (INT_REGNO_P (REGNO (reg))) 3955 rclass = GENERAL_REGS; 3956 else if (FP_REGNO_P (REGNO (reg))) 3957 rclass = FP_REGS; 3958 else 3959 return false; 3960 } 3961 3962 last_reg = reg; 3963 offset += GET_MODE_SIZE (GET_MODE (reg)); 3964 } 3965 3966 /* If we have an automodification, check whether the final offset is OK. */ 3967 if (automod_base && offset != (automod_offset < 0 ? 0 : automod_offset)) 3968 return false; 3969 3970 /* Reject unprofitable cases. */ 3971 if (len < first + (rclass == FP_REGS ? MIN_FMOVEM_REGS : MIN_MOVEM_REGS)) 3972 return false; 3973 3974 return true; 3975 } 3976 3977 /* Return the assembly code template for a movem or fmovem instruction 3978 whose pattern is given by PATTERN. Store the template's operands 3979 in OPERANDS. 3980 3981 If the instruction uses post-increment or pre-decrement addressing, 3982 AUTOMOD_OFFSET is the total adjustment, otherwise it is 0. STORE_P 3983 is true if this is a store instruction. */ 3984 3985 const char * 3986 m68k_output_movem (rtx *operands, rtx pattern, 3987 HOST_WIDE_INT automod_offset, bool store_p) 3988 { 3989 unsigned int mask; 3990 int i, first; 3991 3992 gcc_assert (GET_CODE (pattern) == PARALLEL); 3993 mask = 0; 3994 first = (automod_offset != 0); 3995 for (i = first; i < XVECLEN (pattern, 0); i++) 3996 { 3997 /* When using movem with pre-decrement addressing, register X + D0_REG 3998 is controlled by bit 15 - X. For all other addressing modes, 3999 register X + D0_REG is controlled by bit X. Confusingly, the 4000 register mask for fmovem is in the opposite order to that for 4001 movem. */ 4002 unsigned int regno; 4003 4004 gcc_assert (MEM_P (XEXP (XVECEXP (pattern, 0, i), !store_p))); 4005 gcc_assert (REG_P (XEXP (XVECEXP (pattern, 0, i), store_p))); 4006 regno = REGNO (XEXP (XVECEXP (pattern, 0, i), store_p)); 4007 if (automod_offset < 0) 4008 { 4009 if (FP_REGNO_P (regno)) 4010 mask |= 1 << (regno - FP0_REG); 4011 else 4012 mask |= 1 << (15 - (regno - D0_REG)); 4013 } 4014 else 4015 { 4016 if (FP_REGNO_P (regno)) 4017 mask |= 1 << (7 - (regno - FP0_REG)); 4018 else 4019 mask |= 1 << (regno - D0_REG); 4020 } 4021 } 4022 CC_STATUS_INIT; 4023 4024 if (automod_offset == 0) 4025 operands[0] = XEXP (XEXP (XVECEXP (pattern, 0, first), !store_p), 0); 4026 else if (automod_offset < 0) 4027 operands[0] = gen_rtx_PRE_DEC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); 4028 else 4029 operands[0] = gen_rtx_POST_INC (Pmode, SET_DEST (XVECEXP (pattern, 0, 0))); 4030 operands[1] = GEN_INT (mask); 4031 if (FP_REGNO_P (REGNO (XEXP (XVECEXP (pattern, 0, first), store_p)))) 4032 { 4033 if (store_p) 4034 return "fmovem %1,%a0"; 4035 else 4036 return "fmovem %a0,%1"; 4037 } 4038 else 4039 { 4040 if (store_p) 4041 return "movem%.l %1,%a0"; 4042 else 4043 return "movem%.l %a0,%1"; 4044 } 4045 } 4046 4047 /* Return a REG that occurs in ADDR with coefficient 1. 4048 ADDR can be effectively incremented by incrementing REG. */ 4049 4050 static rtx 4051 find_addr_reg (rtx addr) 4052 { 4053 while (GET_CODE (addr) == PLUS) 4054 { 4055 if (GET_CODE (XEXP (addr, 0)) == REG) 4056 addr = XEXP (addr, 0); 4057 else if (GET_CODE (XEXP (addr, 1)) == REG) 4058 addr = XEXP (addr, 1); 4059 else if (CONSTANT_P (XEXP (addr, 0))) 4060 addr = XEXP (addr, 1); 4061 else if (CONSTANT_P (XEXP (addr, 1))) 4062 addr = XEXP (addr, 0); 4063 else 4064 gcc_unreachable (); 4065 } 4066 gcc_assert (GET_CODE (addr) == REG); 4067 return addr; 4068 } 4069 4070 /* Output assembler code to perform a 32-bit 3-operand add. */ 4071 4072 const char * 4073 output_addsi3 (rtx *operands) 4074 { 4075 if (! operands_match_p (operands[0], operands[1])) 4076 { 4077 if (!ADDRESS_REG_P (operands[1])) 4078 { 4079 rtx tmp = operands[1]; 4080 4081 operands[1] = operands[2]; 4082 operands[2] = tmp; 4083 } 4084 4085 /* These insns can result from reloads to access 4086 stack slots over 64k from the frame pointer. */ 4087 if (GET_CODE (operands[2]) == CONST_INT 4088 && (INTVAL (operands[2]) < -32768 || INTVAL (operands[2]) > 32767)) 4089 return "move%.l %2,%0\n\tadd%.l %1,%0"; 4090 if (GET_CODE (operands[2]) == REG) 4091 return MOTOROLA ? "lea (%1,%2.l),%0" : "lea %1@(0,%2:l),%0"; 4092 return MOTOROLA ? "lea (%c2,%1),%0" : "lea %1@(%c2),%0"; 4093 } 4094 if (GET_CODE (operands[2]) == CONST_INT) 4095 { 4096 if (INTVAL (operands[2]) > 0 4097 && INTVAL (operands[2]) <= 8) 4098 return "addq%.l %2,%0"; 4099 if (INTVAL (operands[2]) < 0 4100 && INTVAL (operands[2]) >= -8) 4101 { 4102 operands[2] = GEN_INT (- INTVAL (operands[2])); 4103 return "subq%.l %2,%0"; 4104 } 4105 /* On the CPU32 it is faster to use two addql instructions to 4106 add a small integer (8 < N <= 16) to a register. 4107 Likewise for subql. */ 4108 if (TUNE_CPU32 && REG_P (operands[0])) 4109 { 4110 if (INTVAL (operands[2]) > 8 4111 && INTVAL (operands[2]) <= 16) 4112 { 4113 operands[2] = GEN_INT (INTVAL (operands[2]) - 8); 4114 return "addq%.l #8,%0\n\taddq%.l %2,%0"; 4115 } 4116 if (INTVAL (operands[2]) < -8 4117 && INTVAL (operands[2]) >= -16) 4118 { 4119 operands[2] = GEN_INT (- INTVAL (operands[2]) - 8); 4120 return "subq%.l #8,%0\n\tsubq%.l %2,%0"; 4121 } 4122 } 4123 if (ADDRESS_REG_P (operands[0]) 4124 && INTVAL (operands[2]) >= -0x8000 4125 && INTVAL (operands[2]) < 0x8000) 4126 { 4127 if (TUNE_68040) 4128 return "add%.w %2,%0"; 4129 else 4130 return MOTOROLA ? "lea (%c2,%0),%0" : "lea %0@(%c2),%0"; 4131 } 4132 } 4133 return "add%.l %2,%0"; 4134 } 4135 4136 /* Store in cc_status the expressions that the condition codes will 4137 describe after execution of an instruction whose pattern is EXP. 4138 Do not alter them if the instruction would not alter the cc's. */ 4139 4140 /* On the 68000, all the insns to store in an address register fail to 4141 set the cc's. However, in some cases these instructions can make it 4142 possibly invalid to use the saved cc's. In those cases we clear out 4143 some or all of the saved cc's so they won't be used. */ 4144 4145 void 4146 notice_update_cc (rtx exp, rtx insn) 4147 { 4148 if (GET_CODE (exp) == SET) 4149 { 4150 if (GET_CODE (SET_SRC (exp)) == CALL) 4151 CC_STATUS_INIT; 4152 else if (ADDRESS_REG_P (SET_DEST (exp))) 4153 { 4154 if (cc_status.value1 && modified_in_p (cc_status.value1, insn)) 4155 cc_status.value1 = 0; 4156 if (cc_status.value2 && modified_in_p (cc_status.value2, insn)) 4157 cc_status.value2 = 0; 4158 } 4159 /* fmoves to memory or data registers do not set the condition 4160 codes. Normal moves _do_ set the condition codes, but not in 4161 a way that is appropriate for comparison with 0, because -0.0 4162 would be treated as a negative nonzero number. Note that it 4163 isn't appropriate to conditionalize this restriction on 4164 HONOR_SIGNED_ZEROS because that macro merely indicates whether 4165 we care about the difference between -0.0 and +0.0. */ 4166 else if (!FP_REG_P (SET_DEST (exp)) 4167 && SET_DEST (exp) != cc0_rtx 4168 && (FP_REG_P (SET_SRC (exp)) 4169 || GET_CODE (SET_SRC (exp)) == FIX 4170 || FLOAT_MODE_P (GET_MODE (SET_DEST (exp))))) 4171 CC_STATUS_INIT; 4172 /* A pair of move insns doesn't produce a useful overall cc. */ 4173 else if (!FP_REG_P (SET_DEST (exp)) 4174 && !FP_REG_P (SET_SRC (exp)) 4175 && GET_MODE_SIZE (GET_MODE (SET_SRC (exp))) > 4 4176 && (GET_CODE (SET_SRC (exp)) == REG 4177 || GET_CODE (SET_SRC (exp)) == MEM 4178 || GET_CODE (SET_SRC (exp)) == CONST_DOUBLE)) 4179 CC_STATUS_INIT; 4180 else if (SET_DEST (exp) != pc_rtx) 4181 { 4182 cc_status.flags = 0; 4183 cc_status.value1 = SET_DEST (exp); 4184 cc_status.value2 = SET_SRC (exp); 4185 } 4186 } 4187 else if (GET_CODE (exp) == PARALLEL 4188 && GET_CODE (XVECEXP (exp, 0, 0)) == SET) 4189 { 4190 rtx dest = SET_DEST (XVECEXP (exp, 0, 0)); 4191 rtx src = SET_SRC (XVECEXP (exp, 0, 0)); 4192 4193 if (ADDRESS_REG_P (dest)) 4194 CC_STATUS_INIT; 4195 else if (dest != pc_rtx) 4196 { 4197 cc_status.flags = 0; 4198 cc_status.value1 = dest; 4199 cc_status.value2 = src; 4200 } 4201 } 4202 else 4203 CC_STATUS_INIT; 4204 if (cc_status.value2 != 0 4205 && ADDRESS_REG_P (cc_status.value2) 4206 && GET_MODE (cc_status.value2) == QImode) 4207 CC_STATUS_INIT; 4208 if (cc_status.value2 != 0) 4209 switch (GET_CODE (cc_status.value2)) 4210 { 4211 case ASHIFT: case ASHIFTRT: case LSHIFTRT: 4212 case ROTATE: case ROTATERT: 4213 /* These instructions always clear the overflow bit, and set 4214 the carry to the bit shifted out. */ 4215 cc_status.flags |= CC_OVERFLOW_UNUSABLE | CC_NO_CARRY; 4216 break; 4217 4218 case PLUS: case MINUS: case MULT: 4219 case DIV: case UDIV: case MOD: case UMOD: case NEG: 4220 if (GET_MODE (cc_status.value2) != VOIDmode) 4221 cc_status.flags |= CC_NO_OVERFLOW; 4222 break; 4223 case ZERO_EXTEND: 4224 /* (SET r1 (ZERO_EXTEND r2)) on this machine 4225 ends with a move insn moving r2 in r2's mode. 4226 Thus, the cc's are set for r2. 4227 This can set N bit spuriously. */ 4228 cc_status.flags |= CC_NOT_NEGATIVE; 4229 4230 default: 4231 break; 4232 } 4233 if (cc_status.value1 && GET_CODE (cc_status.value1) == REG 4234 && cc_status.value2 4235 && reg_overlap_mentioned_p (cc_status.value1, cc_status.value2)) 4236 cc_status.value2 = 0; 4237 /* Check for PRE_DEC in dest modifying a register used in src. */ 4238 if (cc_status.value1 && GET_CODE (cc_status.value1) == MEM 4239 && GET_CODE (XEXP (cc_status.value1, 0)) == PRE_DEC 4240 && cc_status.value2 4241 && reg_overlap_mentioned_p (XEXP (XEXP (cc_status.value1, 0), 0), 4242 cc_status.value2)) 4243 cc_status.value2 = 0; 4244 if (((cc_status.value1 && FP_REG_P (cc_status.value1)) 4245 || (cc_status.value2 && FP_REG_P (cc_status.value2)))) 4246 cc_status.flags = CC_IN_68881; 4247 if (cc_status.value2 && GET_CODE (cc_status.value2) == COMPARE 4248 && GET_MODE_CLASS (GET_MODE (XEXP (cc_status.value2, 0))) == MODE_FLOAT) 4249 { 4250 cc_status.flags = CC_IN_68881; 4251 if (!FP_REG_P (XEXP (cc_status.value2, 0)) 4252 && FP_REG_P (XEXP (cc_status.value2, 1))) 4253 cc_status.flags |= CC_REVERSED; 4254 } 4255 } 4256 4257 const char * 4258 output_move_const_double (rtx *operands) 4259 { 4260 int code = standard_68881_constant_p (operands[1]); 4261 4262 if (code != 0) 4263 { 4264 static char buf[40]; 4265 4266 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); 4267 return buf; 4268 } 4269 return "fmove%.d %1,%0"; 4270 } 4271 4272 const char * 4273 output_move_const_single (rtx *operands) 4274 { 4275 int code = standard_68881_constant_p (operands[1]); 4276 4277 if (code != 0) 4278 { 4279 static char buf[40]; 4280 4281 sprintf (buf, "fmovecr #0x%x,%%0", code & 0xff); 4282 return buf; 4283 } 4284 return "fmove%.s %f1,%0"; 4285 } 4286 4287 /* Return nonzero if X, a CONST_DOUBLE, has a value that we can get 4288 from the "fmovecr" instruction. 4289 The value, anded with 0xff, gives the code to use in fmovecr 4290 to get the desired constant. */ 4291 4292 /* This code has been fixed for cross-compilation. */ 4293 4294 static int inited_68881_table = 0; 4295 4296 static const char *const strings_68881[7] = { 4297 "0.0", 4298 "1.0", 4299 "10.0", 4300 "100.0", 4301 "10000.0", 4302 "1e8", 4303 "1e16" 4304 }; 4305 4306 static const int codes_68881[7] = { 4307 0x0f, 4308 0x32, 4309 0x33, 4310 0x34, 4311 0x35, 4312 0x36, 4313 0x37 4314 }; 4315 4316 REAL_VALUE_TYPE values_68881[7]; 4317 4318 /* Set up values_68881 array by converting the decimal values 4319 strings_68881 to binary. */ 4320 4321 void 4322 init_68881_table (void) 4323 { 4324 int i; 4325 REAL_VALUE_TYPE r; 4326 machine_mode mode; 4327 4328 mode = SFmode; 4329 for (i = 0; i < 7; i++) 4330 { 4331 if (i == 6) 4332 mode = DFmode; 4333 r = REAL_VALUE_ATOF (strings_68881[i], mode); 4334 values_68881[i] = r; 4335 } 4336 inited_68881_table = 1; 4337 } 4338 4339 int 4340 standard_68881_constant_p (rtx x) 4341 { 4342 REAL_VALUE_TYPE r; 4343 int i; 4344 4345 /* fmovecr must be emulated on the 68040 and 68060, so it shouldn't be 4346 used at all on those chips. */ 4347 if (TUNE_68040_60) 4348 return 0; 4349 4350 if (! inited_68881_table) 4351 init_68881_table (); 4352 4353 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 4354 4355 /* Use REAL_VALUES_IDENTICAL instead of REAL_VALUES_EQUAL so that -0.0 4356 is rejected. */ 4357 for (i = 0; i < 6; i++) 4358 { 4359 if (REAL_VALUES_IDENTICAL (r, values_68881[i])) 4360 return (codes_68881[i]); 4361 } 4362 4363 if (GET_MODE (x) == SFmode) 4364 return 0; 4365 4366 if (REAL_VALUES_EQUAL (r, values_68881[6])) 4367 return (codes_68881[6]); 4368 4369 /* larger powers of ten in the constants ram are not used 4370 because they are not equal to a `double' C constant. */ 4371 return 0; 4372 } 4373 4374 /* If X is a floating-point constant, return the logarithm of X base 2, 4375 or 0 if X is not a power of 2. */ 4376 4377 int 4378 floating_exact_log2 (rtx x) 4379 { 4380 REAL_VALUE_TYPE r, r1; 4381 int exp; 4382 4383 REAL_VALUE_FROM_CONST_DOUBLE (r, x); 4384 4385 if (REAL_VALUES_LESS (r, dconst1)) 4386 return 0; 4387 4388 exp = real_exponent (&r); 4389 real_2expN (&r1, exp, DFmode); 4390 if (REAL_VALUES_EQUAL (r1, r)) 4391 return exp; 4392 4393 return 0; 4394 } 4395 4396 /* A C compound statement to output to stdio stream STREAM the 4397 assembler syntax for an instruction operand X. X is an RTL 4398 expression. 4399 4400 CODE is a value that can be used to specify one of several ways 4401 of printing the operand. It is used when identical operands 4402 must be printed differently depending on the context. CODE 4403 comes from the `%' specification that was used to request 4404 printing of the operand. If the specification was just `%DIGIT' 4405 then CODE is 0; if the specification was `%LTR DIGIT' then CODE 4406 is the ASCII code for LTR. 4407 4408 If X is a register, this macro should print the register's name. 4409 The names can be found in an array `reg_names' whose type is 4410 `char *[]'. `reg_names' is initialized from `REGISTER_NAMES'. 4411 4412 When the machine description has a specification `%PUNCT' (a `%' 4413 followed by a punctuation character), this macro is called with 4414 a null pointer for X and the punctuation character for CODE. 4415 4416 The m68k specific codes are: 4417 4418 '.' for dot needed in Motorola-style opcode names. 4419 '-' for an operand pushing on the stack: 4420 sp@-, -(sp) or -(%sp) depending on the style of syntax. 4421 '+' for an operand pushing on the stack: 4422 sp@+, (sp)+ or (%sp)+ depending on the style of syntax. 4423 '@' for a reference to the top word on the stack: 4424 sp@, (sp) or (%sp) depending on the style of syntax. 4425 '#' for an immediate operand prefix (# in MIT and Motorola syntax 4426 but & in SGS syntax). 4427 '!' for the cc register (used in an `and to cc' insn). 4428 '$' for the letter `s' in an op code, but only on the 68040. 4429 '&' for the letter `d' in an op code, but only on the 68040. 4430 '/' for register prefix needed by longlong.h. 4431 '?' for m68k_library_id_string 4432 4433 'b' for byte insn (no effect, on the Sun; this is for the ISI). 4434 'd' to force memory addressing to be absolute, not relative. 4435 'f' for float insn (print a CONST_DOUBLE as a float rather than in hex) 4436 'x' for float insn (print a CONST_DOUBLE as a float rather than in hex), 4437 or print pair of registers as rx:ry. 4438 'p' print an address with @PLTPC attached, but only if the operand 4439 is not locally-bound. */ 4440 4441 void 4442 print_operand (FILE *file, rtx op, int letter) 4443 { 4444 if (letter == '.') 4445 { 4446 if (MOTOROLA) 4447 fprintf (file, "."); 4448 } 4449 else if (letter == '#') 4450 asm_fprintf (file, "%I"); 4451 else if (letter == '-') 4452 asm_fprintf (file, MOTOROLA ? "-(%Rsp)" : "%Rsp@-"); 4453 else if (letter == '+') 4454 asm_fprintf (file, MOTOROLA ? "(%Rsp)+" : "%Rsp@+"); 4455 else if (letter == '@') 4456 asm_fprintf (file, MOTOROLA ? "(%Rsp)" : "%Rsp@"); 4457 else if (letter == '!') 4458 asm_fprintf (file, "%Rfpcr"); 4459 else if (letter == '$') 4460 { 4461 if (TARGET_68040) 4462 fprintf (file, "s"); 4463 } 4464 else if (letter == '&') 4465 { 4466 if (TARGET_68040) 4467 fprintf (file, "d"); 4468 } 4469 else if (letter == '/') 4470 asm_fprintf (file, "%R"); 4471 else if (letter == '?') 4472 asm_fprintf (file, m68k_library_id_string); 4473 else if (letter == 'p') 4474 { 4475 output_addr_const (file, op); 4476 if (!(GET_CODE (op) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (op))) 4477 fprintf (file, "@PLTPC"); 4478 } 4479 else if (GET_CODE (op) == REG) 4480 { 4481 if (letter == 'R') 4482 /* Print out the second register name of a register pair. 4483 I.e., R (6) => 7. */ 4484 fputs (M68K_REGNAME(REGNO (op) + 1), file); 4485 else 4486 fputs (M68K_REGNAME(REGNO (op)), file); 4487 } 4488 else if (GET_CODE (op) == MEM) 4489 { 4490 output_address (XEXP (op, 0)); 4491 if (letter == 'd' && ! TARGET_68020 4492 && CONSTANT_ADDRESS_P (XEXP (op, 0)) 4493 && !(GET_CODE (XEXP (op, 0)) == CONST_INT 4494 && INTVAL (XEXP (op, 0)) < 0x8000 4495 && INTVAL (XEXP (op, 0)) >= -0x8000)) 4496 fprintf (file, MOTOROLA ? ".l" : ":l"); 4497 } 4498 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == SFmode) 4499 { 4500 REAL_VALUE_TYPE r; 4501 long l; 4502 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 4503 REAL_VALUE_TO_TARGET_SINGLE (r, l); 4504 asm_fprintf (file, "%I0x%lx", l & 0xFFFFFFFF); 4505 } 4506 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == XFmode) 4507 { 4508 REAL_VALUE_TYPE r; 4509 long l[3]; 4510 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 4511 REAL_VALUE_TO_TARGET_LONG_DOUBLE (r, l); 4512 asm_fprintf (file, "%I0x%lx%08lx%08lx", l[0] & 0xFFFFFFFF, 4513 l[1] & 0xFFFFFFFF, l[2] & 0xFFFFFFFF); 4514 } 4515 else if (GET_CODE (op) == CONST_DOUBLE && GET_MODE (op) == DFmode) 4516 { 4517 REAL_VALUE_TYPE r; 4518 long l[2]; 4519 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 4520 REAL_VALUE_TO_TARGET_DOUBLE (r, l); 4521 asm_fprintf (file, "%I0x%lx%08lx", l[0] & 0xFFFFFFFF, l[1] & 0xFFFFFFFF); 4522 } 4523 else 4524 { 4525 /* Use `print_operand_address' instead of `output_addr_const' 4526 to ensure that we print relevant PIC stuff. */ 4527 asm_fprintf (file, "%I"); 4528 if (TARGET_PCREL 4529 && (GET_CODE (op) == SYMBOL_REF || GET_CODE (op) == CONST)) 4530 print_operand_address (file, op); 4531 else 4532 output_addr_const (file, op); 4533 } 4534 } 4535 4536 /* Return string for TLS relocation RELOC. */ 4537 4538 static const char * 4539 m68k_get_reloc_decoration (enum m68k_reloc reloc) 4540 { 4541 /* To my knowledge, !MOTOROLA assemblers don't support TLS. */ 4542 gcc_assert (MOTOROLA || reloc == RELOC_GOT); 4543 4544 switch (reloc) 4545 { 4546 case RELOC_GOT: 4547 if (MOTOROLA) 4548 { 4549 if (flag_pic == 1 && TARGET_68020) 4550 return "@GOT.w"; 4551 else 4552 return "@GOT"; 4553 } 4554 else 4555 { 4556 if (TARGET_68020) 4557 { 4558 switch (flag_pic) 4559 { 4560 case 1: 4561 return ":w"; 4562 case 2: 4563 return ":l"; 4564 default: 4565 return ""; 4566 } 4567 } 4568 } 4569 4570 case RELOC_TLSGD: 4571 return "@TLSGD"; 4572 4573 case RELOC_TLSLDM: 4574 return "@TLSLDM"; 4575 4576 case RELOC_TLSLDO: 4577 return "@TLSLDO"; 4578 4579 case RELOC_TLSIE: 4580 return "@TLSIE"; 4581 4582 case RELOC_TLSLE: 4583 return "@TLSLE"; 4584 4585 default: 4586 gcc_unreachable (); 4587 } 4588 } 4589 4590 /* m68k implementation of TARGET_OUTPUT_ADDR_CONST_EXTRA. */ 4591 4592 static bool 4593 m68k_output_addr_const_extra (FILE *file, rtx x) 4594 { 4595 if (GET_CODE (x) == UNSPEC) 4596 { 4597 switch (XINT (x, 1)) 4598 { 4599 case UNSPEC_RELOC16: 4600 case UNSPEC_RELOC32: 4601 output_addr_const (file, XVECEXP (x, 0, 0)); 4602 fputs (m68k_get_reloc_decoration 4603 ((enum m68k_reloc) INTVAL (XVECEXP (x, 0, 1))), file); 4604 return true; 4605 4606 default: 4607 break; 4608 } 4609 } 4610 4611 return false; 4612 } 4613 4614 /* M68K implementation of TARGET_ASM_OUTPUT_DWARF_DTPREL. */ 4615 4616 static void 4617 m68k_output_dwarf_dtprel (FILE *file, int size, rtx x) 4618 { 4619 gcc_assert (size == 4); 4620 fputs ("\t.long\t", file); 4621 output_addr_const (file, x); 4622 fputs ("@TLSLDO+0x8000", file); 4623 } 4624 4625 /* In the name of slightly smaller debug output, and to cater to 4626 general assembler lossage, recognize various UNSPEC sequences 4627 and turn them back into a direct symbol reference. */ 4628 4629 static rtx 4630 m68k_delegitimize_address (rtx orig_x) 4631 { 4632 rtx x; 4633 struct m68k_address addr; 4634 rtx unspec; 4635 4636 orig_x = delegitimize_mem_from_attrs (orig_x); 4637 x = orig_x; 4638 if (MEM_P (x)) 4639 x = XEXP (x, 0); 4640 4641 if (GET_CODE (x) != PLUS || GET_MODE (x) != Pmode) 4642 return orig_x; 4643 4644 if (!m68k_decompose_address (GET_MODE (x), x, false, &addr) 4645 || addr.offset == NULL_RTX 4646 || GET_CODE (addr.offset) != CONST) 4647 return orig_x; 4648 4649 unspec = XEXP (addr.offset, 0); 4650 if (GET_CODE (unspec) == PLUS && CONST_INT_P (XEXP (unspec, 1))) 4651 unspec = XEXP (unspec, 0); 4652 if (GET_CODE (unspec) != UNSPEC 4653 || (XINT (unspec, 1) != UNSPEC_RELOC16 4654 && XINT (unspec, 1) != UNSPEC_RELOC32)) 4655 return orig_x; 4656 x = XVECEXP (unspec, 0, 0); 4657 gcc_assert (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF); 4658 if (unspec != XEXP (addr.offset, 0)) 4659 x = gen_rtx_PLUS (Pmode, x, XEXP (XEXP (addr.offset, 0), 1)); 4660 if (addr.index) 4661 { 4662 rtx idx = addr.index; 4663 if (addr.scale != 1) 4664 idx = gen_rtx_MULT (Pmode, idx, GEN_INT (addr.scale)); 4665 x = gen_rtx_PLUS (Pmode, idx, x); 4666 } 4667 if (addr.base) 4668 x = gen_rtx_PLUS (Pmode, addr.base, x); 4669 if (MEM_P (orig_x)) 4670 x = replace_equiv_address_nv (orig_x, x); 4671 return x; 4672 } 4673 4674 4675 /* A C compound statement to output to stdio stream STREAM the 4676 assembler syntax for an instruction operand that is a memory 4677 reference whose address is ADDR. ADDR is an RTL expression. 4678 4679 Note that this contains a kludge that knows that the only reason 4680 we have an address (plus (label_ref...) (reg...)) when not generating 4681 PIC code is in the insn before a tablejump, and we know that m68k.md 4682 generates a label LInnn: on such an insn. 4683 4684 It is possible for PIC to generate a (plus (label_ref...) (reg...)) 4685 and we handle that just like we would a (plus (symbol_ref...) (reg...)). 4686 4687 This routine is responsible for distinguishing between -fpic and -fPIC 4688 style relocations in an address. When generating -fpic code the 4689 offset is output in word mode (e.g. movel a5@(_foo:w), a0). When generating 4690 -fPIC code the offset is output in long mode (e.g. movel a5@(_foo:l), a0) */ 4691 4692 void 4693 print_operand_address (FILE *file, rtx addr) 4694 { 4695 struct m68k_address address; 4696 4697 if (!m68k_decompose_address (QImode, addr, true, &address)) 4698 gcc_unreachable (); 4699 4700 if (address.code == PRE_DEC) 4701 fprintf (file, MOTOROLA ? "-(%s)" : "%s@-", 4702 M68K_REGNAME (REGNO (address.base))); 4703 else if (address.code == POST_INC) 4704 fprintf (file, MOTOROLA ? "(%s)+" : "%s@+", 4705 M68K_REGNAME (REGNO (address.base))); 4706 else if (!address.base && !address.index) 4707 { 4708 /* A constant address. */ 4709 gcc_assert (address.offset == addr); 4710 if (GET_CODE (addr) == CONST_INT) 4711 { 4712 /* (xxx).w or (xxx).l. */ 4713 if (IN_RANGE (INTVAL (addr), -0x8000, 0x7fff)) 4714 fprintf (file, MOTOROLA ? "%d.w" : "%d:w", (int) INTVAL (addr)); 4715 else 4716 fprintf (file, HOST_WIDE_INT_PRINT_DEC, INTVAL (addr)); 4717 } 4718 else if (TARGET_PCREL) 4719 { 4720 /* (d16,PC) or (bd,PC,Xn) (with suppressed index register). */ 4721 fputc ('(', file); 4722 output_addr_const (file, addr); 4723 asm_fprintf (file, flag_pic == 1 ? ":w,%Rpc)" : ":l,%Rpc)"); 4724 } 4725 else 4726 { 4727 /* (xxx).l. We need a special case for SYMBOL_REF if the symbol 4728 name ends in `.<letter>', as the last 2 characters can be 4729 mistaken as a size suffix. Put the name in parentheses. */ 4730 if (GET_CODE (addr) == SYMBOL_REF 4731 && strlen (XSTR (addr, 0)) > 2 4732 && XSTR (addr, 0)[strlen (XSTR (addr, 0)) - 2] == '.') 4733 { 4734 putc ('(', file); 4735 output_addr_const (file, addr); 4736 putc (')', file); 4737 } 4738 else 4739 output_addr_const (file, addr); 4740 } 4741 } 4742 else 4743 { 4744 int labelno; 4745 4746 /* If ADDR is a (d8,pc,Xn) address, this is the number of the 4747 label being accessed, otherwise it is -1. */ 4748 labelno = (address.offset 4749 && !address.base 4750 && GET_CODE (address.offset) == LABEL_REF 4751 ? CODE_LABEL_NUMBER (XEXP (address.offset, 0)) 4752 : -1); 4753 if (MOTOROLA) 4754 { 4755 /* Print the "offset(base" component. */ 4756 if (labelno >= 0) 4757 asm_fprintf (file, "%LL%d(%Rpc,", labelno); 4758 else 4759 { 4760 if (address.offset) 4761 output_addr_const (file, address.offset); 4762 4763 putc ('(', file); 4764 if (address.base) 4765 fputs (M68K_REGNAME (REGNO (address.base)), file); 4766 } 4767 /* Print the ",index" component, if any. */ 4768 if (address.index) 4769 { 4770 if (address.base) 4771 putc (',', file); 4772 fprintf (file, "%s.%c", 4773 M68K_REGNAME (REGNO (address.index)), 4774 GET_MODE (address.index) == HImode ? 'w' : 'l'); 4775 if (address.scale != 1) 4776 fprintf (file, "*%d", address.scale); 4777 } 4778 putc (')', file); 4779 } 4780 else /* !MOTOROLA */ 4781 { 4782 if (!address.offset && !address.index) 4783 fprintf (file, "%s@", M68K_REGNAME (REGNO (address.base))); 4784 else 4785 { 4786 /* Print the "base@(offset" component. */ 4787 if (labelno >= 0) 4788 asm_fprintf (file, "%Rpc@(%LL%d", labelno); 4789 else 4790 { 4791 if (address.base) 4792 fputs (M68K_REGNAME (REGNO (address.base)), file); 4793 fprintf (file, "@("); 4794 if (address.offset) 4795 output_addr_const (file, address.offset); 4796 } 4797 /* Print the ",index" component, if any. */ 4798 if (address.index) 4799 { 4800 fprintf (file, ",%s:%c", 4801 M68K_REGNAME (REGNO (address.index)), 4802 GET_MODE (address.index) == HImode ? 'w' : 'l'); 4803 if (address.scale != 1) 4804 fprintf (file, ":%d", address.scale); 4805 } 4806 putc (')', file); 4807 } 4808 } 4809 } 4810 } 4811 4812 /* Check for cases where a clr insns can be omitted from code using 4813 strict_low_part sets. For example, the second clrl here is not needed: 4814 clrl d0; movw a0@+,d0; use d0; clrl d0; movw a0@+; use d0; ... 4815 4816 MODE is the mode of this STRICT_LOW_PART set. FIRST_INSN is the clear 4817 insn we are checking for redundancy. TARGET is the register set by the 4818 clear insn. */ 4819 4820 bool 4821 strict_low_part_peephole_ok (machine_mode mode, rtx_insn *first_insn, 4822 rtx target) 4823 { 4824 rtx_insn *p = first_insn; 4825 4826 while ((p = PREV_INSN (p))) 4827 { 4828 if (NOTE_INSN_BASIC_BLOCK_P (p)) 4829 return false; 4830 4831 if (NOTE_P (p)) 4832 continue; 4833 4834 /* If it isn't an insn, then give up. */ 4835 if (!INSN_P (p)) 4836 return false; 4837 4838 if (reg_set_p (target, p)) 4839 { 4840 rtx set = single_set (p); 4841 rtx dest; 4842 4843 /* If it isn't an easy to recognize insn, then give up. */ 4844 if (! set) 4845 return false; 4846 4847 dest = SET_DEST (set); 4848 4849 /* If this sets the entire target register to zero, then our 4850 first_insn is redundant. */ 4851 if (rtx_equal_p (dest, target) 4852 && SET_SRC (set) == const0_rtx) 4853 return true; 4854 else if (GET_CODE (dest) == STRICT_LOW_PART 4855 && GET_CODE (XEXP (dest, 0)) == REG 4856 && REGNO (XEXP (dest, 0)) == REGNO (target) 4857 && (GET_MODE_SIZE (GET_MODE (XEXP (dest, 0))) 4858 <= GET_MODE_SIZE (mode))) 4859 /* This is a strict low part set which modifies less than 4860 we are using, so it is safe. */ 4861 ; 4862 else 4863 return false; 4864 } 4865 } 4866 4867 return false; 4868 } 4869 4870 /* Operand predicates for implementing asymmetric pc-relative addressing 4871 on m68k. The m68k supports pc-relative addressing (mode 7, register 2) 4872 when used as a source operand, but not as a destination operand. 4873 4874 We model this by restricting the meaning of the basic predicates 4875 (general_operand, memory_operand, etc) to forbid the use of this 4876 addressing mode, and then define the following predicates that permit 4877 this addressing mode. These predicates can then be used for the 4878 source operands of the appropriate instructions. 4879 4880 n.b. While it is theoretically possible to change all machine patterns 4881 to use this addressing more where permitted by the architecture, 4882 it has only been implemented for "common" cases: SImode, HImode, and 4883 QImode operands, and only for the principle operations that would 4884 require this addressing mode: data movement and simple integer operations. 4885 4886 In parallel with these new predicates, two new constraint letters 4887 were defined: 'S' and 'T'. 'S' is the -mpcrel analog of 'm'. 4888 'T' replaces 's' in the non-pcrel case. It is a no-op in the pcrel case. 4889 In the pcrel case 's' is only valid in combination with 'a' registers. 4890 See addsi3, subsi3, cmpsi, and movsi patterns for a better understanding 4891 of how these constraints are used. 4892 4893 The use of these predicates is strictly optional, though patterns that 4894 don't will cause an extra reload register to be allocated where one 4895 was not necessary: 4896 4897 lea (abc:w,%pc),%a0 ; need to reload address 4898 moveq &1,%d1 ; since write to pc-relative space 4899 movel %d1,%a0@ ; is not allowed 4900 ... 4901 lea (abc:w,%pc),%a1 ; no need to reload address here 4902 movel %a1@,%d0 ; since "movel (abc:w,%pc),%d0" is ok 4903 4904 For more info, consult tiemann@cygnus.com. 4905 4906 4907 All of the ugliness with predicates and constraints is due to the 4908 simple fact that the m68k does not allow a pc-relative addressing 4909 mode as a destination. gcc does not distinguish between source and 4910 destination addresses. Hence, if we claim that pc-relative address 4911 modes are valid, e.g. TARGET_LEGITIMATE_ADDRESS_P accepts them, then we 4912 end up with invalid code. To get around this problem, we left 4913 pc-relative modes as invalid addresses, and then added special 4914 predicates and constraints to accept them. 4915 4916 A cleaner way to handle this is to modify gcc to distinguish 4917 between source and destination addresses. We can then say that 4918 pc-relative is a valid source address but not a valid destination 4919 address, and hopefully avoid a lot of the predicate and constraint 4920 hackery. Unfortunately, this would be a pretty big change. It would 4921 be a useful change for a number of ports, but there aren't any current 4922 plans to undertake this. 4923 4924 ***************************************************************************/ 4925 4926 4927 const char * 4928 output_andsi3 (rtx *operands) 4929 { 4930 int logval; 4931 if (GET_CODE (operands[2]) == CONST_INT 4932 && (INTVAL (operands[2]) | 0xffff) == -1 4933 && (DATA_REG_P (operands[0]) 4934 || offsettable_memref_p (operands[0])) 4935 && !TARGET_COLDFIRE) 4936 { 4937 if (GET_CODE (operands[0]) != REG) 4938 operands[0] = adjust_address (operands[0], HImode, 2); 4939 operands[2] = GEN_INT (INTVAL (operands[2]) & 0xffff); 4940 /* Do not delete a following tstl %0 insn; that would be incorrect. */ 4941 CC_STATUS_INIT; 4942 if (operands[2] == const0_rtx) 4943 return "clr%.w %0"; 4944 return "and%.w %2,%0"; 4945 } 4946 if (GET_CODE (operands[2]) == CONST_INT 4947 && (logval = exact_log2 (~ INTVAL (operands[2]) & 0xffffffff)) >= 0 4948 && (DATA_REG_P (operands[0]) 4949 || offsettable_memref_p (operands[0]))) 4950 { 4951 if (DATA_REG_P (operands[0])) 4952 operands[1] = GEN_INT (logval); 4953 else 4954 { 4955 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); 4956 operands[1] = GEN_INT (logval % 8); 4957 } 4958 /* This does not set condition codes in a standard way. */ 4959 CC_STATUS_INIT; 4960 return "bclr %1,%0"; 4961 } 4962 return "and%.l %2,%0"; 4963 } 4964 4965 const char * 4966 output_iorsi3 (rtx *operands) 4967 { 4968 register int logval; 4969 if (GET_CODE (operands[2]) == CONST_INT 4970 && INTVAL (operands[2]) >> 16 == 0 4971 && (DATA_REG_P (operands[0]) 4972 || offsettable_memref_p (operands[0])) 4973 && !TARGET_COLDFIRE) 4974 { 4975 if (GET_CODE (operands[0]) != REG) 4976 operands[0] = adjust_address (operands[0], HImode, 2); 4977 /* Do not delete a following tstl %0 insn; that would be incorrect. */ 4978 CC_STATUS_INIT; 4979 if (INTVAL (operands[2]) == 0xffff) 4980 return "mov%.w %2,%0"; 4981 return "or%.w %2,%0"; 4982 } 4983 if (GET_CODE (operands[2]) == CONST_INT 4984 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0 4985 && (DATA_REG_P (operands[0]) 4986 || offsettable_memref_p (operands[0]))) 4987 { 4988 if (DATA_REG_P (operands[0])) 4989 operands[1] = GEN_INT (logval); 4990 else 4991 { 4992 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); 4993 operands[1] = GEN_INT (logval % 8); 4994 } 4995 CC_STATUS_INIT; 4996 return "bset %1,%0"; 4997 } 4998 return "or%.l %2,%0"; 4999 } 5000 5001 const char * 5002 output_xorsi3 (rtx *operands) 5003 { 5004 register int logval; 5005 if (GET_CODE (operands[2]) == CONST_INT 5006 && INTVAL (operands[2]) >> 16 == 0 5007 && (offsettable_memref_p (operands[0]) || DATA_REG_P (operands[0])) 5008 && !TARGET_COLDFIRE) 5009 { 5010 if (! DATA_REG_P (operands[0])) 5011 operands[0] = adjust_address (operands[0], HImode, 2); 5012 /* Do not delete a following tstl %0 insn; that would be incorrect. */ 5013 CC_STATUS_INIT; 5014 if (INTVAL (operands[2]) == 0xffff) 5015 return "not%.w %0"; 5016 return "eor%.w %2,%0"; 5017 } 5018 if (GET_CODE (operands[2]) == CONST_INT 5019 && (logval = exact_log2 (INTVAL (operands[2]) & 0xffffffff)) >= 0 5020 && (DATA_REG_P (operands[0]) 5021 || offsettable_memref_p (operands[0]))) 5022 { 5023 if (DATA_REG_P (operands[0])) 5024 operands[1] = GEN_INT (logval); 5025 else 5026 { 5027 operands[0] = adjust_address (operands[0], SImode, 3 - (logval / 8)); 5028 operands[1] = GEN_INT (logval % 8); 5029 } 5030 CC_STATUS_INIT; 5031 return "bchg %1,%0"; 5032 } 5033 return "eor%.l %2,%0"; 5034 } 5035 5036 /* Return the instruction that should be used for a call to address X, 5037 which is known to be in operand 0. */ 5038 5039 const char * 5040 output_call (rtx x) 5041 { 5042 if (symbolic_operand (x, VOIDmode)) 5043 return m68k_symbolic_call; 5044 else 5045 return "jsr %a0"; 5046 } 5047 5048 /* Likewise sibling calls. */ 5049 5050 const char * 5051 output_sibcall (rtx x) 5052 { 5053 if (symbolic_operand (x, VOIDmode)) 5054 return m68k_symbolic_jump; 5055 else 5056 return "jmp %a0"; 5057 } 5058 5059 static void 5060 m68k_output_mi_thunk (FILE *file, tree thunk ATTRIBUTE_UNUSED, 5061 HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset, 5062 tree function) 5063 { 5064 rtx this_slot, offset, addr, mem, tmp; 5065 rtx_insn *insn; 5066 5067 /* Avoid clobbering the struct value reg by using the 5068 static chain reg as a temporary. */ 5069 tmp = gen_rtx_REG (Pmode, STATIC_CHAIN_REGNUM); 5070 5071 /* Pretend to be a post-reload pass while generating rtl. */ 5072 reload_completed = 1; 5073 5074 /* The "this" pointer is stored at 4(%sp). */ 5075 this_slot = gen_rtx_MEM (Pmode, plus_constant (Pmode, 5076 stack_pointer_rtx, 4)); 5077 5078 /* Add DELTA to THIS. */ 5079 if (delta != 0) 5080 { 5081 /* Make the offset a legitimate operand for memory addition. */ 5082 offset = GEN_INT (delta); 5083 if ((delta < -8 || delta > 8) 5084 && (TARGET_COLDFIRE || USE_MOVQ (delta))) 5085 { 5086 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), offset); 5087 offset = gen_rtx_REG (Pmode, D0_REG); 5088 } 5089 emit_insn (gen_add3_insn (copy_rtx (this_slot), 5090 copy_rtx (this_slot), offset)); 5091 } 5092 5093 /* If needed, add *(*THIS + VCALL_OFFSET) to THIS. */ 5094 if (vcall_offset != 0) 5095 { 5096 /* Set the static chain register to *THIS. */ 5097 emit_move_insn (tmp, this_slot); 5098 emit_move_insn (tmp, gen_rtx_MEM (Pmode, tmp)); 5099 5100 /* Set ADDR to a legitimate address for *THIS + VCALL_OFFSET. */ 5101 addr = plus_constant (Pmode, tmp, vcall_offset); 5102 if (!m68k_legitimate_address_p (Pmode, addr, true)) 5103 { 5104 emit_insn (gen_rtx_SET (VOIDmode, tmp, addr)); 5105 addr = tmp; 5106 } 5107 5108 /* Load the offset into %d0 and add it to THIS. */ 5109 emit_move_insn (gen_rtx_REG (Pmode, D0_REG), 5110 gen_rtx_MEM (Pmode, addr)); 5111 emit_insn (gen_add3_insn (copy_rtx (this_slot), 5112 copy_rtx (this_slot), 5113 gen_rtx_REG (Pmode, D0_REG))); 5114 } 5115 5116 /* Jump to the target function. Use a sibcall if direct jumps are 5117 allowed, otherwise load the address into a register first. */ 5118 mem = DECL_RTL (function); 5119 if (!sibcall_operand (XEXP (mem, 0), VOIDmode)) 5120 { 5121 gcc_assert (flag_pic); 5122 5123 if (!TARGET_SEP_DATA) 5124 { 5125 /* Use the static chain register as a temporary (call-clobbered) 5126 GOT pointer for this function. We can use the static chain 5127 register because it isn't live on entry to the thunk. */ 5128 SET_REGNO (pic_offset_table_rtx, STATIC_CHAIN_REGNUM); 5129 emit_insn (gen_load_got (pic_offset_table_rtx)); 5130 } 5131 legitimize_pic_address (XEXP (mem, 0), Pmode, tmp); 5132 mem = replace_equiv_address (mem, tmp); 5133 } 5134 insn = emit_call_insn (gen_sibcall (mem, const0_rtx)); 5135 SIBLING_CALL_P (insn) = 1; 5136 5137 /* Run just enough of rest_of_compilation. */ 5138 insn = get_insns (); 5139 split_all_insns_noflow (); 5140 final_start_function (insn, file, 1); 5141 final (insn, file, 1); 5142 final_end_function (); 5143 5144 /* Clean up the vars set above. */ 5145 reload_completed = 0; 5146 5147 /* Restore the original PIC register. */ 5148 if (flag_pic) 5149 SET_REGNO (pic_offset_table_rtx, PIC_REG); 5150 } 5151 5152 /* Worker function for TARGET_STRUCT_VALUE_RTX. */ 5153 5154 static rtx 5155 m68k_struct_value_rtx (tree fntype ATTRIBUTE_UNUSED, 5156 int incoming ATTRIBUTE_UNUSED) 5157 { 5158 return gen_rtx_REG (Pmode, M68K_STRUCT_VALUE_REGNUM); 5159 } 5160 5161 /* Return nonzero if register old_reg can be renamed to register new_reg. */ 5162 int 5163 m68k_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, 5164 unsigned int new_reg) 5165 { 5166 5167 /* Interrupt functions can only use registers that have already been 5168 saved by the prologue, even if they would normally be 5169 call-clobbered. */ 5170 5171 if ((m68k_get_function_kind (current_function_decl) 5172 == m68k_fk_interrupt_handler) 5173 && !df_regs_ever_live_p (new_reg)) 5174 return 0; 5175 5176 return 1; 5177 } 5178 5179 /* Value is true if hard register REGNO can hold a value of machine-mode 5180 MODE. On the 68000, we let the cpu registers can hold any mode, but 5181 restrict the 68881 registers to floating-point modes. */ 5182 5183 bool 5184 m68k_regno_mode_ok (int regno, machine_mode mode) 5185 { 5186 if (DATA_REGNO_P (regno)) 5187 { 5188 /* Data Registers, can hold aggregate if fits in. */ 5189 if (regno + GET_MODE_SIZE (mode) / 4 <= 8) 5190 return true; 5191 } 5192 else if (ADDRESS_REGNO_P (regno)) 5193 { 5194 if (regno + GET_MODE_SIZE (mode) / 4 <= 16) 5195 return true; 5196 } 5197 else if (FP_REGNO_P (regno)) 5198 { 5199 /* FPU registers, hold float or complex float of long double or 5200 smaller. */ 5201 if ((GET_MODE_CLASS (mode) == MODE_FLOAT 5202 || GET_MODE_CLASS (mode) == MODE_COMPLEX_FLOAT) 5203 && GET_MODE_UNIT_SIZE (mode) <= TARGET_FP_REG_SIZE) 5204 return true; 5205 } 5206 return false; 5207 } 5208 5209 /* Implement SECONDARY_RELOAD_CLASS. */ 5210 5211 enum reg_class 5212 m68k_secondary_reload_class (enum reg_class rclass, 5213 machine_mode mode, rtx x) 5214 { 5215 int regno; 5216 5217 regno = true_regnum (x); 5218 5219 /* If one operand of a movqi is an address register, the other 5220 operand must be a general register or constant. Other types 5221 of operand must be reloaded through a data register. */ 5222 if (GET_MODE_SIZE (mode) == 1 5223 && reg_classes_intersect_p (rclass, ADDR_REGS) 5224 && !(INT_REGNO_P (regno) || CONSTANT_P (x))) 5225 return DATA_REGS; 5226 5227 /* PC-relative addresses must be loaded into an address register first. */ 5228 if (TARGET_PCREL 5229 && !reg_class_subset_p (rclass, ADDR_REGS) 5230 && symbolic_operand (x, VOIDmode)) 5231 return ADDR_REGS; 5232 5233 return NO_REGS; 5234 } 5235 5236 /* Implement PREFERRED_RELOAD_CLASS. */ 5237 5238 enum reg_class 5239 m68k_preferred_reload_class (rtx x, enum reg_class rclass) 5240 { 5241 enum reg_class secondary_class; 5242 5243 /* If RCLASS might need a secondary reload, try restricting it to 5244 a class that doesn't. */ 5245 secondary_class = m68k_secondary_reload_class (rclass, GET_MODE (x), x); 5246 if (secondary_class != NO_REGS 5247 && reg_class_subset_p (secondary_class, rclass)) 5248 return secondary_class; 5249 5250 /* Prefer to use moveq for in-range constants. */ 5251 if (GET_CODE (x) == CONST_INT 5252 && reg_class_subset_p (DATA_REGS, rclass) 5253 && IN_RANGE (INTVAL (x), -0x80, 0x7f)) 5254 return DATA_REGS; 5255 5256 /* ??? Do we really need this now? */ 5257 if (GET_CODE (x) == CONST_DOUBLE 5258 && GET_MODE_CLASS (GET_MODE (x)) == MODE_FLOAT) 5259 { 5260 if (TARGET_HARD_FLOAT && reg_class_subset_p (FP_REGS, rclass)) 5261 return FP_REGS; 5262 5263 return NO_REGS; 5264 } 5265 5266 return rclass; 5267 } 5268 5269 /* Return floating point values in a 68881 register. This makes 68881 code 5270 a little bit faster. It also makes -msoft-float code incompatible with 5271 hard-float code, so people have to be careful not to mix the two. 5272 For ColdFire it was decided the ABI incompatibility is undesirable. 5273 If there is need for a hard-float ABI it is probably worth doing it 5274 properly and also passing function arguments in FP registers. */ 5275 rtx 5276 m68k_libcall_value (machine_mode mode) 5277 { 5278 switch (mode) { 5279 case SFmode: 5280 case DFmode: 5281 case XFmode: 5282 if (TARGET_68881) 5283 return gen_rtx_REG (mode, FP0_REG); 5284 break; 5285 default: 5286 break; 5287 } 5288 5289 return gen_rtx_REG (mode, m68k_libcall_value_in_a0_p ? A0_REG : D0_REG); 5290 } 5291 5292 /* Location in which function value is returned. 5293 NOTE: Due to differences in ABIs, don't call this function directly, 5294 use FUNCTION_VALUE instead. */ 5295 rtx 5296 m68k_function_value (const_tree valtype, const_tree func ATTRIBUTE_UNUSED) 5297 { 5298 machine_mode mode; 5299 5300 mode = TYPE_MODE (valtype); 5301 switch (mode) { 5302 case SFmode: 5303 case DFmode: 5304 case XFmode: 5305 if (TARGET_68881) 5306 return gen_rtx_REG (mode, FP0_REG); 5307 break; 5308 default: 5309 break; 5310 } 5311 5312 /* If the function returns a pointer, push that into %a0. */ 5313 if (func && POINTER_TYPE_P (TREE_TYPE (TREE_TYPE (func)))) 5314 /* For compatibility with the large body of existing code which 5315 does not always properly declare external functions returning 5316 pointer types, the m68k/SVR4 convention is to copy the value 5317 returned for pointer functions from a0 to d0 in the function 5318 epilogue, so that callers that have neglected to properly 5319 declare the callee can still find the correct return value in 5320 d0. */ 5321 return gen_rtx_PARALLEL 5322 (mode, 5323 gen_rtvec (2, 5324 gen_rtx_EXPR_LIST (VOIDmode, 5325 gen_rtx_REG (mode, A0_REG), 5326 const0_rtx), 5327 gen_rtx_EXPR_LIST (VOIDmode, 5328 gen_rtx_REG (mode, D0_REG), 5329 const0_rtx))); 5330 else if (POINTER_TYPE_P (valtype)) 5331 return gen_rtx_REG (mode, A0_REG); 5332 else 5333 return gen_rtx_REG (mode, D0_REG); 5334 } 5335 5336 /* Worker function for TARGET_RETURN_IN_MEMORY. */ 5337 #if M68K_HONOR_TARGET_STRICT_ALIGNMENT 5338 static bool 5339 m68k_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 5340 { 5341 machine_mode mode = TYPE_MODE (type); 5342 5343 if (mode == BLKmode) 5344 return true; 5345 5346 /* If TYPE's known alignment is less than the alignment of MODE that 5347 would contain the structure, then return in memory. We need to 5348 do so to maintain the compatibility between code compiled with 5349 -mstrict-align and that compiled with -mno-strict-align. */ 5350 if (AGGREGATE_TYPE_P (type) 5351 && TYPE_ALIGN (type) < GET_MODE_ALIGNMENT (mode)) 5352 return true; 5353 5354 return false; 5355 } 5356 #endif 5357 5358 /* CPU to schedule the program for. */ 5359 enum attr_cpu m68k_sched_cpu; 5360 5361 /* MAC to schedule the program for. */ 5362 enum attr_mac m68k_sched_mac; 5363 5364 /* Operand type. */ 5365 enum attr_op_type 5366 { 5367 /* No operand. */ 5368 OP_TYPE_NONE, 5369 5370 /* Integer register. */ 5371 OP_TYPE_RN, 5372 5373 /* FP register. */ 5374 OP_TYPE_FPN, 5375 5376 /* Implicit mem reference (e.g. stack). */ 5377 OP_TYPE_MEM1, 5378 5379 /* Memory without offset or indexing. EA modes 2, 3 and 4. */ 5380 OP_TYPE_MEM234, 5381 5382 /* Memory with offset but without indexing. EA mode 5. */ 5383 OP_TYPE_MEM5, 5384 5385 /* Memory with indexing. EA mode 6. */ 5386 OP_TYPE_MEM6, 5387 5388 /* Memory referenced by absolute address. EA mode 7. */ 5389 OP_TYPE_MEM7, 5390 5391 /* Immediate operand that doesn't require extension word. */ 5392 OP_TYPE_IMM_Q, 5393 5394 /* Immediate 16 bit operand. */ 5395 OP_TYPE_IMM_W, 5396 5397 /* Immediate 32 bit operand. */ 5398 OP_TYPE_IMM_L 5399 }; 5400 5401 /* Return type of memory ADDR_RTX refers to. */ 5402 static enum attr_op_type 5403 sched_address_type (machine_mode mode, rtx addr_rtx) 5404 { 5405 struct m68k_address address; 5406 5407 if (symbolic_operand (addr_rtx, VOIDmode)) 5408 return OP_TYPE_MEM7; 5409 5410 if (!m68k_decompose_address (mode, addr_rtx, 5411 reload_completed, &address)) 5412 { 5413 gcc_assert (!reload_completed); 5414 /* Reload will likely fix the address to be in the register. */ 5415 return OP_TYPE_MEM234; 5416 } 5417 5418 if (address.scale != 0) 5419 return OP_TYPE_MEM6; 5420 5421 if (address.base != NULL_RTX) 5422 { 5423 if (address.offset == NULL_RTX) 5424 return OP_TYPE_MEM234; 5425 5426 return OP_TYPE_MEM5; 5427 } 5428 5429 gcc_assert (address.offset != NULL_RTX); 5430 5431 return OP_TYPE_MEM7; 5432 } 5433 5434 /* Return X or Y (depending on OPX_P) operand of INSN. */ 5435 static rtx 5436 sched_get_operand (rtx_insn *insn, bool opx_p) 5437 { 5438 int i; 5439 5440 if (recog_memoized (insn) < 0) 5441 gcc_unreachable (); 5442 5443 extract_constrain_insn_cached (insn); 5444 5445 if (opx_p) 5446 i = get_attr_opx (insn); 5447 else 5448 i = get_attr_opy (insn); 5449 5450 if (i >= recog_data.n_operands) 5451 return NULL; 5452 5453 return recog_data.operand[i]; 5454 } 5455 5456 /* Return type of INSN's operand X (if OPX_P) or operand Y (if !OPX_P). 5457 If ADDRESS_P is true, return type of memory location operand refers to. */ 5458 static enum attr_op_type 5459 sched_attr_op_type (rtx_insn *insn, bool opx_p, bool address_p) 5460 { 5461 rtx op; 5462 5463 op = sched_get_operand (insn, opx_p); 5464 5465 if (op == NULL) 5466 { 5467 gcc_assert (!reload_completed); 5468 return OP_TYPE_RN; 5469 } 5470 5471 if (address_p) 5472 return sched_address_type (QImode, op); 5473 5474 if (memory_operand (op, VOIDmode)) 5475 return sched_address_type (GET_MODE (op), XEXP (op, 0)); 5476 5477 if (register_operand (op, VOIDmode)) 5478 { 5479 if ((!reload_completed && FLOAT_MODE_P (GET_MODE (op))) 5480 || (reload_completed && FP_REG_P (op))) 5481 return OP_TYPE_FPN; 5482 5483 return OP_TYPE_RN; 5484 } 5485 5486 if (GET_CODE (op) == CONST_INT) 5487 { 5488 int ival; 5489 5490 ival = INTVAL (op); 5491 5492 /* Check for quick constants. */ 5493 switch (get_attr_type (insn)) 5494 { 5495 case TYPE_ALUQ_L: 5496 if (IN_RANGE (ival, 1, 8) || IN_RANGE (ival, -8, -1)) 5497 return OP_TYPE_IMM_Q; 5498 5499 gcc_assert (!reload_completed); 5500 break; 5501 5502 case TYPE_MOVEQ_L: 5503 if (USE_MOVQ (ival)) 5504 return OP_TYPE_IMM_Q; 5505 5506 gcc_assert (!reload_completed); 5507 break; 5508 5509 case TYPE_MOV3Q_L: 5510 if (valid_mov3q_const (ival)) 5511 return OP_TYPE_IMM_Q; 5512 5513 gcc_assert (!reload_completed); 5514 break; 5515 5516 default: 5517 break; 5518 } 5519 5520 if (IN_RANGE (ival, -0x8000, 0x7fff)) 5521 return OP_TYPE_IMM_W; 5522 5523 return OP_TYPE_IMM_L; 5524 } 5525 5526 if (GET_CODE (op) == CONST_DOUBLE) 5527 { 5528 switch (GET_MODE (op)) 5529 { 5530 case SFmode: 5531 return OP_TYPE_IMM_W; 5532 5533 case VOIDmode: 5534 case DFmode: 5535 return OP_TYPE_IMM_L; 5536 5537 default: 5538 gcc_unreachable (); 5539 } 5540 } 5541 5542 if (GET_CODE (op) == CONST 5543 || symbolic_operand (op, VOIDmode) 5544 || LABEL_P (op)) 5545 { 5546 switch (GET_MODE (op)) 5547 { 5548 case QImode: 5549 return OP_TYPE_IMM_Q; 5550 5551 case HImode: 5552 return OP_TYPE_IMM_W; 5553 5554 case SImode: 5555 return OP_TYPE_IMM_L; 5556 5557 default: 5558 if (symbolic_operand (m68k_unwrap_symbol (op, false), VOIDmode)) 5559 /* Just a guess. */ 5560 return OP_TYPE_IMM_W; 5561 5562 return OP_TYPE_IMM_L; 5563 } 5564 } 5565 5566 gcc_assert (!reload_completed); 5567 5568 if (FLOAT_MODE_P (GET_MODE (op))) 5569 return OP_TYPE_FPN; 5570 5571 return OP_TYPE_RN; 5572 } 5573 5574 /* Implement opx_type attribute. 5575 Return type of INSN's operand X. 5576 If ADDRESS_P is true, return type of memory location operand refers to. */ 5577 enum attr_opx_type 5578 m68k_sched_attr_opx_type (rtx_insn *insn, int address_p) 5579 { 5580 switch (sched_attr_op_type (insn, true, address_p != 0)) 5581 { 5582 case OP_TYPE_RN: 5583 return OPX_TYPE_RN; 5584 5585 case OP_TYPE_FPN: 5586 return OPX_TYPE_FPN; 5587 5588 case OP_TYPE_MEM1: 5589 return OPX_TYPE_MEM1; 5590 5591 case OP_TYPE_MEM234: 5592 return OPX_TYPE_MEM234; 5593 5594 case OP_TYPE_MEM5: 5595 return OPX_TYPE_MEM5; 5596 5597 case OP_TYPE_MEM6: 5598 return OPX_TYPE_MEM6; 5599 5600 case OP_TYPE_MEM7: 5601 return OPX_TYPE_MEM7; 5602 5603 case OP_TYPE_IMM_Q: 5604 return OPX_TYPE_IMM_Q; 5605 5606 case OP_TYPE_IMM_W: 5607 return OPX_TYPE_IMM_W; 5608 5609 case OP_TYPE_IMM_L: 5610 return OPX_TYPE_IMM_L; 5611 5612 default: 5613 gcc_unreachable (); 5614 } 5615 } 5616 5617 /* Implement opy_type attribute. 5618 Return type of INSN's operand Y. 5619 If ADDRESS_P is true, return type of memory location operand refers to. */ 5620 enum attr_opy_type 5621 m68k_sched_attr_opy_type (rtx_insn *insn, int address_p) 5622 { 5623 switch (sched_attr_op_type (insn, false, address_p != 0)) 5624 { 5625 case OP_TYPE_RN: 5626 return OPY_TYPE_RN; 5627 5628 case OP_TYPE_FPN: 5629 return OPY_TYPE_FPN; 5630 5631 case OP_TYPE_MEM1: 5632 return OPY_TYPE_MEM1; 5633 5634 case OP_TYPE_MEM234: 5635 return OPY_TYPE_MEM234; 5636 5637 case OP_TYPE_MEM5: 5638 return OPY_TYPE_MEM5; 5639 5640 case OP_TYPE_MEM6: 5641 return OPY_TYPE_MEM6; 5642 5643 case OP_TYPE_MEM7: 5644 return OPY_TYPE_MEM7; 5645 5646 case OP_TYPE_IMM_Q: 5647 return OPY_TYPE_IMM_Q; 5648 5649 case OP_TYPE_IMM_W: 5650 return OPY_TYPE_IMM_W; 5651 5652 case OP_TYPE_IMM_L: 5653 return OPY_TYPE_IMM_L; 5654 5655 default: 5656 gcc_unreachable (); 5657 } 5658 } 5659 5660 /* Return size of INSN as int. */ 5661 static int 5662 sched_get_attr_size_int (rtx_insn *insn) 5663 { 5664 int size; 5665 5666 switch (get_attr_type (insn)) 5667 { 5668 case TYPE_IGNORE: 5669 /* There should be no references to m68k_sched_attr_size for 'ignore' 5670 instructions. */ 5671 gcc_unreachable (); 5672 return 0; 5673 5674 case TYPE_MUL_L: 5675 size = 2; 5676 break; 5677 5678 default: 5679 size = 1; 5680 break; 5681 } 5682 5683 switch (get_attr_opx_type (insn)) 5684 { 5685 case OPX_TYPE_NONE: 5686 case OPX_TYPE_RN: 5687 case OPX_TYPE_FPN: 5688 case OPX_TYPE_MEM1: 5689 case OPX_TYPE_MEM234: 5690 case OPY_TYPE_IMM_Q: 5691 break; 5692 5693 case OPX_TYPE_MEM5: 5694 case OPX_TYPE_MEM6: 5695 /* Here we assume that most absolute references are short. */ 5696 case OPX_TYPE_MEM7: 5697 case OPY_TYPE_IMM_W: 5698 ++size; 5699 break; 5700 5701 case OPY_TYPE_IMM_L: 5702 size += 2; 5703 break; 5704 5705 default: 5706 gcc_unreachable (); 5707 } 5708 5709 switch (get_attr_opy_type (insn)) 5710 { 5711 case OPY_TYPE_NONE: 5712 case OPY_TYPE_RN: 5713 case OPY_TYPE_FPN: 5714 case OPY_TYPE_MEM1: 5715 case OPY_TYPE_MEM234: 5716 case OPY_TYPE_IMM_Q: 5717 break; 5718 5719 case OPY_TYPE_MEM5: 5720 case OPY_TYPE_MEM6: 5721 /* Here we assume that most absolute references are short. */ 5722 case OPY_TYPE_MEM7: 5723 case OPY_TYPE_IMM_W: 5724 ++size; 5725 break; 5726 5727 case OPY_TYPE_IMM_L: 5728 size += 2; 5729 break; 5730 5731 default: 5732 gcc_unreachable (); 5733 } 5734 5735 if (size > 3) 5736 { 5737 gcc_assert (!reload_completed); 5738 5739 size = 3; 5740 } 5741 5742 return size; 5743 } 5744 5745 /* Return size of INSN as attribute enum value. */ 5746 enum attr_size 5747 m68k_sched_attr_size (rtx_insn *insn) 5748 { 5749 switch (sched_get_attr_size_int (insn)) 5750 { 5751 case 1: 5752 return SIZE_1; 5753 5754 case 2: 5755 return SIZE_2; 5756 5757 case 3: 5758 return SIZE_3; 5759 5760 default: 5761 gcc_unreachable (); 5762 } 5763 } 5764 5765 /* Return operand X or Y (depending on OPX_P) of INSN, 5766 if it is a MEM, or NULL overwise. */ 5767 static enum attr_op_type 5768 sched_get_opxy_mem_type (rtx_insn *insn, bool opx_p) 5769 { 5770 if (opx_p) 5771 { 5772 switch (get_attr_opx_type (insn)) 5773 { 5774 case OPX_TYPE_NONE: 5775 case OPX_TYPE_RN: 5776 case OPX_TYPE_FPN: 5777 case OPX_TYPE_IMM_Q: 5778 case OPX_TYPE_IMM_W: 5779 case OPX_TYPE_IMM_L: 5780 return OP_TYPE_RN; 5781 5782 case OPX_TYPE_MEM1: 5783 case OPX_TYPE_MEM234: 5784 case OPX_TYPE_MEM5: 5785 case OPX_TYPE_MEM7: 5786 return OP_TYPE_MEM1; 5787 5788 case OPX_TYPE_MEM6: 5789 return OP_TYPE_MEM6; 5790 5791 default: 5792 gcc_unreachable (); 5793 } 5794 } 5795 else 5796 { 5797 switch (get_attr_opy_type (insn)) 5798 { 5799 case OPY_TYPE_NONE: 5800 case OPY_TYPE_RN: 5801 case OPY_TYPE_FPN: 5802 case OPY_TYPE_IMM_Q: 5803 case OPY_TYPE_IMM_W: 5804 case OPY_TYPE_IMM_L: 5805 return OP_TYPE_RN; 5806 5807 case OPY_TYPE_MEM1: 5808 case OPY_TYPE_MEM234: 5809 case OPY_TYPE_MEM5: 5810 case OPY_TYPE_MEM7: 5811 return OP_TYPE_MEM1; 5812 5813 case OPY_TYPE_MEM6: 5814 return OP_TYPE_MEM6; 5815 5816 default: 5817 gcc_unreachable (); 5818 } 5819 } 5820 } 5821 5822 /* Implement op_mem attribute. */ 5823 enum attr_op_mem 5824 m68k_sched_attr_op_mem (rtx_insn *insn) 5825 { 5826 enum attr_op_type opx; 5827 enum attr_op_type opy; 5828 5829 opx = sched_get_opxy_mem_type (insn, true); 5830 opy = sched_get_opxy_mem_type (insn, false); 5831 5832 if (opy == OP_TYPE_RN && opx == OP_TYPE_RN) 5833 return OP_MEM_00; 5834 5835 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM1) 5836 { 5837 switch (get_attr_opx_access (insn)) 5838 { 5839 case OPX_ACCESS_R: 5840 return OP_MEM_10; 5841 5842 case OPX_ACCESS_W: 5843 return OP_MEM_01; 5844 5845 case OPX_ACCESS_RW: 5846 return OP_MEM_11; 5847 5848 default: 5849 gcc_unreachable (); 5850 } 5851 } 5852 5853 if (opy == OP_TYPE_RN && opx == OP_TYPE_MEM6) 5854 { 5855 switch (get_attr_opx_access (insn)) 5856 { 5857 case OPX_ACCESS_R: 5858 return OP_MEM_I0; 5859 5860 case OPX_ACCESS_W: 5861 return OP_MEM_0I; 5862 5863 case OPX_ACCESS_RW: 5864 return OP_MEM_I1; 5865 5866 default: 5867 gcc_unreachable (); 5868 } 5869 } 5870 5871 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_RN) 5872 return OP_MEM_10; 5873 5874 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM1) 5875 { 5876 switch (get_attr_opx_access (insn)) 5877 { 5878 case OPX_ACCESS_W: 5879 return OP_MEM_11; 5880 5881 default: 5882 gcc_assert (!reload_completed); 5883 return OP_MEM_11; 5884 } 5885 } 5886 5887 if (opy == OP_TYPE_MEM1 && opx == OP_TYPE_MEM6) 5888 { 5889 switch (get_attr_opx_access (insn)) 5890 { 5891 case OPX_ACCESS_W: 5892 return OP_MEM_1I; 5893 5894 default: 5895 gcc_assert (!reload_completed); 5896 return OP_MEM_1I; 5897 } 5898 } 5899 5900 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_RN) 5901 return OP_MEM_I0; 5902 5903 if (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM1) 5904 { 5905 switch (get_attr_opx_access (insn)) 5906 { 5907 case OPX_ACCESS_W: 5908 return OP_MEM_I1; 5909 5910 default: 5911 gcc_assert (!reload_completed); 5912 return OP_MEM_I1; 5913 } 5914 } 5915 5916 gcc_assert (opy == OP_TYPE_MEM6 && opx == OP_TYPE_MEM6); 5917 gcc_assert (!reload_completed); 5918 return OP_MEM_I1; 5919 } 5920 5921 /* Data for ColdFire V4 index bypass. 5922 Producer modifies register that is used as index in consumer with 5923 specified scale. */ 5924 static struct 5925 { 5926 /* Producer instruction. */ 5927 rtx pro; 5928 5929 /* Consumer instruction. */ 5930 rtx con; 5931 5932 /* Scale of indexed memory access within consumer. 5933 Or zero if bypass should not be effective at the moment. */ 5934 int scale; 5935 } sched_cfv4_bypass_data; 5936 5937 /* An empty state that is used in m68k_sched_adjust_cost. */ 5938 static state_t sched_adjust_cost_state; 5939 5940 /* Implement adjust_cost scheduler hook. 5941 Return adjusted COST of dependency LINK between DEF_INSN and INSN. */ 5942 static int 5943 m68k_sched_adjust_cost (rtx_insn *insn, rtx link ATTRIBUTE_UNUSED, 5944 rtx_insn *def_insn, int cost) 5945 { 5946 int delay; 5947 5948 if (recog_memoized (def_insn) < 0 5949 || recog_memoized (insn) < 0) 5950 return cost; 5951 5952 if (sched_cfv4_bypass_data.scale == 1) 5953 /* Handle ColdFire V4 bypass for indexed address with 1x scale. */ 5954 { 5955 /* haifa-sched.c: insn_cost () calls bypass_p () just before 5956 targetm.sched.adjust_cost (). Hence, we can be relatively sure 5957 that the data in sched_cfv4_bypass_data is up to date. */ 5958 gcc_assert (sched_cfv4_bypass_data.pro == def_insn 5959 && sched_cfv4_bypass_data.con == insn); 5960 5961 if (cost < 3) 5962 cost = 3; 5963 5964 sched_cfv4_bypass_data.pro = NULL; 5965 sched_cfv4_bypass_data.con = NULL; 5966 sched_cfv4_bypass_data.scale = 0; 5967 } 5968 else 5969 gcc_assert (sched_cfv4_bypass_data.pro == NULL 5970 && sched_cfv4_bypass_data.con == NULL 5971 && sched_cfv4_bypass_data.scale == 0); 5972 5973 /* Don't try to issue INSN earlier than DFA permits. 5974 This is especially useful for instructions that write to memory, 5975 as their true dependence (default) latency is better to be set to 0 5976 to workaround alias analysis limitations. 5977 This is, in fact, a machine independent tweak, so, probably, 5978 it should be moved to haifa-sched.c: insn_cost (). */ 5979 delay = min_insn_conflict_delay (sched_adjust_cost_state, def_insn, insn); 5980 if (delay > cost) 5981 cost = delay; 5982 5983 return cost; 5984 } 5985 5986 /* Return maximal number of insns that can be scheduled on a single cycle. */ 5987 static int 5988 m68k_sched_issue_rate (void) 5989 { 5990 switch (m68k_sched_cpu) 5991 { 5992 case CPU_CFV1: 5993 case CPU_CFV2: 5994 case CPU_CFV3: 5995 return 1; 5996 5997 case CPU_CFV4: 5998 return 2; 5999 6000 default: 6001 gcc_unreachable (); 6002 return 0; 6003 } 6004 } 6005 6006 /* Maximal length of instruction for current CPU. 6007 E.g. it is 3 for any ColdFire core. */ 6008 static int max_insn_size; 6009 6010 /* Data to model instruction buffer of CPU. */ 6011 struct _sched_ib 6012 { 6013 /* True if instruction buffer model is modeled for current CPU. */ 6014 bool enabled_p; 6015 6016 /* Size of the instruction buffer in words. */ 6017 int size; 6018 6019 /* Number of filled words in the instruction buffer. */ 6020 int filled; 6021 6022 /* Additional information about instruction buffer for CPUs that have 6023 a buffer of instruction records, rather then a plain buffer 6024 of instruction words. */ 6025 struct _sched_ib_records 6026 { 6027 /* Size of buffer in records. */ 6028 int n_insns; 6029 6030 /* Array to hold data on adjustements made to the size of the buffer. */ 6031 int *adjust; 6032 6033 /* Index of the above array. */ 6034 int adjust_index; 6035 } records; 6036 6037 /* An insn that reserves (marks empty) one word in the instruction buffer. */ 6038 rtx insn; 6039 }; 6040 6041 static struct _sched_ib sched_ib; 6042 6043 /* ID of memory unit. */ 6044 static int sched_mem_unit_code; 6045 6046 /* Implementation of the targetm.sched.variable_issue () hook. 6047 It is called after INSN was issued. It returns the number of insns 6048 that can possibly get scheduled on the current cycle. 6049 It is used here to determine the effect of INSN on the instruction 6050 buffer. */ 6051 static int 6052 m68k_sched_variable_issue (FILE *sched_dump ATTRIBUTE_UNUSED, 6053 int sched_verbose ATTRIBUTE_UNUSED, 6054 rtx_insn *insn, int can_issue_more) 6055 { 6056 int insn_size; 6057 6058 if (recog_memoized (insn) >= 0 && get_attr_type (insn) != TYPE_IGNORE) 6059 { 6060 switch (m68k_sched_cpu) 6061 { 6062 case CPU_CFV1: 6063 case CPU_CFV2: 6064 insn_size = sched_get_attr_size_int (insn); 6065 break; 6066 6067 case CPU_CFV3: 6068 insn_size = sched_get_attr_size_int (insn); 6069 6070 /* ColdFire V3 and V4 cores have instruction buffers that can 6071 accumulate up to 8 instructions regardless of instructions' 6072 sizes. So we should take care not to "prefetch" 24 one-word 6073 or 12 two-words instructions. 6074 To model this behavior we temporarily decrease size of the 6075 buffer by (max_insn_size - insn_size) for next 7 instructions. */ 6076 { 6077 int adjust; 6078 6079 adjust = max_insn_size - insn_size; 6080 sched_ib.size -= adjust; 6081 6082 if (sched_ib.filled > sched_ib.size) 6083 sched_ib.filled = sched_ib.size; 6084 6085 sched_ib.records.adjust[sched_ib.records.adjust_index] = adjust; 6086 } 6087 6088 ++sched_ib.records.adjust_index; 6089 if (sched_ib.records.adjust_index == sched_ib.records.n_insns) 6090 sched_ib.records.adjust_index = 0; 6091 6092 /* Undo adjustement we did 7 instructions ago. */ 6093 sched_ib.size 6094 += sched_ib.records.adjust[sched_ib.records.adjust_index]; 6095 6096 break; 6097 6098 case CPU_CFV4: 6099 gcc_assert (!sched_ib.enabled_p); 6100 insn_size = 0; 6101 break; 6102 6103 default: 6104 gcc_unreachable (); 6105 } 6106 6107 if (insn_size > sched_ib.filled) 6108 /* Scheduling for register pressure does not always take DFA into 6109 account. Workaround instruction buffer not being filled enough. */ 6110 { 6111 gcc_assert (sched_pressure == SCHED_PRESSURE_WEIGHTED); 6112 insn_size = sched_ib.filled; 6113 } 6114 6115 --can_issue_more; 6116 } 6117 else if (GET_CODE (PATTERN (insn)) == ASM_INPUT 6118 || asm_noperands (PATTERN (insn)) >= 0) 6119 insn_size = sched_ib.filled; 6120 else 6121 insn_size = 0; 6122 6123 sched_ib.filled -= insn_size; 6124 6125 return can_issue_more; 6126 } 6127 6128 /* Return how many instructions should scheduler lookahead to choose the 6129 best one. */ 6130 static int 6131 m68k_sched_first_cycle_multipass_dfa_lookahead (void) 6132 { 6133 return m68k_sched_issue_rate () - 1; 6134 } 6135 6136 /* Implementation of targetm.sched.init_global () hook. 6137 It is invoked once per scheduling pass and is used here 6138 to initialize scheduler constants. */ 6139 static void 6140 m68k_sched_md_init_global (FILE *sched_dump ATTRIBUTE_UNUSED, 6141 int sched_verbose ATTRIBUTE_UNUSED, 6142 int n_insns ATTRIBUTE_UNUSED) 6143 { 6144 #ifdef ENABLE_CHECKING 6145 /* Check that all instructions have DFA reservations and 6146 that all instructions can be issued from a clean state. */ 6147 { 6148 rtx_insn *insn; 6149 state_t state; 6150 6151 state = alloca (state_size ()); 6152 6153 for (insn = get_insns (); insn != NULL; insn = NEXT_INSN (insn)) 6154 { 6155 if (INSN_P (insn) && recog_memoized (insn) >= 0) 6156 { 6157 gcc_assert (insn_has_dfa_reservation_p (insn)); 6158 6159 state_reset (state); 6160 if (state_transition (state, insn) >= 0) 6161 gcc_unreachable (); 6162 } 6163 } 6164 } 6165 #endif 6166 6167 /* Setup target cpu. */ 6168 6169 /* ColdFire V4 has a set of features to keep its instruction buffer full 6170 (e.g., a separate memory bus for instructions) and, hence, we do not model 6171 buffer for this CPU. */ 6172 sched_ib.enabled_p = (m68k_sched_cpu != CPU_CFV4); 6173 6174 switch (m68k_sched_cpu) 6175 { 6176 case CPU_CFV4: 6177 sched_ib.filled = 0; 6178 6179 /* FALLTHRU */ 6180 6181 case CPU_CFV1: 6182 case CPU_CFV2: 6183 max_insn_size = 3; 6184 sched_ib.records.n_insns = 0; 6185 sched_ib.records.adjust = NULL; 6186 break; 6187 6188 case CPU_CFV3: 6189 max_insn_size = 3; 6190 sched_ib.records.n_insns = 8; 6191 sched_ib.records.adjust = XNEWVEC (int, sched_ib.records.n_insns); 6192 break; 6193 6194 default: 6195 gcc_unreachable (); 6196 } 6197 6198 sched_mem_unit_code = get_cpu_unit_code ("cf_mem1"); 6199 6200 sched_adjust_cost_state = xmalloc (state_size ()); 6201 state_reset (sched_adjust_cost_state); 6202 6203 start_sequence (); 6204 emit_insn (gen_ib ()); 6205 sched_ib.insn = get_insns (); 6206 end_sequence (); 6207 } 6208 6209 /* Scheduling pass is now finished. Free/reset static variables. */ 6210 static void 6211 m68k_sched_md_finish_global (FILE *dump ATTRIBUTE_UNUSED, 6212 int verbose ATTRIBUTE_UNUSED) 6213 { 6214 sched_ib.insn = NULL; 6215 6216 free (sched_adjust_cost_state); 6217 sched_adjust_cost_state = NULL; 6218 6219 sched_mem_unit_code = 0; 6220 6221 free (sched_ib.records.adjust); 6222 sched_ib.records.adjust = NULL; 6223 sched_ib.records.n_insns = 0; 6224 max_insn_size = 0; 6225 } 6226 6227 /* Implementation of targetm.sched.init () hook. 6228 It is invoked each time scheduler starts on the new block (basic block or 6229 extended basic block). */ 6230 static void 6231 m68k_sched_md_init (FILE *sched_dump ATTRIBUTE_UNUSED, 6232 int sched_verbose ATTRIBUTE_UNUSED, 6233 int n_insns ATTRIBUTE_UNUSED) 6234 { 6235 switch (m68k_sched_cpu) 6236 { 6237 case CPU_CFV1: 6238 case CPU_CFV2: 6239 sched_ib.size = 6; 6240 break; 6241 6242 case CPU_CFV3: 6243 sched_ib.size = sched_ib.records.n_insns * max_insn_size; 6244 6245 memset (sched_ib.records.adjust, 0, 6246 sched_ib.records.n_insns * sizeof (*sched_ib.records.adjust)); 6247 sched_ib.records.adjust_index = 0; 6248 break; 6249 6250 case CPU_CFV4: 6251 gcc_assert (!sched_ib.enabled_p); 6252 sched_ib.size = 0; 6253 break; 6254 6255 default: 6256 gcc_unreachable (); 6257 } 6258 6259 if (sched_ib.enabled_p) 6260 /* haifa-sched.c: schedule_block () calls advance_cycle () just before 6261 the first cycle. Workaround that. */ 6262 sched_ib.filled = -2; 6263 } 6264 6265 /* Implementation of targetm.sched.dfa_pre_advance_cycle () hook. 6266 It is invoked just before current cycle finishes and is used here 6267 to track if instruction buffer got its two words this cycle. */ 6268 static void 6269 m68k_sched_dfa_pre_advance_cycle (void) 6270 { 6271 if (!sched_ib.enabled_p) 6272 return; 6273 6274 if (!cpu_unit_reservation_p (curr_state, sched_mem_unit_code)) 6275 { 6276 sched_ib.filled += 2; 6277 6278 if (sched_ib.filled > sched_ib.size) 6279 sched_ib.filled = sched_ib.size; 6280 } 6281 } 6282 6283 /* Implementation of targetm.sched.dfa_post_advance_cycle () hook. 6284 It is invoked just after new cycle begins and is used here 6285 to setup number of filled words in the instruction buffer so that 6286 instructions which won't have all their words prefetched would be 6287 stalled for a cycle. */ 6288 static void 6289 m68k_sched_dfa_post_advance_cycle (void) 6290 { 6291 int i; 6292 6293 if (!sched_ib.enabled_p) 6294 return; 6295 6296 /* Setup number of prefetched instruction words in the instruction 6297 buffer. */ 6298 i = max_insn_size - sched_ib.filled; 6299 6300 while (--i >= 0) 6301 { 6302 if (state_transition (curr_state, sched_ib.insn) >= 0) 6303 /* Pick up scheduler state. */ 6304 ++sched_ib.filled; 6305 } 6306 } 6307 6308 /* Return X or Y (depending on OPX_P) operand of INSN, 6309 if it is an integer register, or NULL overwise. */ 6310 static rtx 6311 sched_get_reg_operand (rtx_insn *insn, bool opx_p) 6312 { 6313 rtx op = NULL; 6314 6315 if (opx_p) 6316 { 6317 if (get_attr_opx_type (insn) == OPX_TYPE_RN) 6318 { 6319 op = sched_get_operand (insn, true); 6320 gcc_assert (op != NULL); 6321 6322 if (!reload_completed && !REG_P (op)) 6323 return NULL; 6324 } 6325 } 6326 else 6327 { 6328 if (get_attr_opy_type (insn) == OPY_TYPE_RN) 6329 { 6330 op = sched_get_operand (insn, false); 6331 gcc_assert (op != NULL); 6332 6333 if (!reload_completed && !REG_P (op)) 6334 return NULL; 6335 } 6336 } 6337 6338 return op; 6339 } 6340 6341 /* Return true, if X or Y (depending on OPX_P) operand of INSN 6342 is a MEM. */ 6343 static bool 6344 sched_mem_operand_p (rtx_insn *insn, bool opx_p) 6345 { 6346 switch (sched_get_opxy_mem_type (insn, opx_p)) 6347 { 6348 case OP_TYPE_MEM1: 6349 case OP_TYPE_MEM6: 6350 return true; 6351 6352 default: 6353 return false; 6354 } 6355 } 6356 6357 /* Return X or Y (depending on OPX_P) operand of INSN, 6358 if it is a MEM, or NULL overwise. */ 6359 static rtx 6360 sched_get_mem_operand (rtx_insn *insn, bool must_read_p, bool must_write_p) 6361 { 6362 bool opx_p; 6363 bool opy_p; 6364 6365 opx_p = false; 6366 opy_p = false; 6367 6368 if (must_read_p) 6369 { 6370 opx_p = true; 6371 opy_p = true; 6372 } 6373 6374 if (must_write_p) 6375 { 6376 opx_p = true; 6377 opy_p = false; 6378 } 6379 6380 if (opy_p && sched_mem_operand_p (insn, false)) 6381 return sched_get_operand (insn, false); 6382 6383 if (opx_p && sched_mem_operand_p (insn, true)) 6384 return sched_get_operand (insn, true); 6385 6386 gcc_unreachable (); 6387 return NULL; 6388 } 6389 6390 /* Return non-zero if PRO modifies register used as part of 6391 address in CON. */ 6392 int 6393 m68k_sched_address_bypass_p (rtx_insn *pro, rtx_insn *con) 6394 { 6395 rtx pro_x; 6396 rtx con_mem_read; 6397 6398 pro_x = sched_get_reg_operand (pro, true); 6399 if (pro_x == NULL) 6400 return 0; 6401 6402 con_mem_read = sched_get_mem_operand (con, true, false); 6403 gcc_assert (con_mem_read != NULL); 6404 6405 if (reg_mentioned_p (pro_x, con_mem_read)) 6406 return 1; 6407 6408 return 0; 6409 } 6410 6411 /* Helper function for m68k_sched_indexed_address_bypass_p. 6412 if PRO modifies register used as index in CON, 6413 return scale of indexed memory access in CON. Return zero overwise. */ 6414 static int 6415 sched_get_indexed_address_scale (rtx_insn *pro, rtx_insn *con) 6416 { 6417 rtx reg; 6418 rtx mem; 6419 struct m68k_address address; 6420 6421 reg = sched_get_reg_operand (pro, true); 6422 if (reg == NULL) 6423 return 0; 6424 6425 mem = sched_get_mem_operand (con, true, false); 6426 gcc_assert (mem != NULL && MEM_P (mem)); 6427 6428 if (!m68k_decompose_address (GET_MODE (mem), XEXP (mem, 0), reload_completed, 6429 &address)) 6430 gcc_unreachable (); 6431 6432 if (REGNO (reg) == REGNO (address.index)) 6433 { 6434 gcc_assert (address.scale != 0); 6435 return address.scale; 6436 } 6437 6438 return 0; 6439 } 6440 6441 /* Return non-zero if PRO modifies register used 6442 as index with scale 2 or 4 in CON. */ 6443 int 6444 m68k_sched_indexed_address_bypass_p (rtx_insn *pro, rtx_insn *con) 6445 { 6446 gcc_assert (sched_cfv4_bypass_data.pro == NULL 6447 && sched_cfv4_bypass_data.con == NULL 6448 && sched_cfv4_bypass_data.scale == 0); 6449 6450 switch (sched_get_indexed_address_scale (pro, con)) 6451 { 6452 case 1: 6453 /* We can't have a variable latency bypass, so 6454 remember to adjust the insn cost in adjust_cost hook. */ 6455 sched_cfv4_bypass_data.pro = pro; 6456 sched_cfv4_bypass_data.con = con; 6457 sched_cfv4_bypass_data.scale = 1; 6458 return 0; 6459 6460 case 2: 6461 case 4: 6462 return 1; 6463 6464 default: 6465 return 0; 6466 } 6467 } 6468 6469 /* We generate a two-instructions program at M_TRAMP : 6470 movea.l &CHAIN_VALUE,%a0 6471 jmp FNADDR 6472 where %a0 can be modified by changing STATIC_CHAIN_REGNUM. */ 6473 6474 static void 6475 m68k_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 6476 { 6477 rtx fnaddr = XEXP (DECL_RTL (fndecl), 0); 6478 rtx mem; 6479 6480 gcc_assert (ADDRESS_REGNO_P (STATIC_CHAIN_REGNUM)); 6481 6482 mem = adjust_address (m_tramp, HImode, 0); 6483 emit_move_insn (mem, GEN_INT(0x207C + ((STATIC_CHAIN_REGNUM-8) << 9))); 6484 mem = adjust_address (m_tramp, SImode, 2); 6485 emit_move_insn (mem, chain_value); 6486 6487 mem = adjust_address (m_tramp, HImode, 6); 6488 emit_move_insn (mem, GEN_INT(0x4EF9)); 6489 mem = adjust_address (m_tramp, SImode, 8); 6490 emit_move_insn (mem, fnaddr); 6491 6492 FINALIZE_TRAMPOLINE (XEXP (m_tramp, 0)); 6493 } 6494 6495 /* On the 68000, the RTS insn cannot pop anything. 6496 On the 68010, the RTD insn may be used to pop them if the number 6497 of args is fixed, but if the number is variable then the caller 6498 must pop them all. RTD can't be used for library calls now 6499 because the library is compiled with the Unix compiler. 6500 Use of RTD is a selectable option, since it is incompatible with 6501 standard Unix calling sequences. If the option is not selected, 6502 the caller must always pop the args. */ 6503 6504 static int 6505 m68k_return_pops_args (tree fundecl, tree funtype, int size) 6506 { 6507 return ((TARGET_RTD 6508 && (!fundecl 6509 || TREE_CODE (fundecl) != IDENTIFIER_NODE) 6510 && (!stdarg_p (funtype))) 6511 ? size : 0); 6512 } 6513 6514 /* Make sure everything's fine if we *don't* have a given processor. 6515 This assumes that putting a register in fixed_regs will keep the 6516 compiler's mitts completely off it. We don't bother to zero it out 6517 of register classes. */ 6518 6519 static void 6520 m68k_conditional_register_usage (void) 6521 { 6522 int i; 6523 HARD_REG_SET x; 6524 if (!TARGET_HARD_FLOAT) 6525 { 6526 COPY_HARD_REG_SET (x, reg_class_contents[(int)FP_REGS]); 6527 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 6528 if (TEST_HARD_REG_BIT (x, i)) 6529 fixed_regs[i] = call_used_regs[i] = 1; 6530 } 6531 if (flag_pic) 6532 fixed_regs[PIC_REG] = call_used_regs[PIC_REG] = 1; 6533 } 6534 6535 static void 6536 m68k_init_sync_libfuncs (void) 6537 { 6538 init_sync_libfuncs (UNITS_PER_WORD); 6539 } 6540 6541 /* Implements EPILOGUE_USES. All registers are live on exit from an 6542 interrupt routine. */ 6543 bool 6544 m68k_epilogue_uses (int regno ATTRIBUTE_UNUSED) 6545 { 6546 return (reload_completed 6547 && (m68k_get_function_kind (current_function_decl) 6548 == m68k_fk_interrupt_handler)); 6549 } 6550 6551 #include "gt-m68k.h" 6552