1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu. 2 Copyright (C) 1996-2017 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published 8 by the Free Software Foundation; either version 3, or (at your 9 option) any later version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 /* Things to do: 21 - longlong.h? 22 */ 23 24 #undef SIZE_TYPE 25 #undef PTRDIFF_TYPE 26 #undef WCHAR_TYPE 27 #undef WCHAR_TYPE_SIZE 28 #undef CPP_SPEC 29 #undef ASM_SPEC 30 #undef LINK_SPEC 31 #undef STARTFILE_SPEC 32 #undef ENDFILE_SPEC 33 34 #undef ASM_APP_ON 35 #undef ASM_APP_OFF 36 37 38 /* M32R/X overrides. */ 39 40 /* Additional flags for the preprocessor. */ 41 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \ 42 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \ 43 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \ 44 " 45 46 /* Assembler switches. */ 47 #define ASM_CPU_SPEC \ 48 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts" 49 50 /* Use m32rx specific crt0/crtinit/crtfini files. */ 51 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}" 52 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}" 53 54 /* Define this macro as a C expression for the initializer of an array of 55 strings to tell the driver program which options are defaults for this 56 target and thus do not need to be handled specially when using 57 `MULTILIB_OPTIONS'. */ 58 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r" 59 60 /* Number of additional registers the subtarget defines. */ 61 #define SUBTARGET_NUM_REGISTERS 1 62 63 /* 1 for registers that cannot be allocated. */ 64 #define SUBTARGET_FIXED_REGISTERS , 1 65 66 /* 1 for registers that are not available across function calls. */ 67 #define SUBTARGET_CALL_USED_REGISTERS , 1 68 69 /* Order to allocate model specific registers. */ 70 #define SUBTARGET_REG_ALLOC_ORDER , 19 71 72 /* Registers which are accumulators. */ 73 #define SUBTARGET_REG_CLASS_ACCUM 0x80000 74 75 /* All registers added. */ 76 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM 77 78 /* Additional accumulator registers. */ 79 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19) 80 81 /* Define additional register names. */ 82 #define SUBTARGET_REGISTER_NAMES , "a1" 83 /* end M32R/X overrides. */ 84 85 /* Names to predefine in the preprocessor for this target machine. */ 86 /* __M32R__ is defined by the existing compiler so we use that. */ 87 #define TARGET_CPU_CPP_BUILTINS() \ 88 do \ 89 { \ 90 builtin_define ("__M32R__"); \ 91 builtin_define ("__m32r__"); \ 92 builtin_assert ("cpu=m32r"); \ 93 builtin_assert ("machine=m32r"); \ 94 builtin_define (TARGET_BIG_ENDIAN \ 95 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \ 96 } \ 97 while (0) 98 99 /* This macro defines names of additional specifications to put in the specs 100 that can be used in various specifications like CC1_SPEC. Its definition 101 is an initializer with a subgrouping for each command option. 102 103 Each subgrouping contains a string constant, that defines the 104 specification name, and a string constant that used by the GCC driver 105 program. 106 107 Do not define this macro if it does not need to do anything. */ 108 109 #ifndef SUBTARGET_EXTRA_SPECS 110 #define SUBTARGET_EXTRA_SPECS 111 #endif 112 113 #ifndef ASM_CPU_SPEC 114 #define ASM_CPU_SPEC "" 115 #endif 116 117 #ifndef CPP_CPU_SPEC 118 #define CPP_CPU_SPEC "" 119 #endif 120 121 #ifndef CC1_CPU_SPEC 122 #define CC1_CPU_SPEC "" 123 #endif 124 125 #ifndef LINK_CPU_SPEC 126 #define LINK_CPU_SPEC "" 127 #endif 128 129 #ifndef STARTFILE_CPU_SPEC 130 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s" 131 #endif 132 133 #ifndef ENDFILE_CPU_SPEC 134 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s" 135 #endif 136 137 #ifndef RELAX_SPEC 138 #if 0 /* Not supported yet. */ 139 #define RELAX_SPEC "%{mrelax:-relax}" 140 #else 141 #define RELAX_SPEC "" 142 #endif 143 #endif 144 145 #define EXTRA_SPECS \ 146 { "asm_cpu", ASM_CPU_SPEC }, \ 147 { "cpp_cpu", CPP_CPU_SPEC }, \ 148 { "cc1_cpu", CC1_CPU_SPEC }, \ 149 { "link_cpu", LINK_CPU_SPEC }, \ 150 { "startfile_cpu", STARTFILE_CPU_SPEC }, \ 151 { "endfile_cpu", ENDFILE_CPU_SPEC }, \ 152 { "relax", RELAX_SPEC }, \ 153 SUBTARGET_EXTRA_SPECS 154 155 #define CPP_SPEC "%(cpp_cpu)" 156 157 #undef CC1_SPEC 158 #define CC1_SPEC "%{G*} %(cc1_cpu)" 159 160 /* Options to pass on to the assembler. */ 161 #undef ASM_SPEC 162 #define ASM_SPEC "%(asm_cpu) %(relax) %{" FPIE_OR_FPIC_SPEC ":-K PIC}" 163 164 #define LINK_SPEC "%{v} %(link_cpu) %(relax)" 165 166 #undef STARTFILE_SPEC 167 #define STARTFILE_SPEC "%(startfile_cpu)" 168 169 #undef ENDFILE_SPEC 170 #define ENDFILE_SPEC "%(endfile_cpu)" 171 172 #undef LIB_SPEC 173 174 /* Run-time compilation parameters selecting different hardware subsets. */ 175 176 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2) 177 178 #ifndef TARGET_LITTLE_ENDIAN 179 #define TARGET_LITTLE_ENDIAN 0 180 #endif 181 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) 182 183 /* This defaults us to m32r. */ 184 #ifndef TARGET_CPU_DEFAULT 185 #define TARGET_CPU_DEFAULT 0 186 #endif 187 188 #ifndef M32R_OPTS_H 189 #include "config/m32r/m32r-opts.h" 190 #endif 191 192 /* Define this macro as a C expression for the initializer of an array of 193 strings to tell the driver program which options are defaults for this 194 target and thus do not need to be handled specially when using 195 `MULTILIB_OPTIONS'. */ 196 #ifndef SUBTARGET_MULTILIB_DEFAULTS 197 #define SUBTARGET_MULTILIB_DEFAULTS 198 #endif 199 200 #ifndef MULTILIB_DEFAULTS 201 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS } 202 #endif 203 204 #ifndef SUBTARGET_OVERRIDE_OPTIONS 205 #define SUBTARGET_OVERRIDE_OPTIONS 206 #endif 207 208 /* Target machine storage layout. */ 209 210 /* Define this if most significant bit is lowest numbered 211 in instructions that operate on numbered bit-fields. */ 212 #define BITS_BIG_ENDIAN 1 213 214 /* Define this if most significant byte of a word is the lowest numbered. */ 215 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 216 217 /* Define this if most significant word of a multiword number is the lowest 218 numbered. */ 219 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 220 221 /* Width of a word, in units (bytes). */ 222 #define UNITS_PER_WORD 4 223 224 /* Define this macro if it is advisable to hold scalars in registers 225 in a wider mode than that declared by the program. In such cases, 226 the value is constrained to be within the bounds of the declared 227 type, but kept valid in the wider mode. The signedness of the 228 extension may differ from that of the type. */ 229 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 230 if (GET_MODE_CLASS (MODE) == MODE_INT \ 231 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 232 { \ 233 (MODE) = SImode; \ 234 } 235 236 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 237 #define PARM_BOUNDARY 32 238 239 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 240 #define STACK_BOUNDARY 32 241 242 /* ALIGN FRAMES on word boundaries */ 243 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3) 244 245 /* Allocation boundary (in *bits*) for the code of a function. */ 246 #define FUNCTION_BOUNDARY 32 247 248 /* Alignment of field after `int : 0' in a structure. */ 249 #define EMPTY_FIELD_BOUNDARY 32 250 251 /* Every structure's size must be a multiple of this. */ 252 #define STRUCTURE_SIZE_BOUNDARY 8 253 254 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 255 #define PCC_BITFIELD_TYPE_MATTERS 1 256 257 /* No data type wants to be aligned rounder than this. */ 258 #define BIGGEST_ALIGNMENT 32 259 260 /* The best alignment to use in cases where we have a choice. */ 261 #define FASTEST_ALIGNMENT 32 262 263 /* Make strings word-aligned so strcpy from constants will be faster. */ 264 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 265 ((TREE_CODE (EXP) == STRING_CST \ 266 && (ALIGN) < FASTEST_ALIGNMENT) \ 267 ? FASTEST_ALIGNMENT : (ALIGN)) 268 269 /* Make arrays of chars word-aligned for the same reasons. */ 270 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 271 (TREE_CODE (TYPE) == ARRAY_TYPE \ 272 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 273 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 274 275 /* Set this nonzero if move instructions will actually fail to work 276 when given unaligned data. */ 277 #define STRICT_ALIGNMENT 1 278 279 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */ 280 #define LABEL_ALIGN(insn) 2 281 282 /* Layout of source language data types. */ 283 284 #define SHORT_TYPE_SIZE 16 285 #define INT_TYPE_SIZE 32 286 #define LONG_TYPE_SIZE 32 287 #define LONG_LONG_TYPE_SIZE 64 288 #define FLOAT_TYPE_SIZE 32 289 #define DOUBLE_TYPE_SIZE 64 290 #define LONG_DOUBLE_TYPE_SIZE 64 291 292 /* Define this as 1 if `char' should by default be signed; else as 0. */ 293 #define DEFAULT_SIGNED_CHAR 1 294 295 #define SIZE_TYPE "long unsigned int" 296 #define PTRDIFF_TYPE "long int" 297 #define WCHAR_TYPE "short unsigned int" 298 #define WCHAR_TYPE_SIZE 16 299 300 /* Standard register usage. */ 301 302 /* Number of actual hardware registers. 303 The hardware registers are assigned numbers for the compiler 304 from 0 to just below FIRST_PSEUDO_REGISTER. 305 All registers that the compiler knows about must be given numbers, 306 even those that are not normally considered general registers. */ 307 308 #define M32R_NUM_REGISTERS 19 309 310 #ifndef SUBTARGET_NUM_REGISTERS 311 #define SUBTARGET_NUM_REGISTERS 0 312 #endif 313 314 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS) 315 316 /* 1 for registers that have pervasive standard uses 317 and are not available for the register allocator. 318 319 0-3 - arguments/results 320 4-5 - call used [4 is used as a tmp during prologue/epilogue generation] 321 6 - call used, gptmp 322 7 - call used, static chain pointer 323 8-11 - call saved 324 12 - call saved [reserved for global pointer] 325 13 - frame pointer 326 14 - subroutine link register 327 15 - stack pointer 328 16 - arg pointer 329 17 - carry flag 330 18 - accumulator 331 19 - accumulator 1 in the m32r/x 332 By default, the extension registers are not available. */ 333 334 #ifndef SUBTARGET_FIXED_REGISTERS 335 #define SUBTARGET_FIXED_REGISTERS 336 #endif 337 338 #define FIXED_REGISTERS \ 339 { \ 340 0, 0, 0, 0, 0, 0, 0, 0, \ 341 0, 0, 0, 0, 0, 0, 0, 1, \ 342 1, 1, 1 \ 343 SUBTARGET_FIXED_REGISTERS \ 344 } 345 346 /* 1 for registers not available across function calls. 347 These must include the FIXED_REGISTERS and also any 348 registers that can be used without being saved. 349 The latter must include the registers where values are returned 350 and the register where structure-value addresses are passed. 351 Aside from that, you can include as many other registers as you like. */ 352 353 #ifndef SUBTARGET_CALL_USED_REGISTERS 354 #define SUBTARGET_CALL_USED_REGISTERS 355 #endif 356 357 #define CALL_USED_REGISTERS \ 358 { \ 359 1, 1, 1, 1, 1, 1, 1, 1, \ 360 0, 0, 0, 0, 0, 0, 1, 1, \ 361 1, 1, 1 \ 362 SUBTARGET_CALL_USED_REGISTERS \ 363 } 364 365 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS 366 367 /* If defined, an initializer for a vector of integers, containing the 368 numbers of hard registers in the order in which GCC should 369 prefer to use them (from most preferred to least). */ 370 371 #ifndef SUBTARGET_REG_ALLOC_ORDER 372 #define SUBTARGET_REG_ALLOC_ORDER 373 #endif 374 375 #if 1 /* Better for int code. */ 376 #define REG_ALLOC_ORDER \ 377 { \ 378 4, 5, 6, 7, 2, 3, 8, 9, 10, \ 379 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \ 380 SUBTARGET_REG_ALLOC_ORDER \ 381 } 382 383 #else /* Better for fp code at expense of int code. */ 384 #define REG_ALLOC_ORDER \ 385 { \ 386 0, 1, 2, 3, 4, 5, 6, 7, 8, \ 387 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \ 388 SUBTARGET_REG_ALLOC_ORDER \ 389 } 390 #endif 391 392 /* Return number of consecutive hard regs needed starting at reg REGNO 393 to hold something of mode MODE. 394 This is ordinarily the length in words of a value of mode MODE 395 but can be less for certain modes in special long registers. */ 396 #define HARD_REGNO_NREGS(REGNO, MODE) \ 397 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 398 399 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 400 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; 401 extern unsigned int m32r_mode_class[]; 402 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 403 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0) 404 405 /* A C expression that is nonzero if it is desirable to choose 406 register allocation so as to avoid move instructions between a 407 value of mode MODE1 and a value of mode MODE2. 408 409 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 410 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 411 MODE2)' must be zero. */ 412 413 /* Tie QI/HI/SI modes together. */ 414 #define MODES_TIEABLE_P(MODE1, MODE2) \ 415 ( GET_MODE_CLASS (MODE1) == MODE_INT \ 416 && GET_MODE_CLASS (MODE2) == MODE_INT \ 417 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 418 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD) 419 420 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 421 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG) 422 423 /* Register classes and constants. */ 424 425 /* Define the classes of registers for register constraints in the 426 machine description. Also define ranges of constants. 427 428 One of the classes must always be named ALL_REGS and include all hard regs. 429 If there is more than one class, another class must be named NO_REGS 430 and contain no registers. 431 432 The name GENERAL_REGS must be the name of a class (or an alias for 433 another name such as ALL_REGS). This is the class of registers 434 that is allowed by "g" or "r" in a register constraint. 435 Also, registers outside this class are allocated only when 436 instructions express preferences for them. 437 438 The classes must be numbered in nondecreasing order; that is, 439 a larger-numbered class must never be contained completely 440 in a smaller-numbered class. 441 442 For any two classes, it is very desirable that there be another 443 class that represents their union. 444 445 It is important that any condition codes have class NO_REGS. 446 See `register_operand'. */ 447 448 enum reg_class 449 { 450 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES 451 }; 452 453 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 454 455 /* Give names of register classes as strings for dump file. */ 456 #define REG_CLASS_NAMES \ 457 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" } 458 459 /* Define which registers fit in which classes. 460 This is an initializer for a vector of HARD_REG_SET 461 of length N_REG_CLASSES. */ 462 463 #ifndef SUBTARGET_REG_CLASS_CARRY 464 #define SUBTARGET_REG_CLASS_CARRY 0 465 #endif 466 467 #ifndef SUBTARGET_REG_CLASS_ACCUM 468 #define SUBTARGET_REG_CLASS_ACCUM 0 469 #endif 470 471 #ifndef SUBTARGET_REG_CLASS_GENERAL 472 #define SUBTARGET_REG_CLASS_GENERAL 0 473 #endif 474 475 #ifndef SUBTARGET_REG_CLASS_ALL 476 #define SUBTARGET_REG_CLASS_ALL 0 477 #endif 478 479 #define REG_CLASS_CONTENTS \ 480 { \ 481 { 0x00000 }, \ 482 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \ 483 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \ 484 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \ 485 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \ 486 } 487 488 /* The same information, inverted: 489 Return the class number of the smallest class containing 490 reg number REGNO. This could be a conditional expression 491 or could index an array. */ 492 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; 493 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO]) 494 495 /* The class value for index registers, and the one for base regs. */ 496 #define INDEX_REG_CLASS GENERAL_REGS 497 #define BASE_REG_CLASS GENERAL_REGS 498 499 /* These assume that REGNO is a hard or pseudo reg number. 500 They give nonzero only if REGNO is a hard reg of the suitable class 501 or a pseudo reg currently allocated to a suitable hard reg. 502 Since they use reg_renumber, they are safe only once reg_renumber 503 has been allocated, which happens in reginfo.c during register 504 allocation. */ 505 #define REGNO_OK_FOR_BASE_P(REGNO) \ 506 ((REGNO) < FIRST_PSEUDO_REGISTER \ 507 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \ 508 : GPR_P (reg_renumber[REGNO])) 509 510 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) 511 512 /* Return true if a value is inside a range. */ 513 #define IN_RANGE_P(VALUE, LOW, HIGH) \ 514 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \ 515 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW)))) 516 517 /* Some range macros. */ 518 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff) 519 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000) 520 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff) 521 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff) 522 523 /* Stack layout and stack pointer usage. */ 524 525 /* Define this macro if pushing a word onto the stack moves the stack 526 pointer to a smaller address. */ 527 #define STACK_GROWS_DOWNWARD 1 528 529 /* Offset from frame pointer to start allocating local variables at. 530 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 531 first local allocated. Otherwise, it is the offset to the BEGINNING 532 of the first local allocated. */ 533 /* The frame pointer points at the same place as the stack pointer, except if 534 alloca has been called. */ 535 #define STARTING_FRAME_OFFSET \ 536 M32R_STACK_ALIGN (crtl->outgoing_args_size) 537 538 /* Offset from the stack pointer register to the first location at which 539 outgoing arguments are placed. */ 540 #define STACK_POINTER_OFFSET 0 541 542 /* Offset of first parameter from the argument pointer register value. */ 543 #define FIRST_PARM_OFFSET(FNDECL) 0 544 545 /* Register to use for pushing function arguments. */ 546 #define STACK_POINTER_REGNUM 15 547 548 /* Base register for access to local variables of the function. */ 549 #define FRAME_POINTER_REGNUM 13 550 551 /* Base register for access to arguments of the function. */ 552 #define ARG_POINTER_REGNUM 16 553 554 /* Register in which static-chain is passed to a function. 555 This must not be a register used by the prologue. */ 556 #define STATIC_CHAIN_REGNUM 7 557 558 /* These aren't official macros. */ 559 #define PROLOGUE_TMP_REGNUM 4 560 #define RETURN_ADDR_REGNUM 14 561 /* #define GP_REGNUM 12 */ 562 #define CARRY_REGNUM 17 563 #define ACCUM_REGNUM 18 564 #define M32R_MAX_INT_REGS 16 565 566 #ifndef SUBTARGET_GPR_P 567 #define SUBTARGET_GPR_P(REGNO) 0 568 #endif 569 570 #ifndef SUBTARGET_ACCUM_P 571 #define SUBTARGET_ACCUM_P(REGNO) 0 572 #endif 573 574 #ifndef SUBTARGET_CARRY_P 575 #define SUBTARGET_CARRY_P(REGNO) 0 576 #endif 577 578 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO)) 579 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO)) 580 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO)) 581 582 /* Eliminating the frame and arg pointers. */ 583 584 /* If defined, this macro specifies a table of register pairs used to 585 eliminate unneeded registers that point into the stack frame. If 586 it is not defined, the only elimination attempted by the compiler 587 is to replace references to the frame pointer with references to 588 the stack pointer. 589 590 Note that the elimination of the argument pointer with the stack 591 pointer is specified first since that is the preferred elimination. */ 592 593 #define ELIMINABLE_REGS \ 594 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 595 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 596 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }} 597 598 /* This macro returns the initial difference between the specified pair 599 of registers. */ 600 601 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 602 do \ 603 { \ 604 int size = m32r_compute_frame_size (get_frame_size ()); \ 605 \ 606 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ 607 (OFFSET) = 0; \ 608 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ 609 (OFFSET) = size - crtl->args.pretend_args_size; \ 610 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ 611 (OFFSET) = size - crtl->args.pretend_args_size; \ 612 else \ 613 gcc_unreachable (); \ 614 } \ 615 while (0) 616 617 /* Function argument passing. */ 618 619 /* If defined, the maximum amount of space required for outgoing 620 arguments will be computed and placed into the variable 621 `crtl->outgoing_args_size'. No space will be pushed 622 onto the stack for each call; instead, the function prologue should 623 increase the stack frame size by this amount. */ 624 #define ACCUMULATE_OUTGOING_ARGS 1 625 626 /* Define a data type for recording info about an argument list 627 during the scan of that argument list. This data type should 628 hold all necessary information about the function itself 629 and about the args processed so far, enough to enable macros 630 such as FUNCTION_ARG to determine where the next arg should go. */ 631 #define CUMULATIVE_ARGS int 632 633 /* Initialize a variable CUM of type CUMULATIVE_ARGS 634 for a call to a function whose data type is FNTYPE. 635 For a library call, FNTYPE is 0. */ 636 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 637 ((CUM) = 0) 638 639 /* The number of registers used for parameter passing. Local to this file. */ 640 #define M32R_MAX_PARM_REGS 4 641 642 /* 1 if N is a possible register number for function argument passing. */ 643 #define FUNCTION_ARG_REGNO_P(N) \ 644 ((unsigned) (N) < M32R_MAX_PARM_REGS) 645 646 647 /* Function results. */ 648 649 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ 650 #define DEFAULT_PCC_STRUCT_RETURN 0 651 652 /* Function entry and exit. */ 653 654 /* Initialize data used by insn expanders. This is called from 655 init_emit, once for each function, before code is generated. */ 656 #define INIT_EXPANDERS m32r_init_expanders () 657 658 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 659 the stack pointer does not matter. The value is tested only in 660 functions that have frame pointers. 661 No definition is equivalent to always zero. */ 662 #define EXIT_IGNORE_STACK 1 663 664 /* Output assembler code to FILE to increment profiler label # LABELNO 665 for profiling a function entry. */ 666 #undef FUNCTION_PROFILER 667 #define FUNCTION_PROFILER(FILE, LABELNO) \ 668 do \ 669 { \ 670 if (flag_pic) \ 671 { \ 672 fprintf (FILE, "\tld24 r14,#mcount\n"); \ 673 fprintf (FILE, "\tadd r14,r12\n"); \ 674 fprintf (FILE, "\tld r14,@r14\n"); \ 675 fprintf (FILE, "\tjl r14\n"); \ 676 } \ 677 else \ 678 { \ 679 if (TARGET_ADDR24) \ 680 fprintf (FILE, "\tbl mcount\n"); \ 681 else \ 682 { \ 683 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \ 684 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \ 685 fprintf (FILE, "\tjl r14\n"); \ 686 } \ 687 } \ 688 fprintf (FILE, "\taddi sp,#4\n"); \ 689 } \ 690 while (0) 691 692 /* Trampolines. */ 693 694 /* On the M32R, the trampoline is: 695 696 mv r7, lr -> bl L1 ; 178e 7e01 697 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12) 698 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6 699 ld r6, @r6 -> jmp r6 ; 26c6 1fc6 700 L2: .word STATIC 701 .word FUNCTION */ 702 703 #ifndef CACHE_FLUSH_FUNC 704 #define CACHE_FLUSH_FUNC "_flush_cache" 705 #endif 706 #ifndef CACHE_FLUSH_TRAP 707 #define CACHE_FLUSH_TRAP 12 708 #endif 709 710 /* Length in bytes of the trampoline for entering a nested function. */ 711 #define TRAMPOLINE_SIZE 24 712 713 714 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT) 715 716 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) 717 718 /* Addressing modes, and classification of registers for them. */ 719 720 /* Maximum number of registers that can appear in a valid memory address. */ 721 #define MAX_REGS_PER_ADDRESS 1 722 723 /* We have post-inc load and pre-dec,pre-inc store, 724 but only for 4 byte vals. */ 725 #define HAVE_PRE_DECREMENT 1 726 #define HAVE_PRE_INCREMENT 1 727 #define HAVE_POST_INCREMENT 1 728 729 /* Recognize any constant value that is a valid address. */ 730 #define CONSTANT_ADDRESS_P(X) \ 731 ( GET_CODE (X) == LABEL_REF \ 732 || GET_CODE (X) == SYMBOL_REF \ 733 || CONST_INT_P (X) \ 734 || (GET_CODE (X) == CONST \ 735 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X)))) 736 737 /* Condition code usage. */ 738 739 /* Return nonzero if SELECT_CC_MODE will never return MODE for a 740 floating point inequality comparison. */ 741 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ 742 743 /* Costs. */ 744 745 /* The cost of a branch insn. */ 746 /* A value of 2 here causes GCC to avoid using branches in comparisons like 747 while (a < N && a). Branches aren't that expensive on the M32R so 748 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */ 749 #define BRANCH_COST(speed_p, predictable_p) ((TARGET_BRANCH_COST) ? 2 : 1) 750 751 /* Nonzero if access to memory by bytes is slow and undesirable. 752 For RISC chips, it means that access to memory by bytes is no 753 better than access by words when possible, so grab a whole word 754 and maybe make use of that. */ 755 #define SLOW_BYTE_ACCESS 1 756 757 /* Define this macro if it is as good or better to call a constant 758 function address than to call an address kept in a register. */ 759 #define NO_FUNCTION_CSE 1 760 761 /* Section selection. */ 762 763 #define TEXT_SECTION_ASM_OP "\t.section .text" 764 #define DATA_SECTION_ASM_OP "\t.section .data" 765 #define BSS_SECTION_ASM_OP "\t.section .bss" 766 767 /* Define this macro if jump tables (for tablejump insns) should be 768 output in the text section, along with the assembler instructions. 769 Otherwise, the readonly data section is used. 770 This macro is irrelevant if there is no separate readonly data section. */ 771 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 772 773 /* Position Independent Code. */ 774 775 /* The register number of the register used to address a table of static 776 data addresses in memory. In some cases this register is defined by a 777 processor's ``application binary interface'' (ABI). When this macro 778 is defined, RTL is generated for this register once, as with the stack 779 pointer and frame pointer registers. If this macro is not defined, it 780 is up to the machine-dependent files to allocate such a register (if 781 necessary). */ 782 #define PIC_OFFSET_TABLE_REGNUM 12 783 784 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is 785 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM 786 is not defined. */ 787 /* This register is call-saved on the M32R. */ 788 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ 789 790 /* A C expression that is nonzero if X is a legitimate immediate 791 operand on the target machine when generating position independent code. 792 You can assume that X satisfies CONSTANT_P, so you need not 793 check this. You can also assume `flag_pic' is true, so you need not 794 check it either. You need not define this macro if all constants 795 (including SYMBOL_REF) can be immediate operands when generating 796 position independent code. */ 797 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X) 798 799 /* Control the assembler format that we output. */ 800 801 /* A C string constant describing how to begin a comment in the target 802 assembler language. The compiler assumes that the comment will 803 end at the end of the line. */ 804 #define ASM_COMMENT_START ";" 805 806 /* Output to assembler file text saying following lines 807 may contain character constants, extra white space, comments, etc. */ 808 #define ASM_APP_ON "" 809 810 /* Output to assembler file text saying following lines 811 no longer contain unusual constructs. */ 812 #define ASM_APP_OFF "" 813 814 /* Globalizing directive for a label. */ 815 #define GLOBAL_ASM_OP "\t.global\t" 816 817 /* We do not use DBX_LINES_FUNCTION_RELATIVE or 818 dbxout_stab_value_internal_label_diff here because 819 we need to use .debugsym for the line label. */ 820 821 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \ 822 do \ 823 { \ 824 const char * begin_label = \ 825 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \ 826 char label[64]; \ 827 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \ 828 \ 829 dbxout_begin_stabn_sline (line); \ 830 assemble_name (file, label); \ 831 putc ('-', file); \ 832 assemble_name (file, begin_label); \ 833 fputs ("\n\t.debugsym ", file); \ 834 assemble_name (file, label); \ 835 putc ('\n', file); \ 836 counter += 1; \ 837 } \ 838 while (0) 839 840 /* How to refer to registers in assembler output. 841 This sequence is indexed by compiler's hard-register-number (see above). */ 842 #ifndef SUBTARGET_REGISTER_NAMES 843 #define SUBTARGET_REGISTER_NAMES 844 #endif 845 846 #define REGISTER_NAMES \ 847 { \ 848 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 849 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \ 850 "ap", "cbit", "a0" \ 851 SUBTARGET_REGISTER_NAMES \ 852 } 853 854 /* If defined, a C initializer for an array of structures containing 855 a name and a register number. This macro defines additional names 856 for hard registers, thus allowing the `asm' option in declarations 857 to refer to registers using alternate names. */ 858 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES 859 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES 860 #endif 861 862 #define ADDITIONAL_REGISTER_NAMES \ 863 { \ 864 /*{ "gp", GP_REGNUM },*/ \ 865 { "r13", FRAME_POINTER_REGNUM }, \ 866 { "r14", RETURN_ADDR_REGNUM }, \ 867 { "r15", STACK_POINTER_REGNUM }, \ 868 SUBTARGET_ADDITIONAL_REGISTER_NAMES \ 869 } 870 871 /* If defined, C string expressions to be used for the `%R', `%L', 872 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These 873 are useful when a single `md' file must support multiple assembler 874 formats. In that case, the various `tm.h' files can define these 875 macros differently. */ 876 #define REGISTER_PREFIX "" 877 #define LOCAL_LABEL_PREFIX ".L" 878 #define USER_LABEL_PREFIX "" 879 #define IMMEDIATE_PREFIX "#" 880 881 /* This is how to output an element of a case-vector that is absolute. */ 882 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 883 do \ 884 { \ 885 char label[30]; \ 886 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 887 fprintf (FILE, "\t.word\t"); \ 888 assemble_name (FILE, label); \ 889 fprintf (FILE, "\n"); \ 890 } \ 891 while (0) 892 893 /* This is how to output an element of a case-vector that is relative. */ 894 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\ 895 do \ 896 { \ 897 char label[30]; \ 898 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 899 fprintf (FILE, "\t.word\t"); \ 900 assemble_name (FILE, label); \ 901 fprintf (FILE, "-"); \ 902 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ 903 assemble_name (FILE, label); \ 904 fprintf (FILE, "\n"); \ 905 } \ 906 while (0) 907 908 /* The desired alignment for the location counter at the beginning 909 of a loop. */ 910 /* On the M32R, align loops to 32 byte boundaries (cache line size) 911 if -malign-loops. */ 912 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0) 913 914 /* Define this to be the maximum number of insns to move around when moving 915 a loop test from the top of a loop to the bottom 916 and seeing whether to duplicate it. The default is thirty. 917 918 Loop unrolling currently doesn't like this optimization, so 919 disable doing if we are unrolling loops and saving space. */ 920 #define LOOP_TEST_THRESHOLD (optimize_size \ 921 && !flag_unroll_loops \ 922 && !flag_unroll_all_loops ? 2 : 30) 923 924 /* This is how to output an assembler line 925 that says to advance the location counter 926 to a multiple of 2**LOG bytes. */ 927 /* .balign is used to avoid confusion. */ 928 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 929 do \ 930 { \ 931 if ((LOG) != 0) \ 932 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \ 933 } \ 934 while (0) 935 936 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a 937 separate, explicit argument. If you define this macro, it is used in 938 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in 939 handling the required alignment of the variable. The alignment is 940 specified as the number of bits. */ 941 942 #define SCOMMON_ASM_OP "\t.scomm\t" 943 944 #undef ASM_OUTPUT_ALIGNED_COMMON 945 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 946 do \ 947 { \ 948 if (! TARGET_SDATA_NONE \ 949 && (SIZE) > 0 \ 950 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ 951 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \ 952 else \ 953 fprintf ((FILE), "%s", COMMON_ASM_OP); \ 954 assemble_name ((FILE), (NAME)); \ 955 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ 956 } \ 957 while (0) 958 959 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 960 do \ 961 { \ 962 if (! TARGET_SDATA_NONE \ 963 && (SIZE) > 0 \ 964 && (SIZE) <= (unsigned HOST_WIDE_INT) g_switch_value) \ 965 switch_to_section (get_named_section (NULL, ".sbss", 0)); \ 966 else \ 967 switch_to_section (bss_section); \ 968 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \ 969 last_assemble_variable_decl = DECL; \ 970 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \ 971 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \ 972 } \ 973 while (0) 974 975 /* Debugging information. */ 976 977 /* Generate DBX and DWARF debugging information. */ 978 #define DBX_DEBUGGING_INFO 1 979 #define DWARF2_DEBUGGING_INFO 1 980 981 /* Use DWARF2 debugging info by default. */ 982 #undef PREFERRED_DEBUGGING_TYPE 983 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 984 985 /* Turn off splitting of long stabs. */ 986 #define DBX_CONTIN_LENGTH 0 987 988 /* Miscellaneous. */ 989 990 /* Specify the machine mode that this machine uses 991 for the index in the tablejump instruction. */ 992 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode) 993 994 /* Define if operations between registers always perform the operation 995 on the full register even if a narrower mode is specified. */ 996 #define WORD_REGISTER_OPERATIONS 1 997 998 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 999 will either zero-extend or sign-extend. The value of this macro should 1000 be the code that says which one of the two operations is implicitly 1001 done, UNKNOWN if none. */ 1002 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1003 1004 /* Max number of bytes we can move from memory 1005 to memory in one reasonably fast instruction. */ 1006 #define MOVE_MAX 4 1007 1008 /* Define this to be nonzero if shift instructions ignore all but the low-order 1009 few bits. */ 1010 #define SHIFT_COUNT_TRUNCATED 1 1011 1012 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1013 is done just by pretending it is already truncated. */ 1014 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1015 1016 /* Specify the machine mode that pointers have. 1017 After generation of rtl, the compiler makes no further distinction 1018 between pointers and any other objects of this machine mode. */ 1019 /* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has 1020 its own problems (you have to add extendpsisi2 and truncsipsi2). 1021 Try to avoid it. */ 1022 #define Pmode SImode 1023 1024 /* A function address in a call instruction. */ 1025 #define FUNCTION_MODE SImode 1026 1027 /* M32R function types. */ 1028 enum m32r_function_type 1029 { 1030 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT 1031 }; 1032 1033 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT) 1034 1035 /* The maximum number of bytes to copy using pairs of load/store instructions. 1036 If a block is larger than this then a loop will be generated to copy 1037 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice. 1038 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte 1039 string copy in it. */ 1040 #define MAX_MOVE_BYTES 32 1041