1 /* Definitions of target machine for GNU compiler, Renesas M32R cpu. 2 Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 3 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 /* Things to do: 22 - longlong.h? 23 */ 24 25 #undef SWITCH_TAKES_ARG 26 #undef WORD_SWITCH_TAKES_ARG 27 #undef HANDLE_SYSV_PRAGMA 28 #undef SIZE_TYPE 29 #undef PTRDIFF_TYPE 30 #undef WCHAR_TYPE 31 #undef WCHAR_TYPE_SIZE 32 #undef TARGET_VERSION 33 #undef CPP_SPEC 34 #undef ASM_SPEC 35 #undef LINK_SPEC 36 #undef STARTFILE_SPEC 37 #undef ENDFILE_SPEC 38 39 #undef ASM_APP_ON 40 #undef ASM_APP_OFF 41 42 43 /* M32R/X overrides. */ 44 /* Print subsidiary information on the compiler version in use. */ 45 #define TARGET_VERSION fprintf (stderr, " (m32r/x/2)"); 46 47 /* Additional flags for the preprocessor. */ 48 #define CPP_CPU_SPEC "%{m32rx:-D__M32RX__ -D__m32rx__ -U__M32R2__ -U__m32r2__} \ 49 %{m32r2:-D__M32R2__ -D__m32r2__ -U__M32RX__ -U__m32rx__} \ 50 %{m32r:-U__M32RX__ -U__m32rx__ -U__M32R2__ -U__m32r2__} \ 51 " 52 53 /* Assembler switches. */ 54 #define ASM_CPU_SPEC \ 55 "%{m32r} %{m32rx} %{m32r2} %{!O0: %{O*: -O}} --no-warn-explicit-parallel-conflicts" 56 57 /* Use m32rx specific crt0/crtinit/crtfini files. */ 58 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} %{m32rx:m32rx/crtinit.o%s} %{!m32rx:crtinit.o%s}" 59 #define ENDFILE_CPU_SPEC "-lgloss %{m32rx:m32rx/crtfini.o%s} %{!m32rx:crtfini.o%s}" 60 61 /* Define this macro as a C expression for the initializer of an array of 62 strings to tell the driver program which options are defaults for this 63 target and thus do not need to be handled specially when using 64 `MULTILIB_OPTIONS'. */ 65 #define SUBTARGET_MULTILIB_DEFAULTS , "m32r" 66 67 /* Number of additional registers the subtarget defines. */ 68 #define SUBTARGET_NUM_REGISTERS 1 69 70 /* 1 for registers that cannot be allocated. */ 71 #define SUBTARGET_FIXED_REGISTERS , 1 72 73 /* 1 for registers that are not available across function calls. */ 74 #define SUBTARGET_CALL_USED_REGISTERS , 1 75 76 /* Order to allocate model specific registers. */ 77 #define SUBTARGET_REG_ALLOC_ORDER , 19 78 79 /* Registers which are accumulators. */ 80 #define SUBTARGET_REG_CLASS_ACCUM 0x80000 81 82 /* All registers added. */ 83 #define SUBTARGET_REG_CLASS_ALL SUBTARGET_REG_CLASS_ACCUM 84 85 /* Additional accumulator registers. */ 86 #define SUBTARGET_ACCUM_P(REGNO) ((REGNO) == 19) 87 88 /* Define additional register names. */ 89 #define SUBTARGET_REGISTER_NAMES , "a1" 90 /* end M32R/X overrides. */ 91 92 /* Print subsidiary information on the compiler version in use. */ 93 #ifndef TARGET_VERSION 94 #define TARGET_VERSION fprintf (stderr, " (m32r)") 95 #endif 96 97 /* Switch Recognition by gcc.c. Add -G xx support. */ 98 99 #undef SWITCH_TAKES_ARG 100 #define SWITCH_TAKES_ARG(CHAR) \ 101 (DEFAULT_SWITCH_TAKES_ARG (CHAR) || (CHAR) == 'G') 102 103 /* Names to predefine in the preprocessor for this target machine. */ 104 /* __M32R__ is defined by the existing compiler so we use that. */ 105 #define TARGET_CPU_CPP_BUILTINS() \ 106 do \ 107 { \ 108 builtin_define ("__M32R__"); \ 109 builtin_define ("__m32r__"); \ 110 builtin_assert ("cpu=m32r"); \ 111 builtin_assert ("machine=m32r"); \ 112 builtin_define (TARGET_BIG_ENDIAN \ 113 ? "__BIG_ENDIAN__" : "__LITTLE_ENDIAN__"); \ 114 } \ 115 while (0) 116 117 /* This macro defines names of additional specifications to put in the specs 118 that can be used in various specifications like CC1_SPEC. Its definition 119 is an initializer with a subgrouping for each command option. 120 121 Each subgrouping contains a string constant, that defines the 122 specification name, and a string constant that used by the GCC driver 123 program. 124 125 Do not define this macro if it does not need to do anything. */ 126 127 #ifndef SUBTARGET_EXTRA_SPECS 128 #define SUBTARGET_EXTRA_SPECS 129 #endif 130 131 #ifndef ASM_CPU_SPEC 132 #define ASM_CPU_SPEC "" 133 #endif 134 135 #ifndef CPP_CPU_SPEC 136 #define CPP_CPU_SPEC "" 137 #endif 138 139 #ifndef CC1_CPU_SPEC 140 #define CC1_CPU_SPEC "" 141 #endif 142 143 #ifndef LINK_CPU_SPEC 144 #define LINK_CPU_SPEC "" 145 #endif 146 147 #ifndef STARTFILE_CPU_SPEC 148 #define STARTFILE_CPU_SPEC "%{!shared:crt0.o%s} crtinit.o%s" 149 #endif 150 151 #ifndef ENDFILE_CPU_SPEC 152 #define ENDFILE_CPU_SPEC "-lgloss crtfini.o%s" 153 #endif 154 155 #ifndef RELAX_SPEC 156 #if 0 /* Not supported yet. */ 157 #define RELAX_SPEC "%{mrelax:-relax}" 158 #else 159 #define RELAX_SPEC "" 160 #endif 161 #endif 162 163 #define EXTRA_SPECS \ 164 { "asm_cpu", ASM_CPU_SPEC }, \ 165 { "cpp_cpu", CPP_CPU_SPEC }, \ 166 { "cc1_cpu", CC1_CPU_SPEC }, \ 167 { "link_cpu", LINK_CPU_SPEC }, \ 168 { "startfile_cpu", STARTFILE_CPU_SPEC }, \ 169 { "endfile_cpu", ENDFILE_CPU_SPEC }, \ 170 { "relax", RELAX_SPEC }, \ 171 SUBTARGET_EXTRA_SPECS 172 173 #define CPP_SPEC "%(cpp_cpu)" 174 175 #undef CC1_SPEC 176 #define CC1_SPEC "%{G*} %(cc1_cpu)" 177 178 /* Options to pass on to the assembler. */ 179 #undef ASM_SPEC 180 #define ASM_SPEC "%{v} %(asm_cpu) %(relax) %{fpic|fpie:-K PIC} %{fPIC|fPIE:-K PIC}" 181 182 #define LINK_SPEC "%{v} %(link_cpu) %(relax)" 183 184 #undef STARTFILE_SPEC 185 #define STARTFILE_SPEC "%(startfile_cpu)" 186 187 #undef ENDFILE_SPEC 188 #define ENDFILE_SPEC "%(endfile_cpu)" 189 190 #undef LIB_SPEC 191 192 /* Run-time compilation parameters selecting different hardware subsets. */ 193 194 #define TARGET_M32R (! TARGET_M32RX && ! TARGET_M32R2) 195 196 #ifndef TARGET_LITTLE_ENDIAN 197 #define TARGET_LITTLE_ENDIAN 0 198 #endif 199 #define TARGET_BIG_ENDIAN (! TARGET_LITTLE_ENDIAN) 200 201 /* This defaults us to m32r. */ 202 #ifndef TARGET_CPU_DEFAULT 203 #define TARGET_CPU_DEFAULT 0 204 #endif 205 206 /* Code Models 207 208 Code models are used to select between two choices of two separate 209 possibilities (address space size, call insn to use): 210 211 small: addresses use 24 bits, use bl to make calls 212 medium: addresses use 32 bits, use bl to make calls (*1) 213 large: addresses use 32 bits, use seth/add3/jl to make calls (*2) 214 215 The fourth is "addresses use 24 bits, use seth/add3/jl to make calls" but 216 using this one doesn't make much sense. 217 218 (*1) The linker may eventually be able to relax seth/add3 -> ld24. 219 (*2) The linker may eventually be able to relax seth/add3/jl -> bl. 220 221 Internally these are recorded as TARGET_ADDR{24,32} and 222 TARGET_CALL{26,32}. 223 224 The __model__ attribute can be used to select the code model to use when 225 accessing particular objects. */ 226 227 enum m32r_model { M32R_MODEL_SMALL, M32R_MODEL_MEDIUM, M32R_MODEL_LARGE }; 228 229 extern enum m32r_model m32r_model; 230 #define TARGET_MODEL_SMALL (m32r_model == M32R_MODEL_SMALL) 231 #define TARGET_MODEL_MEDIUM (m32r_model == M32R_MODEL_MEDIUM) 232 #define TARGET_MODEL_LARGE (m32r_model == M32R_MODEL_LARGE) 233 #define TARGET_ADDR24 (m32r_model == M32R_MODEL_SMALL) 234 #define TARGET_ADDR32 (! TARGET_ADDR24) 235 #define TARGET_CALL26 (! TARGET_CALL32) 236 #define TARGET_CALL32 (m32r_model == M32R_MODEL_LARGE) 237 238 /* The default is the small model. */ 239 #ifndef M32R_MODEL_DEFAULT 240 #define M32R_MODEL_DEFAULT M32R_MODEL_SMALL 241 #endif 242 243 /* Small Data Area 244 245 The SDA consists of sections .sdata, .sbss, and .scommon. 246 .scommon isn't a real section, symbols in it have their section index 247 set to SHN_M32R_SCOMMON, though support for it exists in the linker script. 248 249 Two switches control the SDA: 250 251 -G NNN - specifies the maximum size of variable to go in the SDA 252 253 -msdata=foo - specifies how such variables are handled 254 255 -msdata=none - small data area is disabled 256 257 -msdata=sdata - small data goes in the SDA, special code isn't 258 generated to use it, and special relocs aren't 259 generated 260 261 -msdata=use - small data goes in the SDA, special code is generated 262 to use the SDA and special relocs are generated 263 264 The SDA is not multilib'd, it isn't necessary. 265 MULTILIB_EXTRA_OPTS is set in tmake_file to -msdata=sdata so multilib'd 266 libraries have small data in .sdata/SHN_M32R_SCOMMON so programs that use 267 -msdata=use will successfully link with them (references in header files 268 will cause the compiler to emit code that refers to library objects in 269 .data). ??? There can be a problem if the user passes a -G value greater 270 than the default and a library object in a header file is that size. 271 The default is 8 so this should be rare - if it occurs the user 272 is required to rebuild the libraries or use a smaller value for -G. */ 273 274 /* Maximum size of variables that go in .sdata/.sbss. 275 The -msdata=foo switch also controls how small variables are handled. */ 276 #ifndef SDATA_DEFAULT_SIZE 277 #define SDATA_DEFAULT_SIZE 8 278 #endif 279 280 enum m32r_sdata { M32R_SDATA_NONE, M32R_SDATA_SDATA, M32R_SDATA_USE }; 281 282 extern enum m32r_sdata m32r_sdata; 283 #define TARGET_SDATA_NONE (m32r_sdata == M32R_SDATA_NONE) 284 #define TARGET_SDATA_SDATA (m32r_sdata == M32R_SDATA_SDATA) 285 #define TARGET_SDATA_USE (m32r_sdata == M32R_SDATA_USE) 286 287 /* Default is to disable the SDA 288 [for upward compatibility with previous toolchains]. */ 289 #ifndef M32R_SDATA_DEFAULT 290 #define M32R_SDATA_DEFAULT M32R_SDATA_NONE 291 #endif 292 293 /* Define this macro as a C expression for the initializer of an array of 294 strings to tell the driver program which options are defaults for this 295 target and thus do not need to be handled specially when using 296 `MULTILIB_OPTIONS'. */ 297 #ifndef SUBTARGET_MULTILIB_DEFAULTS 298 #define SUBTARGET_MULTILIB_DEFAULTS 299 #endif 300 301 #ifndef MULTILIB_DEFAULTS 302 #define MULTILIB_DEFAULTS { "mmodel=small" SUBTARGET_MULTILIB_DEFAULTS } 303 #endif 304 305 /* Sometimes certain combinations of command options do not make 306 sense on a particular target machine. You can define a macro 307 `OVERRIDE_OPTIONS' to take account of this. This macro, if 308 defined, is executed once just after all the command options have 309 been parsed. 310 311 Don't use this macro to turn on various extra optimizations for 312 `-O'. That is what `OPTIMIZATION_OPTIONS' is for. */ 313 314 #ifndef SUBTARGET_OVERRIDE_OPTIONS 315 #define SUBTARGET_OVERRIDE_OPTIONS 316 #endif 317 318 #define OVERRIDE_OPTIONS \ 319 do \ 320 { \ 321 /* These need to be done at start up. \ 322 It's convenient to do them here. */ \ 323 m32r_init (); \ 324 SUBTARGET_OVERRIDE_OPTIONS \ 325 } \ 326 while (0) 327 328 #ifndef SUBTARGET_OPTIMIZATION_OPTIONS 329 #define SUBTARGET_OPTIMIZATION_OPTIONS 330 #endif 331 332 #define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \ 333 do \ 334 { \ 335 if (LEVEL == 1) \ 336 flag_regmove = TRUE; \ 337 \ 338 if (SIZE) \ 339 { \ 340 flag_omit_frame_pointer = TRUE; \ 341 } \ 342 \ 343 SUBTARGET_OPTIMIZATION_OPTIONS \ 344 } \ 345 while (0) 346 347 /* Define this macro if debugging can be performed even without a 348 frame pointer. If this macro is defined, GCC will turn on the 349 `-fomit-frame-pointer' option whenever `-O' is specified. */ 350 #define CAN_DEBUG_WITHOUT_FP 351 352 /* Target machine storage layout. */ 353 354 /* Define this if most significant bit is lowest numbered 355 in instructions that operate on numbered bit-fields. */ 356 #define BITS_BIG_ENDIAN 1 357 358 /* Define this if most significant byte of a word is the lowest numbered. */ 359 #define BYTES_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 360 361 /* Define this if most significant word of a multiword number is the lowest 362 numbered. */ 363 #define WORDS_BIG_ENDIAN (TARGET_LITTLE_ENDIAN == 0) 364 365 /* Define this macro if WORDS_BIG_ENDIAN is not constant. This must 366 be a constant value with the same meaning as WORDS_BIG_ENDIAN, 367 which will be used only when compiling libgcc2.c. Typically the 368 value will be set based on preprocessor defines. */ 369 /*#define LIBGCC2_WORDS_BIG_ENDIAN 1*/ 370 371 /* Width of a word, in units (bytes). */ 372 #define UNITS_PER_WORD 4 373 374 /* Define this macro if it is advisable to hold scalars in registers 375 in a wider mode than that declared by the program. In such cases, 376 the value is constrained to be within the bounds of the declared 377 type, but kept valid in the wider mode. The signedness of the 378 extension may differ from that of the type. */ 379 #define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 380 if (GET_MODE_CLASS (MODE) == MODE_INT \ 381 && GET_MODE_SIZE (MODE) < UNITS_PER_WORD) \ 382 { \ 383 (MODE) = SImode; \ 384 } 385 386 /* Allocation boundary (in *bits*) for storing arguments in argument list. */ 387 #define PARM_BOUNDARY 32 388 389 /* Boundary (in *bits*) on which stack pointer should be aligned. */ 390 #define STACK_BOUNDARY 32 391 392 /* ALIGN FRAMES on word boundaries */ 393 #define M32R_STACK_ALIGN(LOC) (((LOC) + 3) & ~ 3) 394 395 /* Allocation boundary (in *bits*) for the code of a function. */ 396 #define FUNCTION_BOUNDARY 32 397 398 /* Alignment of field after `int : 0' in a structure. */ 399 #define EMPTY_FIELD_BOUNDARY 32 400 401 /* Every structure's size must be a multiple of this. */ 402 #define STRUCTURE_SIZE_BOUNDARY 8 403 404 /* A bit-field declared as `int' forces `int' alignment for the struct. */ 405 #define PCC_BITFIELD_TYPE_MATTERS 1 406 407 /* No data type wants to be aligned rounder than this. */ 408 #define BIGGEST_ALIGNMENT 32 409 410 /* The best alignment to use in cases where we have a choice. */ 411 #define FASTEST_ALIGNMENT 32 412 413 /* Make strings word-aligned so strcpy from constants will be faster. */ 414 #define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 415 ((TREE_CODE (EXP) == STRING_CST \ 416 && (ALIGN) < FASTEST_ALIGNMENT) \ 417 ? FASTEST_ALIGNMENT : (ALIGN)) 418 419 /* Make arrays of chars word-aligned for the same reasons. */ 420 #define DATA_ALIGNMENT(TYPE, ALIGN) \ 421 (TREE_CODE (TYPE) == ARRAY_TYPE \ 422 && TYPE_MODE (TREE_TYPE (TYPE)) == QImode \ 423 && (ALIGN) < FASTEST_ALIGNMENT ? FASTEST_ALIGNMENT : (ALIGN)) 424 425 /* Set this nonzero if move instructions will actually fail to work 426 when given unaligned data. */ 427 #define STRICT_ALIGNMENT 1 428 429 /* Define LAVEL_ALIGN to calculate code length of PNOP at labels. */ 430 #define LABEL_ALIGN(insn) 2 431 432 /* Layout of source language data types. */ 433 434 #define SHORT_TYPE_SIZE 16 435 #define INT_TYPE_SIZE 32 436 #define LONG_TYPE_SIZE 32 437 #define LONG_LONG_TYPE_SIZE 64 438 #define FLOAT_TYPE_SIZE 32 439 #define DOUBLE_TYPE_SIZE 64 440 #define LONG_DOUBLE_TYPE_SIZE 64 441 442 /* Define this as 1 if `char' should by default be signed; else as 0. */ 443 #define DEFAULT_SIGNED_CHAR 1 444 445 #define SIZE_TYPE "long unsigned int" 446 #define PTRDIFF_TYPE "long int" 447 #define WCHAR_TYPE "short unsigned int" 448 #define WCHAR_TYPE_SIZE 16 449 450 /* Standard register usage. */ 451 452 /* Number of actual hardware registers. 453 The hardware registers are assigned numbers for the compiler 454 from 0 to just below FIRST_PSEUDO_REGISTER. 455 All registers that the compiler knows about must be given numbers, 456 even those that are not normally considered general registers. */ 457 458 #define M32R_NUM_REGISTERS 19 459 460 #ifndef SUBTARGET_NUM_REGISTERS 461 #define SUBTARGET_NUM_REGISTERS 0 462 #endif 463 464 #define FIRST_PSEUDO_REGISTER (M32R_NUM_REGISTERS + SUBTARGET_NUM_REGISTERS) 465 466 /* 1 for registers that have pervasive standard uses 467 and are not available for the register allocator. 468 469 0-3 - arguments/results 470 4-5 - call used [4 is used as a tmp during prologue/epilogue generation] 471 6 - call used, gptmp 472 7 - call used, static chain pointer 473 8-11 - call saved 474 12 - call saved [reserved for global pointer] 475 13 - frame pointer 476 14 - subroutine link register 477 15 - stack pointer 478 16 - arg pointer 479 17 - carry flag 480 18 - accumulator 481 19 - accumulator 1 in the m32r/x 482 By default, the extension registers are not available. */ 483 484 #ifndef SUBTARGET_FIXED_REGISTERS 485 #define SUBTARGET_FIXED_REGISTERS 486 #endif 487 488 #define FIXED_REGISTERS \ 489 { \ 490 0, 0, 0, 0, 0, 0, 0, 0, \ 491 0, 0, 0, 0, 0, 0, 0, 1, \ 492 1, 1, 1 \ 493 SUBTARGET_FIXED_REGISTERS \ 494 } 495 496 /* 1 for registers not available across function calls. 497 These must include the FIXED_REGISTERS and also any 498 registers that can be used without being saved. 499 The latter must include the registers where values are returned 500 and the register where structure-value addresses are passed. 501 Aside from that, you can include as many other registers as you like. */ 502 503 #ifndef SUBTARGET_CALL_USED_REGISTERS 504 #define SUBTARGET_CALL_USED_REGISTERS 505 #endif 506 507 #define CALL_USED_REGISTERS \ 508 { \ 509 1, 1, 1, 1, 1, 1, 1, 1, \ 510 0, 0, 0, 0, 0, 0, 1, 1, \ 511 1, 1, 1 \ 512 SUBTARGET_CALL_USED_REGISTERS \ 513 } 514 515 #define CALL_REALLY_USED_REGISTERS CALL_USED_REGISTERS 516 517 /* Zero or more C statements that may conditionally modify two variables 518 `fixed_regs' and `call_used_regs' (both of type `char []') after they 519 have been initialized from the two preceding macros. 520 521 This is necessary in case the fixed or call-clobbered registers depend 522 on target flags. 523 524 You need not define this macro if it has no work to do. */ 525 526 #ifdef SUBTARGET_CONDITIONAL_REGISTER_USAGE 527 #define CONDITIONAL_REGISTER_USAGE SUBTARGET_CONDITIONAL_REGISTER_USAGE 528 #else 529 #define CONDITIONAL_REGISTER_USAGE \ 530 do \ 531 { \ 532 if (flag_pic) \ 533 { \ 534 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 535 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 536 } \ 537 } \ 538 while (0) 539 #endif 540 541 /* If defined, an initializer for a vector of integers, containing the 542 numbers of hard registers in the order in which GCC should 543 prefer to use them (from most preferred to least). */ 544 545 #ifndef SUBTARGET_REG_ALLOC_ORDER 546 #define SUBTARGET_REG_ALLOC_ORDER 547 #endif 548 549 #if 1 /* Better for int code. */ 550 #define REG_ALLOC_ORDER \ 551 { \ 552 4, 5, 6, 7, 2, 3, 8, 9, 10, \ 553 11, 12, 13, 14, 0, 1, 15, 16, 17, 18 \ 554 SUBTARGET_REG_ALLOC_ORDER \ 555 } 556 557 #else /* Better for fp code at expense of int code. */ 558 #define REG_ALLOC_ORDER \ 559 { \ 560 0, 1, 2, 3, 4, 5, 6, 7, 8, \ 561 9, 10, 11, 12, 13, 14, 15, 16, 17, 18 \ 562 SUBTARGET_REG_ALLOC_ORDER \ 563 } 564 #endif 565 566 /* Return number of consecutive hard regs needed starting at reg REGNO 567 to hold something of mode MODE. 568 This is ordinarily the length in words of a value of mode MODE 569 but can be less for certain modes in special long registers. */ 570 #define HARD_REGNO_NREGS(REGNO, MODE) \ 571 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 572 573 /* Value is 1 if hard register REGNO can hold a value of machine-mode MODE. */ 574 extern const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER]; 575 extern unsigned int m32r_mode_class[]; 576 #define HARD_REGNO_MODE_OK(REGNO, MODE) \ 577 ((m32r_hard_regno_mode_ok[REGNO] & m32r_mode_class[MODE]) != 0) 578 579 /* A C expression that is nonzero if it is desirable to choose 580 register allocation so as to avoid move instructions between a 581 value of mode MODE1 and a value of mode MODE2. 582 583 If `HARD_REGNO_MODE_OK (R, MODE1)' and `HARD_REGNO_MODE_OK (R, 584 MODE2)' are ever different for any R, then `MODES_TIEABLE_P (MODE1, 585 MODE2)' must be zero. */ 586 587 /* Tie QI/HI/SI modes together. */ 588 #define MODES_TIEABLE_P(MODE1, MODE2) \ 589 ( GET_MODE_CLASS (MODE1) == MODE_INT \ 590 && GET_MODE_CLASS (MODE2) == MODE_INT \ 591 && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD \ 592 && GET_MODE_SIZE (MODE2) <= UNITS_PER_WORD) 593 594 #define HARD_REGNO_RENAME_OK(OLD_REG, NEW_REG) \ 595 m32r_hard_regno_rename_ok (OLD_REG, NEW_REG) 596 597 /* Register classes and constants. */ 598 599 /* Define the classes of registers for register constraints in the 600 machine description. Also define ranges of constants. 601 602 One of the classes must always be named ALL_REGS and include all hard regs. 603 If there is more than one class, another class must be named NO_REGS 604 and contain no registers. 605 606 The name GENERAL_REGS must be the name of a class (or an alias for 607 another name such as ALL_REGS). This is the class of registers 608 that is allowed by "g" or "r" in a register constraint. 609 Also, registers outside this class are allocated only when 610 instructions express preferences for them. 611 612 The classes must be numbered in nondecreasing order; that is, 613 a larger-numbered class must never be contained completely 614 in a smaller-numbered class. 615 616 For any two classes, it is very desirable that there be another 617 class that represents their union. 618 619 It is important that any condition codes have class NO_REGS. 620 See `register_operand'. */ 621 622 enum reg_class 623 { 624 NO_REGS, CARRY_REG, ACCUM_REGS, GENERAL_REGS, ALL_REGS, LIM_REG_CLASSES 625 }; 626 627 #define IRA_COVER_CLASSES \ 628 { \ 629 ACCUM_REGS, GENERAL_REGS, LIM_REG_CLASSES \ 630 } 631 632 #define N_REG_CLASSES ((int) LIM_REG_CLASSES) 633 634 /* Give names of register classes as strings for dump file. */ 635 #define REG_CLASS_NAMES \ 636 { "NO_REGS", "CARRY_REG", "ACCUM_REGS", "GENERAL_REGS", "ALL_REGS" } 637 638 /* Define which registers fit in which classes. 639 This is an initializer for a vector of HARD_REG_SET 640 of length N_REG_CLASSES. */ 641 642 #ifndef SUBTARGET_REG_CLASS_CARRY 643 #define SUBTARGET_REG_CLASS_CARRY 0 644 #endif 645 646 #ifndef SUBTARGET_REG_CLASS_ACCUM 647 #define SUBTARGET_REG_CLASS_ACCUM 0 648 #endif 649 650 #ifndef SUBTARGET_REG_CLASS_GENERAL 651 #define SUBTARGET_REG_CLASS_GENERAL 0 652 #endif 653 654 #ifndef SUBTARGET_REG_CLASS_ALL 655 #define SUBTARGET_REG_CLASS_ALL 0 656 #endif 657 658 #define REG_CLASS_CONTENTS \ 659 { \ 660 { 0x00000 }, \ 661 { 0x20000 | SUBTARGET_REG_CLASS_CARRY }, \ 662 { 0x40000 | SUBTARGET_REG_CLASS_ACCUM }, \ 663 { 0x1ffff | SUBTARGET_REG_CLASS_GENERAL }, \ 664 { 0x7ffff | SUBTARGET_REG_CLASS_ALL }, \ 665 } 666 667 /* The same information, inverted: 668 Return the class number of the smallest class containing 669 reg number REGNO. This could be a conditional expression 670 or could index an array. */ 671 extern enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; 672 #define REGNO_REG_CLASS(REGNO) (m32r_regno_reg_class[REGNO]) 673 674 /* The class value for index registers, and the one for base regs. */ 675 #define INDEX_REG_CLASS GENERAL_REGS 676 #define BASE_REG_CLASS GENERAL_REGS 677 678 /* These assume that REGNO is a hard or pseudo reg number. 679 They give nonzero only if REGNO is a hard reg of the suitable class 680 or a pseudo reg currently allocated to a suitable hard reg. 681 Since they use reg_renumber, they are safe only once reg_renumber 682 has been allocated, which happens in local-alloc.c. */ 683 #define REGNO_OK_FOR_BASE_P(REGNO) \ 684 ((REGNO) < FIRST_PSEUDO_REGISTER \ 685 ? GPR_P (REGNO) || (REGNO) == ARG_POINTER_REGNUM \ 686 : GPR_P (reg_renumber[REGNO])) 687 688 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO) 689 690 /* Given an rtx X being reloaded into a reg required to be 691 in class CLASS, return the class of reg to actually use. 692 In general this is just CLASS; but on some machines 693 in some cases it is preferable to use a more restrictive class. */ 694 #define PREFERRED_RELOAD_CLASS(X,CLASS) (CLASS) 695 696 /* Return the maximum number of consecutive registers 697 needed to represent mode MODE in a register of class CLASS. */ 698 #define CLASS_MAX_NREGS(CLASS, MODE) \ 699 ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 700 701 /* Return true if a value is inside a range. */ 702 #define IN_RANGE_P(VALUE, LOW, HIGH) \ 703 (((unsigned HOST_WIDE_INT)((VALUE) - (LOW))) \ 704 <= ((unsigned HOST_WIDE_INT)((HIGH) - (LOW)))) 705 706 /* Some range macros. */ 707 #define INT16_P(X) ((X) >= - 0x8000 && (X) <= 0x7fff) 708 #define CMP_INT16_P(X) ((X) >= - 0x7fff && (X) <= 0x8000) 709 #define UINT16_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x0000ffff) 710 #define UINT24_P(X) (((unsigned HOST_WIDE_INT) (X)) <= 0x00ffffff) 711 712 /* Stack layout and stack pointer usage. */ 713 714 /* Define this macro if pushing a word onto the stack moves the stack 715 pointer to a smaller address. */ 716 #define STACK_GROWS_DOWNWARD 717 718 /* Offset from frame pointer to start allocating local variables at. 719 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 720 first local allocated. Otherwise, it is the offset to the BEGINNING 721 of the first local allocated. */ 722 /* The frame pointer points at the same place as the stack pointer, except if 723 alloca has been called. */ 724 #define STARTING_FRAME_OFFSET \ 725 M32R_STACK_ALIGN (crtl->outgoing_args_size) 726 727 /* Offset from the stack pointer register to the first location at which 728 outgoing arguments are placed. */ 729 #define STACK_POINTER_OFFSET 0 730 731 /* Offset of first parameter from the argument pointer register value. */ 732 #define FIRST_PARM_OFFSET(FNDECL) 0 733 734 /* Register to use for pushing function arguments. */ 735 #define STACK_POINTER_REGNUM 15 736 737 /* Base register for access to local variables of the function. */ 738 #define FRAME_POINTER_REGNUM 13 739 740 /* Base register for access to arguments of the function. */ 741 #define ARG_POINTER_REGNUM 16 742 743 /* Register in which static-chain is passed to a function. 744 This must not be a register used by the prologue. */ 745 #define STATIC_CHAIN_REGNUM 7 746 747 /* These aren't official macros. */ 748 #define PROLOGUE_TMP_REGNUM 4 749 #define RETURN_ADDR_REGNUM 14 750 /* #define GP_REGNUM 12 */ 751 #define CARRY_REGNUM 17 752 #define ACCUM_REGNUM 18 753 #define M32R_MAX_INT_REGS 16 754 755 #ifndef SUBTARGET_GPR_P 756 #define SUBTARGET_GPR_P(REGNO) 0 757 #endif 758 759 #ifndef SUBTARGET_ACCUM_P 760 #define SUBTARGET_ACCUM_P(REGNO) 0 761 #endif 762 763 #ifndef SUBTARGET_CARRY_P 764 #define SUBTARGET_CARRY_P(REGNO) 0 765 #endif 766 767 #define GPR_P(REGNO) (IN_RANGE_P ((REGNO), 0, 15) || SUBTARGET_GPR_P (REGNO)) 768 #define ACCUM_P(REGNO) ((REGNO) == ACCUM_REGNUM || SUBTARGET_ACCUM_P (REGNO)) 769 #define CARRY_P(REGNO) ((REGNO) == CARRY_REGNUM || SUBTARGET_CARRY_P (REGNO)) 770 771 /* Eliminating the frame and arg pointers. */ 772 773 #if 0 774 /* C statement to store the difference between the frame pointer 775 and the stack pointer values immediately after the function prologue. 776 If `ELIMINABLE_REGS' is defined, this macro will be not be used and 777 need not be defined. */ 778 #define INITIAL_FRAME_POINTER_OFFSET(VAR) \ 779 ((VAR) = m32r_compute_frame_size (get_frame_size ())) 780 #endif 781 782 /* If defined, this macro specifies a table of register pairs used to 783 eliminate unneeded registers that point into the stack frame. If 784 it is not defined, the only elimination attempted by the compiler 785 is to replace references to the frame pointer with references to 786 the stack pointer. 787 788 Note that the elimination of the argument pointer with the stack 789 pointer is specified first since that is the preferred elimination. */ 790 791 #define ELIMINABLE_REGS \ 792 {{ FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 793 { ARG_POINTER_REGNUM, STACK_POINTER_REGNUM }, \ 794 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM }} 795 796 /* This macro is similar to `INITIAL_FRAME_POINTER_OFFSET'. It 797 specifies the initial difference between the specified pair of 798 registers. This macro must be defined if `ELIMINABLE_REGS' is 799 defined. */ 800 801 #define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 802 do \ 803 { \ 804 int size = m32r_compute_frame_size (get_frame_size ()); \ 805 \ 806 if ((FROM) == FRAME_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ 807 (OFFSET) = 0; \ 808 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == FRAME_POINTER_REGNUM) \ 809 (OFFSET) = size - crtl->args.pretend_args_size; \ 810 else if ((FROM) == ARG_POINTER_REGNUM && (TO) == STACK_POINTER_REGNUM) \ 811 (OFFSET) = size - crtl->args.pretend_args_size; \ 812 else \ 813 gcc_unreachable (); \ 814 } \ 815 while (0) 816 817 /* Function argument passing. */ 818 819 /* If defined, the maximum amount of space required for outgoing 820 arguments will be computed and placed into the variable 821 `crtl->outgoing_args_size'. No space will be pushed 822 onto the stack for each call; instead, the function prologue should 823 increase the stack frame size by this amount. */ 824 #define ACCUMULATE_OUTGOING_ARGS 1 825 826 /* Value is the number of bytes of arguments automatically 827 popped when returning from a subroutine call. 828 FUNDECL is the declaration node of the function (as a tree), 829 FUNTYPE is the data type of the function (as a tree), 830 or for a library call it is an identifier node for the subroutine name. 831 SIZE is the number of bytes of arguments passed on the stack. */ 832 #define RETURN_POPS_ARGS(DECL, FUNTYPE, SIZE) 0 833 834 /* Define a data type for recording info about an argument list 835 during the scan of that argument list. This data type should 836 hold all necessary information about the function itself 837 and about the args processed so far, enough to enable macros 838 such as FUNCTION_ARG to determine where the next arg should go. */ 839 #define CUMULATIVE_ARGS int 840 841 /* Initialize a variable CUM of type CUMULATIVE_ARGS 842 for a call to a function whose data type is FNTYPE. 843 For a library call, FNTYPE is 0. */ 844 #define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, INDIRECT, N_NAMED_ARGS) \ 845 ((CUM) = 0) 846 847 /* The number of registers used for parameter passing. Local to this file. */ 848 #define M32R_MAX_PARM_REGS 4 849 850 /* 1 if N is a possible register number for function argument passing. */ 851 #define FUNCTION_ARG_REGNO_P(N) \ 852 ((unsigned) (N) < M32R_MAX_PARM_REGS) 853 854 /* The ROUND_ADVANCE* macros are local to this file. */ 855 /* Round SIZE up to a word boundary. */ 856 #define ROUND_ADVANCE(SIZE) \ 857 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 858 859 /* Round arg MODE/TYPE up to the next word boundary. */ 860 #define ROUND_ADVANCE_ARG(MODE, TYPE) \ 861 ((MODE) == BLKmode \ 862 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \ 863 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE))) 864 865 /* Round CUM up to the necessary point for argument MODE/TYPE. */ 866 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM) 867 868 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in 869 a reg. This includes arguments that have to be passed by reference as the 870 pointer to them is passed in a reg if one is available (and that is what 871 we're given). 872 This macro is only used in this file. */ 873 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 874 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS) 875 876 /* Determine where to put an argument to a function. 877 Value is zero to push the argument on the stack, 878 or a hard register in which to store the argument. 879 880 MODE is the argument's machine mode. 881 TYPE is the data type of the argument (as a tree). 882 This is null for libcalls where that information may 883 not be available. 884 CUM is a variable of type CUMULATIVE_ARGS which gives info about 885 the preceding args and about the function being called. 886 NAMED is nonzero if this argument is a named parameter 887 (otherwise it is an extra parameter matching an ellipsis). */ 888 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers 889 and the rest are pushed. */ 890 #define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 891 (PASS_IN_REG_P ((CUM), (MODE), (TYPE)) \ 892 ? gen_rtx_REG ((MODE), ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE))) \ 893 : 0) 894 895 /* Update the data in CUM to advance over an argument 896 of mode MODE and data type TYPE. 897 (TYPE is null for libcalls where that information may not be available.) */ 898 #define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 899 ((CUM) = (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) \ 900 + ROUND_ADVANCE_ARG ((MODE), (TYPE)))) 901 902 /* If defined, a C expression that gives the alignment boundary, in bits, 903 of an argument with the specified mode and type. If it is not defined, 904 PARM_BOUNDARY is used for all arguments. */ 905 #if 0 906 /* We assume PARM_BOUNDARY == UNITS_PER_WORD here. */ 907 #define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \ 908 (((TYPE) ? TYPE_ALIGN (TYPE) : GET_MODE_BITSIZE (MODE)) <= PARM_BOUNDARY \ 909 ? PARM_BOUNDARY : 2 * PARM_BOUNDARY) 910 #endif 911 912 /* Function results. */ 913 914 /* Define how to find the value returned by a function. 915 VALTYPE is the data type of the value (as a tree). 916 If the precise function being called is known, FUNC is its FUNCTION_DECL; 917 otherwise, FUNC is 0. */ 918 #define FUNCTION_VALUE(VALTYPE, FUNC) gen_rtx_REG (TYPE_MODE (VALTYPE), 0) 919 920 /* Define how to find the value returned by a library function 921 assuming the value has mode MODE. */ 922 #define LIBCALL_VALUE(MODE) gen_rtx_REG (MODE, 0) 923 924 /* 1 if N is a possible register number for a function value 925 as seen by the caller. */ 926 /* ??? What about r1 in DI/DF values. */ 927 #define FUNCTION_VALUE_REGNO_P(N) ((N) == 0) 928 929 /* Tell GCC to use TARGET_RETURN_IN_MEMORY. */ 930 #define DEFAULT_PCC_STRUCT_RETURN 0 931 932 /* Function entry and exit. */ 933 934 /* Initialize data used by insn expanders. This is called from 935 init_emit, once for each function, before code is generated. */ 936 #define INIT_EXPANDERS m32r_init_expanders () 937 938 /* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 939 the stack pointer does not matter. The value is tested only in 940 functions that have frame pointers. 941 No definition is equivalent to always zero. */ 942 #define EXIT_IGNORE_STACK 1 943 944 /* Output assembler code to FILE to increment profiler label # LABELNO 945 for profiling a function entry. */ 946 #undef FUNCTION_PROFILER 947 #define FUNCTION_PROFILER(FILE, LABELNO) \ 948 do \ 949 { \ 950 if (flag_pic) \ 951 { \ 952 fprintf (FILE, "\tld24 r14,#mcount\n"); \ 953 fprintf (FILE, "\tadd r14,r12\n"); \ 954 fprintf (FILE, "\tld r14,@r14\n"); \ 955 fprintf (FILE, "\tjl r14\n"); \ 956 } \ 957 else \ 958 { \ 959 if (TARGET_ADDR24) \ 960 fprintf (FILE, "\tbl mcount\n"); \ 961 else \ 962 { \ 963 fprintf (FILE, "\tseth r14,#high(mcount)\n"); \ 964 fprintf (FILE, "\tor3 r14,r14,#low(mcount)\n"); \ 965 fprintf (FILE, "\tjl r14\n"); \ 966 } \ 967 } \ 968 fprintf (FILE, "\taddi sp,#4\n"); \ 969 } \ 970 while (0) 971 972 /* Trampolines. */ 973 974 /* On the M32R, the trampoline is: 975 976 mv r7, lr -> bl L1 ; 178e 7e01 977 L1: add3 r6, lr, #L2-L1 ; 86ae 000c (L2 - L1 = 12) 978 mv lr, r7 -> ld r7,@r6+ ; 1e87 27e6 979 ld r6, @r6 -> jmp r6 ; 26c6 1fc6 980 L2: .word STATIC 981 .word FUNCTION */ 982 983 #ifndef CACHE_FLUSH_FUNC 984 #define CACHE_FLUSH_FUNC "_flush_cache" 985 #endif 986 #ifndef CACHE_FLUSH_TRAP 987 #define CACHE_FLUSH_TRAP 12 988 #endif 989 990 /* Length in bytes of the trampoline for entering a nested function. */ 991 #define TRAMPOLINE_SIZE 24 992 993 994 #define RETURN_ADDR_RTX(COUNT, FRAME) m32r_return_addr (COUNT) 995 996 #define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM) 997 998 /* Addressing modes, and classification of registers for them. */ 999 1000 /* Maximum number of registers that can appear in a valid memory address. */ 1001 #define MAX_REGS_PER_ADDRESS 1 1002 1003 /* We have post-inc load and pre-dec,pre-inc store, 1004 but only for 4 byte vals. */ 1005 #define HAVE_PRE_DECREMENT 1 1006 #define HAVE_PRE_INCREMENT 1 1007 #define HAVE_POST_INCREMENT 1 1008 1009 /* Recognize any constant value that is a valid address. */ 1010 #define CONSTANT_ADDRESS_P(X) \ 1011 ( GET_CODE (X) == LABEL_REF \ 1012 || GET_CODE (X) == SYMBOL_REF \ 1013 || CONST_INT_P (X) \ 1014 || (GET_CODE (X) == CONST \ 1015 && ! (flag_pic && ! m32r_legitimate_pic_operand_p (X)))) 1016 1017 /* Nonzero if the constant value X is a legitimate general operand. 1018 We don't allow (plus symbol large-constant) as the relocations can't 1019 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations. 1020 We allow all CONST_DOUBLE's as the md file patterns will force the 1021 constant to memory if they can't handle them. */ 1022 1023 #define LEGITIMATE_CONSTANT_P(X) \ 1024 (! (GET_CODE (X) == CONST \ 1025 && GET_CODE (XEXP (X, 0)) == PLUS \ 1026 && (GET_CODE (XEXP (XEXP (X, 0), 0)) == SYMBOL_REF || GET_CODE (XEXP (XEXP (X, 0), 0)) == LABEL_REF) \ 1027 && CONST_INT_P (XEXP (XEXP (X, 0), 1)) \ 1028 && (unsigned HOST_WIDE_INT) INTVAL (XEXP (XEXP (X, 0), 1)) > 32767)) 1029 1030 /* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 1031 and check its validity for a certain class. 1032 We have two alternate definitions for each of them. 1033 The usual definition accepts all pseudo regs; the other rejects 1034 them unless they have been allocated suitable hard regs. 1035 The symbol REG_OK_STRICT causes the latter definition to be used. 1036 1037 Most source files want to accept pseudo regs in the hope that 1038 they will get allocated to the class that the insn wants them to be in. 1039 Source files for reload pass need to be strict. 1040 After reload, it makes no difference, since pseudo regs have 1041 been eliminated by then. */ 1042 1043 #ifdef REG_OK_STRICT 1044 1045 /* Nonzero if X is a hard reg that can be used as a base reg. */ 1046 #define REG_OK_FOR_BASE_P(X) GPR_P (REGNO (X)) 1047 /* Nonzero if X is a hard reg that can be used as an index. */ 1048 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) 1049 1050 #else 1051 1052 /* Nonzero if X is a hard reg that can be used as a base reg 1053 or if it is a pseudo reg. */ 1054 #define REG_OK_FOR_BASE_P(X) \ 1055 (GPR_P (REGNO (X)) \ 1056 || (REGNO (X)) == ARG_POINTER_REGNUM \ 1057 || REGNO (X) >= FIRST_PSEUDO_REGISTER) 1058 /* Nonzero if X is a hard reg that can be used as an index 1059 or if it is a pseudo reg. */ 1060 #define REG_OK_FOR_INDEX_P(X) REG_OK_FOR_BASE_P (X) 1061 1062 #endif 1063 1064 /* GO_IF_LEGITIMATE_ADDRESS recognizes an RTL expression 1065 that is a valid memory address for an instruction. 1066 The MODE argument is the machine mode for the MEM expression 1067 that wants to use this address. */ 1068 1069 /* Local to this file. */ 1070 #define RTX_OK_FOR_BASE_P(X) (REG_P (X) && REG_OK_FOR_BASE_P (X)) 1071 1072 /* Local to this file. */ 1073 #define RTX_OK_FOR_OFFSET_P(X) \ 1074 (CONST_INT_P (X) && INT16_P (INTVAL (X))) 1075 1076 /* Local to this file. */ 1077 #define LEGITIMATE_OFFSET_ADDRESS_P(MODE, X) \ 1078 (GET_CODE (X) == PLUS \ 1079 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ 1080 && RTX_OK_FOR_OFFSET_P (XEXP (X, 1))) 1081 1082 /* Local to this file. */ 1083 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word, 1084 since more than one instruction will be required. */ 1085 #define LEGITIMATE_LO_SUM_ADDRESS_P(MODE, X) \ 1086 (GET_CODE (X) == LO_SUM \ 1087 && (MODE != BLKmode && GET_MODE_SIZE (MODE) <= UNITS_PER_WORD)\ 1088 && RTX_OK_FOR_BASE_P (XEXP (X, 0)) \ 1089 && CONSTANT_P (XEXP (X, 1))) 1090 1091 /* Local to this file. */ 1092 /* Is this a load and increment operation. */ 1093 #define LOAD_POSTINC_P(MODE, X) \ 1094 (((MODE) == SImode || (MODE) == SFmode) \ 1095 && GET_CODE (X) == POST_INC \ 1096 && REG_P (XEXP (X, 0)) \ 1097 && RTX_OK_FOR_BASE_P (XEXP (X, 0))) 1098 1099 /* Local to this file. */ 1100 /* Is this an increment/decrement and store operation. */ 1101 #define STORE_PREINC_PREDEC_P(MODE, X) \ 1102 (((MODE) == SImode || (MODE) == SFmode) \ 1103 && (GET_CODE (X) == PRE_INC || GET_CODE (X) == PRE_DEC) \ 1104 && REG_P (XEXP (X, 0)) \ 1105 && RTX_OK_FOR_BASE_P (XEXP (X, 0))) 1106 1107 #define GO_IF_LEGITIMATE_ADDRESS(MODE, X, ADDR) \ 1108 do \ 1109 { \ 1110 if (RTX_OK_FOR_BASE_P (X)) \ 1111 goto ADDR; \ 1112 if (LEGITIMATE_OFFSET_ADDRESS_P ((MODE), (X))) \ 1113 goto ADDR; \ 1114 if (LEGITIMATE_LO_SUM_ADDRESS_P ((MODE), (X))) \ 1115 goto ADDR; \ 1116 if (LOAD_POSTINC_P ((MODE), (X))) \ 1117 goto ADDR; \ 1118 if (STORE_PREINC_PREDEC_P ((MODE), (X))) \ 1119 goto ADDR; \ 1120 } \ 1121 while (0) 1122 1123 /* Go to LABEL if ADDR (a legitimate address expression) 1124 has an effect that depends on the machine mode it is used for. */ 1125 #define GO_IF_MODE_DEPENDENT_ADDRESS(ADDR, LABEL) \ 1126 do \ 1127 { \ 1128 if (GET_CODE (ADDR) == LO_SUM) \ 1129 goto LABEL; \ 1130 } \ 1131 while (0) 1132 1133 /* Condition code usage. */ 1134 1135 /* Return nonzero if SELECT_CC_MODE will never return MODE for a 1136 floating point inequality comparison. */ 1137 #define REVERSIBLE_CC_MODE(MODE) 1 /*???*/ 1138 1139 /* Costs. */ 1140 1141 /* Compute extra cost of moving data between one register class 1142 and another. */ 1143 #define REGISTER_MOVE_COST(MODE, CLASS1, CLASS2) 2 1144 1145 /* Compute the cost of moving data between registers and memory. */ 1146 /* Memory is 3 times as expensive as registers. 1147 ??? Is that the right way to look at it? */ 1148 #define MEMORY_MOVE_COST(MODE,CLASS,IN_P) \ 1149 (GET_MODE_SIZE (MODE) <= UNITS_PER_WORD ? 6 : 12) 1150 1151 /* The cost of a branch insn. */ 1152 /* A value of 2 here causes GCC to avoid using branches in comparisons like 1153 while (a < N && a). Branches aren't that expensive on the M32R so 1154 we define this as 1. Defining it as 2 had a heavy hit in fp-bit.c. */ 1155 #define BRANCH_COST(speed_p, predictable_p) ((TARGET_BRANCH_COST) ? 2 : 1) 1156 1157 /* Nonzero if access to memory by bytes is slow and undesirable. 1158 For RISC chips, it means that access to memory by bytes is no 1159 better than access by words when possible, so grab a whole word 1160 and maybe make use of that. */ 1161 #define SLOW_BYTE_ACCESS 1 1162 1163 /* Define this macro if it is as good or better to call a constant 1164 function address than to call an address kept in a register. */ 1165 #define NO_FUNCTION_CSE 1166 1167 /* Section selection. */ 1168 1169 #define TEXT_SECTION_ASM_OP "\t.section .text" 1170 #define DATA_SECTION_ASM_OP "\t.section .data" 1171 #define BSS_SECTION_ASM_OP "\t.section .bss" 1172 1173 /* Define this macro if jump tables (for tablejump insns) should be 1174 output in the text section, along with the assembler instructions. 1175 Otherwise, the readonly data section is used. 1176 This macro is irrelevant if there is no separate readonly data section. */ 1177 #define JUMP_TABLES_IN_TEXT_SECTION (flag_pic) 1178 1179 /* Position Independent Code. */ 1180 1181 /* The register number of the register used to address a table of static 1182 data addresses in memory. In some cases this register is defined by a 1183 processor's ``application binary interface'' (ABI). When this macro 1184 is defined, RTL is generated for this register once, as with the stack 1185 pointer and frame pointer registers. If this macro is not defined, it 1186 is up to the machine-dependent files to allocate such a register (if 1187 necessary). */ 1188 #define PIC_OFFSET_TABLE_REGNUM 12 1189 1190 /* Define this macro if the register defined by PIC_OFFSET_TABLE_REGNUM is 1191 clobbered by calls. Do not define this macro if PIC_OFFSET_TABLE_REGNUM 1192 is not defined. */ 1193 /* This register is call-saved on the M32R. */ 1194 /*#define PIC_OFFSET_TABLE_REG_CALL_CLOBBERED*/ 1195 1196 /* A C expression that is nonzero if X is a legitimate immediate 1197 operand on the target machine when generating position independent code. 1198 You can assume that X satisfies CONSTANT_P, so you need not 1199 check this. You can also assume `flag_pic' is true, so you need not 1200 check it either. You need not define this macro if all constants 1201 (including SYMBOL_REF) can be immediate operands when generating 1202 position independent code. */ 1203 #define LEGITIMATE_PIC_OPERAND_P(X) m32r_legitimate_pic_operand_p (X) 1204 1205 /* Control the assembler format that we output. */ 1206 1207 /* A C string constant describing how to begin a comment in the target 1208 assembler language. The compiler assumes that the comment will 1209 end at the end of the line. */ 1210 #define ASM_COMMENT_START ";" 1211 1212 /* Output to assembler file text saying following lines 1213 may contain character constants, extra white space, comments, etc. */ 1214 #define ASM_APP_ON "" 1215 1216 /* Output to assembler file text saying following lines 1217 no longer contain unusual constructs. */ 1218 #define ASM_APP_OFF "" 1219 1220 /* Globalizing directive for a label. */ 1221 #define GLOBAL_ASM_OP "\t.global\t" 1222 1223 /* We do not use DBX_LINES_FUNCTION_RELATIVE or 1224 dbxout_stab_value_internal_label_diff here because 1225 we need to use .debugsym for the line label. */ 1226 1227 #define DBX_OUTPUT_SOURCE_LINE(file, line, counter) \ 1228 do \ 1229 { \ 1230 const char * begin_label = \ 1231 XSTR (XEXP (DECL_RTL (current_function_decl), 0), 0); \ 1232 char label[64]; \ 1233 ASM_GENERATE_INTERNAL_LABEL (label, "LM", counter); \ 1234 \ 1235 dbxout_begin_stabn_sline (line); \ 1236 assemble_name (file, label); \ 1237 putc ('-', file); \ 1238 assemble_name (file, begin_label); \ 1239 fputs ("\n\t.debugsym ", file); \ 1240 assemble_name (file, label); \ 1241 putc ('\n', file); \ 1242 counter += 1; \ 1243 } \ 1244 while (0) 1245 1246 /* How to refer to registers in assembler output. 1247 This sequence is indexed by compiler's hard-register-number (see above). */ 1248 #ifndef SUBTARGET_REGISTER_NAMES 1249 #define SUBTARGET_REGISTER_NAMES 1250 #endif 1251 1252 #define REGISTER_NAMES \ 1253 { \ 1254 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", \ 1255 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", \ 1256 "ap", "cbit", "a0" \ 1257 SUBTARGET_REGISTER_NAMES \ 1258 } 1259 1260 /* If defined, a C initializer for an array of structures containing 1261 a name and a register number. This macro defines additional names 1262 for hard registers, thus allowing the `asm' option in declarations 1263 to refer to registers using alternate names. */ 1264 #ifndef SUBTARGET_ADDITIONAL_REGISTER_NAMES 1265 #define SUBTARGET_ADDITIONAL_REGISTER_NAMES 1266 #endif 1267 1268 #define ADDITIONAL_REGISTER_NAMES \ 1269 { \ 1270 /*{ "gp", GP_REGNUM },*/ \ 1271 { "r13", FRAME_POINTER_REGNUM }, \ 1272 { "r14", RETURN_ADDR_REGNUM }, \ 1273 { "r15", STACK_POINTER_REGNUM }, \ 1274 SUBTARGET_ADDITIONAL_REGISTER_NAMES \ 1275 } 1276 1277 /* A C expression which evaluates to true if CODE is a valid 1278 punctuation character for use in the `PRINT_OPERAND' macro. */ 1279 extern char m32r_punct_chars[256]; 1280 #define PRINT_OPERAND_PUNCT_VALID_P(CHAR) \ 1281 m32r_punct_chars[(unsigned char) (CHAR)] 1282 1283 /* Print operand X (an rtx) in assembler syntax to file FILE. 1284 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 1285 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 1286 #define PRINT_OPERAND(FILE, X, CODE) \ 1287 m32r_print_operand (FILE, X, CODE) 1288 1289 /* A C compound statement to output to stdio stream STREAM the 1290 assembler syntax for an instruction operand that is a memory 1291 reference whose address is ADDR. ADDR is an RTL expression. */ 1292 #define PRINT_OPERAND_ADDRESS(FILE, ADDR) \ 1293 m32r_print_operand_address (FILE, ADDR) 1294 1295 /* If defined, C string expressions to be used for the `%R', `%L', 1296 `%U', and `%I' options of `asm_fprintf' (see `final.c'). These 1297 are useful when a single `md' file must support multiple assembler 1298 formats. In that case, the various `tm.h' files can define these 1299 macros differently. */ 1300 #define REGISTER_PREFIX "" 1301 #define LOCAL_LABEL_PREFIX ".L" 1302 #define USER_LABEL_PREFIX "" 1303 #define IMMEDIATE_PREFIX "#" 1304 1305 /* This is how to output an element of a case-vector that is absolute. */ 1306 #define ASM_OUTPUT_ADDR_VEC_ELT(FILE, VALUE) \ 1307 do \ 1308 { \ 1309 char label[30]; \ 1310 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1311 fprintf (FILE, "\t.word\t"); \ 1312 assemble_name (FILE, label); \ 1313 fprintf (FILE, "\n"); \ 1314 } \ 1315 while (0) 1316 1317 /* This is how to output an element of a case-vector that is relative. */ 1318 #define ASM_OUTPUT_ADDR_DIFF_ELT(FILE, BODY, VALUE, REL)\ 1319 do \ 1320 { \ 1321 char label[30]; \ 1322 ASM_GENERATE_INTERNAL_LABEL (label, "L", VALUE); \ 1323 fprintf (FILE, "\t.word\t"); \ 1324 assemble_name (FILE, label); \ 1325 fprintf (FILE, "-"); \ 1326 ASM_GENERATE_INTERNAL_LABEL (label, "L", REL); \ 1327 assemble_name (FILE, label); \ 1328 fprintf (FILE, "\n"); \ 1329 } \ 1330 while (0) 1331 1332 /* The desired alignment for the location counter at the beginning 1333 of a loop. */ 1334 /* On the M32R, align loops to 32 byte boundaries (cache line size) 1335 if -malign-loops. */ 1336 #define LOOP_ALIGN(LABEL) (TARGET_ALIGN_LOOPS ? 5 : 0) 1337 1338 /* Define this to be the maximum number of insns to move around when moving 1339 a loop test from the top of a loop to the bottom 1340 and seeing whether to duplicate it. The default is thirty. 1341 1342 Loop unrolling currently doesn't like this optimization, so 1343 disable doing if we are unrolling loops and saving space. */ 1344 #define LOOP_TEST_THRESHOLD (optimize_size \ 1345 && !flag_unroll_loops \ 1346 && !flag_unroll_all_loops ? 2 : 30) 1347 1348 /* This is how to output an assembler line 1349 that says to advance the location counter 1350 to a multiple of 2**LOG bytes. */ 1351 /* .balign is used to avoid confusion. */ 1352 #define ASM_OUTPUT_ALIGN(FILE,LOG) \ 1353 do \ 1354 { \ 1355 if ((LOG) != 0) \ 1356 fprintf (FILE, "\t.balign %d\n", 1 << (LOG)); \ 1357 } \ 1358 while (0) 1359 1360 /* Like `ASM_OUTPUT_COMMON' except takes the required alignment as a 1361 separate, explicit argument. If you define this macro, it is used in 1362 place of `ASM_OUTPUT_COMMON', and gives you more flexibility in 1363 handling the required alignment of the variable. The alignment is 1364 specified as the number of bits. */ 1365 1366 #define SCOMMON_ASM_OP "\t.scomm\t" 1367 1368 #undef ASM_OUTPUT_ALIGNED_COMMON 1369 #define ASM_OUTPUT_ALIGNED_COMMON(FILE, NAME, SIZE, ALIGN) \ 1370 do \ 1371 { \ 1372 if (! TARGET_SDATA_NONE \ 1373 && (SIZE) > 0 && (SIZE) <= g_switch_value) \ 1374 fprintf ((FILE), "%s", SCOMMON_ASM_OP); \ 1375 else \ 1376 fprintf ((FILE), "%s", COMMON_ASM_OP); \ 1377 assemble_name ((FILE), (NAME)); \ 1378 fprintf ((FILE), ",%u,%u\n", (int)(SIZE), (ALIGN) / BITS_PER_UNIT);\ 1379 } \ 1380 while (0) 1381 1382 #define ASM_OUTPUT_ALIGNED_BSS(FILE, DECL, NAME, SIZE, ALIGN) \ 1383 do \ 1384 { \ 1385 if (! TARGET_SDATA_NONE \ 1386 && (SIZE) > 0 && (SIZE) <= g_switch_value) \ 1387 switch_to_section (get_named_section (NULL, ".sbss", 0)); \ 1388 else \ 1389 switch_to_section (bss_section); \ 1390 ASM_OUTPUT_ALIGN (FILE, floor_log2 (ALIGN / BITS_PER_UNIT)); \ 1391 last_assemble_variable_decl = DECL; \ 1392 ASM_DECLARE_OBJECT_NAME (FILE, NAME, DECL); \ 1393 ASM_OUTPUT_SKIP (FILE, SIZE ? SIZE : 1); \ 1394 } \ 1395 while (0) 1396 1397 /* Debugging information. */ 1398 1399 /* Generate DBX and DWARF debugging information. */ 1400 #define DBX_DEBUGGING_INFO 1 1401 #define DWARF2_DEBUGGING_INFO 1 1402 1403 /* Use DWARF2 debugging info by default. */ 1404 #undef PREFERRED_DEBUGGING_TYPE 1405 #define PREFERRED_DEBUGGING_TYPE DWARF2_DEBUG 1406 1407 /* Turn off splitting of long stabs. */ 1408 #define DBX_CONTIN_LENGTH 0 1409 1410 /* Miscellaneous. */ 1411 1412 /* Specify the machine mode that this machine uses 1413 for the index in the tablejump instruction. */ 1414 #define CASE_VECTOR_MODE (flag_pic ? SImode : Pmode) 1415 1416 /* Define if operations between registers always perform the operation 1417 on the full register even if a narrower mode is specified. */ 1418 #define WORD_REGISTER_OPERATIONS 1419 1420 /* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 1421 will either zero-extend or sign-extend. The value of this macro should 1422 be the code that says which one of the two operations is implicitly 1423 done, UNKNOWN if none. */ 1424 #define LOAD_EXTEND_OP(MODE) ZERO_EXTEND 1425 1426 /* Max number of bytes we can move from memory 1427 to memory in one reasonably fast instruction. */ 1428 #define MOVE_MAX 4 1429 1430 /* Define this to be nonzero if shift instructions ignore all but the low-order 1431 few bits. */ 1432 #define SHIFT_COUNT_TRUNCATED 1 1433 1434 /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits 1435 is done just by pretending it is already truncated. */ 1436 #define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 1437 1438 /* Specify the machine mode that pointers have. 1439 After generation of rtl, the compiler makes no further distinction 1440 between pointers and any other objects of this machine mode. */ 1441 /* ??? The M32R doesn't have full 32-bit pointers, but making this PSImode has 1442 its own problems (you have to add extendpsisi2 and truncsipsi2). 1443 Try to avoid it. */ 1444 #define Pmode SImode 1445 1446 /* A function address in a call instruction. */ 1447 #define FUNCTION_MODE SImode 1448 1449 /* M32R function types. */ 1450 enum m32r_function_type 1451 { 1452 M32R_FUNCTION_UNKNOWN, M32R_FUNCTION_NORMAL, M32R_FUNCTION_INTERRUPT 1453 }; 1454 1455 #define M32R_INTERRUPT_P(TYPE) ((TYPE) == M32R_FUNCTION_INTERRUPT) 1456 1457 /* The maximum number of bytes to copy using pairs of load/store instructions. 1458 If a block is larger than this then a loop will be generated to copy 1459 MAX_MOVE_BYTES chunks at a time. The value of 32 is a semi-arbitrary choice. 1460 A customer uses Dhrystome as their benchmark, and Dhrystone has a 31 byte 1461 string copy in it. */ 1462 #define MAX_MOVE_BYTES 32 1463