1 /* Subroutines used for code generation on the Renesas M32R cpu. 2 Copyright (C) 1996-2013 Free Software Foundation, Inc. 3 4 This file is part of GCC. 5 6 GCC is free software; you can redistribute it and/or modify it 7 under the terms of the GNU General Public License as published 8 by the Free Software Foundation; either version 3, or (at your 9 option) any later version. 10 11 GCC is distributed in the hope that it will be useful, but WITHOUT 12 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 13 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 14 License for more details. 15 16 You should have received a copy of the GNU General Public License 17 along with GCC; see the file COPYING3. If not see 18 <http://www.gnu.org/licenses/>. */ 19 20 #include "config.h" 21 #include "system.h" 22 #include "coretypes.h" 23 #include "tm.h" 24 #include "tree.h" 25 #include "rtl.h" 26 #include "regs.h" 27 #include "hard-reg-set.h" 28 #include "insn-config.h" 29 #include "conditions.h" 30 #include "output.h" 31 #include "dbxout.h" 32 #include "insn-attr.h" 33 #include "flags.h" 34 #include "expr.h" 35 #include "function.h" 36 #include "recog.h" 37 #include "diagnostic-core.h" 38 #include "ggc.h" 39 #include "df.h" 40 #include "tm_p.h" 41 #include "target.h" 42 #include "target-def.h" 43 #include "tm-constrs.h" 44 #include "opts.h" 45 46 /* Array of valid operand punctuation characters. */ 47 static char m32r_punct_chars[256]; 48 49 /* Machine-specific symbol_ref flags. */ 50 #define SYMBOL_FLAG_MODEL_SHIFT SYMBOL_FLAG_MACH_DEP_SHIFT 51 #define SYMBOL_REF_MODEL(X) \ 52 ((enum m32r_model) ((SYMBOL_REF_FLAGS (X) >> SYMBOL_FLAG_MODEL_SHIFT) & 3)) 53 54 /* For string literals, etc. */ 55 #define LIT_NAME_P(NAME) ((NAME)[0] == '*' && (NAME)[1] == '.') 56 57 /* Forward declaration. */ 58 static void m32r_option_override (void); 59 static void init_reg_tables (void); 60 static void block_move_call (rtx, rtx, rtx); 61 static int m32r_is_insn (rtx); 62 static bool m32r_legitimate_address_p (enum machine_mode, rtx, bool); 63 static rtx m32r_legitimize_address (rtx, rtx, enum machine_mode); 64 static bool m32r_mode_dependent_address_p (const_rtx, addr_space_t); 65 static tree m32r_handle_model_attribute (tree *, tree, tree, int, bool *); 66 static void m32r_print_operand (FILE *, rtx, int); 67 static void m32r_print_operand_address (FILE *, rtx); 68 static bool m32r_print_operand_punct_valid_p (unsigned char code); 69 static void m32r_output_function_prologue (FILE *, HOST_WIDE_INT); 70 static void m32r_output_function_epilogue (FILE *, HOST_WIDE_INT); 71 72 static void m32r_file_start (void); 73 74 static int m32r_adjust_priority (rtx, int); 75 static int m32r_issue_rate (void); 76 77 static void m32r_encode_section_info (tree, rtx, int); 78 static bool m32r_in_small_data_p (const_tree); 79 static bool m32r_return_in_memory (const_tree, const_tree); 80 static rtx m32r_function_value (const_tree, const_tree, bool); 81 static rtx m32r_libcall_value (enum machine_mode, const_rtx); 82 static bool m32r_function_value_regno_p (const unsigned int); 83 static void m32r_setup_incoming_varargs (cumulative_args_t, enum machine_mode, 84 tree, int *, int); 85 static void init_idents (void); 86 static bool m32r_rtx_costs (rtx, int, int, int, int *, bool speed); 87 static int m32r_memory_move_cost (enum machine_mode, reg_class_t, bool); 88 static bool m32r_pass_by_reference (cumulative_args_t, enum machine_mode, 89 const_tree, bool); 90 static int m32r_arg_partial_bytes (cumulative_args_t, enum machine_mode, 91 tree, bool); 92 static rtx m32r_function_arg (cumulative_args_t, enum machine_mode, 93 const_tree, bool); 94 static void m32r_function_arg_advance (cumulative_args_t, enum machine_mode, 95 const_tree, bool); 96 static bool m32r_can_eliminate (const int, const int); 97 static void m32r_conditional_register_usage (void); 98 static void m32r_trampoline_init (rtx, tree, rtx); 99 static bool m32r_legitimate_constant_p (enum machine_mode, rtx); 100 101 /* M32R specific attributes. */ 102 103 static const struct attribute_spec m32r_attribute_table[] = 104 { 105 /* { name, min_len, max_len, decl_req, type_req, fn_type_req, handler, 106 affects_type_identity } */ 107 { "interrupt", 0, 0, true, false, false, NULL, false }, 108 { "model", 1, 1, true, false, false, m32r_handle_model_attribute, 109 false }, 110 { NULL, 0, 0, false, false, false, NULL, false } 111 }; 112 113 /* Initialize the GCC target structure. */ 114 #undef TARGET_ATTRIBUTE_TABLE 115 #define TARGET_ATTRIBUTE_TABLE m32r_attribute_table 116 117 #undef TARGET_LEGITIMATE_ADDRESS_P 118 #define TARGET_LEGITIMATE_ADDRESS_P m32r_legitimate_address_p 119 #undef TARGET_LEGITIMIZE_ADDRESS 120 #define TARGET_LEGITIMIZE_ADDRESS m32r_legitimize_address 121 #undef TARGET_MODE_DEPENDENT_ADDRESS_P 122 #define TARGET_MODE_DEPENDENT_ADDRESS_P m32r_mode_dependent_address_p 123 124 #undef TARGET_ASM_ALIGNED_HI_OP 125 #define TARGET_ASM_ALIGNED_HI_OP "\t.hword\t" 126 #undef TARGET_ASM_ALIGNED_SI_OP 127 #define TARGET_ASM_ALIGNED_SI_OP "\t.word\t" 128 129 #undef TARGET_PRINT_OPERAND 130 #define TARGET_PRINT_OPERAND m32r_print_operand 131 #undef TARGET_PRINT_OPERAND_ADDRESS 132 #define TARGET_PRINT_OPERAND_ADDRESS m32r_print_operand_address 133 #undef TARGET_PRINT_OPERAND_PUNCT_VALID_P 134 #define TARGET_PRINT_OPERAND_PUNCT_VALID_P m32r_print_operand_punct_valid_p 135 136 #undef TARGET_ASM_FUNCTION_PROLOGUE 137 #define TARGET_ASM_FUNCTION_PROLOGUE m32r_output_function_prologue 138 #undef TARGET_ASM_FUNCTION_EPILOGUE 139 #define TARGET_ASM_FUNCTION_EPILOGUE m32r_output_function_epilogue 140 141 #undef TARGET_ASM_FILE_START 142 #define TARGET_ASM_FILE_START m32r_file_start 143 144 #undef TARGET_SCHED_ADJUST_PRIORITY 145 #define TARGET_SCHED_ADJUST_PRIORITY m32r_adjust_priority 146 #undef TARGET_SCHED_ISSUE_RATE 147 #define TARGET_SCHED_ISSUE_RATE m32r_issue_rate 148 149 #undef TARGET_OPTION_OVERRIDE 150 #define TARGET_OPTION_OVERRIDE m32r_option_override 151 152 #undef TARGET_ENCODE_SECTION_INFO 153 #define TARGET_ENCODE_SECTION_INFO m32r_encode_section_info 154 #undef TARGET_IN_SMALL_DATA_P 155 #define TARGET_IN_SMALL_DATA_P m32r_in_small_data_p 156 157 158 #undef TARGET_MEMORY_MOVE_COST 159 #define TARGET_MEMORY_MOVE_COST m32r_memory_move_cost 160 #undef TARGET_RTX_COSTS 161 #define TARGET_RTX_COSTS m32r_rtx_costs 162 #undef TARGET_ADDRESS_COST 163 #define TARGET_ADDRESS_COST hook_int_rtx_mode_as_bool_0 164 165 #undef TARGET_PROMOTE_PROTOTYPES 166 #define TARGET_PROMOTE_PROTOTYPES hook_bool_const_tree_true 167 #undef TARGET_RETURN_IN_MEMORY 168 #define TARGET_RETURN_IN_MEMORY m32r_return_in_memory 169 170 #undef TARGET_FUNCTION_VALUE 171 #define TARGET_FUNCTION_VALUE m32r_function_value 172 #undef TARGET_LIBCALL_VALUE 173 #define TARGET_LIBCALL_VALUE m32r_libcall_value 174 #undef TARGET_FUNCTION_VALUE_REGNO_P 175 #define TARGET_FUNCTION_VALUE_REGNO_P m32r_function_value_regno_p 176 177 #undef TARGET_SETUP_INCOMING_VARARGS 178 #define TARGET_SETUP_INCOMING_VARARGS m32r_setup_incoming_varargs 179 #undef TARGET_MUST_PASS_IN_STACK 180 #define TARGET_MUST_PASS_IN_STACK must_pass_in_stack_var_size 181 #undef TARGET_PASS_BY_REFERENCE 182 #define TARGET_PASS_BY_REFERENCE m32r_pass_by_reference 183 #undef TARGET_ARG_PARTIAL_BYTES 184 #define TARGET_ARG_PARTIAL_BYTES m32r_arg_partial_bytes 185 #undef TARGET_FUNCTION_ARG 186 #define TARGET_FUNCTION_ARG m32r_function_arg 187 #undef TARGET_FUNCTION_ARG_ADVANCE 188 #define TARGET_FUNCTION_ARG_ADVANCE m32r_function_arg_advance 189 190 #undef TARGET_CAN_ELIMINATE 191 #define TARGET_CAN_ELIMINATE m32r_can_eliminate 192 193 #undef TARGET_CONDITIONAL_REGISTER_USAGE 194 #define TARGET_CONDITIONAL_REGISTER_USAGE m32r_conditional_register_usage 195 196 #undef TARGET_TRAMPOLINE_INIT 197 #define TARGET_TRAMPOLINE_INIT m32r_trampoline_init 198 199 #undef TARGET_LEGITIMATE_CONSTANT_P 200 #define TARGET_LEGITIMATE_CONSTANT_P m32r_legitimate_constant_p 201 202 struct gcc_target targetm = TARGET_INITIALIZER; 203 204 /* Called by m32r_option_override to initialize various things. */ 205 206 void 207 m32r_init (void) 208 { 209 init_reg_tables (); 210 211 /* Initialize array for TARGET_PRINT_OPERAND_PUNCT_VALID_P. */ 212 memset (m32r_punct_chars, 0, sizeof (m32r_punct_chars)); 213 m32r_punct_chars['#'] = 1; 214 m32r_punct_chars['@'] = 1; /* ??? no longer used */ 215 216 /* Provide default value if not specified. */ 217 if (!global_options_set.x_g_switch_value) 218 g_switch_value = SDATA_DEFAULT_SIZE; 219 } 220 221 static void 222 m32r_option_override (void) 223 { 224 /* These need to be done at start up. 225 It's convenient to do them here. */ 226 m32r_init (); 227 SUBTARGET_OVERRIDE_OPTIONS; 228 } 229 230 /* Vectors to keep interesting information about registers where it can easily 231 be got. We use to use the actual mode value as the bit number, but there 232 is (or may be) more than 32 modes now. Instead we use two tables: one 233 indexed by hard register number, and one indexed by mode. */ 234 235 /* The purpose of m32r_mode_class is to shrink the range of modes so that 236 they all fit (as bit numbers) in a 32-bit word (again). Each real mode is 237 mapped into one m32r_mode_class mode. */ 238 239 enum m32r_mode_class 240 { 241 C_MODE, 242 S_MODE, D_MODE, T_MODE, O_MODE, 243 SF_MODE, DF_MODE, TF_MODE, OF_MODE, A_MODE 244 }; 245 246 /* Modes for condition codes. */ 247 #define C_MODES (1 << (int) C_MODE) 248 249 /* Modes for single-word and smaller quantities. */ 250 #define S_MODES ((1 << (int) S_MODE) | (1 << (int) SF_MODE)) 251 252 /* Modes for double-word and smaller quantities. */ 253 #define D_MODES (S_MODES | (1 << (int) D_MODE) | (1 << DF_MODE)) 254 255 /* Modes for quad-word and smaller quantities. */ 256 #define T_MODES (D_MODES | (1 << (int) T_MODE) | (1 << (int) TF_MODE)) 257 258 /* Modes for accumulators. */ 259 #define A_MODES (1 << (int) A_MODE) 260 261 /* Value is 1 if register/mode pair is acceptable on arc. */ 262 263 const unsigned int m32r_hard_regno_mode_ok[FIRST_PSEUDO_REGISTER] = 264 { 265 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, 266 T_MODES, T_MODES, T_MODES, T_MODES, T_MODES, S_MODES, S_MODES, S_MODES, 267 S_MODES, C_MODES, A_MODES, A_MODES 268 }; 269 270 unsigned int m32r_mode_class [NUM_MACHINE_MODES]; 271 272 enum reg_class m32r_regno_reg_class[FIRST_PSEUDO_REGISTER]; 273 274 static void 275 init_reg_tables (void) 276 { 277 int i; 278 279 for (i = 0; i < NUM_MACHINE_MODES; i++) 280 { 281 switch (GET_MODE_CLASS (i)) 282 { 283 case MODE_INT: 284 case MODE_PARTIAL_INT: 285 case MODE_COMPLEX_INT: 286 if (GET_MODE_SIZE (i) <= 4) 287 m32r_mode_class[i] = 1 << (int) S_MODE; 288 else if (GET_MODE_SIZE (i) == 8) 289 m32r_mode_class[i] = 1 << (int) D_MODE; 290 else if (GET_MODE_SIZE (i) == 16) 291 m32r_mode_class[i] = 1 << (int) T_MODE; 292 else if (GET_MODE_SIZE (i) == 32) 293 m32r_mode_class[i] = 1 << (int) O_MODE; 294 else 295 m32r_mode_class[i] = 0; 296 break; 297 case MODE_FLOAT: 298 case MODE_COMPLEX_FLOAT: 299 if (GET_MODE_SIZE (i) <= 4) 300 m32r_mode_class[i] = 1 << (int) SF_MODE; 301 else if (GET_MODE_SIZE (i) == 8) 302 m32r_mode_class[i] = 1 << (int) DF_MODE; 303 else if (GET_MODE_SIZE (i) == 16) 304 m32r_mode_class[i] = 1 << (int) TF_MODE; 305 else if (GET_MODE_SIZE (i) == 32) 306 m32r_mode_class[i] = 1 << (int) OF_MODE; 307 else 308 m32r_mode_class[i] = 0; 309 break; 310 case MODE_CC: 311 m32r_mode_class[i] = 1 << (int) C_MODE; 312 break; 313 default: 314 m32r_mode_class[i] = 0; 315 break; 316 } 317 } 318 319 for (i = 0; i < FIRST_PSEUDO_REGISTER; i++) 320 { 321 if (GPR_P (i)) 322 m32r_regno_reg_class[i] = GENERAL_REGS; 323 else if (i == ARG_POINTER_REGNUM) 324 m32r_regno_reg_class[i] = GENERAL_REGS; 325 else 326 m32r_regno_reg_class[i] = NO_REGS; 327 } 328 } 329 330 /* M32R specific attribute support. 331 332 interrupt - for interrupt functions 333 334 model - select code model used to access object 335 336 small: addresses use 24 bits, use bl to make calls 337 medium: addresses use 32 bits, use bl to make calls 338 large: addresses use 32 bits, use seth/add3/jl to make calls 339 340 Grep for MODEL in m32r.h for more info. */ 341 342 static tree small_ident1; 343 static tree small_ident2; 344 static tree medium_ident1; 345 static tree medium_ident2; 346 static tree large_ident1; 347 static tree large_ident2; 348 349 static void 350 init_idents (void) 351 { 352 if (small_ident1 == 0) 353 { 354 small_ident1 = get_identifier ("small"); 355 small_ident2 = get_identifier ("__small__"); 356 medium_ident1 = get_identifier ("medium"); 357 medium_ident2 = get_identifier ("__medium__"); 358 large_ident1 = get_identifier ("large"); 359 large_ident2 = get_identifier ("__large__"); 360 } 361 } 362 363 /* Handle an "model" attribute; arguments as in 364 struct attribute_spec.handler. */ 365 static tree 366 m32r_handle_model_attribute (tree *node ATTRIBUTE_UNUSED, tree name, 367 tree args, int flags ATTRIBUTE_UNUSED, 368 bool *no_add_attrs) 369 { 370 tree arg; 371 372 init_idents (); 373 arg = TREE_VALUE (args); 374 375 if (arg != small_ident1 376 && arg != small_ident2 377 && arg != medium_ident1 378 && arg != medium_ident2 379 && arg != large_ident1 380 && arg != large_ident2) 381 { 382 warning (OPT_Wattributes, "invalid argument of %qs attribute", 383 IDENTIFIER_POINTER (name)); 384 *no_add_attrs = true; 385 } 386 387 return NULL_TREE; 388 } 389 390 /* Encode section information of DECL, which is either a VAR_DECL, 391 FUNCTION_DECL, STRING_CST, CONSTRUCTOR, or ???. 392 393 For the M32R we want to record: 394 395 - whether the object lives in .sdata/.sbss. 396 - what code model should be used to access the object 397 */ 398 399 static void 400 m32r_encode_section_info (tree decl, rtx rtl, int first) 401 { 402 int extra_flags = 0; 403 tree model_attr; 404 enum m32r_model model; 405 406 default_encode_section_info (decl, rtl, first); 407 408 if (!DECL_P (decl)) 409 return; 410 411 model_attr = lookup_attribute ("model", DECL_ATTRIBUTES (decl)); 412 if (model_attr) 413 { 414 tree id; 415 416 init_idents (); 417 418 id = TREE_VALUE (TREE_VALUE (model_attr)); 419 420 if (id == small_ident1 || id == small_ident2) 421 model = M32R_MODEL_SMALL; 422 else if (id == medium_ident1 || id == medium_ident2) 423 model = M32R_MODEL_MEDIUM; 424 else if (id == large_ident1 || id == large_ident2) 425 model = M32R_MODEL_LARGE; 426 else 427 gcc_unreachable (); /* shouldn't happen */ 428 } 429 else 430 { 431 if (TARGET_MODEL_SMALL) 432 model = M32R_MODEL_SMALL; 433 else if (TARGET_MODEL_MEDIUM) 434 model = M32R_MODEL_MEDIUM; 435 else if (TARGET_MODEL_LARGE) 436 model = M32R_MODEL_LARGE; 437 else 438 gcc_unreachable (); /* shouldn't happen */ 439 } 440 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT; 441 442 if (extra_flags) 443 SYMBOL_REF_FLAGS (XEXP (rtl, 0)) |= extra_flags; 444 } 445 446 /* Only mark the object as being small data area addressable if 447 it hasn't been explicitly marked with a code model. 448 449 The user can explicitly put an object in the small data area with the 450 section attribute. If the object is in sdata/sbss and marked with a 451 code model do both [put the object in .sdata and mark it as being 452 addressed with a specific code model - don't mark it as being addressed 453 with an SDA reloc though]. This is ok and might be useful at times. If 454 the object doesn't fit the linker will give an error. */ 455 456 static bool 457 m32r_in_small_data_p (const_tree decl) 458 { 459 const_tree section; 460 461 if (TREE_CODE (decl) != VAR_DECL) 462 return false; 463 464 if (lookup_attribute ("model", DECL_ATTRIBUTES (decl))) 465 return false; 466 467 section = DECL_SECTION_NAME (decl); 468 if (section) 469 { 470 const char *const name = TREE_STRING_POINTER (section); 471 if (strcmp (name, ".sdata") == 0 || strcmp (name, ".sbss") == 0) 472 return true; 473 } 474 else 475 { 476 if (! TREE_READONLY (decl) && ! TARGET_SDATA_NONE) 477 { 478 int size = int_size_in_bytes (TREE_TYPE (decl)); 479 480 if (size > 0 && size <= g_switch_value) 481 return true; 482 } 483 } 484 485 return false; 486 } 487 488 /* Do anything needed before RTL is emitted for each function. */ 489 490 void 491 m32r_init_expanders (void) 492 { 493 /* ??? At one point there was code here. The function is left in 494 to make it easy to experiment. */ 495 } 496 497 int 498 call_operand (rtx op, enum machine_mode mode) 499 { 500 if (!MEM_P (op)) 501 return 0; 502 op = XEXP (op, 0); 503 return call_address_operand (op, mode); 504 } 505 506 /* Return 1 if OP is a reference to an object in .sdata/.sbss. */ 507 508 int 509 small_data_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 510 { 511 if (! TARGET_SDATA_USE) 512 return 0; 513 514 if (GET_CODE (op) == SYMBOL_REF) 515 return SYMBOL_REF_SMALL_P (op); 516 517 if (GET_CODE (op) == CONST 518 && GET_CODE (XEXP (op, 0)) == PLUS 519 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF 520 && satisfies_constraint_J (XEXP (XEXP (op, 0), 1))) 521 return SYMBOL_REF_SMALL_P (XEXP (XEXP (op, 0), 0)); 522 523 return 0; 524 } 525 526 /* Return 1 if OP is a symbol that can use 24-bit addressing. */ 527 528 int 529 addr24_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 530 { 531 rtx sym; 532 533 if (flag_pic) 534 return 0; 535 536 if (GET_CODE (op) == LABEL_REF) 537 return TARGET_ADDR24; 538 539 if (GET_CODE (op) == SYMBOL_REF) 540 sym = op; 541 else if (GET_CODE (op) == CONST 542 && GET_CODE (XEXP (op, 0)) == PLUS 543 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF 544 && satisfies_constraint_M (XEXP (XEXP (op, 0), 1))) 545 sym = XEXP (XEXP (op, 0), 0); 546 else 547 return 0; 548 549 if (SYMBOL_REF_MODEL (sym) == M32R_MODEL_SMALL) 550 return 1; 551 552 if (TARGET_ADDR24 553 && (CONSTANT_POOL_ADDRESS_P (sym) 554 || LIT_NAME_P (XSTR (sym, 0)))) 555 return 1; 556 557 return 0; 558 } 559 560 /* Return 1 if OP is a symbol that needs 32-bit addressing. */ 561 562 int 563 addr32_operand (rtx op, enum machine_mode mode) 564 { 565 rtx sym; 566 567 if (GET_CODE (op) == LABEL_REF) 568 return TARGET_ADDR32; 569 570 if (GET_CODE (op) == SYMBOL_REF) 571 sym = op; 572 else if (GET_CODE (op) == CONST 573 && GET_CODE (XEXP (op, 0)) == PLUS 574 && GET_CODE (XEXP (XEXP (op, 0), 0)) == SYMBOL_REF 575 && CONST_INT_P (XEXP (XEXP (op, 0), 1)) 576 && ! flag_pic) 577 sym = XEXP (XEXP (op, 0), 0); 578 else 579 return 0; 580 581 return (! addr24_operand (sym, mode) 582 && ! small_data_operand (sym, mode)); 583 } 584 585 /* Return 1 if OP is a function that can be called with the `bl' insn. */ 586 587 int 588 call26_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 589 { 590 if (flag_pic) 591 return 1; 592 593 if (GET_CODE (op) == SYMBOL_REF) 594 return SYMBOL_REF_MODEL (op) != M32R_MODEL_LARGE; 595 596 return TARGET_CALL26; 597 } 598 599 /* Return 1 if OP is a DImode const we want to handle inline. 600 This must match the code in the movdi pattern. 601 It is used by the 'G' CONST_DOUBLE_OK_FOR_LETTER. */ 602 603 int 604 easy_di_const (rtx op) 605 { 606 rtx high_rtx, low_rtx; 607 HOST_WIDE_INT high, low; 608 609 split_double (op, &high_rtx, &low_rtx); 610 high = INTVAL (high_rtx); 611 low = INTVAL (low_rtx); 612 /* Pick constants loadable with 2 16-bit `ldi' insns. */ 613 if (high >= -128 && high <= 127 614 && low >= -128 && low <= 127) 615 return 1; 616 return 0; 617 } 618 619 /* Return 1 if OP is a DFmode const we want to handle inline. 620 This must match the code in the movdf pattern. 621 It is used by the 'H' CONST_DOUBLE_OK_FOR_LETTER. */ 622 623 int 624 easy_df_const (rtx op) 625 { 626 REAL_VALUE_TYPE r; 627 long l[2]; 628 629 REAL_VALUE_FROM_CONST_DOUBLE (r, op); 630 REAL_VALUE_TO_TARGET_DOUBLE (r, l); 631 if (l[0] == 0 && l[1] == 0) 632 return 1; 633 if ((l[0] & 0xffff) == 0 && l[1] == 0) 634 return 1; 635 return 0; 636 } 637 638 /* Return 1 if OP is (mem (reg ...)). 639 This is used in insn length calcs. */ 640 641 int 642 memreg_operand (rtx op, enum machine_mode mode ATTRIBUTE_UNUSED) 643 { 644 return MEM_P (op) && REG_P (XEXP (op, 0)); 645 } 646 647 /* Return nonzero if TYPE must be passed by indirect reference. */ 648 649 static bool 650 m32r_pass_by_reference (cumulative_args_t ca ATTRIBUTE_UNUSED, 651 enum machine_mode mode, const_tree type, 652 bool named ATTRIBUTE_UNUSED) 653 { 654 int size; 655 656 if (type) 657 size = int_size_in_bytes (type); 658 else 659 size = GET_MODE_SIZE (mode); 660 661 return (size < 0 || size > 8); 662 } 663 664 /* Comparisons. */ 665 666 /* X and Y are two things to compare using CODE. Emit the compare insn and 667 return the rtx for compare [arg0 of the if_then_else]. 668 If need_compare is true then the comparison insn must be generated, rather 669 than being subsumed into the following branch instruction. */ 670 671 rtx 672 gen_compare (enum rtx_code code, rtx x, rtx y, int need_compare) 673 { 674 enum rtx_code compare_code; 675 enum rtx_code branch_code; 676 rtx cc_reg = gen_rtx_REG (CCmode, CARRY_REGNUM); 677 int must_swap = 0; 678 679 switch (code) 680 { 681 case EQ: compare_code = EQ; branch_code = NE; break; 682 case NE: compare_code = EQ; branch_code = EQ; break; 683 case LT: compare_code = LT; branch_code = NE; break; 684 case LE: compare_code = LT; branch_code = EQ; must_swap = 1; break; 685 case GT: compare_code = LT; branch_code = NE; must_swap = 1; break; 686 case GE: compare_code = LT; branch_code = EQ; break; 687 case LTU: compare_code = LTU; branch_code = NE; break; 688 case LEU: compare_code = LTU; branch_code = EQ; must_swap = 1; break; 689 case GTU: compare_code = LTU; branch_code = NE; must_swap = 1; break; 690 case GEU: compare_code = LTU; branch_code = EQ; break; 691 692 default: 693 gcc_unreachable (); 694 } 695 696 if (need_compare) 697 { 698 switch (compare_code) 699 { 700 case EQ: 701 if (satisfies_constraint_P (y) /* Reg equal to small const. */ 702 && y != const0_rtx) 703 { 704 rtx tmp = gen_reg_rtx (SImode); 705 706 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y)))); 707 x = tmp; 708 y = const0_rtx; 709 } 710 else if (CONSTANT_P (y)) /* Reg equal to const. */ 711 { 712 rtx tmp = force_reg (GET_MODE (x), y); 713 y = tmp; 714 } 715 716 if (register_operand (y, SImode) /* Reg equal to reg. */ 717 || y == const0_rtx) /* Reg equal to zero. */ 718 { 719 emit_insn (gen_cmp_eqsi_insn (x, y)); 720 721 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx); 722 } 723 break; 724 725 case LT: 726 if (register_operand (y, SImode) 727 || satisfies_constraint_P (y)) 728 { 729 rtx tmp = gen_reg_rtx (SImode); /* Reg compared to reg. */ 730 731 switch (code) 732 { 733 case LT: 734 emit_insn (gen_cmp_ltsi_insn (x, y)); 735 code = EQ; 736 break; 737 case LE: 738 if (y == const0_rtx) 739 tmp = const1_rtx; 740 else 741 emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); 742 emit_insn (gen_cmp_ltsi_insn (x, tmp)); 743 code = EQ; 744 break; 745 case GT: 746 if (CONST_INT_P (y)) 747 tmp = gen_rtx_PLUS (SImode, y, const1_rtx); 748 else 749 emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); 750 emit_insn (gen_cmp_ltsi_insn (x, tmp)); 751 code = NE; 752 break; 753 case GE: 754 emit_insn (gen_cmp_ltsi_insn (x, y)); 755 code = NE; 756 break; 757 default: 758 gcc_unreachable (); 759 } 760 761 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx); 762 } 763 break; 764 765 case LTU: 766 if (register_operand (y, SImode) 767 || satisfies_constraint_P (y)) 768 { 769 rtx tmp = gen_reg_rtx (SImode); /* Reg (unsigned) compared to reg. */ 770 771 switch (code) 772 { 773 case LTU: 774 emit_insn (gen_cmp_ltusi_insn (x, y)); 775 code = EQ; 776 break; 777 case LEU: 778 if (y == const0_rtx) 779 tmp = const1_rtx; 780 else 781 emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); 782 emit_insn (gen_cmp_ltusi_insn (x, tmp)); 783 code = EQ; 784 break; 785 case GTU: 786 if (CONST_INT_P (y)) 787 tmp = gen_rtx_PLUS (SImode, y, const1_rtx); 788 else 789 emit_insn (gen_addsi3 (tmp, y, constm1_rtx)); 790 emit_insn (gen_cmp_ltusi_insn (x, tmp)); 791 code = NE; 792 break; 793 case GEU: 794 emit_insn (gen_cmp_ltusi_insn (x, y)); 795 code = NE; 796 break; 797 default: 798 gcc_unreachable (); 799 } 800 801 return gen_rtx_fmt_ee (code, CCmode, cc_reg, const0_rtx); 802 } 803 break; 804 805 default: 806 gcc_unreachable (); 807 } 808 } 809 else 810 { 811 /* Reg/reg equal comparison. */ 812 if (compare_code == EQ 813 && register_operand (y, SImode)) 814 return gen_rtx_fmt_ee (code, CCmode, x, y); 815 816 /* Reg/zero signed comparison. */ 817 if ((compare_code == EQ || compare_code == LT) 818 && y == const0_rtx) 819 return gen_rtx_fmt_ee (code, CCmode, x, y); 820 821 /* Reg/smallconst equal comparison. */ 822 if (compare_code == EQ 823 && satisfies_constraint_P (y)) 824 { 825 rtx tmp = gen_reg_rtx (SImode); 826 827 emit_insn (gen_addsi3 (tmp, x, GEN_INT (-INTVAL (y)))); 828 return gen_rtx_fmt_ee (code, CCmode, tmp, const0_rtx); 829 } 830 831 /* Reg/const equal comparison. */ 832 if (compare_code == EQ 833 && CONSTANT_P (y)) 834 { 835 rtx tmp = force_reg (GET_MODE (x), y); 836 837 return gen_rtx_fmt_ee (code, CCmode, x, tmp); 838 } 839 } 840 841 if (CONSTANT_P (y)) 842 { 843 if (must_swap) 844 y = force_reg (GET_MODE (x), y); 845 else 846 { 847 int ok_const = reg_or_int16_operand (y, GET_MODE (y)); 848 849 if (! ok_const) 850 y = force_reg (GET_MODE (x), y); 851 } 852 } 853 854 switch (compare_code) 855 { 856 case EQ : 857 emit_insn (gen_cmp_eqsi_insn (must_swap ? y : x, must_swap ? x : y)); 858 break; 859 case LT : 860 emit_insn (gen_cmp_ltsi_insn (must_swap ? y : x, must_swap ? x : y)); 861 break; 862 case LTU : 863 emit_insn (gen_cmp_ltusi_insn (must_swap ? y : x, must_swap ? x : y)); 864 break; 865 866 default: 867 gcc_unreachable (); 868 } 869 870 return gen_rtx_fmt_ee (branch_code, VOIDmode, cc_reg, CONST0_RTX (CCmode)); 871 } 872 873 bool 874 gen_cond_store (enum rtx_code code, rtx op0, rtx op1, rtx op2) 875 { 876 enum machine_mode mode = GET_MODE (op0); 877 878 gcc_assert (mode == SImode); 879 switch (code) 880 { 881 case EQ: 882 if (!register_operand (op1, mode)) 883 op1 = force_reg (mode, op1); 884 885 if (TARGET_M32RX || TARGET_M32R2) 886 { 887 if (!reg_or_zero_operand (op2, mode)) 888 op2 = force_reg (mode, op2); 889 890 emit_insn (gen_seq_insn_m32rx (op0, op1, op2)); 891 return true; 892 } 893 if (CONST_INT_P (op2) && INTVAL (op2) == 0) 894 { 895 emit_insn (gen_seq_zero_insn (op0, op1)); 896 return true; 897 } 898 899 if (!reg_or_eq_int16_operand (op2, mode)) 900 op2 = force_reg (mode, op2); 901 902 emit_insn (gen_seq_insn (op0, op1, op2)); 903 return true; 904 905 case NE: 906 if (!CONST_INT_P (op2) 907 || (INTVAL (op2) != 0 && satisfies_constraint_K (op2))) 908 { 909 rtx reg; 910 911 if (reload_completed || reload_in_progress) 912 return false; 913 914 reg = gen_reg_rtx (SImode); 915 emit_insn (gen_xorsi3 (reg, op1, op2)); 916 op1 = reg; 917 918 if (!register_operand (op1, mode)) 919 op1 = force_reg (mode, op1); 920 921 emit_insn (gen_sne_zero_insn (op0, op1)); 922 return true; 923 } 924 return false; 925 926 case LT: 927 case GT: 928 if (code == GT) 929 { 930 rtx tmp = op2; 931 op2 = op1; 932 op1 = tmp; 933 code = LT; 934 } 935 936 if (!register_operand (op1, mode)) 937 op1 = force_reg (mode, op1); 938 939 if (!reg_or_int16_operand (op2, mode)) 940 op2 = force_reg (mode, op2); 941 942 emit_insn (gen_slt_insn (op0, op1, op2)); 943 return true; 944 945 case LTU: 946 case GTU: 947 if (code == GTU) 948 { 949 rtx tmp = op2; 950 op2 = op1; 951 op1 = tmp; 952 code = LTU; 953 } 954 955 if (!register_operand (op1, mode)) 956 op1 = force_reg (mode, op1); 957 958 if (!reg_or_int16_operand (op2, mode)) 959 op2 = force_reg (mode, op2); 960 961 emit_insn (gen_sltu_insn (op0, op1, op2)); 962 return true; 963 964 case GE: 965 case GEU: 966 if (!register_operand (op1, mode)) 967 op1 = force_reg (mode, op1); 968 969 if (!reg_or_int16_operand (op2, mode)) 970 op2 = force_reg (mode, op2); 971 972 if (code == GE) 973 emit_insn (gen_sge_insn (op0, op1, op2)); 974 else 975 emit_insn (gen_sgeu_insn (op0, op1, op2)); 976 return true; 977 978 case LE: 979 case LEU: 980 if (!register_operand (op1, mode)) 981 op1 = force_reg (mode, op1); 982 983 if (CONST_INT_P (op2)) 984 { 985 HOST_WIDE_INT value = INTVAL (op2); 986 if (value >= 2147483647) 987 { 988 emit_move_insn (op0, const1_rtx); 989 return true; 990 } 991 992 op2 = GEN_INT (value + 1); 993 if (value < -32768 || value >= 32767) 994 op2 = force_reg (mode, op2); 995 996 if (code == LEU) 997 emit_insn (gen_sltu_insn (op0, op1, op2)); 998 else 999 emit_insn (gen_slt_insn (op0, op1, op2)); 1000 return true; 1001 } 1002 1003 if (!register_operand (op2, mode)) 1004 op2 = force_reg (mode, op2); 1005 1006 if (code == LEU) 1007 emit_insn (gen_sleu_insn (op0, op1, op2)); 1008 else 1009 emit_insn (gen_sle_insn (op0, op1, op2)); 1010 return true; 1011 1012 default: 1013 gcc_unreachable (); 1014 } 1015 } 1016 1017 1018 /* Split a 2 word move (DI or DF) into component parts. */ 1019 1020 rtx 1021 gen_split_move_double (rtx operands[]) 1022 { 1023 enum machine_mode mode = GET_MODE (operands[0]); 1024 rtx dest = operands[0]; 1025 rtx src = operands[1]; 1026 rtx val; 1027 1028 /* We might have (SUBREG (MEM)) here, so just get rid of the 1029 subregs to make this code simpler. It is safe to call 1030 alter_subreg any time after reload. */ 1031 if (GET_CODE (dest) == SUBREG) 1032 alter_subreg (&dest, true); 1033 if (GET_CODE (src) == SUBREG) 1034 alter_subreg (&src, true); 1035 1036 start_sequence (); 1037 if (REG_P (dest)) 1038 { 1039 int dregno = REGNO (dest); 1040 1041 /* Reg = reg. */ 1042 if (REG_P (src)) 1043 { 1044 int sregno = REGNO (src); 1045 1046 int reverse = (dregno == sregno + 1); 1047 1048 /* We normally copy the low-numbered register first. However, if 1049 the first register operand 0 is the same as the second register of 1050 operand 1, we must copy in the opposite order. */ 1051 emit_insn (gen_rtx_SET (VOIDmode, 1052 operand_subword (dest, reverse, TRUE, mode), 1053 operand_subword (src, reverse, TRUE, mode))); 1054 1055 emit_insn (gen_rtx_SET (VOIDmode, 1056 operand_subword (dest, !reverse, TRUE, mode), 1057 operand_subword (src, !reverse, TRUE, mode))); 1058 } 1059 1060 /* Reg = constant. */ 1061 else if (CONST_INT_P (src) || GET_CODE (src) == CONST_DOUBLE) 1062 { 1063 rtx words[2]; 1064 split_double (src, &words[0], &words[1]); 1065 emit_insn (gen_rtx_SET (VOIDmode, 1066 operand_subword (dest, 0, TRUE, mode), 1067 words[0])); 1068 1069 emit_insn (gen_rtx_SET (VOIDmode, 1070 operand_subword (dest, 1, TRUE, mode), 1071 words[1])); 1072 } 1073 1074 /* Reg = mem. */ 1075 else if (MEM_P (src)) 1076 { 1077 /* If the high-address word is used in the address, we must load it 1078 last. Otherwise, load it first. */ 1079 int reverse 1080 = (refers_to_regno_p (dregno, dregno + 1, XEXP (src, 0), 0) != 0); 1081 1082 /* We used to optimize loads from single registers as 1083 1084 ld r1,r3+; ld r2,r3 1085 1086 if r3 were not used subsequently. However, the REG_NOTES aren't 1087 propagated correctly by the reload phase, and it can cause bad 1088 code to be generated. We could still try: 1089 1090 ld r1,r3+; ld r2,r3; addi r3,-4 1091 1092 which saves 2 bytes and doesn't force longword alignment. */ 1093 emit_insn (gen_rtx_SET (VOIDmode, 1094 operand_subword (dest, reverse, TRUE, mode), 1095 adjust_address (src, SImode, 1096 reverse * UNITS_PER_WORD))); 1097 1098 emit_insn (gen_rtx_SET (VOIDmode, 1099 operand_subword (dest, !reverse, TRUE, mode), 1100 adjust_address (src, SImode, 1101 !reverse * UNITS_PER_WORD))); 1102 } 1103 else 1104 gcc_unreachable (); 1105 } 1106 1107 /* Mem = reg. */ 1108 /* We used to optimize loads from single registers as 1109 1110 st r1,r3; st r2,+r3 1111 1112 if r3 were not used subsequently. However, the REG_NOTES aren't 1113 propagated correctly by the reload phase, and it can cause bad 1114 code to be generated. We could still try: 1115 1116 st r1,r3; st r2,+r3; addi r3,-4 1117 1118 which saves 2 bytes and doesn't force longword alignment. */ 1119 else if (MEM_P (dest) && REG_P (src)) 1120 { 1121 emit_insn (gen_rtx_SET (VOIDmode, 1122 adjust_address (dest, SImode, 0), 1123 operand_subword (src, 0, TRUE, mode))); 1124 1125 emit_insn (gen_rtx_SET (VOIDmode, 1126 adjust_address (dest, SImode, UNITS_PER_WORD), 1127 operand_subword (src, 1, TRUE, mode))); 1128 } 1129 1130 else 1131 gcc_unreachable (); 1132 1133 val = get_insns (); 1134 end_sequence (); 1135 return val; 1136 } 1137 1138 1139 static int 1140 m32r_arg_partial_bytes (cumulative_args_t cum_v, enum machine_mode mode, 1141 tree type, bool named ATTRIBUTE_UNUSED) 1142 { 1143 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1144 1145 int words; 1146 unsigned int size = 1147 (((mode == BLKmode && type) 1148 ? (unsigned int) int_size_in_bytes (type) 1149 : GET_MODE_SIZE (mode)) + UNITS_PER_WORD - 1) 1150 / UNITS_PER_WORD; 1151 1152 if (*cum >= M32R_MAX_PARM_REGS) 1153 words = 0; 1154 else if (*cum + size > M32R_MAX_PARM_REGS) 1155 words = (*cum + size) - M32R_MAX_PARM_REGS; 1156 else 1157 words = 0; 1158 1159 return words * UNITS_PER_WORD; 1160 } 1161 1162 /* The ROUND_ADVANCE* macros are local to this file. */ 1163 /* Round SIZE up to a word boundary. */ 1164 #define ROUND_ADVANCE(SIZE) \ 1165 (((SIZE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 1166 1167 /* Round arg MODE/TYPE up to the next word boundary. */ 1168 #define ROUND_ADVANCE_ARG(MODE, TYPE) \ 1169 ((MODE) == BLKmode \ 1170 ? ROUND_ADVANCE ((unsigned int) int_size_in_bytes (TYPE)) \ 1171 : ROUND_ADVANCE ((unsigned int) GET_MODE_SIZE (MODE))) 1172 1173 /* Round CUM up to the necessary point for argument MODE/TYPE. */ 1174 #define ROUND_ADVANCE_CUM(CUM, MODE, TYPE) (CUM) 1175 1176 /* Return boolean indicating arg of type TYPE and mode MODE will be passed in 1177 a reg. This includes arguments that have to be passed by reference as the 1178 pointer to them is passed in a reg if one is available (and that is what 1179 we're given). 1180 This macro is only used in this file. */ 1181 #define PASS_IN_REG_P(CUM, MODE, TYPE) \ 1182 (ROUND_ADVANCE_CUM ((CUM), (MODE), (TYPE)) < M32R_MAX_PARM_REGS) 1183 1184 /* Determine where to put an argument to a function. 1185 Value is zero to push the argument on the stack, 1186 or a hard register in which to store the argument. 1187 1188 MODE is the argument's machine mode. 1189 TYPE is the data type of the argument (as a tree). 1190 This is null for libcalls where that information may 1191 not be available. 1192 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1193 the preceding args and about the function being called. 1194 NAMED is nonzero if this argument is a named parameter 1195 (otherwise it is an extra parameter matching an ellipsis). */ 1196 /* On the M32R the first M32R_MAX_PARM_REGS args are normally in registers 1197 and the rest are pushed. */ 1198 1199 static rtx 1200 m32r_function_arg (cumulative_args_t cum_v, enum machine_mode mode, 1201 const_tree type ATTRIBUTE_UNUSED, 1202 bool named ATTRIBUTE_UNUSED) 1203 { 1204 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1205 1206 return (PASS_IN_REG_P (*cum, mode, type) 1207 ? gen_rtx_REG (mode, ROUND_ADVANCE_CUM (*cum, mode, type)) 1208 : NULL_RTX); 1209 } 1210 1211 /* Update the data in CUM to advance over an argument 1212 of mode MODE and data type TYPE. 1213 (TYPE is null for libcalls where that information may not be available.) */ 1214 1215 static void 1216 m32r_function_arg_advance (cumulative_args_t cum_v, enum machine_mode mode, 1217 const_tree type, bool named ATTRIBUTE_UNUSED) 1218 { 1219 CUMULATIVE_ARGS *cum = get_cumulative_args (cum_v); 1220 1221 *cum = (ROUND_ADVANCE_CUM (*cum, mode, type) 1222 + ROUND_ADVANCE_ARG (mode, type)); 1223 } 1224 1225 /* Worker function for TARGET_RETURN_IN_MEMORY. */ 1226 1227 static bool 1228 m32r_return_in_memory (const_tree type, const_tree fntype ATTRIBUTE_UNUSED) 1229 { 1230 cumulative_args_t dummy = pack_cumulative_args (NULL); 1231 1232 return m32r_pass_by_reference (dummy, TYPE_MODE (type), type, false); 1233 } 1234 1235 /* Worker function for TARGET_FUNCTION_VALUE. */ 1236 1237 static rtx 1238 m32r_function_value (const_tree valtype, 1239 const_tree fn_decl_or_type ATTRIBUTE_UNUSED, 1240 bool outgoing ATTRIBUTE_UNUSED) 1241 { 1242 return gen_rtx_REG (TYPE_MODE (valtype), 0); 1243 } 1244 1245 /* Worker function for TARGET_LIBCALL_VALUE. */ 1246 1247 static rtx 1248 m32r_libcall_value (enum machine_mode mode, 1249 const_rtx fun ATTRIBUTE_UNUSED) 1250 { 1251 return gen_rtx_REG (mode, 0); 1252 } 1253 1254 /* Worker function for TARGET_FUNCTION_VALUE_REGNO_P. 1255 1256 ??? What about r1 in DI/DF values. */ 1257 1258 static bool 1259 m32r_function_value_regno_p (const unsigned int regno) 1260 { 1261 return (regno == 0); 1262 } 1263 1264 /* Do any needed setup for a variadic function. For the M32R, we must 1265 create a register parameter block, and then copy any anonymous arguments 1266 in registers to memory. 1267 1268 CUM has not been updated for the last named argument which has type TYPE 1269 and mode MODE, and we rely on this fact. */ 1270 1271 static void 1272 m32r_setup_incoming_varargs (cumulative_args_t cum, enum machine_mode mode, 1273 tree type, int *pretend_size, int no_rtl) 1274 { 1275 int first_anon_arg; 1276 1277 if (no_rtl) 1278 return; 1279 1280 /* All BLKmode values are passed by reference. */ 1281 gcc_assert (mode != BLKmode); 1282 1283 first_anon_arg = (ROUND_ADVANCE_CUM (*get_cumulative_args (cum), mode, type) 1284 + ROUND_ADVANCE_ARG (mode, type)); 1285 1286 if (first_anon_arg < M32R_MAX_PARM_REGS) 1287 { 1288 /* Note that first_reg_offset < M32R_MAX_PARM_REGS. */ 1289 int first_reg_offset = first_anon_arg; 1290 /* Size in words to "pretend" allocate. */ 1291 int size = M32R_MAX_PARM_REGS - first_reg_offset; 1292 rtx regblock; 1293 1294 regblock = gen_frame_mem (BLKmode, 1295 plus_constant (Pmode, arg_pointer_rtx, 1296 FIRST_PARM_OFFSET (0))); 1297 set_mem_alias_set (regblock, get_varargs_alias_set ()); 1298 move_block_from_reg (first_reg_offset, regblock, size); 1299 1300 *pretend_size = (size * UNITS_PER_WORD); 1301 } 1302 } 1303 1304 1305 /* Return true if INSN is real instruction bearing insn. */ 1306 1307 static int 1308 m32r_is_insn (rtx insn) 1309 { 1310 return (NONDEBUG_INSN_P (insn) 1311 && GET_CODE (PATTERN (insn)) != USE 1312 && GET_CODE (PATTERN (insn)) != CLOBBER 1313 && GET_CODE (PATTERN (insn)) != ADDR_VEC); 1314 } 1315 1316 /* Increase the priority of long instructions so that the 1317 short instructions are scheduled ahead of the long ones. */ 1318 1319 static int 1320 m32r_adjust_priority (rtx insn, int priority) 1321 { 1322 if (m32r_is_insn (insn) 1323 && get_attr_insn_size (insn) != INSN_SIZE_SHORT) 1324 priority <<= 3; 1325 1326 return priority; 1327 } 1328 1329 1330 /* Indicate how many instructions can be issued at the same time. 1331 This is sort of a lie. The m32r can issue only 1 long insn at 1332 once, but it can issue 2 short insns. The default therefore is 1333 set at 2, but this can be overridden by the command line option 1334 -missue-rate=1. */ 1335 1336 static int 1337 m32r_issue_rate (void) 1338 { 1339 return ((TARGET_LOW_ISSUE_RATE) ? 1 : 2); 1340 } 1341 1342 /* Cost functions. */ 1343 /* Memory is 3 times as expensive as registers. 1344 ??? Is that the right way to look at it? */ 1345 1346 static int 1347 m32r_memory_move_cost (enum machine_mode mode, 1348 reg_class_t rclass ATTRIBUTE_UNUSED, 1349 bool in ATTRIBUTE_UNUSED) 1350 { 1351 if (GET_MODE_SIZE (mode) <= UNITS_PER_WORD) 1352 return 6; 1353 else 1354 return 12; 1355 } 1356 1357 static bool 1358 m32r_rtx_costs (rtx x, int code, int outer_code ATTRIBUTE_UNUSED, 1359 int opno ATTRIBUTE_UNUSED, int *total, 1360 bool speed ATTRIBUTE_UNUSED) 1361 { 1362 switch (code) 1363 { 1364 /* Small integers are as cheap as registers. 4 byte values can be 1365 fetched as immediate constants - let's give that the cost of an 1366 extra insn. */ 1367 case CONST_INT: 1368 if (INT16_P (INTVAL (x))) 1369 { 1370 *total = 0; 1371 return true; 1372 } 1373 /* FALLTHRU */ 1374 1375 case CONST: 1376 case LABEL_REF: 1377 case SYMBOL_REF: 1378 *total = COSTS_N_INSNS (1); 1379 return true; 1380 1381 case CONST_DOUBLE: 1382 { 1383 rtx high, low; 1384 1385 split_double (x, &high, &low); 1386 *total = COSTS_N_INSNS (!INT16_P (INTVAL (high)) 1387 + !INT16_P (INTVAL (low))); 1388 return true; 1389 } 1390 1391 case MULT: 1392 *total = COSTS_N_INSNS (3); 1393 return true; 1394 1395 case DIV: 1396 case UDIV: 1397 case MOD: 1398 case UMOD: 1399 *total = COSTS_N_INSNS (10); 1400 return true; 1401 1402 default: 1403 return false; 1404 } 1405 } 1406 1407 /* Type of function DECL. 1408 1409 The result is cached. To reset the cache at the end of a function, 1410 call with DECL = NULL_TREE. */ 1411 1412 enum m32r_function_type 1413 m32r_compute_function_type (tree decl) 1414 { 1415 /* Cached value. */ 1416 static enum m32r_function_type fn_type = M32R_FUNCTION_UNKNOWN; 1417 /* Last function we were called for. */ 1418 static tree last_fn = NULL_TREE; 1419 1420 /* Resetting the cached value? */ 1421 if (decl == NULL_TREE) 1422 { 1423 fn_type = M32R_FUNCTION_UNKNOWN; 1424 last_fn = NULL_TREE; 1425 return fn_type; 1426 } 1427 1428 if (decl == last_fn && fn_type != M32R_FUNCTION_UNKNOWN) 1429 return fn_type; 1430 1431 /* Compute function type. */ 1432 fn_type = (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) != NULL_TREE 1433 ? M32R_FUNCTION_INTERRUPT 1434 : M32R_FUNCTION_NORMAL); 1435 1436 last_fn = decl; 1437 return fn_type; 1438 } 1439 /* Function prologue/epilogue handlers. */ 1440 1441 /* M32R stack frames look like: 1442 1443 Before call After call 1444 +-----------------------+ +-----------------------+ 1445 | | | | 1446 high | local variables, | | local variables, | 1447 mem | reg save area, etc. | | reg save area, etc. | 1448 | | | | 1449 +-----------------------+ +-----------------------+ 1450 | | | | 1451 | arguments on stack. | | arguments on stack. | 1452 | | | | 1453 SP+0->+-----------------------+ +-----------------------+ 1454 | reg parm save area, | 1455 | only created for | 1456 | variable argument | 1457 | functions | 1458 +-----------------------+ 1459 | previous frame ptr | 1460 +-----------------------+ 1461 | | 1462 | register save area | 1463 | | 1464 +-----------------------+ 1465 | return address | 1466 +-----------------------+ 1467 | | 1468 | local variables | 1469 | | 1470 +-----------------------+ 1471 | | 1472 | alloca allocations | 1473 | | 1474 +-----------------------+ 1475 | | 1476 low | arguments on stack | 1477 memory | | 1478 SP+0->+-----------------------+ 1479 1480 Notes: 1481 1) The "reg parm save area" does not exist for non variable argument fns. 1482 2) The "reg parm save area" can be eliminated completely if we saved regs 1483 containing anonymous args separately but that complicates things too 1484 much (so it's not done). 1485 3) The return address is saved after the register save area so as to have as 1486 many insns as possible between the restoration of `lr' and the `jmp lr'. */ 1487 1488 /* Structure to be filled in by m32r_compute_frame_size with register 1489 save masks, and offsets for the current function. */ 1490 struct m32r_frame_info 1491 { 1492 unsigned int total_size; /* # bytes that the entire frame takes up. */ 1493 unsigned int extra_size; /* # bytes of extra stuff. */ 1494 unsigned int pretend_size; /* # bytes we push and pretend caller did. */ 1495 unsigned int args_size; /* # bytes that outgoing arguments take up. */ 1496 unsigned int reg_size; /* # bytes needed to store regs. */ 1497 unsigned int var_size; /* # bytes that variables take up. */ 1498 unsigned int gmask; /* Mask of saved gp registers. */ 1499 unsigned int save_fp; /* Nonzero if fp must be saved. */ 1500 unsigned int save_lr; /* Nonzero if lr (return addr) must be saved. */ 1501 int initialized; /* Nonzero if frame size already calculated. */ 1502 }; 1503 1504 /* Current frame information calculated by m32r_compute_frame_size. */ 1505 static struct m32r_frame_info current_frame_info; 1506 1507 /* Zero structure to initialize current_frame_info. */ 1508 static struct m32r_frame_info zero_frame_info; 1509 1510 #define FRAME_POINTER_MASK (1 << (FRAME_POINTER_REGNUM)) 1511 #define RETURN_ADDR_MASK (1 << (RETURN_ADDR_REGNUM)) 1512 1513 /* Tell prologue and epilogue if register REGNO should be saved / restored. 1514 The return address and frame pointer are treated separately. 1515 Don't consider them here. */ 1516 #define MUST_SAVE_REGISTER(regno, interrupt_p) \ 1517 ((regno) != RETURN_ADDR_REGNUM && (regno) != FRAME_POINTER_REGNUM \ 1518 && (df_regs_ever_live_p (regno) && (!call_really_used_regs[regno] || interrupt_p))) 1519 1520 #define MUST_SAVE_FRAME_POINTER (df_regs_ever_live_p (FRAME_POINTER_REGNUM)) 1521 #define MUST_SAVE_RETURN_ADDR (df_regs_ever_live_p (RETURN_ADDR_REGNUM) || crtl->profile) 1522 1523 #define SHORT_INSN_SIZE 2 /* Size of small instructions. */ 1524 #define LONG_INSN_SIZE 4 /* Size of long instructions. */ 1525 1526 /* Return the bytes needed to compute the frame pointer from the current 1527 stack pointer. 1528 1529 SIZE is the size needed for local variables. */ 1530 1531 unsigned int 1532 m32r_compute_frame_size (int size) /* # of var. bytes allocated. */ 1533 { 1534 unsigned int regno; 1535 unsigned int total_size, var_size, args_size, pretend_size, extra_size; 1536 unsigned int reg_size; 1537 unsigned int gmask; 1538 enum m32r_function_type fn_type; 1539 int interrupt_p; 1540 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table 1541 | crtl->profile); 1542 1543 var_size = M32R_STACK_ALIGN (size); 1544 args_size = M32R_STACK_ALIGN (crtl->outgoing_args_size); 1545 pretend_size = crtl->args.pretend_args_size; 1546 extra_size = FIRST_PARM_OFFSET (0); 1547 total_size = extra_size + pretend_size + args_size + var_size; 1548 reg_size = 0; 1549 gmask = 0; 1550 1551 /* See if this is an interrupt handler. Call used registers must be saved 1552 for them too. */ 1553 fn_type = m32r_compute_function_type (current_function_decl); 1554 interrupt_p = M32R_INTERRUPT_P (fn_type); 1555 1556 /* Calculate space needed for registers. */ 1557 for (regno = 0; regno < M32R_MAX_INT_REGS; regno++) 1558 { 1559 if (MUST_SAVE_REGISTER (regno, interrupt_p) 1560 || (regno == PIC_OFFSET_TABLE_REGNUM && pic_reg_used)) 1561 { 1562 reg_size += UNITS_PER_WORD; 1563 gmask |= 1 << regno; 1564 } 1565 } 1566 1567 current_frame_info.save_fp = MUST_SAVE_FRAME_POINTER; 1568 current_frame_info.save_lr = MUST_SAVE_RETURN_ADDR || pic_reg_used; 1569 1570 reg_size += ((current_frame_info.save_fp + current_frame_info.save_lr) 1571 * UNITS_PER_WORD); 1572 total_size += reg_size; 1573 1574 /* ??? Not sure this is necessary, and I don't think the epilogue 1575 handler will do the right thing if this changes total_size. */ 1576 total_size = M32R_STACK_ALIGN (total_size); 1577 1578 /* frame_size = total_size - (pretend_size + reg_size); */ 1579 1580 /* Save computed information. */ 1581 current_frame_info.total_size = total_size; 1582 current_frame_info.extra_size = extra_size; 1583 current_frame_info.pretend_size = pretend_size; 1584 current_frame_info.var_size = var_size; 1585 current_frame_info.args_size = args_size; 1586 current_frame_info.reg_size = reg_size; 1587 current_frame_info.gmask = gmask; 1588 current_frame_info.initialized = reload_completed; 1589 1590 /* Ok, we're done. */ 1591 return total_size; 1592 } 1593 1594 /* Worker function for TARGET_CAN_ELIMINATE. */ 1595 1596 bool 1597 m32r_can_eliminate (const int from, const int to) 1598 { 1599 return (from == ARG_POINTER_REGNUM && to == STACK_POINTER_REGNUM 1600 ? ! frame_pointer_needed 1601 : true); 1602 } 1603 1604 1605 /* The table we use to reference PIC data. */ 1606 static rtx global_offset_table; 1607 1608 static void 1609 m32r_reload_lr (rtx sp, int size) 1610 { 1611 rtx lr = gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM); 1612 1613 if (size == 0) 1614 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, sp))); 1615 else if (size < 32768) 1616 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, 1617 gen_rtx_PLUS (Pmode, sp, 1618 GEN_INT (size))))); 1619 else 1620 { 1621 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); 1622 1623 emit_insn (gen_movsi (tmp, GEN_INT (size))); 1624 emit_insn (gen_addsi3 (tmp, tmp, sp)); 1625 emit_insn (gen_movsi (lr, gen_frame_mem (Pmode, tmp))); 1626 } 1627 1628 emit_use (lr); 1629 } 1630 1631 void 1632 m32r_load_pic_register (void) 1633 { 1634 global_offset_table = gen_rtx_SYMBOL_REF (Pmode, "_GLOBAL_OFFSET_TABLE_"); 1635 emit_insn (gen_get_pc (pic_offset_table_rtx, global_offset_table, 1636 GEN_INT (TARGET_MODEL_SMALL))); 1637 1638 /* Need to emit this whether or not we obey regdecls, 1639 since setjmp/longjmp can cause life info to screw up. */ 1640 emit_use (pic_offset_table_rtx); 1641 } 1642 1643 /* Expand the m32r prologue as a series of insns. */ 1644 1645 void 1646 m32r_expand_prologue (void) 1647 { 1648 int regno; 1649 int frame_size; 1650 unsigned int gmask; 1651 int pic_reg_used = flag_pic && (crtl->uses_pic_offset_table 1652 | crtl->profile); 1653 1654 if (! current_frame_info.initialized) 1655 m32r_compute_frame_size (get_frame_size ()); 1656 1657 gmask = current_frame_info.gmask; 1658 1659 /* These cases shouldn't happen. Catch them now. */ 1660 gcc_assert (current_frame_info.total_size || !gmask); 1661 1662 /* Allocate space for register arguments if this is a variadic function. */ 1663 if (current_frame_info.pretend_size != 0) 1664 { 1665 /* Use a HOST_WIDE_INT temporary, since negating an unsigned int gives 1666 the wrong result on a 64-bit host. */ 1667 HOST_WIDE_INT pretend_size = current_frame_info.pretend_size; 1668 emit_insn (gen_addsi3 (stack_pointer_rtx, 1669 stack_pointer_rtx, 1670 GEN_INT (-pretend_size))); 1671 } 1672 1673 /* Save any registers we need to and set up fp. */ 1674 if (current_frame_info.save_fp) 1675 emit_insn (gen_movsi_push (stack_pointer_rtx, frame_pointer_rtx)); 1676 1677 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK); 1678 1679 /* Save any needed call-saved regs (and call-used if this is an 1680 interrupt handler). */ 1681 for (regno = 0; regno <= M32R_MAX_INT_REGS; ++regno) 1682 { 1683 if ((gmask & (1 << regno)) != 0) 1684 emit_insn (gen_movsi_push (stack_pointer_rtx, 1685 gen_rtx_REG (Pmode, regno))); 1686 } 1687 1688 if (current_frame_info.save_lr) 1689 emit_insn (gen_movsi_push (stack_pointer_rtx, 1690 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM))); 1691 1692 /* Allocate the stack frame. */ 1693 frame_size = (current_frame_info.total_size 1694 - (current_frame_info.pretend_size 1695 + current_frame_info.reg_size)); 1696 1697 if (frame_size == 0) 1698 ; /* Nothing to do. */ 1699 else if (frame_size <= 32768) 1700 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 1701 GEN_INT (-frame_size))); 1702 else 1703 { 1704 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); 1705 1706 emit_insn (gen_movsi (tmp, GEN_INT (frame_size))); 1707 emit_insn (gen_subsi3 (stack_pointer_rtx, stack_pointer_rtx, tmp)); 1708 } 1709 1710 if (frame_pointer_needed) 1711 emit_insn (gen_movsi (frame_pointer_rtx, stack_pointer_rtx)); 1712 1713 if (crtl->profile) 1714 /* Push lr for mcount (form_pc, x). */ 1715 emit_insn (gen_movsi_push (stack_pointer_rtx, 1716 gen_rtx_REG (Pmode, RETURN_ADDR_REGNUM))); 1717 1718 if (pic_reg_used) 1719 { 1720 m32r_load_pic_register (); 1721 m32r_reload_lr (stack_pointer_rtx, 1722 (crtl->profile ? 0 : frame_size)); 1723 } 1724 1725 if (crtl->profile && !pic_reg_used) 1726 emit_insn (gen_blockage ()); 1727 } 1728 1729 1730 /* Set up the stack and frame pointer (if desired) for the function. 1731 Note, if this is changed, you need to mirror the changes in 1732 m32r_compute_frame_size which calculates the prolog size. */ 1733 1734 static void 1735 m32r_output_function_prologue (FILE * file, HOST_WIDE_INT size) 1736 { 1737 enum m32r_function_type fn_type = m32r_compute_function_type (current_function_decl); 1738 1739 /* If this is an interrupt handler, mark it as such. */ 1740 if (M32R_INTERRUPT_P (fn_type)) 1741 fprintf (file, "\t%s interrupt handler\n", ASM_COMMENT_START); 1742 1743 if (! current_frame_info.initialized) 1744 m32r_compute_frame_size (size); 1745 1746 /* This is only for the human reader. */ 1747 fprintf (file, 1748 "\t%s PROLOGUE, vars= %d, regs= %d, args= %d, extra= %d\n", 1749 ASM_COMMENT_START, 1750 current_frame_info.var_size, 1751 current_frame_info.reg_size / 4, 1752 current_frame_info.args_size, 1753 current_frame_info.extra_size); 1754 } 1755 1756 /* Output RTL to pop register REGNO from the stack. */ 1757 1758 static void 1759 pop (int regno) 1760 { 1761 rtx x; 1762 1763 x = emit_insn (gen_movsi_pop (gen_rtx_REG (Pmode, regno), 1764 stack_pointer_rtx)); 1765 add_reg_note (x, REG_INC, stack_pointer_rtx); 1766 } 1767 1768 /* Expand the m32r epilogue as a series of insns. */ 1769 1770 void 1771 m32r_expand_epilogue (void) 1772 { 1773 int regno; 1774 int noepilogue = FALSE; 1775 int total_size; 1776 1777 gcc_assert (current_frame_info.initialized); 1778 total_size = current_frame_info.total_size; 1779 1780 if (total_size == 0) 1781 { 1782 rtx insn = get_last_insn (); 1783 1784 /* If the last insn was a BARRIER, we don't have to write any code 1785 because a jump (aka return) was put there. */ 1786 if (insn && NOTE_P (insn)) 1787 insn = prev_nonnote_insn (insn); 1788 if (insn && BARRIER_P (insn)) 1789 noepilogue = TRUE; 1790 } 1791 1792 if (!noepilogue) 1793 { 1794 unsigned int var_size = current_frame_info.var_size; 1795 unsigned int args_size = current_frame_info.args_size; 1796 unsigned int gmask = current_frame_info.gmask; 1797 int can_trust_sp_p = !cfun->calls_alloca; 1798 1799 if (flag_exceptions) 1800 emit_insn (gen_blockage ()); 1801 1802 /* The first thing to do is point the sp at the bottom of the register 1803 save area. */ 1804 if (can_trust_sp_p) 1805 { 1806 unsigned int reg_offset = var_size + args_size; 1807 1808 if (reg_offset == 0) 1809 ; /* Nothing to do. */ 1810 else if (reg_offset < 32768) 1811 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 1812 GEN_INT (reg_offset))); 1813 else 1814 { 1815 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); 1816 1817 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset))); 1818 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 1819 tmp)); 1820 } 1821 } 1822 else if (frame_pointer_needed) 1823 { 1824 unsigned int reg_offset = var_size + args_size; 1825 1826 if (reg_offset == 0) 1827 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); 1828 else if (reg_offset < 32768) 1829 emit_insn (gen_addsi3 (stack_pointer_rtx, frame_pointer_rtx, 1830 GEN_INT (reg_offset))); 1831 else 1832 { 1833 rtx tmp = gen_rtx_REG (Pmode, PROLOGUE_TMP_REGNUM); 1834 1835 emit_insn (gen_movsi (tmp, GEN_INT (reg_offset))); 1836 emit_insn (gen_movsi (stack_pointer_rtx, frame_pointer_rtx)); 1837 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 1838 tmp)); 1839 } 1840 } 1841 else 1842 gcc_unreachable (); 1843 1844 if (current_frame_info.save_lr) 1845 pop (RETURN_ADDR_REGNUM); 1846 1847 /* Restore any saved registers, in reverse order of course. */ 1848 gmask &= ~(FRAME_POINTER_MASK | RETURN_ADDR_MASK); 1849 for (regno = M32R_MAX_INT_REGS - 1; regno >= 0; --regno) 1850 { 1851 if ((gmask & (1L << regno)) != 0) 1852 pop (regno); 1853 } 1854 1855 if (current_frame_info.save_fp) 1856 pop (FRAME_POINTER_REGNUM); 1857 1858 /* Remove varargs area if present. */ 1859 if (current_frame_info.pretend_size != 0) 1860 emit_insn (gen_addsi3 (stack_pointer_rtx, stack_pointer_rtx, 1861 GEN_INT (current_frame_info.pretend_size))); 1862 1863 emit_insn (gen_blockage ()); 1864 } 1865 } 1866 1867 /* Do any necessary cleanup after a function to restore stack, frame, 1868 and regs. */ 1869 1870 static void 1871 m32r_output_function_epilogue (FILE * file ATTRIBUTE_UNUSED, 1872 HOST_WIDE_INT size ATTRIBUTE_UNUSED) 1873 { 1874 /* Reset state info for each function. */ 1875 current_frame_info = zero_frame_info; 1876 m32r_compute_function_type (NULL_TREE); 1877 } 1878 1879 /* Return nonzero if this function is known to have a null or 1 instruction 1880 epilogue. */ 1881 1882 int 1883 direct_return (void) 1884 { 1885 if (!reload_completed) 1886 return FALSE; 1887 1888 if (M32R_INTERRUPT_P (m32r_compute_function_type (current_function_decl))) 1889 return FALSE; 1890 1891 if (! current_frame_info.initialized) 1892 m32r_compute_frame_size (get_frame_size ()); 1893 1894 return current_frame_info.total_size == 0; 1895 } 1896 1897 1898 /* PIC. */ 1899 1900 int 1901 m32r_legitimate_pic_operand_p (rtx x) 1902 { 1903 if (GET_CODE (x) == SYMBOL_REF || GET_CODE (x) == LABEL_REF) 1904 return 0; 1905 1906 if (GET_CODE (x) == CONST 1907 && GET_CODE (XEXP (x, 0)) == PLUS 1908 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 1909 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF) 1910 && (CONST_INT_P (XEXP (XEXP (x, 0), 1)))) 1911 return 0; 1912 1913 return 1; 1914 } 1915 1916 rtx 1917 m32r_legitimize_pic_address (rtx orig, rtx reg) 1918 { 1919 #ifdef DEBUG_PIC 1920 printf("m32r_legitimize_pic_address()\n"); 1921 #endif 1922 1923 if (GET_CODE (orig) == SYMBOL_REF || GET_CODE (orig) == LABEL_REF) 1924 { 1925 rtx pic_ref, address; 1926 int subregs = 0; 1927 1928 if (reg == 0) 1929 { 1930 gcc_assert (!reload_in_progress && !reload_completed); 1931 reg = gen_reg_rtx (Pmode); 1932 1933 subregs = 1; 1934 } 1935 1936 if (subregs) 1937 address = gen_reg_rtx (Pmode); 1938 else 1939 address = reg; 1940 1941 crtl->uses_pic_offset_table = 1; 1942 1943 if (GET_CODE (orig) == LABEL_REF 1944 || (GET_CODE (orig) == SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig))) 1945 { 1946 emit_insn (gen_gotoff_load_addr (reg, orig)); 1947 emit_insn (gen_addsi3 (reg, reg, pic_offset_table_rtx)); 1948 return reg; 1949 } 1950 1951 emit_insn (gen_pic_load_addr (address, orig)); 1952 1953 emit_insn (gen_addsi3 (address, address, pic_offset_table_rtx)); 1954 pic_ref = gen_const_mem (Pmode, address); 1955 emit_move_insn (reg, pic_ref); 1956 return reg; 1957 } 1958 else if (GET_CODE (orig) == CONST) 1959 { 1960 rtx base, offset; 1961 1962 if (GET_CODE (XEXP (orig, 0)) == PLUS 1963 && XEXP (XEXP (orig, 0), 1) == pic_offset_table_rtx) 1964 return orig; 1965 1966 if (reg == 0) 1967 { 1968 gcc_assert (!reload_in_progress && !reload_completed); 1969 reg = gen_reg_rtx (Pmode); 1970 } 1971 1972 if (GET_CODE (XEXP (orig, 0)) == PLUS) 1973 { 1974 base = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 0), reg); 1975 if (base == reg) 1976 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), NULL_RTX); 1977 else 1978 offset = m32r_legitimize_pic_address (XEXP (XEXP (orig, 0), 1), reg); 1979 } 1980 else 1981 return orig; 1982 1983 if (CONST_INT_P (offset)) 1984 { 1985 if (INT16_P (INTVAL (offset))) 1986 return plus_constant (Pmode, base, INTVAL (offset)); 1987 else 1988 { 1989 gcc_assert (! reload_in_progress && ! reload_completed); 1990 offset = force_reg (Pmode, offset); 1991 } 1992 } 1993 1994 return gen_rtx_PLUS (Pmode, base, offset); 1995 } 1996 1997 return orig; 1998 } 1999 2000 static rtx 2001 m32r_legitimize_address (rtx x, rtx orig_x ATTRIBUTE_UNUSED, 2002 enum machine_mode mode ATTRIBUTE_UNUSED) 2003 { 2004 if (flag_pic) 2005 return m32r_legitimize_pic_address (x, NULL_RTX); 2006 else 2007 return x; 2008 } 2009 2010 /* Worker function for TARGET_MODE_DEPENDENT_ADDRESS_P. */ 2011 2012 static bool 2013 m32r_mode_dependent_address_p (const_rtx addr, addr_space_t as ATTRIBUTE_UNUSED) 2014 { 2015 if (GET_CODE (addr) == LO_SUM) 2016 return true; 2017 2018 return false; 2019 } 2020 2021 /* Nested function support. */ 2022 2023 /* Emit RTL insns to initialize the variable parts of a trampoline. 2024 FNADDR is an RTX for the address of the function's pure code. 2025 CXT is an RTX for the static chain value for the function. */ 2026 2027 void 2028 m32r_initialize_trampoline (rtx tramp ATTRIBUTE_UNUSED, 2029 rtx fnaddr ATTRIBUTE_UNUSED, 2030 rtx cxt ATTRIBUTE_UNUSED) 2031 { 2032 } 2033 2034 static void 2035 m32r_file_start (void) 2036 { 2037 default_file_start (); 2038 2039 if (flag_verbose_asm) 2040 fprintf (asm_out_file, 2041 "%s M32R/D special options: -G %d\n", 2042 ASM_COMMENT_START, g_switch_value); 2043 2044 if (TARGET_LITTLE_ENDIAN) 2045 fprintf (asm_out_file, "\t.little\n"); 2046 } 2047 2048 /* Print operand X (an rtx) in assembler syntax to file FILE. 2049 CODE is a letter or dot (`z' in `%z0') or 0 if no letter was specified. 2050 For `%' followed by punctuation, CODE is the punctuation and X is null. */ 2051 2052 static void 2053 m32r_print_operand (FILE * file, rtx x, int code) 2054 { 2055 rtx addr; 2056 2057 switch (code) 2058 { 2059 /* The 's' and 'p' codes are used by output_block_move() to 2060 indicate post-increment 's'tores and 'p're-increment loads. */ 2061 case 's': 2062 if (REG_P (x)) 2063 fprintf (file, "@+%s", reg_names [REGNO (x)]); 2064 else 2065 output_operand_lossage ("invalid operand to %%s code"); 2066 return; 2067 2068 case 'p': 2069 if (REG_P (x)) 2070 fprintf (file, "@%s+", reg_names [REGNO (x)]); 2071 else 2072 output_operand_lossage ("invalid operand to %%p code"); 2073 return; 2074 2075 case 'R' : 2076 /* Write second word of DImode or DFmode reference, 2077 register or memory. */ 2078 if (REG_P (x)) 2079 fputs (reg_names[REGNO (x)+1], file); 2080 else if (MEM_P (x)) 2081 { 2082 fprintf (file, "@("); 2083 /* Handle possible auto-increment. Since it is pre-increment and 2084 we have already done it, we can just use an offset of four. */ 2085 /* ??? This is taken from rs6000.c I think. I don't think it is 2086 currently necessary, but keep it around. */ 2087 if (GET_CODE (XEXP (x, 0)) == PRE_INC 2088 || GET_CODE (XEXP (x, 0)) == PRE_DEC) 2089 output_address (plus_constant (Pmode, XEXP (XEXP (x, 0), 0), 4)); 2090 else 2091 output_address (plus_constant (Pmode, XEXP (x, 0), 4)); 2092 fputc (')', file); 2093 } 2094 else 2095 output_operand_lossage ("invalid operand to %%R code"); 2096 return; 2097 2098 case 'H' : /* High word. */ 2099 case 'L' : /* Low word. */ 2100 if (REG_P (x)) 2101 { 2102 /* L = least significant word, H = most significant word. */ 2103 if ((WORDS_BIG_ENDIAN != 0) ^ (code == 'L')) 2104 fputs (reg_names[REGNO (x)], file); 2105 else 2106 fputs (reg_names[REGNO (x)+1], file); 2107 } 2108 else if (CONST_INT_P (x) 2109 || GET_CODE (x) == CONST_DOUBLE) 2110 { 2111 rtx first, second; 2112 2113 split_double (x, &first, &second); 2114 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 2115 code == 'L' ? INTVAL (first) : INTVAL (second)); 2116 } 2117 else 2118 output_operand_lossage ("invalid operand to %%H/%%L code"); 2119 return; 2120 2121 case 'A' : 2122 { 2123 char str[30]; 2124 2125 if (GET_CODE (x) != CONST_DOUBLE 2126 || GET_MODE_CLASS (GET_MODE (x)) != MODE_FLOAT) 2127 fatal_insn ("bad insn for 'A'", x); 2128 2129 real_to_decimal (str, CONST_DOUBLE_REAL_VALUE (x), sizeof (str), 0, 1); 2130 fprintf (file, "%s", str); 2131 return; 2132 } 2133 2134 case 'B' : /* Bottom half. */ 2135 case 'T' : /* Top half. */ 2136 /* Output the argument to a `seth' insn (sets the Top half-word). 2137 For constants output arguments to a seth/or3 pair to set Top and 2138 Bottom halves. For symbols output arguments to a seth/add3 pair to 2139 set Top and Bottom halves. The difference exists because for 2140 constants seth/or3 is more readable but for symbols we need to use 2141 the same scheme as `ld' and `st' insns (16-bit addend is signed). */ 2142 switch (GET_CODE (x)) 2143 { 2144 case CONST_INT : 2145 case CONST_DOUBLE : 2146 { 2147 rtx first, second; 2148 2149 split_double (x, &first, &second); 2150 x = WORDS_BIG_ENDIAN ? second : first; 2151 fprintf (file, HOST_WIDE_INT_PRINT_HEX, 2152 (code == 'B' 2153 ? INTVAL (x) & 0xffff 2154 : (INTVAL (x) >> 16) & 0xffff)); 2155 } 2156 return; 2157 case CONST : 2158 case SYMBOL_REF : 2159 if (code == 'B' 2160 && small_data_operand (x, VOIDmode)) 2161 { 2162 fputs ("sda(", file); 2163 output_addr_const (file, x); 2164 fputc (')', file); 2165 return; 2166 } 2167 /* fall through */ 2168 case LABEL_REF : 2169 fputs (code == 'T' ? "shigh(" : "low(", file); 2170 output_addr_const (file, x); 2171 fputc (')', file); 2172 return; 2173 default : 2174 output_operand_lossage ("invalid operand to %%T/%%B code"); 2175 return; 2176 } 2177 break; 2178 2179 case 'U' : 2180 /* ??? wip */ 2181 /* Output a load/store with update indicator if appropriate. */ 2182 if (MEM_P (x)) 2183 { 2184 if (GET_CODE (XEXP (x, 0)) == PRE_INC 2185 || GET_CODE (XEXP (x, 0)) == PRE_DEC) 2186 fputs (".a", file); 2187 } 2188 else 2189 output_operand_lossage ("invalid operand to %%U code"); 2190 return; 2191 2192 case 'N' : 2193 /* Print a constant value negated. */ 2194 if (CONST_INT_P (x)) 2195 output_addr_const (file, GEN_INT (- INTVAL (x))); 2196 else 2197 output_operand_lossage ("invalid operand to %%N code"); 2198 return; 2199 2200 case 'X' : 2201 /* Print a const_int in hex. Used in comments. */ 2202 if (CONST_INT_P (x)) 2203 fprintf (file, HOST_WIDE_INT_PRINT_HEX, INTVAL (x)); 2204 return; 2205 2206 case '#' : 2207 fputs (IMMEDIATE_PREFIX, file); 2208 return; 2209 2210 case 0 : 2211 /* Do nothing special. */ 2212 break; 2213 2214 default : 2215 /* Unknown flag. */ 2216 output_operand_lossage ("invalid operand output code"); 2217 } 2218 2219 switch (GET_CODE (x)) 2220 { 2221 case REG : 2222 fputs (reg_names[REGNO (x)], file); 2223 break; 2224 2225 case MEM : 2226 addr = XEXP (x, 0); 2227 if (GET_CODE (addr) == PRE_INC) 2228 { 2229 if (!REG_P (XEXP (addr, 0))) 2230 fatal_insn ("pre-increment address is not a register", x); 2231 2232 fprintf (file, "@+%s", reg_names[REGNO (XEXP (addr, 0))]); 2233 } 2234 else if (GET_CODE (addr) == PRE_DEC) 2235 { 2236 if (!REG_P (XEXP (addr, 0))) 2237 fatal_insn ("pre-decrement address is not a register", x); 2238 2239 fprintf (file, "@-%s", reg_names[REGNO (XEXP (addr, 0))]); 2240 } 2241 else if (GET_CODE (addr) == POST_INC) 2242 { 2243 if (!REG_P (XEXP (addr, 0))) 2244 fatal_insn ("post-increment address is not a register", x); 2245 2246 fprintf (file, "@%s+", reg_names[REGNO (XEXP (addr, 0))]); 2247 } 2248 else 2249 { 2250 fputs ("@(", file); 2251 output_address (XEXP (x, 0)); 2252 fputc (')', file); 2253 } 2254 break; 2255 2256 case CONST_DOUBLE : 2257 /* We handle SFmode constants here as output_addr_const doesn't. */ 2258 if (GET_MODE (x) == SFmode) 2259 { 2260 REAL_VALUE_TYPE d; 2261 long l; 2262 2263 REAL_VALUE_FROM_CONST_DOUBLE (d, x); 2264 REAL_VALUE_TO_TARGET_SINGLE (d, l); 2265 fprintf (file, "0x%08lx", l); 2266 break; 2267 } 2268 2269 /* Fall through. Let output_addr_const deal with it. */ 2270 2271 default : 2272 output_addr_const (file, x); 2273 break; 2274 } 2275 } 2276 2277 /* Print a memory address as an operand to reference that memory location. */ 2278 2279 static void 2280 m32r_print_operand_address (FILE * file, rtx addr) 2281 { 2282 rtx base; 2283 rtx index = 0; 2284 int offset = 0; 2285 2286 switch (GET_CODE (addr)) 2287 { 2288 case REG : 2289 fputs (reg_names[REGNO (addr)], file); 2290 break; 2291 2292 case PLUS : 2293 if (CONST_INT_P (XEXP (addr, 0))) 2294 offset = INTVAL (XEXP (addr, 0)), base = XEXP (addr, 1); 2295 else if (CONST_INT_P (XEXP (addr, 1))) 2296 offset = INTVAL (XEXP (addr, 1)), base = XEXP (addr, 0); 2297 else 2298 base = XEXP (addr, 0), index = XEXP (addr, 1); 2299 if (REG_P (base)) 2300 { 2301 /* Print the offset first (if present) to conform to the manual. */ 2302 if (index == 0) 2303 { 2304 if (offset != 0) 2305 fprintf (file, "%d,", offset); 2306 fputs (reg_names[REGNO (base)], file); 2307 } 2308 /* The chip doesn't support this, but left in for generality. */ 2309 else if (REG_P (index)) 2310 fprintf (file, "%s,%s", 2311 reg_names[REGNO (base)], reg_names[REGNO (index)]); 2312 /* Not sure this can happen, but leave in for now. */ 2313 else if (GET_CODE (index) == SYMBOL_REF) 2314 { 2315 output_addr_const (file, index); 2316 fputc (',', file); 2317 fputs (reg_names[REGNO (base)], file); 2318 } 2319 else 2320 fatal_insn ("bad address", addr); 2321 } 2322 else if (GET_CODE (base) == LO_SUM) 2323 { 2324 gcc_assert (!index && REG_P (XEXP (base, 0))); 2325 if (small_data_operand (XEXP (base, 1), VOIDmode)) 2326 fputs ("sda(", file); 2327 else 2328 fputs ("low(", file); 2329 output_addr_const (file, plus_constant (Pmode, XEXP (base, 1), 2330 offset)); 2331 fputs ("),", file); 2332 fputs (reg_names[REGNO (XEXP (base, 0))], file); 2333 } 2334 else 2335 fatal_insn ("bad address", addr); 2336 break; 2337 2338 case LO_SUM : 2339 if (!REG_P (XEXP (addr, 0))) 2340 fatal_insn ("lo_sum not of register", addr); 2341 if (small_data_operand (XEXP (addr, 1), VOIDmode)) 2342 fputs ("sda(", file); 2343 else 2344 fputs ("low(", file); 2345 output_addr_const (file, XEXP (addr, 1)); 2346 fputs ("),", file); 2347 fputs (reg_names[REGNO (XEXP (addr, 0))], file); 2348 break; 2349 2350 case PRE_INC : /* Assume SImode. */ 2351 fprintf (file, "+%s", reg_names[REGNO (XEXP (addr, 0))]); 2352 break; 2353 2354 case PRE_DEC : /* Assume SImode. */ 2355 fprintf (file, "-%s", reg_names[REGNO (XEXP (addr, 0))]); 2356 break; 2357 2358 case POST_INC : /* Assume SImode. */ 2359 fprintf (file, "%s+", reg_names[REGNO (XEXP (addr, 0))]); 2360 break; 2361 2362 default : 2363 output_addr_const (file, addr); 2364 break; 2365 } 2366 } 2367 2368 static bool 2369 m32r_print_operand_punct_valid_p (unsigned char code) 2370 { 2371 return m32r_punct_chars[code]; 2372 } 2373 2374 /* Return true if the operands are the constants 0 and 1. */ 2375 2376 int 2377 zero_and_one (rtx operand1, rtx operand2) 2378 { 2379 return 2380 CONST_INT_P (operand1) 2381 && CONST_INT_P (operand2) 2382 && ( ((INTVAL (operand1) == 0) && (INTVAL (operand2) == 1)) 2383 ||((INTVAL (operand1) == 1) && (INTVAL (operand2) == 0))); 2384 } 2385 2386 /* Generate the correct assembler code to handle the conditional loading of a 2387 value into a register. It is known that the operands satisfy the 2388 conditional_move_operand() function above. The destination is operand[0]. 2389 The condition is operand [1]. The 'true' value is operand [2] and the 2390 'false' value is operand [3]. */ 2391 2392 char * 2393 emit_cond_move (rtx * operands, rtx insn ATTRIBUTE_UNUSED) 2394 { 2395 static char buffer [100]; 2396 const char * dest = reg_names [REGNO (operands [0])]; 2397 2398 buffer [0] = 0; 2399 2400 /* Destination must be a register. */ 2401 gcc_assert (REG_P (operands [0])); 2402 gcc_assert (conditional_move_operand (operands [2], SImode)); 2403 gcc_assert (conditional_move_operand (operands [3], SImode)); 2404 2405 /* Check to see if the test is reversed. */ 2406 if (GET_CODE (operands [1]) == NE) 2407 { 2408 rtx tmp = operands [2]; 2409 operands [2] = operands [3]; 2410 operands [3] = tmp; 2411 } 2412 2413 sprintf (buffer, "mvfc %s, cbr", dest); 2414 2415 /* If the true value was '0' then we need to invert the results of the move. */ 2416 if (INTVAL (operands [2]) == 0) 2417 sprintf (buffer + strlen (buffer), "\n\txor3 %s, %s, #1", 2418 dest, dest); 2419 2420 return buffer; 2421 } 2422 2423 /* Returns true if the registers contained in the two 2424 rtl expressions are different. */ 2425 2426 int 2427 m32r_not_same_reg (rtx a, rtx b) 2428 { 2429 int reg_a = -1; 2430 int reg_b = -2; 2431 2432 while (GET_CODE (a) == SUBREG) 2433 a = SUBREG_REG (a); 2434 2435 if (REG_P (a)) 2436 reg_a = REGNO (a); 2437 2438 while (GET_CODE (b) == SUBREG) 2439 b = SUBREG_REG (b); 2440 2441 if (REG_P (b)) 2442 reg_b = REGNO (b); 2443 2444 return reg_a != reg_b; 2445 } 2446 2447 2448 rtx 2449 m32r_function_symbol (const char *name) 2450 { 2451 int extra_flags = 0; 2452 enum m32r_model model; 2453 rtx sym = gen_rtx_SYMBOL_REF (Pmode, name); 2454 2455 if (TARGET_MODEL_SMALL) 2456 model = M32R_MODEL_SMALL; 2457 else if (TARGET_MODEL_MEDIUM) 2458 model = M32R_MODEL_MEDIUM; 2459 else if (TARGET_MODEL_LARGE) 2460 model = M32R_MODEL_LARGE; 2461 else 2462 gcc_unreachable (); /* Shouldn't happen. */ 2463 extra_flags |= model << SYMBOL_FLAG_MODEL_SHIFT; 2464 2465 if (extra_flags) 2466 SYMBOL_REF_FLAGS (sym) |= extra_flags; 2467 2468 return sym; 2469 } 2470 2471 /* Use a library function to move some bytes. */ 2472 2473 static void 2474 block_move_call (rtx dest_reg, rtx src_reg, rtx bytes_rtx) 2475 { 2476 /* We want to pass the size as Pmode, which will normally be SImode 2477 but will be DImode if we are using 64-bit longs and pointers. */ 2478 if (GET_MODE (bytes_rtx) != VOIDmode 2479 && GET_MODE (bytes_rtx) != Pmode) 2480 bytes_rtx = convert_to_mode (Pmode, bytes_rtx, 1); 2481 2482 emit_library_call (m32r_function_symbol ("memcpy"), LCT_NORMAL, 2483 VOIDmode, 3, dest_reg, Pmode, src_reg, Pmode, 2484 convert_to_mode (TYPE_MODE (sizetype), bytes_rtx, 2485 TYPE_UNSIGNED (sizetype)), 2486 TYPE_MODE (sizetype)); 2487 } 2488 2489 /* Expand string/block move operations. 2490 2491 operands[0] is the pointer to the destination. 2492 operands[1] is the pointer to the source. 2493 operands[2] is the number of bytes to move. 2494 operands[3] is the alignment. 2495 2496 Returns 1 upon success, 0 otherwise. */ 2497 2498 int 2499 m32r_expand_block_move (rtx operands[]) 2500 { 2501 rtx orig_dst = operands[0]; 2502 rtx orig_src = operands[1]; 2503 rtx bytes_rtx = operands[2]; 2504 rtx align_rtx = operands[3]; 2505 int constp = CONST_INT_P (bytes_rtx); 2506 HOST_WIDE_INT bytes = constp ? INTVAL (bytes_rtx) : 0; 2507 int align = INTVAL (align_rtx); 2508 int leftover; 2509 rtx src_reg; 2510 rtx dst_reg; 2511 2512 if (constp && bytes <= 0) 2513 return 1; 2514 2515 /* Move the address into scratch registers. */ 2516 dst_reg = copy_addr_to_reg (XEXP (orig_dst, 0)); 2517 src_reg = copy_addr_to_reg (XEXP (orig_src, 0)); 2518 2519 if (align > UNITS_PER_WORD) 2520 align = UNITS_PER_WORD; 2521 2522 /* If we prefer size over speed, always use a function call. 2523 If we do not know the size, use a function call. 2524 If the blocks are not word aligned, use a function call. */ 2525 if (optimize_size || ! constp || align != UNITS_PER_WORD) 2526 { 2527 block_move_call (dst_reg, src_reg, bytes_rtx); 2528 return 0; 2529 } 2530 2531 leftover = bytes % MAX_MOVE_BYTES; 2532 bytes -= leftover; 2533 2534 /* If necessary, generate a loop to handle the bulk of the copy. */ 2535 if (bytes) 2536 { 2537 rtx label = NULL_RTX; 2538 rtx final_src = NULL_RTX; 2539 rtx at_a_time = GEN_INT (MAX_MOVE_BYTES); 2540 rtx rounded_total = GEN_INT (bytes); 2541 rtx new_dst_reg = gen_reg_rtx (SImode); 2542 rtx new_src_reg = gen_reg_rtx (SImode); 2543 2544 /* If we are going to have to perform this loop more than 2545 once, then generate a label and compute the address the 2546 source register will contain upon completion of the final 2547 iteration. */ 2548 if (bytes > MAX_MOVE_BYTES) 2549 { 2550 final_src = gen_reg_rtx (Pmode); 2551 2552 if (INT16_P(bytes)) 2553 emit_insn (gen_addsi3 (final_src, src_reg, rounded_total)); 2554 else 2555 { 2556 emit_insn (gen_movsi (final_src, rounded_total)); 2557 emit_insn (gen_addsi3 (final_src, final_src, src_reg)); 2558 } 2559 2560 label = gen_label_rtx (); 2561 emit_label (label); 2562 } 2563 2564 /* It is known that output_block_move() will update src_reg to point 2565 to the word after the end of the source block, and dst_reg to point 2566 to the last word of the destination block, provided that the block 2567 is MAX_MOVE_BYTES long. */ 2568 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, at_a_time, 2569 new_dst_reg, new_src_reg)); 2570 emit_move_insn (dst_reg, new_dst_reg); 2571 emit_move_insn (src_reg, new_src_reg); 2572 emit_insn (gen_addsi3 (dst_reg, dst_reg, GEN_INT (4))); 2573 2574 if (bytes > MAX_MOVE_BYTES) 2575 { 2576 rtx test = gen_rtx_NE (VOIDmode, src_reg, final_src); 2577 emit_jump_insn (gen_cbranchsi4 (test, src_reg, final_src, label)); 2578 } 2579 } 2580 2581 if (leftover) 2582 emit_insn (gen_movmemsi_internal (dst_reg, src_reg, GEN_INT (leftover), 2583 gen_reg_rtx (SImode), 2584 gen_reg_rtx (SImode))); 2585 return 1; 2586 } 2587 2588 2589 /* Emit load/stores for a small constant word aligned block_move. 2590 2591 operands[0] is the memory address of the destination. 2592 operands[1] is the memory address of the source. 2593 operands[2] is the number of bytes to move. 2594 operands[3] is a temp register. 2595 operands[4] is a temp register. */ 2596 2597 void 2598 m32r_output_block_move (rtx insn ATTRIBUTE_UNUSED, rtx operands[]) 2599 { 2600 HOST_WIDE_INT bytes = INTVAL (operands[2]); 2601 int first_time; 2602 int got_extra = 0; 2603 2604 gcc_assert (bytes >= 1 && bytes <= MAX_MOVE_BYTES); 2605 2606 /* We do not have a post-increment store available, so the first set of 2607 stores are done without any increment, then the remaining ones can use 2608 the pre-increment addressing mode. 2609 2610 Note: expand_block_move() also relies upon this behavior when building 2611 loops to copy large blocks. */ 2612 first_time = 1; 2613 2614 while (bytes > 0) 2615 { 2616 if (bytes >= 8) 2617 { 2618 if (first_time) 2619 { 2620 output_asm_insn ("ld\t%5, %p1", operands); 2621 output_asm_insn ("ld\t%6, %p1", operands); 2622 output_asm_insn ("st\t%5, @%0", operands); 2623 output_asm_insn ("st\t%6, %s0", operands); 2624 } 2625 else 2626 { 2627 output_asm_insn ("ld\t%5, %p1", operands); 2628 output_asm_insn ("ld\t%6, %p1", operands); 2629 output_asm_insn ("st\t%5, %s0", operands); 2630 output_asm_insn ("st\t%6, %s0", operands); 2631 } 2632 2633 bytes -= 8; 2634 } 2635 else if (bytes >= 4) 2636 { 2637 if (bytes > 4) 2638 got_extra = 1; 2639 2640 output_asm_insn ("ld\t%5, %p1", operands); 2641 2642 if (got_extra) 2643 output_asm_insn ("ld\t%6, %p1", operands); 2644 2645 if (first_time) 2646 output_asm_insn ("st\t%5, @%0", operands); 2647 else 2648 output_asm_insn ("st\t%5, %s0", operands); 2649 2650 bytes -= 4; 2651 } 2652 else 2653 { 2654 /* Get the entire next word, even though we do not want all of it. 2655 The saves us from doing several smaller loads, and we assume that 2656 we cannot cause a page fault when at least part of the word is in 2657 valid memory [since we don't get called if things aren't properly 2658 aligned]. */ 2659 int dst_offset = first_time ? 0 : 4; 2660 /* The amount of increment we have to make to the 2661 destination pointer. */ 2662 int dst_inc_amount = dst_offset + bytes - 4; 2663 /* The same for the source pointer. */ 2664 int src_inc_amount = bytes; 2665 int last_shift; 2666 rtx my_operands[3]; 2667 2668 /* If got_extra is true then we have already loaded 2669 the next word as part of loading and storing the previous word. */ 2670 if (! got_extra) 2671 output_asm_insn ("ld\t%6, @%1", operands); 2672 2673 if (bytes >= 2) 2674 { 2675 bytes -= 2; 2676 2677 output_asm_insn ("sra3\t%5, %6, #16", operands); 2678 my_operands[0] = operands[5]; 2679 my_operands[1] = GEN_INT (dst_offset); 2680 my_operands[2] = operands[0]; 2681 output_asm_insn ("sth\t%0, @(%1,%2)", my_operands); 2682 2683 /* If there is a byte left to store then increment the 2684 destination address and shift the contents of the source 2685 register down by 8 bits. We could not do the address 2686 increment in the store half word instruction, because it does 2687 not have an auto increment mode. */ 2688 if (bytes > 0) /* assert (bytes == 1) */ 2689 { 2690 dst_offset += 2; 2691 last_shift = 8; 2692 } 2693 } 2694 else 2695 last_shift = 24; 2696 2697 if (bytes > 0) 2698 { 2699 my_operands[0] = operands[6]; 2700 my_operands[1] = GEN_INT (last_shift); 2701 output_asm_insn ("srai\t%0, #%1", my_operands); 2702 my_operands[0] = operands[6]; 2703 my_operands[1] = GEN_INT (dst_offset); 2704 my_operands[2] = operands[0]; 2705 output_asm_insn ("stb\t%0, @(%1,%2)", my_operands); 2706 } 2707 2708 /* Update the destination pointer if needed. We have to do 2709 this so that the patterns matches what we output in this 2710 function. */ 2711 if (dst_inc_amount 2712 && !find_reg_note (insn, REG_UNUSED, operands[0])) 2713 { 2714 my_operands[0] = operands[0]; 2715 my_operands[1] = GEN_INT (dst_inc_amount); 2716 output_asm_insn ("addi\t%0, #%1", my_operands); 2717 } 2718 2719 /* Update the source pointer if needed. We have to do this 2720 so that the patterns matches what we output in this 2721 function. */ 2722 if (src_inc_amount 2723 && !find_reg_note (insn, REG_UNUSED, operands[1])) 2724 { 2725 my_operands[0] = operands[1]; 2726 my_operands[1] = GEN_INT (src_inc_amount); 2727 output_asm_insn ("addi\t%0, #%1", my_operands); 2728 } 2729 2730 bytes = 0; 2731 } 2732 2733 first_time = 0; 2734 } 2735 } 2736 2737 /* Return true if using NEW_REG in place of OLD_REG is ok. */ 2738 2739 int 2740 m32r_hard_regno_rename_ok (unsigned int old_reg ATTRIBUTE_UNUSED, 2741 unsigned int new_reg) 2742 { 2743 /* Interrupt routines can't clobber any register that isn't already used. */ 2744 if (lookup_attribute ("interrupt", DECL_ATTRIBUTES (current_function_decl)) 2745 && !df_regs_ever_live_p (new_reg)) 2746 return 0; 2747 2748 return 1; 2749 } 2750 2751 rtx 2752 m32r_return_addr (int count) 2753 { 2754 if (count != 0) 2755 return const0_rtx; 2756 2757 return get_hard_reg_initial_val (Pmode, RETURN_ADDR_REGNUM); 2758 } 2759 2760 static void 2761 m32r_trampoline_init (rtx m_tramp, tree fndecl, rtx chain_value) 2762 { 2763 emit_move_insn (adjust_address (m_tramp, SImode, 0), 2764 gen_int_mode (TARGET_LITTLE_ENDIAN ? 2765 0x017e8e17 : 0x178e7e01, SImode)); 2766 emit_move_insn (adjust_address (m_tramp, SImode, 4), 2767 gen_int_mode (TARGET_LITTLE_ENDIAN ? 2768 0x0c00ae86 : 0x86ae000c, SImode)); 2769 emit_move_insn (adjust_address (m_tramp, SImode, 8), 2770 gen_int_mode (TARGET_LITTLE_ENDIAN ? 2771 0xe627871e : 0x1e8727e6, SImode)); 2772 emit_move_insn (adjust_address (m_tramp, SImode, 12), 2773 gen_int_mode (TARGET_LITTLE_ENDIAN ? 2774 0xc616c626 : 0x26c61fc6, SImode)); 2775 emit_move_insn (adjust_address (m_tramp, SImode, 16), 2776 chain_value); 2777 emit_move_insn (adjust_address (m_tramp, SImode, 20), 2778 XEXP (DECL_RTL (fndecl), 0)); 2779 2780 if (m32r_cache_flush_trap >= 0) 2781 emit_insn (gen_flush_icache 2782 (validize_mem (adjust_address (m_tramp, SImode, 0)), 2783 gen_int_mode (m32r_cache_flush_trap, SImode))); 2784 else if (m32r_cache_flush_func && m32r_cache_flush_func[0]) 2785 emit_library_call (m32r_function_symbol (m32r_cache_flush_func), 2786 LCT_NORMAL, VOIDmode, 3, XEXP (m_tramp, 0), Pmode, 2787 gen_int_mode (TRAMPOLINE_SIZE, SImode), SImode, 2788 GEN_INT (3), SImode); 2789 } 2790 2791 /* True if X is a reg that can be used as a base reg. */ 2792 2793 static bool 2794 m32r_rtx_ok_for_base_p (const_rtx x, bool strict) 2795 { 2796 if (! REG_P (x)) 2797 return false; 2798 2799 if (strict) 2800 { 2801 if (GPR_P (REGNO (x))) 2802 return true; 2803 } 2804 else 2805 { 2806 if (GPR_P (REGNO (x)) 2807 || REGNO (x) == ARG_POINTER_REGNUM 2808 || ! HARD_REGISTER_P (x)) 2809 return true; 2810 } 2811 2812 return false; 2813 } 2814 2815 static inline bool 2816 m32r_rtx_ok_for_offset_p (const_rtx x) 2817 { 2818 return (CONST_INT_P (x) && INT16_P (INTVAL (x))); 2819 } 2820 2821 static inline bool 2822 m32r_legitimate_offset_addres_p (enum machine_mode mode ATTRIBUTE_UNUSED, 2823 const_rtx x, bool strict) 2824 { 2825 if (GET_CODE (x) == PLUS 2826 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict) 2827 && m32r_rtx_ok_for_offset_p (XEXP (x, 1))) 2828 return true; 2829 2830 return false; 2831 } 2832 2833 /* For LO_SUM addresses, do not allow them if the MODE is > 1 word, 2834 since more than one instruction will be required. */ 2835 2836 static inline bool 2837 m32r_legitimate_lo_sum_addres_p (enum machine_mode mode, const_rtx x, 2838 bool strict) 2839 { 2840 if (GET_CODE (x) == LO_SUM 2841 && (mode != BLKmode && GET_MODE_SIZE (mode) <= UNITS_PER_WORD) 2842 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict) 2843 && CONSTANT_P (XEXP (x, 1))) 2844 return true; 2845 2846 return false; 2847 } 2848 2849 /* Is this a load and increment operation. */ 2850 2851 static inline bool 2852 m32r_load_postinc_p (enum machine_mode mode, const_rtx x, bool strict) 2853 { 2854 if ((mode == SImode || mode == SFmode) 2855 && GET_CODE (x) == POST_INC 2856 && REG_P (XEXP (x, 0)) 2857 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)) 2858 return true; 2859 2860 return false; 2861 } 2862 2863 /* Is this an increment/decrement and store operation. */ 2864 2865 static inline bool 2866 m32r_store_preinc_predec_p (enum machine_mode mode, const_rtx x, bool strict) 2867 { 2868 if ((mode == SImode || mode == SFmode) 2869 && (GET_CODE (x) == PRE_INC || GET_CODE (x) == PRE_DEC) 2870 && REG_P (XEXP (x, 0)) \ 2871 && m32r_rtx_ok_for_base_p (XEXP (x, 0), strict)) 2872 return true; 2873 2874 return false; 2875 } 2876 2877 /* Implement TARGET_LEGITIMATE_ADDRESS_P. */ 2878 2879 static bool 2880 m32r_legitimate_address_p (enum machine_mode mode, rtx x, bool strict) 2881 { 2882 if (m32r_rtx_ok_for_base_p (x, strict) 2883 || m32r_legitimate_offset_addres_p (mode, x, strict) 2884 || m32r_legitimate_lo_sum_addres_p (mode, x, strict) 2885 || m32r_load_postinc_p (mode, x, strict) 2886 || m32r_store_preinc_predec_p (mode, x, strict)) 2887 return true; 2888 2889 return false; 2890 } 2891 2892 static void 2893 m32r_conditional_register_usage (void) 2894 { 2895 if (flag_pic) 2896 { 2897 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; 2898 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; 2899 } 2900 } 2901 2902 /* Implement TARGET_LEGITIMATE_CONSTANT_P 2903 2904 We don't allow (plus symbol large-constant) as the relocations can't 2905 describe it. INTVAL > 32767 handles both 16-bit and 24-bit relocations. 2906 We allow all CONST_DOUBLE's as the md file patterns will force the 2907 constant to memory if they can't handle them. */ 2908 2909 static bool 2910 m32r_legitimate_constant_p (enum machine_mode mode ATTRIBUTE_UNUSED, rtx x) 2911 { 2912 return !(GET_CODE (x) == CONST 2913 && GET_CODE (XEXP (x, 0)) == PLUS 2914 && (GET_CODE (XEXP (XEXP (x, 0), 0)) == SYMBOL_REF 2915 || GET_CODE (XEXP (XEXP (x, 0), 0)) == LABEL_REF) 2916 && CONST_INT_P (XEXP (XEXP (x, 0), 1)) 2917 && UINTVAL (XEXP (XEXP (x, 0), 1)) > 32767); 2918 } 2919