1 /* Target Definitions for R8C/M16C/M32C 2 Copyright (C) 2005-2013 Free Software Foundation, Inc. 3 Contributed by Red Hat. 4 5 This file is part of GCC. 6 7 GCC is free software; you can redistribute it and/or modify it 8 under the terms of the GNU General Public License as published 9 by the Free Software Foundation; either version 3, or (at your 10 option) any later version. 11 12 GCC is distributed in the hope that it will be useful, but WITHOUT 13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15 License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with GCC; see the file COPYING3. If not see 19 <http://www.gnu.org/licenses/>. */ 20 21 #ifndef GCC_M32C_H 22 #define GCC_M32C_H 23 24 /* Controlling the Compilation Driver, `gcc'. */ 25 26 #undef STARTFILE_SPEC 27 #define STARTFILE_SPEC "crt0.o%s crtbegin.o%s" 28 29 #undef ENDFILE_SPEC 30 #define ENDFILE_SPEC "crtend.o%s crtn.o%s" 31 32 #undef LINK_SPEC 33 #define LINK_SPEC "%{h*} %{v:-V} \ 34 %{static:-Bstatic} %{shared:-shared} %{symbolic:-Bsymbolic}" 35 36 /* There are four CPU series we support, but they basically break down 37 into two families - the R8C/M16C families, with 16-bit address 38 registers and one set of opcodes, and the M32CM/M32C group, with 39 24-bit address registers and a different set of opcodes. The 40 assembler doesn't care except for which opcode set is needed; the 41 big difference is in the memory maps, which we cover in 42 LIB_SPEC. */ 43 44 #undef ASM_SPEC 45 #define ASM_SPEC "\ 46 %{mcpu=r8c:--m16c} \ 47 %{mcpu=m16c:--m16c} \ 48 %{mcpu=m32cm:--m32c} \ 49 %{mcpu=m32c:--m32c} " 50 51 /* The default is R8C hardware. We support a simulator, which has its 52 own libgloss and link map, plus one default link map for each chip 53 family. Most of the logic here is making sure we do the right 54 thing when no CPU is specified, which defaults to R8C. */ 55 #undef LIB_SPEC 56 #define LIB_SPEC "-( -lc %{msim:-lsim}%{!msim:-lnosys} -) \ 57 %{msim:%{!T*: %{mcpu=m32cm:%Tsim24.ld}%{mcpu=m32c:%Tsim24.ld} \ 58 %{!mcpu=m32cm:%{!mcpu=m32c:%Tsim16.ld}}}} \ 59 %{!T*:%{!msim: %{mcpu=m16c:%Tm16c.ld} \ 60 %{mcpu=m32cm:%Tm32cm.ld} \ 61 %{mcpu=m32c:%Tm32c.ld} \ 62 %{!mcpu=m16c:%{!mcpu=m32cm:%{!mcpu=m32c:%Tr8c.ld}}}}} \ 63 " 64 65 /* Run-time Target Specification */ 66 67 /* Nothing unusual here. */ 68 #define TARGET_CPU_CPP_BUILTINS() \ 69 { \ 70 builtin_assert ("cpu=m32c"); \ 71 builtin_assert ("machine=m32c"); \ 72 builtin_define ("__m32c__=1"); \ 73 if (TARGET_R8C) \ 74 builtin_define ("__r8c_cpu__=1"); \ 75 if (TARGET_M16C) \ 76 builtin_define ("__m16c_cpu__=1"); \ 77 if (TARGET_M32CM) \ 78 builtin_define ("__m32cm_cpu__=1"); \ 79 if (TARGET_M32C) \ 80 builtin_define ("__m32c_cpu__=1"); \ 81 } 82 83 /* The pragma handlers need to know if we've started processing 84 functions yet, as the memregs pragma should only be given at the 85 beginning of the file. This variable starts off TRUE and later 86 becomes FALSE. */ 87 extern int ok_to_change_target_memregs; 88 89 /* TARGET_CPU is a multi-way option set in m32c.opt. While we could 90 use enums or defines for this, this and m32c.opt are the only 91 places that know (or care) what values are being used. */ 92 #define TARGET_R8C (target_cpu == 'r') 93 #define TARGET_M16C (target_cpu == '6') 94 #define TARGET_M32CM (target_cpu == 'm') 95 #define TARGET_M32C (target_cpu == '3') 96 97 /* Address register sizes. Warning: these are used all over the place 98 to select between the two CPU families in general. */ 99 #define TARGET_A16 (TARGET_R8C || TARGET_M16C) 100 #define TARGET_A24 (TARGET_M32CM || TARGET_M32C) 101 102 /* Defining data structures for per-function information */ 103 104 typedef struct GTY (()) machine_function 105 { 106 /* How much we adjust the stack when returning from an exception 107 handler. */ 108 rtx eh_stack_adjust; 109 110 /* TRUE if the current function is an interrupt handler. */ 111 int is_interrupt; 112 113 /* TRUE if the current function is a leaf function. Currently, this 114 only affects saving $a0 in interrupt functions. */ 115 int is_leaf; 116 117 /* Bitmask that keeps track of which registers are used in an 118 interrupt function, so we know which ones need to be saved and 119 restored. */ 120 int intr_pushm; 121 /* Likewise, one element for each memreg that needs to be saved. */ 122 char intr_pushmem[16]; 123 124 /* TRUE if the current function can use a simple RTS to return, instead 125 of the longer ENTER/EXIT pair. */ 126 int use_rts; 127 } 128 machine_function; 129 130 #define INIT_EXPANDERS m32c_init_expanders () 131 132 /* Storage Layout */ 133 134 #define BITS_BIG_ENDIAN 0 135 #define BYTES_BIG_ENDIAN 0 136 #define WORDS_BIG_ENDIAN 0 137 138 /* We can do QI, HI, and SI operations pretty much equally well, but 139 GCC expects us to have a "native" format, so we pick the one that 140 matches "int". Pointers are 16 bits for R8C/M16C (when TARGET_A16 141 is true) and 24 bits for M32CM/M32C (when TARGET_A24 is true), but 142 24-bit pointers are stored in 32-bit words. */ 143 #define BITS_PER_UNIT 8 144 #define UNITS_PER_WORD 2 145 #define POINTER_SIZE (TARGET_A16 ? 16 : 32) 146 #define POINTERS_EXTEND_UNSIGNED 1 147 /* We have a problem with libgcc2. It only defines two versions of 148 each function, one for "int" and one for "long long". Ie it assumes 149 that "sizeof (int) == sizeof (long)". For the M32C this is not true 150 and we need a third set of functions. We explicitly define 151 LIBGCC2_UNITS_PER_WORD here so that it is clear that we are expecting 152 to get the SI and DI versions from the libgcc2.c sources, and we 153 provide our own set of HI functions in m32c-lib2.c, which is why this 154 definition is surrounded by #ifndef..#endif. */ 155 #ifndef LIBGCC2_UNITS_PER_WORD 156 #define LIBGCC2_UNITS_PER_WORD 4 157 #endif 158 159 /* These match the alignment enforced by the two types of stack operations. */ 160 #define PARM_BOUNDARY (TARGET_A16 ? 8 : 16) 161 #define STACK_BOUNDARY (TARGET_A16 ? 8 : 16) 162 163 /* We do this because we care more about space than about speed. For 164 the chips with 16-bit busses, we could set these to 16 if 165 desired. */ 166 #define FUNCTION_BOUNDARY 8 167 #define BIGGEST_ALIGNMENT 8 168 169 /* Since we have a maximum structure alignment of 8 there 170 is no need to enforce any alignment of bitfield types. */ 171 #undef PCC_BITFIELD_TYPE_MATTERS 172 #define PCC_BITFIELD_TYPE_MATTERS 0 173 174 #define STRICT_ALIGNMENT 0 175 #define SLOW_BYTE_ACCESS 1 176 177 /* Layout of Source Language Data Types */ 178 179 #define INT_TYPE_SIZE 16 180 #define SHORT_TYPE_SIZE 16 181 #define LONG_TYPE_SIZE 32 182 #define LONG_LONG_TYPE_SIZE 64 183 184 #define FLOAT_TYPE_SIZE 32 185 #define DOUBLE_TYPE_SIZE 64 186 #define LONG_DOUBLE_TYPE_SIZE 64 187 188 #define DEFAULT_SIGNED_CHAR 1 189 190 #undef PTRDIFF_TYPE 191 #define PTRDIFF_TYPE (TARGET_A16 ? "int" : "long int") 192 193 #undef UINTPTR_TYPE 194 #define UINTPTR_TYPE (TARGET_A16 ? "unsigned int" : "long unsigned int") 195 196 #undef SIZE_TYPE 197 #define SIZE_TYPE "unsigned int" 198 199 #undef WCHAR_TYPE 200 #define WCHAR_TYPE "long int" 201 202 #undef WCHAR_TYPE_SIZE 203 #define WCHAR_TYPE_SIZE 32 204 205 /* REGISTER USAGE */ 206 207 /* Register Basics */ 208 209 /* Register layout: 210 211 [r0h][r0l] $r0 (16 bits, or two 8-bit halves) 212 [--------] $r2 (16 bits) 213 [r1h][r1l] $r1 (16 bits, or two 8-bit halves) 214 [--------] $r3 (16 bits) 215 [---][--------] $a0 (might be 24 bits) 216 [---][--------] $a1 (might be 24 bits) 217 [---][--------] $sb (might be 24 bits) 218 [---][--------] $fb (might be 24 bits) 219 [---][--------] $sp (might be 24 bits) 220 [-------------] $pc (20 or 24 bits) 221 [---] $flg (CPU flags) 222 [---][--------] $argp (virtual) 223 [--------] $mem0 (all 16 bits) 224 . . . 225 [--------] $mem14 226 */ 227 228 #define FIRST_PSEUDO_REGISTER 20 229 230 /* Note that these two tables are modified based on which CPU family 231 you select; see m32c_conditional_register_usage for details. */ 232 233 /* r0 r2 r1 r3 - a0 a1 sb fb - sp pc flg argp - mem0..mem14 */ 234 #define FIXED_REGISTERS { 0, 0, 0, 0, \ 235 0, 0, 1, 0, \ 236 1, 1, 0, 1, \ 237 0, 0, 0, 0, 0, 0, 0, 0 } 238 #define CALL_USED_REGISTERS { 1, 1, 1, 1, \ 239 1, 1, 1, 0, \ 240 1, 1, 1, 1, \ 241 1, 1, 1, 1, 1, 1, 1, 1 } 242 243 /* The *_REGNO theme matches m32c.md and most register number 244 arguments; the PC_REGNUM is the odd one out. */ 245 #ifndef PC_REGNO 246 #define PC_REGNO 9 247 #endif 248 #define PC_REGNUM PC_REGNO 249 250 /* Order of Allocation of Registers */ 251 252 #define REG_ALLOC_ORDER { \ 253 0, 1, 2, 3, 4, 5, /* r0..r3, a0, a1 */ \ 254 12, 13, 14, 15, 16, 17, 18, 19, /* mem0..mem7 */ \ 255 6, 7, 8, 9, 10, 11 /* sb, fb, sp, pc, flg, ap */ } 256 257 /* How Values Fit in Registers */ 258 259 #define HARD_REGNO_NREGS(R,M) m32c_hard_regno_nregs (R, M) 260 #define HARD_REGNO_MODE_OK(R,M) m32c_hard_regno_ok (R, M) 261 #define MODES_TIEABLE_P(M1,M2) m32c_modes_tieable_p (M1, M2) 262 #define AVOID_CCMODE_COPIES 263 264 /* Register Classes */ 265 266 /* Most registers are special purpose in some form or another, so this 267 table is pretty big. Class names are used for constraints also; 268 for example the HL_REGS class (HL below) is "Rhl" in the md files. 269 See m32c_reg_class_from_constraint for the mapping. There's some 270 duplication so that we can better isolate the reason for using 271 constraints in the md files from the actual registers used; for 272 example we may want to exclude a1a0 from SI_REGS in the future, 273 without precluding their use as HImode registers. */ 274 275 /* m7654 - m3210 - argp flg pc sp - fb sb a1 a0 - r3 r1 r2 r0 */ 276 /* mmPAR */ 277 #define REG_CLASS_CONTENTS \ 278 { { 0x00000000 }, /* NO */\ 279 { 0x00000100 }, /* SP - sp */\ 280 { 0x00000080 }, /* FB - fb */\ 281 { 0x00000040 }, /* SB - sb */\ 282 { 0x000001c0 }, /* CR - sb fb sp */\ 283 { 0x00000001 }, /* R0 - r0 */\ 284 { 0x00000004 }, /* R1 - r1 */\ 285 { 0x00000002 }, /* R2 - r2 */\ 286 { 0x00000008 }, /* R3 - r3 */\ 287 { 0x00000003 }, /* R02 - r0r2 */\ 288 { 0x0000000c }, /* R13 - r1r3 */\ 289 { 0x00000005 }, /* HL - r0 r1 */\ 290 { 0x0000000a }, /* R23 - r2 r3 */\ 291 { 0x0000000f }, /* R03 - r0r2 r1r3 */\ 292 { 0x00000010 }, /* A0 - a0 */\ 293 { 0x00000020 }, /* A1 - a1 */\ 294 { 0x00000030 }, /* A - a0 a1 */\ 295 { 0x000000f0 }, /* AD - a0 a1 sb fp */\ 296 { 0x000001f0 }, /* PS - a0 a1 sb fp sp */\ 297 { 0x00000033 }, /* R02A - r0r2 a0 a1 */ \ 298 { 0x0000003f }, /* RA - r0 r1 r2 r3 a0 a1 */\ 299 { 0x0000007f }, /* GENERAL */\ 300 { 0x00000400 }, /* FLG */\ 301 { 0x000001ff }, /* HC - r0l r1 r2 r3 a0 a1 sb fb sp */\ 302 { 0x000ff000 }, /* MEM */\ 303 { 0x000ff003 }, /* R02_A_MEM */\ 304 { 0x000ff005 }, /* A_HL_MEM */\ 305 { 0x000ff00c }, /* R1_R3_A_MEM */\ 306 { 0x000ff00f }, /* R03_MEM */\ 307 { 0x000ff03f }, /* A_HI_MEM */\ 308 { 0x000ff0ff }, /* A_AD_CR_MEM_SI */\ 309 { 0x000ff5ff }, /* ALL */\ 310 } 311 312 #define QI_REGS HL_REGS 313 #define HI_REGS RA_REGS 314 #define SI_REGS R03_REGS 315 #define DI_REGS R03_REGS 316 317 enum reg_class 318 { 319 NO_REGS, 320 SP_REGS, 321 FB_REGS, 322 SB_REGS, 323 CR_REGS, 324 R0_REGS, 325 R1_REGS, 326 R2_REGS, 327 R3_REGS, 328 R02_REGS, 329 R13_REGS, 330 HL_REGS, 331 R23_REGS, 332 R03_REGS, 333 A0_REGS, 334 A1_REGS, 335 A_REGS, 336 AD_REGS, 337 PS_REGS, 338 R02A_REGS, 339 RA_REGS, 340 GENERAL_REGS, 341 FLG_REGS, 342 HC_REGS, 343 MEM_REGS, 344 R02_A_MEM_REGS, 345 A_HL_MEM_REGS, 346 R1_R3_A_MEM_REGS, 347 R03_MEM_REGS, 348 A_HI_MEM_REGS, 349 A_AD_CR_MEM_SI_REGS, 350 ALL_REGS, 351 LIM_REG_CLASSES 352 }; 353 354 #define N_REG_CLASSES LIM_REG_CLASSES 355 356 #define REG_CLASS_NAMES {\ 357 "NO_REGS", \ 358 "SP_REGS", \ 359 "FB_REGS", \ 360 "SB_REGS", \ 361 "CR_REGS", \ 362 "R0_REGS", \ 363 "R1_REGS", \ 364 "R2_REGS", \ 365 "R3_REGS", \ 366 "R02_REGS", \ 367 "R13_REGS", \ 368 "HL_REGS", \ 369 "R23_REGS", \ 370 "R03_REGS", \ 371 "A0_REGS", \ 372 "A1_REGS", \ 373 "A_REGS", \ 374 "AD_REGS", \ 375 "PS_REGS", \ 376 "R02A_REGS", \ 377 "RA_REGS", \ 378 "GENERAL_REGS", \ 379 "FLG_REGS", \ 380 "HC_REGS", \ 381 "MEM_REGS", \ 382 "R02_A_MEM_REGS", \ 383 "A_HL_MEM_REGS", \ 384 "R1_R3_A_MEM_REGS", \ 385 "R03_MEM_REGS", \ 386 "A_HI_MEM_REGS", \ 387 "A_AD_CR_MEM_SI_REGS", \ 388 "ALL_REGS", \ 389 } 390 391 #define REGNO_REG_CLASS(R) m32c_regno_reg_class (R) 392 393 /* We support simple displacements off address registers, nothing else. */ 394 #define BASE_REG_CLASS A_REGS 395 #define INDEX_REG_CLASS NO_REGS 396 397 /* We primarily use the new "long" constraint names, with the initial 398 letter classifying the constraint type and following letters 399 specifying which. The types are: 400 401 I - integer values 402 R - register classes 403 S - memory references (M was used) 404 A - addresses (currently unused) 405 */ 406 407 #define REGNO_OK_FOR_BASE_P(NUM) m32c_regno_ok_for_base_p (NUM) 408 #define REGNO_OK_FOR_INDEX_P(NUM) 0 409 410 #define LIMIT_RELOAD_CLASS(MODE,CLASS) \ 411 (enum reg_class) m32c_limit_reload_class (MODE, CLASS) 412 413 #define SECONDARY_RELOAD_CLASS(CLASS,MODE,X) \ 414 (enum reg_class) m32c_secondary_reload_class (CLASS, MODE, X) 415 416 #define TARGET_SMALL_REGISTER_CLASSES_FOR_MODE_P hook_bool_mode_true 417 418 #define CANNOT_CHANGE_MODE_CLASS(F,T,C) m32c_cannot_change_mode_class(F,T,C) 419 420 /* STACK AND CALLING */ 421 422 /* Frame Layout */ 423 424 /* Standard push/pop stack, no surprises here. */ 425 426 #define STACK_GROWS_DOWNWARD 1 427 #define STACK_PUSH_CODE PRE_DEC 428 #define FRAME_GROWS_DOWNWARD 1 429 430 #define STARTING_FRAME_OFFSET 0 431 #define FIRST_PARM_OFFSET(F) 0 432 433 #define RETURN_ADDR_RTX(COUNT,FA) m32c_return_addr_rtx (COUNT) 434 435 #define INCOMING_RETURN_ADDR_RTX m32c_incoming_return_addr_rtx() 436 #define INCOMING_FRAME_SP_OFFSET (TARGET_A24 ? 4 : 3) 437 438 /* Exception Handling Support */ 439 440 #define EH_RETURN_DATA_REGNO(N) m32c_eh_return_data_regno (N) 441 #define EH_RETURN_STACKADJ_RTX m32c_eh_return_stackadj_rtx () 442 443 /* Registers That Address the Stack Frame */ 444 445 #ifndef FP_REGNO 446 #define FP_REGNO 7 447 #endif 448 #ifndef SP_REGNO 449 #define SP_REGNO 8 450 #endif 451 #define AP_REGNO 11 452 453 #define STACK_POINTER_REGNUM SP_REGNO 454 #define FRAME_POINTER_REGNUM FP_REGNO 455 #define ARG_POINTER_REGNUM AP_REGNO 456 457 /* The static chain must be pointer-capable. */ 458 #define STATIC_CHAIN_REGNUM A0_REGNO 459 460 #define DWARF_FRAME_REGISTERS 20 461 #define DWARF_FRAME_REGNUM(N) m32c_dwarf_frame_regnum (N) 462 #define DBX_REGISTER_NUMBER(N) m32c_dwarf_frame_regnum (N) 463 464 #undef ASM_PREFERRED_EH_DATA_FORMAT 465 /* This is the same as the default in practice, except that by making 466 it explicit we tell binutils what size pointers to use. */ 467 #define ASM_PREFERRED_EH_DATA_FORMAT(CODE,GLOBAL) \ 468 (TARGET_A16 ? DW_EH_PE_udata2 : DW_EH_PE_udata4) 469 470 /* Eliminating Frame Pointer and Arg Pointer */ 471 472 #define ELIMINABLE_REGS \ 473 {{AP_REGNO, SP_REGNO}, \ 474 {AP_REGNO, FB_REGNO}, \ 475 {FB_REGNO, SP_REGNO}} 476 477 #define INITIAL_ELIMINATION_OFFSET(FROM,TO,VAR) \ 478 (VAR) = m32c_initial_elimination_offset(FROM,TO) 479 480 /* Passing Function Arguments on the Stack */ 481 482 #define PUSH_ARGS 1 483 #define PUSH_ROUNDING(N) m32c_push_rounding (N) 484 #define CALL_POPS_ARGS(C) 0 485 486 /* Passing Arguments in Registers */ 487 488 typedef struct m32c_cumulative_args 489 { 490 /* For address of return value buffer (structures are returned by 491 passing the address of a buffer as an invisible first argument. 492 This identifies it). If set, the current parameter will be put 493 on the stack, regardless of type. */ 494 int force_mem; 495 /* First parm is 1, parm 0 is hidden pointer for returning 496 aggregates. */ 497 int parm_num; 498 } m32c_cumulative_args; 499 500 #define CUMULATIVE_ARGS m32c_cumulative_args 501 #define INIT_CUMULATIVE_ARGS(CA,FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) \ 502 m32c_init_cumulative_args (&(CA),FNTYPE,LIBNAME,FNDECL,N_NAMED_ARGS) 503 #define FUNCTION_ARG_REGNO_P(r) m32c_function_arg_regno_p (r) 504 505 /* How Large Values Are Returned */ 506 507 #define DEFAULT_PCC_STRUCT_RETURN 1 508 509 /* Function Entry and Exit */ 510 511 #define EXIT_IGNORE_STACK 0 512 #define EPILOGUE_USES(REGNO) m32c_epilogue_uses(REGNO) 513 #define EH_USES(REGNO) 0 /* FIXME */ 514 515 /* Generating Code for Profiling */ 516 517 #define FUNCTION_PROFILER(FILE,LABELNO) 518 519 /* Implementing the Varargs Macros */ 520 521 /* Trampolines for Nested Functions */ 522 523 #define TRAMPOLINE_SIZE m32c_trampoline_size () 524 #define TRAMPOLINE_ALIGNMENT m32c_trampoline_alignment () 525 526 /* Addressing Modes */ 527 528 #define HAVE_PRE_DECREMENT 1 529 #define HAVE_POST_INCREMENT 1 530 #define MAX_REGS_PER_ADDRESS 1 531 532 /* This is passed to the macros below, so that they can be implemented 533 in m32c.c. */ 534 #ifdef REG_OK_STRICT 535 #define REG_OK_STRICT_V 1 536 #else 537 #define REG_OK_STRICT_V 0 538 #endif 539 540 #define REG_OK_FOR_BASE_P(X) m32c_reg_ok_for_base_p (X, REG_OK_STRICT_V) 541 #define REG_OK_FOR_INDEX_P(X) 0 542 543 /* #define FIND_BASE_TERM(X) when we do unspecs for symrefs */ 544 545 #define LEGITIMIZE_RELOAD_ADDRESS(X,MODE,OPNUM,TYPE,IND_LEVELS,WIN) \ 546 if (m32c_legitimize_reload_address(&(X),MODE,OPNUM,TYPE,IND_LEVELS)) \ 547 goto WIN; 548 549 /* Address spaces. */ 550 #define ADDR_SPACE_FAR 1 551 552 553 /* Condition Code Status */ 554 555 #define REVERSIBLE_CC_MODE(MODE) 1 556 557 /* Dividing the Output into Sections (Texts, Data, ...) */ 558 559 #define TEXT_SECTION_ASM_OP ".text" 560 #define DATA_SECTION_ASM_OP ".data" 561 #define BSS_SECTION_ASM_OP ".bss" 562 563 #define CTOR_LIST_BEGIN 564 #define CTOR_LIST_END 565 #define DTOR_LIST_BEGIN 566 #define DTOR_LIST_END 567 #define CTORS_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array" 568 #define DTORS_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array" 569 #define INIT_ARRAY_SECTION_ASM_OP "\t.section\t.init_array,\"aw\",%init_array" 570 #define FINI_ARRAY_SECTION_ASM_OP "\t.section\t.fini_array,\"aw\",%fini_array" 571 572 /* The Overall Framework of an Assembler File */ 573 574 #define ASM_COMMENT_START ";" 575 #define ASM_APP_ON "" 576 #define ASM_APP_OFF "" 577 578 /* Output and Generation of Labels */ 579 580 #define GLOBAL_ASM_OP "\t.global\t" 581 582 /* Output of Assembler Instructions */ 583 584 #define REGISTER_NAMES { \ 585 "r0", "r2", "r1", "r3", \ 586 "a0", "a1", "sb", "fb", "sp", \ 587 "pc", "flg", "argp", \ 588 "mem0", "mem2", "mem4", "mem6", "mem8", "mem10", "mem12", "mem14", \ 589 } 590 591 #define ADDITIONAL_REGISTER_NAMES { \ 592 {"r0l", 0}, \ 593 {"r1l", 2}, \ 594 {"r0r2", 0}, \ 595 {"r1r3", 2}, \ 596 {"a0a1", 4}, \ 597 {"r0r2r1r3", 0} } 598 599 #undef USER_LABEL_PREFIX 600 #define USER_LABEL_PREFIX "_" 601 602 #define ASM_OUTPUT_REG_PUSH(S,R) m32c_output_reg_push (S, R) 603 #define ASM_OUTPUT_REG_POP(S,R) m32c_output_reg_pop (S, R) 604 605 #define ASM_OUTPUT_ALIGNED_DECL_COMMON(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ 606 m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 1) 607 608 #define ASM_OUTPUT_ALIGNED_DECL_LOCAL(STREAM, DECL, NAME, SIZE, ALIGNMENT) \ 609 m32c_output_aligned_common (STREAM, DECL, NAME, SIZE, ALIGNMENT, 0) 610 611 612 /* Output of Dispatch Tables */ 613 614 #define ASM_OUTPUT_ADDR_VEC_ELT(S,V) \ 615 fprintf (S, "\t.word L%d\n", V) 616 617 /* Assembler Commands for Exception Regions */ 618 619 #define DWARF_CIE_DATA_ALIGNMENT -1 620 621 /* Assembler Commands for Alignment */ 622 623 #define ASM_OUTPUT_ALIGN(STREAM,POWER) \ 624 fprintf (STREAM, "\t.p2align\t%d\n", POWER); 625 626 /* Controlling Debugging Information Format */ 627 628 #define DWARF2_ADDR_SIZE 4 629 630 /* Miscellaneous Parameters */ 631 632 #define HAS_LONG_COND_BRANCH false 633 #define HAS_LONG_UNCOND_BRANCH true 634 #define CASE_VECTOR_MODE SImode 635 #define LOAD_EXTEND_OP(MEM) ZERO_EXTEND 636 637 #define MOVE_MAX 4 638 #define TRULY_NOOP_TRUNCATION(op,ip) 1 639 640 #define STORE_FLAG_VALUE 1 641 642 /* 16- or 24-bit pointers */ 643 #define Pmode (TARGET_A16 ? HImode : PSImode) 644 #define FUNCTION_MODE QImode 645 646 #define REGISTER_TARGET_PRAGMAS() m32c_register_pragmas() 647 648 #endif 649