1;; Machine Descriptions for R8C/M16C/M32C 2;; Copyright (C) 2005-2018 Free Software Foundation, Inc. 3;; Contributed by Red Hat. 4;; 5;; This file is part of GCC. 6;; 7;; GCC is free software; you can redistribute it and/or modify it 8;; under the terms of the GNU General Public License as published 9;; by the Free Software Foundation; either version 3, or (at your 10;; option) any later version. 11;; 12;; GCC is distributed in the hope that it will be useful, but WITHOUT 13;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 14;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 15;; License for more details. 16;; 17;; You should have received a copy of the GNU General Public License 18;; along with GCC; see the file COPYING3. If not see 19;; <http://www.gnu.org/licenses/>. 20 21;; add, sub 22 23(define_insn "addqi3" 24 [(set (match_operand:QI 0 "mra_or_sp_operand" 25 "=SdRhl,SdRhl,??Rmm,??Rmm, *Raa,*Raa,SdRhl,??Rmm") 26 (plus:QI (match_operand:QI 1 "mra_operand" 27 "%0,0,0,0, 0,0,0,0") 28 (match_operand:QI 2 "mrai_operand" 29 "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,*Raa,*Raa")))] 30 "" 31 "add.b\t%2,%0" 32 [(set_attr "flags" "oszc")] 33 ) 34 35(define_insn "addhi3" 36 [(set (match_operand:HI 0 "m32c_nonimmediate_operand" 37 "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm, Rhi, Raw, Raw, !Rsp") 38 (plus:HI (match_operand:HI 1 "m32c_any_operand" 39 "%0,0,0,0, 0,0, Raw, Rfb, Rfb, 0") 40 (match_operand:HI 2 "m32c_any_operand" 41 "IU2sSdRhi,?Rmm,IU2sSdRhi,?Rmm, IM2,IM2, IS2IU2, I00, IS1, i")))] 42 "" 43 "@ 44 add.w\t%2,%0 45 add.w\t%2,%0 46 add.w\t%2,%0 47 add.w\t%2,%0 48 sub.w\t%m2,%0 49 sub.w\t%m2,%0 50 mova\t%d2[%1],%0 51 stc\t%1,%0 52 mova\t%D2[%1],%0 53 add.w\t%2,%0" 54 [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc,n,n,n,oszc")] 55 ) 56 57(define_insn "addpsi3" 58 [(set (match_operand:PSI 0 "m32c_nonimmediate_operand" "=Rpi,Raa,SdRpi,SdRpi,Rsp*Rmm, Rpi,Rpi") 59 (plus:PSI (match_operand:PSI 1 "m32c_nonimmediate_operand" "0,0,0,0,0, Raa,Rad") 60 (match_operand:PSI 2 "m32c_any_operand" "Is3,IS1,iSdRpi,?Rmm,i, i,IS2")))] 61 "TARGET_A24" 62 "@ 63 add.l:q\t%2,%0 64 addx\t%2,%0 65 add.l\t%2,%0 66 add.l\t%2,%0 67 add.l\t%2,%0 68 mova\t%d2[%1],%0 69 mova\t%D2[%1],%0" 70 [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,n,n")] 71 ) 72 73(define_expand "addsi3" 74 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm") 75 (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0") 76 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))] 77 "TARGET_A24 ||TARGET_A16" 78 "" 79 ) 80 81(define_insn "addsi3_1" 82 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,??Rmm,RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd") 83 (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0,0,0,0,0") 84 (match_operand:SI 2 "mrai_operand" "IU2,IU2,i,?Rmm,i,RsiSd,?Rmm,RsiSd")))] 85 "TARGET_A16" 86 "* 87 88 switch (which_alternative) 89 { 90 case 0: 91 return \"add.w %X2,%h0\;adcf.w %H0\"; 92 case 1: 93 return \"add.w %X2,%h0\;adcf.w %H0\"; 94 case 2: 95 if (GET_CODE (operands[2]) == SYMBOL_REF) 96 { 97 output_asm_insn (\"add.w #%%lo(%d2),%h0\",operands); 98 return \"adc.w #%%hi(%d2),%H0\"; 99 } 100 else 101 { 102 output_asm_insn (\"add.w %X2,%h0\",operands); 103 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16); 104 return \"adc.w %X2,%H0\"; 105 } 106 case 3: 107 return \"add.w %h2,%h0\;adc.w %H2,%H0\"; 108 case 4: 109 output_asm_insn (\"add.w %X2,%h0\",operands); 110 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16); 111 return \"adc.w %X2,%H0\"; 112 case 5: 113 return \"add.w %h2,%h0\;adc.w %H2,%H0\"; 114 case 6: 115 return \"add.w %h2,%h0\;adc.w %H2,%H0\"; 116 case 7: 117 return \"add.w %h2,%h0\;adc.w %H2,%H0\"; 118 default: 119 gcc_unreachable (); 120 }" 121 [(set_attr "flags" "x,x,x,x,x,x,x,x")] 122) 123 124(define_insn "addsi3_2" 125 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm") 126 (plus:SI (match_operand:SI 1 "mra_operand" "%0,0,0,0") 127 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))] 128 "TARGET_A24" 129 "add.l\t%2,%0" 130 [(set_attr "flags" "oszc")] 131) 132 133(define_insn "subqi3" 134 [(set (match_operand:QI 0 "mra_or_sp_operand" 135 "=SdRhl,SdRhl,??Rmm,??Rmm, Raa,Raa,SdRhl,??Rmm, *Rsp") 136 (minus:QI (match_operand:QI 1 "mra_operand" 137 "0,0,0,0, 0,0,0,0, 0") 138 (match_operand:QI 2 "mrai_operand" 139 "iSdRhl,?Rmm,iSdRhl,?Rmm, iSdRhl,?Rmm,Raa,Raa, i")))] 140 "" 141 "sub.b\t%2,%0" 142 [(set_attr "flags" "oszc")] 143 ) 144 145(define_insn "subhi3" 146 [(set (match_operand:HI 0 "mra_operand" 147 "=SdRhi,SdRhi,??Rmm,??Rmm, SdRhi,??Rmm") 148 (minus:HI (match_operand:HI 1 "mras_operand" 149 "0,0,0,0, 0,0") 150 (match_operand:HI 2 "mrai_operand" 151 "IU2SdRhi,?Rmm,IU2SdRhi,?Rmm, IM2,IM2")))] 152 "" 153 "@ 154 sub.w\t%2,%0 155 sub.w\t%2,%0 156 sub.w\t%2,%0 157 sub.w\t%2,%0 158 add.w\t%m2,%0 159 add.w\t%m2,%0" 160 [(set_attr "flags" "oszc,oszc,oszc,oszc,oszc,oszc")] 161 ) 162 163(define_insn "subpsi3" 164 [(set (match_operand:PSI 0 "mra_operand" "=RpiSd,RpiSd,??Rmm,??Rmm") 165 (minus:PSI (match_operand:PSI 1 "mra_operand" "0,0,0,0") 166 (match_operand:PSI 2 "mrai_operand" "iRpiSd,?Rmm,iRpiSd,?Rmm")))] 167 "TARGET_A24" 168 "sub.%&\t%2,%0" 169 [(set_attr "flags" "oszc")] 170 ) 171 172(define_expand "subsi3" 173 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm") 174 (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0") 175 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))] 176 "TARGET_A24 ||TARGET_A16" 177 "" 178) 179 180(define_insn "subsi3_1" 181 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm,??Rmm,RsiSd") 182 (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0,0,0") 183 (match_operand:SI 2 "mrai_operand" "i,?Rmm,i,RsiSd,?Rmm,RsiSd")))] 184 "TARGET_A16" 185 "* 186 switch (which_alternative) 187 { 188 case 0: 189 output_asm_insn (\"sub.w %X2,%h0\",operands); 190 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16); 191 return \"sbb.w %X2,%H0\"; 192 case 1: 193 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\"; 194 case 2: 195 output_asm_insn (\"sub.w %X2,%h0\",operands); 196 operands[2]= GEN_INT (INTVAL (operands[2]) >> 16); 197 return \"sbb.w %X2,%H0\"; 198 case 3: 199 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\"; 200 case 4: 201 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\"; 202 case 5: 203 return \"sub.w %h2,%h0\;sbb.w %H2,%H0\"; 204 default: 205 gcc_unreachable (); 206 }" 207 [(set_attr "flags" "x,x,x,x,x,x")] 208) 209 210(define_insn "subsi3_2" 211 [(set (match_operand:SI 0 "mra_operand" "=RsiSd,RsiSd,??Rmm,??Rmm") 212 (minus:SI (match_operand:SI 1 "mra_operand" "0,0,0,0") 213 (match_operand:SI 2 "mrai_operand" "iRsiSd,?Rmm,iRsiSd,?Rmm")))] 214 "TARGET_A24" 215 "sub.l\t%2,%0" 216 [(set_attr "flags" "oszc,oszc,oszc,oszc")] 217) 218 219(define_insn "negqi2" 220 [(set (match_operand:QI 0 "mra_operand" "=SdRhl,??Rmm") 221 (neg:QI (match_operand:QI 1 "mra_operand" "0,0")))] 222 "" 223 "neg.b\t%0" 224 [(set_attr "flags" "oszc,oszc")] 225 ) 226 227(define_insn "neghi2" 228 [(set (match_operand:HI 0 "mra_operand" "=SdRhi,??Rmm") 229 (neg:HI (match_operand:HI 1 "mra_operand" "0,0")))] 230 "" 231 "neg.w\t%0" 232 [(set_attr "flags" "oszc,oszc")] 233 ) 234 235; We can negate an SImode by operating on the subparts. GCC deals 236; with this itself for larger modes, but not SI. 237(define_insn "negsi2" 238 [(set (match_operand:SI 0 "mra_operand" "=SdR03,??Rmm") 239 (neg:SI (match_operand:SI 1 "mra_operand" "0,0")))] 240 "" 241 "not.w %h0 | not.w %H0 | add.w #1,%h0 | adcf.w %H0" 242 [(set_attr "flags" "x")] 243 ) 244 245(define_insn "absqi2" 246 [(set (match_operand:QI 0 "mra_operand" "=RhlSd,??Rmm") 247 (abs:QI (match_operand:QI 1 "mra_operand" "0,0")))] 248 "" 249 "abs.b\t%0" 250 [(set_attr "flags" "oszc")] 251 ) 252 253(define_insn "abshi2" 254 [(set (match_operand:HI 0 "mra_operand" "=RhiSd,??Rmm") 255 (abs:HI (match_operand:HI 1 "mra_operand" "0,0")))] 256 "" 257 "abs.w\t%0" 258 [(set_attr "flags" "oszc")] 259 ) 260